diff --git a/README.md b/README.md index 45e89858c..eb827f083 100644 --- a/README.md +++ b/README.md @@ -10,7 +10,7 @@ FSP uses an open software ecosystem and provides flexibility in using your prefe ### Current Release -[FSP v4.1.0](https://github.com/renesas/fsp/releases/tag/v4.1.0) +[FSP v4.2.0](https://github.com/renesas/fsp/releases/tag/v4.2.0) ### Supported RA MCU Kits @@ -65,13 +65,13 @@ For a list of software modules packaged with FSP, see [Supported Software](SUPPO - FSP versions of 4.0.0 and later require a minimum e² studio version of 2022-07. - FSP versions of 4.1.0 and later require a minimum e² studio version of 2022-10. -If you have already installed a previous FSP release that included e² studio then you can download the packs separately. These are available for download under the Assets section for each release. There is a zipped version, FSP_Packs_\.zip (for linux or Windows), and an installer version, FSP_Packs_\.exe (for Windows only). +If you have already installed a previous FSP release that included e² studio then you can download the packs separately. These are available for download under the Assets section for each release. There is a zipped version, FSP_Packs_\.zip, that will work on any supported OS. There is also a self-extracting installer version, FSP_Packs_\.exe, that will work on Windows. -For linux, extract the contents of the zip version into the e2 studio installation directory (typically ~/.local/share/renasas/e2_studio/) +When using the zipped version of the packs the zip file should be extracted into the e² studio support area. This directory is typically found under the user's home directory with a path such as `~/.eclipse/com.renesas.platform_2047834950`. The number on the end of the path is unique to each e² studio installation. If you have two e² studio installations then you will have two directories with names of the format `~/.eclipse/com.renesas.platform_`. Please note that e² studio must have been run at least once for this directory to be created. You can find the support area for a particular e² studio installation by clicking `Help >> About e² studio`. In the window that pops up click `Installation Details` and choose the `Support Folders` tab. The e² studio support area path will be shown. #### For new users that are using FSP with e² studio -1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v4.1.0). +1. Download the FSP with e² studio Installer from the Assets section of the [current release](https://github.com/renesas/fsp/releases/tag/v4.2.0). 2. Run the installer. This will install the e² studio tool, FSP packs, GCC toolchain and other tools required to use this software. No additional installations are required. #### If using RA Smart Configurator (RASC) with IAR Embedded Workbench or Keil MDK #### diff --git a/SUPPORTED_SOFTWARE.md b/SUPPORTED_SOFTWARE.md index 525b26932..f687619f2 100644 --- a/SUPPORTED_SOFTWARE.md +++ b/SUPPORTED_SOFTWARE.md @@ -26,6 +26,7 @@ * [Azure RTOS USBX HCDC](https://docs.microsoft.com/en-us/azure/rtos/usbx/) * [Azure RTOS USBX HHID](https://docs.microsoft.com/en-us/azure/rtos/usbx/) * [Azure RTOS USBX HPRN](https://docs.microsoft.com/en-us/azure/rtos/usbx/) + * [Azure RTOS USBX HUVC](https://docs.microsoft.com/en-us/azure/rtos/usbx/) * [Azure RTOS USBX OTG CDC](https://docs.microsoft.com/en-us/azure/rtos/usbx/) * [Azure RTOS USBX OTG HID](https://docs.microsoft.com/en-us/azure/rtos/usbx/) * [Azure RTOS USBX PAUD](https://docs.microsoft.com/en-us/azure/rtos/usbx/) @@ -35,6 +36,7 @@ * [Azure RTOS USBX PPRN](https://docs.microsoft.com/en-us/azure/rtos/usbx/) * [CAN (r_can)](https://renesas.github.io/fsp/group___c_a_n.html) * [CAN FD (r_canfd)](https://renesas.github.io/fsp/group___c_a_n_f_d.html) + * [CAN FD Lite (r_canfdlite)](https://renesas.github.io/fsp/group___c_a_n_f_d.html) * [CEC (r_cec)](https://renesas.github.io/fsp/group___c_e_c.html) * [I2C Communication Device (rm_comms_i2c)](https://renesas.github.io/fsp/group___r_m___c_o_m_m_s___i2_c.html) * [I2C Master (r_iic_b_master)](https://renesas.github.io/fsp/group___i_i_c___m_a_s_t_e_r.html) @@ -308,11 +310,12 @@ * [AWS Secure Sockets Common (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) * [AWS Secure Sockets TLS Support (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) * [AWS Secure Sockets on FreeRTOS Plus TCP (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) - * [AWS Secure Sockets on WiFi (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) + * [AWS Secure Sockets on WiFi (No Longer Supported)](https://renesas.github.io/fsp/) * [AWS Silex WiFi Sockets Wrapper (rm_aws_sockets_wrapper_silex)](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html) * [AWS TCP Sockets Wrapper](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html) * [AWS Transport Interface on Secure Sockets (No Longer Supported)](https://renesas.github.io/fsp/_f_r_e_e_r_t_o_s__m_i_g_r_a_t_i_o_n.html) * [AWS WiFi Common](https://docs.aws.amazon.com/freertos/latest/userguide/freertos-wifi.html) + * [AWS da16200 WiFi Sockets Wrapper (rm_aws_sockets_wrapper_da16200)](https://docs.aws.amazon.com/embedded-csdk/latest/lib-ref/libraries/standard/coreMQTT/docs/doxygen/output/html/mqtt_transport_interface.html) * [Azure EWF Allocator on ThreadX](https://azure.github.io/embedded-wireless-framework/html/index.html) * [Azure EWF Interface on r_uart](https://azure.github.io/embedded-wireless-framework/html/index.html) * [Azure EWF NetX Duo Middleware](https://azure.github.io/embedded-wireless-framework/html/index.html) @@ -339,6 +342,7 @@ * [NetX Duo WiFi Driver (rm_netxduo_wifi)](https://docs.microsoft.com/en-us/azure/rtos/netx-duo/chapter5) * [RYZ012 SPP Driver Layer](https://renesas.github.io/fsp/group___b_l_e___a_b_s___s_p_p.html) * [WiFi Onchip Silex Driver using r_sci_uart (rm_wifi_onchip_silex)](https://renesas.github.io/fsp/group___w_i_f_i___o_n_c_h_i_p___s_i_l_e_x.html) + * [WiFi Onchip da16200 Driver using r_sci_uart (rm_wifi_onchip_da16200)](https://renesas.github.io/fsp/group___w_i_f_i___o_n_c_h_i_p___s_i_l_e_x.html) * Security * [Azure RTOS NetX Crypto HW Acceleration (rm_netx_secure_crypto)](https://renesas.github.io/fsp/group___r_m___n_e_t_x___s_e_c_u_r_e___c_r_y_p_t_o.html) * [Azure RTOS NetX Crypto Software Only](https://renesas.github.io/fsp/group___r_m___n_e_t_x___s_e_c_u_r_e___c_r_y_p_t_o.html) @@ -350,6 +354,7 @@ * [MCUboot TinyCrypt (S/W Only)](https://github.com/01org/tinycrypt/blob/master/documentation/tinycrypt.rst) * [Mbed Crypto HW Acceleration (rm_psa_crypto)](https://renesas.github.io/fsp/group___r_m___p_s_a___c_r_y_p_t_o.html) * [MbedTLS FSP Port (rm_mbedtls)](https://www.trustedfirmware.org/projects/mbed-tls/) + * [RSIP Compatibility Mode](https://renesas.github.io/fsp/) * [SCE Compatibility Mode](https://renesas.github.io/fsp/) * [SCE5](https://renesas.github.io/fsp/) * [SCE5B](https://renesas.github.io/fsp/) diff --git a/ra/aws/FreeRTOS/FreeRTOS-Plus/Source/Utilities/mbedtls_freertos/mbedtls_bio_freertos_cellular.c b/ra/aws/FreeRTOS/FreeRTOS-Plus/Source/Utilities/mbedtls_freertos/mbedtls_bio_freertos_cellular.c new file mode 100644 index 000000000..7fc83eed5 --- /dev/null +++ b/ra/aws/FreeRTOS/FreeRTOS-Plus/Source/Utilities/mbedtls_freertos/mbedtls_bio_freertos_cellular.c @@ -0,0 +1,97 @@ +/* + * FreeRTOS V202112.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +/** + * @file mbedtls_bio_freertos_cellular.c + * @brief Implements mbed TLS platform send/receive functions for cellular. + */ + +/* FreeRTOS includes. */ +#include "FreeRTOS.h" + +/* Sockets wrapper includes. */ +#include "sockets_wrapper.h" + +/* mbed TLS includes. */ +#include "threading_alt.h" +#include "mbedtls/entropy.h" +#include "mbedtls/ssl.h" + +/*-----------------------------------------------------------*/ + +/** + * @brief Sends data over cellular sockets. + * + * @param[in] ctx The network context containing the socket handle. + * @param[in] buf Buffer containing the bytes to send. + * @param[in] len Number of bytes to send from the buffer. + * + * @return Number of bytes sent on success; else a negative value. + */ +int mbedtls_platform_send( void * ctx, + const unsigned char * buf, + size_t len ) +{ + configASSERT( ctx != NULL ); + configASSERT( buf != NULL ); + + return Sockets_Send( ( Socket_t ) ctx, buf, len ); +} + +/*-----------------------------------------------------------*/ + +/** + * @brief Receives data from cellular socket. + * + * @param[in] ctx The network context containing the socket handle. + * @param[out] buf Buffer to receive bytes into. + * @param[in] len Number of bytes to receive from the network. + * + * @return Number of bytes received if successful; Negative value on error. + */ +int mbedtls_platform_recv( void * ctx, + unsigned char * buf, + size_t len ) +{ + int recvStatus = 0; + int returnStatus = -1; + + configASSERT( ctx != NULL ); + configASSERT( buf != NULL ); + + recvStatus = Sockets_Recv( ( Socket_t ) ctx, buf, len ); + + if( recvStatus < 0 ) + { + returnStatus = MBEDTLS_ERR_SSL_INTERNAL_ERROR; + } + else + { + returnStatus = recvStatus; + } + + return returnStatus; +} diff --git a/ra/fsp/inc/api/r_ble_api.h b/ra/fsp/inc/api/r_ble_api.h index b6b7b5be9..7a9362b5d 100644 --- a/ra/fsp/inc/api/r_ble_api.h +++ b/ra/fsp/inc/api/r_ble_api.h @@ -128,6 +128,7 @@ enum RBLE_STATUS_enum BLE_ERR_RSP_TIMEOUT = 0x0011, BLE_ERR_NOT_YET_READY = 0x0012, BLE_ERR_UNSPECIFIED = 0x0013, + BLE_ERR_ALREADY_INITIALIZED = 0x0014, /* HCI Spec Error */ BLE_ERR_HC_UNKNOWN_HCI_CMD = 0x1001, diff --git a/ra/fsp/inc/api/r_cgc_api.h b/ra/fsp/inc/api/r_cgc_api.h index be84eb09f..0637f9401 100644 --- a/ra/fsp/inc/api/r_cgc_api.h +++ b/ra/fsp/inc/api/r_cgc_api.h @@ -138,7 +138,7 @@ typedef struct u_cgc_divider_cfg { union { - uint32_t sckdivcr_w; ///< System clock Division control register + uint32_t sckdivcr_w; ///< System clock Division control register struct { @@ -155,7 +155,7 @@ typedef struct u_cgc_divider_cfg union { - uint8_t sckdivcr2; ///< System clock Division control register 2 + uint8_t sckdivcr2; ///< System clock Division control register 2 struct { diff --git a/ra/fsp/inc/api/r_ioport_api.h b/ra/fsp/inc/api/r_ioport_api.h index 92e1fcc16..b2fcfdfc1 100644 --- a/ra/fsp/inc/api/r_ioport_api.h +++ b/ra/fsp/inc/api/r_ioport_api.h @@ -69,6 +69,12 @@ typedef enum e_ioport_peripheral /** Pin will function as an AGT peripheral pin */ IOPORT_PERIPHERAL_AGT = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGTW = (0x01UL << IOPORT_PRV_PFS_PSEL_OFFSET), + + /** Pin will function as an AGT peripheral pin */ + IOPORT_PERIPHERAL_AGT1 = (0x18UL << IOPORT_PRV_PFS_PSEL_OFFSET), /** Pin will function as a GPT peripheral pin */ IOPORT_PERIPHERAL_GPT0 = (0x02UL << IOPORT_PRV_PFS_PSEL_OFFSET), diff --git a/ra/fsp/inc/api/r_lpm_api.h b/ra/fsp/inc/api/r_lpm_api.h index c3be79576..5fcf1c207 100644 --- a/ra/fsp/inc/api/r_lpm_api.h +++ b/ra/fsp/inc/api/r_lpm_api.h @@ -62,6 +62,7 @@ FSP_HEADER typedef enum e_lpm_mode { LPM_MODE_SLEEP, ///< Sleep mode + LPM_MODE_DEEP_SLEEP, ///< Deep Sleep mode LPM_MODE_STANDBY, ///< Software Standby mode LPM_MODE_STANDBY_SNOOZE, ///< Software Standby mode with Snooze mode enabled LPM_MODE_DEEP, ///< Deep Software Standby mode @@ -148,44 +149,51 @@ typedef enum e_lpm_snooze_dtc LPM_SNOOZE_DTC_ENABLE = 1U, ///< Enable DTC operation } lpm_snooze_dtc_t; -/** Wake from standby mode sources, does not apply to sleep or deep standby modes */ +/** Wake from deep sleep or standby mode sources, does not apply to sleep or deep standby modes */ typedef enum e_lpm_standby_wake_source { - LPM_STANDBY_WAKE_SOURCE_IRQ0 = 0x00000001ULL, ///< IRQ0 - LPM_STANDBY_WAKE_SOURCE_IRQ1 = 0x00000002ULL, ///< IRQ1 - LPM_STANDBY_WAKE_SOURCE_IRQ2 = 0x00000004ULL, ///< IRQ2 - LPM_STANDBY_WAKE_SOURCE_IRQ3 = 0x00000008ULL, ///< IRQ3 - LPM_STANDBY_WAKE_SOURCE_IRQ4 = 0x00000010ULL, ///< IRQ4 - LPM_STANDBY_WAKE_SOURCE_IRQ5 = 0x00000020ULL, ///< IRQ5 - LPM_STANDBY_WAKE_SOURCE_IRQ6 = 0x00000040ULL, ///< IRQ6 - LPM_STANDBY_WAKE_SOURCE_IRQ7 = 0x00000080ULL, ///< IRQ7 - LPM_STANDBY_WAKE_SOURCE_IRQ8 = 0x00000100ULL, ///< IRQ8 - LPM_STANDBY_WAKE_SOURCE_IRQ9 = 0x00000200ULL, ///< IRQ9 - LPM_STANDBY_WAKE_SOURCE_IRQ10 = 0x00000400ULL, ///< IRQ10 - LPM_STANDBY_WAKE_SOURCE_IRQ11 = 0x00000800ULL, ///< IRQ11 - LPM_STANDBY_WAKE_SOURCE_IRQ12 = 0x00001000ULL, ///< IRQ12 - LPM_STANDBY_WAKE_SOURCE_IRQ13 = 0x00002000ULL, ///< IRQ13 - LPM_STANDBY_WAKE_SOURCE_IRQ14 = 0x00004000ULL, ///< IRQ14 - LPM_STANDBY_WAKE_SOURCE_IRQ15 = 0x00008000ULL, ///< IRQ15 - LPM_STANDBY_WAKE_SOURCE_IWDT = 0x00010000ULL, ///< Independent watchdog interrupt - LPM_STANDBY_WAKE_SOURCE_KEY = 0x00020000ULL, ///< Key interrupt - LPM_STANDBY_WAKE_SOURCE_LVD1 = 0x00040000ULL, ///< Low Voltage Detection 1 interrupt - LPM_STANDBY_WAKE_SOURCE_LVD2 = 0x00080000ULL, ///< Low Voltage Detection 2 interrupt - LPM_STANDBY_WAKE_SOURCE_VBATT = 0x00100000ULL, ///< VBATT Monitor interrupt - LPM_STANDBY_WAKE_SOURCE_ACMPHS0 = 0x00400000ULL, ///< Analog Comparator High-speed 0 interrupt - LPM_STANDBY_WAKE_SOURCE_ACMPLP0 = 0x00800000ULL, ///< Analog Comparator Low-speed 0 interrupt - LPM_STANDBY_WAKE_SOURCE_RTCALM = 0x01000000ULL, ///< RTC Alarm interrupt - LPM_STANDBY_WAKE_SOURCE_RTCPRD = 0x02000000ULL, ///< RTC Period interrupt - LPM_STANDBY_WAKE_SOURCE_USBHS = 0x04000000ULL, ///< USB High-speed interrupt - LPM_STANDBY_WAKE_SOURCE_USBFS = 0x08000000ULL, ///< USB Full-speed interrupt - LPM_STANDBY_WAKE_SOURCE_AGT1UD = 0x10000000ULL, ///< AGT1 underflow interrupt - LPM_STANDBY_WAKE_SOURCE_AGT1CA = 0x20000000ULL, ///< AGT1 compare match A interrupt - LPM_STANDBY_WAKE_SOURCE_AGT1CB = 0x40000000ULL, ///< AGT1 compare match B interrupt - LPM_STANDBY_WAKE_SOURCE_IIC0 = 0x80000000ULL, ///< I2C 0 interrupt - LPM_STANDBY_WAKE_SOURCE_AGT3UD = 0x100000000ULL, ///< AGT3 underflow interrupt - LPM_STANDBY_WAKE_SOURCE_AGT3CA = 0x200000000ULL, ///< AGT3 compare match A interrupt - LPM_STANDBY_WAKE_SOURCE_AGT3CB = 0x400000000ULL, ///< AGT3 compare match B interrupt - LPM_STANDBY_WAKE_SOURCE_I3C0 = 0x80000000000ULL ///< I3C0 address match interrupt + LPM_STANDBY_WAKE_SOURCE_IRQ0 = 0x00000001ULL, ///< IRQ0 + LPM_STANDBY_WAKE_SOURCE_IRQ1 = 0x00000002ULL, ///< IRQ1 + LPM_STANDBY_WAKE_SOURCE_IRQ2 = 0x00000004ULL, ///< IRQ2 + LPM_STANDBY_WAKE_SOURCE_IRQ3 = 0x00000008ULL, ///< IRQ3 + LPM_STANDBY_WAKE_SOURCE_IRQ4 = 0x00000010ULL, ///< IRQ4 + LPM_STANDBY_WAKE_SOURCE_IRQ5 = 0x00000020ULL, ///< IRQ5 + LPM_STANDBY_WAKE_SOURCE_IRQ6 = 0x00000040ULL, ///< IRQ6 + LPM_STANDBY_WAKE_SOURCE_IRQ7 = 0x00000080ULL, ///< IRQ7 + LPM_STANDBY_WAKE_SOURCE_IRQ8 = 0x00000100ULL, ///< IRQ8 + LPM_STANDBY_WAKE_SOURCE_IRQ9 = 0x00000200ULL, ///< IRQ9 + LPM_STANDBY_WAKE_SOURCE_IRQ10 = 0x00000400ULL, ///< IRQ10 + LPM_STANDBY_WAKE_SOURCE_IRQ11 = 0x00000800ULL, ///< IRQ11 + LPM_STANDBY_WAKE_SOURCE_IRQ12 = 0x00001000ULL, ///< IRQ12 + LPM_STANDBY_WAKE_SOURCE_IRQ13 = 0x00002000ULL, ///< IRQ13 + LPM_STANDBY_WAKE_SOURCE_IRQ14 = 0x00004000ULL, ///< IRQ14 + LPM_STANDBY_WAKE_SOURCE_IRQ15 = 0x00008000ULL, ///< IRQ15 + LPM_STANDBY_WAKE_SOURCE_IWDT = 0x00010000ULL, ///< Independent watchdog interrupt + LPM_STANDBY_WAKE_SOURCE_KEY = 0x00020000ULL, ///< Key interrupt + LPM_STANDBY_WAKE_SOURCE_LVD1 = 0x00040000ULL, ///< Low Voltage Detection 1 interrupt + LPM_STANDBY_WAKE_SOURCE_LVD2 = 0x00080000ULL, ///< Low Voltage Detection 2 interrupt + LPM_STANDBY_WAKE_SOURCE_VBATT = 0x00100000ULL, ///< VBATT Monitor interrupt + LPM_STANDBY_WAKE_SOURCE_ACMPHS0 = 0x00400000ULL, ///< Analog Comparator High-speed 0 interrupt + LPM_STANDBY_WAKE_SOURCE_ACMPLP0 = 0x00800000ULL, ///< Analog Comparator Low-speed 0 interrupt + LPM_STANDBY_WAKE_SOURCE_RTCALM = 0x01000000ULL, ///< RTC Alarm interrupt + LPM_STANDBY_WAKE_SOURCE_RTCPRD = 0x02000000ULL, ///< RTC Period interrupt + LPM_STANDBY_WAKE_SOURCE_USBHS = 0x04000000ULL, ///< USB High-speed interrupt + LPM_STANDBY_WAKE_SOURCE_USBFS = 0x08000000ULL, ///< USB Full-speed interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1UD = 0x10000000ULL, ///< AGT1 underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1CA = 0x20000000ULL, ///< AGT1 compare match A interrupt + LPM_STANDBY_WAKE_SOURCE_AGT1CB = 0x40000000ULL, ///< AGT1 compare match B interrupt + LPM_STANDBY_WAKE_SOURCE_IIC0 = 0x80000000ULL, ///< I2C 0 interrupt + LPM_STANDBY_WAKE_SOURCE_AGT3UD = 0x100000000ULL, ///< AGT3 underflow interrupt + LPM_STANDBY_WAKE_SOURCE_AGT3CA = 0x200000000ULL, ///< AGT3 compare match A interrupt + LPM_STANDBY_WAKE_SOURCE_AGT3CB = 0x400000000ULL, ///< AGT3 compare match B interrupt + LPM_STANDBY_WAKE_SOURCE_COMPHS0 = 0x800000000ULL, ///< Comparator-HS0 Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP0U = 0x10000000000ULL, ///< ULPT0 Underflow Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP0A = 0x20000000000ULL, ///< ULPT0 Compare Match A Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP0B = 0x40000000000ULL, ///< ULPT0 Compare Match B Interrupt + LPM_STANDBY_WAKE_SOURCE_I3C0 = 0x800000000000ULL, ///< I3C0 address match interrupt + LPM_STANDBY_WAKE_SOURCE_ULP1U = 0x1000000000000ULL, ///< ULPT1 Underflow Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP1A = 0x2000000000000ULL, ///< ULPT1 Compare Match A Interrupt + LPM_STANDBY_WAKE_SOURCE_ULP1B = 0x4000000000000ULL, ///< ULPT1 Compare Match B Interrupt } lpm_standby_wake_source_t; typedef uint64_t lpm_standby_wake_source_bits_t; @@ -226,6 +234,25 @@ typedef enum e_lpm_power_supply * disabled and the low power function in a poweron reset circuit is enabled */ LPM_POWER_SUPPLY_DEEPCUT3 = 3UL, + + /** + * Power to the standby RAM, Low-speed on-chip oscillator, Programmable Voltage Detection Unit 0, + * and USBFS/HS resume detecting unit is supplied in deep software standby mode. + */ + LPM_POWER_SUPPLY_DEEP_STANDBY_MODE1 = 0U, + + /** + * Power to standby RAM, USBFS/HS resume detecting unit, Low-speed on-chip oscillator, and IWDT is + * disabled in deep software standby mode. Power to the Programmable Voltage Detection Unit 0 is + * supplied in deep software standby mode. + */ + LPM_POWER_SUPPLY_DEEP_STANDBY_MODE2 = 1U, + + /** + * Power to standby RAM, Programmable Voltage Detection Unit 0, USBFS/HS resume detecting unit, + * Low-speed on-chip oscillator, and IWDT is disabled in deep software standby mode. + */ + LPM_POWER_SUPPLY_DEEP_STANDBY_MODE3 = 2U, } lpm_power_supply_t; /** Deep Standby Interrupt Edge */ @@ -308,6 +335,11 @@ typedef enum e_lpm_deep_standby_cancel_source LPM_DEEP_STANDBY_CANCEL_SOURCE_USBFS = 0x01000000U, ///< USBFS Suspend/Resume LPM_DEEP_STANDBY_CANCEL_SOURCE_USBHS = 0x02000000U, ///< USBHS Suspend/Resume LPM_DEEP_STANDBY_CANCEL_SOURCE_AGT1 = 0x04000000U, ///< AGT1 Underflow + LPM_DEEP_STANDBY_CANCEL_SOURCE_AGT3 = 0x08000000U, ///< AGT3 Underflow + LPM_DEEP_STANDBY_CANCEL_SOURCE_ULPT0 = 0x04000000U, ///< ULPT0 Overflow + LPM_DEEP_STANDBY_CANCEL_SOURCE_ULPT1 = 0x08000000U, ///< ULPT1 Overflow + LPM_DEEP_STANDBY_CANCEL_SOURCE_IWDT = 0x20000000U, ///< IWDT Underflow + LPM_DEEP_STANDBY_CANCEL_SOURCE_VBATT = 0x80000000U, ///< VBATT Tamper Detection } lpm_deep_standby_cancel_source_t; typedef uint32_t lpm_deep_standby_cancel_source_bits_t; @@ -332,15 +364,53 @@ typedef enum e_lpm_output_port_enable LPM_OUTPUT_PORT_ENABLE_RETAIN = 1U, } lpm_output_port_enable_t; +/** Configure the behavior of an oscillator's LDO in standby mode. */ +typedef enum e_lpm_ldo_standby_operation +{ + /** The LDO is disabled in standby mode. */ + LPM_LDO_STANDBY_OPERATION_DISABLED, + + /** The LDO state is retained during standby mode. */ + LPM_LDO_STANDBY_OPERATION_RETAINED, +} lpm_ldo_standby_operation_t; + +#if BSP_FEATURE_LPM_HAS_PDRAMSCR || BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP +/** RAM Retention Configuration for deep sleep and standby modes. */ +typedef struct s_lpm_ram_retention +{ +#if BSP_FEATURE_LPM_HAS_PDRAMSCR + /** Configure RAM retention in software standby mode. */ + uint16_t ram_retention; + + /** Enable or disable TCM retention in deep sleep and software standby modes. */ + bool tcm_retention; +#endif +#if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + /** Enable Standby RAM retention in software standby and deep software standby modes. */ + bool standby_ram_retention; +#endif +} lpm_ram_retention_t; +#endif + +/** Configure LDO operation in standby mode. */ +typedef struct lpm_ldo_standby_cfg_s +{ + lpm_ldo_standby_operation_t pll1_ldo; ///< Configure the state of PLL1 LDO in standby mode. + lpm_ldo_standby_operation_t pll2_ldo; ///< Configure the state of PLL2 LDO in standby mode. + lpm_ldo_standby_operation_t hoco_ldo; ///< Configure the state of HOCO LDO in standby mode. +} lpm_ldo_standby_cfg_t; + /** User configuration structure, used in open function */ typedef struct st_lpm_cfg { /** Low Power Mode */ lpm_mode_t low_power_mode; - /** Bitwise list of sources to wake from standby */ + /** Bitwise list of sources to wake from deep sleep and standby mode */ lpm_standby_wake_source_bits_t standby_wake_sources; +#if BSP_FEATURE_LPM_HAS_SNOOZE + /** Snooze request source */ lpm_snooze_request_t snooze_request_source; @@ -349,6 +419,7 @@ typedef struct st_lpm_cfg /** List of snooze cancel sources */ lpm_snooze_cancel_t snooze_cancel_sources; +#endif /** State of DTC in snooze mode, enabled or disabled */ lpm_snooze_dtc_t dtc_state_in_snooze; @@ -372,6 +443,18 @@ typedef struct st_lpm_cfg lpm_deep_standby_cancel_edge_bits_t deep_standby_cancel_edge; #endif +#if BSP_FEATURE_LPM_HAS_PDRAMSCR || BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + + /** RAM retention configuration for deep sleep and standby modes. */ + lpm_ram_retention_t ram_retention_cfg; +#endif + +#if BSP_FEATURE_LPM_HAS_LDO_CONTROL + + /** Configure LDOs that are disabled in standby mode. */ + lpm_ldo_standby_cfg_t ldo_standby_cfg; +#endif + /** Placeholder for extension. */ void const * p_extend; } lpm_cfg_t; diff --git a/ra/fsp/inc/api/r_sce_key_injection_api.h b/ra/fsp/inc/api/r_sce_key_injection_api.h index 0c015f29c..c2d943780 100644 --- a/ra/fsp/inc/api/r_sce_key_injection_api.h +++ b/ra/fsp/inc/api/r_sce_key_injection_api.h @@ -55,18 +55,30 @@ FSP_HEADER /* For RSA operation. */ #define R_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE (256U) +#define R_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE (348U) +#define R_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE (512U) #define R_SCE_RSA_2048_KEY_E_LENGTH_BYTE_SIZE (4U) +#define R_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE (4U) +#define R_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE (4U) #define R_SCE_RSA_2048_KEY_D_LENGTH_BYTE_SIZE (256U) #define R_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE (12U) #define R_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (4U) +#define R_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (4U) +#define R_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (4U) #define R_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (68U) +#define R_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (4U) +#define R_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (5U) #define R_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (4U) +#define R_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (4U) +#define R_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (4U) #define R_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) +#define R_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (196U) +#define R_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (260U) /* For ECC operation. */ #define R_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO_WORD_SIZE (4U) -#define R_SCE_ECC_KEY_LENGTH_BYTE_SIZE (64U) -#define R_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO_WORD_SIZE (16U) +#define R_SCE_ECC_KEY_LENGTH_BYTE_SIZE (96U) +#define R_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO_WORD_SIZE (20U) /********************************************************************************************************************** * Typedef definitions @@ -106,6 +118,34 @@ typedef struct sce_rsa2048_public_wrapped_key } value; } sce_rsa2048_public_wrapped_key_t; +/** RSA 3072bit public wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa3072_public_wrapped_key +{ + uint32_t type; ///< Key type + struct + { + uint32_t key_management_info1[R_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[R_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[R_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[R_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[R_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa3072_public_wrapped_key_t; + +/** RSA 4096bit public wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa4096_public_wrapped_key +{ + uint32_t type; ///< Key type + struct + { + uint32_t key_management_info1[R_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[R_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[R_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[R_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[R_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa4096_public_wrapped_key_t; + /** RSA 2048bit private wrapped key data structure. DO NOT MODIFY. */ typedef struct sce_rsa2048_private_wrapped_key { @@ -118,7 +158,31 @@ typedef struct sce_rsa2048_private_wrapped_key } value; } sce_rsa2048_private_wrapped_key_t; -/** ECC 256 public wrapped key data structure */ +/** RSA 3072bit private wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa3072_private_wrapped_key +{ + uint32_t type; ///< key type + struct + { + uint32_t key_management_info1[R_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[R_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[R_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa3072_private_wrapped_key_t; + +/** RSA 4096bit private wrapped key data structure. DO NOT MODIFY. */ +typedef struct sce_rsa4096_private_wrapped_key +{ + uint32_t type; ///< key type + struct + { + uint32_t key_management_info1[R_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[R_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[R_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa4096_private_wrapped_key_t; + +/** ECC 256/384 public wrapped key data structure */ typedef struct sce_ecc_public_wrapped_key { uint32_t type; @@ -130,7 +194,7 @@ typedef struct sce_ecc_public_wrapped_key } value; } sce_ecc_public_wrapped_key_t; -/** ECC 256 private wrapped key data structure */ +/** ECC 256/384 private wrapped key data structure */ typedef struct sce_ecc_private_wrapped_key { uint32_t type; @@ -230,6 +294,40 @@ typedef struct st_sce_key_injection_api const uint8_t * const encrypted_key, sce_rsa2048_public_wrapped_key_t * const wrapped_key); + /** This API outputs 3072-bit RSA public wrapped key. + * @par Implemented as + * - @ref R_SCE_RSA3072_InitialPublicKeyWrap "R_SCE_RSA3072_InitialPublicKeyWrap()" + * + * @param[in] key_type Key type whether encrypted_key or plain key + * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encrypted and MAC appended + * @param[in,out] wrapped_key 3072-bit RSA wrapped key + */ + fsp_err_t (* RSA3072_InitialPublicKeyWrap)(const uint8_t * const key_type, + const uint8_t * const + wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_rsa3072_public_wrapped_key_t * const wrapped_key); + + /** This API outputs 4096-bit RSA public wrapped key. + * @par Implemented as + * - @ref R_SCE_RSA4096_InitialPublicKeyWrap "R_SCE_RSA4096_InitialPublicKeyWrap()" + * + * @param[in] key_type Key type whether encrypted_key or plain key + * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encrypted and MAC appended + * @param[in,out] wrapped_key 4096-bit RSA wrapped key + */ + fsp_err_t (* RSA4096_InitialPublicKeyWrap)(const uint8_t * const key_type, + const uint8_t * const + wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_rsa4096_public_wrapped_key_t * const wrapped_key); + /** This API outputs 2048-bit RSA private wrapped key. * @par Implemented as * - @ref R_SCE_RSA2048_InitialPrivateKeyWrap "R_SCE_RSA2048_InitialPrivateKeyWrap()" @@ -247,7 +345,7 @@ typedef struct st_sce_key_injection_api const uint8_t * const encrypted_key, sce_rsa2048_private_wrapped_key_t * const wrapped_key); - /** This API outputs 2048-bit RSA public wrapped key. +/** This API outputs 2048-bit RSA public wrapped key. * @par Implemented as * - @ref R_SCE_RSA2048_EncryptedPublicKeyWrap "R_SCE_RSA2048_EncryptedPublicKeyWrap()" * @@ -292,6 +390,40 @@ typedef struct st_sce_key_injection_api const uint8_t * const encrypted_key, sce_ecc_public_wrapped_key_t * const wrapped_key); + /** This API outputs 256-bit ECC public wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp256k1_InitialPublicKeyWrap "R_SCE_ECC_secp256k1_InitialPublicKeyWrap()" + * + * @param[in] key_type Key type whether encrypted_key or plain key + * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encrypted and MAC appended + * @param[in,out] wrapped_key 256-bit ECC wrapped key + */ + fsp_err_t (* ECC_secp256k1_InitialPublicKeyWrap)(const uint8_t * const key_type, + const uint8_t * const + wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_ecc_public_wrapped_key_t * const wrapped_key); + + /** This API outputs 384-bit ECC public wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp384r1_InitialPublicKeyWrap "R_SCE_ECC_secp384r1_InitialPublicKeyWrap()" + * + * @param[in] key_type Key type whether encrypted_key or plain key + * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encrypted and MAC appended + * @param[in,out] wrapped_key 384-bit ECC wrapped key + */ + fsp_err_t (* ECC_secp384r1_InitialPublicKeyWrap)(const uint8_t * const key_type, + const uint8_t * const + wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_ecc_public_wrapped_key_t * const wrapped_key); + /** This API outputs 256-bit ECC private wrapped key. * @par Implemented as * - @ref R_SCE_ECC_secp256r1_InitialPrivateKeyWrap "R_SCE_ECC_secp256r1_InitialPrivateKeyWrap()" @@ -309,6 +441,40 @@ typedef struct st_sce_key_injection_api const uint8_t * const encrypted_key, sce_ecc_private_wrapped_key_t * const wrapped_key); + /** This API outputs 256-bit ECC private wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp256k1_InitialPrivateKeyWrap "R_SCE_ECC_secp256k1_InitialPrivateKeyWrap()" + * + * @param[in] key_type Key type whether encrypted_key or plain key + * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encrypted and MAC appended + * @param[in,out] wrapped_key 256-bit ECC wrapped key + */ + fsp_err_t (* ECC_secp256k1_InitialPrivateKeyWrap)(const uint8_t * const key_type, + const uint8_t * const + wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_ecc_private_wrapped_key_t * const wrapped_key); + + /** This API outputs 384-bit ECC private wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp384r1_InitialPrivateKeyWrap "R_SCE_ECC_secp384r1_InitialPrivateKeyWrap()" + * + * @param[in] key_type Key type whether encrypted_key or plain key + * @param[in] wrapped_user_factory_programming_key Provisioning key wrapped by the DLM server + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encrypted and MAC appended + * @param[in,out] wrapped_key 384-bit ECC wrapped key + */ + fsp_err_t (* ECC_secp384r1_InitialPrivateKeyWrap)(const uint8_t * const key_type, + const uint8_t * const + wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_ecc_private_wrapped_key_t * const wrapped_key); + /** This API outputs 256-bit ECC public wrapped key. * @par Implemented as * - @ref R_SCE_ECC_secp256r1_EncryptedPublicKeyWrap "R_SCE_ECC_secp256r1_EncryptedPublicKeyWrap()" @@ -323,6 +489,34 @@ typedef struct st_sce_key_injection_api const sce_key_update_key_t * const key_update_key, sce_ecc_public_wrapped_key_t * const wrapped_key); + /** This API outputs 256-bit ECC public wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp256k1_EncryptedPublicKeyWrap "R_SCE_ECC_secp256k1_EncryptedPublicKeyWrap()" + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 256-bit ECC wrapped key + */ + fsp_err_t (* ECC_secp256k1_EncryptedPublicKeyWrap)(const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + const sce_key_update_key_t * const key_update_key, + sce_ecc_public_wrapped_key_t * const wrapped_key); + + /** This API outputs 384-bit ECC public wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap "R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap()" + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 384-bit ECC wrapped key + */ + fsp_err_t (* ECC_secp384r1_EncryptedPublicKeyWrap)(const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + const sce_key_update_key_t * const key_update_key, + sce_ecc_public_wrapped_key_t * const wrapped_key); + /** This API outputs 256-bit ECC private wrapped key. * @par Implemented as * - @ref R_SCE_ECC_secp256r1_EncryptedPrivateKeyWrap "R_SCE_ECC_secp256r1_EncryptedPrivateKeyWrap()" @@ -336,6 +530,36 @@ typedef struct st_sce_key_injection_api const uint8_t * const encrypted_key, const sce_key_update_key_t * const key_update_key, sce_ecc_private_wrapped_key_t * const wrapped_key); + + /** This API outputs 256-bit ECC private wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp256k1_EncryptedPrivateKeyWrap "R_SCE_ECC_secp256k1_EncryptedPrivateKeyWrap()" + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 256-bit ECC wrapped key + */ + fsp_err_t (* ECC_secp256k1_EncryptedPrivateKeyWrap)(const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + const sce_key_update_key_t * const key_update_key, + sce_ecc_private_wrapped_key_t * const wrapped_key); + + /** This API outputs 384-bit ECC private wrapped key. + * @par Implemented as + * - @ref R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap "R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap()" + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 384-bit ECC wrapped key + */ + fsp_err_t (* ECC_secp384r1_EncryptedPrivateKeyWrap)(const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + const sce_key_update_key_t * const key_update_key, + sce_ecc_private_wrapped_key_t * const wrapped_key); + + } sce_key_injection_api_t; /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ diff --git a/ra/fsp/inc/api/r_usb_basic_api.h b/ra/fsp/inc/api/r_usb_basic_api.h index deb0f7418..7b71b463e 100644 --- a/ra/fsp/inc/api/r_usb_basic_api.h +++ b/ra/fsp/inc/api/r_usb_basic_api.h @@ -157,7 +157,7 @@ FSP_HEADER #define USB_IFCLS_CDCD (0x0AU) ///< CDC-Data Class #define USB_IFCLS_CHIP (0x0BU) ///< Chip/Smart Card Class #define USB_IFCLS_CNT (0x0CU) ///< Content-Security Class -#define USB_IFCLS_VID (0x0DU) ///< Video Class +#define USB_IFCLS_VID (0x0EU) ///< Video Class #define USB_IFCLS_DIAG (0xDCU) ///< Diagnostic Device #define USB_IFCLS_WIRE (0xE0U) ///< Wireless Controller #define USB_IFCLS_APL (0xFEU) ///< Application-Specific @@ -242,6 +242,7 @@ typedef enum e_usb_class USB_CLASS_HMSC, ///< HMSC Class USB_CLASS_PMSC, ///< PMSC Class USB_CLASS_HPRN, ///< HPRN Class + USB_CLASS_HUVC, ///< HUVC Class USB_CLASS_REQUEST, ///< USB Class Request USB_CLASS_END ///< USB Class End Code } usb_class_t; diff --git a/ra/fsp/inc/api/rm_ble_abs_api.h b/ra/fsp/inc/api/rm_ble_abs_api.h index 56a3735f1..fe0bbd2ab 100644 --- a/ra/fsp/inc/api/rm_ble_abs_api.h +++ b/ra/fsp/inc/api/rm_ble_abs_api.h @@ -43,8 +43,10 @@ #include "bsp_api.h" #include "r_ble_api.h" #ifndef BLE_CFG_RYZ012_DEVICE - #include "r_flash_api.h" - #include "r_timer_api.h" + #ifndef BLE_CFG_DA14531_DEVICE + #include "r_flash_api.h" + #include "r_timer_api.h" + #endif #else #include "r_uart_api.h" #include "r_spi_api.h" @@ -787,8 +789,10 @@ typedef struct st_ble_abs_cfg uint8_t gatt_client_callback_list_number; ///< The number of GATT Client callback functions. ble_abs_pairing_parameter_t * p_pairing_parameter; ///< Pairing parameters. #ifndef BLE_CFG_RYZ012_DEVICE + #ifndef BLE_CFG_DA14531_DEVICE flash_instance_t const * p_flash_instance; ///< Pointer to flash instance. timer_instance_t const * p_timer_instance; ///< Pointer to timer instance. + #endif #else const uart_instance_t * p_uart_instance; ///< SCI UART instance const spi_instance_t * p_spi_instance; ///< SPI instance diff --git a/ra/fsp/inc/api/rm_ble_mesh_api.h b/ra/fsp/inc/api/rm_ble_mesh_api.h index b28732460..054f4c2eb 100644 --- a/ra/fsp/inc/api/rm_ble_mesh_api.h +++ b/ra/fsp/inc/api/rm_ble_mesh_api.h @@ -802,6 +802,9 @@ typedef struct st_rm_ble_mesh_cfg */ uint32_t maximum_health_server_num; + /** Maximum number of Light Lightness Controller Server Instances. */ + uint32_t maximum_light_lc_server_num; + /** The size of the Replay Protection cache. */ uint32_t replay_cache_size; diff --git a/ra/fsp/inc/fsp_common_api.h b/ra/fsp/inc/fsp_common_api.h index ee0f4dec7..b9f468a0c 100644 --- a/ra/fsp/inc/fsp_common_api.h +++ b/ra/fsp/inc/fsp_common_api.h @@ -297,6 +297,17 @@ typedef enum e_fsp_err FSP_ERR_WIFI_FAILED = 70004, ///< WiFi Failed. FSP_ERR_WIFI_SCAN_COMPLETE = 70005, ///< Wifi scan has completed. FSP_ERR_WIFI_AP_NOT_CONNECTED = 70006, ///< WiFi module is not connected to access point + FSP_ERR_WIFI_UNKNOWN_AT_CMD = 70007, ///< DA16200 Unknown AT command Error + FSP_ERR_WIFI_INSUF_PARAM = 70008, ///< DA16200 Insufficient parameter + FSP_ERR_WIFI_TOO_MANY_PARAMS = 70009, ///< DA16200 Too many parameters + FSP_ERR_WIFI_INV_PARAM_VAL = 70010, ///< DA16200 Wrong parameter value + FSP_ERR_WIFI_NO_RESULT = 70011, ///< DA16200 No result + FSP_ERR_WIFI_RSP_BUF_OVFLW = 70012, ///< DA16200 Response buffer overflow + FSP_ERR_WIFI_FUNC_NOT_CONFIG = 70013, ///< DA16200 Function is not configured + FSP_ERR_WIFI_NVRAM_WR_FAIL = 70014, ///< DA16200 NVRAM write failure + FSP_ERR_WIFI_RET_MEM_WR_FAIL = 70015, ///< DA16200 Retention memory write failure + FSP_ERR_WIFI_UNKNOWN_ERR = 70016, ///< DA16200 unknown error + /* Start of SF_CELLULAR Specific */ FSP_ERR_CELLULAR_CONFIG_FAILED = 80000, ///< Cellular module Configuration failed. diff --git a/ra/fsp/inc/fsp_version.h b/ra/fsp/inc/fsp_version.h index 9da3493b1..5b9bc2295 100644 --- a/ra/fsp/inc/fsp_version.h +++ b/ra/fsp/inc/fsp_version.h @@ -45,7 +45,7 @@ extern "C" { #define FSP_VERSION_MAJOR (4U) /** FSP pack minor version. */ - #define FSP_VERSION_MINOR (1U) + #define FSP_VERSION_MINOR (2U) /** FSP pack patch version. */ #define FSP_VERSION_PATCH (0U) @@ -54,10 +54,10 @@ extern "C" { #define FSP_VERSION_BUILD (0U) /** Public FSP version name. */ - #define FSP_VERSION_STRING ("4.1.0") + #define FSP_VERSION_STRING ("4.2.0") /** Unique FSP version ID. */ - #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 4.1.0") + #define FSP_VERSION_BUILD_STRING ("Built with Renesas Advanced Flexible Software Package version 4.2.0") /********************************************************************************************************************** * Typedef definitions diff --git a/ra/fsp/inc/instances/r_cac.h b/ra/fsp/inc/instances/r_cac.h index 5eca42112..a02c56d84 100644 --- a/ra/fsp/inc/instances/r_cac.h +++ b/ra/fsp/inc/instances/r_cac.h @@ -75,7 +75,6 @@ fsp_err_t R_CAC_Open(cac_ctrl_t * const p_ctrl, cac_cfg_t const * const p_cfg); fsp_err_t R_CAC_StartMeasurement(cac_ctrl_t * const p_ctrl); fsp_err_t R_CAC_StopMeasurement(cac_ctrl_t * const p_ctrl); fsp_err_t R_CAC_Read(cac_ctrl_t * const p_ctrl, uint16_t * const p_counter); -fsp_err_t R_CAC_Reset(cac_ctrl_t * const p_ctrl); fsp_err_t R_CAC_Close(cac_ctrl_t * const p_ctrl); fsp_err_t R_CAC_CallbackSet(cac_ctrl_t * const p_ctrl, void ( * p_callback)(cac_callback_args_t *), diff --git a/ra/fsp/inc/instances/r_canfd.h b/ra/fsp/inc/instances/r_canfd.h index 6eff1375a..f74402808 100644 --- a/ra/fsp/inc/instances/r_canfd.h +++ b/ra/fsp/inc/instances/r_canfd.h @@ -243,6 +243,8 @@ typedef enum e_canfd_frame_option /* CAN Instance Control Block */ typedef struct st_canfd_instance_ctrl { + R_CANFD_Type * p_reg; // Pointer to register base address + /* Parameters to control CAN peripheral device */ can_cfg_t const * p_cfg; // Pointer to the configuration structure uint32_t open; // Open status of channel. diff --git a/ra/fsp/inc/instances/r_ctsu.h b/ra/fsp/inc/instances/r_ctsu.h index 8fbaec6c7..6c5894d98 100644 --- a/ra/fsp/inc/instances/r_ctsu.h +++ b/ra/fsp/inc/instances/r_ctsu.h @@ -271,7 +271,10 @@ typedef struct st_ctsu_instance_ctrl uint16_t num_elements; ///< Number of elements to scan uint16_t wr_index; ///< Word index into ctsuwr register array. uint16_t rd_index; ///< Word index into scan data buffer. - uint8_t * p_tuning_count; ///< Pointer to tuning count of each element. g_ctsu_tuning_count[] is set by Open API. + uint8_t * p_element_complete_flag; ///< Pointer to complete flag of each element. g_ctsu_element_complete_flag[] is set by Open API. +#if (BSP_FEATURE_CTSU_VERSION == 2) + uint8_t * p_frequency_complete_flag; ///< Pointer to complete flag of each frequency. g_ctsu_frequency_complete_flag[] is set by Open API. +#endif int32_t * p_tuning_diff; ///< Pointer to difference from base value of each element. g_ctsu_tuning_diff[] is set by Open API. uint16_t average; ///< CTSU Moving average counter. uint16_t num_moving_average; ///< Copy from config by Open API. diff --git a/ra/fsp/inc/instances/r_sce_key_injection.h b/ra/fsp/inc/instances/r_sce_key_injection.h index 8450fac34..53d5f58b9 100644 --- a/ra/fsp/inc/instances/r_sce_key_injection.h +++ b/ra/fsp/inc/instances/r_sce_key_injection.h @@ -87,12 +87,36 @@ fsp_err_t R_SCE_RSA2048_InitialPublicKeyWrap(const uint8_t * const const uint8_t * const encrypted_key, sce_rsa2048_public_wrapped_key_t * const wrapped_key); +fsp_err_t R_SCE_RSA3072_InitialPublicKeyWrap(const uint8_t * const key_type, + const uint8_t * const wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_rsa3072_public_wrapped_key_t * const wrapped_key); + +fsp_err_t R_SCE_RSA4096_InitialPublicKeyWrap(const uint8_t * const key_type, + const uint8_t * const wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_rsa4096_public_wrapped_key_t * const wrapped_key); + fsp_err_t R_SCE_RSA2048_InitialPrivateKeyWrap(const uint8_t * const key_type, const uint8_t * const wrapped_user_factory_programming_key, const uint8_t * const initial_vector, const uint8_t * const encrypted_key, sce_rsa2048_private_wrapped_key_t * const wrapped_key); +fsp_err_t R_SCE_RSA3072_InitialPrivateKeyWrap(const uint8_t * const key_type, + const uint8_t * const wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_rsa3072_private_wrapped_key_t * const wrapped_key); + +fsp_err_t R_SCE_RSA4096_InitialPrivateKeyWrap(const uint8_t * const key_type, + const uint8_t * const wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_rsa4096_private_wrapped_key_t * const wrapped_key); + fsp_err_t R_SCE_RSA2048_EncryptedPublicKeyWrap(const uint8_t * const initial_vector, const uint8_t * const encrypted_key, const sce_key_update_key_t * const key_update_key, @@ -109,22 +133,66 @@ fsp_err_t R_SCE_ECC_secp256r1_InitialPublicKeyWrap(const uint8_t * const const uint8_t * const encrypted_key, sce_ecc_public_wrapped_key_t * const wrapped_key); +fsp_err_t R_SCE_ECC_secp256k1_InitialPublicKeyWrap(const uint8_t * const key_type, + const uint8_t * const wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_ecc_public_wrapped_key_t * const wrapped_key); + +fsp_err_t R_SCE_ECC_secp384r1_InitialPublicKeyWrap(const uint8_t * const key_type, + const uint8_t * const wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_ecc_public_wrapped_key_t * const wrapped_key); + fsp_err_t R_SCE_ECC_secp256r1_InitialPrivateKeyWrap(const uint8_t * const key_type, const uint8_t * const wrapped_user_factory_programming_key, const uint8_t * const initial_vector, const uint8_t * const encrypted_key, sce_ecc_private_wrapped_key_t * const wrapped_key); +fsp_err_t R_SCE_ECC_secp256k1_InitialPrivateKeyWrap(const uint8_t * const key_type, + const uint8_t * const wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_ecc_private_wrapped_key_t * const wrapped_key); + +fsp_err_t R_SCE_ECC_secp384r1_InitialPrivateKeyWrap(const uint8_t * const key_type, + const uint8_t * const wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_ecc_private_wrapped_key_t * const wrapped_key); + fsp_err_t R_SCE_ECC_secp256r1_EncryptedPublicKeyWrap(const uint8_t * const initial_vector, const uint8_t * const encrypted_key, const sce_key_update_key_t * const key_update_key, sce_ecc_public_wrapped_key_t * const wrapped_key); +fsp_err_t R_SCE_ECC_secp256k1_EncryptedPublicKeyWrap(const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + const sce_key_update_key_t * const key_update_key, + sce_ecc_public_wrapped_key_t * const wrapped_key); + +fsp_err_t R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap(const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + const sce_key_update_key_t * const key_update_key, + sce_ecc_public_wrapped_key_t * const wrapped_key); + fsp_err_t R_SCE_ECC_secp256r1_EncryptedPrivateKeyWrap(const uint8_t * const initial_vector, const uint8_t * const encrypted_key, const sce_key_update_key_t * const key_update_key, sce_ecc_private_wrapped_key_t * const wrapped_key); +fsp_err_t R_SCE_ECC_secp256k1_EncryptedPrivateKeyWrap(const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + const sce_key_update_key_t * const key_update_key, + sce_ecc_private_wrapped_key_t * const wrapped_key); + +fsp_err_t R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap(const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + const sce_key_update_key_t * const key_update_key, + sce_ecc_private_wrapped_key_t * const wrapped_key); + /* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ FSP_FOOTER diff --git a/ra/fsp/inc/instances/r_usb_basic.h b/ra/fsp/inc/instances/r_usb_basic.h index efff11629..503b6c79f 100644 --- a/ra/fsp/inc/instances/r_usb_basic.h +++ b/ra/fsp/inc/instances/r_usb_basic.h @@ -41,7 +41,7 @@ FSP_HEADER * Typedef definitions **********************************************************************************************************************/ -/** ICU private control block. DO NOT MODIFY. Initialization occurs when R_ICU_ExternalIrqOpen is called. */ +/** USB private control block. DO NOT MODIFY. Initialization occurs when R_USB_Open is called. */ typedef usb_event_info_t usb_instance_ctrl_t; diff --git a/ra/fsp/inc/instances/rm_ble_abs.h b/ra/fsp/inc/instances/rm_ble_abs.h index 440316de2..7f7c7a204 100644 --- a/ra/fsp/inc/instances/rm_ble_abs.h +++ b/ra/fsp/inc/instances/rm_ble_abs.h @@ -28,11 +28,15 @@ #include "bsp_api.h" #include "r_ble_cfg.h" -#ifndef BLE_CFG_RYZ012_DEVICE - #include "rm_ble_abs_cfg.h" -#else + +#ifdef BLE_CFG_RYZ012_DEVICE #include "rm_ble_abs_spp_cfg.h" +#elif BLE_CFG_DA14531_DEVICE + #include "rm_ble_abs_gtl_cfg.h" +#else + #include "rm_ble_abs_cfg.h" #endif + #include "rm_ble_abs_api.h" /* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ diff --git a/ra/fsp/inc/instances/rm_mesh_light_lc_srv.h b/ra/fsp/inc/instances/rm_mesh_light_lc_srv.h index 4e76cec42..dc2fb46a7 100644 --- a/ra/fsp/inc/instances/rm_mesh_light_lc_srv.h +++ b/ra/fsp/inc/instances/rm_mesh_light_lc_srv.h @@ -45,6 +45,63 @@ FSP_HEADER * @{ **********************************************************************************************************************/ +/** Light LC light event */ +typedef enum e_rm_ble_mesh_light_lc_srv_event +{ + RM_MESH_LIGHT_LC_SRV_LIGHT_EVENT_OFF = 0x01, ///< Light LC Server Event Off + RM_MESH_LIGHT_LC_SRV_LIGHT_EVENT_STANDBY = 0x02, ///< Light LC Server Event Standby + RM_MESH_LIGHT_LC_SRV_LIGHT_EVENT_FADE_ON = 0x03, ///< Light LC Server Event Fade On + RM_MESH_LIGHT_LC_SRV_LIGHT_EVENT_RUN = 0x04, ///< Light LC Server Event Run + RM_MESH_LIGHT_LC_SRV_LIGHT_EVENT_FADE = 0x05, ///< Light LC Server Event Fade + RM_MESH_LIGHT_LC_SRV_LIGHT_EVENT_PROLONG = 0x06, ///< Light LC Server Event Prolong + RM_MESH_LIGHT_LC_SRV_LIGHT_EVENT_FADE_STANDBY_AUTO = 0x07, ///< Light LC Server Event Standby Auto + RM_MESH_LIGHT_LC_SRV_LIGHT_EVENT_FADE_STANDBY_MANUAL = 0x08, ///< Light LC Server Event Standby Manual +} rm_ble_mesh_light_lc_srv_event_t; + +/** Light LC state */ +typedef enum e_rm_ble_mesh_light_lc_srv_state +{ + RM_MESH_LIGHT_LC_SRV_STATE_OFF = 0x01, ///< Light LC Server State Off + RM_MESH_LIGHT_LC_SRV_STATE_STANDBY = 0x02, ///< Light LC Server State Standby + RM_MESH_LIGHT_LC_SRV_STATE_FADE_ON = 0x04, ///< Light LC Server State Fade On + RM_MESH_LIGHT_LC_SRV_STATE_RUN = 0x08, ///< Light LC Server State Run + RM_MESH_LIGHT_LC_SRV_STATE_FADE = 0x10, ///< Light LC Server State Fade + RM_MESH_LIGHT_LC_SRV_STATE_PROLONG = 0x20, ///< Light LC Server State Prolong + RM_MESH_LIGHT_LC_SRV_STATE_FADE_STANDBY_AUTO = 0x40, ///< Light LC Server State Standby Auto + RM_MESH_LIGHT_LC_SRV_STATE_FADE_STANDBY_MANUAL = 0x80, ///< Light LC Server State Standby Manual +} rm_ble_mesh_light_lc_srv_state_t; + +/** Light LC light state */ +typedef enum e_rm_mesh_light_lc_srv_light_state +{ + RM_MESH_LIGHT_LC_SRV_LIGHT_STATE_OFF = 0, ///< Light state Off + RM_MESH_LIGHT_LC_SRV_LIGHT_STATE_ON = 1 ///< Light state ON +} rm_mesh_light_lc_srv_light_state_t; + +/** + * Light LC Server State Info + */ +typedef struct st_rm_mesh_light_lc_srv_scenario +{ + /** Light LC Server Current Scenario */ + rm_ble_mesh_light_lc_srv_state_t state; + + /** Remaining Time in current scenario */ + uint32_t remaining_time_in_ms; + + /** Light LC Occupancy Mode Value */ + uint8_t occupancy_mode; + + /** Light LC Mode Value */ + uint8_t mode; + + /** Current Light LC ONOFF State */ + rm_mesh_light_lc_srv_light_state_t present_light_state; + + /** Target Light LC ONOFF State */ + rm_mesh_light_lc_srv_light_state_t target_light_state; +} rm_mesh_light_lc_srv_scenario_t; + /** Light LC Mode state */ typedef struct st_rm_mesh_light_lc_srv_mode_info { @@ -108,6 +165,15 @@ typedef struct st_rm_mesh_light_lc_srv_property_info uint16_t property_value_len; } rm_mesh_light_lc_srv_property_info_t; +/** Light LC Property state */ +typedef struct st_rm_mesh_light_lc_srv_extended_callback_args +{ + rm_ble_mesh_access_model_handle_t * p_handle; ///< Access model handle. + rm_ble_mesh_light_lc_srv_event_t event_type; ///< Application events defined for Light LC Server Model. + uint8_t * p_event_data; ///< Event data. + uint16_t event_data_length; ///< Event data length. +} rm_mesh_light_lc_srv_extended_callback_args_t; + /** BLE mesh light lc instance control block. DO NOT INITIALIZE. Initialization occurs when RM_MESH_LIGHT_LC_SRV_Open() is called. */ typedef struct st_rm_mesh_light_lc_srv_instance_ctrl { @@ -136,6 +202,16 @@ fsp_err_t RM_MESH_LIGHT_LC_SRV_Open(rm_ble_mesh_model_server_ctrl_t * const fsp_err_t RM_MESH_LIGHT_LC_SRV_Close(rm_ble_mesh_model_server_ctrl_t * const p_ctrl); fsp_err_t RM_MESH_LIGHT_LC_SRV_StateUpdate(rm_ble_mesh_model_server_ctrl_t * const p_ctrl, rm_ble_mesh_access_server_state_t const * p_state); +fsp_err_t RM_MESH_LIGHT_LC_SRV_SetTimeProperty(rm_ble_mesh_model_server_ctrl_t * const p_ctrl, + rm_ble_mesh_model_server_device_property_t property, + uint32_t time_in_ms); +fsp_err_t RM_MESH_LIGHT_LC_SRV_SetScenario(rm_ble_mesh_model_server_ctrl_t * const p_ctrl, + rm_mesh_light_lc_srv_scenario_t const * const p_scenario); +fsp_err_t RM_MESH_LIGHT_LC_SRV_GetCurrentScenario(rm_ble_mesh_model_server_ctrl_t * const p_ctrl, + rm_mesh_light_lc_srv_scenario_t * const p_scenario); +fsp_err_t RM_MESH_LIGHT_LC_SRV_ReportOccupancy(rm_ble_mesh_model_server_ctrl_t * const p_ctrl); +fsp_err_t RM_MESH_LIGHT_LC_SRV_ReportLightOnOff(rm_ble_mesh_model_server_ctrl_t * const p_ctrl, + rm_mesh_light_lc_srv_light_state_t state); /*******************************************************************************************************************//** * @} (end addgroup RM_MESH_LIGHT_LC_SRV) diff --git a/ra/fsp/inc/instances/rm_wifi_onchip_da16200.h b/ra/fsp/inc/instances/rm_wifi_onchip_da16200.h new file mode 100644 index 000000000..13f783e18 --- /dev/null +++ b/ra/fsp/inc/instances/rm_wifi_onchip_da16200.h @@ -0,0 +1,278 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * @addtogroup WIFI_ONCHIP_DA16200 WIFI_ONCHIP_DA16200 + * @{ + **********************************************************************************************************************/ +#ifndef RM_WIFI_ONCHIP_DA16200_H + #define RM_WIFI_ONCHIP_DA16200_H + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ + +/* Register definitions, common services and error codes. */ + #include + #include + #include + #include "bsp_api.h" + #include "time.h" + + #include "r_ioport_api.h" + #include "r_ioport.h" + #include "r_uart_api.h" + + #include "FreeRTOS.h" + #include "semphr.h" + #include "stream_buffer.h" + #include "rm_wifi_config.h" + #include "rm_wifi_api.h" + #include "rm_wifi_onchip_da16200_cfg.h" + +/** + * @brief Max SSID length + */ + #ifndef wificonfigMAX_SSID_LEN + #define wificonfigMAX_SSID_LEN 32 + #endif + +/** + * @brief Max BSSID length + */ + #ifndef wificonfigMAX_BSSID_LEN + #define wificonfigMAX_BSSID_LEN 6 + #endif + +/** + * @brief Max passphrase length + */ + #ifndef wificonfigMAX_PASSPHRASE_LEN + #define wificonfigMAX_PASSPHRASE_LEN 32 + #endif + + #ifndef rm_wifi_onchip_da16200_uart_callback +void rm_wifi_onchip_da16200_uart_callback(uart_callback_args_t * p_args); + + #endif + +#endif + +/* Common macro for FSP header files. There is also a corresponding FSP_FOOTER macro at the end of this file. */ +FSP_HEADER + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +/* Encryption Type supported by DA16200 module */ +#define WIFI_ONCHIP_DA16200_TKIP_ENC_TYPE (0) +#define WIFI_ONCHIP_DA16200_AES_ENC_TYPE (1) +#define WIFI_ONCHIP_DA16200_TKIP_AES_ENC_TYPE (2) + +#define SOCKETS_IPPROTO_V4_DA16200 (4) + +/*********************************************************************************************************************** + * Typedef definitions + **********************************************************************************************************************/ + +/** DA16200 WiFi module enable/disable for SNTP */ +typedef enum e_wifi_onchip_da16200_sntp_enable +{ + WIFI_ONCHIP_DA16200_SNTP_DISABLE = 0, + WIFI_ONCHIP_DA16200_SNTP_ENABLE = 1 +} wifi_onchip_da16200_sntp_enable_t; + +/** DA16200 Wifi socket status types */ +typedef enum e_da16200_socket_status +{ + WIFI_ONCHIP_DA16200_SOCKET_STATUS_CLOSED = 0, + WIFI_ONCHIP_DA16200_SOCKET_STATUS_SOCKET, + WIFI_ONCHIP_DA16200_SOCKET_STATUS_BOUND, + WIFI_ONCHIP_DA16200_SOCKET_STATUS_LISTEN, + WIFI_ONCHIP_DA16200_SOCKET_STATUS_CONNECTED +} da16200_socket_status_t; + +/** DA16200 socket shutdown channels */ +typedef enum e_da16200_socket_rw +{ + WIFI_ONCHIP_DA16200_SOCKET_READ = 1, + WIFI_ONCHIP_DA16200_SOCKET_WRITE = 2 +} da16200_socket_rw; + +/** DA16200 socket receive state */ +typedef enum e_da16200_recv_state +{ + WIFI_ONCHIP_DA16200_RECV_PREFIX, // + + WIFI_ONCHIP_DA16200_RECV_CMD, // command + WIFI_ONCHIP_DA16200_RECV_SUFFIX, // : + WIFI_ONCHIP_DA16200_RECV_PARAM_CID, // cid parameter + WIFI_ONCHIP_DA16200_RECV_PARAM_IP, // ip parameter + WIFI_ONCHIP_DA16200_RECV_PARAM_PORT, // port parameter + WIFI_ONCHIP_DA16200_RECV_PARAM_LEN, // length parameter + WIFI_ONCHIP_DA16200_RECV_DATA +} da16200_recv_state; + +/** DA16200 WiFi module enable/disable for SNTP Daylight */ +typedef enum e_wifi_onchip_da16200_sntp_daylight_savings_enable +{ + WIFI_ONCHIP_DA16200_SNTP_DAYLIGHT_SAVINGS_DISABLE = 0, + WIFI_ONCHIP_DA16200_SNTP_DAYLIGHT_SAVINGS_ENABLE = 1, +} wifi_onchip_da16200_sntp_daylight_savings_enable_t; + +/** User configuration structure, used in open function */ +typedef struct st_wifi_onchip_cfg +{ + const uint32_t num_uarts; ///< Number of UART interfaces to use + const uint32_t num_sockets; ///< Number of sockets to initialize + const uint8_t * country_code; ///< Country code defined in ISO3166-1 alpha-2 standard + const bsp_io_port_pin_t reset_pin; ///< Reset pin used for module + const uart_instance_t * uart_instances[WIFI_ONCHIP_DA16200_CFG_MAX_NUMBER_UART_PORTS]; ///< SCI UART instances + const uint8_t * sntp_server_ip; ///< The SNTP server IP address string + const int32_t sntp_utc_offset_in_hours; ///< Timezone offset in secs (-43200 - 43200) + void const * p_context; ///< User defined context passed into callback function. + void const * p_extend; ///< Pointer to extended configuration by instance of interface. +} wifi_onchip_da16200_cfg_t; + +/** DA16200 Wifi internal socket instance structure */ +typedef struct +{ + uint8_t remote_ipaddr[4]; ///< Remote IP address + int remote_port; ///< Remote Port + int socket_recv_data_len; ///< Data length of incoming socket data + int socket_type; ///< Socket type (TCP Server | TCP Client | UDP) + uint32_t socket_status; ///< Current socket status + uint32_t socket_recv_error_count; ///< Socket receive error count + uint32_t socket_create_flag; ///< Flag to determine in socket has been created. + uint32_t socket_read_write_flag; ///< flag to determine if read and/or write channels are active. + da16200_recv_state socket_recv_state; ///< Incoming Socket data header information + + StreamBufferHandle_t socket_byteq_hdl; ///< Socket stream buffer handle + StaticStreamBuffer_t socket_byteq_struct; ///< Structure to hold stream buffer info + uint8_t socket_recv_buff[WIFI_ONCHIP_DA16200_CFG_MAX_SOCKET_RX_SIZE]; ///< Socket receive buffer used by byte queue +} da16200_socket_t; + +/** WIFI_ONCHIP_DA16200 private control block. DO NOT MODIFY. */ +typedef struct st_wifi_onchip_da16200_instance_ctrl +{ + wifi_onchip_da16200_cfg_t const * p_wifi_onchip_da16200_cfg; ///< Pointer to initial configurations. + bsp_io_port_pin_t reset_pin; ///< Wifi module reset pin + uint32_t num_uarts; ///< number of UARTS currently used for communication with module + uint32_t num_creatable_sockets; ///< Number of simultaneous sockets supported + uint32_t tx_data_size; ///< Size of the data to send + uint32_t curr_cmd_port; ///< Current UART instance index for AT commands + uint32_t open; ///< Flag to indicate if wifi instance has been initialized + uint8_t is_sntp_enabled; ///< Flag to indicate Enable/Disable of SNTP Client + + uint8_t cmd_rx_queue_buf[WIFI_ONCHIP_DA16200_CFG_CMD_RX_BUF_SIZE]; ///< Command port receive buffer used by byte queue // FreeRTOS + StreamBufferHandle_t socket_byteq_hdl; ///< Socket stream buffer handle + StaticStreamBuffer_t socket_byteq_struct; ///< Structure to hold stream buffer info + + volatile uint32_t curr_socket_index; ///< Currently active socket instance + uint8_t cmd_tx_buff[WIFI_ONCHIP_DA16200_CFG_CMD_TX_BUF_SIZE]; ///< Command send buffer + uint8_t cmd_rx_buff[WIFI_ONCHIP_DA16200_CFG_CMD_RX_BUF_SIZE]; ///< Command receive buffer + uint8_t curr_ipaddr[4]; ///< Current IP address of module + uint8_t curr_subnetmask[4]; ///< Current Subnet Mask of module + uint8_t curr_gateway[4]; ///< Current GAteway of module + + SemaphoreHandle_t tx_sem; ///< Transmit binary semaphore handle + SemaphoreHandle_t rx_sem; ///< Receive binary semaphore handle + + uart_instance_t * uart_instance_objects[WIFI_ONCHIP_DA16200_CFG_MAX_NUMBER_UART_PORTS]; ///< UART instance object + SemaphoreHandle_t uart_tei_sem[WIFI_ONCHIP_DA16200_CFG_MAX_NUMBER_UART_PORTS]; ///< UART transmission end binary semaphore + da16200_socket_t sockets[WIFI_ONCHIP_DA16200_CFG_NUM_CREATEABLE_SOCKETS]; ///< Internal socket instances +} wifi_onchip_da16200_instance_ctrl_t; + +/*******************************************************************************************************************//** + * @} (end addtogroup WIFI_ONCHIP_DA16200) + **********************************************************************************************************************/ + +extern const wifi_onchip_da16200_cfg_t g_wifi_onchip_da16200_cfg; +extern const char * g_wifi_onchip_da16200_uart_cmd_baud; + +/********************************************************************************************************************** + * Public Function Prototypes + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_open(wifi_onchip_da16200_cfg_t const * const p_cfg); +fsp_err_t rm_wifi_onchip_da16200_close(void); +fsp_err_t rm_wifi_onchip_da16200_disconnect(void); +fsp_err_t rm_wifi_onchip_da16200_connected(fsp_err_t * p_status); +fsp_err_t rm_wifi_onchip_da16200_network_info_get(uint32_t * p_ip_addr, uint32_t * p_subnet_mask, uint32_t * p_gateway); +fsp_err_t rm_wifi_onchip_da16200_connect(const char * p_ssid, + WIFISecurity_t security, + const char * p_passphrase, + uint8_t enc_type); +fsp_err_t rm_wifi_onchip_da16200_mac_addr_get(uint8_t * p_macaddr); +fsp_err_t rm_wifi_onchip_da16200_scan(WIFIScanResult_t * p_results, uint32_t maxNetworks); +fsp_err_t rm_wifi_onchip_da16200_ping(uint8_t * p_ip_addr, int count, uint32_t interval_ms); +fsp_err_t rm_wifi_onchip_da16200_ipaddr_get(uint32_t * p_ip_addr); +fsp_err_t rm_wifi_onchip_da16200_dns_query(const char * p_textstring, uint8_t * p_ip_addr); + +/* TCP Socket public function prototypes */ +fsp_err_t rm_wifi_onchip_da16200_avail_socket_get(uint32_t * p_socket_id); +fsp_err_t rm_wifi_onchip_da16200_socket_status_get(uint32_t socket_no, uint32_t * p_socket_status); +fsp_err_t rm_wifi_onchip_da16200_socket_create(uint32_t socket_no, uint32_t type, uint32_t ipversion); +fsp_err_t rm_wifi_onchip_da16200_tcp_connect(uint32_t socket_no, uint32_t ipaddr, uint32_t port); +int32_t rm_wifi_onchip_da16200_send(uint32_t socket_no, const uint8_t * p_data, uint32_t length, uint32_t timeout_ms); +int32_t rm_wifi_onchip_da16200_recv(uint32_t socket_no, uint8_t * p_data, uint32_t length, uint32_t timeout_ms); +fsp_err_t rm_wifi_onchip_da16200_socket_disconnect(uint32_t socket_no); + +#ifndef rm_wifi_onchip_da16200_uart_callback +void rm_wifi_onchip_da16200_uart_callback(uart_callback_args_t * p_args); + +#endif + +/**********************************************************************************************************************************//** + * @addtogroup WIFI_ONCHIP_DA16200 WIFI_ONCHIP_DA16200 + * @{ + *************************************************************************************************************************************/ + +/**********************************************************************************************************************************//** + * Update the SNTP Server IP Address + * + *************************************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_DA16200_SntpServerIpAddressSet(uint8_t * p_server_ip_addr); + +/**********************************************************************************************************************************//** + * Enable or Disable the SNTP Client Service + * + *************************************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_DA16200_SntpEnableSet(wifi_onchip_da16200_sntp_enable_t enable); + +/**********************************************************************************************************************************//** + * Update the SNTP Timezone + * + *************************************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_DA16200_SntpTimeZoneSet(int utc_offset_in_hours, + uint32_t minutes, + wifi_onchip_da16200_sntp_daylight_savings_enable_t daylightSavingsEnable); + +/**********************************************************************************************************************************//** + * Get the current local time based on current timezone in a string format + * + *************************************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_DA16200_LocalTimeGet(uint8_t * p_local_time, uint32_t size_string); + +/* Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ +FSP_FOOTER + +/*******************************************************************************************************************//** + * @} (end addtogroup WIFI_ONCHIP_DA16200) + **********************************************************************************************************************/ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h index 2e05aca06..f4131f022 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2A1AB.h @@ -18,9 +18,6 @@ * @file ./out/R7FA2A1AB.h * @brief CMSIS HeaderFile * @version 1.1 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:56:22 - * from File './out/R7FA2A1AB.svd', */ /** @addtogroup Renesas @@ -792,6 +789,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -3750,12 +3766,19 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for * D/A and A/D synchronous conversions. Set bit [1] to 1 to * select unit 1 as the target synchronous unit for the MCU. * When setting the DAADSCR.DAADST bit to 1 for synchronous @@ -3763,7 +3786,7 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure * advance. Only set the DAADUSR register while the ADCSR.ADST * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit * is set to 0. */ - uint8_t : 1; + uint8_t : 6; } DAADUSR_b; }; __IM uint8_t RESERVED3; @@ -4496,18 +4519,69 @@ typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure uint32_t : 26; } FSTATR2_b; }; - __IM uint32_t RESERVED24[3951]; + __IM uint32_t RESERVED24[95]; + + union + { + __IOM uint32_t FCTLFR; /*!< (@ 0x00000370) Flash Control Flag Register */ + + struct + { + __IOM uint32_t BANKSWP : 3; /*!< [2..0] Bank Swap Setting */ + uint32_t : 29; + } FCTLFR_b; + }; + __IM uint32_t RESERVED25[3855]; __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ - __IM uint32_t RESERVED25[3]; + __IM uint32_t RESERVED26[3]; __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ - __IM uint8_t RESERVED26; - __IM uint16_t RESERVED27; - __IM uint32_t RESERVED28; - __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ - __IM uint8_t RESERVED29; - __IM uint16_t RESERVED30; -} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ + __IM uint8_t RESERVED27; + __IM uint16_t RESERVED28; + + union + { + __IOM uint8_t FLDWAITR; /*!< (@ 0x00003FC4) Memory Wait Cycle Control Register for Data Flash */ + + struct + { + __IOM uint8_t FLDWAIT1 : 1; /*!< [0..0] Memory Wait Cycle Select for Data Flash */ + uint8_t : 7; + } FLDWAITR_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + __IM uint32_t RESERVED33; + + union + { + __IOM uint16_t FBKPGCR; /*!< (@ 0x00003FD0) Flash Bank Program Control Register */ + + struct + { + __IOM uint16_t BKPGEN : 1; /*!< [0..0] Bank Programming Setting Enable */ + uint16_t : 7; + __OM uint16_t FEKEY : 8; /*!< [15..8] Key Code */ + } FBKPGCR_b; + }; + __IM uint16_t RESERVED34; + + union + { + __IOM uint16_t FBKSWCR; /*!< (@ 0x00003FD4) Flash Bank Swap Control Register */ + + struct + { + __IOM uint16_t BKSWUPEN : 1; /*!< [0..0] Bank Swap Update Enable */ + uint16_t : 7; + __OM uint16_t FEKEY : 8; /*!< [15..8] Key Code */ + } FBKSWCR_b; + }; + __IM uint16_t RESERVED35; +} R_FACI_LP_Type; /*!< Size = 16344 (0x3fd8) */ /* =========================================================================================================================== */ /* ================ R_FCACHE ================ */ @@ -6390,7 +6464,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -6421,10 +6496,17 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -6432,7 +6514,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -6884,10 +6967,14 @@ typedef struct /*!< (@ 0x40040000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -9199,24 +9286,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -9278,32 +9393,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -9317,8 +9476,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -9333,7 +9492,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -9363,7 +9522,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -9406,7 +9565,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -9444,7 +9603,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -9456,7 +9615,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -9469,7 +9628,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -9483,8 +9642,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -9518,8 +9677,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -9545,8 +9704,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -9601,7 +9760,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -9629,7 +9788,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -9698,7 +9857,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -9760,8 +9919,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -9979,7 +10138,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -10037,7 +10196,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -10054,7 +10213,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -10124,7 +10283,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -10157,7 +10316,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -10192,7 +10351,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -10235,7 +10394,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -10247,9 +10406,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -10272,8 +10431,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -10285,7 +10444,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -10300,8 +10459,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -10340,7 +10499,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -10354,7 +10513,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -10366,7 +10525,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -10501,9 +10660,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -12265,6 +12424,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -13641,8 +13808,10 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ /* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DAC8 ================ */ @@ -13939,10 +14108,26 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_FACI_LP_FSTATR2_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ #define R_FACI_LP_FSTATR2_ERERR_Pos (0UL) /*!< ERERR (Bit 0) */ #define R_FACI_LP_FSTATR2_ERERR_Msk (0x1UL) /*!< ERERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FCTLFR ========================================================= */ + #define R_FACI_LP_FCTLFR_BANKSWP_Pos (0UL) /*!< BANKSWP (Bit 0) */ + #define R_FACI_LP_FCTLFR_BANKSWP_Msk (0x7UL) /*!< BANKSWP (Bitfield-Mask: 0x07) */ /* ====================================================== FENTRYR_MF4 ====================================================== */ /* ======================================================== FENTRYR ======================================================== */ /* ======================================================== FLWAITR ======================================================== */ +/* ======================================================= FLDWAITR ======================================================== */ + #define R_FACI_LP_FLDWAITR_FLDWAIT1_Pos (0UL) /*!< FLDWAIT1 (Bit 0) */ + #define R_FACI_LP_FLDWAITR_FLDWAIT1_Msk (0x1UL) /*!< FLDWAIT1 (Bitfield-Mask: 0x01) */ /* ========================================================= PFBER ========================================================= */ +/* ======================================================== FBKPGCR ======================================================== */ + #define R_FACI_LP_FBKPGCR_BKPGEN_Pos (0UL) /*!< BKPGEN (Bit 0) */ + #define R_FACI_LP_FBKPGCR_BKPGEN_Msk (0x1UL) /*!< BKPGEN (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FBKPGCR_FEKEY_Pos (8UL) /*!< FEKEY (Bit 8) */ + #define R_FACI_LP_FBKPGCR_FEKEY_Msk (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== FBKSWCR ======================================================== */ + #define R_FACI_LP_FBKSWCR_BKSWUPEN_Pos (0UL) /*!< BKSWUPEN (Bit 0) */ + #define R_FACI_LP_FBKSWCR_BKSWUPEN_Msk (0x1UL) /*!< BKSWUPEN (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FBKSWCR_FEKEY_Pos (8UL) /*!< FEKEY (Bit 8) */ + #define R_FACI_LP_FBKSWCR_FEKEY_Msk (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff) */ /* =========================================================================================================================== */ /* ================ R_FCACHE ================ */ @@ -15013,6 +15198,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -15064,6 +15251,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -15078,6 +15267,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -16722,6 +16919,12 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -16760,6 +16963,20 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -16767,6 +16984,13 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h index 9baeda3a5..43672279d 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E1A9.h @@ -22,9 +22,6 @@ * @file ./out/R7FA2E1A9.h * @brief CMSIS HeaderFile * @version 1.20.01 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:56:35 - * from File './out/R7FA2E1A9.svd', */ /** @addtogroup Renesas Electronics Corporation @@ -699,6 +696,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -3917,18 +3933,69 @@ typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure uint32_t : 26; } FSTATR2_b; }; - __IM uint32_t RESERVED24[3951]; + __IM uint32_t RESERVED24[95]; + + union + { + __IOM uint32_t FCTLFR; /*!< (@ 0x00000370) Flash Control Flag Register */ + + struct + { + __IOM uint32_t BANKSWP : 3; /*!< [2..0] Bank Swap Setting */ + uint32_t : 29; + } FCTLFR_b; + }; + __IM uint32_t RESERVED25[3855]; __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ - __IM uint32_t RESERVED25[3]; + __IM uint32_t RESERVED26[3]; __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ - __IM uint8_t RESERVED26; - __IM uint16_t RESERVED27; - __IM uint32_t RESERVED28; - __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ - __IM uint8_t RESERVED29; - __IM uint16_t RESERVED30; -} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ + __IM uint8_t RESERVED27; + __IM uint16_t RESERVED28; + + union + { + __IOM uint8_t FLDWAITR; /*!< (@ 0x00003FC4) Memory Wait Cycle Control Register for Data Flash */ + + struct + { + __IOM uint8_t FLDWAIT1 : 1; /*!< [0..0] Memory Wait Cycle Select for Data Flash */ + uint8_t : 7; + } FLDWAITR_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + __IM uint32_t RESERVED33; + + union + { + __IOM uint16_t FBKPGCR; /*!< (@ 0x00003FD0) Flash Bank Program Control Register */ + + struct + { + __IOM uint16_t BKPGEN : 1; /*!< [0..0] Bank Programming Setting Enable */ + uint16_t : 7; + __OM uint16_t FEKEY : 8; /*!< [15..8] Key Code */ + } FBKPGCR_b; + }; + __IM uint16_t RESERVED34; + + union + { + __IOM uint16_t FBKSWCR; /*!< (@ 0x00003FD4) Flash Bank Swap Control Register */ + + struct + { + __IOM uint16_t BKSWUPEN : 1; /*!< [0..0] Bank Swap Update Enable */ + uint16_t : 7; + __OM uint16_t FEKEY : 8; /*!< [15..8] Key Code */ + } FBKSWCR_b; + }; + __IM uint16_t RESERVED35; +} R_FACI_LP_Type; /*!< Size = 16344 (0x3fd8) */ /* =========================================================================================================================== */ /* ================ R_CTSUTRIM ================ */ @@ -5754,7 +5821,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -5785,10 +5853,17 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -5796,7 +5871,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -6128,10 +6204,14 @@ typedef struct /*!< (@ 0x40040000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -8274,24 +8354,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -8353,32 +8461,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -8392,8 +8544,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -8408,7 +8560,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -8438,7 +8590,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -8481,7 +8633,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -8519,7 +8671,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -8531,7 +8683,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -8544,7 +8696,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -8558,8 +8710,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -8593,8 +8745,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -8620,8 +8772,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -8676,7 +8828,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -8704,7 +8856,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -8773,7 +8925,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -8835,8 +8987,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -9054,7 +9206,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -9112,7 +9264,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -9129,7 +9281,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -9199,7 +9351,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -9232,7 +9384,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -9267,7 +9419,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -9310,7 +9462,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -9322,9 +9474,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -9347,8 +9499,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -9360,7 +9512,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -9375,8 +9527,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -9415,7 +9567,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -9429,7 +9581,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -9441,7 +9593,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -9576,9 +9728,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -10199,6 +10351,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -11617,10 +11777,26 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_FACI_LP_FSTATR2_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ #define R_FACI_LP_FSTATR2_ERERR_Pos (0UL) /*!< ERERR (Bit 0) */ #define R_FACI_LP_FSTATR2_ERERR_Msk (0x1UL) /*!< ERERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FCTLFR ========================================================= */ + #define R_FACI_LP_FCTLFR_BANKSWP_Pos (0UL) /*!< BANKSWP (Bit 0) */ + #define R_FACI_LP_FCTLFR_BANKSWP_Msk (0x7UL) /*!< BANKSWP (Bitfield-Mask: 0x07) */ /* ====================================================== FENTRYR_MF4 ====================================================== */ /* ======================================================== FENTRYR ======================================================== */ /* ======================================================== FLWAITR ======================================================== */ +/* ======================================================= FLDWAITR ======================================================== */ + #define R_FACI_LP_FLDWAITR_FLDWAIT1_Pos (0UL) /*!< FLDWAIT1 (Bit 0) */ + #define R_FACI_LP_FLDWAITR_FLDWAIT1_Msk (0x1UL) /*!< FLDWAIT1 (Bitfield-Mask: 0x01) */ /* ========================================================= PFBER ========================================================= */ +/* ======================================================== FBKPGCR ======================================================== */ + #define R_FACI_LP_FBKPGCR_BKPGEN_Pos (0UL) /*!< BKPGEN (Bit 0) */ + #define R_FACI_LP_FBKPGCR_BKPGEN_Msk (0x1UL) /*!< BKPGEN (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FBKPGCR_FEKEY_Pos (8UL) /*!< FEKEY (Bit 8) */ + #define R_FACI_LP_FBKPGCR_FEKEY_Msk (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== FBKSWCR ======================================================== */ + #define R_FACI_LP_FBKSWCR_BKSWUPEN_Pos (0UL) /*!< BKSWUPEN (Bit 0) */ + #define R_FACI_LP_FBKSWCR_BKSWUPEN_Msk (0x1UL) /*!< BKSWUPEN (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FBKSWCR_FEKEY_Pos (8UL) /*!< FEKEY (Bit 8) */ + #define R_FACI_LP_FBKSWCR_FEKEY_Msk (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff) */ /* =========================================================================================================================== */ /* ================ R_CTSUTRIM ================ */ @@ -12680,6 +12856,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -12731,6 +12909,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -12745,6 +12925,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -14274,6 +14462,12 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -14312,6 +14506,20 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -14319,6 +14527,13 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h index 214986ce9..ea320beb6 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2E2A7.h @@ -22,9 +22,6 @@ * @file ./out/R7FA2E2A7.h * @brief CMSIS HeaderFile * @version 1.00.00 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:56:44 - * from File './out/R7FA2E2A7.svd', */ /** @addtogroup Renesas Electronics Corporation @@ -699,6 +696,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -3142,18 +3158,69 @@ typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure uint32_t : 26; } FSTATR2_b; }; - __IM uint32_t RESERVED24[3951]; + __IM uint32_t RESERVED24[95]; + + union + { + __IOM uint32_t FCTLFR; /*!< (@ 0x00000370) Flash Control Flag Register */ + + struct + { + __IOM uint32_t BANKSWP : 3; /*!< [2..0] Bank Swap Setting */ + uint32_t : 29; + } FCTLFR_b; + }; + __IM uint32_t RESERVED25[3855]; __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ - __IM uint32_t RESERVED25[3]; + __IM uint32_t RESERVED26[3]; __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ - __IM uint8_t RESERVED26; - __IM uint16_t RESERVED27; - __IM uint32_t RESERVED28; - __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ - __IM uint8_t RESERVED29; - __IM uint16_t RESERVED30; -} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ + __IM uint8_t RESERVED27; + __IM uint16_t RESERVED28; + + union + { + __IOM uint8_t FLDWAITR; /*!< (@ 0x00003FC4) Memory Wait Cycle Control Register for Data Flash */ + + struct + { + __IOM uint8_t FLDWAIT1 : 1; /*!< [0..0] Memory Wait Cycle Select for Data Flash */ + uint8_t : 7; + } FLDWAITR_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + __IM uint32_t RESERVED33; + + union + { + __IOM uint16_t FBKPGCR; /*!< (@ 0x00003FD0) Flash Bank Program Control Register */ + + struct + { + __IOM uint16_t BKPGEN : 1; /*!< [0..0] Bank Programming Setting Enable */ + uint16_t : 7; + __OM uint16_t FEKEY : 8; /*!< [15..8] Key Code */ + } FBKPGCR_b; + }; + __IM uint16_t RESERVED34; + + union + { + __IOM uint16_t FBKSWCR; /*!< (@ 0x00003FD4) Flash Bank Swap Control Register */ + + struct + { + __IOM uint16_t BKSWUPEN : 1; /*!< [0..0] Bank Swap Update Enable */ + uint16_t : 7; + __OM uint16_t FEKEY : 8; /*!< [15..8] Key Code */ + } FBKSWCR_b; + }; + __IM uint16_t RESERVED35; +} R_FACI_LP_Type; /*!< Size = 16344 (0x3fd8) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -6072,7 +6139,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -6103,10 +6171,17 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -6114,7 +6189,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -6446,10 +6522,14 @@ typedef struct /*!< (@ 0x40040000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -8092,24 +8172,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -8171,32 +8279,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -8210,8 +8362,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -8226,7 +8378,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -8256,7 +8408,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -8299,7 +8451,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -8337,7 +8489,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -8349,7 +8501,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -8362,7 +8514,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -8376,8 +8528,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -8411,8 +8563,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -8438,8 +8590,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -8494,7 +8646,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -8522,7 +8674,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -8591,7 +8743,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -8653,8 +8805,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -8872,7 +9024,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -8930,7 +9082,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -8947,7 +9099,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -9017,7 +9169,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -9050,7 +9202,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -9085,7 +9237,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -9128,7 +9280,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -9140,9 +9292,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -9165,8 +9317,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -9178,7 +9330,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -9193,8 +9345,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -9233,7 +9385,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -9247,7 +9399,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -9259,7 +9411,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -9394,9 +9546,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -10005,6 +10157,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -10953,10 +11113,26 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_FACI_LP_FSTATR2_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ #define R_FACI_LP_FSTATR2_ERERR_Pos (0UL) /*!< ERERR (Bit 0) */ #define R_FACI_LP_FSTATR2_ERERR_Msk (0x1UL) /*!< ERERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FCTLFR ========================================================= */ + #define R_FACI_LP_FCTLFR_BANKSWP_Pos (0UL) /*!< BANKSWP (Bit 0) */ + #define R_FACI_LP_FCTLFR_BANKSWP_Msk (0x7UL) /*!< BANKSWP (Bitfield-Mask: 0x07) */ /* ====================================================== FENTRYR_MF4 ====================================================== */ /* ======================================================== FENTRYR ======================================================== */ /* ======================================================== FLWAITR ======================================================== */ +/* ======================================================= FLDWAITR ======================================================== */ + #define R_FACI_LP_FLDWAITR_FLDWAIT1_Pos (0UL) /*!< FLDWAIT1 (Bit 0) */ + #define R_FACI_LP_FLDWAITR_FLDWAIT1_Msk (0x1UL) /*!< FLDWAIT1 (Bitfield-Mask: 0x01) */ /* ========================================================= PFBER ========================================================= */ +/* ======================================================== FBKPGCR ======================================================== */ + #define R_FACI_LP_FBKPGCR_BKPGEN_Pos (0UL) /*!< BKPGEN (Bit 0) */ + #define R_FACI_LP_FBKPGCR_BKPGEN_Msk (0x1UL) /*!< BKPGEN (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FBKPGCR_FEKEY_Pos (8UL) /*!< FEKEY (Bit 8) */ + #define R_FACI_LP_FBKPGCR_FEKEY_Msk (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== FBKSWCR ======================================================== */ + #define R_FACI_LP_FBKSWCR_BKSWUPEN_Pos (0UL) /*!< BKSWUPEN (Bit 0) */ + #define R_FACI_LP_FBKSWCR_BKSWUPEN_Msk (0x1UL) /*!< BKSWUPEN (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FBKSWCR_FEKEY_Pos (8UL) /*!< FEKEY (Bit 8) */ + #define R_FACI_LP_FBKSWCR_FEKEY_Msk (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff) */ /* =========================================================================================================================== */ /* ================ R_GPT0 ================ */ @@ -12624,6 +12800,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -12675,6 +12853,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -12689,6 +12869,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -14033,6 +14221,12 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -14071,6 +14265,20 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -14078,6 +14286,13 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h index 5c52ed28a..8debb83dd 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA2L1AB.h @@ -22,9 +22,6 @@ * @file ./out/R7FA2L1AB.h * @brief CMSIS HeaderFile * @version 0.50.00 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:56:52 - * from File './out/R7FA2L1AB.svd', */ /** @addtogroup Renesas Electronics Corporation @@ -758,6 +755,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -3898,12 +3914,19 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for * D/A and A/D synchronous conversions. Set bit [1] to 1 to * select unit 1 as the target synchronous unit for the MCU. * When setting the DAADSCR.DAADST bit to 1 for synchronous @@ -3911,7 +3934,7 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure * advance. Only set the DAADUSR register while the ADCSR.ADST * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit * is set to 0. */ - uint8_t : 1; + uint8_t : 6; } DAADUSR_b; }; __IM uint8_t RESERVED3; @@ -4584,18 +4607,69 @@ typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure uint32_t : 26; } FSTATR2_b; }; - __IM uint32_t RESERVED24[3951]; + __IM uint32_t RESERVED24[95]; + + union + { + __IOM uint32_t FCTLFR; /*!< (@ 0x00000370) Flash Control Flag Register */ + + struct + { + __IOM uint32_t BANKSWP : 3; /*!< [2..0] Bank Swap Setting */ + uint32_t : 29; + } FCTLFR_b; + }; + __IM uint32_t RESERVED25[3855]; __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ - __IM uint32_t RESERVED25[3]; + __IM uint32_t RESERVED26[3]; __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ - __IM uint8_t RESERVED26; - __IM uint16_t RESERVED27; - __IM uint32_t RESERVED28; - __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ - __IM uint8_t RESERVED29; - __IM uint16_t RESERVED30; -} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ + __IM uint8_t RESERVED27; + __IM uint16_t RESERVED28; + + union + { + __IOM uint8_t FLDWAITR; /*!< (@ 0x00003FC4) Memory Wait Cycle Control Register for Data Flash */ + + struct + { + __IOM uint8_t FLDWAIT1 : 1; /*!< [0..0] Memory Wait Cycle Select for Data Flash */ + uint8_t : 7; + } FLDWAITR_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + __IM uint32_t RESERVED33; + + union + { + __IOM uint16_t FBKPGCR; /*!< (@ 0x00003FD0) Flash Bank Program Control Register */ + + struct + { + __IOM uint16_t BKPGEN : 1; /*!< [0..0] Bank Programming Setting Enable */ + uint16_t : 7; + __OM uint16_t FEKEY : 8; /*!< [15..8] Key Code */ + } FBKPGCR_b; + }; + __IM uint16_t RESERVED34; + + union + { + __IOM uint16_t FBKSWCR; /*!< (@ 0x00003FD4) Flash Bank Swap Control Register */ + + struct + { + __IOM uint16_t BKSWUPEN : 1; /*!< [0..0] Bank Swap Update Enable */ + uint16_t : 7; + __OM uint16_t FEKEY : 8; /*!< [15..8] Key Code */ + } FBKSWCR_b; + }; + __IM uint16_t RESERVED35; +} R_FACI_LP_Type; /*!< Size = 16344 (0x3fd8) */ /* =========================================================================================================================== */ /* ================ R_CTSUTRIM ================ */ @@ -6421,7 +6495,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -6452,10 +6527,17 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -6463,7 +6545,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -6795,10 +6878,14 @@ typedef struct /*!< (@ 0x40040000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -8941,24 +9028,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -9020,32 +9135,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -9059,8 +9218,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -9075,7 +9234,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -9105,7 +9264,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -9148,7 +9307,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -9186,7 +9345,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -9198,7 +9357,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -9211,7 +9370,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -9225,8 +9384,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -9260,8 +9419,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -9287,8 +9446,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -9343,7 +9502,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -9371,7 +9530,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -9440,7 +9599,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -9502,8 +9661,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -9721,7 +9880,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -9779,7 +9938,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -9796,7 +9955,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -9866,7 +10025,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -9899,7 +10058,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -9934,7 +10093,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -9977,7 +10136,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -9989,9 +10148,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -10014,8 +10173,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -10027,7 +10186,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -10042,8 +10201,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -10082,7 +10241,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -10096,7 +10255,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -10108,7 +10267,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -10243,9 +10402,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -10897,6 +11056,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -12478,8 +12645,10 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ /* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DEBUG ================ */ @@ -12753,10 +12922,26 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_FACI_LP_FSTATR2_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ #define R_FACI_LP_FSTATR2_ERERR_Pos (0UL) /*!< ERERR (Bit 0) */ #define R_FACI_LP_FSTATR2_ERERR_Msk (0x1UL) /*!< ERERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FCTLFR ========================================================= */ + #define R_FACI_LP_FCTLFR_BANKSWP_Pos (0UL) /*!< BANKSWP (Bit 0) */ + #define R_FACI_LP_FCTLFR_BANKSWP_Msk (0x7UL) /*!< BANKSWP (Bitfield-Mask: 0x07) */ /* ====================================================== FENTRYR_MF4 ====================================================== */ /* ======================================================== FENTRYR ======================================================== */ /* ======================================================== FLWAITR ======================================================== */ +/* ======================================================= FLDWAITR ======================================================== */ + #define R_FACI_LP_FLDWAITR_FLDWAIT1_Pos (0UL) /*!< FLDWAIT1 (Bit 0) */ + #define R_FACI_LP_FLDWAITR_FLDWAIT1_Msk (0x1UL) /*!< FLDWAIT1 (Bitfield-Mask: 0x01) */ /* ========================================================= PFBER ========================================================= */ +/* ======================================================== FBKPGCR ======================================================== */ + #define R_FACI_LP_FBKPGCR_BKPGEN_Pos (0UL) /*!< BKPGEN (Bit 0) */ + #define R_FACI_LP_FBKPGCR_BKPGEN_Msk (0x1UL) /*!< BKPGEN (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FBKPGCR_FEKEY_Pos (8UL) /*!< FEKEY (Bit 8) */ + #define R_FACI_LP_FBKPGCR_FEKEY_Msk (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== FBKSWCR ======================================================== */ + #define R_FACI_LP_FBKSWCR_BKSWUPEN_Pos (0UL) /*!< BKSWUPEN (Bit 0) */ + #define R_FACI_LP_FBKSWCR_BKSWUPEN_Msk (0x1UL) /*!< BKSWUPEN (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FBKSWCR_FEKEY_Pos (8UL) /*!< FEKEY (Bit 8) */ + #define R_FACI_LP_FBKSWCR_FEKEY_Msk (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff) */ /* =========================================================================================================================== */ /* ================ R_CTSUTRIM ================ */ @@ -13816,6 +14001,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -13867,6 +14054,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -13881,6 +14070,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -15410,6 +15607,12 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -15448,6 +15651,20 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -15455,6 +15672,13 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h index d0a5e8292..cf7960318 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4E10D.h @@ -22,9 +22,6 @@ * @file ./out/R7FA4E10D.h * @brief CMSIS HeaderFile * @version 1.10.00 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:57:02 - * from File './out/R7FA4E10D.svd', */ /** @addtogroup Renesas Electronics Corporation @@ -760,6 +757,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -926,6 +942,179 @@ typedef struct __IM uint8_t RESERVED5[3]; } R_RTC_CP_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_BUS_B_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 7; + } ERRRW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, + * It stores an error address. */ + } TZFADD_b; + }; + + union + { + __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the + * time of the error */ + uint8_t : 7; + } TZFERRRW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ + /** * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) */ @@ -3534,12 +3723,19 @@ typedef struct /*!< (@ 0x40171000) R_DAC Structure union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for * D/A and A/D synchronous conversions. Set bit [1] to 1 to * select unit 1 as the target synchronous unit for the MCU. * When setting the DAADSCR.DAADST bit to 1 for synchronous @@ -3547,7 +3743,7 @@ typedef struct /*!< (@ 0x40171000) R_DAC Structure * advance. Only set the DAADUSR register while the ADCSR.ADST * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit * is set to 0. */ - uint8_t : 1; + uint8_t : 6; } DAADUSR_b; }; __IM uint8_t RESERVED3; @@ -6157,7 +6353,8 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -6188,10 +6385,17 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -6199,7 +6403,8 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -6531,10 +6736,14 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -8432,6 +8641,332 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure }; } R_SRAM_Type; /*!< Size = 217 (0xd9) */ +/* =========================================================================================================================== */ +/* ================ R_BUS_B ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS_B) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ +{ + __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[543]; + + union + { + __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTFHBIU_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTFLBIU_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTS0BIU_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPSBIU_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPLBIU_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPHBIU_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[2]; + + union + { + __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTEQBIU_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTEOBIU_b; + }; + __IM uint16_t RESERVED14; + + union + { + __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTECBIU_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[429]; + __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED17[48]; + __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IM uint32_t RESERVED18[48]; + + union + { + __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS1ERRSTAT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + __IM uint32_t RESERVED21; + + union + { + __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS1ERRCLR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24; + + union + { + __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS2ERRSTAT_b; + }; + __IM uint8_t RESERVED25; + __IM uint16_t RESERVED26; + __IM uint32_t RESERVED27; + + union + { + __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS2ERRCLR_b; + }; + __IM uint8_t RESERVED28; + __IM uint16_t RESERVED29; + __IM uint32_t RESERVED30; + + union + { + __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS3ERRSTAT_b; + }; + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + + union + { + __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } DMACDTCERRSTAT_b; + }; + __IM uint8_t RESERVED33; + __IM uint16_t RESERVED34; + + union + { + __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS3ERRCLR_b; + }; + __IM uint8_t RESERVED35; + __IM uint16_t RESERVED36; + + union + { + __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } DMACDTCERRCLR_b; + }; + __IM uint8_t RESERVED37; + __IM uint16_t RESERVED38; + + union + { + __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS4ERRSTAT_b; + }; + __IM uint8_t RESERVED39; + __IM uint16_t RESERVED40; + __IM uint32_t RESERVED41; + + union + { + __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS4ERRCLR_b; + }; + __IM uint8_t RESERVED42; + __IM uint16_t RESERVED43; +} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ + /* =========================================================================================================================== */ /* ================ R_SYSTEM ================ */ /* =========================================================================================================================== */ @@ -8881,24 +9416,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -8960,32 +9523,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -8999,8 +9606,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -9015,7 +9622,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -9045,7 +9652,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -9088,7 +9695,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -9126,7 +9733,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -9138,7 +9745,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -9151,7 +9758,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -9165,8 +9772,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -9200,8 +9807,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -9227,8 +9834,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -9283,7 +9890,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -9311,7 +9918,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -9380,7 +9987,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -9442,8 +10049,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -9661,7 +10268,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -9719,7 +10326,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -9736,7 +10343,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -9806,7 +10413,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -9839,7 +10446,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -9874,7 +10481,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -9917,7 +10524,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -9929,9 +10536,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -9954,8 +10561,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -9967,7 +10574,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -9982,8 +10589,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -10022,7 +10629,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -10036,7 +10643,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -10048,7 +10655,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -10183,9 +10790,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -11833,6 +12440,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL + #define R_BUS_B_BASE 0x40003000UL #define R_SYSTEM_BASE 0x4001E000UL #define R_TSN_BASE 0x407EC000UL #define R_USB_FS0_BASE 0x40090000UL @@ -11860,7 +12468,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) - #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + +/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ #define R_CAC ((R_CAC_Type *) R_CAC_BASE) #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) @@ -11939,6 +12548,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) #define R_TSN ((R_TSN_Type *) R_TSN_BASE) #define R_USB_FS0 ((R_USB_FS0_Type *) R_USB_FS0_BASE) @@ -12283,6 +12893,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -12345,6 +12963,89 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ERRRW ========================================================= */ + #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFADD ========================================================= */ + #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TZFERRRW ======================================================== */ + #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PIPE_TR ================ */ /* =========================================================================================================================== */ @@ -13629,8 +14330,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ /* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DEBUG ================ */ @@ -14964,6 +15667,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -15015,6 +15720,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -15029,6 +15736,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -16051,6 +16766,121 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ +/* =========================================================================================================================== */ +/* ================ R_BUS_B ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== BUSSCNTFHBIU ====================================================== */ + #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTFLBIU ====================================================== */ + #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTS0BIU ====================================================== */ + #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTPSBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTPLBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTPHBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTEQBIU ====================================================== */ + #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTEOBIU ====================================================== */ + #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTECBIU ====================================================== */ + #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ====================================================== BUS1ERRSTAT ====================================================== */ + #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS2ERRSTAT ====================================================== */ + #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS3ERRSTAT ====================================================== */ + #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS4ERRSTAT ====================================================== */ + #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS1ERRCLR ======================================================= */ + #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS2ERRCLR ======================================================= */ + #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS3ERRCLR ======================================================= */ + #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS4ERRCLR ======================================================= */ + #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ==================================================== DMACDTCERRSTAT ===================================================== */ + #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ===================================================== DMACDTCERRCLR ===================================================== */ + #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ R_SYSTEM ================ */ /* =========================================================================================================================== */ @@ -16640,6 +17470,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -16678,6 +17514,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -16685,6 +17535,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h index 1dfbad549..d824c35c4 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M1AB.h @@ -18,9 +18,6 @@ * @file ./out/R7FA4M1AB.h * @brief CMSIS HeaderFile * @version 1.2 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:57:14 - * from File './out/R7FA4M1AB.svd', */ /** @addtogroup Renesas @@ -791,6 +788,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -3674,12 +3690,19 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for * D/A and A/D synchronous conversions. Set bit [1] to 1 to * select unit 1 as the target synchronous unit for the MCU. * When setting the DAADSCR.DAADST bit to 1 for synchronous @@ -3687,7 +3710,7 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure * advance. Only set the DAADUSR register while the ADCSR.ADST * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit * is set to 0. */ - uint8_t : 1; + uint8_t : 6; } DAADUSR_b; }; __IM uint8_t RESERVED3; @@ -4675,18 +4698,69 @@ typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure uint32_t : 26; } FSTATR2_b; }; - __IM uint32_t RESERVED24[3951]; + __IM uint32_t RESERVED24[95]; + + union + { + __IOM uint32_t FCTLFR; /*!< (@ 0x00000370) Flash Control Flag Register */ + + struct + { + __IOM uint32_t BANKSWP : 3; /*!< [2..0] Bank Swap Setting */ + uint32_t : 29; + } FCTLFR_b; + }; + __IM uint32_t RESERVED25[3855]; __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ - __IM uint32_t RESERVED25[3]; + __IM uint32_t RESERVED26[3]; __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ - __IM uint8_t RESERVED26; - __IM uint16_t RESERVED27; - __IM uint32_t RESERVED28; - __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ - __IM uint8_t RESERVED29; - __IM uint16_t RESERVED30; -} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ + __IM uint8_t RESERVED27; + __IM uint16_t RESERVED28; + + union + { + __IOM uint8_t FLDWAITR; /*!< (@ 0x00003FC4) Memory Wait Cycle Control Register for Data Flash */ + + struct + { + __IOM uint8_t FLDWAIT1 : 1; /*!< [0..0] Memory Wait Cycle Select for Data Flash */ + uint8_t : 7; + } FLDWAITR_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + __IM uint32_t RESERVED33; + + union + { + __IOM uint16_t FBKPGCR; /*!< (@ 0x00003FD0) Flash Bank Program Control Register */ + + struct + { + __IOM uint16_t BKPGEN : 1; /*!< [0..0] Bank Programming Setting Enable */ + uint16_t : 7; + __OM uint16_t FEKEY : 8; /*!< [15..8] Key Code */ + } FBKPGCR_b; + }; + __IM uint16_t RESERVED34; + + union + { + __IOM uint16_t FBKSWCR; /*!< (@ 0x00003FD4) Flash Bank Swap Control Register */ + + struct + { + __IOM uint16_t BKSWUPEN : 1; /*!< [0..0] Bank Swap Update Enable */ + uint16_t : 7; + __OM uint16_t FEKEY : 8; /*!< [15..8] Key Code */ + } FBKSWCR_b; + }; + __IM uint16_t RESERVED35; +} R_FACI_LP_Type; /*!< Size = 16344 (0x3fd8) */ /* =========================================================================================================================== */ /* ================ R_FCACHE ================ */ @@ -6531,7 +6605,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -6562,10 +6637,17 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -6573,7 +6655,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -7025,10 +7108,14 @@ typedef struct /*!< (@ 0x40040000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -8389,8 +8476,9 @@ typedef struct /*!< (@ 0x40082000) R_SLCDC Structure struct { - __IOM uint8_t VLCD : 5; /*!< [4..0] Reference Voltage(Contrast Adjustment) Select */ - uint8_t : 3; + __IOM uint8_t VLCD : 5; /*!< [4..0] Reference Voltage(Contrast Adjustment) Select */ + uint8_t : 2; + __IOM uint8_t MDSET2 : 1; /*!< [7..7] Reference Voltage Selection */ } VLCD_b; }; __IM uint8_t RESERVED[252]; @@ -9448,24 +9536,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -9527,32 +9643,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -9566,8 +9726,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -9582,7 +9742,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -9612,7 +9772,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -9655,7 +9815,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -9693,7 +9853,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -9705,7 +9865,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -9718,7 +9878,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -9732,8 +9892,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -9767,8 +9927,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -9794,8 +9954,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -9850,7 +10010,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -9878,7 +10038,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -9947,7 +10107,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -10009,8 +10169,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -10228,7 +10388,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -10286,7 +10446,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -10303,7 +10463,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -10373,7 +10533,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -10406,7 +10566,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -10441,7 +10601,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -10484,7 +10644,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -10496,9 +10656,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -10521,8 +10681,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -10534,7 +10694,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -10549,8 +10709,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -10589,7 +10749,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -10603,7 +10763,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -10615,7 +10775,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -10750,9 +10910,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -12522,6 +12682,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -13866,8 +14034,10 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ /* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DAC8 ================ */ @@ -14273,10 +14443,26 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_FACI_LP_FSTATR2_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ #define R_FACI_LP_FSTATR2_ERERR_Pos (0UL) /*!< ERERR (Bit 0) */ #define R_FACI_LP_FSTATR2_ERERR_Msk (0x1UL) /*!< ERERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FCTLFR ========================================================= */ + #define R_FACI_LP_FCTLFR_BANKSWP_Pos (0UL) /*!< BANKSWP (Bit 0) */ + #define R_FACI_LP_FCTLFR_BANKSWP_Msk (0x7UL) /*!< BANKSWP (Bitfield-Mask: 0x07) */ /* ====================================================== FENTRYR_MF4 ====================================================== */ /* ======================================================== FENTRYR ======================================================== */ /* ======================================================== FLWAITR ======================================================== */ +/* ======================================================= FLDWAITR ======================================================== */ + #define R_FACI_LP_FLDWAITR_FLDWAIT1_Pos (0UL) /*!< FLDWAIT1 (Bit 0) */ + #define R_FACI_LP_FLDWAITR_FLDWAIT1_Msk (0x1UL) /*!< FLDWAIT1 (Bitfield-Mask: 0x01) */ /* ========================================================= PFBER ========================================================= */ +/* ======================================================== FBKPGCR ======================================================== */ + #define R_FACI_LP_FBKPGCR_BKPGEN_Pos (0UL) /*!< BKPGEN (Bit 0) */ + #define R_FACI_LP_FBKPGCR_BKPGEN_Msk (0x1UL) /*!< BKPGEN (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FBKPGCR_FEKEY_Pos (8UL) /*!< FEKEY (Bit 8) */ + #define R_FACI_LP_FBKPGCR_FEKEY_Msk (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== FBKSWCR ======================================================== */ + #define R_FACI_LP_FBKSWCR_BKSWUPEN_Pos (0UL) /*!< BKSWUPEN (Bit 0) */ + #define R_FACI_LP_FBKSWCR_BKSWUPEN_Msk (0x1UL) /*!< BKSWUPEN (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FBKSWCR_FEKEY_Pos (8UL) /*!< FEKEY (Bit 8) */ + #define R_FACI_LP_FBKSWCR_FEKEY_Msk (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff) */ /* =========================================================================================================================== */ /* ================ R_FCACHE ================ */ @@ -15332,6 +15518,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -15383,6 +15571,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -15397,6 +15587,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -16198,6 +16396,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SLCDC_LCDC0_LCDC_Pos (0UL) /*!< LCDC (Bit 0) */ #define R_SLCDC_LCDC0_LCDC_Msk (0x3fUL) /*!< LCDC (Bitfield-Mask: 0x3f) */ /* ========================================================= VLCD ========================================================== */ + #define R_SLCDC_VLCD_MDSET2_Pos (7UL) /*!< MDSET2 (Bit 7) */ + #define R_SLCDC_VLCD_MDSET2_Msk (0x80UL) /*!< MDSET2 (Bitfield-Mask: 0x01) */ #define R_SLCDC_VLCD_VLCD_Pos (0UL) /*!< VLCD (Bit 0) */ #define R_SLCDC_VLCD_VLCD_Msk (0x1fUL) /*!< VLCD (Bitfield-Mask: 0x1f) */ /* ========================================================== SEG ========================================================== */ @@ -17111,6 +17311,12 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -17149,6 +17355,20 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -17156,6 +17376,13 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h index 76abd76e5..a738099d4 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M2AD.h @@ -22,9 +22,6 @@ * @file ./out/R7FA4M2AD.h * @brief CMSIS HeaderFile * @version 1.10.03 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:57:26 - * from File './out/R7FA4M2AD.svd', */ /** @addtogroup Renesas Electronics Corporation @@ -760,6 +757,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -926,6 +942,179 @@ typedef struct __IM uint8_t RESERVED5[3]; } R_RTC_CP_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_BUS_B_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 7; + } ERRRW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, + * It stores an error address. */ + } TZFADD_b; + }; + + union + { + __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the + * time of the error */ + uint8_t : 7; + } TZFERRRW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ + /** * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) */ @@ -3777,12 +3966,19 @@ typedef struct /*!< (@ 0x40171000) R_DAC Structure union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for * D/A and A/D synchronous conversions. Set bit [1] to 1 to * select unit 1 as the target synchronous unit for the MCU. * When setting the DAADSCR.DAADST bit to 1 for synchronous @@ -3790,7 +3986,7 @@ typedef struct /*!< (@ 0x40171000) R_DAC Structure * advance. Only set the DAADUSR register while the ADCSR.ADST * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit * is set to 0. */ - uint8_t : 1; + uint8_t : 6; } DAADUSR_b; }; __IM uint8_t RESERVED3; @@ -6456,7 +6652,8 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -6487,10 +6684,17 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -6498,7 +6702,8 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -6830,10 +7035,14 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -9219,6 +9428,332 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure }; } R_SRAM_Type; /*!< Size = 217 (0xd9) */ +/* =========================================================================================================================== */ +/* ================ R_BUS_B ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS_B) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ +{ + __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[543]; + + union + { + __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTFHBIU_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTFLBIU_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTS0BIU_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPSBIU_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPLBIU_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPHBIU_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[2]; + + union + { + __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTEQBIU_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTEOBIU_b; + }; + __IM uint16_t RESERVED14; + + union + { + __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTECBIU_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[429]; + __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED17[48]; + __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IM uint32_t RESERVED18[48]; + + union + { + __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS1ERRSTAT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + __IM uint32_t RESERVED21; + + union + { + __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS1ERRCLR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24; + + union + { + __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS2ERRSTAT_b; + }; + __IM uint8_t RESERVED25; + __IM uint16_t RESERVED26; + __IM uint32_t RESERVED27; + + union + { + __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS2ERRCLR_b; + }; + __IM uint8_t RESERVED28; + __IM uint16_t RESERVED29; + __IM uint32_t RESERVED30; + + union + { + __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS3ERRSTAT_b; + }; + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + + union + { + __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } DMACDTCERRSTAT_b; + }; + __IM uint8_t RESERVED33; + __IM uint16_t RESERVED34; + + union + { + __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS3ERRCLR_b; + }; + __IM uint8_t RESERVED35; + __IM uint16_t RESERVED36; + + union + { + __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } DMACDTCERRCLR_b; + }; + __IM uint8_t RESERVED37; + __IM uint16_t RESERVED38; + + union + { + __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS4ERRSTAT_b; + }; + __IM uint8_t RESERVED39; + __IM uint16_t RESERVED40; + __IM uint32_t RESERVED41; + + union + { + __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS4ERRCLR_b; + }; + __IM uint8_t RESERVED42; + __IM uint16_t RESERVED43; +} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ + /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ /* =========================================================================================================================== */ @@ -9870,24 +10405,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -9949,32 +10512,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -9988,8 +10595,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -10004,7 +10611,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -10034,7 +10641,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -10077,7 +10684,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -10115,7 +10722,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -10127,7 +10734,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -10140,7 +10747,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -10154,8 +10761,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -10189,8 +10796,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -10216,8 +10823,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -10272,7 +10879,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -10300,7 +10907,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -10369,7 +10976,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -10431,8 +11038,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -10650,7 +11257,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -10708,7 +11315,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -10725,7 +11332,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -10795,7 +11402,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -10828,7 +11435,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -10863,7 +11470,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -10906,7 +11513,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -10918,9 +11525,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -10943,8 +11550,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -10956,7 +11563,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -10971,8 +11578,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -11011,7 +11618,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -11025,7 +11632,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -11037,7 +11644,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -11172,9 +11779,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -12836,6 +13443,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL + #define R_BUS_B_BASE 0x40003000UL #define R_SSI0_BASE 0x4009D000UL #define R_SSI1_BASE 0x4009D100UL #define R_SYSTEM_BASE 0x4001E000UL @@ -12866,7 +13474,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) - #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + +/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ #define R_CAC ((R_CAC_Type *) R_CAC_BASE) #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) @@ -12949,6 +13558,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) @@ -13296,6 +13906,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -13358,6 +13976,89 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ERRRW ========================================================= */ + #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFADD ========================================================= */ + #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TZFERRRW ======================================================== */ + #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PIPE_TR ================ */ /* =========================================================================================================================== */ @@ -14746,8 +15447,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ /* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DEBUG ================ */ @@ -16121,6 +16824,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -16172,6 +16877,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -16186,6 +16893,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -17445,6 +18160,121 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ +/* =========================================================================================================================== */ +/* ================ R_BUS_B ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== BUSSCNTFHBIU ====================================================== */ + #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTFLBIU ====================================================== */ + #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTS0BIU ====================================================== */ + #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTPSBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTPLBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTPHBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTEQBIU ====================================================== */ + #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTEOBIU ====================================================== */ + #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTECBIU ====================================================== */ + #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ====================================================== BUS1ERRSTAT ====================================================== */ + #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS2ERRSTAT ====================================================== */ + #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS3ERRSTAT ====================================================== */ + #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS4ERRSTAT ====================================================== */ + #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS1ERRCLR ======================================================= */ + #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS2ERRCLR ======================================================= */ + #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS3ERRCLR ======================================================= */ + #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS4ERRCLR ======================================================= */ + #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ==================================================== DMACDTCERRSTAT ===================================================== */ + #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ===================================================== DMACDTCERRCLR ===================================================== */ + #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ /* =========================================================================================================================== */ @@ -18151,6 +18981,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -18189,6 +19025,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -18196,6 +19046,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h index fb739cb36..b269b2075 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4M3AF.h @@ -22,9 +22,6 @@ * @file ./out/R7FA4M3AF.h * @brief CMSIS HeaderFile * @version 1.30.00 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:57:40 - * from File './out/R7FA4M3AF.svd', */ /** @addtogroup Renesas Electronics Corporation @@ -760,6 +757,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -926,6 +942,179 @@ typedef struct __IM uint8_t RESERVED5[3]; } R_RTC_CP_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_BUS_B_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 7; + } ERRRW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, + * It stores an error address. */ + } TZFADD_b; + }; + + union + { + __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the + * time of the error */ + uint8_t : 7; + } TZFERRRW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ + /** * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) */ @@ -3777,12 +3966,19 @@ typedef struct /*!< (@ 0x40171000) R_DAC Structure union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for * D/A and A/D synchronous conversions. Set bit [1] to 1 to * select unit 1 as the target synchronous unit for the MCU. * When setting the DAADSCR.DAADST bit to 1 for synchronous @@ -3790,7 +3986,7 @@ typedef struct /*!< (@ 0x40171000) R_DAC Structure * advance. Only set the DAADUSR register while the ADCSR.ADST * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit * is set to 0. */ - uint8_t : 1; + uint8_t : 6; } DAADUSR_b; }; __IM uint8_t RESERVED3; @@ -6456,7 +6652,8 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -6487,10 +6684,17 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -6498,7 +6702,8 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -6830,10 +7035,14 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -9219,6 +9428,332 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure }; } R_SRAM_Type; /*!< Size = 217 (0xd9) */ +/* =========================================================================================================================== */ +/* ================ R_BUS_B ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS_B) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ +{ + __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[543]; + + union + { + __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTFHBIU_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTFLBIU_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTS0BIU_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPSBIU_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPLBIU_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPHBIU_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[2]; + + union + { + __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTEQBIU_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTEOBIU_b; + }; + __IM uint16_t RESERVED14; + + union + { + __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTECBIU_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[429]; + __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED17[48]; + __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IM uint32_t RESERVED18[48]; + + union + { + __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS1ERRSTAT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + __IM uint32_t RESERVED21; + + union + { + __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS1ERRCLR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24; + + union + { + __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS2ERRSTAT_b; + }; + __IM uint8_t RESERVED25; + __IM uint16_t RESERVED26; + __IM uint32_t RESERVED27; + + union + { + __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS2ERRCLR_b; + }; + __IM uint8_t RESERVED28; + __IM uint16_t RESERVED29; + __IM uint32_t RESERVED30; + + union + { + __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS3ERRSTAT_b; + }; + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + + union + { + __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } DMACDTCERRSTAT_b; + }; + __IM uint8_t RESERVED33; + __IM uint16_t RESERVED34; + + union + { + __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS3ERRCLR_b; + }; + __IM uint8_t RESERVED35; + __IM uint16_t RESERVED36; + + union + { + __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } DMACDTCERRCLR_b; + }; + __IM uint8_t RESERVED37; + __IM uint16_t RESERVED38; + + union + { + __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS4ERRSTAT_b; + }; + __IM uint8_t RESERVED39; + __IM uint16_t RESERVED40; + __IM uint32_t RESERVED41; + + union + { + __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS4ERRCLR_b; + }; + __IM uint8_t RESERVED42; + __IM uint16_t RESERVED43; +} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ + /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ /* =========================================================================================================================== */ @@ -9870,24 +10405,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -9949,32 +10512,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -9988,8 +10595,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -10004,7 +10611,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -10034,7 +10641,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -10077,7 +10684,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -10115,7 +10722,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -10127,7 +10734,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -10140,7 +10747,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -10154,8 +10761,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -10189,8 +10796,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -10216,8 +10823,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -10272,7 +10879,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -10300,7 +10907,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -10369,7 +10976,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -10431,8 +11038,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -10650,7 +11257,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -10708,7 +11315,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -10725,7 +11332,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -10795,7 +11402,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -10828,7 +11435,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -10863,7 +11470,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -10906,7 +11513,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -10918,9 +11525,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -10943,8 +11550,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -10956,7 +11563,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -10971,8 +11578,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -11011,7 +11618,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -11025,7 +11632,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -11037,7 +11644,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -11172,9 +11779,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -12939,6 +13546,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL + #define R_BUS_B_BASE 0x40003000UL #define R_SSI0_BASE 0x4009D000UL #define R_SSI1_BASE 0x4009D100UL #define R_SYSTEM_BASE 0x4001E000UL @@ -12970,7 +13578,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) - #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + +/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ #define R_CAC ((R_CAC_Type *) R_CAC_BASE) #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) @@ -13053,6 +13662,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) @@ -13401,6 +14011,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -13463,6 +14081,89 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ERRRW ========================================================= */ + #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFADD ========================================================= */ + #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TZFERRRW ======================================================== */ + #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PIPE_TR ================ */ /* =========================================================================================================================== */ @@ -14851,8 +15552,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ /* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DEBUG ================ */ @@ -16226,6 +16929,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -16277,6 +16982,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -16291,6 +16998,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -17550,6 +18265,121 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ +/* =========================================================================================================================== */ +/* ================ R_BUS_B ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== BUSSCNTFHBIU ====================================================== */ + #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTFLBIU ====================================================== */ + #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTS0BIU ====================================================== */ + #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTPSBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTPLBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTPHBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTEQBIU ====================================================== */ + #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTEOBIU ====================================================== */ + #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTECBIU ====================================================== */ + #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ====================================================== BUS1ERRSTAT ====================================================== */ + #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS2ERRSTAT ====================================================== */ + #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS3ERRSTAT ====================================================== */ + #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS4ERRSTAT ====================================================== */ + #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS1ERRCLR ======================================================= */ + #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS2ERRCLR ======================================================= */ + #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS3ERRCLR ======================================================= */ + #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS4ERRCLR ======================================================= */ + #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ==================================================== DMACDTCERRSTAT ===================================================== */ + #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ===================================================== DMACDTCERRCLR ===================================================== */ + #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ /* =========================================================================================================================== */ @@ -18256,6 +19086,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -18294,6 +19130,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -18301,6 +19151,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h index 935fdb548..25d88e96a 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA4W1AD.h @@ -18,9 +18,6 @@ * @file ./out/R7FA4W1AD.h * @brief CMSIS HeaderFile * @version 1.0 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:58:19 - * from File './out/R7FA4W1AD.svd', */ /** @addtogroup Renesas @@ -791,6 +788,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -3674,12 +3690,19 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for * D/A and A/D synchronous conversions. Set bit [1] to 1 to * select unit 1 as the target synchronous unit for the MCU. * When setting the DAADSCR.DAADST bit to 1 for synchronous @@ -3687,7 +3710,7 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure * advance. Only set the DAADUSR register while the ADCSR.ADST * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit * is set to 0. */ - uint8_t : 1; + uint8_t : 6; } DAADUSR_b; }; __IM uint8_t RESERVED3; @@ -4675,18 +4698,69 @@ typedef struct /*!< (@ 0x407EC000) R_FACI_LP Structure uint32_t : 26; } FSTATR2_b; }; - __IM uint32_t RESERVED24[3951]; + __IM uint32_t RESERVED24[95]; + + union + { + __IOM uint32_t FCTLFR; /*!< (@ 0x00000370) Flash Control Flag Register */ + + struct + { + __IOM uint32_t BANKSWP : 3; /*!< [2..0] Bank Swap Setting */ + uint32_t : 29; + } FCTLFR_b; + }; + __IM uint32_t RESERVED25[3855]; __IOM uint16_t FENTRYR_MF4; /*!< (@ 0x00003FB0) Flash P/E Mode Entry Register for MF4 */ __IOM uint16_t FENTRYR; /*!< (@ 0x00003FB2) Flash P/E Mode Entry Register */ - __IM uint32_t RESERVED25[3]; + __IM uint32_t RESERVED26[3]; __IOM uint8_t FLWAITR; /*!< (@ 0x00003FC0) Flash Wait Cycle Register */ - __IM uint8_t RESERVED26; - __IM uint16_t RESERVED27; - __IM uint32_t RESERVED28; - __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ - __IM uint8_t RESERVED29; - __IM uint16_t RESERVED30; -} R_FACI_LP_Type; /*!< Size = 16332 (0x3fcc) */ + __IM uint8_t RESERVED27; + __IM uint16_t RESERVED28; + + union + { + __IOM uint8_t FLDWAITR; /*!< (@ 0x00003FC4) Memory Wait Cycle Control Register for Data Flash */ + + struct + { + __IOM uint8_t FLDWAIT1 : 1; /*!< [0..0] Memory Wait Cycle Select for Data Flash */ + uint8_t : 7; + } FLDWAITR_b; + }; + __IM uint8_t RESERVED29; + __IM uint16_t RESERVED30; + __IOM uint8_t PFBER; /*!< (@ 0x00003FC8) Prefetch Buffer Enable Register */ + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + __IM uint32_t RESERVED33; + + union + { + __IOM uint16_t FBKPGCR; /*!< (@ 0x00003FD0) Flash Bank Program Control Register */ + + struct + { + __IOM uint16_t BKPGEN : 1; /*!< [0..0] Bank Programming Setting Enable */ + uint16_t : 7; + __OM uint16_t FEKEY : 8; /*!< [15..8] Key Code */ + } FBKPGCR_b; + }; + __IM uint16_t RESERVED34; + + union + { + __IOM uint16_t FBKSWCR; /*!< (@ 0x00003FD4) Flash Bank Swap Control Register */ + + struct + { + __IOM uint16_t BKSWUPEN : 1; /*!< [0..0] Bank Swap Update Enable */ + uint16_t : 7; + __OM uint16_t FEKEY : 8; /*!< [15..8] Key Code */ + } FBKSWCR_b; + }; + __IM uint16_t RESERVED35; +} R_FACI_LP_Type; /*!< Size = 16344 (0x3fd8) */ /* =========================================================================================================================== */ /* ================ R_FCACHE ================ */ @@ -6569,7 +6643,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -6600,10 +6675,17 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -6611,7 +6693,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -7063,10 +7146,14 @@ typedef struct /*!< (@ 0x40040000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -8427,8 +8514,9 @@ typedef struct /*!< (@ 0x40082000) R_SLCDC Structure struct { - __IOM uint8_t VLCD : 5; /*!< [4..0] Reference Voltage(Contrast Adjustment) Select */ - uint8_t : 3; + __IOM uint8_t VLCD : 5; /*!< [4..0] Reference Voltage(Contrast Adjustment) Select */ + uint8_t : 2; + __IOM uint8_t MDSET2 : 1; /*!< [7..7] Reference Voltage Selection */ } VLCD_b; }; __IM uint8_t RESERVED[252]; @@ -9284,24 +9372,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -9363,32 +9479,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -9402,8 +9562,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -9418,7 +9578,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -9448,7 +9608,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -9491,7 +9651,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -9529,7 +9689,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -9541,7 +9701,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -9554,7 +9714,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -9568,8 +9728,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -9603,8 +9763,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -9630,8 +9790,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -9686,7 +9846,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -9714,7 +9874,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -9783,7 +9943,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -9845,8 +10005,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -10064,7 +10224,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -10122,7 +10282,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -10139,7 +10299,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -10209,7 +10369,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -10242,7 +10402,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -10277,7 +10437,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -10320,7 +10480,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -10332,9 +10492,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -10357,8 +10517,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -10370,7 +10530,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -10385,8 +10545,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -10425,7 +10585,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -10439,7 +10599,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -10451,7 +10611,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -10586,9 +10746,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -12356,6 +12516,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -13700,8 +13868,10 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ /* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DAC8 ================ */ @@ -14107,10 +14277,26 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_FACI_LP_FSTATR2_PRGERR1_Msk (0x2UL) /*!< PRGERR1 (Bitfield-Mask: 0x01) */ #define R_FACI_LP_FSTATR2_ERERR_Pos (0UL) /*!< ERERR (Bit 0) */ #define R_FACI_LP_FSTATR2_ERERR_Msk (0x1UL) /*!< ERERR (Bitfield-Mask: 0x01) */ +/* ======================================================== FCTLFR ========================================================= */ + #define R_FACI_LP_FCTLFR_BANKSWP_Pos (0UL) /*!< BANKSWP (Bit 0) */ + #define R_FACI_LP_FCTLFR_BANKSWP_Msk (0x7UL) /*!< BANKSWP (Bitfield-Mask: 0x07) */ /* ====================================================== FENTRYR_MF4 ====================================================== */ /* ======================================================== FENTRYR ======================================================== */ /* ======================================================== FLWAITR ======================================================== */ +/* ======================================================= FLDWAITR ======================================================== */ + #define R_FACI_LP_FLDWAITR_FLDWAIT1_Pos (0UL) /*!< FLDWAIT1 (Bit 0) */ + #define R_FACI_LP_FLDWAITR_FLDWAIT1_Msk (0x1UL) /*!< FLDWAIT1 (Bitfield-Mask: 0x01) */ /* ========================================================= PFBER ========================================================= */ +/* ======================================================== FBKPGCR ======================================================== */ + #define R_FACI_LP_FBKPGCR_BKPGEN_Pos (0UL) /*!< BKPGEN (Bit 0) */ + #define R_FACI_LP_FBKPGCR_BKPGEN_Msk (0x1UL) /*!< BKPGEN (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FBKPGCR_FEKEY_Pos (8UL) /*!< FEKEY (Bit 8) */ + #define R_FACI_LP_FBKPGCR_FEKEY_Msk (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff) */ +/* ======================================================== FBKSWCR ======================================================== */ + #define R_FACI_LP_FBKSWCR_BKSWUPEN_Pos (0UL) /*!< BKSWUPEN (Bit 0) */ + #define R_FACI_LP_FBKSWCR_BKSWUPEN_Msk (0x1UL) /*!< BKSWUPEN (Bitfield-Mask: 0x01) */ + #define R_FACI_LP_FBKSWCR_FEKEY_Pos (8UL) /*!< FEKEY (Bit 8) */ + #define R_FACI_LP_FBKSWCR_FEKEY_Msk (0xff00UL) /*!< FEKEY (Bitfield-Mask: 0xff) */ /* =========================================================================================================================== */ /* ================ R_FCACHE ================ */ @@ -15181,6 +15367,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -15232,6 +15420,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -15246,6 +15436,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -16047,6 +16245,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SLCDC_LCDC0_LCDC_Pos (0UL) /*!< LCDC (Bit 0) */ #define R_SLCDC_LCDC0_LCDC_Msk (0x3fUL) /*!< LCDC (Bitfield-Mask: 0x3f) */ /* ========================================================= VLCD ========================================================== */ + #define R_SLCDC_VLCD_MDSET2_Pos (7UL) /*!< MDSET2 (Bit 7) */ + #define R_SLCDC_VLCD_MDSET2_Msk (0x80UL) /*!< MDSET2 (Bitfield-Mask: 0x01) */ #define R_SLCDC_VLCD_VLCD_Pos (0UL) /*!< VLCD (Bit 0) */ #define R_SLCDC_VLCD_VLCD_Msk (0x1fUL) /*!< VLCD (Bitfield-Mask: 0x1f) */ /* ========================================================== SEG ========================================================== */ @@ -16843,6 +17043,12 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -16881,6 +17087,20 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -16888,6 +17108,13 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h index 10209e360..3805b8135 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6E10F.h @@ -22,9 +22,6 @@ * @file ./out/R7FA6E10F.h * @brief CMSIS HeaderFile * @version 1.10.00 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:58:32 - * from File './out/R7FA6E10F.svd', */ /** @addtogroup Renesas Electronics Corporation @@ -760,6 +757,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -926,6 +942,179 @@ typedef struct __IM uint8_t RESERVED5[3]; } R_RTC_CP_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_BUS_B_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 7; + } ERRRW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, + * It stores an error address. */ + } TZFADD_b; + }; + + union + { + __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the + * time of the error */ + uint8_t : 7; + } TZFERRRW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ + /** * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) */ @@ -3534,12 +3723,19 @@ typedef struct /*!< (@ 0x40171000) R_DAC Structure union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for * D/A and A/D synchronous conversions. Set bit [1] to 1 to * select unit 1 as the target synchronous unit for the MCU. * When setting the DAADSCR.DAADST bit to 1 for synchronous @@ -3547,7 +3743,7 @@ typedef struct /*!< (@ 0x40171000) R_DAC Structure * advance. Only set the DAADUSR register while the ADCSR.ADST * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit * is set to 0. */ - uint8_t : 1; + uint8_t : 6; } DAADUSR_b; }; __IM uint8_t RESERVED3; @@ -6885,7 +7081,8 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -6916,10 +7113,17 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -6927,7 +7131,8 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -7259,10 +7464,14 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -9648,6 +9857,332 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure }; } R_SRAM_Type; /*!< Size = 217 (0xd9) */ +/* =========================================================================================================================== */ +/* ================ R_BUS_B ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS_B) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ +{ + __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[543]; + + union + { + __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTFHBIU_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTFLBIU_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTS0BIU_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPSBIU_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPLBIU_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPHBIU_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[2]; + + union + { + __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTEQBIU_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTEOBIU_b; + }; + __IM uint16_t RESERVED14; + + union + { + __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTECBIU_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[429]; + __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED17[48]; + __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IM uint32_t RESERVED18[48]; + + union + { + __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS1ERRSTAT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + __IM uint32_t RESERVED21; + + union + { + __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS1ERRCLR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24; + + union + { + __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS2ERRSTAT_b; + }; + __IM uint8_t RESERVED25; + __IM uint16_t RESERVED26; + __IM uint32_t RESERVED27; + + union + { + __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS2ERRCLR_b; + }; + __IM uint8_t RESERVED28; + __IM uint16_t RESERVED29; + __IM uint32_t RESERVED30; + + union + { + __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS3ERRSTAT_b; + }; + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + + union + { + __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } DMACDTCERRSTAT_b; + }; + __IM uint8_t RESERVED33; + __IM uint16_t RESERVED34; + + union + { + __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS3ERRCLR_b; + }; + __IM uint8_t RESERVED35; + __IM uint16_t RESERVED36; + + union + { + __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } DMACDTCERRCLR_b; + }; + __IM uint8_t RESERVED37; + __IM uint16_t RESERVED38; + + union + { + __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS4ERRSTAT_b; + }; + __IM uint8_t RESERVED39; + __IM uint16_t RESERVED40; + __IM uint32_t RESERVED41; + + union + { + __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS4ERRCLR_b; + }; + __IM uint8_t RESERVED42; + __IM uint16_t RESERVED43; +} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ + /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ /* =========================================================================================================================== */ @@ -10299,24 +10834,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -10378,32 +10941,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -10417,8 +11024,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -10433,7 +11040,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -10463,7 +11070,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -10506,7 +11113,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -10544,7 +11151,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -10556,7 +11163,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -10569,7 +11176,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -10583,8 +11190,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -10618,8 +11225,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -10645,8 +11252,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -10701,7 +11308,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -10729,7 +11336,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -10798,7 +11405,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -10860,8 +11467,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -11079,7 +11686,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -11137,7 +11744,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -11154,7 +11761,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -11224,7 +11831,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -11257,7 +11864,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -11292,7 +11899,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -11335,7 +11942,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -11347,9 +11954,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -11372,8 +11979,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -11385,7 +11992,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -11400,8 +12007,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -11440,7 +12047,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -11454,7 +12061,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -11466,7 +12073,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -11601,9 +12208,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -13322,6 +13929,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL + #define R_BUS_B_BASE 0x40003000UL #define R_SSI0_BASE 0x4009D000UL #define R_SSI1_BASE 0x4009D100UL #define R_SYSTEM_BASE 0x4001E000UL @@ -13351,7 +13959,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) - #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + +/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ #define R_CAC ((R_CAC_Type *) R_CAC_BASE) #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) @@ -13434,6 +14043,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) @@ -13780,6 +14390,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -13842,6 +14460,89 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ERRRW ========================================================= */ + #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFADD ========================================================= */ + #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TZFERRRW ======================================================== */ + #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PIPE_TR ================ */ /* =========================================================================================================================== */ @@ -15126,8 +15827,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ /* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DEBUG ================ */ @@ -16755,6 +17458,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -16806,6 +17511,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -16820,6 +17527,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -18079,6 +18794,121 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ +/* =========================================================================================================================== */ +/* ================ R_BUS_B ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== BUSSCNTFHBIU ====================================================== */ + #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTFLBIU ====================================================== */ + #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTS0BIU ====================================================== */ + #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTPSBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTPLBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTPHBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTEQBIU ====================================================== */ + #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTEOBIU ====================================================== */ + #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTECBIU ====================================================== */ + #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ====================================================== BUS1ERRSTAT ====================================================== */ + #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS2ERRSTAT ====================================================== */ + #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS3ERRSTAT ====================================================== */ + #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS4ERRSTAT ====================================================== */ + #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS1ERRCLR ======================================================= */ + #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS2ERRCLR ======================================================= */ + #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS3ERRCLR ======================================================= */ + #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS4ERRCLR ======================================================= */ + #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ==================================================== DMACDTCERRSTAT ===================================================== */ + #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ===================================================== DMACDTCERRCLR ===================================================== */ + #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ /* =========================================================================================================================== */ @@ -18785,6 +19615,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -18823,6 +19659,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -18830,6 +19680,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h index 1f1ac34b0..b7a284d06 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M1AD.h @@ -18,9 +18,6 @@ * @file ./out/R7FA6M1AD.h * @brief CMSIS HeaderFile * @version 1.2 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:58:46 - * from File './out/R7FA6M1AD.svd', */ /** @addtogroup Renesas @@ -781,6 +778,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -3688,12 +3704,19 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for * D/A and A/D synchronous conversions. Set bit [1] to 1 to * select unit 1 as the target synchronous unit for the MCU. * When setting the DAADSCR.DAADST bit to 1 for synchronous @@ -3701,7 +3724,7 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure * advance. Only set the DAADUSR register while the ADCSR.ADST * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit * is set to 0. */ - uint8_t : 1; + uint8_t : 6; } DAADUSR_b; }; __IM uint8_t RESERVED3; @@ -6537,7 +6560,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -6568,10 +6592,17 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -6579,7 +6610,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -6911,10 +6943,14 @@ typedef struct /*!< (@ 0x40040000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -10070,24 +10106,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -10149,32 +10213,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -10188,8 +10296,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -10204,7 +10312,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -10234,7 +10342,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -10277,7 +10385,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -10315,7 +10423,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -10327,7 +10435,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -10340,7 +10448,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -10354,8 +10462,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -10389,8 +10497,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -10416,8 +10524,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -10472,7 +10580,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -10500,7 +10608,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -10569,7 +10677,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -10631,8 +10739,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -10850,7 +10958,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -10908,7 +11016,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -10925,7 +11033,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -10995,7 +11103,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -11028,7 +11136,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -11063,7 +11171,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -11106,7 +11214,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -11118,9 +11226,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -11143,8 +11251,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -11156,7 +11264,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -11171,8 +11279,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -11211,7 +11319,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -11225,7 +11333,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -11237,7 +11345,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -11372,9 +11480,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -14157,6 +14265,14 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -15488,8 +15604,10 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ /* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DEBUG ================ */ @@ -16953,6 +17071,8 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -17004,6 +17124,8 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -17018,6 +17140,14 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -19049,6 +19179,12 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -19087,6 +19223,20 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -19094,6 +19244,13 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h index 05928aa89..8f65274b2 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M2AF.h @@ -18,9 +18,6 @@ * @file ./out/R7FA6M2AF.h * @brief CMSIS HeaderFile * @version 1.2 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:59:02 - * from File './out/R7FA6M2AF.svd', */ /** @addtogroup Renesas @@ -781,6 +778,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -3688,12 +3704,19 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for * D/A and A/D synchronous conversions. Set bit [1] to 1 to * select unit 1 as the target synchronous unit for the MCU. * When setting the DAADSCR.DAADST bit to 1 for synchronous @@ -3701,7 +3724,7 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure * advance. Only set the DAADUSR register while the ADCSR.ADST * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit * is set to 0. */ - uint8_t : 1; + uint8_t : 6; } DAADUSR_b; }; __IM uint8_t RESERVED3; @@ -8402,7 +8425,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -8433,10 +8457,17 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -8444,7 +8475,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -8892,10 +8924,14 @@ typedef struct /*!< (@ 0x40040000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12051,24 +12087,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -12130,32 +12194,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -12169,8 +12277,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -12185,7 +12293,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -12215,7 +12323,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -12258,7 +12366,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -12296,7 +12404,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -12308,7 +12416,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -12321,7 +12429,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -12335,8 +12443,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -12370,8 +12478,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -12397,8 +12505,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -12453,7 +12561,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -12481,7 +12589,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -12550,7 +12658,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -12612,8 +12720,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -12831,7 +12939,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -12889,7 +12997,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -12906,7 +13014,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -12976,7 +13084,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -13009,7 +13117,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -13044,7 +13152,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -13087,7 +13195,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -13099,9 +13207,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -13124,8 +13232,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -13137,7 +13245,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -13152,8 +13260,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -13192,7 +13300,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -13206,7 +13314,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -13218,7 +13326,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -13353,9 +13461,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -16148,6 +16256,14 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -17479,8 +17595,10 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ /* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DEBUG ================ */ @@ -19869,6 +19987,8 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -19920,6 +20040,8 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -19934,6 +20056,14 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -22033,6 +22163,12 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -22071,6 +22207,20 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -22078,6 +22228,13 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h index 0e3094405..a3866a8e2 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M3AH.h @@ -18,9 +18,6 @@ * @file ./out/R7FA6M3AH.h * @brief CMSIS HeaderFile * @version 1.2 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:59:21 - * from File './out/R7FA6M3AH.svd', */ /** @addtogroup Renesas @@ -1691,6 +1688,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -4598,12 +4614,19 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for * D/A and A/D synchronous conversions. Set bit [1] to 1 to * select unit 1 as the target synchronous unit for the MCU. * When setting the DAADSCR.DAADST bit to 1 for synchronous @@ -4611,7 +4634,7 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure * advance. Only set the DAADUSR register while the ADCSR.ADST * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit * is set to 0. */ - uint8_t : 1; + uint8_t : 6; } DAADUSR_b; }; __IM uint8_t RESERVED3; @@ -11060,7 +11083,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -11091,10 +11115,17 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -11102,7 +11133,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -11550,10 +11582,14 @@ typedef struct /*!< (@ 0x40040000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -14709,24 +14745,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -14788,32 +14852,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -14827,8 +14935,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -14843,7 +14951,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -14873,7 +14981,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -14916,7 +15024,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -14954,7 +15062,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -14966,7 +15074,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -14979,7 +15087,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -14993,8 +15101,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -15028,8 +15136,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -15055,8 +15163,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -15111,7 +15219,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -15139,7 +15247,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -15208,7 +15316,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -15270,8 +15378,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -15489,7 +15597,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -15547,7 +15655,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -15564,7 +15672,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -15634,7 +15742,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -15667,7 +15775,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -15702,7 +15810,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -15745,7 +15853,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -15757,9 +15865,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -15782,8 +15890,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -15795,7 +15903,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -15810,8 +15918,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -15850,7 +15958,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -15864,7 +15972,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -15876,7 +15984,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -16011,9 +16119,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -19172,6 +19280,14 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -20503,8 +20619,10 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ /* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DEBUG ================ */ @@ -23504,6 +23622,8 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -23555,6 +23675,8 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -23569,6 +23691,14 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -25668,6 +25798,12 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -25706,6 +25842,20 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -25713,6 +25863,13 @@ typedef struct /*!< (@ 0x40060000) R_USB_HS0 Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h index d9958b474..6a90deaa6 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M4AF.h @@ -22,9 +22,6 @@ * @file ./out/R7FA6M4AF.h * @brief CMSIS HeaderFile * @version 1.20.00 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:59:42 - * from File './out/R7FA6M4AF.svd', */ /** @addtogroup Renesas Electronics Corporation @@ -760,6 +757,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -926,6 +942,179 @@ typedef struct __IM uint8_t RESERVED5[3]; } R_RTC_CP_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_BUS_B_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 7; + } ERRRW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, + * It stores an error address. */ + } TZFADD_b; + }; + + union + { + __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the + * time of the error */ + uint8_t : 7; + } TZFERRRW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ + /** * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) */ @@ -3812,12 +4001,19 @@ typedef struct /*!< (@ 0x40171000) R_DAC Structure union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for * D/A and A/D synchronous conversions. Set bit [1] to 1 to * select unit 1 as the target synchronous unit for the MCU. * When setting the DAADSCR.DAADST bit to 1 for synchronous @@ -3825,7 +4021,7 @@ typedef struct /*!< (@ 0x40171000) R_DAC Structure * advance. Only set the DAADUSR register while the ADCSR.ADST * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit * is set to 0. */ - uint8_t : 1; + uint8_t : 6; } DAADUSR_b; }; __IM uint8_t RESERVED3; @@ -7219,7 +7415,8 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -7250,10 +7447,17 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -7261,7 +7465,8 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -7593,10 +7798,14 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -9982,6 +10191,332 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure }; } R_SRAM_Type; /*!< Size = 217 (0xd9) */ +/* =========================================================================================================================== */ +/* ================ R_BUS_B ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS_B) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ +{ + __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[543]; + + union + { + __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTFHBIU_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTFLBIU_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTS0BIU_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPSBIU_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPLBIU_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPHBIU_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[2]; + + union + { + __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTEQBIU_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTEOBIU_b; + }; + __IM uint16_t RESERVED14; + + union + { + __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTECBIU_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[429]; + __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED17[48]; + __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IM uint32_t RESERVED18[48]; + + union + { + __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS1ERRSTAT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + __IM uint32_t RESERVED21; + + union + { + __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS1ERRCLR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24; + + union + { + __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS2ERRSTAT_b; + }; + __IM uint8_t RESERVED25; + __IM uint16_t RESERVED26; + __IM uint32_t RESERVED27; + + union + { + __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS2ERRCLR_b; + }; + __IM uint8_t RESERVED28; + __IM uint16_t RESERVED29; + __IM uint32_t RESERVED30; + + union + { + __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS3ERRSTAT_b; + }; + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + + union + { + __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } DMACDTCERRSTAT_b; + }; + __IM uint8_t RESERVED33; + __IM uint16_t RESERVED34; + + union + { + __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS3ERRCLR_b; + }; + __IM uint8_t RESERVED35; + __IM uint16_t RESERVED36; + + union + { + __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } DMACDTCERRCLR_b; + }; + __IM uint8_t RESERVED37; + __IM uint16_t RESERVED38; + + union + { + __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS4ERRSTAT_b; + }; + __IM uint8_t RESERVED39; + __IM uint16_t RESERVED40; + __IM uint32_t RESERVED41; + + union + { + __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS4ERRCLR_b; + }; + __IM uint8_t RESERVED42; + __IM uint16_t RESERVED43; +} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ + /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ /* =========================================================================================================================== */ @@ -10633,24 +11168,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -10712,32 +11275,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; + }; + + union + { + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -10751,8 +11358,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -10767,7 +11374,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -10797,7 +11404,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -10840,7 +11447,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -10878,7 +11485,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -10890,7 +11497,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -10903,7 +11510,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -10917,8 +11524,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -10952,8 +11559,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -10979,8 +11586,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -11035,7 +11642,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -11063,7 +11670,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -11132,7 +11739,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -11194,8 +11801,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -11413,7 +12020,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -11471,7 +12078,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -11488,7 +12095,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -11558,7 +12165,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -11591,7 +12198,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -11626,7 +12233,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -11669,7 +12276,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -11681,9 +12288,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -11706,8 +12313,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -11719,7 +12326,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -11734,8 +12341,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -11774,7 +12381,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -11788,7 +12395,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -11800,7 +12407,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -11935,9 +12542,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -15016,6 +15623,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL + #define R_BUS_B_BASE 0x40003000UL #define R_SSI0_BASE 0x4009D000UL #define R_SSI1_BASE 0x4009D100UL #define R_SYSTEM_BASE 0x4001E000UL @@ -15049,7 +15657,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) - #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + +/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ #define R_CAC ((R_CAC_Type *) R_CAC_BASE) #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) @@ -15134,6 +15743,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) @@ -15484,6 +16094,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -15546,6 +16164,89 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ERRRW ========================================================= */ + #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFADD ========================================================= */ + #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TZFERRRW ======================================================== */ + #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PIPE_TR ================ */ /* =========================================================================================================================== */ @@ -16947,8 +17648,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ /* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DEBUG ================ */ @@ -18616,6 +19319,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -18667,6 +19372,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -18681,6 +19388,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -19940,6 +20655,121 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ +/* =========================================================================================================================== */ +/* ================ R_BUS_B ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== BUSSCNTFHBIU ====================================================== */ + #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTFLBIU ====================================================== */ + #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTS0BIU ====================================================== */ + #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTPSBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTPLBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTPHBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTEQBIU ====================================================== */ + #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTEOBIU ====================================================== */ + #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTECBIU ====================================================== */ + #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ====================================================== BUS1ERRSTAT ====================================================== */ + #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS2ERRSTAT ====================================================== */ + #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS3ERRSTAT ====================================================== */ + #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS4ERRSTAT ====================================================== */ + #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS1ERRCLR ======================================================= */ + #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS2ERRCLR ======================================================= */ + #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS3ERRCLR ======================================================= */ + #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS4ERRCLR ======================================================= */ + #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ==================================================== DMACDTCERRSTAT ===================================================== */ + #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ===================================================== DMACDTCERRCLR ===================================================== */ + #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ /* =========================================================================================================================== */ @@ -20646,6 +21476,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -20684,6 +21520,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -20691,6 +21541,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h index 1046bffa6..e1a36a912 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6M5BH.h @@ -22,9 +22,6 @@ * @file ./out/R7FA6M5BH.h * @brief CMSIS HeaderFile * @version 1.10.08 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:59:59 - * from File './out/R7FA6M5BH.svd', */ /** @addtogroup Renesas Electronics Corporation @@ -464,65 +461,6 @@ typedef struct __IM uint16_t RESERVED; } R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_CAN0_MB [MB] (Mailbox) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ - - struct - { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 1; - __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ - __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ - } ID_b; - }; - - union - { - __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ - - struct - { - __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ - uint16_t : 12; - } DL_b; - }; - - union - { - __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ - - struct - { - __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN - * message data. Transmission or reception starts from DATA0. - * The bit order on the CAN bus is MSB-first, and transmission - * or reception starts from bit 7 */ - } D_b[8]; - }; - - union - { - __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ - - struct - { - __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter - * value of the time stamp when received messages are stored - * in the mailbox. */ - __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter - * value of the time stamp when received messages are stored - * in the mailbox. */ - } TS_b; - }; -} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ - /** * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) */ @@ -1304,6 +1242,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -1470,6 +1427,179 @@ typedef struct __IM uint8_t RESERVED5[3]; } R_RTC_CP_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_BUS_B_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ + + struct + { + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; + }; + + union + { + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ + + struct + { + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; + }; + + union + { + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ + + struct + { + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; + }; + __IM uint32_t RESERVED1; +} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_CSb [CSb] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; + + union + { + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ + + struct + { + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; + }; + __IM uint16_t RESERVED1[3]; + + union + { + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ + + struct + { + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; + }; + __IM uint16_t RESERVED2[2]; +} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ + + struct + { + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; + }; + + union + { + __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ + + struct + { + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 7; + } ERRRW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) + */ +typedef struct +{ + union + { + __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ + + struct + { + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, + * It stores an error address. */ + } TZFADD_b; + }; + + union + { + __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ + + struct + { + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the + * time of the error */ + uint8_t : 7; + } TZFERRRW_b; + }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ + /** * @brief R_USB_FS0_PIPE_TR [PIPE_TR] (Pipe Transaction Counter Registers) */ @@ -3419,539 +3549,72 @@ typedef struct /*!< (@ 0x40083600) R_CAC Structure } R_CAC_Type; /*!< Size = 12 (0xc) */ /* =========================================================================================================================== */ -/* ================ R_CAN0 ================ */ +/* ================ R_CANFD ================ */ /* =========================================================================================================================== */ /** - * @brief Controller Area Network (CAN) Module (R_CAN0) + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD) */ -typedef struct /*!< (@ 0x400A8000) R_CAN0 Structure */ +typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */ { - __IM uint32_t RESERVED[128]; - __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ + __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED[25]; union { - __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ struct { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 3; - } MKR_b[8]; + __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ + __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ + __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ + __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ + __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ + __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ + uint32_t : 2; + __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ + __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ + __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ + __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ + } CFDGCFG_b; }; union { - __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ struct { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 1; - __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ - __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ - } FIDCR_b[2]; - }; - - union - { - __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ - - struct - { - __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ - __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ - __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ - __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ - __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ - __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ - __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ - __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ - __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ - __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ - __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ - __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ - __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ - __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ - __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ - __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ - __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ - __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ - __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ - __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ - __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ - __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ - __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ - __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ - __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ - __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ - __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ - __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ - __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ - __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ - __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ - __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ - } MKIVLR_b; + __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ + __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ + uint32_t : 5; + __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ + __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ + __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ + __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ + uint32_t : 2; + __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */ + __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */ + __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ + __IOM uint32_t TSWR : 1; /*!< [17..17] Timestamp Write */ + uint32_t : 14; + } CFDGCTR_b; }; union { - union - { - __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ - - struct - { - __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ - __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ - __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ - __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ - __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ - __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ - __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ - __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ - __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ - __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ - __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ - __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ - __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ - __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ - __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ - __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ - __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ - __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ - __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ - __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ - __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ - __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ - __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ - __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ - __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ - __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ - __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ - __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ - __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ - __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ - __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ - __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ - } MIER_b; - }; + __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ - union + struct { - __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox - * Mode */ - - struct - { - __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ - __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ - __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ - __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ - __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ - __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ - __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ - __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ - __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ - __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ - __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ - __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ - __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ - __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ - __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ - __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ - __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ - __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ - __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ - __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ - __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ - __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ - __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ - __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ - __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ - __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ - uint32_t : 2; - __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ - __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ - uint32_t : 2; - } MIER_FIFO_b; - }; - }; - __IM uint32_t RESERVED1[252]; - - union - { - union - { - __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ - - struct - { - __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ - __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox - * setting enabled) */ - __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting - * enabled) */ - uint8_t : 1; - __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ - uint8_t : 1; - __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ - __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ - } MCTL_TX_b[32]; - }; - - union - { - __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ - - struct - { - __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ - __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting - * enabled) */ - __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ - uint8_t : 1; - __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ - uint8_t : 1; - __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ - __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ - } MCTL_RX_b[32]; - }; - }; - - union - { - __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ - - struct - { - __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ - __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ - __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ - __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ - __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ - __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ - __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ - __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ - __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ - __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ - uint16_t : 2; - } CTLR_b; - }; - - union - { - __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ - - struct - { - __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ - __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ - __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ - __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ - __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ - __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ - __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ - __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ - __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ - __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ - __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ - __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ - __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ - __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ - __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ - uint16_t : 1; - } STR_b; - }; - - union - { - __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ - - struct - { - __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ - uint32_t : 7; - __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ - uint32_t : 1; - __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ - uint32_t : 2; - __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the - * frequency of the CAN communication clock (fCANCLK). */ - uint32_t : 2; - __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ - } BCR_b; - }; - - union - { - __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ - - struct - { - __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ - __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ - __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ - __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ - __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ - __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ - } RFCR_b; - }; - - union - { - __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ - - struct - { - __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented - * by writing FFh to RFPCR. */ - } RFPCR_b; - }; - - union - { - __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ - - struct - { - __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ - __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ - uint8_t : 2; - __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ - __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ - } TFCR_b; - }; - - union - { - __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ - - struct - { - __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented - * by writing FFh to TFPCR. */ - } TFPCR_b; - }; - - union - { - __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ - - struct - { - __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ - __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ - __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ - __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ - __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ - __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ - __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ - __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ - } EIER_b; - }; - - union - { - __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ - - struct - { - __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ - __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ - __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ - __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ - __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ - __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ - __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ - __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ - } EIFR_b; - }; - - union - { - __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ - - struct - { - __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements - * the counter value according to the error status of the - * CAN module during reception. */ - } RECR_b; - }; - - union - { - __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ - - struct - { - __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements - * the counter value according to the error status of the - * CAN module during transmission. */ - } TECR_b; - }; - - union - { - __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ - - struct - { - __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ - __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ - __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ - __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ - __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ - __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ - __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ - __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ - } ECSR_b; - }; - - union - { - __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ - - struct - { - __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel - * number is output to MSSR. */ - } CSSR_b; - }; - - union - { - __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ - - struct - { - __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output - * the smallest mailbox number that is searched in each mode - * of MSMR. */ - uint8_t : 2; - __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ - } MSSR_b; - }; - - union - { - __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ - - struct - { - __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ - uint8_t : 6; - } MSMR_b; - }; - - union - { - __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ - - struct - { - __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ - } TSR_b; - }; - - union - { - __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ - - struct - { - __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, - * the value converted for data table search can be read. */ - } AFSR_b; - }; - - union - { - __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ - - struct - { - __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ - __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ - uint8_t : 5; - } TCR_b; - }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ - -/* =========================================================================================================================== */ -/* ================ R_CANFD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD) - */ - -typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */ -{ - __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */ - __IM uint32_t RESERVED[25]; - - union - { - __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ - - struct - { - __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ - __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ - __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ - __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ - __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ - __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ - uint32_t : 2; - __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ - __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ - __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ - __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ - } CFDGCFG_b; - }; - - union - { - __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ - - struct - { - __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ - __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ - uint32_t : 5; - __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ - __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ - __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ - __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ - uint32_t : 2; - __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */ - __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */ - __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ - __IOM uint32_t TSWR : 1; /*!< [17..17] Timestamp Write */ - uint32_t : 14; - } CFDGCTR_b; - }; - - union - { - __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ - - struct - { - __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ - __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ - __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ - __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ - uint32_t : 28; - } CFDGSTS_b; + __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ + __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ + __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ + __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ + uint32_t : 28; + } CFDGSTS_b; }; union @@ -5473,12 +5136,19 @@ typedef struct /*!< (@ 0x40171000) R_DAC Structure union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for * D/A and A/D synchronous conversions. Set bit [1] to 1 to * select unit 1 as the target synchronous unit for the MCU. * When setting the DAADSCR.DAADST bit to 1 for synchronous @@ -5486,7 +5156,7 @@ typedef struct /*!< (@ 0x40171000) R_DAC Structure * advance. Only set the DAADUSR register while the ADCSR.ADST * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit * is set to 0. */ - uint8_t : 1; + uint8_t : 6; } DAADUSR_b; }; __IM uint8_t RESERVED3; @@ -10017,7 +9687,8 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -10048,10 +9719,17 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -10059,7 +9737,8 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -10391,10 +10070,14 @@ typedef struct /*!< (@ 0x40080000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40080800) R_PFS Structure */ +typedef struct /*!< (@ 0x40080800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -12578,207 +12261,533 @@ typedef struct /*!< (@ 0x4011A000) R_SPI0 Structure union { - __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + __IOM uint16_t SPCMD[8]; /*!< (@ 0x00000010) SPI Command Register [0..7] */ + + struct + { + __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ + __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ + __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ + __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ + __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ + __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ + __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ + __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ + __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ + __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ + } SPCMD_b[8]; + }; + + union + { + __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + + struct + { + __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ + __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ + uint8_t : 6; + } SPDCR2_b; + }; + + union + { + __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + + struct + { + __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ + __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ + uint8_t : 2; + __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ + uint8_t : 3; + } SPCR3_b; + }; + __IM uint16_t RESERVED; + __IM uint32_t RESERVED1[6]; + __IM uint16_t RESERVED2; + + union + { + __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + + struct + { + uint16_t : 4; + __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ + uint16_t : 3; + __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ + uint16_t : 1; + __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ + } SPPR_b; + }; +} R_SPI0_Type; /*!< Size = 64 (0x40) */ + +/* =========================================================================================================================== */ +/* ================ R_SRAM ================ */ +/* =========================================================================================================================== */ + +/** + * @brief SRAM (R_SRAM) + */ + +typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ +{ + union + { + __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } PARIOAD_b; + }; + __IM uint8_t RESERVED[3]; + + union + { + __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + + struct + { + __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR_b; + }; + __IM uint8_t RESERVED1[3]; + __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ + __IM uint8_t RESERVED2[3]; + + union + { + __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + + struct + { + __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } SRAMPRCR2_b; + }; + __IM uint8_t RESERVED3[179]; + + union + { + __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + + struct + { + __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ + uint8_t : 6; + } ECCMODE_b; + }; + + union + { + __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ + uint8_t : 7; + } ECC2STS_b; + }; + + union + { + __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + + struct + { + __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ + uint8_t : 7; + } ECC1STSEN_b; + }; + + union + { + __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + + struct + { + __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ + uint8_t : 7; + } ECC1STS_b; + }; + + union + { + __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + + struct + { + __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR_b; + }; + __IM uint8_t RESERVED4[11]; + + union + { + __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + + struct + { + __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ + __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ + } ECCPRCR2_b; + }; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS_B ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS_B) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ +{ + __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[543]; + + union + { + __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTFHBIU_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTFLBIU_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTS0BIU_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPSBIU_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ struct { - __IOM uint16_t CPHA : 1; /*!< [0..0] RSPCK Phase Setting */ - __IOM uint16_t CPOL : 1; /*!< [1..1] RSPCK Polarity Setting */ - __IOM uint16_t BRDV : 2; /*!< [3..2] Bit Rate Division Setting */ - __IOM uint16_t SSLA : 3; /*!< [6..4] SSL Signal Assertion Setting */ - __IOM uint16_t SSLKP : 1; /*!< [7..7] SSL Signal Level Keeping */ - __IOM uint16_t SPB : 4; /*!< [11..8] SPI Data Length Setting */ - __IOM uint16_t LSBF : 1; /*!< [12..12] SPI LSB First */ - __IOM uint16_t SPNDEN : 1; /*!< [13..13] SPI Next-Access Delay Enable */ - __IOM uint16_t SLNDEN : 1; /*!< [14..14] SSL Negation Delay Setting Enable */ - __IOM uint16_t SCKDEN : 1; /*!< [15..15] RSPCK Delay Setting Enable */ - } SPCMD_b[8]; + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPLBIU_b; }; + __IM uint16_t RESERVED10; union { - __IOM uint8_t SPDCR2; /*!< (@ 0x00000020) SPI Data Control Register 2 */ + __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ struct { - __IOM uint8_t BYSW : 1; /*!< [0..0] Byte Swap Operating Mode Select */ - __IOM uint8_t SINV : 1; /*!< [1..1] Serial data invert bit */ - uint8_t : 6; - } SPDCR2_b; + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPHBIU_b; }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[2]; union { - __IOM uint8_t SPCR3; /*!< (@ 0x00000021) RSPI Control Register 3 */ + __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ struct { - __IOM uint8_t ETXMD : 1; /*!< [0..0] Extended Communication Mode Select */ - __IOM uint8_t BFDS : 1; /*!< [1..1] Between Burst Transfer Frames Delay Select */ - uint8_t : 2; - __IOM uint8_t CENDIE : 1; /*!< [4..4] RSPI Communication End Interrupt Enable */ - uint8_t : 3; - } SPCR3_b; + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTEQBIU_b; }; - __IM uint16_t RESERVED; - __IM uint32_t RESERVED1[6]; - __IM uint16_t RESERVED2; + __IM uint16_t RESERVED13; union { - __IOM uint16_t SPPR; /*!< (@ 0x0000003E) RSPI Parameter Read Register */ + __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ struct { - uint16_t : 4; - __IOM uint16_t BUFWID : 1; /*!< [4..4] Buffer Width check */ - uint16_t : 3; - __IOM uint16_t BUFNUM : 3; /*!< [10..8] Buffer Number check */ - uint16_t : 1; - __IOM uint16_t CMDNUM : 4; /*!< [15..12] Command Number check */ - } SPPR_b; + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTEOBIU_b; }; -} R_SPI0_Type; /*!< Size = 64 (0x40) */ - -/* =========================================================================================================================== */ -/* ================ R_SRAM ================ */ -/* =========================================================================================================================== */ - -/** - * @brief SRAM (R_SRAM) - */ + __IM uint16_t RESERVED14; -typedef struct /*!< (@ 0x40002000) R_SRAM Structure */ -{ union { - __IOM uint8_t PARIOAD; /*!< (@ 0x00000000) SRAM Parity Error Operation After Detection Register */ + __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } PARIOAD_b; + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTECBIU_b; }; - __IM uint8_t RESERVED[3]; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[429]; + __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED17[48]; + __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IM uint32_t RESERVED18[48]; union { - __IOM uint8_t SRAMPRCR; /*!< (@ 0x00000004) SRAM Protection Register */ + __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ struct { - __IOM uint8_t SRAMPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR_b; + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS1ERRSTAT_b; }; - __IM uint8_t RESERVED1[3]; - __IOM uint8_t SRAMWTSC; /*!< (@ 0x00000008) RAM Wait State Control Register */ - __IM uint8_t RESERVED2[3]; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + __IM uint32_t RESERVED21; union { - __IOM uint8_t SRAMPRCR2; /*!< (@ 0x0000000C) SRAM Protection Register 2 */ + __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ struct { - __IOM uint8_t SRAMPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } SRAMPRCR2_b; + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS1ERRCLR_b; }; - __IM uint8_t RESERVED3[179]; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24; union { - __IOM uint8_t ECCMODE; /*!< (@ 0x000000C0) ECC Operating Mode Control Register */ + __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ struct { - __IOM uint8_t ECCMOD : 2; /*!< [1..0] ECC Operating Mode Select */ - uint8_t : 6; - } ECCMODE_b; + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS2ERRSTAT_b; }; + __IM uint8_t RESERVED25; + __IM uint16_t RESERVED26; + __IM uint32_t RESERVED27; union { - __IOM uint8_t ECC2STS; /*!< (@ 0x000000C1) ECC 2-Bit Error Status Register */ + __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ struct { - __IOM uint8_t ECC2ERR : 1; /*!< [0..0] ECC 2-Bit Error Status */ - uint8_t : 7; - } ECC2STS_b; + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS2ERRCLR_b; }; + __IM uint8_t RESERVED28; + __IM uint16_t RESERVED29; + __IM uint32_t RESERVED30; union { - __IOM uint8_t ECC1STSEN; /*!< (@ 0x000000C2) ECC 1-Bit Error Information Update Enable Register */ + __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ struct { - __IOM uint8_t E1STSEN : 1; /*!< [0..0] ECC 1-Bit Error Information Update Enable */ - uint8_t : 7; - } ECC1STSEN_b; + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS3ERRSTAT_b; }; + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; union { - __IOM uint8_t ECC1STS; /*!< (@ 0x000000C3) ECC 1-Bit Error Status Register */ + __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ struct { - __IOM uint8_t ECC1ERR : 1; /*!< [0..0] ECC 1-Bit Error Status */ - uint8_t : 7; - } ECC1STS_b; + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } DMACDTCERRSTAT_b; }; + __IM uint8_t RESERVED33; + __IM uint16_t RESERVED34; union { - __IOM uint8_t ECCPRCR; /*!< (@ 0x000000C4) ECC Protection Register */ + __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ struct { - __IOM uint8_t ECCPRCR : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR_b; + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS3ERRCLR_b; }; - __IM uint8_t RESERVED4[11]; + __IM uint8_t RESERVED35; + __IM uint16_t RESERVED36; union { - __IOM uint8_t ECCPRCR2; /*!< (@ 0x000000D0) ECC Protection Register 2 */ + __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ struct { - __IOM uint8_t ECCPRCR2 : 1; /*!< [0..0] Register Write Control */ - __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ - } ECCPRCR2_b; + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } DMACDTCERRCLR_b; }; - __IM uint8_t RESERVED5[3]; + __IM uint8_t RESERVED37; + __IM uint16_t RESERVED38; union { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ struct { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS4ERRSTAT_b; }; - __IM uint8_t RESERVED6[3]; + __IM uint8_t RESERVED39; + __IM uint16_t RESERVED40; + __IM uint32_t RESERVED41; union { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS4ERRCLR_b; }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + __IM uint8_t RESERVED42; + __IM uint16_t RESERVED43; +} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ @@ -13431,24 +13440,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -13510,32 +13547,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -13549,8 +13630,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -13565,7 +13646,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -13595,7 +13676,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -13638,7 +13719,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -13676,7 +13757,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -13688,7 +13769,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -13701,7 +13782,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -13715,8 +13796,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -13750,8 +13831,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -13777,8 +13858,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -13833,7 +13914,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -13861,7 +13942,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -13930,7 +14011,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -13992,8 +14073,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -14211,7 +14292,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -14269,7 +14350,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -14286,7 +14367,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -14356,7 +14437,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -14389,7 +14470,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -14424,7 +14505,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -14467,7 +14548,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -14479,9 +14560,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -14504,8 +14585,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -14517,7 +14598,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -14532,8 +14613,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -14572,7 +14653,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -14586,7 +14667,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -14598,7 +14679,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -14733,9 +14814,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -18085,8 +18166,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGT5_BASE 0x400E8500UL #define R_BUS_BASE 0x40003000UL #define R_CAC_BASE 0x40083600UL - #define R_CAN0_BASE 0x400A8000UL - #define R_CAN1_BASE 0x400A9000UL #define R_CANFD_BASE 0x400B0000UL #define R_CRC_BASE 0x40108000UL #define R_CTSU_BASE 0x400D0000UL @@ -18171,6 +18250,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL + #define R_BUS_B_BASE 0x40003000UL #define R_SSI0_BASE 0x4009D000UL #define R_SSI1_BASE 0x4009D100UL #define R_SYSTEM_BASE 0x4001E000UL @@ -18205,10 +18285,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGT3 ((R_AGT0_Type *) R_AGT3_BASE) #define R_AGT4 ((R_AGT0_Type *) R_AGT4_BASE) #define R_AGT5 ((R_AGT0_Type *) R_AGT5_BASE) - #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + +/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ #define R_CAC ((R_CAC_Type *) R_CAC_BASE) - #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) - #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) #define R_CRC ((R_CRC_Type *) R_CRC_BASE) #define R_CTSU ((R_CTSU_Type *) R_CTSU_BASE) @@ -18293,6 +18372,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SSI0 ((R_SSI0_Type *) R_SSI0_BASE) #define R_SSI1 ((R_SSI0_Type *) R_SSI1_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) @@ -18490,31 +18570,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ -/* =========================================================================================================================== */ -/* ================ MB ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ - #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ - #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ - #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ - #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ - #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ - #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ - #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ -/* ========================================================== DL =========================================================== */ - #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ - #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ -/* =========================================================== D =========================================================== */ - #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ - #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ -/* ========================================================== TS =========================================================== */ - #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ - #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ - #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ - #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ - /* =========================================================================================================================== */ /* ================ CFDC ================ */ /* =========================================================================================================================== */ @@ -19019,6 +19074,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -19081,6 +19144,89 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_RTC_CP_RMON_MON1_Pos (0UL) /*!< MON1 (Bit 0) */ #define R_RTC_CP_RMON_MON1_Msk (0xfUL) /*!< MON1 (Bitfield-Mask: 0x0f) */ +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ERRRW ========================================================= */ + #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFADD ========================================================= */ + #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TZFERRRW ======================================================== */ + #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PIPE_TR ================ */ /* =========================================================================================================================== */ @@ -19908,408 +20054,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CAC_CACNTBR_CACNTBR_Pos (0UL) /*!< CACNTBR (Bit 0) */ #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ -/* =========================================================================================================================== */ -/* ================ R_CAN0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MKR ========================================================== */ - #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ - #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ - #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ - #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ -/* ========================================================= FIDCR ========================================================= */ - #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ - #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ - #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ - #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ - #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ - #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ - #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ - #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ -/* ======================================================== MKIVLR ========================================================= */ - #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ - #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ - #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ - #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ - #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ - #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ - #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ - #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ - #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ - #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ - #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ - #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ - #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ - #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ - #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ - #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ - #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ - #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ - #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ - #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ - #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ - #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ - #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ - #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ - #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ - #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ - #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ - #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ - #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ - #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ - #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ - #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ - #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ -/* ========================================================= MIER ========================================================== */ - #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ - #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ - #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ - #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ - #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ - #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ - #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ - #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ - #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ - #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ - #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ - #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ - #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ - #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ - #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ - #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ - #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ - #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ - #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ - #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ - #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ - #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ - #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ - #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ - #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ - #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ - #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ - #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ - #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ - #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ - #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ - #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ - #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ -/* ======================================================= MIER_FIFO ======================================================= */ - #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ - #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ - #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ - #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ - #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ - #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ - #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ - #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ - #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ - #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ - #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ - #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ - #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ - #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ - #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ - #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ - #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ - #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ - #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ - #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ - #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ - #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ - #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ - #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ - #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ - #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ - #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ - #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ - #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ -/* ======================================================== MCTL_TX ======================================================== */ - #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ - #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ - #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ - #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ - #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ - #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ - #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ -/* ======================================================== MCTL_RX ======================================================== */ - #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ - #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ - #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ - #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ - #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ - #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ - #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ -/* ========================================================= CTLR ========================================================== */ - #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ - #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ - #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ - #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ - #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ - #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ - #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ - #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ - #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ - #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ - #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ - #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ - #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ - #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ - #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ - #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ - #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ - #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ - #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ - #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ -/* ========================================================== STR ========================================================== */ - #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ - #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ - #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ - #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ - #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ - #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ - #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ - #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ - #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ - #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ - #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ - #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ - #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ - #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ - #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ - #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ -/* ========================================================== BCR ========================================================== */ - #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ - #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ - #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ - #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ - #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ - #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ - #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ - #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ - #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ - #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ -/* ========================================================= RFCR ========================================================== */ - #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ - #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ - #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ - #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ - #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ - #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ - #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ - #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ - #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ - #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ - #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ - #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ -/* ========================================================= RFPCR ========================================================= */ - #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ - #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ -/* ========================================================= TFCR ========================================================== */ - #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ - #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ - #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ - #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ - #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ - #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ - #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ - #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ -/* ========================================================= TFPCR ========================================================= */ - #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ - #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ -/* ========================================================= EIER ========================================================== */ - #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ - #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ - #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ - #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ - #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ - #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ - #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ - #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ - #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ -/* ========================================================= EIFR ========================================================== */ - #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ - #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ - #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ - #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ - #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ - #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ - #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ - #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ - #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ -/* ========================================================= RECR ========================================================== */ - #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ - #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ -/* ========================================================= TECR ========================================================== */ - #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ - #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ -/* ========================================================= ECSR ========================================================== */ - #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ - #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ - #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ - #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ - #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ - #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ - #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ - #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ - #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ - #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ - #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ - #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ - #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ - #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ - #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ - #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ -/* ========================================================= CSSR ========================================================== */ - #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ - #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ -/* ========================================================= MSSR ========================================================== */ - #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ - #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ - #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ - #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ -/* ========================================================= MSMR ========================================================== */ - #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ - #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ -/* ========================================================== TSR ========================================================== */ - #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ - #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ -/* ========================================================= AFSR ========================================================== */ - #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ - #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ -/* ========================================================== TCR ========================================================== */ - #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ - #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ - #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ - #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ - /* =========================================================================================================================== */ /* ================ R_CANFD ================ */ /* =========================================================================================================================== */ @@ -21096,8 +20840,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ /* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DEBUG ================ */ @@ -23396,6 +23142,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -23447,6 +23195,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -23461,6 +23211,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -24720,6 +24478,121 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ +/* =========================================================================================================================== */ +/* ================ R_BUS_B ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== BUSSCNTFHBIU ====================================================== */ + #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTFLBIU ====================================================== */ + #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTS0BIU ====================================================== */ + #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTPSBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTPLBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTPHBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTEQBIU ====================================================== */ + #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTEOBIU ====================================================== */ + #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTECBIU ====================================================== */ + #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ====================================================== BUS1ERRSTAT ====================================================== */ + #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS2ERRSTAT ====================================================== */ + #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS3ERRSTAT ====================================================== */ + #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS4ERRSTAT ====================================================== */ + #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS1ERRCLR ======================================================= */ + #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS2ERRCLR ======================================================= */ + #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS3ERRCLR ======================================================= */ + #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS4ERRCLR ======================================================= */ + #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ==================================================== DMACDTCERRSTAT ===================================================== */ + #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ===================================================== DMACDTCERRCLR ===================================================== */ + #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ R_SSI0 ================ */ /* =========================================================================================================================== */ @@ -25426,6 +25299,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -25464,6 +25343,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -25471,6 +25364,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h index dc5747ff5..e23d07904 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T1AD.h @@ -18,9 +18,6 @@ * @file ./out/R7FA6T1AD.h * @brief CMSIS HeaderFile * @version 1.0 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:60:21 - * from File './out/R7FA6T1AD.svd', */ /** @addtogroup Renesas @@ -781,6 +778,25 @@ typedef struct __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ } R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ +/** + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) + */ +typedef struct +{ + __IM uint8_t RESERVED[389]; + + union + { + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ + + struct + { + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; + }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + /** * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) */ @@ -3223,12 +3239,19 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for * D/A and A/D synchronous conversions. Set bit [1] to 1 to * select unit 1 as the target synchronous unit for the MCU. * When setting the DAADSCR.DAADST bit to 1 for synchronous @@ -3236,7 +3259,7 @@ typedef struct /*!< (@ 0x4005E000) R_DAC Structure * advance. Only set the DAADUSR register while the ADCSR.ADST * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit * is set to 0. */ - uint8_t : 1; + uint8_t : 6; } DAADUSR_b; }; __IM uint8_t RESERVED3; @@ -6072,7 +6095,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -6103,10 +6127,17 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -6114,7 +6145,8 @@ typedef struct /*!< (@ 0x40047000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -6446,10 +6478,14 @@ typedef struct /*!< (@ 0x40040000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x40040800) R_PFS Structure */ +typedef struct /*!< (@ 0x40040800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -8250,24 +8286,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -8329,32 +8393,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -8368,8 +8476,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -8384,7 +8492,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -8414,7 +8522,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -8457,7 +8565,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -8495,7 +8603,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -8507,7 +8615,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -8520,7 +8628,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -8534,8 +8642,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -8569,8 +8677,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -8596,8 +8704,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -8652,7 +8760,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -8680,7 +8788,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -8749,7 +8857,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -8811,8 +8919,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -9030,7 +9138,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -9088,7 +9196,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -9105,7 +9213,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -9175,7 +9283,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -9208,7 +9316,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -9243,7 +9351,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -9286,7 +9394,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -9298,9 +9406,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -9323,8 +9431,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -9336,7 +9444,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -9351,8 +9459,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -9391,7 +9499,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -9405,7 +9513,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -9417,7 +9525,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -9552,9 +9660,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -10265,6 +10373,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ @@ -11410,8 +11526,10 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ /* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DEBUG ================ */ @@ -12875,6 +12993,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -12926,6 +13046,8 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -12940,6 +13062,14 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -14362,6 +14492,12 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -14400,6 +14536,20 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -14407,6 +14557,13 @@ typedef struct /*!< (@ 0x40044200) R_WDT Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h index 6d024d9e1..78735ea4d 100644 --- a/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h +++ b/ra/fsp/src/bsp/cmsis/Device/RENESAS/Include/R7FA6T2BD.h @@ -22,9 +22,6 @@ * @file ./out/R7FA6T2BD.h * @brief CMSIS HeaderFile * @version 1.10.01 - * @date 11. October 2022 - * @note Generated by SVDConv V3.3.42 on Tuesday, 11.10.2022 18:60:30 - * from File './out/R7FA6T2BD.svd', */ /** @addtogroup Renesas Electronics Corporation @@ -464,65 +461,6 @@ typedef struct __IM uint16_t RESERVED; } R_BUS_BUSS_Type; /*!< Size = 4 (0x4) */ -/** - * @brief R_CAN0_MB [MB] (Mailbox) - */ -typedef struct -{ - union - { - __IOM uint32_t ID; /*!< (@ 0x00000000) Mailbox ID Register */ - - struct - { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 1; - __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ - __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ - } ID_b; - }; - - union - { - __IOM uint16_t DL; /*!< (@ 0x00000004) Mailbox DLC Register */ - - struct - { - __IOM uint16_t DLC : 4; /*!< [3..0] Data Length Code */ - uint16_t : 12; - } DL_b; - }; - - union - { - __IOM uint8_t D[8]; /*!< (@ 0x00000006) Mailbox Data Register */ - - struct - { - __IOM uint8_t DATA : 8; /*!< [7..0] DATA0 to DATA7 store the transmitted or received CAN - * message data. Transmission or reception starts from DATA0. - * The bit order on the CAN bus is MSB-first, and transmission - * or reception starts from bit 7 */ - } D_b[8]; - }; - - union - { - __IOM uint16_t TS; /*!< (@ 0x0000000E) Mailbox Timestamp Register */ - - struct - { - __IOM uint16_t TSL : 8; /*!< [7..0] Time Stamp Higher ByteBits TSL[7:0] store the counter - * value of the time stamp when received messages are stored - * in the mailbox. */ - __IOM uint16_t TSH : 8; /*!< [15..8] Time Stamp Lower ByteBits TSH[7:0] store the counter - * value of the time stamp when received messages are stored - * in the mailbox. */ - } TS_b; - }; -} R_CAN0_MB_Type; /*!< Size = 16 (0x10) */ - /** * @brief R_CANFD_CFDC [CFDC] (Channel Control/Status) */ @@ -569,9 +507,7 @@ typedef struct __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ - __IOM uint32_t TRWE : 1; /*!< [27..27] TEC/REC Write Enable */ - __IOM uint32_t TRH : 1; /*!< [28..28] TEC/REC Hold */ - __IOM uint32_t TRR : 1; /*!< [29..29] TEC/REC Reset */ + uint32_t : 3; __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ } CTR_b; @@ -660,14 +596,11 @@ typedef struct __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ uint32_t : 5; __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ - __IOM uint32_t GWEN : 1; /*!< [24..24] CAN2.0, CAN-FD <> CAN2.0, CAN-FD Multi Gateway Enable */ - __IOM uint32_t GWFDF : 1; /*!< [25..25] Gateway FDF configuration bit */ - __IOM uint32_t GWBRS : 1; /*!< [26..26] Gateway BRS configuration bit */ - uint32_t : 1; + uint32_t : 4; __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ - __IOM uint32_t CFDTE : 1; /*!< [31..31] CAN-FD frame Distinction enable */ + uint32_t : 1; } FDCFG_b; }; @@ -711,31 +644,7 @@ typedef struct uint32_t : 4; } FDCRC_b; }; - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t BLCT; /*!< (@ 0x00000018) Channel Bus load Control Register */ - - struct - { - __IOM uint32_t BLCE : 1; /*!< [0..0] BUS Load counter Enable */ - uint32_t : 7; - __OM uint32_t BLCLD : 1; /*!< [8..8] BUS Load counter load */ - uint32_t : 23; - } BLCT_b; - }; - - union - { - __IOM uint32_t BLSTS; /*!< (@ 0x0000001C) Channel Bus load Status Register */ - - struct - { - uint32_t : 3; - __IM uint32_t BLC : 29; /*!< [31..3] BUS Load counter Status */ - } BLSTS_b; - }; + __IM uint32_t RESERVED[3]; } R_CANFD_CFDC2_Type; /*!< Size = 32 (0x20) */ /** @@ -776,12 +685,7 @@ typedef struct struct { __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ - __IOM uint32_t GAFLSRD0 : 1; /*!< [4..4] Global Acceptance Filter List Select Routing destination - * 0 */ - __IOM uint32_t GAFLSRD1 : 1; /*!< [5..5] Global Acceptance Filter List Select Routing destination - * 1 */ - __IOM uint32_t GAFLSRD2 : 1; /*!< [6..6] Global Acceptance Filter List Select Routing destination - * 2 */ + uint32_t : 3; __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction * Pointer */ @@ -793,15 +697,15 @@ typedef struct union { - __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ struct { - __IOM uint32_t GAFLFDP : 14; /*!< [13..0] Global Acceptance Filter List FIFO Direction Pointer */ - uint32_t : 18; + __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ + uint32_t : 23; } P1_b; }; -} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ +} R_CANFD_CFDGAFL_Type; /*!< Size = 16 (0x10) */ /** * @brief R_CANFD_CFDTHL [CFDTHL] (Channel TX History List) @@ -816,8 +720,7 @@ typedef struct { __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ - uint32_t : 5; - __IM uint32_t TGW : 1; /*!< [15..15] Transmit Gateway Buffer indication */ + uint32_t : 6; __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ } ACC0_b; }; @@ -835,64 +738,6 @@ typedef struct }; } R_CANFD_CFDTHL_Type; /*!< Size = 8 (0x8) */ -/** - * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Registers) - */ -typedef struct -{ - union - { - __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ - - struct - { - __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ - __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ - } ID_b; - }; - - union - { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ - - struct - { - __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ - uint32_t : 12; - __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ - } PTR_b; - }; - - union - { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ - - struct - { - __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ - } FDSTS_b; - }; - - union - { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ - - struct - { - __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ - } DF_b[64]; - }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDRM_Type; /*!< Size = 128 (0x80) */ - /** * @brief R_CANFD_CFDRF [CFDRF] (RX FIFO Access Registers) */ @@ -948,8 +793,7 @@ typedef struct __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ } DF_b[64]; }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDRF_Type; /*!< Size = 128 (0x80) */ +} R_CANFD_CFDRF_Type; /*!< Size = 76 (0x4c) */ /** * @brief R_CANFD_CFDCF [CFDCF] (Common FIFO Access Registers) @@ -1006,8 +850,7 @@ typedef struct __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ } DF_b[64]; }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDCF_Type; /*!< Size = 128 (0x80) */ +} R_CANFD_CFDCF_Type; /*!< Size = 76 (0x4c) */ /** * @brief R_CANFD_CFDTM [CFDTM] (TX Message Buffer Access Registers) @@ -1064,4427 +907,2586 @@ typedef struct __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ } DF_b[64]; }; - __IM uint32_t RESERVED[13]; -} R_CANFD_CFDTM_Type; /*!< Size = 128 (0x80) */ +} R_CANFD_CFDTM_Type; /*!< Size = 76 (0x4c) */ /** - * @brief R_CANFDL_CFDC [CFDC] (Channel Control/Status) + * @brief R_CANFD_CFDRM_RM [RM] (RX Message Buffer Access Registers) */ typedef struct { union { - __IOM uint32_t NCFG; /*!< (@ 0x00000000) Channel Nominal Bitrate Configuration Register */ + __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ struct { - __IOM uint32_t NBRP : 10; /*!< [9..0] Channel Nominal Baud Rate Prescaler */ - __IOM uint32_t NSJW : 7; /*!< [16..10] Resynchronization Jump Width */ - __IOM uint32_t NTSEG1 : 8; /*!< [24..17] Timing Segment 1 */ - __IOM uint32_t NTSEG2 : 7; /*!< [31..25] Timing Segment 2 */ - } NCFG_b; + __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ + uint32_t : 1; + __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ + __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ + } ID_b; }; union { - __IOM uint32_t CTR; /*!< (@ 0x00000004) Channel Control Registers */ + __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ struct { - __IOM uint32_t CHMDC : 2; /*!< [1..0] Channel Mode Control */ - __IOM uint32_t CSLPR : 1; /*!< [2..2] Channel Sleep Request */ - __IOM uint32_t RTBO : 1; /*!< [3..3] Return from Bus-Off */ - uint32_t : 4; - __IOM uint32_t BEIE : 1; /*!< [8..8] Bus Error Interrupt Enable */ - __IOM uint32_t EWIE : 1; /*!< [9..9] Error Warning Interrupt Enable */ - __IOM uint32_t EPIE : 1; /*!< [10..10] Error Passive Interrupt Enable */ - __IOM uint32_t BOEIE : 1; /*!< [11..11] Bus-Off Entry Interrupt Enable */ - __IOM uint32_t BORIE : 1; /*!< [12..12] Bus-Off Recovery Interrupt Enable */ - __IOM uint32_t OLIE : 1; /*!< [13..13] Overload Interrupt Enable */ - __IOM uint32_t BLIE : 1; /*!< [14..14] Bus Lock Interrupt Enable */ - __IOM uint32_t ALIE : 1; /*!< [15..15] Arbitration Lost Interrupt Enable */ - __IOM uint32_t TAIE : 1; /*!< [16..16] Transmission abort Interrupt Enable */ - __IOM uint32_t EOCOIE : 1; /*!< [17..17] Error occurrence counter overflow Interrupt enable */ - __IOM uint32_t SOCOIE : 1; /*!< [18..18] Successful Occurrence Counter Overflow Interrupt enable */ - __IOM uint32_t TDCVFIE : 1; /*!< [19..19] Transceiver Delay Compensation Violation Interrupt - * enable */ - uint32_t : 1; - __IOM uint32_t BOM : 2; /*!< [22..21] Channel Bus-Off Mode */ - __IOM uint32_t ERRD : 1; /*!< [23..23] Channel Error Display */ - __IOM uint32_t CTME : 1; /*!< [24..24] Channel Test Mode Enable */ - __IOM uint32_t CTMS : 2; /*!< [26..25] Channel Test Mode Select */ - uint32_t : 3; - __IOM uint32_t CRCT : 1; /*!< [30..30] CRC Error Test */ - __IOM uint32_t ROM : 1; /*!< [31..31] Restricted Operation Mode */ - } CTR_b; + __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ + uint32_t : 12; + __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ + } PTR_b; }; union { - __IOM uint32_t STS; /*!< (@ 0x00000008) Channel Status Registers */ + __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ struct { - __IM uint32_t CRSTSTS : 1; /*!< [0..0] Channel RESET Status */ - __IM uint32_t CHLTSTS : 1; /*!< [1..1] Channel HALT Status */ - __IM uint32_t CSLPSTS : 1; /*!< [2..2] Channel SLEEP Status */ - __IM uint32_t EPSTS : 1; /*!< [3..3] Channel Error Passive Status */ - __IM uint32_t BOSTS : 1; /*!< [4..4] Channel Bus-Off Status */ - __IM uint32_t TRMSTS : 1; /*!< [5..5] Channel Transmit Status */ - __IM uint32_t RECSTS : 1; /*!< [6..6] Channel Receive Status */ - __IM uint32_t COMSTS : 1; /*!< [7..7] Channel Communication Status */ - __IOM uint32_t ESIF : 1; /*!< [8..8] Error State Indication Flag */ - uint32_t : 7; - __IM uint32_t REC : 8; /*!< [23..16] Reception Error Count */ - __IOM uint32_t TEC : 8; /*!< [31..24] Transmission Error Count */ - } STS_b; + __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ + __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ + __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ + uint32_t : 5; + __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ + uint32_t : 6; + __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ + } FDSTS_b; }; union { - __IOM uint32_t ERFL; /*!< (@ 0x0000000C) Channel Error Flag Registers */ + __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ struct { - __IOM uint32_t BEF : 1; /*!< [0..0] Bus Error Flag */ - __IOM uint32_t EWF : 1; /*!< [1..1] Error Warning Flag */ - __IOM uint32_t EPF : 1; /*!< [2..2] Error Passive Flag */ - __IOM uint32_t BOEF : 1; /*!< [3..3] Bus-Off Entry Flag */ - __IOM uint32_t BORF : 1; /*!< [4..4] Bus-Off Recovery Flag */ - __IOM uint32_t OVLF : 1; /*!< [5..5] Overload Flag */ - __IOM uint32_t BLF : 1; /*!< [6..6] Bus Lock Flag */ - __IOM uint32_t ALF : 1; /*!< [7..7] Arbitration Lost Flag */ - __IOM uint32_t SERR : 1; /*!< [8..8] Stuff Error */ - __IOM uint32_t FERR : 1; /*!< [9..9] Form Error */ - __IOM uint32_t AERR : 1; /*!< [10..10] Acknowledge Error */ - __IOM uint32_t CERR : 1; /*!< [11..11] CRC Error */ - __IOM uint32_t B1ERR : 1; /*!< [12..12] Bit 1 Error */ - __IOM uint32_t B0ERR : 1; /*!< [13..13] Bit 0 Error */ - __IOM uint32_t ADERR : 1; /*!< [14..14] Acknowledge Delimiter Error */ - uint32_t : 1; - __IM uint32_t CRCREG : 15; /*!< [30..16] CRC Register value */ - uint32_t : 1; - } ERFL_b; + __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ + } DF_b[64]; }; -} R_CANFDL_CFDC_Type; /*!< Size = 16 (0x10) */ +} R_CANFD_CFDRM_RM_Type; /*!< Size = 76 (0x4c) */ + +/** + * @brief R_CANFD_CFDRM [CFDRM] (RX Message Buffer Access Clusters) + */ +typedef struct +{ + __IOM R_CANFD_CFDRM_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ + __IM uint32_t RESERVED[104]; +} R_CANFD_CFDRM_Type; /*!< Size = 1024 (0x400) */ /** - * @brief R_CANFDL_CFDC2 [CFDC2] (Channel Configuration Registers) + * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) */ typedef struct { union { - __IOM uint32_t DCFG; /*!< (@ 0x00000000) Channel Data Bitrate Configuration Register */ + __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ struct { - __IOM uint32_t DBRP : 8; /*!< [7..0] Channel Data Baud Rate Prescaler */ - __IOM uint32_t DTSEG1 : 5; /*!< [12..8] Timing Segment 1 */ - uint32_t : 3; - __IOM uint32_t DTSEG2 : 4; /*!< [19..16] Timing Segment 2 */ - uint32_t : 4; - __IOM uint32_t DSJW : 4; /*!< [27..24] Resynchronization Jump Width */ - uint32_t : 4; - } DCFG_b; + __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ + uint8_t : 5; + __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ + __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ + } BY_b; }; + __IM uint8_t RESERVED; +} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ +/** + * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..29]) + */ +typedef struct +{ union { - __IOM uint32_t FDCFG; /*!< (@ 0x00000004) Channel CAN-FD Configuration Register */ + __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ struct { - __IOM uint32_t EOCCFG : 3; /*!< [2..0] Error Occurrence Counter Configuration */ - uint32_t : 5; - __IOM uint32_t TDCOC : 1; /*!< [8..8] Transceiver Delay Compensation Offset Configuration */ - __IOM uint32_t TDCE : 1; /*!< [9..9] Transceiver Delay Compensation Enable */ - __IOM uint32_t ESIC : 1; /*!< [10..10] Error State Indication Configuration */ - uint32_t : 5; - __IOM uint32_t TDCO : 8; /*!< [23..16] Transceiver Delay Compensation Offset */ - uint32_t : 4; - __IOM uint32_t FDOE : 1; /*!< [28..28] FD only enable */ - __IOM uint32_t REFE : 1; /*!< [29..29] RX edge filter enable */ - __IOM uint32_t CLOE : 1; /*!< [30..30] Classical CAN only enable */ - uint32_t : 1; - } FDCFG_b; - }; - - union - { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) Channel CAN-FD Control Register */ - - struct - { - __IOM uint32_t EOCCLR : 1; /*!< [0..0] Error Occurrence Counter Clear */ - __IOM uint32_t SOCCLR : 1; /*!< [1..1] Successful Occurrence Counter Clear */ - uint32_t : 30; - } FDCTR_b; - }; - - union - { - __IOM uint32_t FDSTS; /*!< (@ 0x0000000C) Channel CAN-FD Status Register */ - - struct - { - __IM uint32_t TDCR : 8; /*!< [7..0] Transceiver Delay Compensation Result */ - __IOM uint32_t EOCO : 1; /*!< [8..8] Error occurrence counter overflow */ - __IOM uint32_t SOCO : 1; /*!< [9..9] Successful occurrence counter overflow */ - uint32_t : 5; - __IOM uint32_t TDCVF : 1; /*!< [15..15] Transceiver Delay Compensation Violation Flag */ - __IM uint32_t EOC : 8; /*!< [23..16] Error occurrence counter register */ - __IM uint32_t SOC : 8; /*!< [31..24] Successful occurrence counter register */ - } FDSTS_b; - }; - - union - { - __IOM uint32_t FDCRC; /*!< (@ 0x00000010) Channel CAN-FD CRC Register */ - - struct - { - __IM uint32_t CRCREG : 21; /*!< [20..0] CRC Register value */ - uint32_t : 3; - __IM uint32_t SCNT : 4; /*!< [27..24] Stuff bit count */ - uint32_t : 4; - } FDCRC_b; + __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ + uint16_t : 7; + } HA_b; }; - __IM uint32_t RESERVED[3]; -} R_CANFDL_CFDC2_Type; /*!< Size = 32 (0x20) */ + __IM uint16_t RESERVED; +} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_CANFDL_CFDGAFL [CFDGAFL] (Global Acceptance Filter List Registers) + * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) */ typedef struct { union { - __IOM uint32_t ID; /*!< (@ 0x00000000) Global Acceptance Filter List ID Registers */ - - struct - { - __IOM uint32_t GAFLID : 29; /*!< [28..0] Global Acceptance Filter List Entry ID Field */ - __IOM uint32_t GAFLLB : 1; /*!< [29..29] Global Acceptance Filter List Entry Loopback Configuration */ - __IOM uint32_t GAFLRTR : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Field */ - __IOM uint32_t GAFLIDE : 1; /*!< [31..31] Global Acceptance Filter List Entry IDE Field */ - } ID_b; - }; - - union - { - __IOM uint32_t M; /*!< (@ 0x00000004) Global Acceptance Filter List Mask Registers */ - - struct - { - __IOM uint32_t GAFLIDM : 29; /*!< [28..0] Global Acceptance Filter List ID Mask Field */ - __IOM uint32_t GAFLIFL1 : 1; /*!< [29..29] Global Acceptance Filter List Information Label 1 */ - __IOM uint32_t GAFLRTRM : 1; /*!< [30..30] Global Acceptance Filter List Entry RTR Mask */ - __IOM uint32_t GAFLIDEM : 1; /*!< [31..31] Global Acceptance Filter List IDE Mask */ - } M_b; - }; - - union - { - __IOM uint32_t P0; /*!< (@ 0x00000008) Global Acceptance Filter List Pointer 0 Registers */ + __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ struct { - __IOM uint32_t GAFLDLC : 4; /*!< [3..0] Global Acceptance Filter List DLC Field */ - uint32_t : 3; - __IOM uint32_t GAFLIFL0 : 1; /*!< [7..7] Global Acceptance Filter List Information Label 0 */ - __IOM uint32_t GAFLRMDP : 5; /*!< [12..8] Global Acceptance Filter List RX Message Buffer Direction - * Pointer */ - uint32_t : 2; - __IOM uint32_t GAFLRMV : 1; /*!< [15..15] Global Acceptance Filter List RX Message Buffer Valid */ - __IOM uint32_t GAFLPTR : 16; /*!< [31..16] Global Acceptance Filter List Pointer Field */ - } P0_b; + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } A_b; }; union { - __IOM uint32_t P1; /*!< (@ 0x0000000C) Global Acceptance Filter List Pointer 1 Registers */ + __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ struct { - __IOM uint32_t GAFLFDP : 9; /*!< [8..0] Global Acceptance Filter List FIFO Direction Pointer */ - uint32_t : 23; - } P1_b; + __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ + uint16_t : 11; + } B_b; }; -} R_CANFDL_CFDGAFL_Type; /*!< Size = 16 (0x10) */ +} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ /** - * @brief R_CANFDL_CFDTHL [CFDTHL] (Channel TX History List) + * @brief R_IIC0_SAR [SAR] (Slave Address Registers) */ typedef struct { union { - __IM uint32_t ACC0; /*!< (@ 0x00000000) Channel TX History List Access Registers 0 */ + __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ struct { - __IM uint32_t BT : 3; /*!< [2..0] Buffer Type */ - __IM uint32_t BN : 7; /*!< [9..3] Buffer No. */ - uint32_t : 6; - __IM uint32_t TMTS : 16; /*!< [31..16] Transmit Timestamp */ - } ACC0_b; + __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit + * Address = { SVA9,SVA8,SVA[7:0] } */ + } L_b; }; union { - __IOM uint32_t ACC1; /*!< (@ 0x00000004) Channel TX History List Access Registers 1 */ + __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ struct { - __IM uint32_t TID : 16; /*!< [15..0] Transmit ID */ - __IM uint32_t TIFL : 2; /*!< [17..16] Transmit Information Label */ - uint32_t : 14; - } ACC1_b; + __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ + __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ + __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ + uint8_t : 5; + } U_b; }; -} R_CANFDL_CFDTHL_Type; /*!< Size = 8 (0x8) */ +} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ /** - * @brief R_CANFDL_CFDRF [CFDRF] (RX FIFO Access Registers) + * @brief R_IIRFA_IIRCH [IIRCH] (Channel Registers) */ typedef struct { + __OM uint32_t INP; /*!< (@ 0x00000000) Channel Input Register */ + __IM uint32_t OUT; /*!< (@ 0x00000004) Channel Output Register */ + union { - __IM uint32_t ID; /*!< (@ 0x00000000) RX FIFO Access ID Register */ + __IOM uint32_t CNT; /*!< (@ 0x00000008) Channel Control Register */ struct { - __IM uint32_t RFID : 29; /*!< [28..0] RX FIFO Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RFRTR : 1; /*!< [30..30] RX FIFO Buffer RTR Frame */ - __IM uint32_t RFIDE : 1; /*!< [31..31] RX FIFO Buffer IDE Bit */ - } ID_b; + __IOM uint32_t STGSEL : 32; /*!< [31..0] Stage selection bit */ + } CNT_b; }; union { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX FIFO Access Pointer Register */ + __IOM uint8_t INT; /*!< (@ 0x0000000C) Channel Interrupt Enable Register */ struct { - __IM uint32_t RFTS : 16; /*!< [15..0] RX FIFO Timestamp Field */ - uint32_t : 12; - __IM uint32_t RFDLC : 4; /*!< [31..28] RX FIFO Buffer DLC Field */ - } PTR_b; + uint8_t : 1; + __IOM uint8_t CPRCFIE : 1; /*!< [1..1] Channel processing completion interrupt enable bit */ + __IOM uint8_t ORDYIE : 1; /*!< [2..2] Output data preparation completion interrupt enable bit */ + __IOM uint8_t CERRIE : 1; /*!< [3..3] Operation error interrupt enable bit */ + uint8_t : 4; + } INT_b; }; union { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX FIFO Access CAN-FD Status Register */ + __IM uint8_t STS; /*!< (@ 0x0000000D) Channel Status Register */ struct { - __IM uint32_t RFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RFIFL : 2; /*!< [9..8] RX FIFO Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RFPTR : 16; /*!< [31..16] RX FIFO Buffer Pointer Field */ - } FDSTS_b; + __IM uint8_t CPRCS : 1; /*!< [0..0] Channel processing status flag */ + __IM uint8_t CPRCFF : 1; /*!< [1..1] Channel processing completion flag */ + __IM uint8_t ORDYF : 1; /*!< [2..2] Output data preparation completion flag */ + __IM uint8_t CERRF : 1; /*!< [3..3] Operation error flag */ + uint8_t : 4; + } STS_b; }; union { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX FIFO Access Data Field Registers */ + __OM uint8_t FCLR; /*!< (@ 0x0000000E) Channel Flag Clear Register */ struct { - __IM uint8_t RFDB : 8; /*!< [7..0] RX FIFO Buffer Data Byte */ - } DF_b[64]; + uint8_t : 1; + __OM uint8_t CPRCFFCLR : 1; /*!< [1..1] Channel processing completion flag clear bit */ + uint8_t : 1; + __OM uint8_t CERRFCLR : 1; /*!< [3..3] Operation error flag clear bit */ + uint8_t : 4; + } FCLR_b; }; -} R_CANFDL_CFDRF_Type; /*!< Size = 76 (0x4c) */ + __IM uint8_t RESERVED; +} R_IIRFA_IIRCH_Type; /*!< Size = 16 (0x10) */ + +/** + * @brief R_IIRFA_IIRSTG [IIRSTG] (Stage Registers) + */ +typedef struct +{ + __IOM uint32_t B0; /*!< (@ 0x00000000) Stage Coefficient b0 Register */ + __IOM uint32_t B1; /*!< (@ 0x00000004) Stage Coefficient b1 Register */ + __IOM uint32_t B2; /*!< (@ 0x00000008) Stage Coefficient b2 Register */ + __IOM uint32_t A1; /*!< (@ 0x0000000C) Stage Coefficient a1 Register */ + __IOM uint32_t A2; /*!< (@ 0x00000010) Stage Coefficient a2 Register */ + __IOM uint32_t D0; /*!< (@ 0x00000014) Stage Delay Data D0 Register */ + __IOM uint32_t D1; /*!< (@ 0x00000018) Stage Delay Data D1 Register */ + __IM uint32_t RESERVED; +} R_IIRFA_IIRSTG_Type; /*!< Size = 32 (0x20) */ /** - * @brief R_CANFDL_CFDCF [CFDCF] (Common FIFO Access Registers) + * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) */ typedef struct { union { - __IOM uint32_t ID; /*!< (@ 0x00000000) Common FIFO Access ID Register */ + __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection + * Register */ struct { - __IOM uint32_t CFID : 29; /*!< [28..0] Common FIFO Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t CFRTR : 1; /*!< [30..30] Common FIFO Buffer RTR Frame */ - __IOM uint32_t CFIDE : 1; /*!< [31..31] Common FIFO Buffer IDE Bit */ - } ID_b; + __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } OAD_b; }; + __IM uint16_t RESERVED; union { - __IOM uint32_t PTR; /*!< (@ 0x00000004) Common FIFO Access Pointer Register */ + __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ struct { - __IOM uint32_t CFTS : 16; /*!< [15..0] Common FIFO Timestamp Field */ - uint32_t : 12; - __IOM uint32_t CFDLC : 4; /*!< [31..28] Common FIFO Buffer DLC Field */ - } PTR_b; + __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ + uint16_t : 7; + __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ + uint16_t : 7; + } CTL_b; }; union { - __IOM uint32_t FDSTS; /*!< (@ 0x00000008) Common FIFO Access CAN-FD Status Register */ + __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ struct { - __IOM uint32_t CFESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t CFBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t CFFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t CFIFL : 2; /*!< [9..8] Common FIFO Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t CFPTR : 16; /*!< [31..16] Common FIFO Buffer Pointer Field */ - } FDSTS_b; + __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ + uint16_t : 7; + __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not + * stored. */ + } PT_b; }; union { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) Common FIFO Access Data Field Registers */ + __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ struct { - __IOM uint8_t CFDB : 8; /*!< [7..0] Common FIFO Buffer Data Byte */ - } DF_b[64]; + __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF + * The low-order 2 bits are fixed to 0. */ + } SA_b; }; -} R_CANFDL_CFDCF_Type; /*!< Size = 76 (0x4c) */ -/** - * @brief R_CANFDL_CFDTM [CFDTM] (TX Message Buffer Access Registers) - */ -typedef struct -{ union { - __IOM uint32_t ID; /*!< (@ 0x00000000) TX Message Buffer ID Register */ + __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ struct { - __IOM uint32_t TMID : 29; /*!< [28..0] TX Message Buffer ID Field */ - uint32_t : 1; - __IOM uint32_t TMRTR : 1; /*!< [30..30] TX Message Buffer RTR Frame */ - __IOM uint32_t TMIDE : 1; /*!< [31..31] TX Message Buffer IDE Bit */ - } ID_b; + __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region + * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF + * The low-order 2 bits are fixed to 1. */ + } EA_b; }; +} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ +/** + * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) + */ +typedef struct +{ union { - __IOM uint32_t PTR; /*!< (@ 0x00000004) TX Message Buffer Pointer Register */ - - struct + union { - __IOM uint32_t TMTS : 16; /*!< [15..0] TX Message Buffer Timestamp Field */ - uint32_t : 12; - __IOM uint32_t TMDLC : 4; /*!< [31..28] TX Message Buffer DLC Field */ - } PTR_b; - }; + __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - union - { - __IOM uint32_t FDCTR; /*!< (@ 0x00000008) TX Message Buffer CAN-FD Control Register */ + struct + { + __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ + uint32_t : 1; + __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint32_t : 3; + __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ + __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ + uint32_t : 7; + __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral + * function. For individual pin functions, see the MPC table */ + uint32_t : 3; + } PmnPFS_b; + }; struct { - __IOM uint32_t TMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IOM uint32_t TMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IOM uint32_t TMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IOM uint32_t TMIFL : 2; /*!< [9..8] TX Message Buffer Information Label Field */ - uint32_t : 6; - __IOM uint32_t TMPTR : 16; /*!< [31..16] TX Message Buffer Pointer Field */ - } FDCTR_b; - }; + union + { + struct + { + __IM uint16_t RESERVED; - union - { - __IOM uint8_t DF[64]; /*!< (@ 0x0000000C) TX Message Buffer Data Field Registers */ + union + { + __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - struct - { - __IOM uint8_t TMDB : 8; /*!< [7..0] TX Message Buffer Data Byte */ - } DF_b[64]; + struct + { + __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ + uint16_t : 1; + __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint16_t : 3; + __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ + __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ + __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ + __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ + } PmnPFS_HA_b; + }; + }; + + struct + { + __IM uint16_t RESERVED1; + __IM uint8_t RESERVED2; + + union + { + __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ + + struct + { + __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ + __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ + __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ + uint8_t : 1; + __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ + __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ + __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ + uint8_t : 1; + } PmnPFS_BY_b; + }; + }; + }; + }; }; -} R_CANFDL_CFDTM_Type; /*!< Size = 76 (0x4c) */ +} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_PFS_PORT [PORT] (Port [0..14]) + */ +typedef struct +{ + __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ +} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ /** - * @brief R_CANFDL_CFDRMC_RM [RM] (RX Message Buffer Access Registers) + * @brief R_PFS_VLSEL [VLSEL] (VLSEL) */ typedef struct { + __IM uint8_t RESERVED[389]; + union { - __IM uint32_t ID; /*!< (@ 0x00000000) RX Message Buffer ID Register */ + __IOM uint8_t VL1SEL; /*!< (@ 0x00000185) VL1 Select Control Register */ struct { - __IM uint32_t RMID : 29; /*!< [28..0] RX Message Buffer ID Field */ - uint32_t : 1; - __IM uint32_t RMRTR : 1; /*!< [30..30] RX Message Buffer RTR Frame */ - __IM uint32_t RMIDE : 1; /*!< [31..31] RX Message Buffer IDE Bit */ - } ID_b; + __IOM uint8_t SELVL : 1; /*!< [0..0] VL1 Voltage Connection Switching Control */ + uint8_t : 7; + } VL1SEL_b; }; +} R_PFS_VLSEL_Type; /*!< Size = 390 (0x186) */ + +/** + * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) + */ +typedef struct +{ + __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ + __IM uint16_t RESERVED; +} R_PMISC_PMSAR_Type; /*!< Size = 4 (0x4) */ + +/** + * @brief R_BUS_B_CSa [CSa] (CS Registers) + */ +typedef struct +{ + __IM uint16_t RESERVED; union { - __IM uint32_t PTR; /*!< (@ 0x00000004) RX Message Buffer Pointer Register */ + __IOM uint16_t MOD; /*!< (@ 0x00000002) Mode Register */ struct { - __IM uint32_t RMTS : 16; /*!< [15..0] RX Message Buffer Timestamp Field */ - uint32_t : 12; - __IM uint32_t RMDLC : 4; /*!< [31..28] RX Message Buffer DLC Field */ - } PTR_b; + __IOM uint16_t WRMOD : 1; /*!< [0..0] Write Access Mode Select */ + uint16_t : 2; + __IOM uint16_t EWENB : 1; /*!< [3..3] External Wait Enable */ + uint16_t : 4; + __IOM uint16_t PRENB : 1; /*!< [8..8] Page Read Access Enable */ + __IOM uint16_t PWENB : 1; /*!< [9..9] Page Write Access Enable */ + uint16_t : 5; + __IOM uint16_t PRMOD : 1; /*!< [15..15] Page Read Access Mode Select */ + } MOD_b; }; union { - __IM uint32_t FDSTS; /*!< (@ 0x00000008) RX Message Buffer CAN-FD Status Register */ + __IOM uint32_t WCR1; /*!< (@ 0x00000004) Wait Control Register 1 */ struct { - __IM uint32_t RMESI : 1; /*!< [0..0] Error State Indicator bit */ - __IM uint32_t RMBRS : 1; /*!< [1..1] Bit Rate Switch bit */ - __IM uint32_t RMFDF : 1; /*!< [2..2] CAN FD Format bit */ - uint32_t : 5; - __IM uint32_t RMIFL : 2; /*!< [9..8] RX Message Buffer Information Label Field */ - uint32_t : 6; - __IM uint32_t RMPTR : 16; /*!< [31..16] RX Message Buffer Pointer Field */ - } FDSTS_b; + __IOM uint32_t CSPWWAIT : 3; /*!< [2..0] Page Write Cycle Wait SelectNOTE: The CSPWWAIT value + * is valid only when the PWENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSPRWAIT : 3; /*!< [10..8] Page Read Cycle Wait SelectNOTE: The CSPRWAIT value + * is valid only when the PRENB bit in CSnMOD is set to 1. */ + uint32_t : 5; + __IOM uint32_t CSWWAIT : 5; /*!< [20..16] Normal Write Cycle Wait Select */ + uint32_t : 3; + __IOM uint32_t CSRWAIT : 5; /*!< [28..24] Normal Read Cycle Wait Select */ + uint32_t : 3; + } WCR1_b; }; union { - __IM uint8_t DF[64]; /*!< (@ 0x0000000C) RX Message Buffer Data Field Registers */ + __IOM uint32_t WCR2; /*!< (@ 0x00000008) Wait Control Register 2 */ struct { - __IM uint8_t RMDB : 8; /*!< [7..0] RX Message Buffer Data Byte */ - } DF_b[64]; + __IOM uint32_t CSROFF : 3; /*!< [2..0] Read-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t CSWOFF : 3; /*!< [6..4] Write-Access CS Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t WDOFF : 3; /*!< [10..8] Write Data Output Extension Cycle Select */ + uint32_t : 1; + __IOM uint32_t AWAIT : 2; /*!< [13..12] CS Assert Wait Select */ + uint32_t : 2; + __IOM uint32_t RDON : 3; /*!< [18..16] RD Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WRON : 3; /*!< [22..20] WR Assert Wait Select */ + uint32_t : 1; + __IOM uint32_t WDON : 3; /*!< [26..24] Write Data Output Wait Select */ + uint32_t : 1; + __IOM uint32_t CSON : 3; /*!< [30..28] CS Assert Wait Select */ + uint32_t : 1; + } WCR2_b; }; -} R_CANFDL_CFDRMC_RM_Type; /*!< Size = 76 (0x4c) */ + __IM uint32_t RESERVED1; +} R_BUS_B_CSa_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_CANFDL_CFDRMC [CFDRMC] (RX Message Buffer Access Clusters) + * @brief R_BUS_B_CSb [CSb] (CS Registers) */ typedef struct { - __IOM R_CANFDL_CFDRMC_RM_Type RM[8]; /*!< (@ 0x00000000) RX Message Buffer Access Registers */ - __IM uint32_t RESERVED[104]; -} R_CANFDL_CFDRMC_Type; /*!< Size = 1024 (0x400) */ + __IM uint16_t RESERVED; -/** - * @brief R_ELC_ELSEGR [ELSEGR] (Event Link Software Event Generation Register) - */ -typedef struct -{ union { - __IOM uint8_t BY; /*!< (@ 0x00000000) Event Link Software Event Generation Register */ + __IOM uint16_t CR; /*!< (@ 0x00000002) Control Register */ struct { - __OM uint8_t SEG : 1; /*!< [0..0] Software Event Generation */ - uint8_t : 5; - __IOM uint8_t WE : 1; /*!< [6..6] SEG Bit Write Enable */ - __OM uint8_t WI : 1; /*!< [7..7] ELSEGR Register Write Disable */ - } BY_b; + __IOM uint16_t EXENB : 1; /*!< [0..0] Operation Enable */ + uint16_t : 3; + __IOM uint16_t BSIZE : 2; /*!< [5..4] External Bus Width Select */ + uint16_t : 2; + __IOM uint16_t EMODE : 1; /*!< [8..8] Endian Mode */ + uint16_t : 3; + __IOM uint16_t MPXEN : 1; /*!< [12..12] Address/Data Multiplexed I/O Interface Select */ + uint16_t : 3; + } CR_b; }; - __IM uint8_t RESERVED; -} R_ELC_ELSEGR_Type; /*!< Size = 2 (0x2) */ + __IM uint16_t RESERVED1[3]; -/** - * @brief R_ELC_ELSR [ELSR] (Event Link Setting Register [0..29]) - */ -typedef struct -{ union { - __IOM uint16_t HA; /*!< (@ 0x00000000) Event Link Setting Register */ + __IOM uint16_t REC; /*!< (@ 0x0000000A) Recovery Cycle Register */ struct { - __IOM uint16_t ELS : 9; /*!< [8..0] Event Link Select */ - uint16_t : 7; - } HA_b; + __IOM uint16_t RRCV : 4; /*!< [3..0] Read Recovery */ + uint16_t : 4; + __IOM uint16_t WRCV : 4; /*!< [11..8] Write Recovery */ + uint16_t : 4; + } REC_b; }; - __IM uint16_t RESERVED; -} R_ELC_ELSR_Type; /*!< Size = 4 (0x4) */ + __IM uint16_t RESERVED2[2]; +} R_BUS_B_CSb_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_GPT_ODC_GTDLYR [GTDLYR] (PWM DELAY RISING) + * @brief R_BUS_B_BUSERR [BUSERR] (Bus Error Registers) */ typedef struct { union { - __IOM uint16_t A; /*!< (@ 0x00000000) GTIOCA Output Delay Register */ + __IM uint32_t ADD; /*!< (@ 0x00000000) Bus Error Address Register */ struct { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; - } A_b; + __IM uint32_t BERAD : 32; /*!< [31..0] Bus Error AddressWhen a bus error occurs, It stores + * an error address. */ + } ADD_b; }; union { - __IOM uint16_t B; /*!< (@ 0x00000002) GTIOCB Output Delay Register */ + __IM uint8_t ERRRW; /*!< (@ 0x00000004) BUS Error Read Write Register */ struct { - __IOM uint16_t DLY : 5; /*!< [4..0] GTIOCnA Output Rising Edge Delay Setting */ - uint16_t : 11; - } B_b; + __IM uint8_t RWSTAT : 1; /*!< [0..0] Error access statusThe status at the time of the error */ + uint8_t : 7; + } ERRRW_b; }; -} R_GPT_ODC_GTDLYR_Type; /*!< Size = 4 (0x4) */ + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_B_BUSERR_Type; /*!< Size = 16 (0x10) */ /** - * @brief R_IIC0_SAR [SAR] (Slave Address Registers) + * @brief R_BUS_B_BUSTZFERR [BUSTZFERR] (Bus TZF Error Registers) */ typedef struct { union { - __IOM uint8_t L; /*!< (@ 0x00000000) Slave Address Register L */ + __IM uint32_t TZFADD; /*!< (@ 0x00000000) Bus TZF Error Address Register */ struct { - __IOM uint8_t SVA : 8; /*!< [7..0] A slave address is set.7-Bit Address = SVA[7:1] 10-Bit - * Address = { SVA9,SVA8,SVA[7:0] } */ - } L_b; + __IM uint32_t BTZFERAD : 32; /*!< [31..0] Bus TrustZone Filter Error AddressWhen a bus error occurs, + * It stores an error address. */ + } TZFADD_b; }; union { - __IOM uint8_t U; /*!< (@ 0x00000001) Slave Address Register U */ - - struct - { - __IOM uint8_t FS : 1; /*!< [0..0] 7-Bit/10-Bit Address Format Selection */ - __IOM uint8_t SVA8 : 1; /*!< [1..1] 10-Bit Address(bit8) */ - __IOM uint8_t SVA9 : 1; /*!< [2..2] 10-Bit Address(bit9) */ - uint8_t : 5; - } U_b; - }; -} R_IIC0_SAR_Type; /*!< Size = 2 (0x2) */ - -/** - * @brief R_IIRFA_IIRCH [IIRCH] (Channel Registers) - */ -typedef struct -{ - __OM uint32_t INP; /*!< (@ 0x00000000) Channel Input Register */ - __IM uint32_t OUT; /*!< (@ 0x00000004) Channel Output Register */ - - union - { - __IOM uint32_t CNT; /*!< (@ 0x00000008) Channel Control Register */ - - struct - { - __IOM uint32_t STGSEL : 32; /*!< [31..0] Stage selection bit */ - } CNT_b; - }; - - union - { - __IOM uint8_t INT; /*!< (@ 0x0000000C) Channel Interrupt Enable Register */ - - struct - { - uint8_t : 1; - __IOM uint8_t CPRCFIE : 1; /*!< [1..1] Channel processing completion interrupt enable bit */ - __IOM uint8_t ORDYIE : 1; /*!< [2..2] Output data preparation completion interrupt enable bit */ - __IOM uint8_t CERRIE : 1; /*!< [3..3] Operation error interrupt enable bit */ - uint8_t : 4; - } INT_b; - }; - - union - { - __IM uint8_t STS; /*!< (@ 0x0000000D) Channel Status Register */ - - struct - { - __IM uint8_t CPRCS : 1; /*!< [0..0] Channel processing status flag */ - __IM uint8_t CPRCFF : 1; /*!< [1..1] Channel processing completion flag */ - __IM uint8_t ORDYF : 1; /*!< [2..2] Output data preparation completion flag */ - __IM uint8_t CERRF : 1; /*!< [3..3] Operation error flag */ - uint8_t : 4; - } STS_b; - }; - - union - { - __OM uint8_t FCLR; /*!< (@ 0x0000000E) Channel Flag Clear Register */ - - struct - { - uint8_t : 1; - __OM uint8_t CPRCFFCLR : 1; /*!< [1..1] Channel processing completion flag clear bit */ - uint8_t : 1; - __OM uint8_t CERRFCLR : 1; /*!< [3..3] Operation error flag clear bit */ - uint8_t : 4; - } FCLR_b; - }; - __IM uint8_t RESERVED; -} R_IIRFA_IIRCH_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_IIRFA_IIRSTG [IIRSTG] (Stage Registers) - */ -typedef struct -{ - __IOM uint32_t B0; /*!< (@ 0x00000000) Stage Coefficient b0 Register */ - __IOM uint32_t B1; /*!< (@ 0x00000004) Stage Coefficient b1 Register */ - __IOM uint32_t B2; /*!< (@ 0x00000008) Stage Coefficient b2 Register */ - __IOM uint32_t A1; /*!< (@ 0x0000000C) Stage Coefficient a1 Register */ - __IOM uint32_t A2; /*!< (@ 0x00000010) Stage Coefficient a2 Register */ - __IOM uint32_t D0; /*!< (@ 0x00000014) Stage Delay Data D0 Register */ - __IOM uint32_t D1; /*!< (@ 0x00000018) Stage Delay Data D1 Register */ - __IM uint32_t RESERVED; -} R_IIRFA_IIRSTG_Type; /*!< Size = 32 (0x20) */ - -/** - * @brief R_MPU_SPMON_SP [SP] (Stack Pointer Monitor) - */ -typedef struct -{ - union - { - __IOM uint16_t OAD; /*!< (@ 0x00000000) Stack Pointer Monitor Operation After Detection - * Register */ - - struct - { - __IOM uint16_t OAD : 1; /*!< [0..0] Operation after detection */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } OAD_b; - }; - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t CTL; /*!< (@ 0x00000004) Stack Pointer Monitor Access Control Register */ - - struct - { - __IOM uint16_t ENABLE : 1; /*!< [0..0] Stack Pointer Monitor Enable */ - uint16_t : 7; - __IOM uint16_t ERROR : 1; /*!< [8..8] Stack Pointer Monitor Error Flag */ - uint16_t : 7; - } CTL_b; - }; - - union - { - __IOM uint16_t PT; /*!< (@ 0x00000006) Stack Pointer Monitor Protection Register */ - - struct - { - __IOM uint16_t PROTECT : 1; /*!< [0..0] Protection of register (MSPMPUAC, MSPMPUSA and MSPMPUSE) */ - uint16_t : 7; - __OM uint16_t KEY : 8; /*!< [15..8] Write Keyword The data written to these bits are not - * stored. */ - } PT_b; - }; - - union - { - __IOM uint32_t SA; /*!< (@ 0x00000008) Stack Pointer Monitor Start Address Register */ - - struct - { - __IOM uint32_t MSPMPUSA : 32; /*!< [31..0] Region start address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00000-0x200FFFF - * The low-order 2 bits are fixed to 0. */ - } SA_b; - }; - - union - { - __IOM uint32_t EA; /*!< (@ 0x0000000C) Stack Pointer Monitor End Address Register */ - - struct - { - __IOM uint32_t MSPMPUEA : 32; /*!< [31..0] Region end address register Address where the region - * starts, for use in region determination.NOTE: Range: 0x1FF00003-0x200FFFF - * The low-order 2 bits are fixed to 1. */ - } EA_b; - }; -} R_MPU_SPMON_SP_Type; /*!< Size = 16 (0x10) */ - -/** - * @brief R_PFS_PORT_PIN [PIN] (Pin Function Selects) - */ -typedef struct -{ - union - { - union - { - __IOM uint32_t PmnPFS; /*!< (@ 0x00000000) Pin Function Control Register */ - - struct - { - __IOM uint32_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint32_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint32_t PDR : 1; /*!< [2..2] Port Direction */ - uint32_t : 1; - __IOM uint32_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint32_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint32_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint32_t : 3; - __IOM uint32_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint32_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint32_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint32_t ASEL : 1; /*!< [15..15] Analog Input enable */ - __IOM uint32_t PMR : 1; /*!< [16..16] Port Mode Control */ - uint32_t : 7; - __IOM uint32_t PSEL : 5; /*!< [28..24] Port Function SelectThese bits select the peripheral - * function. For individual pin functions, see the MPC table */ - uint32_t : 3; - } PmnPFS_b; - }; - - struct - { - union - { - struct - { - __IM uint16_t RESERVED; - - union - { - __IOM uint16_t PmnPFS_HA; /*!< (@ 0x00000002) Pin Function Control Register */ - - struct - { - __IOM uint16_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint16_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint16_t PDR : 1; /*!< [2..2] Port Direction */ - uint16_t : 1; - __IOM uint16_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint16_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint16_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint16_t : 3; - __IOM uint16_t DSCR : 2; /*!< [11..10] Drive Strength Control Register */ - __IOM uint16_t EOFR : 2; /*!< [13..12] Event on Falling/Rising */ - __IOM uint16_t ISEL : 1; /*!< [14..14] IRQ input enable */ - __IOM uint16_t ASEL : 1; /*!< [15..15] Analog Input enable */ - } PmnPFS_HA_b; - }; - }; - - struct - { - __IM uint16_t RESERVED1; - __IM uint8_t RESERVED2; - - union - { - __IOM uint8_t PmnPFS_BY; /*!< (@ 0x00000003) Pin Function Control Register */ - - struct - { - __IOM uint8_t PODR : 1; /*!< [0..0] Port Output Data */ - __IM uint8_t PIDR : 1; /*!< [1..1] Port Input Data */ - __IOM uint8_t PDR : 1; /*!< [2..2] Port Direction */ - uint8_t : 1; - __IOM uint8_t PCR : 1; /*!< [4..4] Pull-up Control */ - __IOM uint8_t PIM : 1; /*!< [5..5] Port Input Mode Control */ - __IOM uint8_t NCODR : 1; /*!< [6..6] N-Channel Open Drain Control */ - uint8_t : 1; - } PmnPFS_BY_b; - }; - }; - }; - }; - }; -} R_PFS_PORT_PIN_Type; /*!< Size = 4 (0x4) */ - -/** - * @brief R_PFS_PORT [PORT] (Port [0..14]) - */ -typedef struct -{ - __IOM R_PFS_PORT_PIN_Type PIN[16]; /*!< (@ 0x00000000) Pin Function Selects */ -} R_PFS_PORT_Type; /*!< Size = 64 (0x40) */ - -/** - * @brief R_PMISC_PMSAR [PMSAR] (Port Security Attribution Register) - */ -typedef struct -{ - __IOM uint16_t PMSAR; /*!< (@ 0x00000000) Port Security Attribution Register */ - __IM uint16_t RESERVED; -} R_PMISC_PMSAR_Type; /*!< Size = 4 (0x4) */ - -/** @} */ /* End of group Device_Peripheral_clusters */ - -/* =========================================================================================================================== */ -/* ================ Device Specific Peripheral Section ================ */ -/* =========================================================================================================================== */ - -/** @addtogroup Device_Peripheral_peripherals - * @{ - */ - -/* =========================================================================================================================== */ -/* ================ R_ACMPHS0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief High-Speed Analog Comparator (R_ACMPHS0) - */ - -typedef struct /*!< (@ 0x400F4000) R_ACMPHS0 Structure */ -{ - union - { - __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ - - struct - { - __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ - __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ - __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ - __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ - __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ - __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ - } CMPCTL_b; - }; - __IM uint8_t RESERVED[3]; - - union - { - __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ - - struct - { - __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ - uint8_t : 4; - } CMPSEL0_b; - }; - __IM uint8_t RESERVED1[3]; - - union - { - __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ - - struct - { - __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ - uint8_t : 2; - } CMPSEL1_b; - }; - __IM uint8_t RESERVED2[3]; - - union - { - __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ - - struct - { - __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ - uint8_t : 7; - } CMPMON_b; - }; - __IM uint8_t RESERVED3[3]; - - union - { - __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ - - struct - { - __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ - uint8_t : 6; - __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ - } CPIOC_b; - }; -} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ - -/* =========================================================================================================================== */ -/* ================ R_ADC0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief A/D Converter (R_ADC0) - */ - -typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ -{ - union - { - __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ - - struct - { - __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog - * input channel for double triggered operation. The setting - * is only effective while double trigger mode is selected. */ - uint16_t : 1; - __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ - __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ - __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ - __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ - __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ - uint16_t : 1; - __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ - __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ - __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ - } ADCSR_b; - }; - - union - { - __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ - - struct - { - __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes - * '1' while scanning. */ - uint8_t : 6; - __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ - } ADREF_b; - }; - - union - { - __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ - - struct - { - __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ - uint8_t : 7; - } ADEXREF_b; - }; - - union - { - __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ - - struct - { - __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ - } ADANSA_b[2]; - }; - - union - { - __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel - * Select Register */ - - struct - { - __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ - __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ - } ADADS_b[2]; - }; - - union - { - __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select - * Register */ - - struct - { - __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid - * at the only setting of ADC[2:0] bits = 001b or 011b. When - * average mode is selected by setting the ADADC.AVEE bit - * to 1, do not set the addition count to three times (ADADC.ADC[2:0] - * = 010b) */ - uint8_t : 4; - __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected - * by setting the ADADC.AVEE bit to 0, set the addition count - * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion - * can only be used with 12-bit accuracy selected. NOTE: AVEE - * bit is valid at the only setting of ADC[2:0] bits = 001b - * or 011b. When average mode is selected by setting the ADADC.AVEE - * bit to 1, do not set the addition count to three times - * (ADADC.ADC[2:0] = 010b) */ - } ADADC_b; - }; - __IM uint8_t RESERVED; - - union - { - __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ - - struct - { - uint16_t : 1; - __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ - uint16_t : 1; - __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ - __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ - uint16_t : 2; - __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ - __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ - __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ - uint16_t : 2; - __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ - __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ - } ADCER_b; - }; - - union - { - __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ - - struct - { - __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect - * the A/D conversion start trigger for group B in group scan - * mode. */ - uint16_t : 2; - __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion - * start trigger in single scan mode and continuous mode. - * In group scan mode, the A/D conversion start trigger for - * group A is selected. */ - uint16_t : 2; - } ADSTRGR_b; - }; - - union - { - __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ - - struct - { - __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average - * Mode Select */ - __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average - * Mode Select */ - uint16_t : 6; - __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ - __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ - __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for - * Group B in group scan mode. */ - __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for - * Group B in group scan mode. */ - uint16_t : 2; - __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ - __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ - } ADEXICR_b; - }; - - union - { - __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ - - struct - { - __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ - } ADANSB_b[2]; - }; - - union - { - __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ - - struct - { - __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * result of A/D conversion in response to the second trigger - * in double trigger mode. */ - } ADDBLDR_b; - }; - - union - { - __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ - - struct - { - __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D conversion result of temperature sensor output. */ - } ADTSDR_b; - }; - - union - { - __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ - - struct - { - __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the - * A/D result of internal reference voltage. */ - } ADOCDR_b; - }; - - union - { - union - { - __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ - - struct - { - __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ - } ADRD_RIGHT_b; - }; - - union - { - __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ - - struct - { - __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for - * data determine ADCER.ADRFMT and ADCER.ADPRC. */ - } ADRD_LEFT_b; - }; - }; - - union - { - __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ - - struct - { - __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for - * storing the result of A/D conversion. */ - } ADDR_b[28]; - }; - __IM uint32_t RESERVED1[2]; - __IM uint16_t RESERVED2; - - union - { - __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ - - struct - { - __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ - } ADAMPOFF_b; - }; - - union - { - __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ - - struct - { - __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ - __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ - uint8_t : 6; - } ADTSTPR_b; - }; - - union - { - __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ - - struct - { - __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ - uint16_t : 3; - __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ - uint16_t : 2; - __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ - } ADDDACER_b; - }; - - union - { - __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ - - struct - { - __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time - * Setting Set the sampling time (4 to 255 states) */ - __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ - __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ - __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ - uint16_t : 5; - } ADSHCR_b; - }; - - union - { - __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ - - struct - { - __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit - * only for channel. */ - uint16_t : 1; - __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ - uint16_t : 2; - __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit - * for adjustment to hardening of process. */ - uint16_t : 1; - __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator - * power save bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim - * bit for A/D hard macro to hardening of process. */ - __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim - * bit for A/D hard macro to hardening of process. */ - } ADEXTSTR_b; - }; - - union - { - __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ - - struct - { - __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ - __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit - * amplifier test.Refreshing the pressure switch that opens - * for the DAC output voltage charge period when the amplifier - * of the S&H circuit is tested only for the channel is set. */ - uint16_t : 1; - __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control - * bit. */ - __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control - * bit */ - uint16_t : 1; - __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog - * module Details are described to the bit explanation. */ - __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the - * bit explanation. */ - } ADTSTRA_b; - }; - - union - { - __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ - - struct - { - __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It - * corresponds to ADVAL 14:0 input of A/D analog module. */ - uint16_t : 1; - } ADTSTRB_b; - }; - - union - { - __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ - - struct - { - __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D - * analog module. */ - uint16_t : 4; - __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ - uint16_t : 3; - } ADTSTRC_b; - }; - - union - { - __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ - - struct - { - __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It - * corresponds to ADVAL 16 input of A/D analog module. */ - uint16_t : 15; - } ADTSTRD_b; - }; - - union - { - __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ - - struct - { - __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR0_b; - }; - - union - { - __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ - - struct - { - __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ - __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ - __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ - __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ - __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ - __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ - uint16_t : 10; - } ADSWTSTR1_b; - }; - - union - { - __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ - - struct - { - __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit - * (ANEX0 switch) */ - __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit - * (ANEX1 switch). */ - uint16_t : 2; - __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ - __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ - __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ - uint16_t : 1; - __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ - __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ - __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ - __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ - __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ - uint16_t : 3; - } ADSWTSTR2_b; - }; - __IM uint16_t RESERVED3; - - union - { - __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ - - struct - { - __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ - __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ - uint8_t : 3; - } ADDISCR_b; - }; - - union - { - __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ - - struct - { - __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing - * the pressure switch in A/D analog module is set. */ - uint8_t : 1; - __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ - uint8_t : 1; - } ADSWCR_b; - }; - - union - { - __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ - - struct - { - __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode - * Select */ - uint8_t : 7; - } ADSHMSR_b; - }; - - union - { - __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ - - struct - { - __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ - uint8_t : 6; - } ADICR_b; - }; - - union - { - __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ - - struct - { - uint8_t : 1; - __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ - uint8_t : 6; - } ADACSR_b; - }; - __IM uint8_t RESERVED4; - - union - { - __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ - - struct - { - __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS - * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be - * set to 01b (group scan mode). If the bits are set to any - * other values, proper operation is not guaranteed. */ - __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved - * when PGS = 0.) */ - uint16_t : 6; - __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ - uint16_t : 6; - __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when - * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit - * has been set to 1, single scan is performed continuously - * for group B regardless of the setting of the GBRSCN bit. */ - } ADGSPCR_b; - }; - - union - { - __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group - * Scan) */ - - struct - { - __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ - __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ - } ADGSCS_b; - }; - - union - { - __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ - - struct - { - __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRA_b; - }; - - union - { - __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ - - struct - { - __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing - * the result of A/D conversion in response to the respective - * triggers during extended operation in double trigger mode. */ - } ADDBLDRB_b; - }; - - union - { - __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ - - struct - { - uint8_t : 7; - __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ - } ADSER_b; - }; - __IM uint8_t RESERVED5; - - union - { - __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage - * Control Register */ - - struct - { - __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } ADHVREFCNT_b; - }; - __IM uint8_t RESERVED6; - - union - { - __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor - * Register */ - - struct - { - __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination - * result.This bit is valid when both window A operation and - * window B operation are enabled. */ - uint8_t : 3; - __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ - __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ - uint8_t : 2; - } ADWINMON_b; - }; - __IM uint8_t RESERVED7; - __IM uint16_t RESERVED8; - - union - { - __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ - - struct - { - __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits - * are valid when both window A and window B are enabled (CMPAE - * = 1 and CMPBE = 1). */ - uint16_t : 7; - __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ - uint16_t : 1; - __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ - __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ - __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ - } ADCMPCR_b; - }; - - union - { - __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input - * Select Register */ - - struct - { - __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ - __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ - uint8_t : 6; - } ADCMPANSER_b; - }; - - union - { - __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input - * Comparison Condition Setting Register */ - - struct - { - __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison - * Condition Select */ - __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition - * Select */ - uint8_t : 6; - } ADCMPLER_b; - }; - - union - { - __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select - * Register */ - - struct - { - __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ - __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ - __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ - __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ - __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ - __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ - __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ - __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ - __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ - __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ - __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ - __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ - __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ - __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ - __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ - __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ - } ADCMPANSR_b[2]; - }; - - union - { - __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition - * Setting Register */ - - struct - { - __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ - __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ - __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ - __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ - __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ - __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ - __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ - __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ - __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ - __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ - __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ - __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ - __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ - __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ - __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ - __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ - } ADCMPLR_b[2]; - }; - - union - { - __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the - * compare window A function is used. ADCMPDR0 sets the lower-side - * level of window A. */ - } ADCMPDR0_b; - }; - - union - { - __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the - * compare window A function is used. ADCMPDR1 sets the upper-side - * level of window A.. */ - } ADCMPDR1_b; - }; - - union - { - __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status - * Register */ - - struct - { - __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ - __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ - } ADCMPSR_b[2]; - }; - - union - { - __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input - * Channel Status Register */ - - struct - { - __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag - * When window A operation is enabled (ADCMPCR.CMPAE = 1b), - * this bit indicates the temperature sensor output comparison - * result. When window A operation is disabled (ADCMPCR.CMPAE - * = 0b), comparison conditions for CMPSTTSA are not met any - * time. */ - uint8_t : 6; - } ADCMPSER_b; - }; - __IM uint8_t RESERVED9; - - union - { - __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection - * Register */ - - struct - { - __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that - * compares it on the condition of compare window B is selected. */ - uint8_t : 1; - __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ - } ADCMPBNSR_b; - }; - __IM uint8_t RESERVED10; - - union - { - __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the lower level of the window B. */ - } ADWINLLB_b; - }; - - union - { - __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level - * Setting Register */ - - struct - { - __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is - * used to set the higher level of the window B. */ - } ADWINULB_b; - }; - - union - { - __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ - - struct - { - __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows - * the comparative result of CH (AN000-AN027, temperature - * sensor, and internal reference voltage) made the object - * of window B relation condition. */ - uint8_t : 7; - } ADCMPBSR_b; - }; - __IM uint8_t RESERVED11; - __IM uint16_t RESERVED12; - - union - { - __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF0_b; - }; - - union - { - __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF1_b; - }; - - union - { - __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF2_b; - }; - - union - { - __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF3_b; - }; - - union - { - __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF4_b; - }; - - union - { - __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF5_b; - }; - - union - { - __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF6_b; - }; - - union - { - __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF7_b; - }; - - union - { - __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF8_b; - }; - - union - { - __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF9_b; - }; - - union - { - __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF10_b; - }; - - union - { - __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF11_b; - }; - - union - { - __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF12_b; - }; - - union - { - __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF13_b; - }; - - union - { - __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF14_b; - }; - - union - { - __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ - - struct - { - __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only - * registers that sequentially store all A/D converted values. - * The automatic clear function is not applied to these registers. */ - } ADBUF15_b; - }; - - union - { - __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ - - struct - { - __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ - uint8_t : 7; - } ADBUFEN_b; - }; - __IM uint8_t RESERVED13; - - union - { - __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ - - struct - { - __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of - * data buffer to which the next A/D converted data is transferred. */ - __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ - uint8_t : 3; - } ADBUFPTR_b; - }; - __IM uint8_t RESERVED14; - __IM uint32_t RESERVED15[2]; - __IM uint8_t RESERVED16; - - union - { - __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ - } ADSSTRL_b; - }; - - union - { - __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ - } ADSSTRT_b; - }; - - union - { - __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ - } ADSSTRO_b; - }; - - union - { - __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ - - struct - { - __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ - } ADSSTR_b[16]; - }; - - union - { - __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ - - struct - { - __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ - __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ - uint16_t : 12; - } ADANIM_b; - }; - - union - { - __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ - - struct - { - uint8_t : 6; - __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ - __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ - } ADCALEXE_b; - }; - __IM uint8_t RESERVED17; - - union - { - __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control - * Register */ - - struct - { - __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ - __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ - __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ - __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ - uint8_t : 2; - __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ - } VREFAMPCNT_b; - }; - __IM uint8_t RESERVED18; - __IM uint16_t RESERVED19; - - union - { - __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ - - struct - { - __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ - } ADRD_b; - }; - - union - { - __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ - - struct - { - __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ - uint8_t : 6; - } ADRST_b; - }; - __IM uint8_t RESERVED20; - __IM uint32_t RESERVED21[41]; - - union - { - __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ - - struct - { - __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ - __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ - __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ - __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ - __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ - __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ - __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ - __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ - __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ - __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ - __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ - __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ - __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ - __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ - __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ - __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ - } ADPGACR_b; - }; - - union - { - __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting - * Register 0 */ - - struct - { - __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= - * b) when the shingle end is input and each PGA P000 is set. - * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P000DG 1:0. */ - __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= - * b) when the shingle end is input and each PGA P001 is set. - * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) - * sets the gain magnification when the differential motion - * is input by the combination with ADPGSDCR0.P001DG 1:0. */ - __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of - * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and - * each PGA P002 is set. When the differential motion is input, - * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P002DG 1:0. */ - __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of - * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and - * each PGA P003 is set. When the differential motion is input, - * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when - * the differential motion is input by the combination with - * ADPGSDCR0.P003DG 1:0. */ - } ADPGAGS0_b; - }; - __IM uint32_t RESERVED22[3]; - - union - { - __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential - * Input Control Register */ - - struct - { - __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these - * bits are used, set {P000DEN, P000GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ - __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these - * bits are used, set {P001DEN, P001GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ - __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these - * bits are used, set {P002DEN, P002GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ - __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these - * bits are used, set {P003DEN, P003GEN} to 11b. */ - uint16_t : 1; - __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ - } ADPGADCR0_b; - }; - __IM uint16_t RESERVED23; - - union - { - __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 0 */ + __IM uint8_t TZFERRRW; /*!< (@ 0x00000004) BUS TZF Error Read Write Register */ struct { - __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage - * SelectNOTE: This bit selects the input bias voltage value - * when differential inputs are used. */ + __IM uint8_t TRWSTAT : 1; /*!< [0..0] TrustZone filter Error access statusThe status at the + * time of the error */ uint8_t : 7; - } ADPGADBS0_b; + } TZFERRRW_b; }; + __IM uint8_t RESERVED; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[2]; +} R_BUS_B_BUSTZFERR_Type; /*!< Size = 16 (0x10) */ - union - { - __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential - * Input Bias Select Register 1 */ - - struct - { - __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: - * This bit selects the input bias voltage value when differential - * inputs are used. */ - uint8_t : 7; - } ADPGADBS1_b; - }; - __IM uint16_t RESERVED24; - __IM uint32_t RESERVED25[10]; +/** @} */ /* End of group Device_Peripheral_clusters */ - union - { - __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ +/* =========================================================================================================================== */ +/* ================ Device Specific Peripheral Section ================ */ +/* =========================================================================================================================== */ - struct - { - __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ - uint32_t : 13; - __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ - uint32_t : 12; - } ADREFMON_b; - }; -} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ +/** @addtogroup Device_Peripheral_peripherals + * @{ + */ /* =========================================================================================================================== */ -/* ================ R_PSCU ================ */ +/* ================ R_ACMPHS0 ================ */ /* =========================================================================================================================== */ /** - * @brief Peripheral Security Control Unit (R_PSCU) + * @brief High-Speed Analog Comparator (R_ACMPHS0) */ -typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ +typedef struct /*!< (@ 0x400F4000) R_ACMPHS0 Structure */ { - __IM uint32_t RESERVED; - - union - { - __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ - - struct - { - uint32_t : 1; - __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ - __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ - __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ - uint32_t : 2; - __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ - __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ - __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ - __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ - __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ - uint32_t : 2; - __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 - * bit security attribution */ - __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ - __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ - __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ - __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ - __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ - __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ - __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ - __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ - __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ - __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ - __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ - } PSARB_b; - }; - - union - { - __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ - - struct - { - __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ - __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ - uint32_t : 4; - __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ - __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ - uint32_t : 3; - __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ - } PSARC_b; - }; - - union - { - __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ - - struct - { - __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ - __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ - __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ - __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ - uint32_t : 7; - __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ - __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ - __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ - __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ - __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ - __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ - __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ - uint32_t : 1; - __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ - uint32_t : 2; - __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ - __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ - __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ - __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ - uint32_t : 3; - } PSARD_b; - }; - - union - { - __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ - - struct - { - __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ - __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ - __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ - uint32_t : 11; - __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ - __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ - uint32_t : 6; - __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ - __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ - __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ - __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ - __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ - __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ - __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ - __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ - __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ - __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ - } PSARE_b; - }; - - union - { - __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ - - struct - { - __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ - __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ - __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ - __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ - uint32_t : 28; - } MSSAR_b; - }; - - union - { - __IM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register - * A */ - - struct - { - uint32_t : 15; - __IM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ - uint32_t : 8; - } CFSAMONA_b; - }; - union { - __IM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register - * B */ + __IOM uint8_t CMPCTL; /*!< (@ 0x00000000) Comparator Control Register */ struct { - uint32_t : 10; - __IM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ - uint32_t : 8; - } CFSAMONB_b; + __IOM uint8_t CINV : 1; /*!< [0..0] Comparator output polarity selection */ + __IOM uint8_t COE : 1; /*!< [1..1] Comparator output enable */ + __IOM uint8_t CSTEN : 1; /*!< [2..2] Interrupt Select */ + __IOM uint8_t CEG : 2; /*!< [4..3] Selection of valid edge (Edge selector) */ + __IOM uint8_t CDFS : 2; /*!< [6..5] Noise filter selection */ + __IOM uint8_t HCMPON : 1; /*!< [7..7] Comparator operation control */ + } CMPCTL_b; }; + __IM uint8_t RESERVED[3]; union { - __IM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ - - struct - { - uint32_t : 10; - __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ - uint32_t : 16; - } DFSAMON_b; + __IOM uint8_t CMPSEL0; /*!< (@ 0x00000004) Comparator Input Select Register */ + + struct + { + __IOM uint8_t CMPSEL : 4; /*!< [3..0] Comparator Input Selection */ + uint8_t : 4; + } CMPSEL0_b; }; + __IM uint8_t RESERVED1[3]; union { - __IM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ + __IOM uint8_t CMPSEL1; /*!< (@ 0x00000008) Comparator Reference Voltage Select Register */ struct { - uint32_t : 13; - __IM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ - uint32_t : 11; - } SSAMONA_b; + __IOM uint8_t CRVS : 6; /*!< [5..0] Reference Voltage Selection */ + uint8_t : 2; + } CMPSEL1_b; }; + __IM uint8_t RESERVED2[3]; union { - __IM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ + __IM uint8_t CMPMON; /*!< (@ 0x0000000C) Comparator Output Monitor Register */ struct { - uint32_t : 10; - __IM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ - uint32_t : 11; - } SSAMONB_b; + __IM uint8_t CMPMON : 1; /*!< [0..0] Comparator output monitor */ + uint8_t : 7; + } CMPMON_b; }; + __IM uint8_t RESERVED3[3]; union { - __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ + __IOM uint8_t CPIOC; /*!< (@ 0x00000010) Comparator Output Control Register */ struct { - __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ - uint32_t : 28; - } DLMMON_b; + __IOM uint8_t CPOE : 1; /*!< [0..0] Comparator output selection */ + uint8_t : 6; + __IOM uint8_t VREFEN : 1; /*!< [7..7] Internal Vref enable */ + } CPIOC_b; }; -} R_PSCU_Type; /*!< Size = 48 (0x30) */ +} R_ACMPHS0_Type; /*!< Size = 17 (0x11) */ /* =========================================================================================================================== */ -/* ================ R_AGTW0 ================ */ +/* ================ R_ADC0 ================ */ /* =========================================================================================================================== */ /** - * @brief Asynchronous General Purpose Timer (R_AGTW0) + * @brief A/D Converter (R_ADC0) */ -typedef struct /*!< (@ 0x400E8000) R_AGTW0 Structure */ +typedef struct /*!< (@ 0x40170000) R_ADC0 Structure */ { union { - __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ + __IOM uint16_t ADCSR; /*!< (@ 0x00000000) A/D Control Register */ struct { - __IOM uint32_t AGT : 32; /*!< [31..0] 16bit counter and reload registerNOTE : When 1 is written - * to the TSTOP bit in the AGTCRn register, the 16-bit counter - * is forcibly stopped and set to FFFFH. */ - } AGT_b; + __IOM uint16_t DBLANS : 5; /*!< [4..0] Double Trigger Channel SelectThese bits select one analog + * input channel for double triggered operation. The setting + * is only effective while double trigger mode is selected. */ + uint16_t : 1; + __IOM uint16_t GBADIE : 1; /*!< [6..6] Group B Scan End Interrupt Enable */ + __IOM uint16_t DBLE : 1; /*!< [7..7] Double Trigger Mode Select */ + __IOM uint16_t EXTRG : 1; /*!< [8..8] Trigger Select */ + __IOM uint16_t TRGE : 1; /*!< [9..9] Trigger Start Enable */ + __IOM uint16_t ADHSC : 1; /*!< [10..10] A/D Conversion Operation Mode Select */ + uint16_t : 1; + __IOM uint16_t ADIE : 1; /*!< [12..12] Scan End Interrupt Enable */ + __IOM uint16_t ADCS : 2; /*!< [14..13] Scan Mode Select */ + __IOM uint16_t ADST : 1; /*!< [15..15] A/D Conversion Start */ + } ADCSR_b; }; union { - __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ + __IOM uint8_t ADREF; /*!< (@ 0x00000002) A/D status register */ struct { - __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCRn register, set to - * FFFFH */ - } AGTCMA_b; + __IOM uint8_t ADF : 1; /*!< [0..0] Scanning end flag bitThis bit is a status bit that becomes + * '1' while scanning. */ + uint8_t : 6; + __IM uint8_t ADSCACT : 1; /*!< [7..7] Scanning status bit */ + } ADREF_b; }; union { - __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ + __IOM uint8_t ADEXREF; /*!< (@ 0x00000003) A/D enhancing status register */ struct { - __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is - * written to the TSTOP bit in the AGTCR register, set to - * FFFFH */ - } AGTCMB_b; + __IOM uint8_t GBADF : 1; /*!< [0..0] Group B scanning end flag bit. */ + uint8_t : 7; + } ADEXREF_b; }; union { - __IOM uint8_t AGTCR; /*!< (@ 0x0000000C) AGT Control Register */ + __IOM uint16_t ADANSA[2]; /*!< (@ 0x00000004) A/D Channel Select Register */ struct { - __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ - __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ - __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ - uint8_t : 1; - __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ - __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ - __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ - __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ - } AGTCR_b; + __IOM uint16_t ANSA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSA15 : 1; /*!< [15..15] AN Input Select */ + } ADANSA_b[2]; }; union { - __IOM uint8_t AGTMR1; /*!< (@ 0x0000000D) AGT Mode Register 1 */ + __IOM uint16_t ADADS[2]; /*!< (@ 0x00000008) A/D-Converted Value Addition/Average Channel + * Select Register */ struct { - __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ - __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ - __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ - uint8_t : 1; - } AGTMR1_b; + __IOM uint16_t ADS0 : 1; /*!< [0..0] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS1 : 1; /*!< [1..1] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS2 : 1; /*!< [2..2] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS3 : 1; /*!< [3..3] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS4 : 1; /*!< [4..4] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS5 : 1; /*!< [5..5] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS6 : 1; /*!< [6..6] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS7 : 1; /*!< [7..7] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS8 : 1; /*!< [8..8] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS9 : 1; /*!< [9..9] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS10 : 1; /*!< [10..10] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS11 : 1; /*!< [11..11] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS12 : 1; /*!< [12..12] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS13 : 1; /*!< [13..13] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS14 : 1; /*!< [14..14] A/D-Converted Value Addition/Average Channel Select */ + __IOM uint16_t ADS15 : 1; /*!< [15..15] A/D-Converted Value Addition/Average Channel Select */ + } ADADS_b[2]; }; union { - __IOM uint8_t AGTMR2; /*!< (@ 0x0000000E) AGT Mode Register 2 */ + __IOM uint8_t ADADC; /*!< (@ 0x0000000C) A/D-Converted Value Addition/Average Count Select + * Register */ struct { - __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division - * ratio */ - uint8_t : 4; - __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ - } AGTMR2_b; + __IOM uint8_t ADC : 3; /*!< [2..0] Addition frequency selection bit.NOTE: AVEE bit is valid + * at the only setting of ADC[2:0] bits = 001b or 011b. When + * average mode is selected by setting the ADADC.AVEE bit + * to 1, do not set the addition count to three times (ADADC.ADC[2:0] + * = 010b) */ + uint8_t : 4; + __IOM uint8_t AVEE : 1; /*!< [7..7] Average Mode Enable. NOTE:When average mode is deselected + * by setting the ADADC.AVEE bit to 0, set the addition count + * to 1, 2, 3, 4 or 16-time conversion. 16-time conversion + * can only be used with 12-bit accuracy selected. NOTE: AVEE + * bit is valid at the only setting of ADC[2:0] bits = 001b + * or 011b. When average mode is selected by setting the ADADC.AVEE + * bit to 1, do not set the addition count to three times + * (ADADC.ADC[2:0] = 010b) */ + } ADADC_b; }; __IM uint8_t RESERVED; union { - __IOM uint8_t AGTIOC; /*!< (@ 0x00000010) AGT I/O Control Register */ + __IOM uint16_t ADCER; /*!< (@ 0x0000000E) A/D Control Extended Register */ struct { - __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + uint16_t : 1; + __IOM uint16_t ADPRC : 2; /*!< [2..1] A/D Conversion Accuracy Specify */ + uint16_t : 1; + __IOM uint16_t DCE : 1; /*!< [4..4] Discharge Enable */ + __IOM uint16_t ACE : 1; /*!< [5..5] A/D Data Register Automatic Clearing Enable */ + uint16_t : 2; + __IOM uint16_t DIAGVAL : 2; /*!< [9..8] Self-Diagnosis Conversion Voltage Select */ + __IOM uint16_t DIAGLD : 1; /*!< [10..10] Self-Diagnosis Mode Select */ + __IOM uint16_t DIAGM : 1; /*!< [11..11] Self-Diagnosis Enable */ + uint16_t : 2; + __IOM uint16_t ADINV : 1; /*!< [14..14] Single-Ended Input A/D Converted Data Inversion Select */ + __IOM uint16_t ADRFMT : 1; /*!< [15..15] A/D Data Register Format Select */ + } ADCER_b; + }; + + union + { + __IOM uint16_t ADSTRGR; /*!< (@ 0x00000010) A/D Conversion Start Trigger Select Register */ + + struct + { + __IOM uint16_t TRSB : 6; /*!< [5..0] A/D Conversion Start Trigger Select for Group BSelect + * the A/D conversion start trigger for group B in group scan * mode. */ - uint8_t : 1; - __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ - uint8_t : 1; - __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ - __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ - } AGTIOC_b; + uint16_t : 2; + __IOM uint16_t TRSA : 6; /*!< [13..8] A/D Conversion Start Trigger SelectSelect the A/D conversion + * start trigger in single scan mode and continuous mode. + * In group scan mode, the A/D conversion start trigger for + * group A is selected. */ + uint16_t : 2; + } ADSTRGR_b; }; union { - __IOM uint8_t AGTISR; /*!< (@ 0x00000011) AGT Event Pin Select Register */ + __IOM uint16_t ADEXICR; /*!< (@ 0x00000012) A/D Conversion Extended Input Control Register */ struct { - uint8_t : 2; - __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ - uint8_t : 5; - } AGTISR_b; + __IOM uint16_t TSSAD : 1; /*!< [0..0] Temperature Sensor Output A/D converted Value Addition/Average + * Mode Select */ + __IOM uint16_t OCSAD : 1; /*!< [1..1] Internal Reference Voltage A/D converted Value Addition/Average + * Mode Select */ + uint16_t : 6; + __IOM uint16_t TSSA : 1; /*!< [8..8] Temperature Sensor Output A/D Conversion Select */ + __IOM uint16_t OCSA : 1; /*!< [9..9] Internal Reference Voltage A/D Conversion Select */ + __IOM uint16_t TSSB : 1; /*!< [10..10] Temperature Sensor Output A/D Conversion Select for + * Group B in group scan mode. */ + __IOM uint16_t OCSB : 1; /*!< [11..11] Internal Reference Voltage A/D Conversion Select for + * Group B in group scan mode. */ + uint16_t : 2; + __IOM uint16_t EXSEL : 1; /*!< [14..14] Extended Analog Input Select */ + __IOM uint16_t EXOEN : 1; /*!< [15..15] Extended Analog Output Control */ + } ADEXICR_b; }; union { - __IOM uint8_t AGTCMSR; /*!< (@ 0x00000012) AGT Compare Match Function Select Register */ + __IOM uint16_t ADANSB[2]; /*!< (@ 0x00000014) A/D Channel Select Register B */ struct { - __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ - __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ - __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ - uint8_t : 1; - __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ - __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ - __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ - uint8_t : 1; - } AGTCMSR_b; + __IOM uint16_t ANSB0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t ANSB1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t ANSB2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t ANSB3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t ANSB4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t ANSB5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t ANSB6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t ANSB7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t ANSB8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t ANSB9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t ANSB10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t ANSB11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t ANSB12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t ANSB13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t ANSB14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t ANSB15 : 1; /*!< [15..15] AN Input Select */ + } ADANSB_b[2]; + }; + + union + { + __IM uint16_t ADDBLDR; /*!< (@ 0x00000018) A/D Data Duplication Register */ + + struct + { + __IM uint16_t ADDBLDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * result of A/D conversion in response to the second trigger + * in double trigger mode. */ + } ADDBLDR_b; }; union { - __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000013) AGT Pin Select Register */ + __IM uint16_t ADTSDR; /*!< (@ 0x0000001A) A/D Temperature Sensor Data Register */ struct { - uint8_t : 4; - __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ - uint8_t : 3; - } AGTIOSEL_b; + __IM uint16_t ADTSDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D conversion result of temperature sensor output. */ + } ADTSDR_b; }; -} R_AGTW0_Type; /*!< Size = 20 (0x14) */ - -/* =========================================================================================================================== */ -/* ================ R_BUS ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Bus Interface (R_BUS) - */ - -typedef struct /*!< (@ 0x40003000) R_BUS Structure */ -{ - __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ - __IM uint32_t RESERVED[480]; - __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + __IM uint16_t ADOCDR; /*!< (@ 0x0000001C) A/D Internal Reference Voltage Data Register */ struct { - __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ - __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ - } CSRECEN_b; + __IM uint16_t ADOCDR : 16; /*!< [15..0] This is a 16-bit read-only register for storing the + * A/D result of internal reference voltage. */ + } ADOCDR_b; }; - __IM uint16_t RESERVED1; - __IM uint32_t RESERVED2[223]; - __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ - __IM uint32_t RESERVED3[235]; - __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ - __IM uint32_t RESERVED4[58]; - __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ - __IM uint32_t RESERVED5[432]; - __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ -} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ -/* =========================================================================================================================== */ -/* ================ R_CAC ================ */ -/* =========================================================================================================================== */ + union + { + union + { + __IM uint16_t ADRD_RIGHT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Right Justified */ -/** - * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) - */ + struct + { + __IM uint16_t AD : 14; /*!< [13..0] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + __IM uint16_t DIAGST : 2; /*!< [15..14] Self-Diagnosis Status */ + } ADRD_RIGHT_b; + }; + + union + { + __IM uint16_t ADRD_LEFT; /*!< (@ 0x0000001E) A/D Self-Diagnosis Data Register Left Justified */ + + struct + { + __IM uint16_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + __IM uint16_t AD : 14; /*!< [15..2] A/D-converted value (right-justified)The format for + * data determine ADCER.ADRFMT and ADCER.ADPRC. */ + } ADRD_LEFT_b; + }; + }; -typedef struct /*!< (@ 0x40083600) R_CAC Structure */ -{ union { - __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ + __IM uint16_t ADDR[28]; /*!< (@ 0x00000020) A/D Data Register */ struct { - __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ - uint8_t : 7; - } CACR0_b; + __IM uint16_t ADDR : 16; /*!< [15..0] The ADDR register is a 16-bit read-only registers for + * storing the result of A/D conversion. */ + } ADDR_b[28]; }; + __IM uint32_t RESERVED1[2]; + __IM uint16_t RESERVED2; union { - __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ + __IOM uint8_t ADAMPOFF; /*!< (@ 0x00000062) A/D RRAMP off state register */ struct { - __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ - __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ - __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ - __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ - } CACR1_b; + __IOM uint8_t OPOFF : 8; /*!< [7..0] OPOFF */ + } ADAMPOFF_b; }; union { - __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ + __IOM uint8_t ADTSTPR; /*!< (@ 0x00000063) A/D Test Protecting Release Register */ struct { - __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ - __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ - __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio - * Select */ - __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ - } CACR2_b; + __IOM uint8_t PRO : 1; /*!< [0..0] Test register protecting bit. */ + __IOM uint8_t B0WI : 1; /*!< [1..1] Bit 0 writing permission bit. */ + uint8_t : 6; + } ADTSTPR_b; }; union { - __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ + __IOM uint16_t ADDDACER; /*!< (@ 0x00000064) A/D RRAMP Discharge Period Register */ struct { - __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ - __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ - __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ - uint8_t : 1; - __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ - __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ - __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ - uint8_t : 1; - } CAICR_b; + __IOM uint16_t WRION : 5; /*!< [4..0] WRION */ + uint16_t : 3; + __IOM uint16_t WRIOFF : 5; /*!< [12..8] WRIOFF */ + uint16_t : 2; + __IOM uint16_t ADHS : 1; /*!< [15..15] ADHS */ + } ADDDACER_b; }; union { - __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ + __IOM uint16_t ADSHCR; /*!< (@ 0x00000066) A/D Sample and Hold Circuit Control Register */ struct { - __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ - __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ - __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ - uint8_t : 5; - } CASTR_b; + __IOM uint16_t SSTSH : 8; /*!< [7..0] Channel-Dedicated Sample-and-Hold Circuit Sampling Time + * Setting Set the sampling time (4 to 255 states) */ + __IOM uint16_t SHANS0 : 1; /*!< [8..8] AN000 sample-and-hold circuit Select */ + __IOM uint16_t SHANS1 : 1; /*!< [9..9] AN001 sample-and-hold circuit Select */ + __IOM uint16_t SHANS2 : 1; /*!< [10..10] AN002 sample-and-hold circuit Select */ + uint16_t : 5; + } ADSHCR_b; }; - __IM uint8_t RESERVED; union { - __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + __IOM uint16_t ADEXTSTR; /*!< (@ 0x00000068) A/D Enhancing Test Register */ struct { - __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores - * the upper-limit value of the frequency. */ - } CAULVR_b; + __IOM uint16_t SHTEST : 3; /*!< [2..0] Test mode bit for S&H circuit.Test mode bit of S&H circuit + * only for channel. */ + uint16_t : 1; + __IOM uint16_t SWTST : 2; /*!< [5..4] Test selection bit for pressure switch. */ + uint16_t : 2; + __IOM uint16_t SHTRM : 2; /*!< [9..8] Current adjustment trim bit for S&H circuit.Trim bit + * for adjustment to hardening of process. */ + uint16_t : 1; + __IOM uint16_t ADTRM3 : 1; /*!< [11..11] Trim bit 3 for A/D hard macro.3bit Flash comparator + * power save bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM2 : 2; /*!< [13..12] Trim bit 2 for A/D hard macro.Bias adjustment trim + * bit for A/D hard macro to hardening of process. */ + __IOM uint16_t ADTRM1 : 2; /*!< [15..14] Trim bit 1 for A/D hard macro.Timing adjustment trim + * bit for A/D hard macro to hardening of process. */ + } ADEXTSTR_b; }; union { - __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ + __IOM uint16_t ADTSTRA; /*!< (@ 0x0000006A) A/D Test Register A */ struct { - __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores - * the lower-limit value of the frequency. */ - } CALLVR_b; + __IOM uint16_t ATBUSSEL : 1; /*!< [0..0] Analog test bus selection bit. */ + __IOM uint16_t TSTSWREF : 3; /*!< [3..1] Pressure switch refreshing setting bit for S&H circuit + * amplifier test.Refreshing the pressure switch that opens + * for the DAC output voltage charge period when the amplifier + * of the S&H circuit is tested only for the channel is set. */ + uint16_t : 1; + __IOM uint16_t OCSW : 1; /*!< [5..5] Internal reference voltage analog switch test control + * bit. */ + __IOM uint16_t TSSW : 1; /*!< [6..6] Temperature sensor output analogue switch test control + * bit */ + uint16_t : 1; + __IOM uint16_t ADTEST_AD : 4; /*!< [11..8] Test bit for A/D analog module Bit for test of A/D analog + * module Details are described to the bit explanation. */ + __IOM uint16_t ADTEST_IO : 4; /*!< [15..12] Test bit for analog I/ODetails are described to the + * bit explanation. */ + } ADTSTRA_b; }; union { - __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ + __IOM uint16_t ADTSTRB; /*!< (@ 0x0000006C) A/D Test Register B */ struct { - __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains - * the counter value at the time a valid reference signal - * edge is input */ - } CACNTBR_b; + __IOM uint16_t ADVAL : 15; /*!< [14..0] Signal input bit bit14-0 for A/D analog module test.It + * corresponds to ADVAL 14:0 input of A/D analog module. */ + uint16_t : 1; + } ADTSTRB_b; }; -} R_CAC_Type; /*!< Size = 12 (0xc) */ - -/* =========================================================================================================================== */ -/* ================ R_CAN0 ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Controller Area Network (CAN) Module (R_CAN0) - */ - -typedef struct /*!< (@ 0x400A8000) R_CAN0 Structure */ -{ - __IM uint32_t RESERVED[128]; - __IOM R_CAN0_MB_Type MB[32]; /*!< (@ 0x00000200) Mailbox */ union { - __IOM uint32_t MKR[8]; /*!< (@ 0x00000400) Mask Register */ + __IOM uint16_t ADTSTRC; /*!< (@ 0x0000006E) A/D Test Register C */ struct { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 3; - } MKR_b[8]; + __IOM uint16_t ADMD : 8; /*!< [7..0] Bit for A/D analog module test.ADMODE 6:0 input of A/D + * analog module. */ + uint16_t : 4; + __IOM uint16_t SYNCERR : 1; /*!< [12..12] Synchronous analog to digital conversion error bit. */ + uint16_t : 3; + } ADTSTRC_b; }; union { - __IOM uint32_t FIDCR[2]; /*!< (@ 0x00000420) FIFO Received ID Compare Registers */ + __IOM uint16_t ADTSTRD; /*!< (@ 0x00000070) A/D Test Register D */ struct { - __IOM uint32_t EID : 18; /*!< [17..0] Extended ID */ - __IOM uint32_t SID : 11; /*!< [28..18] Standard ID */ - uint32_t : 1; - __IOM uint32_t RTR : 1; /*!< [30..30] Remote Transmission Request */ - __IOM uint32_t IDE : 1; /*!< [31..31] ID Extension */ - } FIDCR_b[2]; + __IOM uint16_t ADVAL16 : 1; /*!< [0..0] Signal input bit bit16 for A/D analog module test.It + * corresponds to ADVAL 16 input of A/D analog module. */ + uint16_t : 15; + } ADTSTRD_b; }; union { - __IOM uint32_t MKIVLR; /*!< (@ 0x00000428) Mask Invalid Register */ + __IOM uint16_t ADSWTSTR0; /*!< (@ 0x00000072) A/D Channel Switch Test Control Register 0 */ struct { - __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Mask Invalid */ - __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Mask Invalid */ - __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Mask Invalid */ - __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Mask Invalid */ - __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Mask Invalid */ - __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Mask Invalid */ - __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Mask Invalid */ - __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Mask Invalid */ - __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Mask Invalid */ - __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Mask Invalid */ - __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Mask Invalid */ - __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Mask Invalid */ - __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Mask Invalid */ - __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Mask Invalid */ - __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Mask Invalid */ - __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Mask Invalid */ - __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Mask Invalid */ - __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Mask Invalid */ - __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Mask Invalid */ - __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Mask Invalid */ - __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Mask Invalid */ - __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Mask Invalid */ - __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Mask Invalid */ - __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Mask Invalid */ - __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Mask Invalid */ - __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Mask Invalid */ - __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Mask Invalid */ - __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Mask Invalid */ - __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Mask Invalid */ - __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Mask Invalid */ - __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Mask Invalid */ - __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Mask Invalid */ - } MKIVLR_b; + __IOM uint16_t CHSW00 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW01 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW02 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW03 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW04 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW05 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR0_b; }; union { - union - { - __IOM uint32_t MIER; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register */ - - struct - { - __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ - __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ - __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ - __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ - __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ - __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ - __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ - __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ - __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ - __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ - __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ - __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ - __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ - __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ - __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ - __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ - __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ - __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ - __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ - __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ - __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ - __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ - __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ - __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ - __IOM uint32_t MB24 : 1; /*!< [24..24] mailbox 24 Interrupt Enable */ - __IOM uint32_t MB25 : 1; /*!< [25..25] mailbox 25 Interrupt Enable */ - __IOM uint32_t MB26 : 1; /*!< [26..26] mailbox 26 Interrupt Enable */ - __IOM uint32_t MB27 : 1; /*!< [27..27] mailbox 27 Interrupt Enable */ - __IOM uint32_t MB28 : 1; /*!< [28..28] mailbox 28 Interrupt Enable */ - __IOM uint32_t MB29 : 1; /*!< [29..29] mailbox 29 Interrupt Enable */ - __IOM uint32_t MB30 : 1; /*!< [30..30] mailbox 30 Interrupt Enable */ - __IOM uint32_t MB31 : 1; /*!< [31..31] mailbox 31 Interrupt Enable */ - } MIER_b; - }; + __IOM uint16_t ADSWTSTR1; /*!< (@ 0x00000074) A/D Channel Switch Test Control Register 1 */ - union + struct { - __IOM uint32_t MIER_FIFO; /*!< (@ 0x0000042C) Mailbox Interrupt Enable Register for FIFO Mailbox - * Mode */ - - struct - { - __IOM uint32_t MB0 : 1; /*!< [0..0] mailbox 0 Interrupt Enable */ - __IOM uint32_t MB1 : 1; /*!< [1..1] mailbox 1 Interrupt Enable */ - __IOM uint32_t MB2 : 1; /*!< [2..2] mailbox 2 Interrupt Enable */ - __IOM uint32_t MB3 : 1; /*!< [3..3] mailbox 3 Interrupt Enable */ - __IOM uint32_t MB4 : 1; /*!< [4..4] mailbox 4 Interrupt Enable */ - __IOM uint32_t MB5 : 1; /*!< [5..5] mailbox 5 Interrupt Enable */ - __IOM uint32_t MB6 : 1; /*!< [6..6] mailbox 6 Interrupt Enable */ - __IOM uint32_t MB7 : 1; /*!< [7..7] mailbox 7 Interrupt Enable */ - __IOM uint32_t MB8 : 1; /*!< [8..8] mailbox 8 Interrupt Enable */ - __IOM uint32_t MB9 : 1; /*!< [9..9] mailbox 9 Interrupt Enable */ - __IOM uint32_t MB10 : 1; /*!< [10..10] mailbox 10 Interrupt Enable */ - __IOM uint32_t MB11 : 1; /*!< [11..11] mailbox 11 Interrupt Enable */ - __IOM uint32_t MB12 : 1; /*!< [12..12] mailbox 12 Interrupt Enable */ - __IOM uint32_t MB13 : 1; /*!< [13..13] mailbox 13 Interrupt Enable */ - __IOM uint32_t MB14 : 1; /*!< [14..14] mailbox 14 Interrupt Enable */ - __IOM uint32_t MB15 : 1; /*!< [15..15] mailbox 15 Interrupt Enable */ - __IOM uint32_t MB16 : 1; /*!< [16..16] mailbox 16 Interrupt Enable */ - __IOM uint32_t MB17 : 1; /*!< [17..17] mailbox 17 Interrupt Enable */ - __IOM uint32_t MB18 : 1; /*!< [18..18] mailbox 18 Interrupt Enable */ - __IOM uint32_t MB19 : 1; /*!< [19..19] mailbox 19 Interrupt Enable */ - __IOM uint32_t MB20 : 1; /*!< [20..20] mailbox 20 Interrupt Enable */ - __IOM uint32_t MB21 : 1; /*!< [21..21] mailbox 21 Interrupt Enable */ - __IOM uint32_t MB22 : 1; /*!< [22..22] mailbox 22 Interrupt Enable */ - __IOM uint32_t MB23 : 1; /*!< [23..23] mailbox 23 Interrupt Enable */ - __IOM uint32_t MB24 : 1; /*!< [24..24] Transmit FIFO Interrupt Enable */ - __IOM uint32_t MB25 : 1; /*!< [25..25] Transmit FIFO Interrupt Generation Timing Control */ - uint32_t : 2; - __IOM uint32_t MB28 : 1; /*!< [28..28] Receive FIFO Interrupt Enable */ - __IOM uint32_t MB29 : 1; /*!< [29..29] Receive FIFO Interrupt Generation Timing Control */ - uint32_t : 2; - } MIER_FIFO_b; - }; + __IOM uint16_t CHSW16 : 1; /*!< [0..0] Channel switch test control bit. */ + __IOM uint16_t CHSW17 : 1; /*!< [1..1] Channel switch test control bit. */ + __IOM uint16_t CHSW18 : 1; /*!< [2..2] Channel switch test control bit. */ + __IOM uint16_t CHSW19 : 1; /*!< [3..3] Channel switch test control bit. */ + __IOM uint16_t CHSW20 : 1; /*!< [4..4] Channel switch test control bit. */ + __IOM uint16_t CHSW21 : 1; /*!< [5..5] Channel switch test control bit. */ + uint16_t : 10; + } ADSWTSTR1_b; }; - __IM uint32_t RESERVED1[252]; union { - union - { - __IOM uint8_t MCTL_TX[32]; /*!< (@ 0x00000820) Message Control Register for Transmit */ - - struct - { - __IOM uint8_t SENTDATA : 1; /*!< [0..0] Transmission Complete Flag */ - __IM uint8_t TRMACTIVE : 1; /*!< [1..1] Transmission-in-Progress Status Flag (Transmit mailbox - * setting enabled) */ - __IOM uint8_t TRMABT : 1; /*!< [2..2] Transmission Abort Complete Flag (Transmit mailbox setting - * enabled) */ - uint8_t : 1; - __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ - uint8_t : 1; - __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ - __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ - } MCTL_TX_b[32]; - }; + __IOM uint16_t ADSWTSTR2; /*!< (@ 0x00000076) A/D Channel Switch Test Control Register 2 */ - union + struct { - __IOM uint8_t MCTL_RX[32]; /*!< (@ 0x00000820) Message Control Register for Receive */ - - struct - { - __IOM uint8_t NEWDATA : 1; /*!< [0..0] Reception Complete Flag */ - __IM uint8_t INVALDATA : 1; /*!< [1..1] Reception-in-Progress Status Flag (Receive mailbox setting - * enabled) */ - __IOM uint8_t MSGLOST : 1; /*!< [2..2] Message Lost Flag(Receive mailbox setting enabled) */ - uint8_t : 1; - __IOM uint8_t ONESHOT : 1; /*!< [4..4] One-Shot Enable */ - uint8_t : 1; - __IOM uint8_t RECREQ : 1; /*!< [6..6] Receive Mailbox Request */ - __IOM uint8_t TRMREQ : 1; /*!< [7..7] Transmit Mailbox Request */ - } MCTL_RX_b[32]; - }; + __IOM uint16_t EX0SW : 1; /*!< [0..0] Test control of 0 enhancing input channel switches bit + * (ANEX0 switch) */ + __IOM uint16_t EX1SW : 1; /*!< [1..1] Test control of one enhancing input channel switch bit + * (ANEX1 switch). */ + uint16_t : 2; + __IOM uint16_t SHBYPS0 : 1; /*!< [4..4] S&H circuit by-pass switch control bit 0. */ + __IOM uint16_t SHBYPS1 : 1; /*!< [5..5] S&H circuit by-pass switch control bit 1. */ + __IOM uint16_t SHBYPS2 : 1; /*!< [6..6] S&H circuit by-pass switch control bit 2. */ + uint16_t : 1; + __IOM uint16_t GRP0SW : 1; /*!< [8..8] Test control of 0 group switches bit. */ + __IOM uint16_t GRP1SW : 1; /*!< [9..9] Test control of one group switch bit. */ + __IOM uint16_t GRP2SW : 1; /*!< [10..10] Test control of two group switches bit */ + __IOM uint16_t GRP3SW : 1; /*!< [11..11] Test control of two group switches bit */ + __IOM uint16_t GRPEX1SW : 1; /*!< [12..12] Switch test control bit of enhancing analog ANEX1 */ + uint16_t : 3; + } ADSWTSTR2_b; }; + __IM uint16_t RESERVED3; union { - __IOM uint16_t CTLR; /*!< (@ 0x00000840) Control Register */ + __IOM uint8_t ADDISCR; /*!< (@ 0x0000007A) A/D Disconnection Detection Control Register */ struct { - __IOM uint16_t MBM : 1; /*!< [0..0] CAN Mailbox Mode Select */ - __IOM uint16_t IDFM : 2; /*!< [2..1] ID Format Mode Select */ - __IOM uint16_t MLM : 1; /*!< [3..3] Message Lost Mode Select */ - __IOM uint16_t TPM : 1; /*!< [4..4] Transmission Priority Mode Select */ - __IOM uint16_t TSRC : 1; /*!< [5..5] Time Stamp Counter Reset Command */ - __IOM uint16_t TSPS : 2; /*!< [7..6] Time Stamp Prescaler Select */ - __IOM uint16_t CANM : 2; /*!< [9..8] CAN Operating Mode Select */ - __IOM uint16_t SLPM : 1; /*!< [10..10] CAN Sleep Mode */ - __IOM uint16_t BOM : 2; /*!< [12..11] Bus-Off Recovery Mode by a program request */ - __IOM uint16_t RBOC : 1; /*!< [13..13] Forcible Return From Bus-Off */ - uint16_t : 2; - } CTLR_b; + __IOM uint8_t ADNDIS : 4; /*!< [3..0] The charging time */ + __IOM uint8_t CHARGE : 1; /*!< [4..4] Selection of Precharge or Discharge */ + uint8_t : 3; + } ADDISCR_b; }; union { - __IM uint16_t STR; /*!< (@ 0x00000842) Status Register */ + __IOM uint8_t ADSWCR; /*!< (@ 0x0000007B) A/D Pressure Switch Control Register */ struct { - __IM uint16_t NDST : 1; /*!< [0..0] NEWDATA Status Flag */ - __IM uint16_t SDST : 1; /*!< [1..1] SENTDATA Status Flag */ - __IM uint16_t RFST : 1; /*!< [2..2] Receive FIFO Status Flag */ - __IM uint16_t TFST : 1; /*!< [3..3] Transmit FIFO Status Flag */ - __IM uint16_t NMLST : 1; /*!< [4..4] Normal Mailbox Message Lost Status Flag */ - __IM uint16_t FMLST : 1; /*!< [5..5] FIFO Mailbox Message Lost Status Flag */ - __IM uint16_t TABST : 1; /*!< [6..6] Transmission Abort Status Flag */ - __IM uint16_t EST : 1; /*!< [7..7] Error Status Flag */ - __IM uint16_t RSTST : 1; /*!< [8..8] CAN Reset Status Flag */ - __IM uint16_t HLTST : 1; /*!< [9..9] CAN Halt Status Flag */ - __IM uint16_t SLPST : 1; /*!< [10..10] CAN Sleep Status Flag */ - __IM uint16_t EPST : 1; /*!< [11..11] Error-Passive Status Flag */ - __IM uint16_t BOST : 1; /*!< [12..12] Bus-Off Status Flag */ - __IM uint16_t TRMST : 1; /*!< [13..13] Transmit Status Flag (transmitter) */ - __IM uint16_t RECST : 1; /*!< [14..14] Receive Status Flag (receiver) */ - uint16_t : 1; - } STR_b; + __IOM uint8_t ADSWREF : 3; /*!< [2..0] These bits are read as 0. The write value should be 0.Refreshing + * the pressure switch in A/D analog module is set. */ + uint8_t : 1; + __IOM uint8_t SHSWREF : 3; /*!< [6..4] S&H Boost Switch Refresh Interval Setting */ + uint8_t : 1; + } ADSWCR_b; }; union { - __IOM uint32_t BCR; /*!< (@ 0x00000844) Bit Configuration Register */ + __IOM uint8_t ADSHMSR; /*!< (@ 0x0000007C) A/D Sample and Hold Operation Mode Select Register */ struct { - __IOM uint32_t CCLKS : 1; /*!< [0..0] CAN Clock Source Selection */ - uint32_t : 7; - __IOM uint32_t TSEG2 : 3; /*!< [10..8] Time Segment 2 Control */ - uint32_t : 1; - __IOM uint32_t SJW : 2; /*!< [13..12] Resynchronization Jump Width Control */ - uint32_t : 2; - __IOM uint32_t BRP : 10; /*!< [25..16] Prescaler Division Ratio Select . These bits set the - * frequency of the CAN communication clock (fCANCLK). */ - uint32_t : 2; - __IOM uint32_t TSEG1 : 4; /*!< [31..28] Time Segment 1 Control */ - } BCR_b; + __IOM uint8_t SHMD : 1; /*!< [0..0] Channel-Dedicated Sample-and-Hold Circuit Operation Mode + * Select */ + uint8_t : 7; + } ADSHMSR_b; }; union { - __IOM uint8_t RFCR; /*!< (@ 0x00000848) Receive FIFO Control Register */ + __IOM uint8_t ADICR; /*!< (@ 0x0000007D) A/D Interrupt Control Register */ struct { - __IOM uint8_t RFE : 1; /*!< [0..0] Receive FIFO Enable */ - __IM uint8_t RFUST : 3; /*!< [3..1] Receive FIFO Unread Message Number Status */ - __IOM uint8_t RFMLF : 1; /*!< [4..4] Receive FIFO Message Lost Flag */ - __IM uint8_t RFFST : 1; /*!< [5..5] Receive FIFO Full Status Flag */ - __IM uint8_t RFWST : 1; /*!< [6..6] Receive FIFO Buffer Warning Status Flag */ - __IM uint8_t RFEST : 1; /*!< [7..7] Receive FIFO Empty Status Flag */ - } RFCR_b; + __IOM uint8_t ADIC : 2; /*!< [1..0] A/D Interrupt Control */ + uint8_t : 6; + } ADICR_b; }; union { - __OM uint8_t RFPCR; /*!< (@ 0x00000849) Receive FIFO Pointer Control Register */ + __IOM uint8_t ADACSR; /*!< (@ 0x0000007E) A/D Conversion Operation Mode Select Register */ struct { - __OM uint8_t RFPCR : 8; /*!< [7..0] The CPU-side pointer for the receive FIFO is incremented - * by writing FFh to RFPCR. */ - } RFPCR_b; + uint8_t : 1; + __IOM uint8_t ADSAC : 1; /*!< [1..1] Successive Approximation Control Setting */ + uint8_t : 6; + } ADACSR_b; }; + __IM uint8_t RESERVED4; union { - __IOM uint8_t TFCR; /*!< (@ 0x0000084A) Transmit FIFO Control Register */ + __IOM uint16_t ADGSPCR; /*!< (@ 0x00000080) A/D Group Scan Priority Control Register */ struct { - __IOM uint8_t TFE : 1; /*!< [0..0] Transmit FIFO Enable */ - __IM uint8_t TFUST : 3; /*!< [3..1] Transmit FIFO Unsent Message Number Status */ - uint8_t : 2; - __IM uint8_t TFFST : 1; /*!< [6..6] Transmit FIFO Full Status */ - __IM uint8_t TFEST : 1; /*!< [7..7] Transmit FIFO Empty Status */ - } TFCR_b; + __IOM uint16_t PGS : 1; /*!< [0..0] Group A priority control setting bit.Note: When the PGS + * bit is to be set to 1, the ADCSR.ADCS[1:0] bits must be + * set to 01b (group scan mode). If the bits are set to any + * other values, proper operation is not guaranteed. */ + __IOM uint16_t GBRSCN : 1; /*!< [1..1] Group B Restart Setting(Enabled only when PGS = 1. Reserved + * when PGS = 0.) */ + uint16_t : 6; + __IOM uint16_t GBEXTRG : 1; /*!< [8..8] External trigger selection bit for group B. */ + uint16_t : 6; + __IOM uint16_t GBRP : 1; /*!< [15..15] Group B Single Scan Continuous Start(Enabled only when + * PGS = 1. Reserved when PGS = 0.)Note: When the GBRP bit + * has been set to 1, single scan is performed continuously + * for group B regardless of the setting of the GBRSCN bit. */ + } ADGSPCR_b; }; union { - __OM uint8_t TFPCR; /*!< (@ 0x0000084B) Transmit FIFO Pointer Control Register */ + __IM uint16_t ADGSCS; /*!< (@ 0x00000082) A/D Conversion Channel Status Register (for Group + * Scan) */ struct { - __OM uint8_t TFPCR : 8; /*!< [7..0] The CPU-side pointer for the transmit FIFO is incremented - * by writing FFh to TFPCR. */ - } TFPCR_b; + __IM uint16_t CHSELGB : 8; /*!< [7..0] Channel status of Group B scan */ + __IM uint16_t CHSELGA : 8; /*!< [15..8] Channel status of Group A scan */ + } ADGSCS_b; }; union { - __IOM uint8_t EIER; /*!< (@ 0x0000084C) Error Interrupt Enable Register */ + __IM uint16_t ADDBLDRA; /*!< (@ 0x00000084) A/D Data Duplexing Register A */ struct { - __IOM uint8_t BEIE : 1; /*!< [0..0] Bus Error Interrupt Enable */ - __IOM uint8_t EWIE : 1; /*!< [1..1] Error-Warning Interrupt Enable */ - __IOM uint8_t EPIE : 1; /*!< [2..2] Error-Passive Interrupt Enable */ - __IOM uint8_t BOEIE : 1; /*!< [3..3] Bus-Off Entry Interrupt Enable */ - __IOM uint8_t BORIE : 1; /*!< [4..4] Bus-Off Recovery Interrupt Enable */ - __IOM uint8_t ORIE : 1; /*!< [5..5] Overrun Interrupt Enable */ - __IOM uint8_t OLIE : 1; /*!< [6..6] Overload Frame Transmit Interrupt Enable */ - __IOM uint8_t BLIE : 1; /*!< [7..7] Bus Lock Interrupt Enable */ - } EIER_b; + __IM uint16_t ADDBLDRA : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRA_b; }; union { - __IOM uint8_t EIFR; /*!< (@ 0x0000084D) Error Interrupt Factor Judge Register */ + __IM uint16_t ADDBLDRB; /*!< (@ 0x00000086) A/D Data Duplexing Register B */ struct { - __IOM uint8_t BEIF : 1; /*!< [0..0] Bus Error Detect Flag */ - __IOM uint8_t EWIF : 1; /*!< [1..1] Error-Warning Detect Flag */ - __IOM uint8_t EPIF : 1; /*!< [2..2] Error-Passive Detect Flag */ - __IOM uint8_t BOEIF : 1; /*!< [3..3] Bus-Off Entry Detect Flag */ - __IOM uint8_t BORIF : 1; /*!< [4..4] Bus-Off Recovery Detect Flag */ - __IOM uint8_t ORIF : 1; /*!< [5..5] Receive Overrun Detect Flag */ - __IOM uint8_t OLIF : 1; /*!< [6..6] Overload Frame Transmission Detect Flag */ - __IOM uint8_t BLIF : 1; /*!< [7..7] Bus Lock Detect Flag */ - } EIFR_b; + __IM uint16_t ADDBLDRB : 16; /*!< [15..0] This register is a 16-bit read-only registers for storing + * the result of A/D conversion in response to the respective + * triggers during extended operation in double trigger mode. */ + } ADDBLDRB_b; }; union { - __IM uint8_t RECR; /*!< (@ 0x0000084E) Receive Error Count Register */ + __IOM uint8_t ADSER; /*!< (@ 0x00000088) A/D Sampling Extension Register */ struct { - __IM uint8_t RECR : 8; /*!< [7..0] Receive error count functionRECR increments or decrements - * the counter value according to the error status of the - * CAN module during reception. */ - } RECR_b; + uint8_t : 7; + __IOM uint8_t SMPEX : 1; /*!< [7..7] Sampling extension control */ + } ADSER_b; }; + __IM uint8_t RESERVED5; union { - __IM uint8_t TECR; /*!< (@ 0x0000084F) Transmit Error Count Register */ + __IOM uint8_t ADHVREFCNT; /*!< (@ 0x0000008A) A/D High-Potential/Low-Potential Reference Voltage + * Control Register */ struct { - __IM uint8_t TECR : 8; /*!< [7..0] Transmit error count functionTECR increments or decrements - * the counter value according to the error status of the - * CAN module during transmission. */ - } TECR_b; + __IOM uint8_t HVSEL : 2; /*!< [1..0] High-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t LVSEL : 1; /*!< [4..4] Low-Potential Reference Voltage Select */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } ADHVREFCNT_b; }; + __IM uint8_t RESERVED6; union { - __IOM uint8_t ECSR; /*!< (@ 0x00000850) Error Code Store Register */ + __IM uint8_t ADWINMON; /*!< (@ 0x0000008C) A/D Compare Function Window A/B Status Monitor + * Register */ struct { - __IOM uint8_t SEF : 1; /*!< [0..0] Stuff Error Flag */ - __IOM uint8_t FEF : 1; /*!< [1..1] Form Error Flag */ - __IOM uint8_t AEF : 1; /*!< [2..2] ACK Error Flag */ - __IOM uint8_t CEF : 1; /*!< [3..3] CRC Error Flag */ - __IOM uint8_t BE1F : 1; /*!< [4..4] Bit Error (recessive) Flag */ - __IOM uint8_t BE0F : 1; /*!< [5..5] Bit Error (dominant) Flag */ - __IOM uint8_t ADEF : 1; /*!< [6..6] ACK Delimiter Error Flag */ - __IOM uint8_t EDPM : 1; /*!< [7..7] Error Display Mode Select */ - } ECSR_b; + __IM uint8_t MONCOMB : 1; /*!< [0..0] Combination result monitorThis bit indicates the combination + * result.This bit is valid when both window A operation and + * window B operation are enabled. */ + uint8_t : 3; + __IM uint8_t MONCMPA : 1; /*!< [4..4] Comparison Result Monitor A */ + __IM uint8_t MONCMPB : 1; /*!< [5..5] Comparison Result Monitor B */ + uint8_t : 2; + } ADWINMON_b; }; + __IM uint8_t RESERVED7; + __IM uint16_t RESERVED8; union { - __IOM uint8_t CSSR; /*!< (@ 0x00000851) Channel Search Support Register */ + __IOM uint16_t ADCMPCR; /*!< (@ 0x00000090) A/D Compare Function Control Register */ struct { - __IOM uint8_t CSSR : 8; /*!< [7..0] When the value for the channel search is input, the channel - * number is output to MSSR. */ - } CSSR_b; + __IOM uint16_t CMPAB : 2; /*!< [1..0] Window A/B Composite Conditions SettingNOTE: These bits + * are valid when both window A and window B are enabled (CMPAE + * = 1 and CMPBE = 1). */ + uint16_t : 7; + __IOM uint16_t CMPBE : 1; /*!< [9..9] Compare Window B Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPAE : 1; /*!< [11..11] Compare Window A Operation Enable */ + uint16_t : 1; + __IOM uint16_t CMPBIE : 1; /*!< [13..13] Compare B Interrupt Enable */ + __IOM uint16_t WCMPE : 1; /*!< [14..14] Window Function Setting */ + __IOM uint16_t CMPAIE : 1; /*!< [15..15] Compare A Interrupt Enable */ + } ADCMPCR_b; }; union { - __IM uint8_t MSSR; /*!< (@ 0x00000852) Mailbox Search Status Register */ + __IOM uint8_t ADCMPANSER; /*!< (@ 0x00000092) A/D Compare Function Window A Extended Input + * Select Register */ struct { - __IM uint8_t MBNST : 5; /*!< [4..0] Search Result Mailbox Number Status These bits output - * the smallest mailbox number that is searched in each mode - * of MSMR. */ - uint8_t : 2; - __IM uint8_t SEST : 1; /*!< [7..7] Search Result Status */ - } MSSR_b; + __IOM uint8_t CMPTSA : 1; /*!< [0..0] Temperature sensor output Compare selection bit. */ + __IOM uint8_t CMPOCA : 1; /*!< [1..1] Internal reference voltage Compare selection bit. */ + uint8_t : 6; + } ADCMPANSER_b; }; union { - __IOM uint8_t MSMR; /*!< (@ 0x00000853) Mailbox Search Mode Register */ + __IOM uint8_t ADCMPLER; /*!< (@ 0x00000093) A/D Compare Function Window A Extended Input + * Comparison Condition Setting Register */ struct { - __IOM uint8_t MBSM : 2; /*!< [1..0] Mailbox Search Mode Select */ - uint8_t : 6; - } MSMR_b; + __IOM uint8_t CMPLTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Comparison + * Condition Select */ + __IOM uint8_t CMPLOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage ComparisonCondition + * Select */ + uint8_t : 6; + } ADCMPLER_b; }; union { - __IM uint16_t TSR; /*!< (@ 0x00000854) Time Stamp Register */ + __IOM uint16_t ADCMPANSR[2]; /*!< (@ 0x00000094) A/D Compare Function Window A Channel Select + * Register */ struct { - __IM uint16_t TSR : 16; /*!< [15..0] Free-running counter value for the time stamp function */ - } TSR_b; + __IOM uint16_t CMPCHA0 : 1; /*!< [0..0] AN Input Select */ + __IOM uint16_t CMPCHA1 : 1; /*!< [1..1] AN Input Select */ + __IOM uint16_t CMPCHA2 : 1; /*!< [2..2] AN Input Select */ + __IOM uint16_t CMPCHA3 : 1; /*!< [3..3] AN Input Select */ + __IOM uint16_t CMPCHA4 : 1; /*!< [4..4] AN Input Select */ + __IOM uint16_t CMPCHA5 : 1; /*!< [5..5] AN Input Select */ + __IOM uint16_t CMPCHA6 : 1; /*!< [6..6] AN Input Select */ + __IOM uint16_t CMPCHA7 : 1; /*!< [7..7] AN Input Select */ + __IOM uint16_t CMPCHA8 : 1; /*!< [8..8] AN Input Select */ + __IOM uint16_t CMPCHA9 : 1; /*!< [9..9] AN Input Select */ + __IOM uint16_t CMPCHA10 : 1; /*!< [10..10] AN Input Select */ + __IOM uint16_t CMPCHA11 : 1; /*!< [11..11] AN Input Select */ + __IOM uint16_t CMPCHA12 : 1; /*!< [12..12] AN Input Select */ + __IOM uint16_t CMPCHA13 : 1; /*!< [13..13] AN Input Select */ + __IOM uint16_t CMPCHA14 : 1; /*!< [14..14] AN Input Select */ + __IOM uint16_t CMPCHA15 : 1; /*!< [15..15] AN Input Select */ + } ADCMPANSR_b[2]; }; union { - __IOM uint16_t AFSR; /*!< (@ 0x00000856) Acceptance Filter Support Register */ + __IOM uint16_t ADCMPLR[2]; /*!< (@ 0x00000098) A/D Compare Function Window A Comparison Condition + * Setting Register */ struct { - __IOM uint16_t AFSR : 16; /*!< [15..0] After the standard ID of a received message is written, - * the value converted for data table search can be read. */ - } AFSR_b; + __IOM uint16_t CMPLCHA0 : 1; /*!< [0..0] Comparison condition of input */ + __IOM uint16_t CMPLCHA1 : 1; /*!< [1..1] Comparison condition of input */ + __IOM uint16_t CMPLCHA2 : 1; /*!< [2..2] Comparison condition of input */ + __IOM uint16_t CMPLCHA3 : 1; /*!< [3..3] Comparison condition of input */ + __IOM uint16_t CMPLCHA4 : 1; /*!< [4..4] Comparison condition of input */ + __IOM uint16_t CMPLCHA5 : 1; /*!< [5..5] Comparison condition of input */ + __IOM uint16_t CMPLCHA6 : 1; /*!< [6..6] Comparison condition of input */ + __IOM uint16_t CMPLCHA7 : 1; /*!< [7..7] Comparison condition of input */ + __IOM uint16_t CMPLCHA8 : 1; /*!< [8..8] Comparison condition of input */ + __IOM uint16_t CMPLCHA9 : 1; /*!< [9..9] Comparison condition of input */ + __IOM uint16_t CMPLCHA10 : 1; /*!< [10..10] Comparison condition of input */ + __IOM uint16_t CMPLCHA11 : 1; /*!< [11..11] Comparison condition of input */ + __IOM uint16_t CMPLCHA12 : 1; /*!< [12..12] Comparison condition of input */ + __IOM uint16_t CMPLCHA13 : 1; /*!< [13..13] Comparison condition of input */ + __IOM uint16_t CMPLCHA14 : 1; /*!< [14..14] Comparison condition of input */ + __IOM uint16_t CMPLCHA15 : 1; /*!< [15..15] Comparison condition of input */ + } ADCMPLR_b[2]; }; union { - __IOM uint8_t TCR; /*!< (@ 0x00000858) Test Control Register */ + __IOM uint16_t ADCMPDR0; /*!< (@ 0x0000009C) A/D Compare Function Window A Lower-Side Level + * Setting Register */ struct { - __IOM uint8_t TSTE : 1; /*!< [0..0] CAN Test Mode Enable */ - __IOM uint8_t TSTM : 2; /*!< [2..1] CAN Test Mode Select */ - uint8_t : 5; - } TCR_b; + __IOM uint16_t ADCMPDR0 : 16; /*!< [15..0] The ADCMPDR0 register sets the reference data when the + * compare window A function is used. ADCMPDR0 sets the lower-side + * level of window A. */ + } ADCMPDR0_b; }; - __IM uint8_t RESERVED2; - __IM uint16_t RESERVED3; -} R_CAN0_Type; /*!< Size = 2140 (0x85c) */ - -/* =========================================================================================================================== */ -/* ================ R_CANFD ================ */ -/* =========================================================================================================================== */ - -/** - * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD) - */ - -typedef struct /*!< (@ 0x400B0000) R_CANFD Structure */ -{ - __IOM R_CANFD_CFDC_Type CFDC[2]; /*!< (@ 0x00000000) Channel Control/Status */ - __IM uint32_t RESERVED[25]; union { - __IOM uint32_t CFDGCFG; /*!< (@ 0x00000084) Global Configuration Register */ + __IOM uint16_t ADCMPDR1; /*!< (@ 0x0000009E) A/D Compare Function Window A Upper-Side Level + * Setting Register */ struct { - __IOM uint32_t TPRI : 1; /*!< [0..0] Transmission Priority */ - __IOM uint32_t DCE : 1; /*!< [1..1] DLC Check Enable */ - __IOM uint32_t DRE : 1; /*!< [2..2] DLC Replacement Enable */ - __IOM uint32_t MME : 1; /*!< [3..3] Mirror Mode Enable */ - __IOM uint32_t DCS : 1; /*!< [4..4] Data Link Controller Clock Select */ - __IOM uint32_t CMPOC : 1; /*!< [5..5] CAN-FD message Payload overflow configuration */ - uint32_t : 2; - __IOM uint32_t TSP : 4; /*!< [11..8] Timestamp Prescaler */ - __IOM uint32_t TSSS : 1; /*!< [12..12] Timestamp Source Select */ - __IOM uint32_t TSBTCS : 3; /*!< [15..13] Timestamp Bit Time Channel Select */ - __IOM uint32_t ITRCP : 16; /*!< [31..16] Interval Timer Reference Clock Prescaler */ - } CFDGCFG_b; + __IOM uint16_t ADCMPDR1 : 16; /*!< [15..0] The ADCMPDR1 register sets the reference data when the + * compare window A function is used. ADCMPDR1 sets the upper-side + * level of window A.. */ + } ADCMPDR1_b; }; union { - __IOM uint32_t CFDGCTR; /*!< (@ 0x00000088) Global Control Register */ + __IOM uint16_t ADCMPSR[2]; /*!< (@ 0x000000A0) A/D Compare Function Window A Channel Status + * Register */ struct { - __IOM uint32_t GMDC : 2; /*!< [1..0] Global Mode Control */ - __IOM uint32_t GSLPR : 1; /*!< [2..2] Global Sleep Request */ - uint32_t : 5; - __IOM uint32_t DEIE : 1; /*!< [8..8] DLC check Interrupt Enable */ - __IOM uint32_t MEIE : 1; /*!< [9..9] Message lost Error Interrupt Enable */ - __IOM uint32_t THLEIE : 1; /*!< [10..10] TX History List Entry Lost Interrupt Enable */ - __IOM uint32_t CMPOFIE : 1; /*!< [11..11] CAN-FD message payload overflow Flag Interrupt enable */ - uint32_t : 2; - __IOM uint32_t QMEIE : 1; /*!< [14..14] TXQ Message lost Error Interrupt Enable */ - __IOM uint32_t MOWEIE : 1; /*!< [15..15] GW FIFO Message overwrite Error Interrupt Enable */ - __IOM uint32_t TSRST : 1; /*!< [16..16] Timestamp Reset */ - __IOM uint32_t TSWR : 1; /*!< [17..17] Timestamp Write */ - uint32_t : 14; - } CFDGCTR_b; + __IOM uint16_t CMPSTCHA0 : 1; /*!< [0..0] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA1 : 1; /*!< [1..1] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA2 : 1; /*!< [2..2] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA3 : 1; /*!< [3..3] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA4 : 1; /*!< [4..4] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA5 : 1; /*!< [5..5] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA6 : 1; /*!< [6..6] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA7 : 1; /*!< [7..7] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA8 : 1; /*!< [8..8] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA9 : 1; /*!< [9..9] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA10 : 1; /*!< [10..10] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA11 : 1; /*!< [11..11] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA12 : 1; /*!< [12..12] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA13 : 1; /*!< [13..13] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA14 : 1; /*!< [14..14] Compare window A flag of input */ + __IOM uint16_t CMPSTCHA15 : 1; /*!< [15..15] Compare window A flag of input */ + } ADCMPSR_b[2]; }; union { - __IOM uint32_t CFDGSTS; /*!< (@ 0x0000008C) Global Status Register */ - - struct - { - __IM uint32_t GRSTSTS : 1; /*!< [0..0] Global Reset Status */ - __IM uint32_t GHLTSTS : 1; /*!< [1..1] Global Halt Status */ - __IM uint32_t GSLPSTS : 1; /*!< [2..2] Global Sleep Status */ - __IM uint32_t GRAMINIT : 1; /*!< [3..3] Global RAM Initialisation */ - uint32_t : 28; - } CFDGSTS_b; + __IOM uint8_t ADCMPSER; /*!< (@ 0x000000A4) A/D Compare Function Window A Extended Input + * Channel Status Register */ + + struct + { + __IOM uint8_t CMPSTTSA : 1; /*!< [0..0] Compare Window A Temperature Sensor Output Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + __IOM uint8_t CMPSTOCA : 1; /*!< [1..1] Compare Window A Internal Reference Voltage Compare Flag + * When window A operation is enabled (ADCMPCR.CMPAE = 1b), + * this bit indicates the temperature sensor output comparison + * result. When window A operation is disabled (ADCMPCR.CMPAE + * = 0b), comparison conditions for CMPSTTSA are not met any + * time. */ + uint8_t : 6; + } ADCMPSER_b; }; + __IM uint8_t RESERVED9; union { - __IOM uint32_t CFDGERFL; /*!< (@ 0x00000090) Global Error Flag Register */ + __IOM uint8_t ADCMPBNSR; /*!< (@ 0x000000A6) A/D Compare Function Window B Channel Selection + * Register */ struct { - __IOM uint32_t DEF : 1; /*!< [0..0] DLC Error Flag */ - __IM uint32_t MES : 1; /*!< [1..1] Message Lost Error Status */ - __IM uint32_t THLES : 1; /*!< [2..2] TX History List Entry Lost Error Status */ - __IOM uint32_t CMPOF : 1; /*!< [3..3] CAN-FD message payload overflow Flag */ - __IM uint32_t QOWES : 1; /*!< [4..4] TXQ Message overwrite Error Status */ - __IM uint32_t OTBMLTSTS : 1; /*!< [5..5] OTB FIFO Message Lost Status */ - __IM uint32_t QMES : 1; /*!< [6..6] TXQ Message Lost Error Status */ - uint32_t : 1; - __IOM uint32_t RXSFAIL0 : 1; /*!< [8..8] RX Scan Fail of Channel 0 */ - __IOM uint32_t RXSFAIL1 : 1; /*!< [9..9] RX Scan Fail of Channel 1 */ - uint32_t : 6; - __IOM uint32_t EEF0 : 1; /*!< [16..16] ECC Error Flag for Channel 0 */ - __IOM uint32_t EEF1 : 1; /*!< [17..17] ECC Error Flag for Channel 1 */ - uint32_t : 14; - } CFDGERFL_b; + __IOM uint8_t CMPCHB : 6; /*!< [5..0] Compare window B channel selection bit.The channel that + * compares it on the condition of compare window B is selected. */ + uint8_t : 1; + __IOM uint8_t CMPLB : 1; /*!< [7..7] Compare window B Compare condition setting bit. */ + } ADCMPBNSR_b; }; + __IM uint8_t RESERVED10; union { - __IOM uint32_t CFDGTSC; /*!< (@ 0x00000094) Global Timestamp Counter Register */ + __IOM uint16_t ADWINLLB; /*!< (@ 0x000000A8) A/D Compare Function Window B Lower-Side Level + * Setting Register */ struct { - __IM uint32_t TS : 16; /*!< [15..0] Timestamp Value */ - uint32_t : 16; - } CFDGTSC_b; + __IOM uint16_t ADWINLLB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the lower level of the window B. */ + } ADWINLLB_b; }; union { - __IOM uint32_t CFDGAFLECTR; /*!< (@ 0x00000098) Global Acceptance Filter List Entry Control Register */ + __IOM uint16_t ADWINULB; /*!< (@ 0x000000AA) A/D Compare Function Window B Upper-Side Level + * Setting Register */ struct { - __IOM uint32_t AFLPN : 4; /*!< [3..0] Acceptance Filter List Page Number */ - uint32_t : 4; - __IOM uint32_t AFLDAE : 1; /*!< [8..8] Acceptance Filter List Data Access Enable */ - uint32_t : 23; - } CFDGAFLECTR_b; + __IOM uint16_t ADWINULB : 16; /*!< [15..0] This register is used to compare A window function is + * used to set the higher level of the window B. */ + } ADWINULB_b; }; union { - __IOM uint32_t CFDGAFLCFG0; /*!< (@ 0x0000009C) Global Acceptance Filter List Configuration Register - * 0 */ + __IOM uint8_t ADCMPBSR; /*!< (@ 0x000000AC) A/D Compare Function Window B Status Register */ struct { - __IOM uint32_t RNC1 : 9; /*!< [8..0] Rule Number for Channel 1 */ - uint32_t : 7; - __IOM uint32_t RNC0 : 9; /*!< [24..16] Rule Number for Channel 0 */ - uint32_t : 7; - } CFDGAFLCFG0_b; + __IOM uint8_t CMPSTB : 1; /*!< [0..0] Compare window B flag.It is a status flag that shows + * the comparative result of CH (AN000-AN027, temperature + * sensor, and internal reference voltage) made the object + * of window B relation condition. */ + uint8_t : 7; + } ADCMPBSR_b; }; - __IM uint32_t RESERVED1[3]; + __IM uint8_t RESERVED11; + __IM uint16_t RESERVED12; union { - __IOM uint32_t CFDRMNB; /*!< (@ 0x000000AC) RX Message Buffer Number Register */ + __IM uint16_t ADBUF0; /*!< (@ 0x000000B0) A/D Data Buffer Register 0 */ struct { - __IOM uint32_t NRXMB : 8; /*!< [7..0] Number of RX Message Buffers */ - __IOM uint32_t RMPLS : 3; /*!< [10..8] Reception Message Buffer Payload Data Size */ - uint32_t : 21; - } CFDRMNB_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF0_b; }; union { - __IOM uint32_t CFDRMND0; /*!< (@ 0x000000B0) RX Message Buffer New Data Register 0 */ + __IM uint16_t ADBUF1; /*!< (@ 0x000000B2) A/D Data Buffer Register 1 */ struct { - __IOM uint32_t RMNSu : 32; /*!< [31..0] RX Message Buffer New Data Status */ - } CFDRMND0_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF1_b; }; - __IM uint32_t RESERVED2[3]; union { - __IOM uint32_t CFDRFCC[8]; /*!< (@ 0x000000C0) RX FIFO Configuration / Control Registers */ + __IM uint16_t ADBUF2; /*!< (@ 0x000000B4) A/D Data Buffer Register 2 */ struct { - __IOM uint32_t RFE : 1; /*!< [0..0] RX FIFO Enable */ - __IOM uint32_t RFIE : 1; /*!< [1..1] RX FIFO Interrupt Enable */ - uint32_t : 2; - __IOM uint32_t RFPLS : 3; /*!< [6..4] Rx FIFO Payload Data Size configuration */ - uint32_t : 1; - __IOM uint32_t RFDC : 3; /*!< [10..8] RX FIFO Depth Configuration */ - uint32_t : 1; - __IOM uint32_t RFIM : 1; /*!< [12..12] RX FIFO Interrupt Mode */ - __IOM uint32_t RFIGCV : 3; /*!< [15..13] RX FIFO Interrupt Generation Counter Value */ - __IOM uint32_t RFFIE : 1; /*!< [16..16] RX FIFO Full interrupt Enable */ - uint32_t : 15; - } CFDRFCC_b[8]; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF2_b; }; union { - __IOM uint32_t CFDRFSTS[8]; /*!< (@ 0x000000E0) RX FIFO Status Registers */ + __IM uint16_t ADBUF3; /*!< (@ 0x000000B6) A/D Data Buffer Register 3 */ struct { - __IM uint32_t RFEMP : 1; /*!< [0..0] RX FIFO Empty */ - __IM uint32_t RFFLL : 1; /*!< [1..1] RX FIFO Full */ - __IOM uint32_t RFMLT : 1; /*!< [2..2] RX FIFO Message Lost */ - __IOM uint32_t RFIF : 1; /*!< [3..3] RX FIFO Interrupt Flag */ - uint32_t : 4; - __IM uint32_t RFMC : 8; /*!< [15..8] RX FIFO Message Count */ - __IOM uint32_t RFFIF : 1; /*!< [16..16] RX FIFO Full Interrupt Flag */ - uint32_t : 15; - } CFDRFSTS_b[8]; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF3_b; }; union { - __IOM uint32_t CFDRFPCTR[8]; /*!< (@ 0x00000100) RX FIFO Pointer Control Registers */ + __IM uint16_t ADBUF4; /*!< (@ 0x000000B8) A/D Data Buffer Register 4 */ struct { - __OM uint32_t RFPC : 8; /*!< [7..0] RX FIFO Pointer Control */ - uint32_t : 24; - } CFDRFPCTR_b[8]; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF4_b; }; union { - __IOM uint32_t CFDCFCC[6]; /*!< (@ 0x00000120) Common FIFO Configuration / Control Registers */ + __IM uint16_t ADBUF5; /*!< (@ 0x000000BA) A/D Data Buffer Register 5 */ struct { - __IOM uint32_t CFE : 1; /*!< [0..0] Common FIFO Enable */ - __IOM uint32_t CFRXIE : 1; /*!< [1..1] Common FIFO RX Interrupt Enable */ - __IOM uint32_t CFTXIE : 1; /*!< [2..2] Common FIFO TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t CFPLS : 3; /*!< [6..4] Common FIFO Payload Data size configuration */ - uint32_t : 1; - __IOM uint32_t CFM : 2; /*!< [9..8] Common FIFO Mode */ - __IOM uint32_t CFITSS : 1; /*!< [10..10] Common FIFO Interval Timer Source Select */ - __IOM uint32_t CFITR : 1; /*!< [11..11] Common FIFO Interval Timer Resolution */ - __IOM uint32_t CFIM : 1; /*!< [12..12] Common FIFO Interrupt Mode */ - __IOM uint32_t CFIGCV : 3; /*!< [15..13] Common FIFO Interrupt Generation Counter Value */ - __IOM uint32_t CFTML : 5; /*!< [20..16] Common FIFO TX Message Buffer Link */ - __IOM uint32_t CFDC : 3; /*!< [23..21] Common FIFO Depth Configuration */ - __IOM uint32_t CFITT : 8; /*!< [31..24] Common FIFO Interval Transmission Time */ - } CFDCFCC_b[6]; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF5_b; }; - __IM uint32_t RESERVED3[18]; union { - __IOM uint32_t CFDCFCCE[6]; /*!< (@ 0x00000180) Common FIFO Configuration / Control Enhancement - * Registers */ + __IM uint16_t ADBUF6; /*!< (@ 0x000000BC) A/D Data Buffer Register 6 */ struct { - __IOM uint32_t CFFIE : 1; /*!< [0..0] Common FIFO Full interrupt Enable */ - __IOM uint32_t CFOFRXIE : 1; /*!< [1..1] Common FIFO One Frame Reception Interrupt Enable */ - __IOM uint32_t CFOFTXIE : 1; /*!< [2..2] Common FIFO One Frame Transmission Interrupt Enable */ - uint32_t : 5; - __IOM uint32_t CFMOWM : 1; /*!< [8..8] Common FIFO message overwrite mode */ - uint32_t : 7; - __IOM uint32_t CFBME : 1; /*!< [16..16] Common FIFO Buffering Mode Enable */ - uint32_t : 15; - } CFDCFCCE_b[6]; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF6_b; }; - __IM uint32_t RESERVED4[18]; union { - __IOM uint32_t CFDCFSTS[6]; /*!< (@ 0x000001E0) Common FIFO Status Registers */ + __IM uint16_t ADBUF7; /*!< (@ 0x000000BE) A/D Data Buffer Register 7 */ struct { - __IM uint32_t CFEMP : 1; /*!< [0..0] Common FIFO Empty */ - __IM uint32_t CFFLL : 1; /*!< [1..1] Common FIFO Full */ - __IOM uint32_t CFMLT : 1; /*!< [2..2] Common FIFO Message Lost */ - __IOM uint32_t CFRXIF : 1; /*!< [3..3] Common RX FIFO Interrupt Flag */ - __IOM uint32_t CFTXIF : 1; /*!< [4..4] Common TX FIFO Interrupt Flag */ - uint32_t : 3; - __IM uint32_t CFMC : 8; /*!< [15..8] Common FIFO Message Count */ - __IOM uint32_t CFFIF : 1; /*!< [16..16] Common FIFO Full Interrupt Flag */ - __IOM uint32_t CFOFRXIF : 1; /*!< [17..17] Common FIFO One Frame Reception Interrupt Flag */ - __IOM uint32_t CFOFTXIF : 1; /*!< [18..18] Common FIFO One Frame Transmission Interrupt Flag */ - uint32_t : 5; - __IOM uint32_t CFMOW : 1; /*!< [24..24] Common FIFO message overwrite */ - uint32_t : 7; - } CFDCFSTS_b[6]; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF7_b; }; - __IM uint32_t RESERVED5[18]; union { - __IOM uint32_t CFDCFPCTR[6]; /*!< (@ 0x00000240) Common FIFO Pointer Control Registers */ + __IM uint16_t ADBUF8; /*!< (@ 0x000000C0) A/D Data Buffer Register 8 */ struct { - __OM uint32_t CFPC : 8; /*!< [7..0] Common FIFO Pointer Control */ - uint32_t : 24; - } CFDCFPCTR_b[6]; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF8_b; }; - __IM uint32_t RESERVED6[18]; union { - __IM uint32_t CFDFESTS; /*!< (@ 0x000002A0) FIFO Empty Status Register */ + __IM uint16_t ADBUF9; /*!< (@ 0x000000C2) A/D Data Buffer Register 9 */ struct { - __IM uint32_t RFXEMP : 8; /*!< [7..0] RX FIF0 Empty Status */ - __IM uint32_t CFXEMP : 6; /*!< [13..8] Common FIF0 Empty Status */ - uint32_t : 18; - } CFDFESTS_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF9_b; }; union { - __IM uint32_t CFDFFSTS; /*!< (@ 0x000002A4) FIFO Full Status Register */ + __IM uint16_t ADBUF10; /*!< (@ 0x000000C4) A/D Data Buffer Register 10 */ struct { - __IM uint32_t RFXFLL : 8; /*!< [7..0] RX FIF0 Full Status */ - __IM uint32_t CFXFLL : 6; /*!< [13..8] Common FIF0 Full Status */ - uint32_t : 18; - } CFDFFSTS_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF10_b; }; union { - __IM uint32_t CFDFMSTS; /*!< (@ 0x000002A8) FIFO Message Lost Status Register */ + __IM uint16_t ADBUF11; /*!< (@ 0x000000C6) A/D Data Buffer Register 11 */ struct { - __IM uint32_t RFXMLT : 8; /*!< [7..0] RX FIFO Msg Lost Status */ - __IM uint32_t CFXMLT : 6; /*!< [13..8] Common FIFO Msg Lost Status */ - uint32_t : 18; - } CFDFMSTS_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF11_b; }; union { - __IOM uint32_t CFDRFISTS; /*!< (@ 0x000002AC) RX FIFO Interrupt Flag Status Register */ + __IM uint16_t ADBUF12; /*!< (@ 0x000000C8) A/D Data Buffer Register 12 */ struct { - __IM uint32_t RFXIF : 8; /*!< [7..0] RX FIFO[x] Interrupt Flag Status */ - uint32_t : 8; - __IM uint32_t RFXFFLL : 8; /*!< [23..16] RX FIFO[x] Interrupt Full Flag Status */ - uint32_t : 8; - } CFDRFISTS_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF12_b; }; union { - __IOM uint32_t CFDCFRISTS; /*!< (@ 0x000002B0) Common FIFO RX Interrupt Flag Status Register */ + __IM uint16_t ADBUF13; /*!< (@ 0x000000CA) A/D Data Buffer Register 13 */ struct { - __IM uint32_t CFXRXIF : 6; /*!< [5..0] Common FIFO [x] RX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFRISTS_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF13_b; }; union { - __IOM uint32_t CFDCFTISTS; /*!< (@ 0x000002B4) Common FIFO TX Interrupt Flag Status Register */ + __IM uint16_t ADBUF14; /*!< (@ 0x000000CC) A/D Data Buffer Register 14 */ struct { - __IM uint32_t CFXTXIF : 6; /*!< [5..0] Common FIFO [x] TX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFTISTS_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF14_b; }; union { - __IM uint32_t CFDCFOFRISTS; /*!< (@ 0x000002B8) Common FIFO One Frame RX Interrupt Flag Status - * Register */ + __IM uint16_t ADBUF15; /*!< (@ 0x000000CE) A/D Data Buffer Register 15 */ struct { - __IM uint32_t CFXOFRXIF : 6; /*!< [5..0] Common FIFO [x] One Frame RX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFOFRISTS_b; + __IM uint16_t ADBUF : 16; /*!< [15..0] A/D data buffer registers (ADBUF) are 16-bit read-only + * registers that sequentially store all A/D converted values. + * The automatic clear function is not applied to these registers. */ + } ADBUF15_b; }; union { - __IM uint32_t CFDCFOFTISTS; /*!< (@ 0x000002BC) Common FIFO One Frame TX Interrupt Flag Status - * Register */ + __IOM uint8_t ADBUFEN; /*!< (@ 0x000000D0) A/D Data Buffer Enable Register */ struct { - __IM uint32_t CFXOFTXIF : 6; /*!< [5..0] Common FIFO [x] One Frame TX Interrupt Flag Status */ - uint32_t : 26; - } CFDCFOFTISTS_b; + __IOM uint8_t BUFEN : 1; /*!< [0..0] Data Buffer Enable */ + uint8_t : 7; + } ADBUFEN_b; }; + __IM uint8_t RESERVED13; union { - __IM uint32_t CFDCFMOWSTS; /*!< (@ 0x000002C0) Common FIFO Message Over Write Status Register */ + __IOM uint8_t ADBUFPTR; /*!< (@ 0x000000D2) A/D Data Buffer Pointer Register */ struct { - __IM uint32_t CFXMOW : 6; /*!< [5..0] Common FIFO [x] Massage overwrite status */ - uint32_t : 26; - } CFDCFMOWSTS_b; + __IM uint8_t BUFPTR : 4; /*!< [3..0] Data Buffer PointerThese bits indicate the number of + * data buffer to which the next A/D converted data is transferred. */ + __IM uint8_t PTROVF : 1; /*!< [4..4] Pointer Overflow Flag */ + uint8_t : 3; + } ADBUFPTR_b; }; + __IM uint8_t RESERVED14; + __IM uint32_t RESERVED15[2]; + __IM uint8_t RESERVED16; union { - __IM uint32_t CFDFFFSTS; /*!< (@ 0x000002C4) FIFO FDC Full Status Register */ + __IOM uint8_t ADSSTRL; /*!< (@ 0x000000DD) A/D Sampling State Register L */ struct { - __IM uint32_t RFXFFLL : 8; /*!< [7..0] RX FIFO FDC level full Status */ - __IM uint32_t CFXFFLL : 6; /*!< [13..8] COMMON FIFO FDC level full Status */ - uint32_t : 18; - } CFDFFFSTS_b; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (AN016-AN027) */ + } ADSSTRL_b; }; - __IM uint32_t RESERVED7[2]; union { - __IOM uint8_t CFDTMC[128]; /*!< (@ 0x000002D0) TX Message Buffer Control Registers */ + __IOM uint8_t ADSSTRT; /*!< (@ 0x000000DE) A/D Sampling State Register T */ struct { - __IOM uint8_t TMTR : 1; /*!< [0..0] TX Message Buffer Transmission Request */ - __IOM uint8_t TMTAR : 1; /*!< [1..1] TX Message Buffer Transmission abort Request */ - __IOM uint8_t TMOM : 1; /*!< [2..2] TX Message Buffer One-shot Mode */ - uint8_t : 5; - } CFDTMC_b[128]; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (temperature sensor output) */ + } ADSSTRT_b; }; - __IM uint32_t RESERVED8[288]; union { - __IOM uint8_t CFDTMSTS[128]; /*!< (@ 0x000007D0) TX Message Buffer Status Registers */ + __IOM uint8_t ADSSTRO; /*!< (@ 0x000000DF) A/D Sampling State Register O */ struct { - __IM uint8_t TMTSTS : 1; /*!< [0..0] TX Message Buffer Transmission Status */ - __IOM uint8_t TMTRF : 2; /*!< [2..1] TX Message Buffer Transmission Result Flag */ - __IM uint8_t TMTRM : 1; /*!< [3..3] TX Message Buffer Transmission Request Mirrored */ - __IM uint8_t TMTARM : 1; /*!< [4..4] TX Message Buffer Transmission abort Request Mirrored */ - uint8_t : 3; - } CFDTMSTS_b[128]; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling Time Setting (Internal reference voltage) */ + } ADSSTRO_b; }; - __IM uint32_t RESERVED9[288]; union { - __IM uint32_t CFDTMTRSTS[4]; /*!< (@ 0x00000CD0) TX Message Buffer Transmission Request Status - * Register */ + __IOM uint8_t ADSSTR[16]; /*!< (@ 0x000000E0) A/D Sampling State Registers */ struct { - __IM uint32_t CFDTMTRSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Request Status */ - uint32_t : 24; - } CFDTMTRSTS_b[4]; + __IOM uint8_t SST : 8; /*!< [7..0] Sampling time setting */ + } ADSSTR_b[16]; }; - __IM uint32_t RESERVED10[36]; union { - __IM uint32_t CFDTMTARSTS[4]; /*!< (@ 0x00000D70) TX Message Buffer Transmission Abort Request - * Status Register */ + __IOM uint16_t ADANIM; /*!< (@ 0x000000F0) A/D Channel Input Mode Select Register */ struct { - __IM uint32_t CFDTMTARSTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Request Status */ - uint32_t : 24; - } CFDTMTARSTS_b[4]; + __IOM uint16_t ANIM0 : 1; /*!< [0..0] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM1 : 1; /*!< [1..1] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM2 : 1; /*!< [2..2] Analog Channel Input Mode Select */ + __IOM uint16_t ANIM3 : 1; /*!< [3..3] Analog Channel Input Mode Select */ + uint16_t : 12; + } ADANIM_b; }; - __IM uint32_t RESERVED11[36]; union { - __IM uint32_t CFDTMTCSTS[4]; /*!< (@ 0x00000E10) TX Message Buffer Transmission Completion Status - * Register */ + __IOM uint8_t ADCALEXE; /*!< (@ 0x000000F2) A/D Calibration Execution Register */ struct { - __IM uint32_t CFDTMTCSTSg : 8; /*!< [7..0] TX Message Buffer Transmission Completion Status */ - uint32_t : 24; - } CFDTMTCSTS_b[4]; + uint8_t : 6; + __IM uint8_t CALMON : 1; /*!< [6..6] Calibration Status Flag */ + __IOM uint8_t CALEXE : 1; /*!< [7..7] Calibration Start */ + } ADCALEXE_b; }; - __IM uint32_t RESERVED12[36]; + __IM uint8_t RESERVED17; union { - __IM uint32_t CFDTMTASTS[4]; /*!< (@ 0x00000EB0) TX Message Buffer Transmission Abort Status Register */ + __IOM uint8_t VREFAMPCNT; /*!< (@ 0x000000F4) A/D Dedicated Reference Voltage Circuit Control + * Register */ struct { - __IM uint32_t CFDTMTASTSg : 8; /*!< [7..0] TX Message Buffer Transmission abort Status */ - uint32_t : 24; - } CFDTMTASTS_b[4]; + __IOM uint8_t OLDETEN : 1; /*!< [0..0] OLDET Enable */ + __IOM uint8_t VREFADCG : 2; /*!< [2..1] VREFADC Output Voltage Control */ + __IOM uint8_t VREFADCEN : 1; /*!< [3..3] VREFADCG Enable */ + __IOM uint8_t BGREN : 1; /*!< [4..4] BGR Enable */ + uint8_t : 2; + __IOM uint8_t ADSLP : 1; /*!< [7..7] Sleep */ + } VREFAMPCNT_b; }; - __IM uint32_t RESERVED13[36]; + __IM uint8_t RESERVED18; + __IM uint16_t RESERVED19; union { - __IOM uint32_t CFDTMIEC[4]; /*!< (@ 0x00000F50) TX Message Buffer Interrupt Enable Configuration - * Register */ + __IOM uint16_t ADRD; /*!< (@ 0x000000F8) A/D Self-Diagnosis Data Register */ struct { - __IOM uint32_t TMIEg : 8; /*!< [7..0] TX Message Buffer Interrupt Enable */ - uint32_t : 24; - } CFDTMIEC_b[4]; + __IM uint16_t AD : 16; /*!< [15..0] Converted Value 15 to 0 */ + } ADRD_b; }; - __IM uint32_t RESERVED14[40]; union { - __IOM uint32_t CFDTXQCC0[2]; /*!< (@ 0x00001000) TX Queue Configuration / Control Registers 0 */ + __IM uint8_t ADRST; /*!< (@ 0x000000FA) A/D Self-Diagnostic Status Register */ struct { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC0_b[2]; + __IM uint8_t DIAGST : 2; /*!< [1..0] Self-Diagnosis Status */ + uint8_t : 6; + } ADRST_b; }; - __IM uint32_t RESERVED15[6]; + __IM uint8_t RESERVED20; + __IM uint32_t RESERVED21[41]; union { - __IOM uint32_t CFDTXQSTS0[2]; /*!< (@ 0x00001020) TX Queue Status Registers 0 */ + __IOM uint16_t ADPGACR; /*!< (@ 0x000001A0) A/D Programmable Gain Amplifier Control Register */ struct { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS0_b[2]; + __IOM uint16_t P000SEL0 : 1; /*!< [0..0] A through amplifier is enable for PGA P000 */ + __IOM uint16_t P000SEL1 : 1; /*!< [1..1] The amplifier passing is enable for PGA P000 */ + __IOM uint16_t P000ENAMP : 1; /*!< [2..2] Amplifier enable bit for PGA P000 */ + __IOM uint16_t P000GEN : 1; /*!< [3..3] PGA P000 gain setting and enable bit */ + __IOM uint16_t P001SEL0 : 1; /*!< [4..4] A through amplifier is enable for PGA P001 */ + __IOM uint16_t P001SEL1 : 1; /*!< [5..5] The amplifier passing is enable for PGA P001 */ + __IOM uint16_t P001ENAMP : 1; /*!< [6..6] Amplifier enable bit for PGA P001 */ + __IOM uint16_t P001GEN : 1; /*!< [7..7] PGA P001 gain setting and enable bit */ + __IOM uint16_t P002SEL0 : 1; /*!< [8..8] A through amplifier is enable for PGA P002 */ + __IOM uint16_t P002SEL1 : 1; /*!< [9..9] The amplifier passing is enable for PGA P002 */ + __IOM uint16_t P002ENAMP : 1; /*!< [10..10] Amplifier enable bit for PGA P002 */ + __IOM uint16_t P002GEN : 1; /*!< [11..11] PGA P002 gain setting and enable bit */ + __IOM uint16_t P003SEL0 : 1; /*!< [12..12] A through amplifier is enable for PGA P003 */ + __IOM uint16_t P003SEL1 : 1; /*!< [13..13] The amplifier passing is enable for PGA P003 */ + __IOM uint16_t P003ENAMP : 1; /*!< [14..14] Amplifier enable bit for PGA P003 */ + __IOM uint16_t P003GEN : 1; /*!< [15..15] PGA P003 gain setting and enable bit */ + } ADPGACR_b; }; - __IM uint32_t RESERVED16[6]; union { - __IOM uint32_t CFDTXQPCTR0[2]; /*!< (@ 0x00001040) TX Queue Pointer Control Registers 0 */ + __IOM uint16_t ADPGAGS0; /*!< (@ 0x000001A2) A/D Programmable Gain Amplifier Gain Setting + * Register 0 */ struct { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR0_b[2]; + __IOM uint16_t P000GAIN : 4; /*!< [3..0] PGA P000 gain setting bit.The gain magnification of (ADPGSDCR0.P000GEN= + * b) when the shingle end is input and each PGA P000 is set. + * When the differential motion is input, (ADPGSDCR0.P000GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P000DG 1:0. */ + __IOM uint16_t P001GAIN : 4; /*!< [7..4] PGA P001 gain setting bit.The gain magnification of (ADPGSDCR0.P001GEN= + * b) when the shingle end is input and each PGA P001 is set. + * When the differential motion is input, (ADPGSDCR0.P001GEN=1b) + * sets the gain magnification when the differential motion + * is input by the combination with ADPGSDCR0.P001DG 1:0. */ + __IOM uint16_t P002GAIN : 4; /*!< [11..8] PGA P002 gain setting bit.The gain magnification of + * (ADPGSDCR0.P002GEN=0b) when the shingle end is input and + * each PGA P002 is set. When the differential motion is input, + * (ADPGSDCR0.P002GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P002DG 1:0. */ + __IOM uint16_t P003GAIN : 4; /*!< [15..12] PGA P003 gain setting bit.The gain magnification of + * (ADPGSDCR0.P003GEN=0b) when the shingle end is input and + * each PGA P003 is set. When the differential motion is input, + * (ADPGSDCR0.P003GEN=1b) sets the gain magnification when + * the differential motion is input by the combination with + * ADPGSDCR0.P003DG 1:0. */ + } ADPGAGS0_b; }; - __IM uint32_t RESERVED17[6]; + __IM uint32_t RESERVED22[3]; union { - __IOM uint32_t CFDTXQCC1[2]; /*!< (@ 0x00001060) TX Queue Configuration / Control Registers 1 */ + __IOM uint16_t ADPGADCR0; /*!< (@ 0x000001B0) A/D Programmable Gain Amplifier Differential + * Input Control Register */ struct { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full Interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC1_b[2]; + __IOM uint16_t P000DG : 2; /*!< [1..0] P000 Differential Input Gain SettingNOTE: When these + * bits are used, set {P000DEN, P000GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P000DEN : 1; /*!< [3..3] P000 Differential Input Enable */ + __IOM uint16_t P001DG : 2; /*!< [5..4] P001 Differential Input Gain SettingNOTE: When these + * bits are used, set {P001DEN, P001GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P001DEN : 1; /*!< [7..7] P001 Differential Input Enable */ + __IOM uint16_t P002DG : 2; /*!< [9..8] P002 Differential Input Gain SettingNOTE: When these + * bits are used, set {P002DEN, P002GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P002DEN : 1; /*!< [11..11] P002 Differential Input Enable */ + __IOM uint16_t P003DG : 2; /*!< [13..12] P003 Differential Input Gain SettingNOTE: When these + * bits are used, set {P003DEN, P003GEN} to 11b. */ + uint16_t : 1; + __IOM uint16_t P003DEN : 1; /*!< [15..15] P003 Differential Input Enable */ + } ADPGADCR0_b; }; - __IM uint32_t RESERVED18[6]; + __IM uint16_t RESERVED23; union { - __IOM uint32_t CFDTXQSTS1[2]; /*!< (@ 0x00001080) TX Queue Status Registers 1 */ + __IOM uint8_t ADPGADBS0; /*!< (@ 0x000001B4) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 0 */ struct { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS1_b[2]; + __IOM uint8_t P0BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P000 to P002 Bias Voltage + * SelectNOTE: This bit selects the input bias voltage value + * when differential inputs are used. */ + uint8_t : 7; + } ADPGADBS0_b; }; - __IM uint32_t RESERVED19[6]; union { - __IOM uint32_t CFDTXQPCTR1[2]; /*!< (@ 0x000010A0) TX Queue Pointer Control Registers 1 */ + __IOM uint8_t ADPGADBS1; /*!< (@ 0x000001B5) A/D Programmable Gain Amplifier Differential + * Input Bias Select Register 1 */ struct { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR1_b[2]; + __IOM uint8_t P3BIAS : 1; /*!< [0..0] Programmable Gain Amplifiers P003 Bias Voltage SelectNOTE: + * This bit selects the input bias voltage value when differential + * inputs are used. */ + uint8_t : 7; + } ADPGADBS1_b; }; - __IM uint32_t RESERVED20[6]; + __IM uint16_t RESERVED24; + __IM uint32_t RESERVED25[10]; union { - __IOM uint32_t CFDTXQCC2[2]; /*!< (@ 0x000010C0) TX Queue Configuration / Control Registers 2 */ + __IOM uint32_t ADREFMON; /*!< (@ 0x000001E0) A/D External Reference Voltage Monitor Register */ struct { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - __IOM uint32_t TXQGWE : 1; /*!< [1..1] TX Queue Gateway Mode Enable */ - uint32_t : 3; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 3; - __IOM uint32_t TXQFIE : 1; /*!< [16..16] TXQ Full interrupt Enable */ - __IOM uint32_t TXQOFRXIE : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Enable */ - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC2_b[2]; + __IOM uint32_t PGAMON : 3; /*!< [2..0] PGA Monitor Output Enable */ + uint32_t : 13; + __IOM uint32_t MONSEL : 4; /*!< [19..16] Monitor output selection bit. */ + uint32_t : 12; + } ADREFMON_b; }; - __IM uint32_t RESERVED21[6]; +} R_ADC0_Type; /*!< Size = 484 (0x1e4) */ - union - { - __IOM uint32_t CFDTXQSTS2[2]; /*!< (@ 0x000010E0) TX Queue Status Registers 2 */ +/* =========================================================================================================================== */ +/* ================ R_PSCU ================ */ +/* =========================================================================================================================== */ - struct - { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 2; - __IOM uint32_t TXQFIF : 1; /*!< [16..16] TXQ Full Interrupt Flag */ - __IOM uint32_t TXQOFRXIF : 1; /*!< [17..17] TXQ One Frame Reception Interrupt Flag */ - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - __IOM uint32_t TXQMLT : 1; /*!< [19..19] TXQ Message Lost */ - uint32_t : 12; - } CFDTXQSTS2_b[2]; - }; - __IM uint32_t RESERVED22[6]; +/** + * @brief Peripheral Security Control Unit (R_PSCU) + */ + +typedef struct /*!< (@ 0x400E0000) R_PSCU Structure */ +{ + __IM uint32_t RESERVED; union { - __IOM uint32_t CFDTXQPCTR2[2]; /*!< (@ 0x00001100) TX Queue Pointer Control Registers 2 */ + __IOM uint32_t PSARB; /*!< (@ 0x00000004) Peripheral Security Attribution Register B */ struct { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR2_b[2]; + uint32_t : 1; + __IOM uint32_t PSARB1 : 1; /*!< [1..1] CAN1 and the MSTPCRB.MSTPB1 bit security attribution */ + __IOM uint32_t PSARB2 : 1; /*!< [2..2] CAN0 and the MSTPCRB.MSTPB2 bit security attribution */ + __IOM uint32_t PSARB3 : 1; /*!< [3..3] CEC and the MSTPCRB.MSTPB3 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB6 : 1; /*!< [6..6] QSPI and the MSTPCRB.MSTPB6 bit security attribution */ + __IOM uint32_t PSARB7 : 1; /*!< [7..7] IIC2 and the MSTPCRB.MSTPB7 bit security attribution */ + __IOM uint32_t PSARB8 : 1; /*!< [8..8] IIC1 and the MSTPCRB.MSTPB8 bit security attribution */ + __IOM uint32_t PSARB9 : 1; /*!< [9..9] IIC0 and the MSTPCRB.MSTPB9 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB11 : 1; /*!< [11..11] USBFS and the MSTPCRB.MSTPB11 bit security attribution */ + __IOM uint32_t PSARB12 : 1; /*!< [12..12] USBHS and the MSTPCRB.MSTPB12 bit security attribution */ + uint32_t : 2; + __IM uint32_t PSARB15 : 1; /*!< [15..15] ETHER0/EDMAC0, the MSTPCRB.MSTPB15 bit and the PFENET.PHYMODE0 + * bit security attribution */ + __IM uint32_t PSARB16 : 1; /*!< [16..16] OSPI and the MSTPCRB.MSTPB16 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARB18 : 1; /*!< [18..18] RSPI1 and the MSTPCRB.MSTPB18 bit security attribution */ + __IOM uint32_t PSARB19 : 1; /*!< [19..19] RSPI0 and the MSTPCRB.MSTPB19 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARB22 : 1; /*!< [22..22] SCI9 and the MSTPCRB.MSTPB22 bit security attribution */ + __IOM uint32_t PSARB23 : 1; /*!< [23..23] SCI8 and the MSTPCRB.MSTPB23 bit security attribution */ + __IOM uint32_t PSARB24 : 1; /*!< [24..24] SCI7 and the MSTPCRB.MSTPB24 bit security attribution */ + __IOM uint32_t PSARB25 : 1; /*!< [25..25] SCI6 and the MSTPCRB.MSTPB25 bit security attribution */ + __IOM uint32_t PSARB26 : 1; /*!< [26..26] SCI5 and the MSTPCRB.MSTPB26 bit security attribution */ + __IOM uint32_t PSARB27 : 1; /*!< [27..27] SCI4 and the MSTPCRB.MSTPB27 bit security attribution */ + __IOM uint32_t PSARB28 : 1; /*!< [28..28] SCI3 and the MSTPCRB.MSTPB28 bit security attribution */ + __IOM uint32_t PSARB29 : 1; /*!< [29..29] SCI2 and the MSTPCRB.MSTPB29 bit security attribution */ + __IOM uint32_t PSARB30 : 1; /*!< [30..30] SCI1 and the MSTPCRB.MSTPB30 bit security attribution */ + __IOM uint32_t PSARB31 : 1; /*!< [31..31] SCI0 and the MSTPCRB.MSTPB31 bit security attribution */ + } PSARB_b; }; - __IM uint32_t RESERVED23[6]; union { - __IOM uint32_t CFDTXQCC3[2]; /*!< (@ 0x00001120) TX Queue Configuration / Control Registers 3 */ + __IOM uint32_t PSARC; /*!< (@ 0x00000008) Peripheral Security Attribution Register C */ struct { - __IOM uint32_t TXQE : 1; /*!< [0..0] TX Queue Enable */ - uint32_t : 4; - __IOM uint32_t TXQTXIE : 1; /*!< [5..5] TX Queue TX Interrupt Enable */ - uint32_t : 1; - __IOM uint32_t TXQIM : 1; /*!< [7..7] TX Queue Interrupt Mode */ - __IOM uint32_t TXQDC : 5; /*!< [12..8] TX Queue Depth Configuration */ - uint32_t : 5; - __IOM uint32_t TXQOFTXIE : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Enable */ - uint32_t : 13; - } CFDTXQCC3_b[2]; + __IOM uint32_t PSARC0 : 1; /*!< [0..0] CAC and the MSTPCRC.MSTPC0 bit security attribution */ + __IOM uint32_t PSARC1 : 1; /*!< [1..1] CRC and the MSTPCRC.MSTPC1 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARC3 : 1; /*!< [3..3] CTSU and the MSTPCRC.MSTPC3 bit security attribution */ + uint32_t : 4; + __IOM uint32_t PSARC8 : 1; /*!< [8..8] SSIE0 and the MSTPCRC.MSTPC8 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC12 : 1; /*!< [12..12] SDHI0 and the MSTPCRC.MSTPC12 bit security attribution */ + __IOM uint32_t PSARC13 : 1; /*!< [13..13] DOC and the MSTPCRC.MSTPC13 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC20 : 1; /*!< [20..20] TFU and the MSTPCRC.MSTPC20 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARC27 : 1; /*!< [27..27] CANFD0 and the MSTPCRC.MSTPC27 bit security attribution */ + uint32_t : 3; + __IOM uint32_t PSARC31 : 1; /*!< [31..31] TSIP and the MSTPCRC.MSTPC31 bit security attribution */ + } PSARC_b; }; - __IM uint32_t RESERVED24[6]; union { - __IOM uint32_t CFDTXQSTS3[2]; /*!< (@ 0x00001140) TX Queue Status Registers 3 */ + __IOM uint32_t PSARD; /*!< (@ 0x0000000C) Peripheral Security Attribution Register D */ struct { - __IM uint32_t TXQEMP : 1; /*!< [0..0] TX Queue Empty */ - __IM uint32_t TXQFLL : 1; /*!< [1..1] TX Queue Full */ - __IOM uint32_t TXQTXIF : 1; /*!< [2..2] TX Queue TX Interrupt Flag */ - uint32_t : 5; - __IM uint32_t TXQMC : 6; /*!< [13..8] TX Queue Message Count */ - uint32_t : 4; - __IOM uint32_t TXQOFTXIF : 1; /*!< [18..18] TXQ One Frame Transmission Interrupt Flag */ - uint32_t : 13; - } CFDTXQSTS3_b[2]; + __IOM uint32_t PSARD0 : 1; /*!< [0..0] AGT3 and the MSTPCRD.MSTPD0 bit security attribution */ + __IOM uint32_t PSARD1 : 1; /*!< [1..1] AGT2 and the MSTPCRD.MSTPD1 bit security attribution */ + __IOM uint32_t PSARD2 : 1; /*!< [2..2] AGT1 and the MSTPCRD.MSTPD2 bit security attribution */ + __IOM uint32_t PSARD3 : 1; /*!< [3..3] AGT0 and the MSTPCRD.MSTPD3 bit security attribution */ + uint32_t : 7; + __IOM uint32_t PSARD11 : 1; /*!< [11..11] PGI3 and the MSTPCRD.MSTPD11 bit security attribution */ + __IOM uint32_t PSARD12 : 1; /*!< [12..12] PGI2 and the MSTPCRD.MSTPD12 bit security attribution */ + __IOM uint32_t PSARD13 : 1; /*!< [13..13] PGI1 and the MSTPCRD.MSTPD13 bit security attribution */ + __IOM uint32_t PSARD14 : 1; /*!< [14..14] PGI0 and the MSTPCRD.MSTPD14 bit security attribution */ + __IOM uint32_t PSARD15 : 1; /*!< [15..15] ADC1 and the MSTPCRD.MSTPD15 bit security attribution */ + __IOM uint32_t PSARD16 : 1; /*!< [16..16] ADC0 and the MSTPCRD.MSTPD16 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD19 : 1; /*!< [19..19] DAC121 and the MSTPCRD.MSTPD19 bit security attribution */ + __IOM uint32_t PSARD20 : 1; /*!< [20..20] DAC120 and the MSTPCRD.MSTPD20 bit security attribution */ + uint32_t : 1; + __IOM uint32_t PSARD22 : 1; /*!< [22..22] TSN and the MSTPCRD.MSTPD22 bit security attribution */ + uint32_t : 2; + __IOM uint32_t PSARD25 : 1; /*!< [25..25] ACMPHS3 and the MSTPCRD.MSTPD25 bit security attribution */ + __IOM uint32_t PSARD26 : 1; /*!< [26..26] ACMPHS2 and the MSTPCRD.MSTPD26 bit security attribution */ + __IOM uint32_t PSARD27 : 1; /*!< [27..27] ACMPHS1 and the MSTPCRD.MSTPD27 bit security attribution */ + __IOM uint32_t PSARD28 : 1; /*!< [28..28] ACMPHS0 and the MSTPCRD.MSTPD28 bit security attribution */ + uint32_t : 3; + } PSARD_b; }; - __IM uint32_t RESERVED25[6]; union { - __IOM uint32_t CFDTXQPCTR3[2]; /*!< (@ 0x00001160) TX Queue Pointer Control Registers 3 */ + __IOM uint32_t PSARE; /*!< (@ 0x00000010) Peripheral Security Attribution Register E */ struct { - __OM uint32_t TXQPC : 8; /*!< [7..0] TX Queue Pointer Control */ - uint32_t : 24; - } CFDTXQPCTR3_b[2]; + __IOM uint32_t PSARE0 : 1; /*!< [0..0] WDT security attribution */ + __IOM uint32_t PSARE1 : 1; /*!< [1..1] IWDT security attribution */ + __IOM uint32_t PSARE2 : 1; /*!< [2..2] RTC security attribution */ + uint32_t : 11; + __IOM uint32_t PSARE14 : 1; /*!< [14..14] AGT5 and the MSTPCRE.MSTPE14 bit security attribution */ + __IOM uint32_t PSARE15 : 1; /*!< [15..15] AGT4 and the MSTPCRE.MSTPE15 bit security attribution */ + uint32_t : 6; + __IOM uint32_t PSARE22 : 1; /*!< [22..22] GPT9 and the MSTPCRE.MSTPE22 bit security attribution */ + __IOM uint32_t PSARE23 : 1; /*!< [23..23] GPT8 and the MSTPCRE.MSTPE23 bit security attribution */ + __IOM uint32_t PSARE24 : 1; /*!< [24..24] GPT7 and the MSTPCRE.MSTPE24 bit security attribution */ + __IOM uint32_t PSARE25 : 1; /*!< [25..25] GPT6 and the MSTPCRE.MSTPE25 bit security attribution */ + __IOM uint32_t PSARE26 : 1; /*!< [26..26] GPT5 and the MSTPCRE.MSTPE26 bit security attribution */ + __IOM uint32_t PSARE27 : 1; /*!< [27..27] GPT4 and the MSTPCRE.MSTPE27 bit security attribution */ + __IOM uint32_t PSARE28 : 1; /*!< [28..28] GPT3 and the MSTPCRE.MSTPE28 bit security attribution */ + __IOM uint32_t PSARE29 : 1; /*!< [29..29] GPT2 and the MSTPCRE.MSTPE29 bit security attribution */ + __IOM uint32_t PSARE30 : 1; /*!< [30..30] GPT1 and the MSTPCRE.MSTPE30 bit security attribution */ + __IOM uint32_t PSARE31 : 1; /*!< [31..31] GPT0 and the MSTPCRE.MSTPE31 bit security attribution */ + } PSARE_b; }; - __IM uint32_t RESERVED26[6]; union { - __IM uint32_t CFDTXQESTS; /*!< (@ 0x00001180) TX Queue Empty Status Register */ + __IOM uint32_t MSSAR; /*!< (@ 0x00000014) Module Stop Security Attribution Register */ struct { - __IM uint32_t TXQxEMP : 8; /*!< [7..0] TXQ empty Status */ - uint32_t : 24; - } CFDTXQESTS_b; + __IOM uint32_t MSSAR0 : 1; /*!< [0..0] The MSTPCRC.MSTPC14 bit security attribution */ + __IOM uint32_t MSSAR1 : 1; /*!< [1..1] The MSTPCRA.MSTPA22 bit security attribution */ + __IOM uint32_t MSSAR2 : 1; /*!< [2..2] The MSTPCRA.MSTPA7 bit security attribution */ + __IOM uint32_t MSSAR3 : 1; /*!< [3..3] The MSTPCRA.MSTPA0 bit security attribution */ + uint32_t : 28; + } MSSAR_b; }; union { - __IOM uint32_t CFDTXQFISTS; /*!< (@ 0x00001184) TX Queue Full Interrupt Status Register */ + __IM uint32_t CFSAMONA; /*!< (@ 0x00000018) Code Flash Security Attribution Monitor Register + * A */ struct { - __IM uint32_t TXQ0FULL : 3; /*!< [2..0] TXQ Full Interrupt Status for channel 0 */ - uint32_t : 1; - __IM uint32_t TXQ1FULL : 3; /*!< [6..4] TXQ Full Interrupt Status for channel 1 */ - uint32_t : 25; - } CFDTXQFISTS_b; + uint32_t : 15; + __IM uint32_t CFS2 : 9; /*!< [23..15] Code Flash Secure area 2 */ + uint32_t : 8; + } CFSAMONA_b; }; union { - __IOM uint32_t CFDTXQMSTS; /*!< (@ 0x00001188) TX Queue Message Lost Status Register */ + __IM uint32_t CFSAMONB; /*!< (@ 0x0000001C) Code Flash Security Attribution Monitor Register + * B */ struct { - __IM uint32_t TXQ0ML : 3; /*!< [2..0] TXQ message lost Status for channel 0 */ - uint32_t : 1; - __IM uint32_t TXQ1ML : 3; /*!< [6..4] TXQ message lost Status for channel 1 */ - uint32_t : 25; - } CFDTXQMSTS_b; + uint32_t : 10; + __IM uint32_t CFS1 : 14; /*!< [23..10] Code Flash Secure area 1 */ + uint32_t : 8; + } CFSAMONB_b; }; - __IM uint32_t RESERVED27; union { - __IOM uint32_t CFDTXQISTS; /*!< (@ 0x00001190) TX Queue Interrupt Status Register */ + __IM uint32_t DFSAMON; /*!< (@ 0x00000020) Data Flash Security Attribution Monitor Register */ struct { - __IM uint32_t TXQ0ISF : 4; /*!< [3..0] TXQ Interrupt Status Flag for channel 0 */ - __IM uint32_t TXQ1ISF : 4; /*!< [7..4] TXQ Interrupt Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQISTS_b; + uint32_t : 10; + __IM uint32_t DFS : 6; /*!< [15..10] Data flash Secure area */ + uint32_t : 16; + } DFSAMON_b; }; union { - __IOM uint32_t CFDTXQOFTISTS; /*!< (@ 0x00001194) TX Queue One Frame TX Interrupt Status Register */ + __IM uint32_t SSAMONA; /*!< (@ 0x00000024) SRAM Security Attribution Monitor Register A */ struct { - __IM uint32_t TXQ0OFTISF : 4; /*!< [3..0] TXQ One Frame TX Interrupt Status Flag for channel 0 */ - __IM uint32_t TXQ1OFTISF : 4; /*!< [7..4] TXQ One Frame TX Interrupt Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQOFTISTS_b; + uint32_t : 13; + __IM uint32_t SS2 : 8; /*!< [20..13] SRAM Secure area 2 */ + uint32_t : 11; + } SSAMONA_b; }; union { - __IOM uint32_t CFDTXQOFRISTS; /*!< (@ 0x00001198) TX Queue One Frame RX Interrupt Status Register */ + __IM uint32_t SSAMONB; /*!< (@ 0x00000028) SRAM Security Attribution Monitor Register B */ struct { - __IM uint32_t TXQ0OFRISF : 3; /*!< [2..0] TXQ One Frame RX Interrupt Status Flag */ - uint32_t : 1; - __IM uint32_t TXQ1OFRISF : 3; /*!< [6..4] TXQ One Frame RX Interrupt Status Flag */ - uint32_t : 25; - } CFDTXQOFRISTS_b; + uint32_t : 10; + __IM uint32_t SS1 : 11; /*!< [20..10] SRAM secure area 1 */ + uint32_t : 11; + } SSAMONB_b; }; union { - __IM uint32_t CFDTXQFSTS; /*!< (@ 0x0000119C) TX Queue Full Status Register */ + __IM uint32_t DLMMON; /*!< (@ 0x0000002C) Device Lifecycle Management State Monitor Register */ struct { - __IM uint32_t TXQ0FSF : 4; /*!< [3..0] TXQ Full Status Flag for channel 0 */ - __IM uint32_t TXQ1FSF : 4; /*!< [7..4] TXQ Full Status Flag for channel 1 */ - uint32_t : 24; - } CFDTXQFSTS_b; + __IM uint32_t DLMMON : 4; /*!< [3..0] Device Lifecycle Management State Monitor */ + uint32_t : 28; + } DLMMON_b; }; - __IM uint32_t RESERVED28[24]; +} R_PSCU_Type; /*!< Size = 48 (0x30) */ + +/* =========================================================================================================================== */ +/* ================ R_AGTW0 ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Asynchronous General Purpose Timer (R_AGTW0) + */ +typedef struct /*!< (@ 0x400E8000) R_AGTW0 Structure */ +{ union { - __IOM uint32_t CFDTHLCC[2]; /*!< (@ 0x00001200) TX History List Configuration / Control Register */ + __IOM uint32_t AGT; /*!< (@ 0x00000000) AGT Counter Register */ struct { - __IOM uint32_t THLE : 1; /*!< [0..0] TX History List Enable */ - uint32_t : 7; - __IOM uint32_t THLIE : 1; /*!< [8..8] TX History List Interrupt Enable */ - __IOM uint32_t THLIM : 1; /*!< [9..9] TX History List Interrupt Mode */ - __IOM uint32_t THLDTE : 1; /*!< [10..10] TX History List Dedicated TX Enable */ - __IOM uint32_t THLDGE : 1; /*!< [11..11] TX History List Dedicated GW Enable */ - uint32_t : 20; - } CFDTHLCC_b[2]; + __IOM uint32_t AGT : 32; /*!< [31..0] 16bit counter and reload registerNOTE : When 1 is written + * to the TSTOP bit in the AGTCRn register, the 16-bit counter + * is forcibly stopped and set to FFFFH. */ + } AGT_b; }; - __IM uint32_t RESERVED29[6]; union { - __IOM uint32_t CFDTHLSTS[2]; /*!< (@ 0x00001220) TX History List Status Register */ + __IOM uint32_t AGTCMA; /*!< (@ 0x00000004) AGT Compare Match A Register */ struct { - __IM uint32_t THLEMP : 1; /*!< [0..0] TX History List Empty */ - __IM uint32_t THLFLL : 1; /*!< [1..1] TX History List Full */ - __IOM uint32_t THLELT : 1; /*!< [2..2] TX History List Entry Lost */ - __IOM uint32_t THLIF : 1; /*!< [3..3] TX History List Interrupt Flag */ - uint32_t : 4; - __IM uint32_t THLMC : 6; /*!< [13..8] TX History List Message Count */ - uint32_t : 18; - } CFDTHLSTS_b[2]; + __IOM uint32_t AGTCMA : 32; /*!< [31..0] AGT Compare Match A data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCRn register, set to + * FFFFH */ + } AGTCMA_b; }; - __IM uint32_t RESERVED30[6]; union { - __IOM uint32_t CFDTHLPCTR[2]; /*!< (@ 0x00001240) TX History List Pointer Control Registers */ + __IOM uint32_t AGTCMB; /*!< (@ 0x00000008) AGT Compare Match B Register */ struct { - __OM uint32_t THLPC : 8; /*!< [7..0] TX History List Pointer Control */ - uint32_t : 24; - } CFDTHLPCTR_b[2]; + __IOM uint32_t AGTCMB : 32; /*!< [31..0] AGT Compare Match B data is stored.NOTE : When 1 is + * written to the TSTOP bit in the AGTCR register, set to + * FFFFH */ + } AGTCMB_b; }; - __IM uint32_t RESERVED31[46]; union { - __IOM uint32_t CFDGTINTSTS0; /*!< (@ 0x00001300) Global TX Interrupt Status Register 0 */ + __IOM uint8_t AGTCR; /*!< (@ 0x0000000C) AGT Control Register */ struct { - __IM uint32_t TSIF0 : 1; /*!< [0..0] TX Successful Interrupt Flag Channel 0 */ - __IM uint32_t TAIF0 : 1; /*!< [1..1] TX Abort Interrupt Flag Channel 0 */ - __IM uint32_t TQIF0 : 1; /*!< [2..2] TX Queue Interrupt Flag Channel 0 */ - __IM uint32_t CFTIF0 : 1; /*!< [3..3] COM FIFO TX/GW Mode Interrupt Flag Channel 0 */ - __IM uint32_t THIF0 : 1; /*!< [4..4] TX History List Interrupt Channel 0 */ - __IM uint32_t TQOFIF0 : 1; /*!< [5..5] TX Queue One Frame Transmission Interrupt Flag Channel - * 0 */ - __IM uint32_t CFOTIF0 : 1; /*!< [6..6] COM FIFO One Frame Transmission Interrupt Flag Channel - * 0 */ - uint32_t : 1; - __IM uint32_t TSIF1 : 1; /*!< [8..8] TX Successful Interrupt Flag Channel 1 */ - __IM uint32_t TAIF1 : 1; /*!< [9..9] TX Abort Interrupt Flag Channel 1 */ - __IM uint32_t TQIF1 : 1; /*!< [10..10] TX Queue Interrupt Flag Channel 1 */ - __IM uint32_t CFTIF1 : 1; /*!< [11..11] COM FIFO TX/GW Mode Interrupt Flag Channel 1 */ - __IM uint32_t THIF1 : 1; /*!< [12..12] TX History List Interrupt Channel 1 */ - __IM uint32_t TQOFIF1 : 1; /*!< [13..13] TX Queue One Frame Transmission Interrupt Flag Channel - * 1 */ - __IM uint32_t CFOTIF1 : 1; /*!< [14..14] COM FIFO One Frame Transmission Interrupt Flag Channel - * 1 */ - uint32_t : 17; - } CFDGTINTSTS0_b; + __IOM uint8_t TSTART : 1; /*!< [0..0] AGT count start */ + __IM uint8_t TCSTF : 1; /*!< [1..1] AGT count status flag */ + __OM uint8_t TSTOP : 1; /*!< [2..2] AGT count forced stop */ + uint8_t : 1; + __IOM uint8_t TEDGF : 1; /*!< [4..4] Active edge judgment flag */ + __IOM uint8_t TUNDF : 1; /*!< [5..5] Underflow flag */ + __IOM uint8_t TCMAF : 1; /*!< [6..6] Compare match A flag */ + __IOM uint8_t TCMBF : 1; /*!< [7..7] Compare match B flag */ + } AGTCR_b; }; - __IM uint32_t RESERVED32; union { - __IOM uint32_t CFDGTSTCFG; /*!< (@ 0x00001308) Global Test Configuration Register */ + __IOM uint8_t AGTMR1; /*!< (@ 0x0000000D) AGT Mode Register 1 */ struct { - __IOM uint32_t ICBCE : 2; /*!< [1..0] Channel n Internal CAN Bus Communication Test Mode Enable */ - uint32_t : 14; - __IOM uint32_t RTMPS : 10; /*!< [25..16] RAM Test Mode Page Select */ - uint32_t : 6; - } CFDGTSTCFG_b; + __IOM uint8_t TMOD : 3; /*!< [2..0] Operating mode */ + __IOM uint8_t TEDGPL : 1; /*!< [3..3] Edge polarity */ + __IOM uint8_t TCK : 3; /*!< [6..4] Count source */ + uint8_t : 1; + } AGTMR1_b; }; union { - __IOM uint32_t CFDGTSTCTR; /*!< (@ 0x0000130C) Global Test Control Register */ + __IOM uint8_t AGTMR2; /*!< (@ 0x0000000E) AGT Mode Register 2 */ struct { - __IOM uint32_t ICBCTME : 1; /*!< [0..0] Internal CAN Bus Communication Test Mode Enable */ - uint32_t : 1; - __IOM uint32_t RTME : 1; /*!< [2..2] RAM Test Mode Enable */ - uint32_t : 29; - } CFDGTSTCTR_b; + __IOM uint8_t CKS : 3; /*!< [2..0] AGTLCLK/AGTSCLK count source clock frequency division + * ratio */ + uint8_t : 4; + __IOM uint8_t LPM : 1; /*!< [7..7] Low Power Mode */ + } AGTMR2_b; }; - __IM uint32_t RESERVED33; + __IM uint8_t RESERVED; union { - __IOM uint32_t CFDGFDCFG; /*!< (@ 0x00001314) Global FD Configuration register */ + __IOM uint8_t AGTIOC; /*!< (@ 0x00000010) AGT I/O Control Register */ struct { - __IOM uint32_t RPED : 1; /*!< [0..0] RES bit Protocol exception disable */ - uint32_t : 7; - __IOM uint32_t TSCCFG : 2; /*!< [9..8] Timestamp capture configuration */ - uint32_t : 22; - } CFDGFDCFG_b; + __IOM uint8_t TEDGSEL : 1; /*!< [0..0] I/O polarity switchFunction varies depending on the operating + * mode. */ + uint8_t : 1; + __IOM uint8_t TOE : 1; /*!< [2..2] AGTOn output enable */ + uint8_t : 1; + __IOM uint8_t TIPF : 2; /*!< [5..4] Input filter */ + __IOM uint8_t TIOGT : 2; /*!< [7..6] Count control */ + } AGTIOC_b; }; union { - __IOM uint32_t CFDGCRCCFG; /*!< (@ 0x00001318) Global FD CRC Configuration register */ + __IOM uint8_t AGTISR; /*!< (@ 0x00000011) AGT Event Pin Select Register */ struct { - __IOM uint32_t NIE : 1; /*!< [0..0] Non ISO enable */ - uint32_t : 31; - } CFDGCRCCFG_b; + uint8_t : 2; + __IOM uint8_t EEPS : 1; /*!< [2..2] AGTEE polarty selection */ + uint8_t : 5; + } AGTISR_b; }; union { - __IOM uint32_t CFDGLOCKK; /*!< (@ 0x0000131C) Global Lock Key Register */ + __IOM uint8_t AGTCMSR; /*!< (@ 0x00000012) AGT Compare Match Function Select Register */ struct { - __OM uint32_t LOCK : 16; /*!< [15..0] Lock Key */ - uint32_t : 16; - } CFDGLOCKK_b; + __IOM uint8_t TCMEA : 1; /*!< [0..0] Compare match A register enable */ + __IOM uint8_t TOEA : 1; /*!< [1..1] AGTOA output enable */ + __IOM uint8_t TOPOLA : 1; /*!< [2..2] AGTOA polarity select */ + uint8_t : 1; + __IOM uint8_t TCMEB : 1; /*!< [4..4] Compare match B register enable */ + __IOM uint8_t TOEB : 1; /*!< [5..5] AGTOB output enable */ + __IOM uint8_t TOPOLB : 1; /*!< [6..6] AGTOB polarity select */ + uint8_t : 1; + } AGTCMSR_b; }; union { - __IOM uint32_t CFDGLOTB; /*!< (@ 0x00001320) Global OTB FIFO Configuration / Status Register */ + __IOM uint8_t AGTIOSEL; /*!< (@ 0x00000013) AGT Pin Select Register */ struct { - __IOM uint32_t OTBFE : 1; /*!< [0..0] OTB FIFO Enable */ - uint32_t : 7; - __IM uint32_t OTBEMP : 1; /*!< [8..8] OTB FIFO Empty */ - __IM uint32_t OTBFLL : 1; /*!< [9..9] OTB FIFO Full */ - __IOM uint32_t OTBMLT : 1; /*!< [10..10] OTB FIFO Message Lost */ - __IM uint32_t OTBMC : 5; /*!< [15..11] OTB FIFO Message Count */ - uint32_t : 16; - } CFDGLOTB_b; + uint8_t : 4; + __IOM uint8_t TIES : 1; /*!< [4..4] AGTIO input enable */ + uint8_t : 3; + } AGTIOSEL_b; }; +} R_AGTW0_Type; /*!< Size = 20 (0x14) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS Structure */ +{ + __IOM R_BUS_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ union { - __IOM uint32_t CFDGAFLIGNENT; /*!< (@ 0x00001324) Global AFL Ignore Entry Register */ + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ struct { - __IOM uint32_t IRN : 9; /*!< [8..0] Ignore Rule Number */ - uint32_t : 7; - __IOM uint32_t ICN : 3; /*!< [18..16] Ignore Channel Number */ - uint32_t : 13; - } CFDGAFLIGNENT_b; + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[223]; + __IOM R_BUS_SDRAM_Type SDRAM; /*!< (@ 0x00000C00) SDRAM Registers */ + __IM uint32_t RESERVED3[235]; + __IOM R_BUS_BUSM_Type BUSM[6]; /*!< (@ 0x00001000) Master Bus Control Register Array */ + __IM uint32_t RESERVED4[58]; + __IOM R_BUS_BUSS_Type BUSS[16]; /*!< (@ 0x00001100) Slave Bus Control Register Array */ + __IM uint32_t RESERVED5[432]; + __IOM R_BUS_BUSERR_Type BUSERR[11]; /*!< (@ 0x00001800) Bus Error Registers */ +} R_BUS_Type; /*!< Size = 6320 (0x18b0) */ + +/* =========================================================================================================================== */ +/* ================ R_CAC ================ */ +/* =========================================================================================================================== */ +/** + * @brief Clock Frequency Accuracy Measurement Circuit (R_CAC) + */ + +typedef struct /*!< (@ 0x40083600) R_CAC Structure */ +{ union { - __IOM uint32_t CFDGAFLIGNCTR; /*!< (@ 0x00001328) Global AFL Ignore Control Register */ + __IOM uint8_t CACR0; /*!< (@ 0x00000000) CAC Control Register 0 */ struct { - __IOM uint32_t IREN : 1; /*!< [0..0] Ignore Rule Enable */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGAFLIGNCTR_b; + __IOM uint8_t CFME : 1; /*!< [0..0] Clock Frequency Measurement Enable. */ + uint8_t : 7; + } CACR0_b; }; - __IM uint32_t RESERVED34; union { - __IOM uint32_t CFDCDTCT; /*!< (@ 0x00001330) DMA Transfer Control Register */ + __IOM uint8_t CACR1; /*!< (@ 0x00000001) CAC Control Register 1 */ struct { - __IOM uint32_t RFDMAE0 : 1; /*!< [0..0] DMA Transfer Enable for RXFIFO 0 */ - __IOM uint32_t RFDMAE1 : 1; /*!< [1..1] DMA Transfer Enable for RXFIFO 1 */ - __IOM uint32_t RFDMAE2 : 1; /*!< [2..2] DMA Transfer Enable for RXFIFO 2 */ - __IOM uint32_t RFDMAE3 : 1; /*!< [3..3] DMA Transfer Enable for RXFIFO 3 */ - __IOM uint32_t RFDMAE4 : 1; /*!< [4..4] DMA Transfer Enable for RXFIFO 4 */ - __IOM uint32_t RFDMAE5 : 1; /*!< [5..5] DMA Transfer Enable for RXFIFO 5 */ - __IOM uint32_t RFDMAE6 : 1; /*!< [6..6] DMA Transfer Enable for RXFIFO 6 */ - __IOM uint32_t RFDMAE7 : 1; /*!< [7..7] DMA Transfer Enable for RXFIFO 7 */ - __IOM uint32_t CFDMAE0 : 1; /*!< [8..8] DMA Transfer Enable for Common FIFO 0 of channel 0 */ - __IOM uint32_t CFDMAE1 : 1; /*!< [9..9] DMA Transfer Enable for Common FIFO 0 of channel 1 */ - uint32_t : 22; - } CFDCDTCT_b; + __IOM uint8_t CACREFE : 1; /*!< [0..0] CACREF Pin Input Enable */ + __IOM uint8_t FMCS : 3; /*!< [3..1] Measurement Target Clock Select */ + __IOM uint8_t TCSS : 2; /*!< [5..4] Measurement Target Clock Frequency Division Ratio Select */ + __IOM uint8_t EDGES : 2; /*!< [7..6] Valid Edge Select */ + } CACR1_b; }; union { - __IM uint32_t CFDCDTSTS; /*!< (@ 0x00001334) DMA Transfer Status Register */ + __IOM uint8_t CACR2; /*!< (@ 0x00000002) CAC Control Register 2 */ struct { - __IM uint32_t RFDMASTS0 : 1; /*!< [0..0] DMA Transfer Status for RX FIFO 0 */ - __IM uint32_t RFDMASTS1 : 1; /*!< [1..1] DMA Transfer Status for RX FIFO 1 */ - __IM uint32_t RFDMASTS2 : 1; /*!< [2..2] DMA Transfer Status for RX FIFO 2 */ - __IM uint32_t RFDMASTS3 : 1; /*!< [3..3] DMA Transfer Status for RX FIFO 3 */ - __IM uint32_t RFDMASTS4 : 1; /*!< [4..4] DMA Transfer Status for RX FIFO 4 */ - __IM uint32_t RFDMASTS5 : 1; /*!< [5..5] DMA Transfer Status for RX FIFO 5 */ - __IM uint32_t RFDMASTS6 : 1; /*!< [6..6] DMA Transfer Status for RX FIFO 6 */ - __IM uint32_t RFDMASTS7 : 1; /*!< [7..7] DMA Transfer Status for RX FIFO 7 */ - __IM uint32_t CFDMASTS0 : 1; /*!< [8..8] DMA Transfer Status only for Common FIFO 0 of channel - * 0 */ - __IM uint32_t CFDMASTS1 : 1; /*!< [9..9] DMA Transfer Status only for Common FIFO 0 of channel - * 1 */ - uint32_t : 22; - } CFDCDTSTS_b; + __IOM uint8_t RPS : 1; /*!< [0..0] Reference Signal Select */ + __IOM uint8_t RSCS : 3; /*!< [3..1] Measurement Reference Clock Select */ + __IOM uint8_t RCDS : 2; /*!< [5..4] Measurement Reference Clock Frequency Division Ratio + * Select */ + __IOM uint8_t DFS : 2; /*!< [7..6] Digital Filter Selection */ + } CACR2_b; }; - __IM uint32_t RESERVED35[2]; union { - __IOM uint32_t CFDCDTTCT; /*!< (@ 0x00001340) DMA TX Transfer Control Register */ + __IOM uint8_t CAICR; /*!< (@ 0x00000003) CAC Interrupt Control Register */ struct { - __IOM uint32_t TQ0DMAE0 : 1; /*!< [0..0] DMA TX Transfer Enable for TXQ 0 of channel 0 */ - __IOM uint32_t TQ0DMAE1 : 1; /*!< [1..1] DMA TX Transfer Enable for TXQ 0 of channel 1 */ - uint32_t : 6; - __IOM uint32_t TQ3DMAE0 : 1; /*!< [8..8] DMA TX Transfer Enable for TXQ 3 of channel 0 */ - __IOM uint32_t TQ3DMAE1 : 1; /*!< [9..9] DMA TX Transfer Enable for TXQ 3 of channel 1 */ - uint32_t : 6; - __IOM uint32_t CFDMAE0 : 1; /*!< [16..16] DMA TX Transfer Enable for Common FIFO 2 of channel - * 0 */ - __IOM uint32_t CFDMAE1 : 1; /*!< [17..17] DMA TX Transfer Enable for Common FIFO 2 of channel - * 1 */ - uint32_t : 14; - } CFDCDTTCT_b; + __IOM uint8_t FERRIE : 1; /*!< [0..0] Frequency Error Interrupt Request Enable */ + __IOM uint8_t MENDIE : 1; /*!< [1..1] Measurement End Interrupt Request Enable */ + __IOM uint8_t OVFIE : 1; /*!< [2..2] Overflow Interrupt Request Enable */ + uint8_t : 1; + __OM uint8_t FERRFCL : 1; /*!< [4..4] FERRF Clear */ + __OM uint8_t MENDFCL : 1; /*!< [5..5] MENDF Clear */ + __OM uint8_t OVFFCL : 1; /*!< [6..6] OVFF Clear */ + uint8_t : 1; + } CAICR_b; }; union { - __IOM uint32_t CFDCDTTSTS; /*!< (@ 0x00001344) DMA TX Transfer Status Register */ + __IM uint8_t CASTR; /*!< (@ 0x00000004) CAC Status Register */ struct { - __IM uint32_t TQ0DMASTS0 : 1; /*!< [0..0] DMA TX Transfer Status for TXQ0 of channel 0 */ - __IM uint32_t TQ0DMASTS1 : 1; /*!< [1..1] DMA TX Transfer Status for TXQ0 of channel 1 */ - uint32_t : 6; - __IM uint32_t TQ3DMASTS0 : 1; /*!< [8..8] DMA TX Transfer Status for TXQ3 of channel 0 */ - __IM uint32_t TQ3DMASTS1 : 1; /*!< [9..9] DMA TX Transfer Status for TXQ3 of channel 1 */ - uint32_t : 6; - __IM uint32_t CFDMASTS0 : 1; /*!< [16..16] DMA TX Transfer Status only for Common FIFO 2 of channel - * 0 */ - __IM uint32_t CFDMASTS1 : 1; /*!< [17..17] DMA TX Transfer Status only for Common FIFO 2 of channel - * 1 */ - uint32_t : 14; - } CFDCDTTSTS_b; + __IM uint8_t FERRF : 1; /*!< [0..0] Frequency Error Flag */ + __IM uint8_t MENDF : 1; /*!< [1..1] Measurement End Flag */ + __IM uint8_t OVFF : 1; /*!< [2..2] Counter Overflow Flag */ + uint8_t : 5; + } CASTR_b; }; - __IM uint32_t RESERVED36[2]; + __IM uint8_t RESERVED; union { - __IOM uint32_t CFDGRINTSTS[2]; /*!< (@ 0x00001350) Global RX Interrupt Status Register */ - - struct - { - __IM uint32_t QFIF : 3; /*!< [2..0] TXQ Full Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t QOFRIF : 3; /*!< [10..8] TXQ One Frame RX Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t CFRIF : 3; /*!< [18..16] Common FIFO RX Interrupt Flag Channel n */ - uint32_t : 5; - __IM uint32_t CFRFIF : 3; /*!< [26..24] Common FIFO FDC level Full Interrupt Flag Channel n */ - uint32_t : 1; - __IM uint32_t CFOFRIF : 3; /*!< [30..28] Common FIFO One Frame RX Interrupt Flag Channel n */ - uint32_t : 1; - } CFDGRINTSTS_b[2]; + __IOM uint16_t CAULVR; /*!< (@ 0x00000006) CAC Upper-Limit Value Setting Register */ + + struct + { + __IOM uint16_t CAULVR : 16; /*!< [15..0] CAULVR is a 16-bit readable/writable register that stores + * the upper-limit value of the frequency. */ + } CAULVR_b; }; - __IM uint32_t RESERVED37[10]; union { - __IOM uint32_t CFDGRSTC; /*!< (@ 0x00001380) Global SW reset Register */ + __IOM uint16_t CALLVR; /*!< (@ 0x00000008) CAC Lower-Limit Value Setting Register */ struct { - __IOM uint32_t SRST : 1; /*!< [0..0] SW reset */ - uint32_t : 7; - __OM uint32_t KEY : 8; /*!< [15..8] Key code */ - uint32_t : 16; - } CFDGRSTC_b; + __IOM uint16_t CALLVR : 16; /*!< [15..0] CALLVR is a 16-bit readable/writable register that stores + * the lower-limit value of the frequency. */ + } CALLVR_b; }; - __IM uint32_t RESERVED38[31]; - __IOM R_CANFD_CFDC2_Type CFDC2[2]; /*!< (@ 0x00001400) Channel Configuration Registers */ - __IM uint32_t RESERVED39[240]; - __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00001800) Global Acceptance Filter List Registers */ - __IM uint32_t RESERVED40[448]; - __IOM R_CANFD_CFDRM_Type CFDRM[32]; /*!< (@ 0x00002000) RX Message Buffer Access Registers */ - __IM uint32_t RESERVED41[3072]; - __IOM R_CANFD_CFDRF_Type CFDRF[8]; /*!< (@ 0x00006000) RX FIFO Access Registers */ - __IOM R_CANFD_CFDCF_Type CFDCF[6]; /*!< (@ 0x00006400) Common FIFO Access Registers */ - __IM uint32_t RESERVED42[1600]; - __IOM R_CANFD_CFDTHL_Type CFDTHL[2]; /*!< (@ 0x00008000) Channel TX History List */ - __IM uint32_t RESERVED43[252]; union { - __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00008400) RAM Test Page Access Registers */ + __IM uint16_t CACNTBR; /*!< (@ 0x0000000A) CAC Counter Buffer Register */ struct { - __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ - } CFDRPGACC_b[64]; + __IM uint16_t CACNTBR : 16; /*!< [15..0] CACNTBR is a 16-bit read-only register that retains + * the counter value at the time a valid reference signal + * edge is input */ + } CACNTBR_b; }; - __IM uint32_t RESERVED44[7872]; - __IOM R_CANFD_CFDTM_Type CFDTM[128]; /*!< (@ 0x00010000) TX Message Buffer Access Registers */ -} R_CANFD_Type; /*!< Size = 81920 (0x14000) */ +} R_CAC_Type; /*!< Size = 12 (0xc) */ /* =========================================================================================================================== */ -/* ================ R_CANFDL ================ */ +/* ================ R_CANFD0 ================ */ /* =========================================================================================================================== */ /** - * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFDL) + * @brief Controller Area Network - Flexible Data (CAN-FD) Module (R_CANFD0) */ -typedef struct /*!< (@ 0x400B0000) R_CANFDL Structure */ +typedef struct /*!< (@ 0x400B0000) R_CANFD0 Structure */ { - __IOM R_CANFDL_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */ - __IM uint32_t RESERVED; + __IOM R_CANFD_CFDC_Type CFDC[1]; /*!< (@ 0x00000000) Channel Control/Status */ + __IM uint32_t RESERVED; union { @@ -6074,29 +4076,29 @@ typedef struct /*!< (@ 0x400B0000) R_CANFDL Structure uint32_t : 16; } CFDGRSTC_b; }; - __IM uint32_t RESERVED4[9]; - __IOM R_CANFDL_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */ - __IOM R_CANFDL_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */ - __IM uint32_t RESERVED5[24]; + __IM uint32_t RESERVED4[9]; + __IOM R_CANFD_CFDC2_Type CFDC2[1]; /*!< (@ 0x00000100) Channel Configuration Registers */ + __IOM R_CANFD_CFDGAFL_Type CFDGAFL[16]; /*!< (@ 0x00000120) Global Acceptance Filter List Registers */ + __IM uint32_t RESERVED5[24]; union { - __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */ + __IOM uint32_t CFDRPGACC[64]; /*!< (@ 0x00000280) RAM Test Page Access Registers */ struct { - __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ + __IOM uint32_t RDTA : 32; /*!< [31..0] RAM Data Test Access */ } CFDRPGACC_b[64]; }; - __IM uint32_t RESERVED6[104]; - __IOM R_CANFDL_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */ - __IOM R_CANFDL_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */ - __IOM R_CANFDL_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */ - __IM uint32_t RESERVED7[3]; - __IOM R_CANFDL_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */ - __IM uint32_t RESERVED8[118]; - __IOM R_CANFDL_CFDRMC_Type CFDRMC[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */ -} R_CANFDL_Type; /*!< Size = 6432 (0x1920) */ + __IM uint32_t RESERVED6[104]; + __IOM R_CANFD_CFDRF_Type CFDRF[2]; /*!< (@ 0x00000520) RX FIFO Access Registers */ + __IOM R_CANFD_CFDCF_Type CFDCF[1]; /*!< (@ 0x000005B8) Common FIFO Access Registers */ + __IOM R_CANFD_CFDTM_Type CFDTM[4]; /*!< (@ 0x00000604) TX Message Buffer Access Registers */ + __IM uint32_t RESERVED7[3]; + __IOM R_CANFD_CFDTHL_Type CFDTHL[1]; /*!< (@ 0x00000740) Channel TX History List */ + __IM uint32_t RESERVED8[118]; + __IOM R_CANFD_CFDRM_Type CFDRM[4]; /*!< (@ 0x00000920) RX Message Buffer Access Clusters */ +} R_CANFD_Type; /*!< Size = 6432 (0x1920) */ /* =========================================================================================================================== */ /* ================ R_CRC ================ */ @@ -6326,12 +4328,19 @@ typedef struct /*!< (@ 0x40172000) R_DAC Structure union { - __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ + __IOM uint8_t DAADUSR; /*!< (@ 0x000010C0) D/A A/D Synchronous Unit Select Register */ struct { - uint8_t : 6; - __IOM uint8_t AMADSEL1 : 1; /*!< [6..6] The DAADUSR register selects the target ADC12 unit for + __IOM uint8_t AMADSEL0 : 1; /*!< [0..0] The DAADUSR register selects the target ADC12 unit for + * D/A and A/D synchronous conversions. Set bit [0] to 1 to + * select unit 0 as the target synchronous unit for the MCU. + * When setting the DAADSCR.DAADST bit to 1 for synchronous + * conversions, select the target unit in this register in + * advance. Only set the DAADUSR register while the ADCSR.ADST + * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit + * is set to 0. */ + __IOM uint8_t AMADSEL1 : 1; /*!< [1..1] The DAADUSR register selects the target ADC12 unit for * D/A and A/D synchronous conversions. Set bit [1] to 1 to * select unit 1 as the target synchronous unit for the MCU. * When setting the DAADSCR.DAADST bit to 1 for synchronous @@ -6339,7 +4348,7 @@ typedef struct /*!< (@ 0x40172000) R_DAC Structure * advance. Only set the DAADUSR register while the ADCSR.ADST * bit of the ADC12 is set to 0 and the DAADSCR.DAADST bit * is set to 0. */ - uint8_t : 1; + uint8_t : 6; } DAADUSR_b; }; __IM uint8_t RESERVED3; @@ -10361,7 +8370,8 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure __IOM uint32_t MSTPC12 : 1; /*!< [12..12] Secure Digital Host IF/ Multi Media Card 0 Module Stop */ __IOM uint32_t MSTPC13 : 1; /*!< [13..13] Data Operation Circuit Module Stop */ __IOM uint32_t MSTPC14 : 1; /*!< [14..14] Event Link Controller Module Stop */ - uint32_t : 5; + __IOM uint32_t MSTPC15 : 1; /*!< [15..15] 32-bit Multiply-Accumulator Module Stop */ + uint32_t : 4; __IOM uint32_t MSTPC20 : 1; /*!< [20..20] Trigonometric Function Unit Module Stop */ __IOM uint32_t MSTPC21 : 1; /*!< [21..21] IIR Filter Accelerator Module Stop */ uint32_t : 5; @@ -10392,10 +8402,17 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure * In case the count source is sub-clock or LOCO, this bit * should be set to 1 except when accessing the registers * of AGT0. */ - uint32_t : 1; - __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ - __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ - uint32_t : 4; + uint32_t : 1; + __IOM uint32_t MSTPD5 : 1; /*!< [5..5] GPT Lower Module Stop */ + __IOM uint32_t MSTPD6 : 1; /*!< [6..6] GPT Higher Module Stop */ + __IOM uint32_t MSTPD7 : 1; /*!< [7..7] 16-bit Low Power Asynchronous General Purpose Timer 7 + * Module Stop */ + __IOM uint32_t MSTPD8 : 1; /*!< [8..8] 16-bit Low Power Asynchronous General Purpose Timer 6 + * Module Stop */ + __IOM uint32_t MSTPD9 : 1; /*!< [9..9] 16-bit Low Power Asynchronous General Purpose Timer 5 + * Module Stop */ + __IOM uint32_t MSTPD10 : 1; /*!< [10..10] 16-bit Low Power Asynchronous General Purpose Timer + * 4 Module Stop */ __IOM uint32_t MSTPD11 : 1; /*!< [11..11] Port Output Enable for GPT 3 Module Stop */ __IOM uint32_t MSTPD12 : 1; /*!< [12..12] Port Output Enable for GPT 2 Module Stop */ __IOM uint32_t MSTPD13 : 1; /*!< [13..13] Port Output Enable for GPT 1 Module Stop */ @@ -10403,7 +8420,8 @@ typedef struct /*!< (@ 0x40084000) R_MSTP Structure __IOM uint32_t MSTPD15 : 1; /*!< [15..15] 12-Bit A/D Converter 1 Module Stop */ __IOM uint32_t MSTPD16 : 1; /*!< [16..16] 16-Bit A/D Converter Module Stop */ __IOM uint32_t MSTPD17 : 1; /*!< [17..17] 24-bit Sigma-Delta A/DConverter Module Stop */ - uint32_t : 1; + __IOM uint32_t MSTPD18 : 1; /*!< [18..18] 16-bit Low Power Asynchronous General Purpose Timer + * 1 Module Stop */ __IOM uint32_t MSTPD19 : 1; /*!< [19..19] 8-Bit D/A Converter Module Stop */ __IOM uint32_t MSTPD20 : 1; /*!< [20..20] 12-bit D/A Converter Module Stop */ uint32_t : 1; @@ -10735,10 +8753,14 @@ typedef struct /*!< (@ 0x4001F000) R_PORT0 Structure * @brief I/O Ports-PFS (R_PFS) */ -typedef struct /*!< (@ 0x4001F800) R_PFS Structure */ +typedef struct /*!< (@ 0x4001F800) R_PFS Structure */ { - __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ -} R_PFS_Type; /*!< Size = 960 (0x3c0) */ + union + { + __IOM R_PFS_PORT_Type PORT[15]; /*!< (@ 0x00000000) Port [0..14] */ + __IOM R_PFS_VLSEL_Type VLSEL; /*!< (@ 0x00000000) VLSEL */ + }; +} R_PFS_Type; /*!< Size = 960 (0x3c0) */ /* =========================================================================================================================== */ /* ================ R_PMISC ================ */ @@ -11898,31 +9920,357 @@ typedef struct /*!< (@ 0x40002000) R_SRAM Structure __OM uint8_t KW2 : 7; /*!< [7..1] Write Key Code */ } ECCPRCR2_b; }; - __IM uint8_t RESERVED5[3]; + __IM uint8_t RESERVED5[3]; + + union + { + __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + + struct + { + __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ + uint8_t : 7; + } ECCETST_b; + }; + __IM uint8_t RESERVED6[3]; + + union + { + __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + + struct + { + __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ + uint8_t : 7; + } ECCOAD_b; + }; +} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + +/* =========================================================================================================================== */ +/* ================ R_BUS_B ================ */ +/* =========================================================================================================================== */ + +/** + * @brief Bus Interface (R_BUS_B) + */ + +typedef struct /*!< (@ 0x40003000) R_BUS_B Structure */ +{ + __IOM R_BUS_B_CSa_Type CSa[8]; /*!< (@ 0x00000000) CS Registers */ + __IM uint32_t RESERVED[480]; + __IOM R_BUS_B_CSb_Type CSb[8]; /*!< (@ 0x00000800) CS Registers */ + + union + { + __IOM uint16_t CSRECEN; /*!< (@ 0x00000880) CS Recovery Cycle Insertion Enable Register */ + + struct + { + __IOM uint16_t RCVEN0 : 1; /*!< [0..0] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN1 : 1; /*!< [1..1] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN2 : 1; /*!< [2..2] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN3 : 1; /*!< [3..3] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN4 : 1; /*!< [4..4] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN5 : 1; /*!< [5..5] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN6 : 1; /*!< [6..6] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVEN7 : 1; /*!< [7..7] Separate Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM0 : 1; /*!< [8..8] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM1 : 1; /*!< [9..9] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM2 : 1; /*!< [10..10] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM3 : 1; /*!< [11..11] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM4 : 1; /*!< [12..12] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM5 : 1; /*!< [13..13] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM6 : 1; /*!< [14..14] Multiplexed Bus Recovery Cycle Insertion Enable */ + __IOM uint16_t RCVENM7 : 1; /*!< [15..15] Multiplexed Bus Recovery Cycle Insertion Enable */ + } CSRECEN_b; + }; + __IM uint16_t RESERVED1; + __IM uint32_t RESERVED2[543]; + + union + { + __IOM uint16_t BUSSCNTFHBIU; /*!< (@ 0x00001100) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTFHBIU_b; + }; + __IM uint16_t RESERVED3; + + union + { + __IOM uint16_t BUSSCNTFLBIU; /*!< (@ 0x00001104) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTFLBIU_b; + }; + __IM uint16_t RESERVED4; + __IM uint32_t RESERVED5[2]; + + union + { + __IOM uint16_t BUSSCNTS0BIU; /*!< (@ 0x00001110) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTS0BIU_b; + }; + __IM uint16_t RESERVED6; + __IM uint32_t RESERVED7[3]; + + union + { + __IOM uint16_t BUSSCNTPSBIU; /*!< (@ 0x00001120) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPSBIU_b; + }; + __IM uint16_t RESERVED8; + __IM uint32_t RESERVED9[3]; + + union + { + __IOM uint16_t BUSSCNTPLBIU; /*!< (@ 0x00001130) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPLBIU_b; + }; + __IM uint16_t RESERVED10; + + union + { + __IOM uint16_t BUSSCNTPHBIU; /*!< (@ 0x00001134) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 1; /*!< [0..0] Arbitration Select for two masters */ + uint16_t : 15; + } BUSSCNTPHBIU_b; + }; + __IM uint16_t RESERVED11; + __IM uint32_t RESERVED12[2]; + + union + { + __IOM uint16_t BUSSCNTEQBIU; /*!< (@ 0x00001140) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTEQBIU_b; + }; + __IM uint16_t RESERVED13; + + union + { + __IOM uint16_t BUSSCNTEOBIU; /*!< (@ 0x00001144) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTEOBIU_b; + }; + __IM uint16_t RESERVED14; + + union + { + __IOM uint16_t BUSSCNTECBIU; /*!< (@ 0x00001148) Slave Bus Control Register */ + + struct + { + __IOM uint16_t ARBS : 2; /*!< [1..0] Arbitration Select for three masters */ + uint16_t : 14; + } BUSSCNTECBIU_b; + }; + __IM uint16_t RESERVED15; + __IM uint32_t RESERVED16[429]; + __IOM R_BUS_B_BUSERR_Type BUSERR[4]; /*!< (@ 0x00001800) Bus Error Registers */ + __IM uint32_t RESERVED17[48]; + __IOM R_BUS_B_BUSTZFERR_Type BUSTZFERR[4]; /*!< (@ 0x00001900) Bus TZF Error Registers */ + __IM uint32_t RESERVED18[48]; + + union + { + __IM uint8_t BUS1ERRSTAT; /*!< (@ 0x00001A00) BUS Error Status Register 1 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS1ERRSTAT_b; + }; + __IM uint8_t RESERVED19; + __IM uint16_t RESERVED20; + __IM uint32_t RESERVED21; + + union + { + __IOM uint8_t BUS1ERRCLR; /*!< (@ 0x00001A08) BUS Error Clear Register 1 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS1ERRCLR_b; + }; + __IM uint8_t RESERVED22; + __IM uint16_t RESERVED23; + __IM uint32_t RESERVED24; + + union + { + __IM uint8_t BUS2ERRSTAT; /*!< (@ 0x00001A10) BUS Error Status Register 2 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS2ERRSTAT_b; + }; + __IM uint8_t RESERVED25; + __IM uint16_t RESERVED26; + __IM uint32_t RESERVED27; + + union + { + __IOM uint8_t BUS2ERRCLR; /*!< (@ 0x00001A18) BUS Error Clear Register 2 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS2ERRCLR_b; + }; + __IM uint8_t RESERVED28; + __IM uint16_t RESERVED29; + __IM uint32_t RESERVED30; + + union + { + __IM uint8_t BUS3ERRSTAT; /*!< (@ 0x00001A20) BUS Error Status Register 3 */ + + struct + { + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS3ERRSTAT_b; + }; + __IM uint8_t RESERVED31; + __IM uint16_t RESERVED32; + + union + { + __IM uint8_t DMACDTCERRSTAT; /*!< (@ 0x00001A24) DMAC/DTC Error Status Register */ + + struct + { + __IM uint8_t MTERRSTAT : 1; /*!< [0..0] Master TrustZone Filter Error Status */ + uint8_t : 7; + } DMACDTCERRSTAT_b; + }; + __IM uint8_t RESERVED33; + __IM uint16_t RESERVED34; + + union + { + __IOM uint8_t BUS3ERRCLR; /*!< (@ 0x00001A28) BUS Error Clear Register 3 */ + + struct + { + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS3ERRCLR_b; + }; + __IM uint8_t RESERVED35; + __IM uint16_t RESERVED36; + + union + { + __IOM uint8_t DMACDTCERRCLR; /*!< (@ 0x00001A2C) DMAC/DTC Error Clear Register */ + + struct + { + __IOM uint8_t MTERRCLR : 1; /*!< [0..0] Master TrustZone filter Error Clear */ + uint8_t : 7; + } DMACDTCERRCLR_b; + }; + __IM uint8_t RESERVED37; + __IM uint16_t RESERVED38; union { - __IOM uint8_t ECCETST; /*!< (@ 0x000000D4) ECC Test Control Register */ + __IM uint8_t BUS4ERRSTAT; /*!< (@ 0x00001A30) BUS Error Status Register 4 */ struct { - __IOM uint8_t TSTBYP : 1; /*!< [0..0] ECC Bypass Select */ - uint8_t : 7; - } ECCETST_b; + __IM uint8_t SLERRSTAT : 1; /*!< [0..0] Slave bus Error Status */ + __IM uint8_t STERRSTAT : 1; /*!< [1..1] Slave TrustZone filter Error Status */ + uint8_t : 1; + __IM uint8_t MMERRSTAT : 1; /*!< [3..3] Master MPU Error Status */ + __IM uint8_t ILERRSTAT : 1; /*!< [4..4] Illegal address access Error Status */ + uint8_t : 3; + } BUS4ERRSTAT_b; }; - __IM uint8_t RESERVED6[3]; + __IM uint8_t RESERVED39; + __IM uint16_t RESERVED40; + __IM uint32_t RESERVED41; union { - __IOM uint8_t ECCOAD; /*!< (@ 0x000000D8) SRAM ECC Error Operation After Detection Register */ + __IOM uint8_t BUS4ERRCLR; /*!< (@ 0x00001A38) BUS Error Clear Register 4 */ struct { - __IOM uint8_t OAD : 1; /*!< [0..0] Operation after Detection */ - uint8_t : 7; - } ECCOAD_b; + __IOM uint8_t SLERRCLR : 1; /*!< [0..0] Slave bus Error Clear */ + __IOM uint8_t STERRCLR : 1; /*!< [1..1] Slave TrustZone filter Error Clear */ + uint8_t : 1; + __IOM uint8_t MMERRCLR : 1; /*!< [3..3] Master MPU Error Clear */ + __IOM uint8_t ILERRCLR : 1; /*!< [4..4] Illegal Address Access Error Clear */ + uint8_t : 3; + } BUS4ERRCLR_b; }; -} R_SRAM_Type; /*!< Size = 217 (0xd9) */ + __IM uint8_t RESERVED42; + __IM uint16_t RESERVED43; +} R_BUS_B_Type; /*!< Size = 6716 (0x1a3c) */ /* =========================================================================================================================== */ /* ================ R_SYSTEM ================ */ @@ -12373,24 +10721,52 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ + union + { + __IOM uint8_t GPTCKDIVCR; /*!< (@ 0x0000006F) GPT Clock Division Control Register */ - struct + struct + { + __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ + uint8_t : 5; + } GPTCKDIVCR_b; + }; + + union { - __IOM uint8_t GPTCKDIV : 3; /*!< [2..0] GPT Clock (GPTCLK) Division Select */ - uint8_t : 5; - } GPTCKDIVCR_b; + __IOM uint8_t USB60CKDIVCR; /*!< (@ 0x0000006F) USB60 Clock Division Control Register */ + + struct + { + __IOM uint8_t USB60CKDIV : 3; /*!< [2..0] USB clock (USB60CLK) Division Select */ + uint8_t : 5; + } USB60CKDIVCR_b; + }; }; union { - __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + union + { + __IOM uint8_t CECCKDIVCR; /*!< (@ 0x00000070) CEC Clock Division Control Register */ - struct + struct + { + __IOM uint8_t CECCKDIV : 3; /*!< [2..0] CEC clock (CECCLK) Division Select */ + uint8_t : 5; + } CECCKDIVCR_b; + }; + + union { - __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ - uint8_t : 5; - } IICCKDIVCR_b; + __IOM uint8_t IICCKDIVCR; /*!< (@ 0x00000070) IIC Clock Division Control Register */ + + struct + { + __IOM uint8_t IICCKDIV : 3; /*!< [2..0] IIC Clock (IICCLK) Division Select */ + uint8_t : 5; + } IICCKDIVCR_b; + }; }; __IM uint8_t RESERVED20; __IM uint16_t RESERVED21; @@ -12452,32 +10828,76 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure union { - __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ + union + { + __IOM uint8_t GPTCKCR; /*!< (@ 0x00000077) GPT Clock Control Register */ - struct + struct + { + __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ + __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ + } GPTCKCR_b; + }; + + union { - __IOM uint8_t GPTCKSEL : 3; /*!< [2..0] GPT Clock (GPTCLK) Source Select */ - uint8_t : 3; - __IOM uint8_t GPTCKSREQ : 1; /*!< [6..6] GPT Clock (GPTCLK) Switching Request */ - __IM uint8_t GPTCKSRDY : 1; /*!< [7..7] GPT Clock (GPTCLK) Switching Ready state flag */ - } GPTCKCR_b; + __IOM uint8_t USB60CKCR; /*!< (@ 0x00000077) USB60 clock control register */ + + struct + { + __IOM uint8_t USB60CKSEL : 4; /*!< [3..0] USB clock (USB60CLK) Source Select */ + uint8_t : 2; + __IOM uint8_t USB60CKSREQ : 1; /*!< [6..6] USB clock (USB60CLK) Switching Request */ + __IOM uint8_t USB60CKSRDY : 1; /*!< [7..7] USB clock (USB60CLK) Switching Ready state flag */ + } USB60CKCR_b; + }; + }; + + union + { + union + { + __IOM uint8_t CECCKCR; /*!< (@ 0x00000078) CEC Clock Control Register */ + + struct + { + __IOM uint8_t CECCKSEL : 3; /*!< [2..0] CEC clock (CECCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t CECCKSREQ : 1; /*!< [6..6] CEC clock (CECCLK) Switching Request */ + __IM uint8_t CECCKSRDY : 1; /*!< [7..7] CEC clock (CECCLK) Switching Ready state flag */ + } CECCKCR_b; + }; + + union + { + __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + + struct + { + __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + uint8_t : 3; + __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ + __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ + } IICCKCR_b; + }; }; union { - __IOM uint8_t IICCKCR; /*!< (@ 0x00000078) IIC Clock Control Register */ + __IOM uint8_t I3CCKCR; /*!< (@ 0x00000079) I3C Clock Control Register */ struct { - __IOM uint8_t IICCKSEL : 3; /*!< [2..0] IIC Clock (IICCLK) Source Select */ + __IOM uint8_t I3CCKSEL : 3; /*!< [2..0] I3C clock (I3CCLK) source select */ uint8_t : 3; - __IOM uint8_t IICCKSREQ : 1; /*!< [6..6] IIC Clock (IICCLK) Switching Request */ - __IM uint8_t IICCKSRDY : 1; /*!< [7..7] IIC Clock (IICCLK) Switching Ready state flag */ - } IICCKCR_b; + __IOM uint8_t I3CCKSREQ : 1; /*!< [6..6] I3C clock (I3CCLK) switching request */ + __IM uint8_t I3CCKSRDY : 1; /*!< [7..7] I3C clock (I3CCLK) switching ready state flag */ + } I3CCKCR_b; }; - __IM uint8_t RESERVED22; - __IM uint16_t RESERVED23; - __IM uint32_t RESERVED24[3]; + __IM uint16_t RESERVED22; + __IM uint32_t RESERVED23[3]; union { @@ -12491,8 +10911,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 29; } SNZREQCR1_b; }; - __IM uint32_t RESERVED25; - __IM uint16_t RESERVED26; + __IM uint32_t RESERVED24; + __IM uint16_t RESERVED25; union { @@ -12507,7 +10927,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SNZE : 1; /*!< [7..7] Snooze Mode Enable */ } SNZCR_b; }; - __IM uint8_t RESERVED27; + __IM uint8_t RESERVED26; union { @@ -12537,7 +10957,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } SNZEDCR1_b; }; - __IM uint16_t RESERVED28; + __IM uint16_t RESERVED27; union { @@ -12580,7 +11000,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 1; } SNZREQCR_b; }; - __IM uint16_t RESERVED29; + __IM uint16_t RESERVED28; union { @@ -12618,7 +11038,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } OPCCR_b; }; - __IM uint8_t RESERVED30; + __IM uint8_t RESERVED29; union { @@ -12630,7 +11050,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } MOSCWTCR_b; }; - __IM uint8_t RESERVED31[2]; + __IM uint8_t RESERVED30[2]; union { @@ -12643,7 +11063,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 5; } HOCOWTCR_b; }; - __IM uint16_t RESERVED32[2]; + __IM uint16_t RESERVED31[2]; union { @@ -12657,8 +11077,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } SOPCCR_b; }; - __IM uint8_t RESERVED33; - __IM uint32_t RESERVED34[5]; + __IM uint8_t RESERVED32; + __IM uint32_t RESERVED33[5]; union { @@ -12692,8 +11112,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint16_t CPERF : 1; /*!< [15..15] Cache Parity Error Reset Detect Flag */ } RSTSR1_b; }; - __IM uint16_t RESERVED35; - __IM uint32_t RESERVED36[3]; + __IM uint16_t RESERVED34; + __IM uint32_t RESERVED35[3]; union { @@ -12719,8 +11139,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t SDADCCKEN : 1; /*!< [7..7] 24-bit Sigma-Delta A/D Converter Clock Enable */ } SDADCCKCR_b; }; - __IM uint16_t RESERVED37; - __IM uint32_t RESERVED38[3]; + __IM uint16_t RESERVED36; + __IM uint32_t RESERVED37[3]; union { @@ -12775,7 +11195,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } LVD2SR_b; }; - __IM uint32_t RESERVED39[183]; + __IM uint32_t RESERVED38[183]; union { @@ -12803,7 +11223,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 14; } CGFSAR_b; }; - __IM uint32_t RESERVED40; + __IM uint32_t RESERVED39; union { @@ -12872,7 +11292,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 8; } BBFSAR_b; }; - __IM uint32_t RESERVED41[3]; + __IM uint32_t RESERVED40[3]; union { @@ -12934,8 +11354,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint32_t : 4; } DPFSAR_b; }; - __IM uint32_t RESERVED42[6]; - __IM uint16_t RESERVED43; + __IM uint32_t RESERVED41[6]; + __IM uint16_t RESERVED42; union { @@ -13153,7 +11573,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 3; } DPSIEGR2_b; }; - __IM uint8_t RESERVED44; + __IM uint8_t RESERVED43; union { @@ -13211,7 +11631,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } RSTSR2_b; }; - __IM uint8_t RESERVED45; + __IM uint8_t RESERVED44; union { @@ -13228,7 +11648,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * Enable */ } MOMCR_b; }; - __IM uint16_t RESERVED46; + __IM uint16_t RESERVED45; union { @@ -13298,7 +11718,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure } LVD2CMPCR_b; }; }; - __IM uint8_t RESERVED47; + __IM uint8_t RESERVED46; union { @@ -13331,7 +11751,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure __IOM uint8_t RN : 1; /*!< [7..7] Voltage Monitor Reset Negate Select */ } LVD2CR0_b; }; - __IM uint8_t RESERVED48; + __IM uint8_t RESERVED47; union { @@ -13366,7 +11786,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCR1_b; }; - __IM uint32_t RESERVED49[8]; + __IM uint32_t RESERVED48[8]; union { @@ -13409,7 +11829,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VCCSEL_b; }; - __IM uint16_t RESERVED50; + __IM uint16_t RESERVED49; union { @@ -13421,9 +11841,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } PL2LDOSCR_b; }; - __IM uint8_t RESERVED51; - __IM uint16_t RESERVED52; - __IM uint32_t RESERVED53[14]; + __IM uint8_t RESERVED50; + __IM uint16_t RESERVED51; + __IM uint32_t RESERVED52[14]; union { @@ -13446,8 +11866,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } SOMCR_b; }; - __IM uint16_t RESERVED54; - __IM uint32_t RESERVED55[3]; + __IM uint16_t RESERVED53; + __IM uint32_t RESERVED54[3]; union { @@ -13459,7 +11879,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } LOCOCR_b; }; - __IM uint8_t RESERVED56; + __IM uint8_t RESERVED55; union { @@ -13474,8 +11894,8 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure * trimming bits */ } LOCOUTCR_b; }; - __IM uint8_t RESERVED57; - __IM uint32_t RESERVED58[7]; + __IM uint8_t RESERVED56; + __IM uint32_t RESERVED57[7]; union { @@ -13514,7 +11934,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTCMPCR_b; }; - __IM uint8_t RESERVED59; + __IM uint8_t RESERVED58; union { @@ -13528,7 +11948,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 6; } VBTLVDICR_b; }; - __IM uint8_t RESERVED60; + __IM uint8_t RESERVED59; union { @@ -13540,7 +11960,7 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 7; } VBTWCTLR_b; }; - __IM uint8_t RESERVED61; + __IM uint8_t RESERVED60; union { @@ -13675,9 +12095,9 @@ typedef struct /*!< (@ 0x4001E000) R_SYSTEM Structure uint8_t : 4; } VBTBER_b; }; - __IM uint8_t RESERVED62; - __IM uint16_t RESERVED63; - __IM uint32_t RESERVED64[15]; + __IM uint8_t RESERVED61; + __IM uint16_t RESERVED62; + __IM uint32_t RESERVED63[15]; union { @@ -20006,10 +18426,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_AGTW1_BASE 0x400E8100UL #define R_BUS_BASE 0x40003000UL #define R_CAC_BASE 0x40083600UL - #define R_CAN0_BASE 0x400A8000UL - #define R_CAN1_BASE 0x400A9000UL #define R_CANFD_BASE 0x400B0000UL - #define R_CANFDL_BASE 0x400B0000UL + #define R_CANFD1_BASE 0x400B2000UL #define R_CRC_BASE 0x40108000UL #define R_DAC_BASE 0x40172000UL #define R_DAC1_BASE 0x40172100UL @@ -20090,6 +18508,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0_BASE 0x4011A000UL #define R_SPI1_BASE 0x4011A100UL #define R_SRAM_BASE 0x40002000UL + #define R_BUS_B_BASE 0x40003000UL #define R_SYSTEM_BASE 0x4001E000UL #define R_TSN_CAL_BASE 0x407FB17CUL #define R_TSN_CTRL_BASE 0x400F3000UL @@ -20131,12 +18550,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_PSCU ((R_PSCU_Type *) R_PSCU_BASE) #define R_AGTW0 ((R_AGTW0_Type *) R_AGTW0_BASE) #define R_AGTW1 ((R_AGTW0_Type *) R_AGTW1_BASE) - #define R_BUS ((R_BUS_Type *) R_BUS_BASE) + +/* #define R_BUS ((R_BUS_Type*) R_BUS_BASE) */ #define R_CAC ((R_CAC_Type *) R_CAC_BASE) - #define R_CAN0 ((R_CAN0_Type *) R_CAN0_BASE) - #define R_CAN1 ((R_CAN0_Type *) R_CAN1_BASE) - #define R_CANFD ((R_CANFDL_Type *) R_CANFD_BASE) - #define R_CANFDL ((R_CANFDL_Type *) R_CANFDL_BASE) + #define R_CANFD ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD0 ((R_CANFD_Type *) R_CANFD_BASE) + #define R_CANFD1 ((R_CANFD_Type *) R_CANFD1_BASE) #define R_CRC ((R_CRC_Type *) R_CRC_BASE) #define R_DAC0 ((R_DAC_Type *) R_DAC_BASE) #define R_DAC1 ((R_DAC_Type *) R_DAC1_BASE) @@ -20217,6 +18636,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SPI0 ((R_SPI0_Type *) R_SPI0_BASE) #define R_SPI1 ((R_SPI0_Type *) R_SPI1_BASE) #define R_SRAM ((R_SRAM_Type *) R_SRAM_BASE) + #define R_BUS ((R_BUS_B_Type *) R_BUS_B_BASE) #define R_SYSTEM ((R_SYSTEM_Type *) R_SYSTEM_BASE) #define R_TSN_CAL ((R_TSN_CAL_Type *) R_TSN_CAL_BASE) #define R_TSN_CTRL ((R_TSN_CTRL_Type *) R_TSN_CTRL_BASE) @@ -20419,31 +18839,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_BUS_BUSS_CNT_ARBMET_Pos (4UL) /*!< ARBMET (Bit 4) */ #define R_BUS_BUSS_CNT_ARBMET_Msk (0x30UL) /*!< ARBMET (Bitfield-Mask: 0x03) */ -/* =========================================================================================================================== */ -/* ================ MB ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CAN0_MB_ID_IDE_Pos (31UL) /*!< IDE (Bit 31) */ - #define R_CAN0_MB_ID_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ - #define R_CAN0_MB_ID_RTR_Pos (30UL) /*!< RTR (Bit 30) */ - #define R_CAN0_MB_ID_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ - #define R_CAN0_MB_ID_SID_Pos (18UL) /*!< SID (Bit 18) */ - #define R_CAN0_MB_ID_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ - #define R_CAN0_MB_ID_EID_Pos (0UL) /*!< EID (Bit 0) */ - #define R_CAN0_MB_ID_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ -/* ========================================================== DL =========================================================== */ - #define R_CAN0_MB_DL_DLC_Pos (0UL) /*!< DLC (Bit 0) */ - #define R_CAN0_MB_DL_DLC_Msk (0xfUL) /*!< DLC (Bitfield-Mask: 0x0f) */ -/* =========================================================== D =========================================================== */ - #define R_CAN0_MB_D_DATA_Pos (0UL) /*!< DATA (Bit 0) */ - #define R_CAN0_MB_D_DATA_Msk (0xffUL) /*!< DATA (Bitfield-Mask: 0xff) */ -/* ========================================================== TS =========================================================== */ - #define R_CAN0_MB_TS_TSH_Pos (8UL) /*!< TSH (Bit 8) */ - #define R_CAN0_MB_TS_TSH_Msk (0xff00UL) /*!< TSH (Bitfield-Mask: 0xff) */ - #define R_CAN0_MB_TS_TSL_Pos (0UL) /*!< TSL (Bit 0) */ - #define R_CAN0_MB_TS_TSL_Msk (0xffUL) /*!< TSL (Bitfield-Mask: 0xff) */ - /* =========================================================================================================================== */ /* ================ CFDC ================ */ /* =========================================================================================================================== */ @@ -20496,12 +18891,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ #define R_CANFD_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDC_CTR_TRWE_Pos (27UL) /*!< TRWE (Bit 27) */ - #define R_CANFD_CFDC_CTR_TRWE_Msk (0x8000000UL) /*!< TRWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TRH_Pos (28UL) /*!< TRH (Bit 28) */ - #define R_CANFD_CFDC_CTR_TRH_Msk (0x10000000UL) /*!< TRH (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC_CTR_TRR_Pos (29UL) /*!< TRR (Bit 29) */ - #define R_CANFD_CFDC_CTR_TRR_Msk (0x20000000UL) /*!< TRR (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ #define R_CANFD_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ @@ -20587,20 +18976,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ #define R_CANFD_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDC2_FDCFG_GWEN_Pos (24UL) /*!< GWEN (Bit 24) */ - #define R_CANFD_CFDC2_FDCFG_GWEN_Msk (0x1000000UL) /*!< GWEN (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_GWFDF_Pos (25UL) /*!< GWFDF (Bit 25) */ - #define R_CANFD_CFDC2_FDCFG_GWFDF_Msk (0x2000000UL) /*!< GWFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_GWBRS_Pos (26UL) /*!< GWBRS (Bit 26) */ - #define R_CANFD_CFDC2_FDCFG_GWBRS_Msk (0x4000000UL) /*!< GWBRS (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ #define R_CANFD_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ #define R_CANFD_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ #define R_CANFD_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_FDCFG_CFDTE_Pos (31UL) /*!< CFDTE (Bit 31) */ - #define R_CANFD_CFDC2_FDCFG_CFDTE_Msk (0x80000000UL) /*!< CFDTE (Bitfield-Mask: 0x01) */ /* ========================================================= FDCTR ========================================================= */ #define R_CANFD_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ #define R_CANFD_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ @@ -20624,14 +19005,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ #define R_CANFD_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ #define R_CANFD_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ -/* ========================================================= BLCT ========================================================== */ - #define R_CANFD_CFDC2_BLCT_BLCE_Pos (0UL) /*!< BLCE (Bit 0) */ - #define R_CANFD_CFDC2_BLCT_BLCE_Msk (0x1UL) /*!< BLCE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDC2_BLCT_BLCLD_Pos (8UL) /*!< BLCLD (Bit 8) */ - #define R_CANFD_CFDC2_BLCT_BLCLD_Msk (0x100UL) /*!< BLCLD (Bitfield-Mask: 0x01) */ -/* ========================================================= BLSTS ========================================================= */ - #define R_CANFD_CFDC2_BLSTS_BLC_Pos (3UL) /*!< BLC (Bit 3) */ - #define R_CANFD_CFDC2_BLSTS_BLC_Msk (0xfffffff8UL) /*!< BLC (Bitfield-Mask: 0x1fffffff) */ /* =========================================================================================================================== */ /* ================ CFDGAFL ================ */ @@ -20658,12 +19031,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ========================================================== P0 =========================================================== */ #define R_CANFD_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ #define R_CANFD_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Pos (4UL) /*!< GAFLSRD0 (Bit 4) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD0_Msk (0x10UL) /*!< GAFLSRD0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Pos (5UL) /*!< GAFLSRD1 (Bit 5) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD1_Msk (0x20UL) /*!< GAFLSRD1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Pos (6UL) /*!< GAFLSRD2 (Bit 6) */ - #define R_CANFD_CFDGAFL_P0_GAFLSRD2_Msk (0x40UL) /*!< GAFLSRD2 (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ #define R_CANFD_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ @@ -20674,7 +19041,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ /* ========================================================== P1 =========================================================== */ #define R_CANFD_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ - #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x3fffUL) /*!< GAFLFDP (Bitfield-Mask: 0x3fff) */ + #define R_CANFD_CFDGAFL_P1_GAFLFDP_Msk (0x1ffUL) /*!< GAFLFDP (Bitfield-Mask: 0x1ff) */ /* =========================================================================================================================== */ /* ================ CFDTHL ================ */ @@ -20685,8 +19052,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ #define R_CANFD_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ #define R_CANFD_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ - #define R_CANFD_CFDTHL_ACC0_TGW_Pos (15UL) /*!< TGW (Bit 15) */ - #define R_CANFD_CFDTHL_ACC0_TGW_Msk (0x8000UL) /*!< TGW (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ #define R_CANFD_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ /* ========================================================= ACC1 ========================================================== */ @@ -20695,37 +19060,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ #define R_CANFD_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ -/* =========================================================================================================================== */ -/* ================ CFDRM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFD_CFDRM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ - #define R_CANFD_CFDRM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFD_CFDRM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ - #define R_CANFD_CFDRM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ - #define R_CANFD_CFDRM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFD_CFDRM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ - #define R_CANFD_CFDRM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ - #define R_CANFD_CFDRM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ - #define R_CANFD_CFDRM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFD_CFDRM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ - #define R_CANFD_CFDRM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ - #define R_CANFD_CFDRM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ - #define R_CANFD_CFDRM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDRM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ - #define R_CANFD_CFDRM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ - #define R_CANFD_CFDRM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ - #define R_CANFD_CFDRM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFD_CFDRM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ - #define R_CANFD_CFDRM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ - /* =========================================================================================================================== */ /* ================ CFDRF ================ */ /* =========================================================================================================================== */ @@ -20819,353 +19153,39 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ #define R_CANFD_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ -/* =========================================================================================================================== */ -/* ================ CFDC ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= NCFG ========================================================== */ - #define R_CANFDL_CFDC_NCFG_NBRP_Pos (0UL) /*!< NBRP (Bit 0) */ - #define R_CANFDL_CFDC_NCFG_NBRP_Msk (0x3ffUL) /*!< NBRP (Bitfield-Mask: 0x3ff) */ - #define R_CANFDL_CFDC_NCFG_NSJW_Pos (10UL) /*!< NSJW (Bit 10) */ - #define R_CANFDL_CFDC_NCFG_NSJW_Msk (0x1fc00UL) /*!< NSJW (Bitfield-Mask: 0x7f) */ - #define R_CANFDL_CFDC_NCFG_NTSEG1_Pos (17UL) /*!< NTSEG1 (Bit 17) */ - #define R_CANFDL_CFDC_NCFG_NTSEG1_Msk (0x1fe0000UL) /*!< NTSEG1 (Bitfield-Mask: 0xff) */ - #define R_CANFDL_CFDC_NCFG_NTSEG2_Pos (25UL) /*!< NTSEG2 (Bit 25) */ - #define R_CANFDL_CFDC_NCFG_NTSEG2_Msk (0xfe000000UL) /*!< NTSEG2 (Bitfield-Mask: 0x7f) */ -/* ========================================================== CTR ========================================================== */ - #define R_CANFDL_CFDC_CTR_CHMDC_Pos (0UL) /*!< CHMDC (Bit 0) */ - #define R_CANFDL_CFDC_CTR_CHMDC_Msk (0x3UL) /*!< CHMDC (Bitfield-Mask: 0x03) */ - #define R_CANFDL_CFDC_CTR_CSLPR_Pos (2UL) /*!< CSLPR (Bit 2) */ - #define R_CANFDL_CFDC_CTR_CSLPR_Msk (0x4UL) /*!< CSLPR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_RTBO_Pos (3UL) /*!< RTBO (Bit 3) */ - #define R_CANFDL_CFDC_CTR_RTBO_Msk (0x8UL) /*!< RTBO (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_BEIE_Pos (8UL) /*!< BEIE (Bit 8) */ - #define R_CANFDL_CFDC_CTR_BEIE_Msk (0x100UL) /*!< BEIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_EWIE_Pos (9UL) /*!< EWIE (Bit 9) */ - #define R_CANFDL_CFDC_CTR_EWIE_Msk (0x200UL) /*!< EWIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_EPIE_Pos (10UL) /*!< EPIE (Bit 10) */ - #define R_CANFDL_CFDC_CTR_EPIE_Msk (0x400UL) /*!< EPIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_BOEIE_Pos (11UL) /*!< BOEIE (Bit 11) */ - #define R_CANFDL_CFDC_CTR_BOEIE_Msk (0x800UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_BORIE_Pos (12UL) /*!< BORIE (Bit 12) */ - #define R_CANFDL_CFDC_CTR_BORIE_Msk (0x1000UL) /*!< BORIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_OLIE_Pos (13UL) /*!< OLIE (Bit 13) */ - #define R_CANFDL_CFDC_CTR_OLIE_Msk (0x2000UL) /*!< OLIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_BLIE_Pos (14UL) /*!< BLIE (Bit 14) */ - #define R_CANFDL_CFDC_CTR_BLIE_Msk (0x4000UL) /*!< BLIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_ALIE_Pos (15UL) /*!< ALIE (Bit 15) */ - #define R_CANFDL_CFDC_CTR_ALIE_Msk (0x8000UL) /*!< ALIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_TAIE_Pos (16UL) /*!< TAIE (Bit 16) */ - #define R_CANFDL_CFDC_CTR_TAIE_Msk (0x10000UL) /*!< TAIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_EOCOIE_Pos (17UL) /*!< EOCOIE (Bit 17) */ - #define R_CANFDL_CFDC_CTR_EOCOIE_Msk (0x20000UL) /*!< EOCOIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_SOCOIE_Pos (18UL) /*!< SOCOIE (Bit 18) */ - #define R_CANFDL_CFDC_CTR_SOCOIE_Msk (0x40000UL) /*!< SOCOIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_TDCVFIE_Pos (19UL) /*!< TDCVFIE (Bit 19) */ - #define R_CANFDL_CFDC_CTR_TDCVFIE_Msk (0x80000UL) /*!< TDCVFIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_BOM_Pos (21UL) /*!< BOM (Bit 21) */ - #define R_CANFDL_CFDC_CTR_BOM_Msk (0x600000UL) /*!< BOM (Bitfield-Mask: 0x03) */ - #define R_CANFDL_CFDC_CTR_ERRD_Pos (23UL) /*!< ERRD (Bit 23) */ - #define R_CANFDL_CFDC_CTR_ERRD_Msk (0x800000UL) /*!< ERRD (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_CTME_Pos (24UL) /*!< CTME (Bit 24) */ - #define R_CANFDL_CFDC_CTR_CTME_Msk (0x1000000UL) /*!< CTME (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_CTMS_Pos (25UL) /*!< CTMS (Bit 25) */ - #define R_CANFDL_CFDC_CTR_CTMS_Msk (0x6000000UL) /*!< CTMS (Bitfield-Mask: 0x03) */ - #define R_CANFDL_CFDC_CTR_CRCT_Pos (30UL) /*!< CRCT (Bit 30) */ - #define R_CANFDL_CFDC_CTR_CRCT_Msk (0x40000000UL) /*!< CRCT (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_CTR_ROM_Pos (31UL) /*!< ROM (Bit 31) */ - #define R_CANFDL_CFDC_CTR_ROM_Msk (0x80000000UL) /*!< ROM (Bitfield-Mask: 0x01) */ -/* ========================================================== STS ========================================================== */ - #define R_CANFDL_CFDC_STS_CRSTSTS_Pos (0UL) /*!< CRSTSTS (Bit 0) */ - #define R_CANFDL_CFDC_STS_CRSTSTS_Msk (0x1UL) /*!< CRSTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_STS_CHLTSTS_Pos (1UL) /*!< CHLTSTS (Bit 1) */ - #define R_CANFDL_CFDC_STS_CHLTSTS_Msk (0x2UL) /*!< CHLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_STS_CSLPSTS_Pos (2UL) /*!< CSLPSTS (Bit 2) */ - #define R_CANFDL_CFDC_STS_CSLPSTS_Msk (0x4UL) /*!< CSLPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_STS_EPSTS_Pos (3UL) /*!< EPSTS (Bit 3) */ - #define R_CANFDL_CFDC_STS_EPSTS_Msk (0x8UL) /*!< EPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_STS_BOSTS_Pos (4UL) /*!< BOSTS (Bit 4) */ - #define R_CANFDL_CFDC_STS_BOSTS_Msk (0x10UL) /*!< BOSTS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_STS_TRMSTS_Pos (5UL) /*!< TRMSTS (Bit 5) */ - #define R_CANFDL_CFDC_STS_TRMSTS_Msk (0x20UL) /*!< TRMSTS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_STS_RECSTS_Pos (6UL) /*!< RECSTS (Bit 6) */ - #define R_CANFDL_CFDC_STS_RECSTS_Msk (0x40UL) /*!< RECSTS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_STS_COMSTS_Pos (7UL) /*!< COMSTS (Bit 7) */ - #define R_CANFDL_CFDC_STS_COMSTS_Msk (0x80UL) /*!< COMSTS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_STS_ESIF_Pos (8UL) /*!< ESIF (Bit 8) */ - #define R_CANFDL_CFDC_STS_ESIF_Msk (0x100UL) /*!< ESIF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_STS_REC_Pos (16UL) /*!< REC (Bit 16) */ - #define R_CANFDL_CFDC_STS_REC_Msk (0xff0000UL) /*!< REC (Bitfield-Mask: 0xff) */ - #define R_CANFDL_CFDC_STS_TEC_Pos (24UL) /*!< TEC (Bit 24) */ - #define R_CANFDL_CFDC_STS_TEC_Msk (0xff000000UL) /*!< TEC (Bitfield-Mask: 0xff) */ -/* ========================================================= ERFL ========================================================== */ - #define R_CANFDL_CFDC_ERFL_BEF_Pos (0UL) /*!< BEF (Bit 0) */ - #define R_CANFDL_CFDC_ERFL_BEF_Msk (0x1UL) /*!< BEF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_ERFL_EWF_Pos (1UL) /*!< EWF (Bit 1) */ - #define R_CANFDL_CFDC_ERFL_EWF_Msk (0x2UL) /*!< EWF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_ERFL_EPF_Pos (2UL) /*!< EPF (Bit 2) */ - #define R_CANFDL_CFDC_ERFL_EPF_Msk (0x4UL) /*!< EPF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_ERFL_BOEF_Pos (3UL) /*!< BOEF (Bit 3) */ - #define R_CANFDL_CFDC_ERFL_BOEF_Msk (0x8UL) /*!< BOEF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_ERFL_BORF_Pos (4UL) /*!< BORF (Bit 4) */ - #define R_CANFDL_CFDC_ERFL_BORF_Msk (0x10UL) /*!< BORF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_ERFL_OVLF_Pos (5UL) /*!< OVLF (Bit 5) */ - #define R_CANFDL_CFDC_ERFL_OVLF_Msk (0x20UL) /*!< OVLF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_ERFL_BLF_Pos (6UL) /*!< BLF (Bit 6) */ - #define R_CANFDL_CFDC_ERFL_BLF_Msk (0x40UL) /*!< BLF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_ERFL_ALF_Pos (7UL) /*!< ALF (Bit 7) */ - #define R_CANFDL_CFDC_ERFL_ALF_Msk (0x80UL) /*!< ALF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_ERFL_SERR_Pos (8UL) /*!< SERR (Bit 8) */ - #define R_CANFDL_CFDC_ERFL_SERR_Msk (0x100UL) /*!< SERR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_ERFL_FERR_Pos (9UL) /*!< FERR (Bit 9) */ - #define R_CANFDL_CFDC_ERFL_FERR_Msk (0x200UL) /*!< FERR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_ERFL_AERR_Pos (10UL) /*!< AERR (Bit 10) */ - #define R_CANFDL_CFDC_ERFL_AERR_Msk (0x400UL) /*!< AERR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_ERFL_CERR_Pos (11UL) /*!< CERR (Bit 11) */ - #define R_CANFDL_CFDC_ERFL_CERR_Msk (0x800UL) /*!< CERR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_ERFL_B1ERR_Pos (12UL) /*!< B1ERR (Bit 12) */ - #define R_CANFDL_CFDC_ERFL_B1ERR_Msk (0x1000UL) /*!< B1ERR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_ERFL_B0ERR_Pos (13UL) /*!< B0ERR (Bit 13) */ - #define R_CANFDL_CFDC_ERFL_B0ERR_Msk (0x2000UL) /*!< B0ERR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_ERFL_ADERR_Pos (14UL) /*!< ADERR (Bit 14) */ - #define R_CANFDL_CFDC_ERFL_ADERR_Msk (0x4000UL) /*!< ADERR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC_ERFL_CRCREG_Pos (16UL) /*!< CRCREG (Bit 16) */ - #define R_CANFDL_CFDC_ERFL_CRCREG_Msk (0x7fff0000UL) /*!< CRCREG (Bitfield-Mask: 0x7fff) */ - -/* =========================================================================================================================== */ -/* ================ CFDC2 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= DCFG ========================================================== */ - #define R_CANFDL_CFDC2_DCFG_DBRP_Pos (0UL) /*!< DBRP (Bit 0) */ - #define R_CANFDL_CFDC2_DCFG_DBRP_Msk (0xffUL) /*!< DBRP (Bitfield-Mask: 0xff) */ - #define R_CANFDL_CFDC2_DCFG_DTSEG1_Pos (8UL) /*!< DTSEG1 (Bit 8) */ - #define R_CANFDL_CFDC2_DCFG_DTSEG1_Msk (0x1f00UL) /*!< DTSEG1 (Bitfield-Mask: 0x1f) */ - #define R_CANFDL_CFDC2_DCFG_DTSEG2_Pos (16UL) /*!< DTSEG2 (Bit 16) */ - #define R_CANFDL_CFDC2_DCFG_DTSEG2_Msk (0xf0000UL) /*!< DTSEG2 (Bitfield-Mask: 0x0f) */ - #define R_CANFDL_CFDC2_DCFG_DSJW_Pos (24UL) /*!< DSJW (Bit 24) */ - #define R_CANFDL_CFDC2_DCFG_DSJW_Msk (0xf000000UL) /*!< DSJW (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDCFG ========================================================= */ - #define R_CANFDL_CFDC2_FDCFG_EOCCFG_Pos (0UL) /*!< EOCCFG (Bit 0) */ - #define R_CANFDL_CFDC2_FDCFG_EOCCFG_Msk (0x7UL) /*!< EOCCFG (Bitfield-Mask: 0x07) */ - #define R_CANFDL_CFDC2_FDCFG_TDCOC_Pos (8UL) /*!< TDCOC (Bit 8) */ - #define R_CANFDL_CFDC2_FDCFG_TDCOC_Msk (0x100UL) /*!< TDCOC (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC2_FDCFG_TDCE_Pos (9UL) /*!< TDCE (Bit 9) */ - #define R_CANFDL_CFDC2_FDCFG_TDCE_Msk (0x200UL) /*!< TDCE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC2_FDCFG_ESIC_Pos (10UL) /*!< ESIC (Bit 10) */ - #define R_CANFDL_CFDC2_FDCFG_ESIC_Msk (0x400UL) /*!< ESIC (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC2_FDCFG_TDCO_Pos (16UL) /*!< TDCO (Bit 16) */ - #define R_CANFDL_CFDC2_FDCFG_TDCO_Msk (0xff0000UL) /*!< TDCO (Bitfield-Mask: 0xff) */ - #define R_CANFDL_CFDC2_FDCFG_FDOE_Pos (28UL) /*!< FDOE (Bit 28) */ - #define R_CANFDL_CFDC2_FDCFG_FDOE_Msk (0x10000000UL) /*!< FDOE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC2_FDCFG_REFE_Pos (29UL) /*!< REFE (Bit 29) */ - #define R_CANFDL_CFDC2_FDCFG_REFE_Msk (0x20000000UL) /*!< REFE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC2_FDCFG_CLOE_Pos (30UL) /*!< CLOE (Bit 30) */ - #define R_CANFDL_CFDC2_FDCFG_CLOE_Msk (0x40000000UL) /*!< CLOE (Bitfield-Mask: 0x01) */ -/* ========================================================= FDCTR ========================================================= */ - #define R_CANFDL_CFDC2_FDCTR_EOCCLR_Pos (0UL) /*!< EOCCLR (Bit 0) */ - #define R_CANFDL_CFDC2_FDCTR_EOCCLR_Msk (0x1UL) /*!< EOCCLR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC2_FDCTR_SOCCLR_Pos (1UL) /*!< SOCCLR (Bit 1) */ - #define R_CANFDL_CFDC2_FDCTR_SOCCLR_Msk (0x2UL) /*!< SOCCLR (Bitfield-Mask: 0x01) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFDL_CFDC2_FDSTS_TDCR_Pos (0UL) /*!< TDCR (Bit 0) */ - #define R_CANFDL_CFDC2_FDSTS_TDCR_Msk (0xffUL) /*!< TDCR (Bitfield-Mask: 0xff) */ - #define R_CANFDL_CFDC2_FDSTS_EOCO_Pos (8UL) /*!< EOCO (Bit 8) */ - #define R_CANFDL_CFDC2_FDSTS_EOCO_Msk (0x100UL) /*!< EOCO (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC2_FDSTS_SOCO_Pos (9UL) /*!< SOCO (Bit 9) */ - #define R_CANFDL_CFDC2_FDSTS_SOCO_Msk (0x200UL) /*!< SOCO (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC2_FDSTS_TDCVF_Pos (15UL) /*!< TDCVF (Bit 15) */ - #define R_CANFDL_CFDC2_FDSTS_TDCVF_Msk (0x8000UL) /*!< TDCVF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDC2_FDSTS_EOC_Pos (16UL) /*!< EOC (Bit 16) */ - #define R_CANFDL_CFDC2_FDSTS_EOC_Msk (0xff0000UL) /*!< EOC (Bitfield-Mask: 0xff) */ - #define R_CANFDL_CFDC2_FDSTS_SOC_Pos (24UL) /*!< SOC (Bit 24) */ - #define R_CANFDL_CFDC2_FDSTS_SOC_Msk (0xff000000UL) /*!< SOC (Bitfield-Mask: 0xff) */ -/* ========================================================= FDCRC ========================================================= */ - #define R_CANFDL_CFDC2_FDCRC_CRCREG_Pos (0UL) /*!< CRCREG (Bit 0) */ - #define R_CANFDL_CFDC2_FDCRC_CRCREG_Msk (0x1fffffUL) /*!< CRCREG (Bitfield-Mask: 0x1fffff) */ - #define R_CANFDL_CFDC2_FDCRC_SCNT_Pos (24UL) /*!< SCNT (Bit 24) */ - #define R_CANFDL_CFDC2_FDCRC_SCNT_Msk (0xf000000UL) /*!< SCNT (Bitfield-Mask: 0x0f) */ - -/* =========================================================================================================================== */ -/* ================ CFDGAFL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFDL_CFDGAFL_ID_GAFLID_Pos (0UL) /*!< GAFLID (Bit 0) */ - #define R_CANFDL_CFDGAFL_ID_GAFLID_Msk (0x1fffffffUL) /*!< GAFLID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFDL_CFDGAFL_ID_GAFLLB_Pos (29UL) /*!< GAFLLB (Bit 29) */ - #define R_CANFDL_CFDGAFL_ID_GAFLLB_Msk (0x20000000UL) /*!< GAFLLB (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGAFL_ID_GAFLRTR_Pos (30UL) /*!< GAFLRTR (Bit 30) */ - #define R_CANFDL_CFDGAFL_ID_GAFLRTR_Msk (0x40000000UL) /*!< GAFLRTR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGAFL_ID_GAFLIDE_Pos (31UL) /*!< GAFLIDE (Bit 31) */ - #define R_CANFDL_CFDGAFL_ID_GAFLIDE_Msk (0x80000000UL) /*!< GAFLIDE (Bitfield-Mask: 0x01) */ -/* =========================================================== M =========================================================== */ - #define R_CANFDL_CFDGAFL_M_GAFLIDM_Pos (0UL) /*!< GAFLIDM (Bit 0) */ - #define R_CANFDL_CFDGAFL_M_GAFLIDM_Msk (0x1fffffffUL) /*!< GAFLIDM (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFDL_CFDGAFL_M_GAFLIFL1_Pos (29UL) /*!< GAFLIFL1 (Bit 29) */ - #define R_CANFDL_CFDGAFL_M_GAFLIFL1_Msk (0x20000000UL) /*!< GAFLIFL1 (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGAFL_M_GAFLRTRM_Pos (30UL) /*!< GAFLRTRM (Bit 30) */ - #define R_CANFDL_CFDGAFL_M_GAFLRTRM_Msk (0x40000000UL) /*!< GAFLRTRM (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGAFL_M_GAFLIDEM_Pos (31UL) /*!< GAFLIDEM (Bit 31) */ - #define R_CANFDL_CFDGAFL_M_GAFLIDEM_Msk (0x80000000UL) /*!< GAFLIDEM (Bitfield-Mask: 0x01) */ -/* ========================================================== P0 =========================================================== */ - #define R_CANFDL_CFDGAFL_P0_GAFLDLC_Pos (0UL) /*!< GAFLDLC (Bit 0) */ - #define R_CANFDL_CFDGAFL_P0_GAFLDLC_Msk (0xfUL) /*!< GAFLDLC (Bitfield-Mask: 0x0f) */ - #define R_CANFDL_CFDGAFL_P0_GAFLIFL0_Pos (7UL) /*!< GAFLIFL0 (Bit 7) */ - #define R_CANFDL_CFDGAFL_P0_GAFLIFL0_Msk (0x80UL) /*!< GAFLIFL0 (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGAFL_P0_GAFLRMDP_Pos (8UL) /*!< GAFLRMDP (Bit 8) */ - #define R_CANFDL_CFDGAFL_P0_GAFLRMDP_Msk (0x1f00UL) /*!< GAFLRMDP (Bitfield-Mask: 0x1f) */ - #define R_CANFDL_CFDGAFL_P0_GAFLRMV_Pos (15UL) /*!< GAFLRMV (Bit 15) */ - #define R_CANFDL_CFDGAFL_P0_GAFLRMV_Msk (0x8000UL) /*!< GAFLRMV (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGAFL_P0_GAFLPTR_Pos (16UL) /*!< GAFLPTR (Bit 16) */ - #define R_CANFDL_CFDGAFL_P0_GAFLPTR_Msk (0xffff0000UL) /*!< GAFLPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== P1 =========================================================== */ - #define R_CANFDL_CFDGAFL_P1_GAFLFDP_Pos (0UL) /*!< GAFLFDP (Bit 0) */ - #define R_CANFDL_CFDGAFL_P1_GAFLFDP_Msk (0x1ffUL) /*!< GAFLFDP (Bitfield-Mask: 0x1ff) */ - -/* =========================================================================================================================== */ -/* ================ CFDTHL ================ */ -/* =========================================================================================================================== */ - -/* ========================================================= ACC0 ========================================================== */ - #define R_CANFDL_CFDTHL_ACC0_BT_Pos (0UL) /*!< BT (Bit 0) */ - #define R_CANFDL_CFDTHL_ACC0_BT_Msk (0x7UL) /*!< BT (Bitfield-Mask: 0x07) */ - #define R_CANFDL_CFDTHL_ACC0_BN_Pos (3UL) /*!< BN (Bit 3) */ - #define R_CANFDL_CFDTHL_ACC0_BN_Msk (0x3f8UL) /*!< BN (Bitfield-Mask: 0x7f) */ - #define R_CANFDL_CFDTHL_ACC0_TMTS_Pos (16UL) /*!< TMTS (Bit 16) */ - #define R_CANFDL_CFDTHL_ACC0_TMTS_Msk (0xffff0000UL) /*!< TMTS (Bitfield-Mask: 0xffff) */ -/* ========================================================= ACC1 ========================================================== */ - #define R_CANFDL_CFDTHL_ACC1_TID_Pos (0UL) /*!< TID (Bit 0) */ - #define R_CANFDL_CFDTHL_ACC1_TID_Msk (0xffffUL) /*!< TID (Bitfield-Mask: 0xffff) */ - #define R_CANFDL_CFDTHL_ACC1_TIFL_Pos (16UL) /*!< TIFL (Bit 16) */ - #define R_CANFDL_CFDTHL_ACC1_TIFL_Msk (0x30000UL) /*!< TIFL (Bitfield-Mask: 0x03) */ - -/* =========================================================================================================================== */ -/* ================ CFDRF ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFDL_CFDRF_ID_RFID_Pos (0UL) /*!< RFID (Bit 0) */ - #define R_CANFDL_CFDRF_ID_RFID_Msk (0x1fffffffUL) /*!< RFID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFDL_CFDRF_ID_RFRTR_Pos (30UL) /*!< RFRTR (Bit 30) */ - #define R_CANFDL_CFDRF_ID_RFRTR_Msk (0x40000000UL) /*!< RFRTR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDRF_ID_RFIDE_Pos (31UL) /*!< RFIDE (Bit 31) */ - #define R_CANFDL_CFDRF_ID_RFIDE_Msk (0x80000000UL) /*!< RFIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFDL_CFDRF_PTR_RFTS_Pos (0UL) /*!< RFTS (Bit 0) */ - #define R_CANFDL_CFDRF_PTR_RFTS_Msk (0xffffUL) /*!< RFTS (Bitfield-Mask: 0xffff) */ - #define R_CANFDL_CFDRF_PTR_RFDLC_Pos (28UL) /*!< RFDLC (Bit 28) */ - #define R_CANFDL_CFDRF_PTR_RFDLC_Msk (0xf0000000UL) /*!< RFDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFDL_CFDRF_FDSTS_RFESI_Pos (0UL) /*!< RFESI (Bit 0) */ - #define R_CANFDL_CFDRF_FDSTS_RFESI_Msk (0x1UL) /*!< RFESI (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDRF_FDSTS_RFBRS_Pos (1UL) /*!< RFBRS (Bit 1) */ - #define R_CANFDL_CFDRF_FDSTS_RFBRS_Msk (0x2UL) /*!< RFBRS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDRF_FDSTS_RFFDF_Pos (2UL) /*!< RFFDF (Bit 2) */ - #define R_CANFDL_CFDRF_FDSTS_RFFDF_Msk (0x4UL) /*!< RFFDF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDRF_FDSTS_RFIFL_Pos (8UL) /*!< RFIFL (Bit 8) */ - #define R_CANFDL_CFDRF_FDSTS_RFIFL_Msk (0x300UL) /*!< RFIFL (Bitfield-Mask: 0x03) */ - #define R_CANFDL_CFDRF_FDSTS_RFPTR_Pos (16UL) /*!< RFPTR (Bit 16) */ - #define R_CANFDL_CFDRF_FDSTS_RFPTR_Msk (0xffff0000UL) /*!< RFPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFDL_CFDRF_DF_RFDB_Pos (0UL) /*!< RFDB (Bit 0) */ - #define R_CANFDL_CFDRF_DF_RFDB_Msk (0xffUL) /*!< RFDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDCF ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFDL_CFDCF_ID_CFID_Pos (0UL) /*!< CFID (Bit 0) */ - #define R_CANFDL_CFDCF_ID_CFID_Msk (0x1fffffffUL) /*!< CFID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFDL_CFDCF_ID_CFRTR_Pos (30UL) /*!< CFRTR (Bit 30) */ - #define R_CANFDL_CFDCF_ID_CFRTR_Msk (0x40000000UL) /*!< CFRTR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCF_ID_CFIDE_Pos (31UL) /*!< CFIDE (Bit 31) */ - #define R_CANFDL_CFDCF_ID_CFIDE_Msk (0x80000000UL) /*!< CFIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFDL_CFDCF_PTR_CFTS_Pos (0UL) /*!< CFTS (Bit 0) */ - #define R_CANFDL_CFDCF_PTR_CFTS_Msk (0xffffUL) /*!< CFTS (Bitfield-Mask: 0xffff) */ - #define R_CANFDL_CFDCF_PTR_CFDLC_Pos (28UL) /*!< CFDLC (Bit 28) */ - #define R_CANFDL_CFDCF_PTR_CFDLC_Msk (0xf0000000UL) /*!< CFDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDSTS ========================================================= */ - #define R_CANFDL_CFDCF_FDSTS_CFESI_Pos (0UL) /*!< CFESI (Bit 0) */ - #define R_CANFDL_CFDCF_FDSTS_CFESI_Msk (0x1UL) /*!< CFESI (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCF_FDSTS_CFBRS_Pos (1UL) /*!< CFBRS (Bit 1) */ - #define R_CANFDL_CFDCF_FDSTS_CFBRS_Msk (0x2UL) /*!< CFBRS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCF_FDSTS_CFFDF_Pos (2UL) /*!< CFFDF (Bit 2) */ - #define R_CANFDL_CFDCF_FDSTS_CFFDF_Msk (0x4UL) /*!< CFFDF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCF_FDSTS_CFIFL_Pos (8UL) /*!< CFIFL (Bit 8) */ - #define R_CANFDL_CFDCF_FDSTS_CFIFL_Msk (0x300UL) /*!< CFIFL (Bitfield-Mask: 0x03) */ - #define R_CANFDL_CFDCF_FDSTS_CFPTR_Pos (16UL) /*!< CFPTR (Bit 16) */ - #define R_CANFDL_CFDCF_FDSTS_CFPTR_Msk (0xffff0000UL) /*!< CFPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFDL_CFDCF_DF_CFDB_Pos (0UL) /*!< CFDB (Bit 0) */ - #define R_CANFDL_CFDCF_DF_CFDB_Msk (0xffUL) /*!< CFDB (Bitfield-Mask: 0xff) */ - -/* =========================================================================================================================== */ -/* ================ CFDTM ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== ID =========================================================== */ - #define R_CANFDL_CFDTM_ID_TMID_Pos (0UL) /*!< TMID (Bit 0) */ - #define R_CANFDL_CFDTM_ID_TMID_Msk (0x1fffffffUL) /*!< TMID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFDL_CFDTM_ID_TMRTR_Pos (30UL) /*!< TMRTR (Bit 30) */ - #define R_CANFDL_CFDTM_ID_TMRTR_Msk (0x40000000UL) /*!< TMRTR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTM_ID_TMIDE_Pos (31UL) /*!< TMIDE (Bit 31) */ - #define R_CANFDL_CFDTM_ID_TMIDE_Msk (0x80000000UL) /*!< TMIDE (Bitfield-Mask: 0x01) */ -/* ========================================================== PTR ========================================================== */ - #define R_CANFDL_CFDTM_PTR_TMTS_Pos (0UL) /*!< TMTS (Bit 0) */ - #define R_CANFDL_CFDTM_PTR_TMTS_Msk (0xffffUL) /*!< TMTS (Bitfield-Mask: 0xffff) */ - #define R_CANFDL_CFDTM_PTR_TMDLC_Pos (28UL) /*!< TMDLC (Bit 28) */ - #define R_CANFDL_CFDTM_PTR_TMDLC_Msk (0xf0000000UL) /*!< TMDLC (Bitfield-Mask: 0x0f) */ -/* ========================================================= FDCTR ========================================================= */ - #define R_CANFDL_CFDTM_FDCTR_TMESI_Pos (0UL) /*!< TMESI (Bit 0) */ - #define R_CANFDL_CFDTM_FDCTR_TMESI_Msk (0x1UL) /*!< TMESI (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTM_FDCTR_TMBRS_Pos (1UL) /*!< TMBRS (Bit 1) */ - #define R_CANFDL_CFDTM_FDCTR_TMBRS_Msk (0x2UL) /*!< TMBRS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTM_FDCTR_TMFDF_Pos (2UL) /*!< TMFDF (Bit 2) */ - #define R_CANFDL_CFDTM_FDCTR_TMFDF_Msk (0x4UL) /*!< TMFDF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTM_FDCTR_TMIFL_Pos (8UL) /*!< TMIFL (Bit 8) */ - #define R_CANFDL_CFDTM_FDCTR_TMIFL_Msk (0x300UL) /*!< TMIFL (Bitfield-Mask: 0x03) */ - #define R_CANFDL_CFDTM_FDCTR_TMPTR_Pos (16UL) /*!< TMPTR (Bit 16) */ - #define R_CANFDL_CFDTM_FDCTR_TMPTR_Msk (0xffff0000UL) /*!< TMPTR (Bitfield-Mask: 0xffff) */ -/* ========================================================== DF =========================================================== */ - #define R_CANFDL_CFDTM_DF_TMDB_Pos (0UL) /*!< TMDB (Bit 0) */ - #define R_CANFDL_CFDTM_DF_TMDB_Msk (0xffUL) /*!< TMDB (Bitfield-Mask: 0xff) */ - /* =========================================================================================================================== */ /* ================ RM ================ */ /* =========================================================================================================================== */ /* ========================================================== ID =========================================================== */ - #define R_CANFDL_CFDRMC_RM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ - #define R_CANFDL_CFDRMC_RM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ - #define R_CANFDL_CFDRMC_RM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ - #define R_CANFDL_CFDRMC_RM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDRMC_RM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ - #define R_CANFDL_CFDRMC_RM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_ID_RMID_Pos (0UL) /*!< RMID (Bit 0) */ + #define R_CANFD_CFDRM_RM_ID_RMID_Msk (0x1fffffffUL) /*!< RMID (Bitfield-Mask: 0x1fffffff) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Pos (30UL) /*!< RMRTR (Bit 30) */ + #define R_CANFD_CFDRM_RM_ID_RMRTR_Msk (0x40000000UL) /*!< RMRTR (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Pos (31UL) /*!< RMIDE (Bit 31) */ + #define R_CANFD_CFDRM_RM_ID_RMIDE_Msk (0x80000000UL) /*!< RMIDE (Bitfield-Mask: 0x01) */ /* ========================================================== PTR ========================================================== */ - #define R_CANFDL_CFDRMC_RM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ - #define R_CANFDL_CFDRMC_RM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ - #define R_CANFDL_CFDRMC_RM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ - #define R_CANFDL_CFDRMC_RM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Pos (0UL) /*!< RMTS (Bit 0) */ + #define R_CANFD_CFDRM_RM_PTR_RMTS_Msk (0xffffUL) /*!< RMTS (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Pos (28UL) /*!< RMDLC (Bit 28) */ + #define R_CANFD_CFDRM_RM_PTR_RMDLC_Msk (0xf0000000UL) /*!< RMDLC (Bitfield-Mask: 0x0f) */ /* ========================================================= FDSTS ========================================================= */ - #define R_CANFDL_CFDRMC_RM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ - #define R_CANFDL_CFDRMC_RM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDRMC_RM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ - #define R_CANFDL_CFDRMC_RM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDRMC_RM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ - #define R_CANFDL_CFDRMC_RM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDRMC_RM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ - #define R_CANFDL_CFDRMC_RM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ - #define R_CANFDL_CFDRMC_RM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ - #define R_CANFDL_CFDRMC_RM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Pos (0UL) /*!< RMESI (Bit 0) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMESI_Msk (0x1UL) /*!< RMESI (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Pos (1UL) /*!< RMBRS (Bit 1) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMBRS_Msk (0x2UL) /*!< RMBRS (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Pos (2UL) /*!< RMFDF (Bit 2) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMFDF_Msk (0x4UL) /*!< RMFDF (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Pos (8UL) /*!< RMIFL (Bit 8) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMIFL_Msk (0x300UL) /*!< RMIFL (Bitfield-Mask: 0x03) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Pos (16UL) /*!< RMPTR (Bit 16) */ + #define R_CANFD_CFDRM_RM_FDSTS_RMPTR_Msk (0xffff0000UL) /*!< RMPTR (Bitfield-Mask: 0xffff) */ /* ========================================================== DF =========================================================== */ - #define R_CANFDL_CFDRMC_RM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ - #define R_CANFDL_CFDRMC_RM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Pos (0UL) /*!< RMDB (Bit 0) */ + #define R_CANFD_CFDRM_RM_DF_RMDB_Msk (0xffUL) /*!< RMDB (Bitfield-Mask: 0xff) */ /* =========================================================================================================================== */ -/* ================ CFDRMC ================ */ +/* ================ CFDRM ================ */ /* =========================================================================================================================== */ /* =========================================================================================================================== */ @@ -21351,12 +19371,103 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ================ PORT ================ */ /* =========================================================================================================================== */ +/* =========================================================================================================================== */ +/* ================ VLSEL ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== VL1SEL ========================================================= */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Pos (0UL) /*!< SELVL (Bit 0) */ + #define R_PFS_VLSEL_VL1SEL_SELVL_Msk (0x1UL) /*!< SELVL (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ PMSAR ================ */ /* =========================================================================================================================== */ /* ========================================================= PMSAR ========================================================= */ +/* =========================================================================================================================== */ +/* ================ CSa ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== MOD ========================================================== */ + #define R_BUS_B_CSa_MOD_PRMOD_Pos (15UL) /*!< PRMOD (Bit 15) */ + #define R_BUS_B_CSa_MOD_PRMOD_Msk (0x8000UL) /*!< PRMOD (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_PWENB_Pos (9UL) /*!< PWENB (Bit 9) */ + #define R_BUS_B_CSa_MOD_PWENB_Msk (0x200UL) /*!< PWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_PRENB_Pos (8UL) /*!< PRENB (Bit 8) */ + #define R_BUS_B_CSa_MOD_PRENB_Msk (0x100UL) /*!< PRENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_EWENB_Pos (3UL) /*!< EWENB (Bit 3) */ + #define R_BUS_B_CSa_MOD_EWENB_Msk (0x8UL) /*!< EWENB (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSa_MOD_WRMOD_Pos (0UL) /*!< WRMOD (Bit 0) */ + #define R_BUS_B_CSa_MOD_WRMOD_Msk (0x1UL) /*!< WRMOD (Bitfield-Mask: 0x01) */ +/* ========================================================= WCR1 ========================================================== */ + #define R_BUS_B_CSa_WCR1_CSRWAIT_Pos (24UL) /*!< CSRWAIT (Bit 24) */ + #define R_BUS_B_CSa_WCR1_CSRWAIT_Msk (0x1f000000UL) /*!< CSRWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_B_CSa_WCR1_CSWWAIT_Pos (16UL) /*!< CSWWAIT (Bit 16) */ + #define R_BUS_B_CSa_WCR1_CSWWAIT_Msk (0x1f0000UL) /*!< CSWWAIT (Bitfield-Mask: 0x1f) */ + #define R_BUS_B_CSa_WCR1_CSPRWAIT_Pos (8UL) /*!< CSPRWAIT (Bit 8) */ + #define R_BUS_B_CSa_WCR1_CSPRWAIT_Msk (0x700UL) /*!< CSPRWAIT (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR1_CSPWWAIT_Pos (0UL) /*!< CSPWWAIT (Bit 0) */ + #define R_BUS_B_CSa_WCR1_CSPWWAIT_Msk (0x7UL) /*!< CSPWWAIT (Bitfield-Mask: 0x07) */ +/* ========================================================= WCR2 ========================================================== */ + #define R_BUS_B_CSa_WCR2_CSON_Pos (28UL) /*!< CSON (Bit 28) */ + #define R_BUS_B_CSa_WCR2_CSON_Msk (0x70000000UL) /*!< CSON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_WDON_Pos (24UL) /*!< WDON (Bit 24) */ + #define R_BUS_B_CSa_WCR2_WDON_Msk (0x7000000UL) /*!< WDON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_WRON_Pos (20UL) /*!< WRON (Bit 20) */ + #define R_BUS_B_CSa_WCR2_WRON_Msk (0x700000UL) /*!< WRON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_RDON_Pos (16UL) /*!< RDON (Bit 16) */ + #define R_BUS_B_CSa_WCR2_RDON_Msk (0x70000UL) /*!< RDON (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_AWAIT_Pos (12UL) /*!< AWAIT (Bit 12) */ + #define R_BUS_B_CSa_WCR2_AWAIT_Msk (0x3000UL) /*!< AWAIT (Bitfield-Mask: 0x03) */ + #define R_BUS_B_CSa_WCR2_WDOFF_Pos (8UL) /*!< WDOFF (Bit 8) */ + #define R_BUS_B_CSa_WCR2_WDOFF_Msk (0x700UL) /*!< WDOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_CSWOFF_Pos (4UL) /*!< CSWOFF (Bit 4) */ + #define R_BUS_B_CSa_WCR2_CSWOFF_Msk (0x70UL) /*!< CSWOFF (Bitfield-Mask: 0x07) */ + #define R_BUS_B_CSa_WCR2_CSROFF_Pos (0UL) /*!< CSROFF (Bit 0) */ + #define R_BUS_B_CSa_WCR2_CSROFF_Msk (0x7UL) /*!< CSROFF (Bitfield-Mask: 0x07) */ + +/* =========================================================================================================================== */ +/* ================ CSb ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== CR =========================================================== */ + #define R_BUS_B_CSb_CR_MPXEN_Pos (12UL) /*!< MPXEN (Bit 12) */ + #define R_BUS_B_CSb_CR_MPXEN_Msk (0x1000UL) /*!< MPXEN (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSb_CR_EMODE_Pos (8UL) /*!< EMODE (Bit 8) */ + #define R_BUS_B_CSb_CR_EMODE_Msk (0x100UL) /*!< EMODE (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSb_CR_BSIZE_Pos (4UL) /*!< BSIZE (Bit 4) */ + #define R_BUS_B_CSb_CR_BSIZE_Msk (0x30UL) /*!< BSIZE (Bitfield-Mask: 0x03) */ + #define R_BUS_B_CSb_CR_EXENB_Pos (0UL) /*!< EXENB (Bit 0) */ + #define R_BUS_B_CSb_CR_EXENB_Msk (0x1UL) /*!< EXENB (Bitfield-Mask: 0x01) */ +/* ========================================================== REC ========================================================== */ + #define R_BUS_B_CSb_REC_WRCV_Pos (8UL) /*!< WRCV (Bit 8) */ + #define R_BUS_B_CSb_REC_WRCV_Msk (0xf00UL) /*!< WRCV (Bitfield-Mask: 0x0f) */ + #define R_BUS_B_CSb_REC_RRCV_Pos (0UL) /*!< RRCV (Bit 0) */ + #define R_BUS_B_CSb_REC_RRCV_Msk (0xfUL) /*!< RRCV (Bitfield-Mask: 0x0f) */ + +/* =========================================================================================================================== */ +/* ================ BUSERR ================ */ +/* =========================================================================================================================== */ + +/* ========================================================== ADD ========================================================== */ + #define R_BUS_B_BUSERR_ADD_BERAD_Pos (0UL) /*!< BERAD (Bit 0) */ + #define R_BUS_B_BUSERR_ADD_BERAD_Msk (0xffffffffUL) /*!< BERAD (Bitfield-Mask: 0xffffffff) */ +/* ========================================================= ERRRW ========================================================= */ + #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Pos (0UL) /*!< RWSTAT (Bit 0) */ + #define R_BUS_B_BUSERR_ERRRW_RWSTAT_Msk (0x1UL) /*!< RWSTAT (Bitfield-Mask: 0x01) */ + +/* =========================================================================================================================== */ +/* ================ BUSTZFERR ================ */ +/* =========================================================================================================================== */ + +/* ======================================================== TZFADD ========================================================= */ + #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Pos (0UL) /*!< BTZFERAD (Bit 0) */ + #define R_BUS_B_BUSTZFERR_TZFADD_BTZFERAD_Msk (0xffffffffUL) /*!< BTZFERAD (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= TZFERRRW ======================================================== */ + #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Pos (0UL) /*!< TRWSTAT (Bit 0) */ + #define R_BUS_B_BUSTZFERR_TZFERRRW_TRWSTAT_Msk (0x1UL) /*!< TRWSTAT (Bitfield-Mask: 0x01) */ + /** @} */ /* End of group PosMask_clusters */ /* =========================================================================================================================== */ @@ -22189,409 +20300,7 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CAC_CACNTBR_CACNTBR_Msk (0xffffUL) /*!< CACNTBR (Bitfield-Mask: 0xffff) */ /* =========================================================================================================================== */ -/* ================ R_CAN0 ================ */ -/* =========================================================================================================================== */ - -/* ========================================================== MKR ========================================================== */ - #define R_CAN0_MKR_SID_Pos (18UL) /*!< SID (Bit 18) */ - #define R_CAN0_MKR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ - #define R_CAN0_MKR_EID_Pos (0UL) /*!< EID (Bit 0) */ - #define R_CAN0_MKR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ -/* ========================================================= FIDCR ========================================================= */ - #define R_CAN0_FIDCR_IDE_Pos (31UL) /*!< IDE (Bit 31) */ - #define R_CAN0_FIDCR_IDE_Msk (0x80000000UL) /*!< IDE (Bitfield-Mask: 0x01) */ - #define R_CAN0_FIDCR_RTR_Pos (30UL) /*!< RTR (Bit 30) */ - #define R_CAN0_FIDCR_RTR_Msk (0x40000000UL) /*!< RTR (Bitfield-Mask: 0x01) */ - #define R_CAN0_FIDCR_SID_Pos (18UL) /*!< SID (Bit 18) */ - #define R_CAN0_FIDCR_SID_Msk (0x1ffc0000UL) /*!< SID (Bitfield-Mask: 0x7ff) */ - #define R_CAN0_FIDCR_EID_Pos (0UL) /*!< EID (Bit 0) */ - #define R_CAN0_FIDCR_EID_Msk (0x3ffffUL) /*!< EID (Bitfield-Mask: 0x3ffff) */ -/* ======================================================== MKIVLR ========================================================= */ - #define R_CAN0_MKIVLR_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ - #define R_CAN0_MKIVLR_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ - #define R_CAN0_MKIVLR_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ - #define R_CAN0_MKIVLR_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ - #define R_CAN0_MKIVLR_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ - #define R_CAN0_MKIVLR_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ - #define R_CAN0_MKIVLR_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ - #define R_CAN0_MKIVLR_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ - #define R_CAN0_MKIVLR_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ - #define R_CAN0_MKIVLR_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ - #define R_CAN0_MKIVLR_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ - #define R_CAN0_MKIVLR_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ - #define R_CAN0_MKIVLR_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ - #define R_CAN0_MKIVLR_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ - #define R_CAN0_MKIVLR_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ - #define R_CAN0_MKIVLR_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ - #define R_CAN0_MKIVLR_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ - #define R_CAN0_MKIVLR_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ - #define R_CAN0_MKIVLR_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ - #define R_CAN0_MKIVLR_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ - #define R_CAN0_MKIVLR_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ - #define R_CAN0_MKIVLR_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ - #define R_CAN0_MKIVLR_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ - #define R_CAN0_MKIVLR_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ - #define R_CAN0_MKIVLR_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ - #define R_CAN0_MKIVLR_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ - #define R_CAN0_MKIVLR_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ - #define R_CAN0_MKIVLR_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ - #define R_CAN0_MKIVLR_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ - #define R_CAN0_MKIVLR_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ - #define R_CAN0_MKIVLR_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ - #define R_CAN0_MKIVLR_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MKIVLR_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ - #define R_CAN0_MKIVLR_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ -/* ========================================================= MIER ========================================================== */ - #define R_CAN0_MIER_MB31_Pos (31UL) /*!< MB31 (Bit 31) */ - #define R_CAN0_MIER_MB31_Msk (0x80000000UL) /*!< MB31 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB30_Pos (30UL) /*!< MB30 (Bit 30) */ - #define R_CAN0_MIER_MB30_Msk (0x40000000UL) /*!< MB30 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ - #define R_CAN0_MIER_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ - #define R_CAN0_MIER_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB27_Pos (27UL) /*!< MB27 (Bit 27) */ - #define R_CAN0_MIER_MB27_Msk (0x8000000UL) /*!< MB27 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB26_Pos (26UL) /*!< MB26 (Bit 26) */ - #define R_CAN0_MIER_MB26_Msk (0x4000000UL) /*!< MB26 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ - #define R_CAN0_MIER_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ - #define R_CAN0_MIER_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ - #define R_CAN0_MIER_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ - #define R_CAN0_MIER_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ - #define R_CAN0_MIER_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ - #define R_CAN0_MIER_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ - #define R_CAN0_MIER_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ - #define R_CAN0_MIER_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ - #define R_CAN0_MIER_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ - #define R_CAN0_MIER_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ - #define R_CAN0_MIER_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ - #define R_CAN0_MIER_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ - #define R_CAN0_MIER_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ - #define R_CAN0_MIER_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ - #define R_CAN0_MIER_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ - #define R_CAN0_MIER_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ - #define R_CAN0_MIER_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ - #define R_CAN0_MIER_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ - #define R_CAN0_MIER_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ - #define R_CAN0_MIER_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ - #define R_CAN0_MIER_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ - #define R_CAN0_MIER_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ - #define R_CAN0_MIER_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ - #define R_CAN0_MIER_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ - #define R_CAN0_MIER_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ - #define R_CAN0_MIER_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ -/* ======================================================= MIER_FIFO ======================================================= */ - #define R_CAN0_MIER_FIFO_MB29_Pos (29UL) /*!< MB29 (Bit 29) */ - #define R_CAN0_MIER_FIFO_MB29_Msk (0x20000000UL) /*!< MB29 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB28_Pos (28UL) /*!< MB28 (Bit 28) */ - #define R_CAN0_MIER_FIFO_MB28_Msk (0x10000000UL) /*!< MB28 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB25_Pos (25UL) /*!< MB25 (Bit 25) */ - #define R_CAN0_MIER_FIFO_MB25_Msk (0x2000000UL) /*!< MB25 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB24_Pos (24UL) /*!< MB24 (Bit 24) */ - #define R_CAN0_MIER_FIFO_MB24_Msk (0x1000000UL) /*!< MB24 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB23_Pos (23UL) /*!< MB23 (Bit 23) */ - #define R_CAN0_MIER_FIFO_MB23_Msk (0x800000UL) /*!< MB23 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB22_Pos (22UL) /*!< MB22 (Bit 22) */ - #define R_CAN0_MIER_FIFO_MB22_Msk (0x400000UL) /*!< MB22 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB21_Pos (21UL) /*!< MB21 (Bit 21) */ - #define R_CAN0_MIER_FIFO_MB21_Msk (0x200000UL) /*!< MB21 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB20_Pos (20UL) /*!< MB20 (Bit 20) */ - #define R_CAN0_MIER_FIFO_MB20_Msk (0x100000UL) /*!< MB20 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB19_Pos (19UL) /*!< MB19 (Bit 19) */ - #define R_CAN0_MIER_FIFO_MB19_Msk (0x80000UL) /*!< MB19 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB18_Pos (18UL) /*!< MB18 (Bit 18) */ - #define R_CAN0_MIER_FIFO_MB18_Msk (0x40000UL) /*!< MB18 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB17_Pos (17UL) /*!< MB17 (Bit 17) */ - #define R_CAN0_MIER_FIFO_MB17_Msk (0x20000UL) /*!< MB17 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB16_Pos (16UL) /*!< MB16 (Bit 16) */ - #define R_CAN0_MIER_FIFO_MB16_Msk (0x10000UL) /*!< MB16 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB15_Pos (15UL) /*!< MB15 (Bit 15) */ - #define R_CAN0_MIER_FIFO_MB15_Msk (0x8000UL) /*!< MB15 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB14_Pos (14UL) /*!< MB14 (Bit 14) */ - #define R_CAN0_MIER_FIFO_MB14_Msk (0x4000UL) /*!< MB14 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB13_Pos (13UL) /*!< MB13 (Bit 13) */ - #define R_CAN0_MIER_FIFO_MB13_Msk (0x2000UL) /*!< MB13 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB12_Pos (12UL) /*!< MB12 (Bit 12) */ - #define R_CAN0_MIER_FIFO_MB12_Msk (0x1000UL) /*!< MB12 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB11_Pos (11UL) /*!< MB11 (Bit 11) */ - #define R_CAN0_MIER_FIFO_MB11_Msk (0x800UL) /*!< MB11 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB10_Pos (10UL) /*!< MB10 (Bit 10) */ - #define R_CAN0_MIER_FIFO_MB10_Msk (0x400UL) /*!< MB10 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB9_Pos (9UL) /*!< MB9 (Bit 9) */ - #define R_CAN0_MIER_FIFO_MB9_Msk (0x200UL) /*!< MB9 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB8_Pos (8UL) /*!< MB8 (Bit 8) */ - #define R_CAN0_MIER_FIFO_MB8_Msk (0x100UL) /*!< MB8 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB7_Pos (7UL) /*!< MB7 (Bit 7) */ - #define R_CAN0_MIER_FIFO_MB7_Msk (0x80UL) /*!< MB7 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB6_Pos (6UL) /*!< MB6 (Bit 6) */ - #define R_CAN0_MIER_FIFO_MB6_Msk (0x40UL) /*!< MB6 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB5_Pos (5UL) /*!< MB5 (Bit 5) */ - #define R_CAN0_MIER_FIFO_MB5_Msk (0x20UL) /*!< MB5 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB4_Pos (4UL) /*!< MB4 (Bit 4) */ - #define R_CAN0_MIER_FIFO_MB4_Msk (0x10UL) /*!< MB4 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB3_Pos (3UL) /*!< MB3 (Bit 3) */ - #define R_CAN0_MIER_FIFO_MB3_Msk (0x8UL) /*!< MB3 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB2_Pos (2UL) /*!< MB2 (Bit 2) */ - #define R_CAN0_MIER_FIFO_MB2_Msk (0x4UL) /*!< MB2 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB1_Pos (1UL) /*!< MB1 (Bit 1) */ - #define R_CAN0_MIER_FIFO_MB1_Msk (0x2UL) /*!< MB1 (Bitfield-Mask: 0x01) */ - #define R_CAN0_MIER_FIFO_MB0_Pos (0UL) /*!< MB0 (Bit 0) */ - #define R_CAN0_MIER_FIFO_MB0_Msk (0x1UL) /*!< MB0 (Bitfield-Mask: 0x01) */ -/* ======================================================== MCTL_TX ======================================================== */ - #define R_CAN0_MCTL_TX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ - #define R_CAN0_MCTL_TX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_TX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ - #define R_CAN0_MCTL_TX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_TX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ - #define R_CAN0_MCTL_TX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_TX_TRMABT_Pos (2UL) /*!< TRMABT (Bit 2) */ - #define R_CAN0_MCTL_TX_TRMABT_Msk (0x4UL) /*!< TRMABT (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_TX_TRMACTIVE_Pos (1UL) /*!< TRMACTIVE (Bit 1) */ - #define R_CAN0_MCTL_TX_TRMACTIVE_Msk (0x2UL) /*!< TRMACTIVE (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_TX_SENTDATA_Pos (0UL) /*!< SENTDATA (Bit 0) */ - #define R_CAN0_MCTL_TX_SENTDATA_Msk (0x1UL) /*!< SENTDATA (Bitfield-Mask: 0x01) */ -/* ======================================================== MCTL_RX ======================================================== */ - #define R_CAN0_MCTL_RX_TRMREQ_Pos (7UL) /*!< TRMREQ (Bit 7) */ - #define R_CAN0_MCTL_RX_TRMREQ_Msk (0x80UL) /*!< TRMREQ (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_RX_RECREQ_Pos (6UL) /*!< RECREQ (Bit 6) */ - #define R_CAN0_MCTL_RX_RECREQ_Msk (0x40UL) /*!< RECREQ (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_RX_ONESHOT_Pos (4UL) /*!< ONESHOT (Bit 4) */ - #define R_CAN0_MCTL_RX_ONESHOT_Msk (0x10UL) /*!< ONESHOT (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_RX_MSGLOST_Pos (2UL) /*!< MSGLOST (Bit 2) */ - #define R_CAN0_MCTL_RX_MSGLOST_Msk (0x4UL) /*!< MSGLOST (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_RX_INVALDATA_Pos (1UL) /*!< INVALDATA (Bit 1) */ - #define R_CAN0_MCTL_RX_INVALDATA_Msk (0x2UL) /*!< INVALDATA (Bitfield-Mask: 0x01) */ - #define R_CAN0_MCTL_RX_NEWDATA_Pos (0UL) /*!< NEWDATA (Bit 0) */ - #define R_CAN0_MCTL_RX_NEWDATA_Msk (0x1UL) /*!< NEWDATA (Bitfield-Mask: 0x01) */ -/* ========================================================= CTLR ========================================================== */ - #define R_CAN0_CTLR_RBOC_Pos (13UL) /*!< RBOC (Bit 13) */ - #define R_CAN0_CTLR_RBOC_Msk (0x2000UL) /*!< RBOC (Bitfield-Mask: 0x01) */ - #define R_CAN0_CTLR_BOM_Pos (11UL) /*!< BOM (Bit 11) */ - #define R_CAN0_CTLR_BOM_Msk (0x1800UL) /*!< BOM (Bitfield-Mask: 0x03) */ - #define R_CAN0_CTLR_SLPM_Pos (10UL) /*!< SLPM (Bit 10) */ - #define R_CAN0_CTLR_SLPM_Msk (0x400UL) /*!< SLPM (Bitfield-Mask: 0x01) */ - #define R_CAN0_CTLR_CANM_Pos (8UL) /*!< CANM (Bit 8) */ - #define R_CAN0_CTLR_CANM_Msk (0x300UL) /*!< CANM (Bitfield-Mask: 0x03) */ - #define R_CAN0_CTLR_TSPS_Pos (6UL) /*!< TSPS (Bit 6) */ - #define R_CAN0_CTLR_TSPS_Msk (0xc0UL) /*!< TSPS (Bitfield-Mask: 0x03) */ - #define R_CAN0_CTLR_TSRC_Pos (5UL) /*!< TSRC (Bit 5) */ - #define R_CAN0_CTLR_TSRC_Msk (0x20UL) /*!< TSRC (Bitfield-Mask: 0x01) */ - #define R_CAN0_CTLR_TPM_Pos (4UL) /*!< TPM (Bit 4) */ - #define R_CAN0_CTLR_TPM_Msk (0x10UL) /*!< TPM (Bitfield-Mask: 0x01) */ - #define R_CAN0_CTLR_MLM_Pos (3UL) /*!< MLM (Bit 3) */ - #define R_CAN0_CTLR_MLM_Msk (0x8UL) /*!< MLM (Bitfield-Mask: 0x01) */ - #define R_CAN0_CTLR_IDFM_Pos (1UL) /*!< IDFM (Bit 1) */ - #define R_CAN0_CTLR_IDFM_Msk (0x6UL) /*!< IDFM (Bitfield-Mask: 0x03) */ - #define R_CAN0_CTLR_MBM_Pos (0UL) /*!< MBM (Bit 0) */ - #define R_CAN0_CTLR_MBM_Msk (0x1UL) /*!< MBM (Bitfield-Mask: 0x01) */ -/* ========================================================== STR ========================================================== */ - #define R_CAN0_STR_RECST_Pos (14UL) /*!< RECST (Bit 14) */ - #define R_CAN0_STR_RECST_Msk (0x4000UL) /*!< RECST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_TRMST_Pos (13UL) /*!< TRMST (Bit 13) */ - #define R_CAN0_STR_TRMST_Msk (0x2000UL) /*!< TRMST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_BOST_Pos (12UL) /*!< BOST (Bit 12) */ - #define R_CAN0_STR_BOST_Msk (0x1000UL) /*!< BOST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_EPST_Pos (11UL) /*!< EPST (Bit 11) */ - #define R_CAN0_STR_EPST_Msk (0x800UL) /*!< EPST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_SLPST_Pos (10UL) /*!< SLPST (Bit 10) */ - #define R_CAN0_STR_SLPST_Msk (0x400UL) /*!< SLPST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_HLTST_Pos (9UL) /*!< HLTST (Bit 9) */ - #define R_CAN0_STR_HLTST_Msk (0x200UL) /*!< HLTST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_RSTST_Pos (8UL) /*!< RSTST (Bit 8) */ - #define R_CAN0_STR_RSTST_Msk (0x100UL) /*!< RSTST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_EST_Pos (7UL) /*!< EST (Bit 7) */ - #define R_CAN0_STR_EST_Msk (0x80UL) /*!< EST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_TABST_Pos (6UL) /*!< TABST (Bit 6) */ - #define R_CAN0_STR_TABST_Msk (0x40UL) /*!< TABST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_FMLST_Pos (5UL) /*!< FMLST (Bit 5) */ - #define R_CAN0_STR_FMLST_Msk (0x20UL) /*!< FMLST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_NMLST_Pos (4UL) /*!< NMLST (Bit 4) */ - #define R_CAN0_STR_NMLST_Msk (0x10UL) /*!< NMLST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_TFST_Pos (3UL) /*!< TFST (Bit 3) */ - #define R_CAN0_STR_TFST_Msk (0x8UL) /*!< TFST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_RFST_Pos (2UL) /*!< RFST (Bit 2) */ - #define R_CAN0_STR_RFST_Msk (0x4UL) /*!< RFST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_SDST_Pos (1UL) /*!< SDST (Bit 1) */ - #define R_CAN0_STR_SDST_Msk (0x2UL) /*!< SDST (Bitfield-Mask: 0x01) */ - #define R_CAN0_STR_NDST_Pos (0UL) /*!< NDST (Bit 0) */ - #define R_CAN0_STR_NDST_Msk (0x1UL) /*!< NDST (Bitfield-Mask: 0x01) */ -/* ========================================================== BCR ========================================================== */ - #define R_CAN0_BCR_TSEG1_Pos (28UL) /*!< TSEG1 (Bit 28) */ - #define R_CAN0_BCR_TSEG1_Msk (0xf0000000UL) /*!< TSEG1 (Bitfield-Mask: 0x0f) */ - #define R_CAN0_BCR_BRP_Pos (16UL) /*!< BRP (Bit 16) */ - #define R_CAN0_BCR_BRP_Msk (0x3ff0000UL) /*!< BRP (Bitfield-Mask: 0x3ff) */ - #define R_CAN0_BCR_SJW_Pos (12UL) /*!< SJW (Bit 12) */ - #define R_CAN0_BCR_SJW_Msk (0x3000UL) /*!< SJW (Bitfield-Mask: 0x03) */ - #define R_CAN0_BCR_TSEG2_Pos (8UL) /*!< TSEG2 (Bit 8) */ - #define R_CAN0_BCR_TSEG2_Msk (0x700UL) /*!< TSEG2 (Bitfield-Mask: 0x07) */ - #define R_CAN0_BCR_CCLKS_Pos (0UL) /*!< CCLKS (Bit 0) */ - #define R_CAN0_BCR_CCLKS_Msk (0x1UL) /*!< CCLKS (Bitfield-Mask: 0x01) */ -/* ========================================================= RFCR ========================================================== */ - #define R_CAN0_RFCR_RFEST_Pos (7UL) /*!< RFEST (Bit 7) */ - #define R_CAN0_RFCR_RFEST_Msk (0x80UL) /*!< RFEST (Bitfield-Mask: 0x01) */ - #define R_CAN0_RFCR_RFWST_Pos (6UL) /*!< RFWST (Bit 6) */ - #define R_CAN0_RFCR_RFWST_Msk (0x40UL) /*!< RFWST (Bitfield-Mask: 0x01) */ - #define R_CAN0_RFCR_RFFST_Pos (5UL) /*!< RFFST (Bit 5) */ - #define R_CAN0_RFCR_RFFST_Msk (0x20UL) /*!< RFFST (Bitfield-Mask: 0x01) */ - #define R_CAN0_RFCR_RFMLF_Pos (4UL) /*!< RFMLF (Bit 4) */ - #define R_CAN0_RFCR_RFMLF_Msk (0x10UL) /*!< RFMLF (Bitfield-Mask: 0x01) */ - #define R_CAN0_RFCR_RFUST_Pos (1UL) /*!< RFUST (Bit 1) */ - #define R_CAN0_RFCR_RFUST_Msk (0xeUL) /*!< RFUST (Bitfield-Mask: 0x07) */ - #define R_CAN0_RFCR_RFE_Pos (0UL) /*!< RFE (Bit 0) */ - #define R_CAN0_RFCR_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ -/* ========================================================= RFPCR ========================================================= */ - #define R_CAN0_RFPCR_RFPCR_Pos (0UL) /*!< RFPCR (Bit 0) */ - #define R_CAN0_RFPCR_RFPCR_Msk (0xffUL) /*!< RFPCR (Bitfield-Mask: 0xff) */ -/* ========================================================= TFCR ========================================================== */ - #define R_CAN0_TFCR_TFEST_Pos (7UL) /*!< TFEST (Bit 7) */ - #define R_CAN0_TFCR_TFEST_Msk (0x80UL) /*!< TFEST (Bitfield-Mask: 0x01) */ - #define R_CAN0_TFCR_TFFST_Pos (6UL) /*!< TFFST (Bit 6) */ - #define R_CAN0_TFCR_TFFST_Msk (0x40UL) /*!< TFFST (Bitfield-Mask: 0x01) */ - #define R_CAN0_TFCR_TFUST_Pos (1UL) /*!< TFUST (Bit 1) */ - #define R_CAN0_TFCR_TFUST_Msk (0xeUL) /*!< TFUST (Bitfield-Mask: 0x07) */ - #define R_CAN0_TFCR_TFE_Pos (0UL) /*!< TFE (Bit 0) */ - #define R_CAN0_TFCR_TFE_Msk (0x1UL) /*!< TFE (Bitfield-Mask: 0x01) */ -/* ========================================================= TFPCR ========================================================= */ - #define R_CAN0_TFPCR_TFPCR_Pos (0UL) /*!< TFPCR (Bit 0) */ - #define R_CAN0_TFPCR_TFPCR_Msk (0xffUL) /*!< TFPCR (Bitfield-Mask: 0xff) */ -/* ========================================================= EIER ========================================================== */ - #define R_CAN0_EIER_BLIE_Pos (7UL) /*!< BLIE (Bit 7) */ - #define R_CAN0_EIER_BLIE_Msk (0x80UL) /*!< BLIE (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIER_OLIE_Pos (6UL) /*!< OLIE (Bit 6) */ - #define R_CAN0_EIER_OLIE_Msk (0x40UL) /*!< OLIE (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIER_ORIE_Pos (5UL) /*!< ORIE (Bit 5) */ - #define R_CAN0_EIER_ORIE_Msk (0x20UL) /*!< ORIE (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIER_BORIE_Pos (4UL) /*!< BORIE (Bit 4) */ - #define R_CAN0_EIER_BORIE_Msk (0x10UL) /*!< BORIE (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIER_BOEIE_Pos (3UL) /*!< BOEIE (Bit 3) */ - #define R_CAN0_EIER_BOEIE_Msk (0x8UL) /*!< BOEIE (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIER_EPIE_Pos (2UL) /*!< EPIE (Bit 2) */ - #define R_CAN0_EIER_EPIE_Msk (0x4UL) /*!< EPIE (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIER_EWIE_Pos (1UL) /*!< EWIE (Bit 1) */ - #define R_CAN0_EIER_EWIE_Msk (0x2UL) /*!< EWIE (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIER_BEIE_Pos (0UL) /*!< BEIE (Bit 0) */ - #define R_CAN0_EIER_BEIE_Msk (0x1UL) /*!< BEIE (Bitfield-Mask: 0x01) */ -/* ========================================================= EIFR ========================================================== */ - #define R_CAN0_EIFR_BLIF_Pos (7UL) /*!< BLIF (Bit 7) */ - #define R_CAN0_EIFR_BLIF_Msk (0x80UL) /*!< BLIF (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIFR_OLIF_Pos (6UL) /*!< OLIF (Bit 6) */ - #define R_CAN0_EIFR_OLIF_Msk (0x40UL) /*!< OLIF (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIFR_ORIF_Pos (5UL) /*!< ORIF (Bit 5) */ - #define R_CAN0_EIFR_ORIF_Msk (0x20UL) /*!< ORIF (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIFR_BORIF_Pos (4UL) /*!< BORIF (Bit 4) */ - #define R_CAN0_EIFR_BORIF_Msk (0x10UL) /*!< BORIF (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIFR_BOEIF_Pos (3UL) /*!< BOEIF (Bit 3) */ - #define R_CAN0_EIFR_BOEIF_Msk (0x8UL) /*!< BOEIF (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIFR_EPIF_Pos (2UL) /*!< EPIF (Bit 2) */ - #define R_CAN0_EIFR_EPIF_Msk (0x4UL) /*!< EPIF (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIFR_EWIF_Pos (1UL) /*!< EWIF (Bit 1) */ - #define R_CAN0_EIFR_EWIF_Msk (0x2UL) /*!< EWIF (Bitfield-Mask: 0x01) */ - #define R_CAN0_EIFR_BEIF_Pos (0UL) /*!< BEIF (Bit 0) */ - #define R_CAN0_EIFR_BEIF_Msk (0x1UL) /*!< BEIF (Bitfield-Mask: 0x01) */ -/* ========================================================= RECR ========================================================== */ - #define R_CAN0_RECR_RECR_Pos (0UL) /*!< RECR (Bit 0) */ - #define R_CAN0_RECR_RECR_Msk (0xffUL) /*!< RECR (Bitfield-Mask: 0xff) */ -/* ========================================================= TECR ========================================================== */ - #define R_CAN0_TECR_TECR_Pos (0UL) /*!< TECR (Bit 0) */ - #define R_CAN0_TECR_TECR_Msk (0xffUL) /*!< TECR (Bitfield-Mask: 0xff) */ -/* ========================================================= ECSR ========================================================== */ - #define R_CAN0_ECSR_EDPM_Pos (7UL) /*!< EDPM (Bit 7) */ - #define R_CAN0_ECSR_EDPM_Msk (0x80UL) /*!< EDPM (Bitfield-Mask: 0x01) */ - #define R_CAN0_ECSR_ADEF_Pos (6UL) /*!< ADEF (Bit 6) */ - #define R_CAN0_ECSR_ADEF_Msk (0x40UL) /*!< ADEF (Bitfield-Mask: 0x01) */ - #define R_CAN0_ECSR_BE0F_Pos (5UL) /*!< BE0F (Bit 5) */ - #define R_CAN0_ECSR_BE0F_Msk (0x20UL) /*!< BE0F (Bitfield-Mask: 0x01) */ - #define R_CAN0_ECSR_BE1F_Pos (4UL) /*!< BE1F (Bit 4) */ - #define R_CAN0_ECSR_BE1F_Msk (0x10UL) /*!< BE1F (Bitfield-Mask: 0x01) */ - #define R_CAN0_ECSR_CEF_Pos (3UL) /*!< CEF (Bit 3) */ - #define R_CAN0_ECSR_CEF_Msk (0x8UL) /*!< CEF (Bitfield-Mask: 0x01) */ - #define R_CAN0_ECSR_AEF_Pos (2UL) /*!< AEF (Bit 2) */ - #define R_CAN0_ECSR_AEF_Msk (0x4UL) /*!< AEF (Bitfield-Mask: 0x01) */ - #define R_CAN0_ECSR_FEF_Pos (1UL) /*!< FEF (Bit 1) */ - #define R_CAN0_ECSR_FEF_Msk (0x2UL) /*!< FEF (Bitfield-Mask: 0x01) */ - #define R_CAN0_ECSR_SEF_Pos (0UL) /*!< SEF (Bit 0) */ - #define R_CAN0_ECSR_SEF_Msk (0x1UL) /*!< SEF (Bitfield-Mask: 0x01) */ -/* ========================================================= CSSR ========================================================== */ - #define R_CAN0_CSSR_CSSR_Pos (0UL) /*!< CSSR (Bit 0) */ - #define R_CAN0_CSSR_CSSR_Msk (0xffUL) /*!< CSSR (Bitfield-Mask: 0xff) */ -/* ========================================================= MSSR ========================================================== */ - #define R_CAN0_MSSR_SEST_Pos (7UL) /*!< SEST (Bit 7) */ - #define R_CAN0_MSSR_SEST_Msk (0x80UL) /*!< SEST (Bitfield-Mask: 0x01) */ - #define R_CAN0_MSSR_MBNST_Pos (0UL) /*!< MBNST (Bit 0) */ - #define R_CAN0_MSSR_MBNST_Msk (0x1fUL) /*!< MBNST (Bitfield-Mask: 0x1f) */ -/* ========================================================= MSMR ========================================================== */ - #define R_CAN0_MSMR_MBSM_Pos (0UL) /*!< MBSM (Bit 0) */ - #define R_CAN0_MSMR_MBSM_Msk (0x3UL) /*!< MBSM (Bitfield-Mask: 0x03) */ -/* ========================================================== TSR ========================================================== */ - #define R_CAN0_TSR_TSR_Pos (0UL) /*!< TSR (Bit 0) */ - #define R_CAN0_TSR_TSR_Msk (0xffffUL) /*!< TSR (Bitfield-Mask: 0xffff) */ -/* ========================================================= AFSR ========================================================== */ - #define R_CAN0_AFSR_AFSR_Pos (0UL) /*!< AFSR (Bit 0) */ - #define R_CAN0_AFSR_AFSR_Msk (0xffffUL) /*!< AFSR (Bitfield-Mask: 0xffff) */ -/* ========================================================== TCR ========================================================== */ - #define R_CAN0_TCR_TSTM_Pos (1UL) /*!< TSTM (Bit 1) */ - #define R_CAN0_TCR_TSTM_Msk (0x6UL) /*!< TSTM (Bitfield-Mask: 0x03) */ - #define R_CAN0_TCR_TSTE_Pos (0UL) /*!< TSTE (Bit 0) */ - #define R_CAN0_TCR_TSTE_Msk (0x1UL) /*!< TSTE (Bitfield-Mask: 0x01) */ - -/* =========================================================================================================================== */ -/* ================ R_CANFD ================ */ +/* ================ R_CANFD0 ================ */ /* =========================================================================================================================== */ /* ======================================================== CFDGCFG ======================================================== */ @@ -22611,8 +20320,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ #define R_CANFD_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ #define R_CANFD_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCFG_TSBTCS_Pos (13UL) /*!< TSBTCS (Bit 13) */ - #define R_CANFD_CFDGCFG_TSBTCS_Msk (0xe000UL) /*!< TSBTCS (Bitfield-Mask: 0x07) */ #define R_CANFD_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ #define R_CANFD_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ /* ======================================================== CFDGCTR ======================================================== */ @@ -22628,14 +20335,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ #define R_CANFD_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_QMEIE_Pos (14UL) /*!< QMEIE (Bit 14) */ - #define R_CANFD_CFDGCTR_QMEIE_Msk (0x4000UL) /*!< QMEIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_MOWEIE_Pos (15UL) /*!< MOWEIE (Bit 15) */ - #define R_CANFD_CFDGCTR_MOWEIE_Msk (0x8000UL) /*!< MOWEIE (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ #define R_CANFD_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGCTR_TSWR_Pos (17UL) /*!< TSWR (Bit 17) */ - #define R_CANFD_CFDGCTR_TSWR_Msk (0x20000UL) /*!< TSWR (Bitfield-Mask: 0x01) */ /* ======================================================== CFDGSTS ======================================================== */ #define R_CANFD_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ #define R_CANFD_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ @@ -22654,20 +20355,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ #define R_CANFD_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_QOWES_Pos (4UL) /*!< QOWES (Bit 4) */ - #define R_CANFD_CFDGERFL_QOWES_Msk (0x10UL) /*!< QOWES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_OTBMLTSTS_Pos (5UL) /*!< OTBMLTSTS (Bit 5) */ - #define R_CANFD_CFDGERFL_OTBMLTSTS_Msk (0x20UL) /*!< OTBMLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_QMES_Pos (6UL) /*!< QMES (Bit 6) */ - #define R_CANFD_CFDGERFL_QMES_Msk (0x40UL) /*!< QMES (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_RXSFAIL0_Pos (8UL) /*!< RXSFAIL0 (Bit 8) */ - #define R_CANFD_CFDGERFL_RXSFAIL0_Msk (0x100UL) /*!< RXSFAIL0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_RXSFAIL1_Pos (9UL) /*!< RXSFAIL1 (Bit 9) */ - #define R_CANFD_CFDGERFL_RXSFAIL1_Msk (0x200UL) /*!< RXSFAIL1 (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ #define R_CANFD_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGERFL_EEF1_Pos (17UL) /*!< EEF1 (Bit 17) */ - #define R_CANFD_CFDGERFL_EEF1_Msk (0x20000UL) /*!< EEF1 (Bitfield-Mask: 0x01) */ /* ======================================================== CFDGTSC ======================================================== */ #define R_CANFD_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ #define R_CANFD_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ @@ -22689,6 +20378,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ======================================================= CFDRMND0 ======================================================== */ #define R_CANFD_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ #define R_CANFD_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ +/* ======================================================= CFDRMIEC ======================================================== */ + #define R_CANFD_CFDRMIEC_RMIE_Pos (0UL) /*!< RMIE (Bit 0) */ + #define R_CANFD_CFDRMIEC_RMIE_Msk (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff) */ /* ======================================================== CFDRFCC ======================================================== */ #define R_CANFD_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ #define R_CANFD_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ @@ -22702,8 +20394,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ #define R_CANFD_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDRFCC_RFFIE_Pos (16UL) /*!< RFFIE (Bit 16) */ - #define R_CANFD_CFDRFCC_RFFIE_Msk (0x10000UL) /*!< RFFIE (Bitfield-Mask: 0x01) */ /* ======================================================= CFDRFSTS ======================================================== */ #define R_CANFD_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ #define R_CANFD_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ @@ -22715,8 +20405,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ #define R_CANFD_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRFSTS_RFFIF_Pos (16UL) /*!< RFFIF (Bit 16) */ - #define R_CANFD_CFDRFSTS_RFFIF_Msk (0x10000UL) /*!< RFFIF (Bitfield-Mask: 0x01) */ /* ======================================================= CFDRFPCTR ======================================================= */ #define R_CANFD_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ #define R_CANFD_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ @@ -22745,17 +20433,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ #define R_CANFD_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ #define R_CANFD_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDCFCCE ======================================================== */ - #define R_CANFD_CFDCFCCE_CFFIE_Pos (0UL) /*!< CFFIE (Bit 0) */ - #define R_CANFD_CFDCFCCE_CFFIE_Msk (0x1UL) /*!< CFFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFOFRXIE_Pos (1UL) /*!< CFOFRXIE (Bit 1) */ - #define R_CANFD_CFDCFCCE_CFOFRXIE_Msk (0x2UL) /*!< CFOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFOFTXIE_Pos (2UL) /*!< CFOFTXIE (Bit 2) */ - #define R_CANFD_CFDCFCCE_CFOFTXIE_Msk (0x4UL) /*!< CFOFTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFMOWM_Pos (8UL) /*!< CFMOWM (Bit 8) */ - #define R_CANFD_CFDCFCCE_CFMOWM_Msk (0x100UL) /*!< CFMOWM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFCCE_CFBME_Pos (16UL) /*!< CFBME (Bit 16) */ - #define R_CANFD_CFDCFCCE_CFBME_Msk (0x10000UL) /*!< CFBME (Bitfield-Mask: 0x01) */ /* ======================================================= CFDCFSTS ======================================================== */ #define R_CANFD_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ #define R_CANFD_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ @@ -22769,57 +20446,27 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ #define R_CANFD_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDCFSTS_CFFIF_Pos (16UL) /*!< CFFIF (Bit 16) */ - #define R_CANFD_CFDCFSTS_CFFIF_Msk (0x10000UL) /*!< CFFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFOFRXIF_Pos (17UL) /*!< CFOFRXIF (Bit 17) */ - #define R_CANFD_CFDCFSTS_CFOFRXIF_Msk (0x20000UL) /*!< CFOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFOFTXIF_Pos (18UL) /*!< CFOFTXIF (Bit 18) */ - #define R_CANFD_CFDCFSTS_CFOFTXIF_Msk (0x40000UL) /*!< CFOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCFSTS_CFMOW_Pos (24UL) /*!< CFMOW (Bit 24) */ - #define R_CANFD_CFDCFSTS_CFMOW_Msk (0x1000000UL) /*!< CFMOW (Bitfield-Mask: 0x01) */ /* ======================================================= CFDCFPCTR ======================================================= */ #define R_CANFD_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ #define R_CANFD_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ /* ======================================================= CFDFESTS ======================================================== */ #define R_CANFD_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ - #define R_CANFD_CFDFESTS_RFXEMP_Msk (0xffUL) /*!< RFXEMP (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFESTS_RFXEMP_Msk (0x3UL) /*!< RFXEMP (Bitfield-Mask: 0x03) */ #define R_CANFD_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ - #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x3f00UL) /*!< CFXEMP (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDFESTS_CFXEMP_Msk (0x100UL) /*!< CFXEMP (Bitfield-Mask: 0x01) */ /* ======================================================= CFDFFSTS ======================================================== */ #define R_CANFD_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ - #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0xffUL) /*!< RFXFLL (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFFSTS_RFXFLL_Msk (0x3UL) /*!< RFXFLL (Bitfield-Mask: 0x03) */ #define R_CANFD_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ - #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x3f00UL) /*!< CFXFLL (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDFFSTS_CFXFLL_Msk (0x100UL) /*!< CFXFLL (Bitfield-Mask: 0x01) */ /* ======================================================= CFDFMSTS ======================================================== */ #define R_CANFD_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ - #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0xffUL) /*!< RFXMLT (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDFMSTS_RFXMLT_Msk (0x3UL) /*!< RFXMLT (Bitfield-Mask: 0x03) */ #define R_CANFD_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ - #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x3f00UL) /*!< CFXMLT (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ /* ======================================================= CFDRFISTS ======================================================= */ #define R_CANFD_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ - #define R_CANFD_CFDRFISTS_RFXIF_Msk (0xffUL) /*!< RFXIF (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDRFISTS_RFXFFLL_Pos (16UL) /*!< RFXFFLL (Bit 16) */ - #define R_CANFD_CFDRFISTS_RFXFFLL_Msk (0xff0000UL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDCFRISTS ======================================================= */ - #define R_CANFD_CFDCFRISTS_CFXRXIF_Pos (0UL) /*!< CFXRXIF (Bit 0) */ - #define R_CANFD_CFDCFRISTS_CFXRXIF_Msk (0x3fUL) /*!< CFXRXIF (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDCFTISTS ======================================================= */ - #define R_CANFD_CFDCFTISTS_CFXTXIF_Pos (0UL) /*!< CFXTXIF (Bit 0) */ - #define R_CANFD_CFDCFTISTS_CFXTXIF_Msk (0x3fUL) /*!< CFXTXIF (Bitfield-Mask: 0x3f) */ -/* ===================================================== CFDCFOFRISTS ====================================================== */ - #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Pos (0UL) /*!< CFXOFRXIF (Bit 0) */ - #define R_CANFD_CFDCFOFRISTS_CFXOFRXIF_Msk (0x3fUL) /*!< CFXOFRXIF (Bitfield-Mask: 0x3f) */ -/* ===================================================== CFDCFOFTISTS ====================================================== */ - #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Pos (0UL) /*!< CFXOFTXIF (Bit 0) */ - #define R_CANFD_CFDCFOFTISTS_CFXOFTXIF_Msk (0x3fUL) /*!< CFXOFTXIF (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDCFMOWSTS ====================================================== */ - #define R_CANFD_CFDCFMOWSTS_CFXMOW_Pos (0UL) /*!< CFXMOW (Bit 0) */ - #define R_CANFD_CFDCFMOWSTS_CFXMOW_Msk (0x3fUL) /*!< CFXMOW (Bitfield-Mask: 0x3f) */ -/* ======================================================= CFDFFFSTS ======================================================= */ - #define R_CANFD_CFDFFFSTS_RFXFFLL_Pos (0UL) /*!< RFXFFLL (Bit 0) */ - #define R_CANFD_CFDFFFSTS_RFXFFLL_Msk (0xffUL) /*!< RFXFFLL (Bitfield-Mask: 0xff) */ - #define R_CANFD_CFDFFFSTS_CFXFFLL_Pos (8UL) /*!< CFXFFLL (Bit 8) */ - #define R_CANFD_CFDFFFSTS_CFXFFLL_Msk (0x3f00UL) /*!< CFXFFLL (Bitfield-Mask: 0x3f) */ + #define R_CANFD_CFDRFISTS_RFXIF_Msk (0x1UL) /*!< RFXIF (Bitfield-Mask: 0x01) */ /* ======================================================== CFDTMC ========================================================= */ #define R_CANFD_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ #define R_CANFD_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ @@ -22838,36 +20485,28 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ /* ====================================================== CFDTMTRSTS ======================================================= */ #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ - #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xffUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xfUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f) */ /* ====================================================== CFDTMTARSTS ====================================================== */ #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ - #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xffUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xfUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f) */ /* ====================================================== CFDTMTCSTS ======================================================= */ #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ - #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xffUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xfUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f) */ /* ====================================================== CFDTMTASTS ======================================================= */ #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ - #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xffUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDTMTASTS_CFDTMTASTSg_Msk (0xfUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f) */ /* ======================================================= CFDTMIEC ======================================================== */ #define R_CANFD_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ - #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xffUL) /*!< TMIEg (Bitfield-Mask: 0xff) */ + #define R_CANFD_CFDTMIEC_TMIEg_Msk (0xfUL) /*!< TMIEg (Bitfield-Mask: 0x0f) */ /* ======================================================= CFDTXQCC0 ======================================================= */ #define R_CANFD_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ #define R_CANFD_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC0_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ #define R_CANFD_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ #define R_CANFD_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC0_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC0_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC0_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC0_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ + #define R_CANFD_CFDTXQCC0_TXQDC_Msk (0x300UL) /*!< TXQDC (Bitfield-Mask: 0x03) */ /* ====================================================== CFDTXQSTS0 ======================================================= */ #define R_CANFD_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ #define R_CANFD_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ @@ -22877,149 +20516,9 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ #define R_CANFD_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS0_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS0_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS0_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS0_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS0_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS0_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ /* ====================================================== CFDTXQPCTR0 ====================================================== */ #define R_CANFD_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ #define R_CANFD_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC1 ======================================================= */ - #define R_CANFD_CFDTXQCC1_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC1_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC1_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC1_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC1_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC1_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC1_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC1_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC1_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC1_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS1 ======================================================= */ - #define R_CANFD_CFDTXQSTS1_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS1_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS1_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS1_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS1_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS1_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS1_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS1_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS1_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS1_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS1_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR1 ====================================================== */ - #define R_CANFD_CFDTXQPCTR1_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR1_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC2 ======================================================= */ - #define R_CANFD_CFDTXQCC2_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC2_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQGWE_Pos (1UL) /*!< TXQGWE (Bit 1) */ - #define R_CANFD_CFDTXQCC2_TXQGWE_Msk (0x2UL) /*!< TXQGWE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC2_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC2_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC2_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC2_TXQFIE_Pos (16UL) /*!< TXQFIE (Bit 16) */ - #define R_CANFD_CFDTXQCC2_TXQFIE_Msk (0x10000UL) /*!< TXQFIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Pos (17UL) /*!< TXQOFRXIE (Bit 17) */ - #define R_CANFD_CFDTXQCC2_TXQOFRXIE_Msk (0x20000UL) /*!< TXQOFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC2_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS2 ======================================================= */ - #define R_CANFD_CFDTXQSTS2_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS2_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS2_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS2_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS2_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS2_TXQFIF_Pos (16UL) /*!< TXQFIF (Bit 16) */ - #define R_CANFD_CFDTXQSTS2_TXQFIF_Msk (0x10000UL) /*!< TXQFIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Pos (17UL) /*!< TXQOFRXIF (Bit 17) */ - #define R_CANFD_CFDTXQSTS2_TXQOFRXIF_Msk (0x20000UL) /*!< TXQOFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS2_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS2_TXQMLT_Pos (19UL) /*!< TXQMLT (Bit 19) */ - #define R_CANFD_CFDTXQSTS2_TXQMLT_Msk (0x80000UL) /*!< TXQMLT (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR2 ====================================================== */ - #define R_CANFD_CFDTXQPCTR2_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR2_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTXQCC3 ======================================================= */ - #define R_CANFD_CFDTXQCC3_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFD_CFDTXQCC3_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFD_CFDTXQCC3_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFD_CFDTXQCC3_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQCC3_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFD_CFDTXQCC3_TXQDC_Msk (0x1f00UL) /*!< TXQDC (Bitfield-Mask: 0x1f) */ - #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Pos (18UL) /*!< TXQOFTXIE (Bit 18) */ - #define R_CANFD_CFDTXQCC3_TXQOFTXIE_Msk (0x40000UL) /*!< TXQOFTXIE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQSTS3 ======================================================= */ - #define R_CANFD_CFDTXQSTS3_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFD_CFDTXQSTS3_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFD_CFDTXQSTS3_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFD_CFDTXQSTS3_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTXQSTS3_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFD_CFDTXQSTS3_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ - #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Pos (18UL) /*!< TXQOFTXIF (Bit 18) */ - #define R_CANFD_CFDTXQSTS3_TXQOFTXIF_Msk (0x40000UL) /*!< TXQOFTXIF (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTXQPCTR3 ====================================================== */ - #define R_CANFD_CFDTXQPCTR3_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFD_CFDTXQPCTR3_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTXQESTS ======================================================= */ - #define R_CANFD_CFDTXQESTS_TXQxEMP_Pos (0UL) /*!< TXQxEMP (Bit 0) */ - #define R_CANFD_CFDTXQESTS_TXQxEMP_Msk (0xffUL) /*!< TXQxEMP (Bitfield-Mask: 0xff) */ -/* ====================================================== CFDTXQFISTS ====================================================== */ - #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Pos (0UL) /*!< TXQ0FULL (Bit 0) */ - #define R_CANFD_CFDTXQFISTS_TXQ0FULL_Msk (0x7UL) /*!< TXQ0FULL (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Pos (4UL) /*!< TXQ1FULL (Bit 4) */ - #define R_CANFD_CFDTXQFISTS_TXQ1FULL_Msk (0x70UL) /*!< TXQ1FULL (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQMSTS ======================================================= */ - #define R_CANFD_CFDTXQMSTS_TXQ0ML_Pos (0UL) /*!< TXQ0ML (Bit 0) */ - #define R_CANFD_CFDTXQMSTS_TXQ0ML_Msk (0x7UL) /*!< TXQ0ML (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQMSTS_TXQ1ML_Pos (4UL) /*!< TXQ1ML (Bit 4) */ - #define R_CANFD_CFDTXQMSTS_TXQ1ML_Msk (0x70UL) /*!< TXQ1ML (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQISTS ======================================================= */ - #define R_CANFD_CFDTXQISTS_TXQ0ISF_Pos (0UL) /*!< TXQ0ISF (Bit 0) */ - #define R_CANFD_CFDTXQISTS_TXQ0ISF_Msk (0xfUL) /*!< TXQ0ISF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQISTS_TXQ1ISF_Pos (4UL) /*!< TXQ1ISF (Bit 4) */ - #define R_CANFD_CFDTXQISTS_TXQ1ISF_Msk (0xf0UL) /*!< TXQ1ISF (Bitfield-Mask: 0x0f) */ -/* ===================================================== CFDTXQOFTISTS ===================================================== */ - #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Pos (0UL) /*!< TXQ0OFTISF (Bit 0) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ0OFTISF_Msk (0xfUL) /*!< TXQ0OFTISF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Pos (4UL) /*!< TXQ1OFTISF (Bit 4) */ - #define R_CANFD_CFDTXQOFTISTS_TXQ1OFTISF_Msk (0xf0UL) /*!< TXQ1OFTISF (Bitfield-Mask: 0x0f) */ -/* ===================================================== CFDTXQOFRISTS ===================================================== */ - #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Pos (0UL) /*!< TXQ0OFRISF (Bit 0) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ0OFRISF_Msk (0x7UL) /*!< TXQ0OFRISF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Pos (4UL) /*!< TXQ1OFRISF (Bit 4) */ - #define R_CANFD_CFDTXQOFRISTS_TXQ1OFRISF_Msk (0x70UL) /*!< TXQ1OFRISF (Bitfield-Mask: 0x07) */ -/* ====================================================== CFDTXQFSTS ======================================================= */ - #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Pos (0UL) /*!< TXQ0FSF (Bit 0) */ - #define R_CANFD_CFDTXQFSTS_TXQ0FSF_Msk (0xfUL) /*!< TXQ0FSF (Bitfield-Mask: 0x0f) */ - #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Pos (4UL) /*!< TXQ1FSF (Bit 4) */ - #define R_CANFD_CFDTXQFSTS_TXQ1FSF_Msk (0xf0UL) /*!< TXQ1FSF (Bitfield-Mask: 0x0f) */ /* ======================================================= CFDTHLCC ======================================================== */ #define R_CANFD_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ #define R_CANFD_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ @@ -23029,8 +20528,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ #define R_CANFD_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDTHLCC_THLDGE_Pos (11UL) /*!< THLDGE (Bit 11) */ - #define R_CANFD_CFDTHLCC_THLDGE_Msk (0x800UL) /*!< THLDGE (Bitfield-Mask: 0x01) */ /* ======================================================= CFDTHLSTS ======================================================= */ #define R_CANFD_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ #define R_CANFD_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ @@ -23056,32 +20553,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ #define R_CANFD_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Pos (5UL) /*!< TQOFIF0 (Bit 5) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF0_Msk (0x20UL) /*!< TQOFIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Pos (6UL) /*!< CFOTIF0 (Bit 6) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF0_Msk (0x40UL) /*!< CFOTIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TSIF1_Pos (8UL) /*!< TSIF1 (Bit 8) */ - #define R_CANFD_CFDGTINTSTS0_TSIF1_Msk (0x100UL) /*!< TSIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TAIF1_Pos (9UL) /*!< TAIF1 (Bit 9) */ - #define R_CANFD_CFDGTINTSTS0_TAIF1_Msk (0x200UL) /*!< TAIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQIF1_Pos (10UL) /*!< TQIF1 (Bit 10) */ - #define R_CANFD_CFDGTINTSTS0_TQIF1_Msk (0x400UL) /*!< TQIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF1_Pos (11UL) /*!< CFTIF1 (Bit 11) */ - #define R_CANFD_CFDGTINTSTS0_CFTIF1_Msk (0x800UL) /*!< CFTIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_THIF1_Pos (12UL) /*!< THIF1 (Bit 12) */ - #define R_CANFD_CFDGTINTSTS0_THIF1_Msk (0x1000UL) /*!< THIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Pos (13UL) /*!< TQOFIF1 (Bit 13) */ - #define R_CANFD_CFDGTINTSTS0_TQOFIF1_Msk (0x2000UL) /*!< TQOFIF1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Pos (14UL) /*!< CFOTIF1 (Bit 14) */ - #define R_CANFD_CFDGTINTSTS0_CFOTIF1_Msk (0x4000UL) /*!< CFOTIF1 (Bitfield-Mask: 0x01) */ /* ====================================================== CFDGTSTCFG ======================================================= */ - #define R_CANFD_CFDGTSTCFG_ICBCE_Pos (0UL) /*!< ICBCE (Bit 0) */ - #define R_CANFD_CFDGTSTCFG_ICBCE_Msk (0x3UL) /*!< ICBCE (Bitfield-Mask: 0x03) */ #define R_CANFD_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ #define R_CANFD_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ /* ====================================================== CFDGTSTCTR ======================================================= */ - #define R_CANFD_CFDGTSTCTR_ICBCTME_Pos (0UL) /*!< ICBCTME (Bit 0) */ - #define R_CANFD_CFDGTSTCTR_ICBCTME_Msk (0x1UL) /*!< ICBCTME (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ #define R_CANFD_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ /* ======================================================= CFDGFDCFG ======================================================= */ @@ -23089,28 +20564,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ #define R_CANFD_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ -/* ====================================================== CFDGCRCCFG ======================================================= */ - #define R_CANFD_CFDGCRCCFG_NIE_Pos (0UL) /*!< NIE (Bit 0) */ - #define R_CANFD_CFDGCRCCFG_NIE_Msk (0x1UL) /*!< NIE (Bitfield-Mask: 0x01) */ /* ======================================================= CFDGLOCKK ======================================================= */ #define R_CANFD_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ #define R_CANFD_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ -/* ======================================================= CFDGLOTB ======================================================== */ - #define R_CANFD_CFDGLOTB_OTBFE_Pos (0UL) /*!< OTBFE (Bit 0) */ - #define R_CANFD_CFDGLOTB_OTBFE_Msk (0x1UL) /*!< OTBFE (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBEMP_Pos (8UL) /*!< OTBEMP (Bit 8) */ - #define R_CANFD_CFDGLOTB_OTBEMP_Msk (0x100UL) /*!< OTBEMP (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBFLL_Pos (9UL) /*!< OTBFLL (Bit 9) */ - #define R_CANFD_CFDGLOTB_OTBFLL_Msk (0x200UL) /*!< OTBFLL (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBMLT_Pos (10UL) /*!< OTBMLT (Bit 10) */ - #define R_CANFD_CFDGLOTB_OTBMLT_Msk (0x400UL) /*!< OTBMLT (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDGLOTB_OTBMC_Pos (11UL) /*!< OTBMC (Bit 11) */ - #define R_CANFD_CFDGLOTB_OTBMC_Msk (0xf800UL) /*!< OTBMC (Bitfield-Mask: 0x1f) */ /* ===================================================== CFDGAFLIGNENT ===================================================== */ #define R_CANFD_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ - #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1ffUL) /*!< IRN (Bitfield-Mask: 0x1ff) */ - #define R_CANFD_CFDGAFLIGNENT_ICN_Pos (16UL) /*!< ICN (Bit 16) */ - #define R_CANFD_CFDGAFLIGNENT_ICN_Msk (0x70000UL) /*!< ICN (Bitfield-Mask: 0x07) */ + #define R_CANFD_CFDGAFLIGNENT_IRN_Msk (0x1fUL) /*!< IRN (Bitfield-Mask: 0x1f) */ /* ===================================================== CFDGAFLIGNCTR ===================================================== */ #define R_CANFD_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ #define R_CANFD_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ @@ -23121,80 +20580,15 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ #define R_CANFD_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE2_Pos (2UL) /*!< RFDMAE2 (Bit 2) */ - #define R_CANFD_CFDCDTCT_RFDMAE2_Msk (0x4UL) /*!< RFDMAE2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE3_Pos (3UL) /*!< RFDMAE3 (Bit 3) */ - #define R_CANFD_CFDCDTCT_RFDMAE3_Msk (0x8UL) /*!< RFDMAE3 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE4_Pos (4UL) /*!< RFDMAE4 (Bit 4) */ - #define R_CANFD_CFDCDTCT_RFDMAE4_Msk (0x10UL) /*!< RFDMAE4 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE5_Pos (5UL) /*!< RFDMAE5 (Bit 5) */ - #define R_CANFD_CFDCDTCT_RFDMAE5_Msk (0x20UL) /*!< RFDMAE5 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE6_Pos (6UL) /*!< RFDMAE6 (Bit 6) */ - #define R_CANFD_CFDCDTCT_RFDMAE6_Msk (0x40UL) /*!< RFDMAE6 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_RFDMAE7_Pos (7UL) /*!< RFDMAE7 (Bit 7) */ - #define R_CANFD_CFDCDTCT_RFDMAE7_Msk (0x80UL) /*!< RFDMAE7 (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ #define R_CANFD_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTCT_CFDMAE1_Pos (9UL) /*!< CFDMAE1 (Bit 9) */ - #define R_CANFD_CFDCDTCT_CFDMAE1_Msk (0x200UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ /* ======================================================= CFDCDTSTS ======================================================= */ #define R_CANFD_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ #define R_CANFD_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ #define R_CANFD_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS2_Pos (2UL) /*!< RFDMASTS2 (Bit 2) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS2_Msk (0x4UL) /*!< RFDMASTS2 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS3_Pos (3UL) /*!< RFDMASTS3 (Bit 3) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS3_Msk (0x8UL) /*!< RFDMASTS3 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS4_Pos (4UL) /*!< RFDMASTS4 (Bit 4) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS4_Msk (0x10UL) /*!< RFDMASTS4 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS5_Pos (5UL) /*!< RFDMASTS5 (Bit 5) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS5_Msk (0x20UL) /*!< RFDMASTS5 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS6_Pos (6UL) /*!< RFDMASTS6 (Bit 6) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS6_Msk (0x40UL) /*!< RFDMASTS6 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS7_Pos (7UL) /*!< RFDMASTS7 (Bit 7) */ - #define R_CANFD_CFDCDTSTS_RFDMASTS7_Msk (0x80UL) /*!< RFDMASTS7 (Bitfield-Mask: 0x01) */ #define R_CANFD_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ #define R_CANFD_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS1_Pos (9UL) /*!< CFDMASTS1 (Bit 9) */ - #define R_CANFD_CFDCDTSTS_CFDMASTS1_Msk (0x200UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCDTTCT ======================================================= */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Pos (0UL) /*!< TQ0DMAE0 (Bit 0) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE0_Msk (0x1UL) /*!< TQ0DMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Pos (1UL) /*!< TQ0DMAE1 (Bit 1) */ - #define R_CANFD_CFDCDTTCT_TQ0DMAE1_Msk (0x2UL) /*!< TQ0DMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Pos (8UL) /*!< TQ3DMAE0 (Bit 8) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE0_Msk (0x100UL) /*!< TQ3DMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Pos (9UL) /*!< TQ3DMAE1 (Bit 9) */ - #define R_CANFD_CFDCDTTCT_TQ3DMAE1_Msk (0x200UL) /*!< TQ3DMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_CFDMAE0_Pos (16UL) /*!< CFDMAE0 (Bit 16) */ - #define R_CANFD_CFDCDTTCT_CFDMAE0_Msk (0x10000UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTCT_CFDMAE1_Pos (17UL) /*!< CFDMAE1 (Bit 17) */ - #define R_CANFD_CFDCDTTCT_CFDMAE1_Msk (0x20000UL) /*!< CFDMAE1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDCDTTSTS ======================================================= */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Pos (0UL) /*!< TQ0DMASTS0 (Bit 0) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS0_Msk (0x1UL) /*!< TQ0DMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Pos (1UL) /*!< TQ0DMASTS1 (Bit 1) */ - #define R_CANFD_CFDCDTTSTS_TQ0DMASTS1_Msk (0x2UL) /*!< TQ0DMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Pos (8UL) /*!< TQ3DMASTS0 (Bit 8) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS0_Msk (0x100UL) /*!< TQ3DMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Pos (9UL) /*!< TQ3DMASTS1 (Bit 9) */ - #define R_CANFD_CFDCDTTSTS_TQ3DMASTS1_Msk (0x200UL) /*!< TQ3DMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Pos (16UL) /*!< CFDMASTS0 (Bit 16) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS0_Msk (0x10000UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Pos (17UL) /*!< CFDMASTS1 (Bit 17) */ - #define R_CANFD_CFDCDTTSTS_CFDMASTS1_Msk (0x20000UL) /*!< CFDMASTS1 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGRINTSTS ====================================================== */ - #define R_CANFD_CFDGRINTSTS_QFIF_Pos (0UL) /*!< QFIF (Bit 0) */ - #define R_CANFD_CFDGRINTSTS_QFIF_Msk (0x7UL) /*!< QFIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_QOFRIF_Pos (8UL) /*!< QOFRIF (Bit 8) */ - #define R_CANFD_CFDGRINTSTS_QOFRIF_Msk (0x700UL) /*!< QOFRIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFRIF_Pos (16UL) /*!< CFRIF (Bit 16) */ - #define R_CANFD_CFDGRINTSTS_CFRIF_Msk (0x70000UL) /*!< CFRIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFRFIF_Pos (24UL) /*!< CFRFIF (Bit 24) */ - #define R_CANFD_CFDGRINTSTS_CFRFIF_Msk (0x7000000UL) /*!< CFRFIF (Bitfield-Mask: 0x07) */ - #define R_CANFD_CFDGRINTSTS_CFOFRIF_Pos (28UL) /*!< CFOFRIF (Bit 28) */ - #define R_CANFD_CFDGRINTSTS_CFOFRIF_Msk (0x70000000UL) /*!< CFOFRIF (Bitfield-Mask: 0x07) */ /* ======================================================= CFDGRSTC ======================================================== */ #define R_CANFD_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ #define R_CANFD_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ @@ -23204,305 +20598,6 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_CANFD_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ #define R_CANFD_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ -/* =========================================================================================================================== */ -/* ================ R_CANFDL ================ */ -/* =========================================================================================================================== */ - -/* ======================================================== CFDGCFG ======================================================== */ - #define R_CANFDL_CFDGCFG_TPRI_Pos (0UL) /*!< TPRI (Bit 0) */ - #define R_CANFDL_CFDGCFG_TPRI_Msk (0x1UL) /*!< TPRI (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGCFG_DCE_Pos (1UL) /*!< DCE (Bit 1) */ - #define R_CANFDL_CFDGCFG_DCE_Msk (0x2UL) /*!< DCE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGCFG_DRE_Pos (2UL) /*!< DRE (Bit 2) */ - #define R_CANFDL_CFDGCFG_DRE_Msk (0x4UL) /*!< DRE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGCFG_MME_Pos (3UL) /*!< MME (Bit 3) */ - #define R_CANFDL_CFDGCFG_MME_Msk (0x8UL) /*!< MME (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGCFG_DCS_Pos (4UL) /*!< DCS (Bit 4) */ - #define R_CANFDL_CFDGCFG_DCS_Msk (0x10UL) /*!< DCS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGCFG_CMPOC_Pos (5UL) /*!< CMPOC (Bit 5) */ - #define R_CANFDL_CFDGCFG_CMPOC_Msk (0x20UL) /*!< CMPOC (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGCFG_TSP_Pos (8UL) /*!< TSP (Bit 8) */ - #define R_CANFDL_CFDGCFG_TSP_Msk (0xf00UL) /*!< TSP (Bitfield-Mask: 0x0f) */ - #define R_CANFDL_CFDGCFG_TSSS_Pos (12UL) /*!< TSSS (Bit 12) */ - #define R_CANFDL_CFDGCFG_TSSS_Msk (0x1000UL) /*!< TSSS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGCFG_ITRCP_Pos (16UL) /*!< ITRCP (Bit 16) */ - #define R_CANFDL_CFDGCFG_ITRCP_Msk (0xffff0000UL) /*!< ITRCP (Bitfield-Mask: 0xffff) */ -/* ======================================================== CFDGCTR ======================================================== */ - #define R_CANFDL_CFDGCTR_GMDC_Pos (0UL) /*!< GMDC (Bit 0) */ - #define R_CANFDL_CFDGCTR_GMDC_Msk (0x3UL) /*!< GMDC (Bitfield-Mask: 0x03) */ - #define R_CANFDL_CFDGCTR_GSLPR_Pos (2UL) /*!< GSLPR (Bit 2) */ - #define R_CANFDL_CFDGCTR_GSLPR_Msk (0x4UL) /*!< GSLPR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGCTR_DEIE_Pos (8UL) /*!< DEIE (Bit 8) */ - #define R_CANFDL_CFDGCTR_DEIE_Msk (0x100UL) /*!< DEIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGCTR_MEIE_Pos (9UL) /*!< MEIE (Bit 9) */ - #define R_CANFDL_CFDGCTR_MEIE_Msk (0x200UL) /*!< MEIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGCTR_THLEIE_Pos (10UL) /*!< THLEIE (Bit 10) */ - #define R_CANFDL_CFDGCTR_THLEIE_Msk (0x400UL) /*!< THLEIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGCTR_CMPOFIE_Pos (11UL) /*!< CMPOFIE (Bit 11) */ - #define R_CANFDL_CFDGCTR_CMPOFIE_Msk (0x800UL) /*!< CMPOFIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGCTR_TSRST_Pos (16UL) /*!< TSRST (Bit 16) */ - #define R_CANFDL_CFDGCTR_TSRST_Msk (0x10000UL) /*!< TSRST (Bitfield-Mask: 0x01) */ -/* ======================================================== CFDGSTS ======================================================== */ - #define R_CANFDL_CFDGSTS_GRSTSTS_Pos (0UL) /*!< GRSTSTS (Bit 0) */ - #define R_CANFDL_CFDGSTS_GRSTSTS_Msk (0x1UL) /*!< GRSTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGSTS_GHLTSTS_Pos (1UL) /*!< GHLTSTS (Bit 1) */ - #define R_CANFDL_CFDGSTS_GHLTSTS_Msk (0x2UL) /*!< GHLTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGSTS_GSLPSTS_Pos (2UL) /*!< GSLPSTS (Bit 2) */ - #define R_CANFDL_CFDGSTS_GSLPSTS_Msk (0x4UL) /*!< GSLPSTS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGSTS_GRAMINIT_Pos (3UL) /*!< GRAMINIT (Bit 3) */ - #define R_CANFDL_CFDGSTS_GRAMINIT_Msk (0x8UL) /*!< GRAMINIT (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDGERFL ======================================================== */ - #define R_CANFDL_CFDGERFL_DEF_Pos (0UL) /*!< DEF (Bit 0) */ - #define R_CANFDL_CFDGERFL_DEF_Msk (0x1UL) /*!< DEF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGERFL_MES_Pos (1UL) /*!< MES (Bit 1) */ - #define R_CANFDL_CFDGERFL_MES_Msk (0x2UL) /*!< MES (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGERFL_THLES_Pos (2UL) /*!< THLES (Bit 2) */ - #define R_CANFDL_CFDGERFL_THLES_Msk (0x4UL) /*!< THLES (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGERFL_CMPOF_Pos (3UL) /*!< CMPOF (Bit 3) */ - #define R_CANFDL_CFDGERFL_CMPOF_Msk (0x8UL) /*!< CMPOF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGERFL_EEF0_Pos (16UL) /*!< EEF0 (Bit 16) */ - #define R_CANFDL_CFDGERFL_EEF0_Msk (0x10000UL) /*!< EEF0 (Bitfield-Mask: 0x01) */ -/* ======================================================== CFDGTSC ======================================================== */ - #define R_CANFDL_CFDGTSC_TS_Pos (0UL) /*!< TS (Bit 0) */ - #define R_CANFDL_CFDGTSC_TS_Msk (0xffffUL) /*!< TS (Bitfield-Mask: 0xffff) */ -/* ====================================================== CFDGAFLECTR ====================================================== */ - #define R_CANFDL_CFDGAFLECTR_AFLPN_Pos (0UL) /*!< AFLPN (Bit 0) */ - #define R_CANFDL_CFDGAFLECTR_AFLPN_Msk (0xfUL) /*!< AFLPN (Bitfield-Mask: 0x0f) */ - #define R_CANFDL_CFDGAFLECTR_AFLDAE_Pos (8UL) /*!< AFLDAE (Bit 8) */ - #define R_CANFDL_CFDGAFLECTR_AFLDAE_Msk (0x100UL) /*!< AFLDAE (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGAFLCFG0 ====================================================== */ - #define R_CANFDL_CFDGAFLCFG0_RNC1_Pos (0UL) /*!< RNC1 (Bit 0) */ - #define R_CANFDL_CFDGAFLCFG0_RNC1_Msk (0x1ffUL) /*!< RNC1 (Bitfield-Mask: 0x1ff) */ - #define R_CANFDL_CFDGAFLCFG0_RNC0_Pos (16UL) /*!< RNC0 (Bit 16) */ - #define R_CANFDL_CFDGAFLCFG0_RNC0_Msk (0x1ff0000UL) /*!< RNC0 (Bitfield-Mask: 0x1ff) */ -/* ======================================================== CFDRMNB ======================================================== */ - #define R_CANFDL_CFDRMNB_NRXMB_Pos (0UL) /*!< NRXMB (Bit 0) */ - #define R_CANFDL_CFDRMNB_NRXMB_Msk (0xffUL) /*!< NRXMB (Bitfield-Mask: 0xff) */ - #define R_CANFDL_CFDRMNB_RMPLS_Pos (8UL) /*!< RMPLS (Bit 8) */ - #define R_CANFDL_CFDRMNB_RMPLS_Msk (0x700UL) /*!< RMPLS (Bitfield-Mask: 0x07) */ -/* ======================================================= CFDRMND0 ======================================================== */ - #define R_CANFDL_CFDRMND0_RMNSu_Pos (0UL) /*!< RMNSu (Bit 0) */ - #define R_CANFDL_CFDRMND0_RMNSu_Msk (0xffffffffUL) /*!< RMNSu (Bitfield-Mask: 0xffffffff) */ -/* ======================================================= CFDRMIEC ======================================================== */ - #define R_CANFDL_CFDRMIEC_RMIE_Pos (0UL) /*!< RMIE (Bit 0) */ - #define R_CANFDL_CFDRMIEC_RMIE_Msk (0xffffffffUL) /*!< RMIE (Bitfield-Mask: 0xffffffff) */ -/* ======================================================== CFDRFCC ======================================================== */ - #define R_CANFDL_CFDRFCC_RFE_Pos (0UL) /*!< RFE (Bit 0) */ - #define R_CANFDL_CFDRFCC_RFE_Msk (0x1UL) /*!< RFE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDRFCC_RFIE_Pos (1UL) /*!< RFIE (Bit 1) */ - #define R_CANFDL_CFDRFCC_RFIE_Msk (0x2UL) /*!< RFIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDRFCC_RFPLS_Pos (4UL) /*!< RFPLS (Bit 4) */ - #define R_CANFDL_CFDRFCC_RFPLS_Msk (0x70UL) /*!< RFPLS (Bitfield-Mask: 0x07) */ - #define R_CANFDL_CFDRFCC_RFDC_Pos (8UL) /*!< RFDC (Bit 8) */ - #define R_CANFDL_CFDRFCC_RFDC_Msk (0x700UL) /*!< RFDC (Bitfield-Mask: 0x07) */ - #define R_CANFDL_CFDRFCC_RFIM_Pos (12UL) /*!< RFIM (Bit 12) */ - #define R_CANFDL_CFDRFCC_RFIM_Msk (0x1000UL) /*!< RFIM (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDRFCC_RFIGCV_Pos (13UL) /*!< RFIGCV (Bit 13) */ - #define R_CANFDL_CFDRFCC_RFIGCV_Msk (0xe000UL) /*!< RFIGCV (Bitfield-Mask: 0x07) */ -/* ======================================================= CFDRFSTS ======================================================== */ - #define R_CANFDL_CFDRFSTS_RFEMP_Pos (0UL) /*!< RFEMP (Bit 0) */ - #define R_CANFDL_CFDRFSTS_RFEMP_Msk (0x1UL) /*!< RFEMP (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDRFSTS_RFFLL_Pos (1UL) /*!< RFFLL (Bit 1) */ - #define R_CANFDL_CFDRFSTS_RFFLL_Msk (0x2UL) /*!< RFFLL (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDRFSTS_RFMLT_Pos (2UL) /*!< RFMLT (Bit 2) */ - #define R_CANFDL_CFDRFSTS_RFMLT_Msk (0x4UL) /*!< RFMLT (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDRFSTS_RFIF_Pos (3UL) /*!< RFIF (Bit 3) */ - #define R_CANFDL_CFDRFSTS_RFIF_Msk (0x8UL) /*!< RFIF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDRFSTS_RFMC_Pos (8UL) /*!< RFMC (Bit 8) */ - #define R_CANFDL_CFDRFSTS_RFMC_Msk (0xff00UL) /*!< RFMC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDRFPCTR ======================================================= */ - #define R_CANFDL_CFDRFPCTR_RFPC_Pos (0UL) /*!< RFPC (Bit 0) */ - #define R_CANFDL_CFDRFPCTR_RFPC_Msk (0xffUL) /*!< RFPC (Bitfield-Mask: 0xff) */ -/* ======================================================== CFDCFCC ======================================================== */ - #define R_CANFDL_CFDCFCC_CFE_Pos (0UL) /*!< CFE (Bit 0) */ - #define R_CANFDL_CFDCFCC_CFE_Msk (0x1UL) /*!< CFE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCFCC_CFRXIE_Pos (1UL) /*!< CFRXIE (Bit 1) */ - #define R_CANFDL_CFDCFCC_CFRXIE_Msk (0x2UL) /*!< CFRXIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCFCC_CFTXIE_Pos (2UL) /*!< CFTXIE (Bit 2) */ - #define R_CANFDL_CFDCFCC_CFTXIE_Msk (0x4UL) /*!< CFTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCFCC_CFPLS_Pos (4UL) /*!< CFPLS (Bit 4) */ - #define R_CANFDL_CFDCFCC_CFPLS_Msk (0x70UL) /*!< CFPLS (Bitfield-Mask: 0x07) */ - #define R_CANFDL_CFDCFCC_CFM_Pos (8UL) /*!< CFM (Bit 8) */ - #define R_CANFDL_CFDCFCC_CFM_Msk (0x300UL) /*!< CFM (Bitfield-Mask: 0x03) */ - #define R_CANFDL_CFDCFCC_CFITSS_Pos (10UL) /*!< CFITSS (Bit 10) */ - #define R_CANFDL_CFDCFCC_CFITSS_Msk (0x400UL) /*!< CFITSS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCFCC_CFITR_Pos (11UL) /*!< CFITR (Bit 11) */ - #define R_CANFDL_CFDCFCC_CFITR_Msk (0x800UL) /*!< CFITR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCFCC_CFIM_Pos (12UL) /*!< CFIM (Bit 12) */ - #define R_CANFDL_CFDCFCC_CFIM_Msk (0x1000UL) /*!< CFIM (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCFCC_CFIGCV_Pos (13UL) /*!< CFIGCV (Bit 13) */ - #define R_CANFDL_CFDCFCC_CFIGCV_Msk (0xe000UL) /*!< CFIGCV (Bitfield-Mask: 0x07) */ - #define R_CANFDL_CFDCFCC_CFTML_Pos (16UL) /*!< CFTML (Bit 16) */ - #define R_CANFDL_CFDCFCC_CFTML_Msk (0x1f0000UL) /*!< CFTML (Bitfield-Mask: 0x1f) */ - #define R_CANFDL_CFDCFCC_CFDC_Pos (21UL) /*!< CFDC (Bit 21) */ - #define R_CANFDL_CFDCFCC_CFDC_Msk (0xe00000UL) /*!< CFDC (Bitfield-Mask: 0x07) */ - #define R_CANFDL_CFDCFCC_CFITT_Pos (24UL) /*!< CFITT (Bit 24) */ - #define R_CANFDL_CFDCFCC_CFITT_Msk (0xff000000UL) /*!< CFITT (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDCFSTS ======================================================== */ - #define R_CANFDL_CFDCFSTS_CFEMP_Pos (0UL) /*!< CFEMP (Bit 0) */ - #define R_CANFDL_CFDCFSTS_CFEMP_Msk (0x1UL) /*!< CFEMP (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCFSTS_CFFLL_Pos (1UL) /*!< CFFLL (Bit 1) */ - #define R_CANFDL_CFDCFSTS_CFFLL_Msk (0x2UL) /*!< CFFLL (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCFSTS_CFMLT_Pos (2UL) /*!< CFMLT (Bit 2) */ - #define R_CANFDL_CFDCFSTS_CFMLT_Msk (0x4UL) /*!< CFMLT (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCFSTS_CFRXIF_Pos (3UL) /*!< CFRXIF (Bit 3) */ - #define R_CANFDL_CFDCFSTS_CFRXIF_Msk (0x8UL) /*!< CFRXIF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCFSTS_CFTXIF_Pos (4UL) /*!< CFTXIF (Bit 4) */ - #define R_CANFDL_CFDCFSTS_CFTXIF_Msk (0x10UL) /*!< CFTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCFSTS_CFMC_Pos (8UL) /*!< CFMC (Bit 8) */ - #define R_CANFDL_CFDCFSTS_CFMC_Msk (0xff00UL) /*!< CFMC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDCFPCTR ======================================================= */ - #define R_CANFDL_CFDCFPCTR_CFPC_Pos (0UL) /*!< CFPC (Bit 0) */ - #define R_CANFDL_CFDCFPCTR_CFPC_Msk (0xffUL) /*!< CFPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDFESTS ======================================================== */ - #define R_CANFDL_CFDFESTS_RFXEMP_Pos (0UL) /*!< RFXEMP (Bit 0) */ - #define R_CANFDL_CFDFESTS_RFXEMP_Msk (0x3UL) /*!< RFXEMP (Bitfield-Mask: 0x03) */ - #define R_CANFDL_CFDFESTS_CFXEMP_Pos (8UL) /*!< CFXEMP (Bit 8) */ - #define R_CANFDL_CFDFESTS_CFXEMP_Msk (0x100UL) /*!< CFXEMP (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDFFSTS ======================================================== */ - #define R_CANFDL_CFDFFSTS_RFXFLL_Pos (0UL) /*!< RFXFLL (Bit 0) */ - #define R_CANFDL_CFDFFSTS_RFXFLL_Msk (0x3UL) /*!< RFXFLL (Bitfield-Mask: 0x03) */ - #define R_CANFDL_CFDFFSTS_CFXFLL_Pos (8UL) /*!< CFXFLL (Bit 8) */ - #define R_CANFDL_CFDFFSTS_CFXFLL_Msk (0x100UL) /*!< CFXFLL (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDFMSTS ======================================================== */ - #define R_CANFDL_CFDFMSTS_RFXMLT_Pos (0UL) /*!< RFXMLT (Bit 0) */ - #define R_CANFDL_CFDFMSTS_RFXMLT_Msk (0x3UL) /*!< RFXMLT (Bitfield-Mask: 0x03) */ - #define R_CANFDL_CFDFMSTS_CFXMLT_Pos (8UL) /*!< CFXMLT (Bit 8) */ - #define R_CANFDL_CFDFMSTS_CFXMLT_Msk (0x100UL) /*!< CFXMLT (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDRFISTS ======================================================= */ - #define R_CANFDL_CFDRFISTS_RFXIF_Pos (0UL) /*!< RFXIF (Bit 0) */ - #define R_CANFDL_CFDRFISTS_RFXIF_Msk (0x1UL) /*!< RFXIF (Bitfield-Mask: 0x01) */ -/* ======================================================== CFDTMC ========================================================= */ - #define R_CANFDL_CFDTMC_TMTR_Pos (0UL) /*!< TMTR (Bit 0) */ - #define R_CANFDL_CFDTMC_TMTR_Msk (0x1UL) /*!< TMTR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTMC_TMTAR_Pos (1UL) /*!< TMTAR (Bit 1) */ - #define R_CANFDL_CFDTMC_TMTAR_Msk (0x2UL) /*!< TMTAR (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTMC_TMOM_Pos (2UL) /*!< TMOM (Bit 2) */ - #define R_CANFDL_CFDTMC_TMOM_Msk (0x4UL) /*!< TMOM (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDTMSTS ======================================================== */ - #define R_CANFDL_CFDTMSTS_TMTSTS_Pos (0UL) /*!< TMTSTS (Bit 0) */ - #define R_CANFDL_CFDTMSTS_TMTSTS_Msk (0x1UL) /*!< TMTSTS (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTMSTS_TMTRF_Pos (1UL) /*!< TMTRF (Bit 1) */ - #define R_CANFDL_CFDTMSTS_TMTRF_Msk (0x6UL) /*!< TMTRF (Bitfield-Mask: 0x03) */ - #define R_CANFDL_CFDTMSTS_TMTRM_Pos (3UL) /*!< TMTRM (Bit 3) */ - #define R_CANFDL_CFDTMSTS_TMTRM_Msk (0x8UL) /*!< TMTRM (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTMSTS_TMTARM_Pos (4UL) /*!< TMTARM (Bit 4) */ - #define R_CANFDL_CFDTMSTS_TMTARM_Msk (0x10UL) /*!< TMTARM (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDTMTRSTS ======================================================= */ - #define R_CANFDL_CFDTMTRSTS_CFDTMTRSTSg_Pos (0UL) /*!< CFDTMTRSTSg (Bit 0) */ - #define R_CANFDL_CFDTMTRSTS_CFDTMTRSTSg_Msk (0xfUL) /*!< CFDTMTRSTSg (Bitfield-Mask: 0x0f) */ -/* ====================================================== CFDTMTARSTS ====================================================== */ - #define R_CANFDL_CFDTMTARSTS_CFDTMTARSTSg_Pos (0UL) /*!< CFDTMTARSTSg (Bit 0) */ - #define R_CANFDL_CFDTMTARSTS_CFDTMTARSTSg_Msk (0xfUL) /*!< CFDTMTARSTSg (Bitfield-Mask: 0x0f) */ -/* ====================================================== CFDTMTCSTS ======================================================= */ - #define R_CANFDL_CFDTMTCSTS_CFDTMTCSTSg_Pos (0UL) /*!< CFDTMTCSTSg (Bit 0) */ - #define R_CANFDL_CFDTMTCSTS_CFDTMTCSTSg_Msk (0xfUL) /*!< CFDTMTCSTSg (Bitfield-Mask: 0x0f) */ -/* ====================================================== CFDTMTASTS ======================================================= */ - #define R_CANFDL_CFDTMTASTS_CFDTMTASTSg_Pos (0UL) /*!< CFDTMTASTSg (Bit 0) */ - #define R_CANFDL_CFDTMTASTS_CFDTMTASTSg_Msk (0xfUL) /*!< CFDTMTASTSg (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFDTMIEC ======================================================== */ - #define R_CANFDL_CFDTMIEC_TMIEg_Pos (0UL) /*!< TMIEg (Bit 0) */ - #define R_CANFDL_CFDTMIEC_TMIEg_Msk (0xfUL) /*!< TMIEg (Bitfield-Mask: 0x0f) */ -/* ======================================================= CFDTXQCC0 ======================================================= */ - #define R_CANFDL_CFDTXQCC0_TXQE_Pos (0UL) /*!< TXQE (Bit 0) */ - #define R_CANFDL_CFDTXQCC0_TXQE_Msk (0x1UL) /*!< TXQE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTXQCC0_TXQTXIE_Pos (5UL) /*!< TXQTXIE (Bit 5) */ - #define R_CANFDL_CFDTXQCC0_TXQTXIE_Msk (0x20UL) /*!< TXQTXIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTXQCC0_TXQIM_Pos (7UL) /*!< TXQIM (Bit 7) */ - #define R_CANFDL_CFDTXQCC0_TXQIM_Msk (0x80UL) /*!< TXQIM (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTXQCC0_TXQDC_Pos (8UL) /*!< TXQDC (Bit 8) */ - #define R_CANFDL_CFDTXQCC0_TXQDC_Msk (0x300UL) /*!< TXQDC (Bitfield-Mask: 0x03) */ -/* ====================================================== CFDTXQSTS0 ======================================================= */ - #define R_CANFDL_CFDTXQSTS0_TXQEMP_Pos (0UL) /*!< TXQEMP (Bit 0) */ - #define R_CANFDL_CFDTXQSTS0_TXQEMP_Msk (0x1UL) /*!< TXQEMP (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTXQSTS0_TXQFLL_Pos (1UL) /*!< TXQFLL (Bit 1) */ - #define R_CANFDL_CFDTXQSTS0_TXQFLL_Msk (0x2UL) /*!< TXQFLL (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTXQSTS0_TXQTXIF_Pos (2UL) /*!< TXQTXIF (Bit 2) */ - #define R_CANFDL_CFDTXQSTS0_TXQTXIF_Msk (0x4UL) /*!< TXQTXIF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTXQSTS0_TXQMC_Pos (8UL) /*!< TXQMC (Bit 8) */ - #define R_CANFDL_CFDTXQSTS0_TXQMC_Msk (0x3f00UL) /*!< TXQMC (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDTXQPCTR0 ====================================================== */ - #define R_CANFDL_CFDTXQPCTR0_TXQPC_Pos (0UL) /*!< TXQPC (Bit 0) */ - #define R_CANFDL_CFDTXQPCTR0_TXQPC_Msk (0xffUL) /*!< TXQPC (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDTHLCC ======================================================== */ - #define R_CANFDL_CFDTHLCC_THLE_Pos (0UL) /*!< THLE (Bit 0) */ - #define R_CANFDL_CFDTHLCC_THLE_Msk (0x1UL) /*!< THLE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTHLCC_THLIE_Pos (8UL) /*!< THLIE (Bit 8) */ - #define R_CANFDL_CFDTHLCC_THLIE_Msk (0x100UL) /*!< THLIE (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTHLCC_THLIM_Pos (9UL) /*!< THLIM (Bit 9) */ - #define R_CANFDL_CFDTHLCC_THLIM_Msk (0x200UL) /*!< THLIM (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTHLCC_THLDTE_Pos (10UL) /*!< THLDTE (Bit 10) */ - #define R_CANFDL_CFDTHLCC_THLDTE_Msk (0x400UL) /*!< THLDTE (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDTHLSTS ======================================================= */ - #define R_CANFDL_CFDTHLSTS_THLEMP_Pos (0UL) /*!< THLEMP (Bit 0) */ - #define R_CANFDL_CFDTHLSTS_THLEMP_Msk (0x1UL) /*!< THLEMP (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTHLSTS_THLFLL_Pos (1UL) /*!< THLFLL (Bit 1) */ - #define R_CANFDL_CFDTHLSTS_THLFLL_Msk (0x2UL) /*!< THLFLL (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTHLSTS_THLELT_Pos (2UL) /*!< THLELT (Bit 2) */ - #define R_CANFDL_CFDTHLSTS_THLELT_Msk (0x4UL) /*!< THLELT (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTHLSTS_THLIF_Pos (3UL) /*!< THLIF (Bit 3) */ - #define R_CANFDL_CFDTHLSTS_THLIF_Msk (0x8UL) /*!< THLIF (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDTHLSTS_THLMC_Pos (8UL) /*!< THLMC (Bit 8) */ - #define R_CANFDL_CFDTHLSTS_THLMC_Msk (0x3f00UL) /*!< THLMC (Bitfield-Mask: 0x3f) */ -/* ====================================================== CFDTHLPCTR ======================================================= */ - #define R_CANFDL_CFDTHLPCTR_THLPC_Pos (0UL) /*!< THLPC (Bit 0) */ - #define R_CANFDL_CFDTHLPCTR_THLPC_Msk (0xffUL) /*!< THLPC (Bitfield-Mask: 0xff) */ -/* ===================================================== CFDGTINTSTS0 ====================================================== */ - #define R_CANFDL_CFDGTINTSTS0_TSIF0_Pos (0UL) /*!< TSIF0 (Bit 0) */ - #define R_CANFDL_CFDGTINTSTS0_TSIF0_Msk (0x1UL) /*!< TSIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGTINTSTS0_TAIF0_Pos (1UL) /*!< TAIF0 (Bit 1) */ - #define R_CANFDL_CFDGTINTSTS0_TAIF0_Msk (0x2UL) /*!< TAIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGTINTSTS0_TQIF0_Pos (2UL) /*!< TQIF0 (Bit 2) */ - #define R_CANFDL_CFDGTINTSTS0_TQIF0_Msk (0x4UL) /*!< TQIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGTINTSTS0_CFTIF0_Pos (3UL) /*!< CFTIF0 (Bit 3) */ - #define R_CANFDL_CFDGTINTSTS0_CFTIF0_Msk (0x8UL) /*!< CFTIF0 (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGTINTSTS0_THIF0_Pos (4UL) /*!< THIF0 (Bit 4) */ - #define R_CANFDL_CFDGTINTSTS0_THIF0_Msk (0x10UL) /*!< THIF0 (Bitfield-Mask: 0x01) */ -/* ====================================================== CFDGTSTCFG ======================================================= */ - #define R_CANFDL_CFDGTSTCFG_RTMPS_Pos (16UL) /*!< RTMPS (Bit 16) */ - #define R_CANFDL_CFDGTSTCFG_RTMPS_Msk (0x3ff0000UL) /*!< RTMPS (Bitfield-Mask: 0x3ff) */ -/* ====================================================== CFDGTSTCTR ======================================================= */ - #define R_CANFDL_CFDGTSTCTR_RTME_Pos (2UL) /*!< RTME (Bit 2) */ - #define R_CANFDL_CFDGTSTCTR_RTME_Msk (0x4UL) /*!< RTME (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDGFDCFG ======================================================= */ - #define R_CANFDL_CFDGFDCFG_RPED_Pos (0UL) /*!< RPED (Bit 0) */ - #define R_CANFDL_CFDGFDCFG_RPED_Msk (0x1UL) /*!< RPED (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGFDCFG_TSCCFG_Pos (8UL) /*!< TSCCFG (Bit 8) */ - #define R_CANFDL_CFDGFDCFG_TSCCFG_Msk (0x300UL) /*!< TSCCFG (Bitfield-Mask: 0x03) */ -/* ======================================================= CFDGLOCKK ======================================================= */ - #define R_CANFDL_CFDGLOCKK_LOCK_Pos (0UL) /*!< LOCK (Bit 0) */ - #define R_CANFDL_CFDGLOCKK_LOCK_Msk (0xffffUL) /*!< LOCK (Bitfield-Mask: 0xffff) */ -/* ===================================================== CFDGAFLIGNENT ===================================================== */ - #define R_CANFDL_CFDGAFLIGNENT_IRN_Pos (0UL) /*!< IRN (Bit 0) */ - #define R_CANFDL_CFDGAFLIGNENT_IRN_Msk (0x1fUL) /*!< IRN (Bitfield-Mask: 0x1f) */ -/* ===================================================== CFDGAFLIGNCTR ===================================================== */ - #define R_CANFDL_CFDGAFLIGNCTR_IREN_Pos (0UL) /*!< IREN (Bit 0) */ - #define R_CANFDL_CFDGAFLIGNCTR_IREN_Msk (0x1UL) /*!< IREN (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGAFLIGNCTR_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_CANFDL_CFDGAFLIGNCTR_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDCDTCT ======================================================== */ - #define R_CANFDL_CFDCDTCT_RFDMAE0_Pos (0UL) /*!< RFDMAE0 (Bit 0) */ - #define R_CANFDL_CFDCDTCT_RFDMAE0_Msk (0x1UL) /*!< RFDMAE0 (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCDTCT_RFDMAE1_Pos (1UL) /*!< RFDMAE1 (Bit 1) */ - #define R_CANFDL_CFDCDTCT_RFDMAE1_Msk (0x2UL) /*!< RFDMAE1 (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCDTCT_CFDMAE0_Pos (8UL) /*!< CFDMAE0 (Bit 8) */ - #define R_CANFDL_CFDCDTCT_CFDMAE0_Msk (0x100UL) /*!< CFDMAE0 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDCDTSTS ======================================================= */ - #define R_CANFDL_CFDCDTSTS_RFDMASTS0_Pos (0UL) /*!< RFDMASTS0 (Bit 0) */ - #define R_CANFDL_CFDCDTSTS_RFDMASTS0_Msk (0x1UL) /*!< RFDMASTS0 (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCDTSTS_RFDMASTS1_Pos (1UL) /*!< RFDMASTS1 (Bit 1) */ - #define R_CANFDL_CFDCDTSTS_RFDMASTS1_Msk (0x2UL) /*!< RFDMASTS1 (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDCDTSTS_CFDMASTS0_Pos (8UL) /*!< CFDMASTS0 (Bit 8) */ - #define R_CANFDL_CFDCDTSTS_CFDMASTS0_Msk (0x100UL) /*!< CFDMASTS0 (Bitfield-Mask: 0x01) */ -/* ======================================================= CFDGRSTC ======================================================== */ - #define R_CANFDL_CFDGRSTC_SRST_Pos (0UL) /*!< SRST (Bit 0) */ - #define R_CANFDL_CFDGRSTC_SRST_Msk (0x1UL) /*!< SRST (Bitfield-Mask: 0x01) */ - #define R_CANFDL_CFDGRSTC_KEY_Pos (8UL) /*!< KEY (Bit 8) */ - #define R_CANFDL_CFDGRSTC_KEY_Msk (0xff00UL) /*!< KEY (Bitfield-Mask: 0xff) */ -/* ======================================================= CFDRPGACC ======================================================= */ - #define R_CANFDL_CFDRPGACC_RDTA_Pos (0UL) /*!< RDTA (Bit 0) */ - #define R_CANFDL_CFDRPGACC_RDTA_Msk (0xffffffffUL) /*!< RDTA (Bitfield-Mask: 0xffffffff) */ - /* =========================================================================================================================== */ /* ================ R_CRC ================ */ /* =========================================================================================================================== */ @@ -23571,8 +20666,10 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_DAC_DAASWCR_DAASW0_Pos (6UL) /*!< DAASW0 (Bit 6) */ #define R_DAC_DAASWCR_DAASW0_Msk (0x40UL) /*!< DAASW0 (Bitfield-Mask: 0x01) */ /* ======================================================== DAADUSR ======================================================== */ - #define R_DAC_DAADUSR_AMADSEL1_Pos (6UL) /*!< AMADSEL1 (Bit 6) */ - #define R_DAC_DAADUSR_AMADSEL1_Msk (0x40UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL0_Pos (0UL) /*!< AMADSEL0 (Bit 0) */ + #define R_DAC_DAADUSR_AMADSEL0_Msk (0x1UL) /*!< AMADSEL0 (Bitfield-Mask: 0x01) */ + #define R_DAC_DAADUSR_AMADSEL1_Pos (1UL) /*!< AMADSEL1 (Bit 1) */ + #define R_DAC_DAADUSR_AMADSEL1_Msk (0x2UL) /*!< AMADSEL1 (Bitfield-Mask: 0x01) */ /* =========================================================================================================================== */ /* ================ R_DEBUG ================ */ @@ -25687,6 +22784,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRC_MSTPC21_Msk (0x200000UL) /*!< MSTPC21 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC20_Pos (20UL) /*!< MSTPC20 (Bit 20) */ #define R_MSTP_MSTPCRC_MSTPC20_Msk (0x100000UL) /*!< MSTPC20 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRC_MSTPC15_Pos (15UL) /*!< MSTPC15 (Bit 15) */ + #define R_MSTP_MSTPCRC_MSTPC15_Msk (0x8000UL) /*!< MSTPC15 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC14_Pos (14UL) /*!< MSTPC14 (Bit 14) */ #define R_MSTP_MSTPCRC_MSTPC14_Msk (0x4000UL) /*!< MSTPC14 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRC_MSTPC13_Pos (13UL) /*!< MSTPC13 (Bit 13) */ @@ -25738,6 +22837,8 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRD_MSTPD20_Msk (0x100000UL) /*!< MSTPD20 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD19_Pos (19UL) /*!< MSTPD19 (Bit 19) */ #define R_MSTP_MSTPCRD_MSTPD19_Msk (0x80000UL) /*!< MSTPD19 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD18_Pos (18UL) /*!< MSTPD18 (Bit 18) */ + #define R_MSTP_MSTPCRD_MSTPD18_Msk (0x40000UL) /*!< MSTPD18 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD17_Pos (17UL) /*!< MSTPD17 (Bit 17) */ #define R_MSTP_MSTPCRD_MSTPD17_Msk (0x20000UL) /*!< MSTPD17 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD16_Pos (16UL) /*!< MSTPD16 (Bit 16) */ @@ -25752,6 +22853,14 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_MSTP_MSTPCRD_MSTPD12_Msk (0x1000UL) /*!< MSTPD12 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD11_Pos (11UL) /*!< MSTPD11 (Bit 11) */ #define R_MSTP_MSTPCRD_MSTPD11_Msk (0x800UL) /*!< MSTPD11 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD10_Pos (10UL) /*!< MSTPD10 (Bit 10) */ + #define R_MSTP_MSTPCRD_MSTPD10_Msk (0x400UL) /*!< MSTPD10 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD9_Pos (9UL) /*!< MSTPD9 (Bit 9) */ + #define R_MSTP_MSTPCRD_MSTPD9_Msk (0x200UL) /*!< MSTPD9 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD8_Pos (8UL) /*!< MSTPD8 (Bit 8) */ + #define R_MSTP_MSTPCRD_MSTPD8_Msk (0x100UL) /*!< MSTPD8 (Bitfield-Mask: 0x01) */ + #define R_MSTP_MSTPCRD_MSTPD7_Pos (7UL) /*!< MSTPD7 (Bit 7) */ + #define R_MSTP_MSTPCRD_MSTPD7_Msk (0x80UL) /*!< MSTPD7 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD6_Pos (6UL) /*!< MSTPD6 (Bit 6) */ #define R_MSTP_MSTPCRD_MSTPD6_Msk (0x40UL) /*!< MSTPD6 (Bitfield-Mask: 0x01) */ #define R_MSTP_MSTPCRD_MSTPD5_Pos (5UL) /*!< MSTPD5 (Bit 5) */ @@ -26503,6 +23612,121 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SRAM_SRAMPRCR2_KW_Pos (1UL) /*!< KW (Bit 1) */ #define R_SRAM_SRAMPRCR2_KW_Msk (0xfeUL) /*!< KW (Bitfield-Mask: 0x7f) */ +/* =========================================================================================================================== */ +/* ================ R_BUS_B ================ */ +/* =========================================================================================================================== */ + +/* ===================================================== BUSSCNTFHBIU ====================================================== */ + #define R_BUS_B_BUSSCNTFHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTFHBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTFLBIU ====================================================== */ + #define R_BUS_B_BUSSCNTFLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTFLBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTS0BIU ====================================================== */ + #define R_BUS_B_BUSSCNTS0BIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTS0BIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTPSBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPSBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPSBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTPLBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPLBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPLBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTPHBIU ====================================================== */ + #define R_BUS_B_BUSSCNTPHBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTPHBIU_ARBS_Msk (0x1UL) /*!< ARBS (Bitfield-Mask: 0x01) */ +/* ===================================================== BUSSCNTEQBIU ====================================================== */ + #define R_BUS_B_BUSSCNTEQBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTEQBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTEOBIU ====================================================== */ + #define R_BUS_B_BUSSCNTEOBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTEOBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ===================================================== BUSSCNTECBIU ====================================================== */ + #define R_BUS_B_BUSSCNTECBIU_ARBS_Pos (0UL) /*!< ARBS (Bit 0) */ + #define R_BUS_B_BUSSCNTECBIU_ARBS_Msk (0x3UL) /*!< ARBS (Bitfield-Mask: 0x03) */ +/* ====================================================== BUS1ERRSTAT ====================================================== */ + #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS1ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS1ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS1ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS1ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS2ERRSTAT ====================================================== */ + #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS2ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS2ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS2ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS2ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS3ERRSTAT ====================================================== */ + #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS3ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS3ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS3ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS3ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS4ERRSTAT ====================================================== */ + #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Pos (0UL) /*!< SLERRSTAT (Bit 0) */ + #define R_BUS_B_BUS4ERRSTAT_SLERRSTAT_Msk (0x1UL) /*!< SLERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Pos (1UL) /*!< STERRSTAT (Bit 1) */ + #define R_BUS_B_BUS4ERRSTAT_STERRSTAT_Msk (0x2UL) /*!< STERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Pos (3UL) /*!< MMERRSTAT (Bit 3) */ + #define R_BUS_B_BUS4ERRSTAT_MMERRSTAT_Msk (0x8UL) /*!< MMERRSTAT (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Pos (4UL) /*!< ILERRSTAT (Bit 4) */ + #define R_BUS_B_BUS4ERRSTAT_ILERRSTAT_Msk (0x10UL) /*!< ILERRSTAT (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS1ERRCLR ======================================================= */ + #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS1ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS1ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS1ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS1ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS2ERRCLR ======================================================= */ + #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS2ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS2ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS2ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS2ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS3ERRCLR ======================================================= */ + #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS3ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS3ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS3ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS3ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ====================================================== BUS4ERRCLR ======================================================= */ + #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Pos (0UL) /*!< SLERRCLR (Bit 0) */ + #define R_BUS_B_BUS4ERRCLR_SLERRCLR_Msk (0x1UL) /*!< SLERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_STERRCLR_Pos (1UL) /*!< STERRCLR (Bit 1) */ + #define R_BUS_B_BUS4ERRCLR_STERRCLR_Msk (0x2UL) /*!< STERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Pos (3UL) /*!< MMERRCLR (Bit 3) */ + #define R_BUS_B_BUS4ERRCLR_MMERRCLR_Msk (0x8UL) /*!< MMERRCLR (Bitfield-Mask: 0x01) */ + #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Pos (4UL) /*!< ILERRCLR (Bit 4) */ + #define R_BUS_B_BUS4ERRCLR_ILERRCLR_Msk (0x10UL) /*!< ILERRCLR (Bitfield-Mask: 0x01) */ +/* ==================================================== DMACDTCERRSTAT ===================================================== */ + #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Pos (0UL) /*!< MTERRSTAT (Bit 0) */ + #define R_BUS_B_DMACDTCERRSTAT_MTERRSTAT_Msk (0x1UL) /*!< MTERRSTAT (Bitfield-Mask: 0x01) */ +/* ===================================================== DMACDTCERRCLR ===================================================== */ + #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Pos (0UL) /*!< MTERRCLR (Bit 0) */ + #define R_BUS_B_DMACDTCERRCLR_MTERRCLR_Msk (0x1UL) /*!< MTERRCLR (Bitfield-Mask: 0x01) */ +/* ======================================================== CSRECEN ======================================================== */ + #define R_BUS_B_CSRECEN_RCVENM_Pos (8UL) /*!< RCVENM (Bit 8) */ + #define R_BUS_B_CSRECEN_RCVENM_Msk (0x100UL) /*!< RCVENM (Bitfield-Mask: 0x01) */ + #define R_BUS_B_CSRECEN_RCVEN_Pos (0UL) /*!< RCVEN (Bit 0) */ + #define R_BUS_B_CSRECEN_RCVEN_Msk (0x1UL) /*!< RCVEN (Bitfield-Mask: 0x01) */ + /* =========================================================================================================================== */ /* ================ R_SYSTEM ================ */ /* =========================================================================================================================== */ @@ -27092,6 +24316,12 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure /* ====================================================== GPTCKDIVCR ======================================================= */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Pos (0UL) /*!< GPTCKDIV (Bit 0) */ #define R_SYSTEM_GPTCKDIVCR_GPTCKDIV_Msk (0x7UL) /*!< GPTCKDIV (Bitfield-Mask: 0x07) */ +/* ===================================================== USB60CKDIVCR ====================================================== */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Pos (0UL) /*!< USB60CKDIV (Bit 0) */ + #define R_SYSTEM_USB60CKDIVCR_USB60CKDIV_Msk (0x7UL) /*!< USB60CKDIV (Bitfield-Mask: 0x07) */ +/* ====================================================== CECCKDIVCR ======================================================= */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Pos (0UL) /*!< CECCKDIV (Bit 0) */ + #define R_SYSTEM_CECCKDIVCR_CECCKDIV_Msk (0x7UL) /*!< CECCKDIV (Bitfield-Mask: 0x07) */ /* ====================================================== IICCKDIVCR ======================================================= */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Pos (0UL) /*!< IICCKDIV (Bit 0) */ #define R_SYSTEM_IICCKDIVCR_IICCKDIV_Msk (0x7UL) /*!< IICCKDIV (Bitfield-Mask: 0x07) */ @@ -27130,6 +24360,20 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_GPTCKCR_GPTCKSREQ_Msk (0x40UL) /*!< GPTCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Pos (7UL) /*!< GPTCKSRDY (Bit 7) */ #define R_SYSTEM_GPTCKCR_GPTCKSRDY_Msk (0x80UL) /*!< GPTCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================= USB60CKCR ======================================================= */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Pos (0UL) /*!< USB60CKSEL (Bit 0) */ + #define R_SYSTEM_USB60CKCR_USB60CKSEL_Msk (0xfUL) /*!< USB60CKSEL (Bitfield-Mask: 0x0f) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Pos (6UL) /*!< USB60CKSREQ (Bit 6) */ + #define R_SYSTEM_USB60CKCR_USB60CKSREQ_Msk (0x40UL) /*!< USB60CKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Pos (7UL) /*!< USB60CKSRDY (Bit 7) */ + #define R_SYSTEM_USB60CKCR_USB60CKSRDY_Msk (0x80UL) /*!< USB60CKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== CECCKCR ======================================================== */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Pos (0UL) /*!< CECCKSEL (Bit 0) */ + #define R_SYSTEM_CECCKCR_CECCKSEL_Msk (0x7UL) /*!< CECCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Pos (6UL) /*!< CECCKSREQ (Bit 6) */ + #define R_SYSTEM_CECCKCR_CECCKSREQ_Msk (0x40UL) /*!< CECCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Pos (7UL) /*!< CECCKSRDY (Bit 7) */ + #define R_SYSTEM_CECCKCR_CECCKSRDY_Msk (0x80UL) /*!< CECCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================== IICCKCR ======================================================== */ #define R_SYSTEM_IICCKCR_IICCKSEL_Pos (0UL) /*!< IICCKSEL (Bit 0) */ #define R_SYSTEM_IICCKCR_IICCKSEL_Msk (0x7UL) /*!< IICCKSEL (Bitfield-Mask: 0x07) */ @@ -27137,6 +24381,13 @@ typedef struct /*!< (@ 0x407FC000) R_FLAD Structure #define R_SYSTEM_IICCKCR_IICCKSREQ_Msk (0x40UL) /*!< IICCKSREQ (Bitfield-Mask: 0x01) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Pos (7UL) /*!< IICCKSRDY (Bit 7) */ #define R_SYSTEM_IICCKCR_IICCKSRDY_Msk (0x80UL) /*!< IICCKSRDY (Bitfield-Mask: 0x01) */ +/* ======================================================== I3CCKCR ======================================================== */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Pos (0UL) /*!< I3CCKSEL (Bit 0) */ + #define R_SYSTEM_I3CCKCR_I3CCKSEL_Msk (0x7UL) /*!< I3CCKSEL (Bitfield-Mask: 0x07) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Pos (6UL) /*!< I3CCKSREQ (Bit 6) */ + #define R_SYSTEM_I3CCKCR_I3CCKSREQ_Msk (0x40UL) /*!< I3CCKSREQ (Bitfield-Mask: 0x01) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Pos (7UL) /*!< I3CCKSRDY (Bit 7) */ + #define R_SYSTEM_I3CCKCR_I3CCKSRDY_Msk (0x80UL) /*!< I3CCKSRDY (Bitfield-Mask: 0x01) */ /* ======================================================= SNZREQCR1 ======================================================= */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Pos (0UL) /*!< SNZREQEN0 (Bit 0) */ #define R_SYSTEM_SNZREQCR1_SNZREQEN0_Msk (0x1UL) /*!< SNZREQEN0 (Bitfield-Mask: 0x01) */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c index 2eba223db..ecaa49651 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.c @@ -116,7 +116,15 @@ #endif #endif #endif - +#if BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ + #define BSP_CLOCKS_USB60_CLOCK_DIV_1 (0) // Divide USB source clock by 1 + #define BSP_CLOCKS_USB60_CLOCK_DIV_2 (1) // Divide USB source clock by 2 + #define BSP_CLOCKS_USB60_CLOCK_DIV_3 (5) // Divide USB source clock by 3 + #define BSP_CLOCKS_USB60_CLOCK_DIV_4 (2) // Divide USB source clock by 4 + #define BSP_CLOCKS_USB60_CLOCK_DIV_5 (6) // Divide USB source clock by 5 + #define BSP_CLOCKS_USB60_CLOCK_DIV_6 (3) // Divide USB source clock by 6 + #define BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) // Divide USB source clock by 8 +#endif /* BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ*/ /* Choose the value to write to FLLCR2 (if applicable). */ #if BSP_PRV_HOCO_USE_FLL #if 1U == BSP_CFG_HOCO_FREQUENCY @@ -267,6 +275,24 @@ BSP_PRV_PLLCCR2_PLL_DIV_Q_BIT) | \ (BSP_CFG_PLODIVP & BSP_PRV_PLLCCR2_PLL_DIV_MASK)) #endif + #if (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) + #if BSP_CLOCKS_SOURCE_CLOCK_SUBCLOCK == BSP_CFG_PLL_SOURCE + #define BSP_PRV_PLL_USED (1) + #else + #define BSP_PRV_PLL_USED (0) + #endif + + #define BSP_PRV_PLLCCR_PLLMUL_MASK (0xFFU) // PLLMUL is 8 bits wide + #define BSP_PRV_PLLCCR_PLLMUL_BIT (8) // PLLMUL starts at bit 8 + #define BSP_PRV_PLSET_MASK (0x01U) // PLSET is 1 bit wide + #define BSP_PRV_PLSET_BIT (6) // PLSET starts at bit 6 + #define BSP_PRV_PLLCCR_RESET (0x0008U) // Bit 3 must be written as 1 + #define BSP_PRV_PLLCCR (((BSP_CFG_PLL_MUL & BSP_PRV_PLLCCR_PLLMUL_MASK) << \ + BSP_PRV_PLLCCR_PLLMUL_BIT) | \ + ((BSP_CFG_PLSET & BSP_PRV_PLSET_MASK) << \ + BSP_PRV_PLSET_BIT) | \ + BSP_PRV_PLLCCR_RESET + #endif #endif #if BSP_FEATURE_CGC_HAS_PLL2 @@ -338,13 +364,15 @@ #define BSP_PRV_MAIN_OSC_USED (1) #elif defined(BSP_CFG_IICCLK_SOURCE) && (BSP_CFG_IICCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) #define BSP_PRV_MAIN_OSC_USED (1) +#elif defined(BSP_CFG_CECCLK_SOURCE) && (BSP_CFG_CECCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) + #define BSP_PRV_MAIN_OSC_USED (1) #elif defined(BSP_CFG_I3CCLK_SOURCE) && (BSP_CFG_I3CCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) #define BSP_PRV_MAIN_OSC_USED (1) #elif defined(BSP_CFG_ADCCLK_SOURCE) && (BSP_CFG_ADCCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) #define BSP_PRV_MAIN_OSC_USED (1) #elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) #define BSP_PRV_MAIN_OSC_USED (1) -#elif defined(BSP_CFG_UHSCLK_SOURCE) && (BSP_CFG_UHSCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) +#elif defined(BSP_CFG_U60CLK_SOURCE) && (BSP_CFG_U60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) #define BSP_PRV_MAIN_OSC_USED (1) #elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC) #define BSP_PRV_MAIN_OSC_USED (1) @@ -352,7 +380,7 @@ #define BSP_PRV_MAIN_OSC_USED (0) #endif -/* All clocks with configurable source can use HOCO except the I3CCLK. */ +/* All clocks with configurable source can use HOCO except the CECCLK and I3CCLK. */ #if (BSP_CFG_CLOCK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) #define BSP_PRV_HOCO_USED (1) #define BSP_PRV_STABILIZE_HOCO (1) @@ -383,7 +411,7 @@ #define BSP_PRV_HOCO_USED (1) #elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) #define BSP_PRV_HOCO_USED (1) -#elif defined(BSP_CFG_UHSCLK_SOURCE) && (BSP_CFG_UHSCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) +#elif defined(BSP_CFG_U60CLK_SOURCE) && (BSP_CFG_U60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) #define BSP_PRV_HOCO_USED (1) #elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_HOCO) #define BSP_PRV_HOCO_USED (1) @@ -418,7 +446,7 @@ #define BSP_PRV_MOCO_USED (1) #elif defined(BSP_CFG_LCDCLK_SOURCE) && (BSP_CFG_LCDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) #define BSP_PRV_MOCO_USED (1) -#elif defined(BSP_CFG_UHSCLK_SOURCE) && (BSP_CFG_UHSCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) +#elif defined(BSP_CFG_U60CLK_SOURCE) && (BSP_CFG_U60CLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) #define BSP_PRV_MOCO_USED (1) #elif defined(BSP_CFG_OCTA_SOURCE) && (BSP_CFG_OCTA_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MOCO) #define BSP_PRV_MOCO_USED (1) @@ -476,8 +504,10 @@ (BSP_FEATURE_BSP_HAS_SPI_CLOCK && (BSP_CFG_SPICLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ (BSP_FEATURE_BSP_HAS_GPT_CLOCK && (BSP_CFG_GPTCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ (BSP_FEATURE_BSP_HAS_IIC_CLOCK && (BSP_CFG_IICCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_BSP_HAS_CEC_CLOCK && (BSP_CFG_CECCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ (BSP_FEATURE_BSP_HAS_I3C_CLOCK && (BSP_CFG_I3CCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ (BSP_FEATURE_BSP_HAS_ADC_CLOCK && (BSP_CFG_ADCCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ + (BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ && (BSP_CFG_U60CK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) || \ (BSP_FEATURE_BSP_HAS_LCD_CLOCK && (BSP_CFG_LCDCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED)) #define BSP_PRV_HAS_ENABLED_PERIPHERAL_CLOCKS (1U) @@ -1132,6 +1162,8 @@ static void bsp_clock_freq_var_init (void) g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = BSP_CFG_PLL1P_FREQUENCY_HZ; g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1Q] = BSP_CFG_PLL1Q_FREQUENCY_HZ; g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL1R] = BSP_CFG_PLL1R_FREQUENCY_HZ; + #elif (4U == BSP_FEATURE_CGC_PLLCCR_TYPE) + g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = (g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U; #else g_clock_freq[BSP_CLOCKS_SOURCE_CLOCK_PLL] = ((g_clock_freq[BSP_CFG_PLL_SOURCE] * (BSP_CFG_PLL_MUL + 1U)) >> 1U) >> BSP_CFG_PLL_DIV; @@ -1583,6 +1615,11 @@ void bsp_clock_init (void) bsp_peripheral_clock_set(&R_SYSTEM->IICCKCR, &R_SYSTEM->IICCKDIVCR, BSP_CFG_IICCLK_DIV, BSP_CFG_IICCLK_SOURCE); #endif + /* Set the CEC clock if it exists on the MCU */ +#if BSP_FEATURE_BSP_HAS_CEC_CLOCK && (BSP_CFG_CECCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->CECCKCR, &R_SYSTEM->CECCKDIVCR, BSP_CFG_CECCLK_DIV, BSP_CFG_CECCLK_SOURCE); +#endif + /* Set the I3C clock if it exists on the MCU */ #if BSP_FEATURE_BSP_HAS_I3C_CLOCK && (BSP_CFG_I3CCLK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) bsp_peripheral_clock_set(&R_SYSTEM->I3CCKCR, &R_SYSTEM->I3CCKDIVCR, BSP_CFG_I3CCLK_DIV, BSP_CFG_I3CCLK_SOURCE); @@ -1599,8 +1636,8 @@ void bsp_clock_init (void) #endif /* Set the USB-HS clock if it exists on the MCU */ -#if BSP_FEATURE_BSP_HAS_USBHS_CLOCK && (BSP_CFG_UHSCK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) - bsp_peripheral_clock_set(&R_SYSTEM->USBHSCKCR, &R_SYSTEM->USBHSCKDIVCR, BSP_CFG_UHSCK_DIV, BSP_CFG_UHSCK_SOURCE); +#if BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ && (BSP_CFG_U60CK_SOURCE != BSP_CLOCKS_CLOCK_DISABLED) + bsp_peripheral_clock_set(&R_SYSTEM->USB60CKCR, &R_SYSTEM->USB60CKDIVCR, BSP_CFG_U60CK_DIV, BSP_CFG_U60CK_SOURCE); #endif /* Lock CGC and LPM protection registers. */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h index b4a8fbebf..684aa9603 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_clocks.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_clocks.h @@ -61,7 +61,10 @@ FSP_HEADER * - When the PLL only accepts the main oscillator as a source and XTAL is not used */ #if BSP_FEATURE_CGC_HAS_PLL && !BSP_CFG_USE_LOW_VOLTAGE_MODE && \ - !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && !BSP_CLOCK_CFG_MAIN_OSC_POPULATED) + !((1U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ + (3U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ + (4U != BSP_FEATURE_CGC_PLLCCR_TYPE) && \ + !BSP_CLOCK_CFG_MAIN_OSC_POPULATED) #define BSP_PRV_PLL_SUPPORTED (1) #if BSP_FEATURE_CGC_HAS_PLL2 #define BSP_PRV_PLL2_SUPPORTED (1) @@ -169,14 +172,14 @@ FSP_HEADER #define BSP_CLOCKS_USB_CLOCK_DIV_6 (3) // Divide USB source clock by 6 #define BSP_CLOCKS_USB_CLOCK_DIV_8 (4) // Divide USB source clock by 8 -/* USBHS clock divider options. */ -#define BSP_CLOCKS_USBHS_CLOCK_DIV_1 (0) // Divide USBHS source clock by 1 -#define BSP_CLOCKS_USBHS_CLOCK_DIV_2 (1) // Divide USBHS source clock by 2 -#define BSP_CLOCKS_USBHS_CLOCK_DIV_3 (5) // Divide USBHS source clock by 3 -#define BSP_CLOCKS_USBHS_CLOCK_DIV_4 (2) // Divide USBHS source clock by 4 -#define BSP_CLOCKS_USBHS_CLOCK_DIV_5 (6) // Divide USBHS source clock by 5 -#define BSP_CLOCKS_USBHS_CLOCK_DIV_6 (3) // Divide USBHS source clock by 6 -#define BSP_CLOCKS_USBHS_CLOCK_DIV_8 (4) // Divide USBHS source clock by 8 +/* USB60 clock divider options. */ +#define BSP_CLOCKS_USB60_CLOCK_DIV_1 (0) // Divide USB60 source clock by 1 +#define BSP_CLOCKS_USB60_CLOCK_DIV_2 (1) // Divide USB60 source clock by 2 +#define BSP_CLOCKS_USB60_CLOCK_DIV_3 (5) // Divide USB60 source clock by 3 +#define BSP_CLOCKS_USB60_CLOCK_DIV_4 (2) // Divide USB60 source clock by 4 +#define BSP_CLOCKS_USB60_CLOCK_DIV_5 (6) // Divide USB60 source clock by 5 +#define BSP_CLOCKS_USB60_CLOCK_DIV_6 (3) // Divide USB66 source clock by 6 +#define BSP_CLOCKS_USB60_CLOCK_DIV_8 (4) // Divide USB60 source clock by 8 /* GLCD clock divider options. */ #define BSP_CLOCKS_LCD_CLOCK_DIV_1 (0) // Divide LCD source clock by 1 @@ -197,7 +200,9 @@ FSP_HEADER /* CANFD clock divider options. */ #define BSP_CLOCKS_CANFD_CLOCK_DIV_1 (0) // Divide CANFD source clock by 1 #define BSP_CLOCKS_CANFD_CLOCK_DIV_2 (1) // Divide CANFD source clock by 2 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_3 (5) // Divide CANFD source clock by 3 #define BSP_CLOCKS_CANFD_CLOCK_DIV_4 (2) // Divide CANFD source clock by 4 +#define BSP_CLOCKS_CANFD_CLOCK_DIV_5 (6) // Divide CANFD source clock by 5 #define BSP_CLOCKS_CANFD_CLOCK_DIV_6 (3) // Divide CANFD source clock by 6 #define BSP_CLOCKS_CANFD_CLOCK_DIV_8 (4) // Divide CANFD source clock by 8 @@ -242,6 +247,10 @@ FSP_HEADER #define BSP_CLOCKS_IIC_CLOCK_DIV_6 (3) // Divide IIC source clock by 6 #define BSP_CLOCKS_IIC_CLOCK_DIV_8 (4) // Divide IIC source clock by 8 +/* CEC clock divider options. */ +#define BSP_CLOCKS_CEC_CLOCK_DIV_1 (0) // Divide CEC source clock by 1 +#define BSP_CLOCKS_CEC_CLOCK_DIV_2 (1) // Divide CEC source clock by 2 + /* I3C clock divider options. */ #define BSP_CLOCKS_I3C_CLOCK_DIV_1 (0) // Divide I3C source clock by 1 #define BSP_CLOCKS_I3C_CLOCK_DIV_2 (1) // Divide I3C source clock by 2 @@ -1044,6 +1053,8 @@ typedef enum e_cgc_pll_mul CGC_PLL_MUL_180_33 = BSP_CLOCKS_PLL_MUL(180U, 33U), ///< PLL multiplier of 180.33 CGC_PLL_MUL_180_5 = BSP_CLOCKS_PLL_MUL(180U, 50U), ///< PLL multiplier of 180.50 CGC_PLL_MUL_180_66 = BSP_CLOCKS_PLL_MUL(180U, 66U), ///< PLL multiplier of 180.66 + CGC_PLL_MUL_732_0 = BSP_CLOCKS_PLL_MUL(732U, 0U), ///< PLL multiplier of 732.00 + CGC_PLL_MUL_781_0 = BSP_CLOCKS_PLL_MUL(781U, 0U), ///< PLL multiplier of 781.00 } cgc_pll_mul_t; /*********************************************************************************************************************** diff --git a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h index b666f4a9e..f152ba484 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h +++ b/ra/fsp/src/bsp/mcu/all/bsp_module_stop.h @@ -90,6 +90,8 @@ FSP_HEADER #define BSP_MSTP_BIT_FSP_IP_KEY(channel) (1U << 4U); #define BSP_MSTP_REG_FSP_IP_POEG(channel) R_MSTP->MSTPCRD #define BSP_MSTP_BIT_FSP_IP_POEG(channel) (1U << (14U - channel)); + #define BSP_MSTP_REG_FSP_IP_ULPT(channel) R_MSTP->MSTPCRE + #define BSP_MSTP_BIT_FSP_IP_ULPT(channel) (1U << (9U - channel)); #else #define BSP_MSTP_REG_FSP_IP_GPT(channel) R_MSTP->MSTPCRE #define BSP_MSTP_BIT_FSP_IP_GPT(channel) (1U << (31 - channel)); diff --git a/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c b/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c index e8d64246e..f6fac448e 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_rom_registers.c @@ -62,6 +62,27 @@ #if !BSP_CFG_BOOT_IMAGE + #if BSP_FEATURE_BSP_HAS_OSIS_REG == 1 + +/** ID code definitions defined here. */ +BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) = +{ + BSP_CFG_ID_CODE_LONG_1, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, + #endif + BSP_CFG_ID_CODE_LONG_2, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, + #endif + BSP_CFG_ID_CODE_LONG_3, + #if BSP_FEATURE_BSP_OSIS_PADDING + 0xFFFFFFFFU, + #endif + BSP_CFG_ID_CODE_LONG_4 +}; + #endif + #if 33U != __CORTEX_M && 85U != __CORTEX_M // NOLINT(readability-magic-numbers) /** ROM registers defined here. Some have masks to make sure reserved bits are set appropriately. */ @@ -84,23 +105,22 @@ BSP_DONT_REMOVE static const uint32_t g_bsp_rom_registers[] BSP_PLACE_IN_SECTION (uint32_t) BSP_ROM_REG_MPU_CONTROL_SETTING }; -/** ID code definitions defined here. */ -BSP_DONT_REMOVE static const uint32_t g_bsp_id_codes[] BSP_PLACE_IN_SECTION (BSP_SECTION_ID_CODE) = -{ - BSP_CFG_ID_CODE_LONG_1, - #if BSP_FEATURE_BSP_OSIS_PADDING - 0xFFFFFFFFU, - #endif - BSP_CFG_ID_CODE_LONG_2, - #if BSP_FEATURE_BSP_OSIS_PADDING - 0xFFFFFFFFU, - #endif - BSP_CFG_ID_CODE_LONG_3, - #if BSP_FEATURE_BSP_OSIS_PADDING - 0xFFFFFFFFU, - #endif - BSP_CFG_ID_CODE_LONG_4 -}; + #elif BSP_FEATURE_BSP_HAS_OSIS_REG == 1 + + BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs0") g_bsp_rom_ofs0 = + BSP_CFG_ROM_REG_OFS0; + + BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_sas") g_bsp_rom_sas = + 0xFFFFFFFF; + + BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_ofs1_sec") g_bsp_rom_ofs1 = + BSP_ROM_REG_OFS1_SETTING; + + BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_bps_sec0") g_bsp_rom_bps0 = + BSP_CFG_ROM_REG_BPS0; + + BSP_DONT_REMOVE static const uint32_t BSP_PLACE_IN_SECTION(".option_setting_pbps_sec0") g_bsp_rom_pbps0 = + BSP_CFG_ROM_REG_PBPS0; #else /* CM33 parts */ diff --git a/ra/fsp/src/bsp/mcu/all/bsp_security.c b/ra/fsp/src/bsp/mcu/all/bsp_security.c index 4696a5718..237efc404 100644 --- a/ra/fsp/src/bsp/mcu/all/bsp_security.c +++ b/ra/fsp/src/bsp/mcu/all/bsp_security.c @@ -55,37 +55,9 @@ typedef BSP_CMSE_NONSECURE_CALL void (*volatile bsp_nonsecure_func_t)(void); #endif #if defined(__IAR_SYSTEMS_ICC__) && BSP_TZ_SECURE_BUILD - #pragma section=".tz_flash_nsc_start" - #pragma section=".tz_ram_nsc_start" - #pragma section=".tz_ram_ns_start" - #pragma section=".tz_data_flash_ns_start" - #pragma section=".tz_sdram_ns_start" - #pragma section=".tz_qspi_flash_ns_start" - #pragma section=".tz_ospi_device_0_ns_start" - #pragma section=".tz_ospi_device_1_ns_start" - -/* &__tz__C is the address of the non-secure callable section. Must assign value to this variable or - * linker will give error. */ - -/* &__tz__N is the start address of the non-secure region. */ -BSP_DONT_REMOVE void const * const __tz_FLASH_C BSP_ALIGN_VARIABLE(1024) @".tz_flash_nsc_start" = 0; -BSP_DONT_REMOVE void * __tz_RAM_C BSP_ALIGN_VARIABLE(1024) @".tz_ram_nsc_start"; -BSP_DONT_REMOVE void * __tz_RAM_N BSP_ALIGN_VARIABLE(8192) @".tz_ram_ns_start"; -BSP_DONT_REMOVE void * __tz_DATA_FLASH_N BSP_ALIGN_VARIABLE(1024) @".tz_data_flash_ns_start"; - - #if BSP_FEATURE_SDRAM_START_ADDRESS -BSP_DONT_REMOVE void * __tz_SDRAM_N @".tz_sdram_ns_start"; - #endif -BSP_DONT_REMOVE void * __tz_QSPI_FLASH_N @".tz_qspi_flash_ns_start"; - #if BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS -BSP_DONT_REMOVE void * __tz_OSPI_DEVICE_0_N @".tz_ospi_device_0_ns_start"; - #endif - #if BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS -BSP_DONT_REMOVE void * __tz_OSPI_DEVICE_1_N @".tz_ospi_device_1_ns_start"; - #endif + #pragma section=".tz_flash_ns_start" -extern void const * const __tz_FLASH_N; -BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = (uint32_t *) &__tz_FLASH_N; +BSP_DONT_REMOVE uint32_t const * const gp_start_of_nonsecure_flash = (uint32_t *) __section_begin(".tz_flash_ns_start"); #elif defined(__ARMCC_VERSION) #if BSP_FEATURE_BSP_HAS_ITCM extern const uint32_t Image$$__tz_ITCM_N$$Base; diff --git a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h index 5ba6f7d3b..cb4c0261e 100644 --- a/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2a1/bsp_feature.h @@ -90,11 +90,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,13 +108,14 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (1) #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) @@ -125,6 +127,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (1U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (1) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) @@ -144,6 +147,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (1U) #define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_ICLK) @@ -171,9 +175,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. #define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (1U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz @@ -205,7 +209,6 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (4U) @@ -218,6 +221,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (1U) #define BSP_FEATURE_DAC8_MAX_CHANNELS (2U) +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (1U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (1U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -286,6 +290,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB8F00FFU) +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE @@ -307,16 +312,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) #define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) @@ -367,6 +380,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) diff --git a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h index 8a20f8588..dd0228208 100644 --- a/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2e1/bsp_feature.h @@ -90,11 +90,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (1U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,15 +108,16 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (1) #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) @@ -125,6 +127,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (1U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (1) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) @@ -142,6 +145,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) // Feature not available on this MCU #define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_ICLK) // Feature not available on this MCU @@ -163,15 +167,15 @@ #define BSP_FEATURE_CGC_HAS_PCLKD (1U) #define BSP_FEATURE_CGC_HAS_PCLKE (0U) #define BSP_FEATURE_CGC_HAS_PLL (0U) -#define BSP_FEATURE_CGC_HAS_PLL2 (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_HAS_PLL2 (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_SOPCCR (1U) #define BSP_FEATURE_CGC_HAS_SOSC (1U) -#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (2000000U) @@ -203,7 +207,6 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (5U) @@ -216,6 +219,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) // Feature not available on this MCU #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) // Feature not available on this MCU #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (0U) // Feature not available on this MCU @@ -284,6 +288,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0xF38F00FFU) +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE @@ -305,16 +310,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STCONR (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1) @@ -365,6 +378,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SPI_HAS_SPCR3 (0) // Feature not available on this MCU diff --git a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h index 3e4c8930b..4be9e01ec 100644 --- a/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2e2/bsp_feature.h @@ -90,11 +90,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (1U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,15 +108,16 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (1) #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) -#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL_ALT (0U) #define BSP_FEATURE_BSP_MCU_INFO_POINTER_LOCATION (0U) @@ -125,6 +127,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (1U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (1) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) @@ -142,6 +145,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) // Feature not available on this MCU #define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_ICLK) // Feature not available on this MCU @@ -163,15 +167,15 @@ #define BSP_FEATURE_CGC_HAS_PCLKD (1U) #define BSP_FEATURE_CGC_HAS_PCLKE (0U) #define BSP_FEATURE_CGC_HAS_PLL (0U) -#define BSP_FEATURE_CGC_HAS_PLL2 (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_HAS_PLL2 (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_SOPCCR (1U) #define BSP_FEATURE_CGC_HAS_SOSC (0) -#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0) // Feature not available on this MCU +#define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0) // Feature not available on this MCU #define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (3U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) // Feature not available on this MCU +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (3U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (2000000U) @@ -203,7 +207,6 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0) @@ -216,6 +219,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) // Feature not available on this MCU #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) // Feature not available on this MCU #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (0U) // Feature not available on this MCU @@ -284,6 +288,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (0) // Feature not available on this MCU #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x0FU) #define BSP_FEATURE_ICU_WUPEN_MASK (0x700F00FFU) +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (3U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (1U) @@ -305,16 +310,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_HAS_STCONR (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000001FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x700200FFU) +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1) @@ -365,6 +378,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SPI_HAS_SPCR3 (0) // Feature not available on this MCU diff --git a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h index 108f53a1c..eba16b04b 100644 --- a/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra2l1/bsp_feature.h @@ -90,11 +90,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (1) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (1U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (1U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,13 +108,14 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (1) #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) @@ -125,6 +127,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (1U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (1) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) @@ -142,6 +145,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (1U) #define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_ICLK) @@ -169,9 +173,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. #define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (2000000U) // This MCU does have Low Speed Mode, up to 2 MHz @@ -203,7 +207,6 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (4U) @@ -211,11 +214,12 @@ #define BSP_FEATURE_CTSU_HAS_TXVSEL (1) #define BSP_FEATURE_CTSU_VERSION (2) -#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU -#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_CHARGEPUMP (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_DA_AD_SYNCHRONIZE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (1U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -284,6 +288,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0xF38F00FFU) +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE @@ -305,16 +310,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) #define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x738200FFU) +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) @@ -365,6 +378,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKB) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h index bf0df76d5..8b4ac4716 100644 --- a/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4e1/bsp_feature.h @@ -94,11 +94,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,13 +112,14 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) @@ -129,6 +131,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (6U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (0U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) @@ -146,6 +149,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) #define BSP_FEATURE_CAN_CLOCK (0U) @@ -173,9 +177,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // This MCU has an additional register to enable write access for SRAMWTSC. #define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz @@ -207,7 +211,6 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (1) #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0U) // Feature not available on this MCU @@ -220,6 +223,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x01U) #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -288,6 +292,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x23FFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0D23FFULL) // Note there is another WUPEN1 register +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE @@ -309,16 +314,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0x1303F3U) #define BSP_FEATURE_LPM_DPSIER_MASK (0x0D1F03F3U) +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) #define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) @@ -369,6 +382,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) diff --git a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h index d4d1750cc..b8c1f4c53 100644 --- a/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m1/bsp_feature.h @@ -90,11 +90,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,13 +108,14 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) @@ -125,6 +127,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (1U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (1) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) @@ -144,6 +147,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (1U) #define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_PCLKA) @@ -171,9 +175,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. #define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (1U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz @@ -205,7 +209,6 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (1) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (5U) @@ -218,6 +221,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0U) #define BSP_FEATURE_DAC8_MAX_CHANNELS (2U) +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0U) // Do not need to select ADC Unit on this MCU #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (1U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -286,6 +290,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xDFFFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB9FDFFFU) +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE @@ -307,16 +312,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) #define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7382DFFFU) +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) @@ -367,6 +380,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (1U) #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (1U) #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (38U) +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) diff --git a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h index 9bd5ab390..2b1ba0e29 100644 --- a/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m2/bsp_feature.h @@ -94,11 +94,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,13 +112,14 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA4M2 there are specific registers for configuring the USB clock. -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) @@ -129,6 +131,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (8U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (0U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) @@ -146,6 +149,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) #define BSP_FEATURE_CAN_CLOCK (0U) @@ -173,9 +177,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // On the RA4M2 there is another register to enable write access for SRAMWTSC. #define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz @@ -207,7 +211,6 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (1) #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (2U) @@ -220,6 +223,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x01U) #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -288,6 +292,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE @@ -309,16 +314,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13DFF3U) #define BSP_FEATURE_LPM_DPSIER_MASK (0x0D1FDFF3U) +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) #define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000019FU) // note there is another SNZEDCR1 register -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000019FU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) @@ -369,6 +382,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) diff --git a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h index 4d88efe5d..8a06f7a97 100644 --- a/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4m3/bsp_feature.h @@ -94,11 +94,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,13 +112,14 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA4M3 there are specific registers for configuring the USB clock. -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) @@ -129,6 +131,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (9U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (0U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) @@ -146,6 +149,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) #define BSP_FEATURE_CAN_CLOCK (0U) @@ -173,9 +177,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // On the RA4M3 there is another register to enable write access for SRAMWTSC. #define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz @@ -207,7 +211,6 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (1) #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U) @@ -220,6 +223,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02U) #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -288,6 +292,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE @@ -309,16 +314,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13FFFFU) #define BSP_FEATURE_LPM_DPSIER_MASK (0x0D1FFFFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) #define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note there is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) @@ -369,6 +382,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) diff --git a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h index d8a6b4f18..460a5340d 100644 --- a/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra4w1/bsp_feature.h @@ -90,11 +90,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -107,13 +108,14 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) @@ -125,6 +127,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFF8FFFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (12U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (1U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (1) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) @@ -144,6 +147,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (1U) #define BSP_FEATURE_CAN_CLOCK (FSP_PRIV_CLOCK_PCLKA) @@ -171,9 +175,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. #define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (1U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (1U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_16) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (100U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz @@ -205,7 +209,6 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (1) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (5U) @@ -218,6 +221,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0U) #define BSP_FEATURE_DAC8_MAX_CHANNELS (2U) +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0U) #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (1U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -286,6 +290,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xCBDFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB97CADFU) +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE @@ -307,16 +312,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0) // Feature not available on this MCU #define BSP_FEATURE_LPM_DPSIER_MASK (0) // Feature not available on this MCU +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (0U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) #define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000009FU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7382CADFU) +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (0U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) @@ -367,6 +380,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0U) #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0U) #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (54U) +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h index 03d6b58a6..b76b7c29d 100644 --- a/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6e1/bsp_feature.h @@ -94,11 +94,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,13 +112,14 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) @@ -129,6 +131,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (8U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (0U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) @@ -146,6 +149,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) #define BSP_FEATURE_CAN_CLOCK (0U) @@ -173,9 +177,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // This MCU has another register to enable write access for SRAMWTSC. #define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz @@ -207,7 +211,6 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (1) #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0) // Feature not available on this MCU @@ -220,6 +223,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x01U) #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -288,6 +292,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE @@ -309,16 +314,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13DFF3U) #define BSP_FEATURE_LPM_DPSIER_MASK (0x0D1FDFF3U) +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) #define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000019FU) // note there is another SNZEDCR1 register -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x0000019FU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) @@ -341,8 +354,8 @@ #define BSP_FEATURE_OPAMP_TRIM_CAPABLE (0U) #define BSP_FEATURE_OPAMP_VARIANT_CHANNEL_MASK (0U) -#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x68000000U) -#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x70000000U) +#define BSP_FEATURE_OSPI_DEVICE_0_START_ADDRESS (0x0U) +#define BSP_FEATURE_OSPI_DEVICE_1_START_ADDRESS (0x0U) #define BSP_FEATURE_POEG_CHANNEL_MASK (0xFU) @@ -369,6 +382,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) diff --git a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h index b9accb869..956fda295 100644 --- a/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m1/bsp_feature.h @@ -94,11 +94,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,13 +112,14 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) @@ -129,6 +131,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (1U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) @@ -148,6 +151,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) #define BSP_FEATURE_CAN_CLOCK (0U) @@ -175,9 +179,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. #define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (2U) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (2U) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) ///< This MCU does have Low Speed Mode, up to 1MHz @@ -209,8 +213,7 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (1) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (1) -#define BSP_FEATURE_CRYPTO_HAS_SCE9 (1) +#define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (2U) #define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (2U) @@ -222,6 +225,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02U) #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -290,6 +294,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x3FFFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB4FFFFFU) +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE @@ -311,16 +316,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (1U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00133FFFU) #define BSP_FEATURE_LPM_DPSIER_MASK (0x051F3FFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) #define BSP_FEATURE_LPM_HAS_STCONR (1U) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) @@ -371,6 +384,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h index ec0a108a3..0fc3a5720 100644 --- a/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m2/bsp_feature.h @@ -94,11 +94,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,13 +112,14 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) @@ -129,6 +131,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (1U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) @@ -148,6 +151,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) #define BSP_FEATURE_CAN_CLOCK (0U) @@ -175,9 +179,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. #define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (2U) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (2U) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz @@ -209,8 +213,7 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (1) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (1) -#define BSP_FEATURE_CRYPTO_HAS_SCE9 (1) +#define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U) #define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U) @@ -222,6 +225,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02U) #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -290,6 +294,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0xFB4FFFFFU) +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE @@ -311,16 +316,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (1U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00133FFFU) #define BSP_FEATURE_LPM_DPSIER_MASK (0x051F3FFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) #define BSP_FEATURE_LPM_HAS_STCONR (1U) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) @@ -371,6 +384,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h index 6fa976c31..793e305da 100644 --- a/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m3/bsp_feature.h @@ -94,11 +94,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,13 +112,14 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) @@ -129,6 +131,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (1U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) @@ -148,6 +151,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) #define BSP_FEATURE_CAN_CLOCK (0U) @@ -175,9 +179,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. #define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (2U) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (2U) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz @@ -209,8 +213,7 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (1) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (1) -#define BSP_FEATURE_CRYPTO_HAS_SCE9 (1) +#define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U) #define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (3U) @@ -222,6 +225,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02U) #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -290,6 +294,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0xFF4FFFFFU) +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE @@ -311,16 +316,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (1U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00137FFFU) #define BSP_FEATURE_LPM_DPSIER_MASK (0x071F7FFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) #define BSP_FEATURE_LPM_HAS_STCONR (1U) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7342FFFFU) +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) @@ -371,6 +384,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h index 8bee329b9..b88c829c7 100644 --- a/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m4/bsp_feature.h @@ -94,11 +94,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,13 +112,14 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA6M4 there are specific registers for configuring the USB clock. -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) @@ -129,6 +131,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (9U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (0U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) @@ -146,6 +149,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) #define BSP_FEATURE_CAN_CLOCK (0U) @@ -173,9 +177,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. #define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz @@ -207,7 +211,6 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (1) #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U) @@ -220,6 +223,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02U) #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -288,6 +292,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FB0DFFFFULL) // Note there is another WUPEN1 register +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE @@ -309,16 +314,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13FFFFU) #define BSP_FEATURE_LPM_DPSIER_MASK (0x0D1FFFFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) #define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) @@ -369,6 +382,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) diff --git a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h index 651fa250b..3a3d129cc 100644 --- a/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6m5/bsp_feature.h @@ -94,11 +94,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1) +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (1) #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,13 +112,14 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (1U) // Feature available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (1U) // On the RA6M5 there are specific registers for configuring the USB clock. -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (1U) @@ -129,6 +131,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (12U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (0U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) @@ -146,6 +149,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (BSP_MCU_FEATURE_SET == 'B') #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (2U) +#define BSP_FEATURE_CANFD_NUM_INSTANCES (1U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) #define BSP_FEATURE_CAN_CLOCK (0U) @@ -173,9 +177,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (1U) // On the RA6M5 there is another register to enable write access for SRAMWTSC. #define BSP_FEATURE_CGC_HAS_SRAMWTSC (1U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz @@ -207,7 +211,6 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (1) #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (3U) @@ -220,6 +223,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02U) #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -288,6 +292,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (1U) #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0x7FF0DFFFFULL) // Note there is another WUPEN1 register +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE @@ -309,16 +314,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13FFFFU) #define BSP_FEATURE_LPM_DPSIER_MASK (0x0F1FFFFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (1U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (1U) #define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) -#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register -#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000001FFU) // note there is another SNZEDCR1 register +#define BSP_FEATURE_LPM_SNZREQCR_MASK (0x77300FFFFULL) // note tehre is another SNZEREQCR1 register +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) @@ -369,6 +382,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) diff --git a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h index 7f842c9ef..3d3bbf1ba 100644 --- a/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t1/bsp_feature.h @@ -94,11 +94,12 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (0) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) #define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (0) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (0U) @@ -111,13 +112,14 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (0) // Feature not available on this MCU TODO_CHECK_FEATURE #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (1U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (1U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (0) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (1U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) // On the RA6M4 there is a request bit that must be set before changing USB clock settings. #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) @@ -129,6 +131,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (0U) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (1U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (0U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (1U) @@ -148,6 +151,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (0U) #define BSP_FEATURE_CANFD_LITE (0U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (0U) // Feature not available on this MCU +#define BSP_FEATURE_CANFD_NUM_INSTANCES (0U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) #define BSP_FEATURE_CAN_CLOCK (0U) @@ -175,9 +179,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6M4 there is another register to enable write access for SRAMWTSC. #define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (2U) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (2U) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) ///< This MCU does have Low Speed Mode, up to 1MHz @@ -209,8 +213,7 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (0) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (1) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (1) -#define BSP_FEATURE_CRYPTO_HAS_SCE9 (1) +#define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0) // Feature not available on this MCU #define BSP_FEATURE_CTSU_CTSUCHTRC_REGISTER_COUNT (0) // Feature not available on this MCU @@ -222,6 +225,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0x02U) #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (1U) @@ -290,6 +294,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (0U) #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0x3FFFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0xF04F3FFFU) +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (0U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0) // Feature not available on this MCU TODO_CHECK_FEATURE @@ -311,16 +316,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (1U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0x00131FF3U) #define BSP_FEATURE_LPM_DPSIER_MASK (0x04131FF3U) +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (1U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) #define BSP_FEATURE_LPM_HAS_STCONR (1U) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (0) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000FFU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x70423FFFU) +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (1U) @@ -371,6 +384,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (0U) diff --git a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h index b91921319..c26d8a23a 100644 --- a/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h +++ b/ra/fsp/src/bsp/mcu/ra6t2/bsp_feature.h @@ -94,15 +94,16 @@ #define BSP_FEATURE_BSP_FLASH_PREFETCH_BUFFER (0) #define BSP_FEATURE_BSP_HAS_ADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_CANFD_CLOCK (1U) +#define BSP_FEATURE_BSP_HAS_CEC_CLOCK (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_CLOCK_SUPPLY_TYPEB (0U) #define BSP_FEATURE_BSP_HAS_CODE_SYSTEM_CACHE (1) #define BSP_FEATURE_BSP_HAS_DCDC_REGULATOR (0U) -#define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (1U) +#define BSP_FEATURE_BSP_HAS_DTCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_GPT_CLOCK (1U) // Mutually exclusive with USB60 Clock #define BSP_FEATURE_BSP_HAS_GRAPHICS_DOMAIN (0) #define BSP_FEATURE_BSP_HAS_I3C_CLOCK (0) #define BSP_FEATURE_BSP_HAS_IIC_CLOCK (1U) -#define BSP_FEATURE_BSP_HAS_ITCM (0) // Feature not available on this MCU +#define BSP_FEATURE_BSP_HAS_ITCM (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_LCD_CLOCK (0) #define BSP_FEATURE_BSP_HAS_OCTASPI_CLOCK (0U) #define BSP_FEATURE_BSP_HAS_OFS2 (0) @@ -111,13 +112,14 @@ #define BSP_FEATURE_BSP_HAS_SCE_ON_RA2 (0) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_SCISPI_CLOCK (1) #define BSP_FEATURE_BSP_HAS_SCI_CLOCK (0) +#define BSP_FEATURE_BSP_HAS_SDADC_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SECURITY_MPU (0U) #define BSP_FEATURE_BSP_HAS_SPI_CLOCK (0) #define BSP_FEATURE_BSP_HAS_SP_MON (0U) #define BSP_FEATURE_BSP_HAS_SYRACCR (0U) #define BSP_FEATURE_BSP_HAS_TZFSAR (1) +#define BSP_FEATURE_BSP_HAS_USB60_CLOCK_REQ (0U) // Feature not available on this MCU #define BSP_FEATURE_BSP_HAS_USBCKDIVCR (0U) // Feature not available on this MCU -#define BSP_FEATURE_BSP_HAS_USBHS_CLOCK (0) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_DIV (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_REQ (0U) #define BSP_FEATURE_BSP_HAS_USB_CLOCK_SEL (0U) @@ -129,6 +131,7 @@ #define BSP_FEATURE_BSP_NUM_PMSAR (16U) // 16 due to offset address change from PMSAR2 to PMSAR3 #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_MASK (0xFFFFF9FFU) #define BSP_FEATURE_BSP_OFS1_HOCOFRQ_OFFSET (9U) +#define BSP_FEATURE_BSP_HAS_OSIS_REG (0U) #define BSP_FEATURE_BSP_OFS_HAS_SECURITY_ATTRIBUTION (1U) #define BSP_FEATURE_BSP_OSIS_PADDING (0U) #define BSP_FEATURE_BSP_POWER_CHANGE_MSTP_REQUIRED (0U) @@ -146,6 +149,7 @@ #define BSP_FEATURE_CANFD_FD_SUPPORT (BSP_MCU_FEATURE_SET == 'B') #define BSP_FEATURE_CANFD_LITE (1U) #define BSP_FEATURE_CANFD_NUM_CHANNELS (1U) +#define BSP_FEATURE_CANFD_NUM_INSTANCES (1U) #define BSP_FEATURE_CAN_CHECK_PCLKB_RATIO (0U) #define BSP_FEATURE_CAN_CLOCK (0U) @@ -173,9 +177,9 @@ #define BSP_FEATURE_CGC_HAS_SRAMPRCR2 (0U) // On the RA6T2 there is another register to enable write access for SRAMWTSC. #define BSP_FEATURE_CGC_HAS_SRAMWTSC (0U) // On the RA6T2 there is no SRAMWTSC register #define BSP_FEATURE_CGC_HOCOSF_BEFORE_OPCCR (0U) -#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) -#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) #define BSP_FEATURE_CGC_HOCOWTCR_64MHZ_ONLY (0U) +#define BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE (0) +#define BSP_FEATURE_CGC_HOCOWTCR_VALUE (6U) #define BSP_FEATURE_CGC_ICLK_DIV_RESET (BSP_CLOCKS_SYS_CLOCK_DIV_4) #define BSP_FEATURE_CGC_LOCO_STABILIZATION_MAX_US (61U) #define BSP_FEATURE_CGC_LOW_SPEED_MAX_FREQ_HZ (1000000U) // This MCU does have Low Speed Mode, up to 1MHz @@ -207,7 +211,6 @@ #define BSP_FEATURE_CRYPTO_HAS_SCE5 (0) #define BSP_FEATURE_CRYPTO_HAS_SCE5B (1) #define BSP_FEATURE_CRYPTO_HAS_SCE7 (0) -#define BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS (0) #define BSP_FEATURE_CRYPTO_HAS_SCE9 (0) #define BSP_FEATURE_CTSU_CTSUCHAC_REGISTER_COUNT (0U) // Feature not available on this MCU @@ -220,6 +223,7 @@ #define BSP_FEATURE_DAC8_HAS_REALTIME_MODE (0) // Feature not available on this MCU #define BSP_FEATURE_DAC8_MAX_CHANNELS (0) // Feature not available on this MCU +#define BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK (0U) // Feature not available on this MCU #define BSP_FEATURE_DAC_HAS_CHARGEPUMP (0U) #define BSP_FEATURE_DAC_HAS_DAVREFCR (0U) #define BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE (0U) // Feature not available on this MCU @@ -288,6 +292,7 @@ #define BSP_FEATURE_ICU_HAS_WUPEN1 (0) #define BSP_FEATURE_ICU_IRQ_CHANNELS_MASK (0xFFFFU) #define BSP_FEATURE_ICU_WUPEN_MASK (0xF00FFFFFU) // Note there is another WUPEN1 register +#define BSP_FEATURE_ICU_FIXED_IELSR_COUNT (0U) #define BSP_FEATURE_IIC_BUS_FREE_TIME_MULTIPLIER (5U) #define BSP_FEATURE_IIC_B_FAST_MODE_PLUS (0x03) @@ -309,16 +314,24 @@ #define BSP_FEATURE_LPM_CHANGE_MSTP_REQUIRED (0U) #define BSP_FEATURE_LPM_DPSIEGR_MASK (0x13FFFFU) #define BSP_FEATURE_LPM_DPSIER_MASK (0x13FFFFU) +#define BSP_FEATURE_LPM_HAS_DEEP_SLEEP (0U) #define BSP_FEATURE_LPM_HAS_DEEP_STANDBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY (1U) +#define BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP (0U) +#define BSP_FEATURE_LPM_HAS_LDO_CONTROL (0U) #define BSP_FEATURE_LPM_HAS_LPSCR (0U) +#define BSP_FEATURE_LPM_HAS_PDRAMSCR (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_OPE (0U) #define BSP_FEATURE_LPM_HAS_SBYCR_SSBY (1U) +#define BSP_FEATURE_LPM_HAS_SNOOZE (1U) #define BSP_FEATURE_LPM_HAS_SNZEDCR1 (0U) #define BSP_FEATURE_LPM_HAS_SNZREQCR1 (0U) #define BSP_FEATURE_LPM_HAS_STCONR (0U) #define BSP_FEATURE_LPM_SBYCR_WRITE1_B14 (1U) #define BSP_FEATURE_LPM_SNZEDCR_MASK (0x000000AFU) #define BSP_FEATURE_LPM_SNZREQCR_MASK (0x7002FFFFU) +#define BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED (0U) #define BSP_FEATURE_LVD_HAS_DIGITAL_FILTER (1U) #define BSP_FEATURE_LVD_HAS_LVDLVLR (0U) @@ -369,6 +382,7 @@ #define BSP_FEATURE_SLCDC_HAS_8_TIME_SLICE (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_HAS_INTERNAL_VOLT_GEN (0) // Feature not available on this MCU #define BSP_FEATURE_SLCDC_MAX_NUM_SEG (0) // Feature not available on this MCU +#define BSP_FEATURE_SLCDC_HAS_VL1SEL (0) #define BSP_FEATURE_SPI_CLK (FSP_PRIV_CLOCK_PCLKA) #define BSP_FEATURE_SPI_HAS_SPCR3 (1U) diff --git a/ra/fsp/src/r_canfd/.util/Renesas##HAL Drivers##all##r_canfd####4.2.0.xml.j2 b/ra/fsp/src/r_canfd/.util/Renesas##HAL Drivers##all##r_canfd####4.2.0.xml.j2 new file mode 100644 index 000000000..7ba1b1d79 --- /dev/null +++ b/ra/fsp/src/r_canfd/.util/Renesas##HAL Drivers##all##r_canfd####4.2.0.xml.j2 @@ -0,0 +1,864 @@ +{% macro deref_id(id_prefix,name) %}${{ '{' + id_prefix + '.driver.' + id_name() + '.' + name + '}' }}{% endmacro %} +{% macro id_name() %}{%- if 'r_canfd' == module_variant %}canfd{%- else %}canfdlite{%- endif %}{% endmacro %} +{% macro rx_fifo_properties(id_prefix, index) %} + + + + + + + + + +{% endmacro %} +{% macro global_config(id_prefix, num_fifos) %} + + + + + + + + + + + + + + testInteger("${{ '{' }}{{ id_prefix }}.driver.{{ id_name() }}.rxmb.number{{ '}' }}") && (("${{ '{' }}{{ id_prefix }}.driver.{{ id_name() }}.rxmb.number{{ '}' }}" >= 0) && ("${{ '{' }}{{ id_prefix }}.driver.{{ id_name() }}.rxmb.number{{ '}' }}" <= 32)) + + + +{% for index in range(num_fifos) %}{{ rx_fifo_properties(id_prefix,index) }}{% endfor %} +{% endmacro %} +{% macro global_config_constraints(id_prefix, num_fifos) %} + + (((parseInt("{{deref_id(id_prefix,'rxmb.size')}}".substring("{{id_prefix}}.driver.{{id_name()}}.rxmb.size.".length)) + 12) * parseInt("{{deref_id(id_prefix,'rxmb.number')}}")) +{% for fifo_number in range(num_fifos - 1) %} + ((parseInt("{{deref_id(id_prefix,'rxfifo.'~fifo_number~'.payload')}}".substring("enum.driver.canfd.fifo.payload.".length)) + 12) * parseInt("{{deref_id(id_prefix,'rxfifo.'~fifo_number~'.depth')}}".substring("enum.driver.canfd.fifo.depth.".length)) * ("{{deref_id(id_prefix,'rxfifo.'~fifo_number~'.enable')}}" == "{{id_prefix}}.driver.{{ id_name() }}.rxfifo.{{ fifo_number }}.enable.enabled" ? 1 : 0)) +{% endfor %} + ((parseInt("{{deref_id(id_prefix,'rxfifo.'~(num_fifos-1)~'.payload')}}".substring("enum.driver.canfd.fifo.payload.".length)) + 12) * parseInt("{{deref_id(id_prefix,'rxfifo.'~(num_fifos-1)~'.depth')}}".substring("enum.driver.canfd.fifo.depth.".length)) * ("{{deref_id(id_prefix,'rxfifo.'~(num_fifos-1)~'.enable')}}" == "{{id_prefix}}.driver.{{ id_name() }}.rxfifo.{{ num_fifos - 1 }}.enable.enabled" ? 1 : 0))) <= ${config.bsp.fsp.mcu.canfd.buffer_ram} + + + ("${interface.mcu.feature_set.b}" > "0") || + (("{{deref_id(id_prefix,'rxmb.size')}}" === "{{id_prefix}}.driver.{{ id_name() }}.rxmb.size.8") &&{% for fifo_number in range(num_fifos - 1) %} + ("{{deref_id(id_prefix,'rxfifo.'~fifo_number~'.payload')}}" === "enum.driver.canfd.fifo.payload.8") &&{% endfor %} + ("{{deref_id(id_prefix,'rxfifo.'~(num_fifos-1)~'.payload')}}" === "enum.driver.canfd.fifo.payload.8")) + + + !(("${config.driver.{{ id_name() }}.rxfifo.ipl}" === "_disabled") && + ({% for fifo_number in range(num_fifos - 1) %} + (("{{deref_id(id_prefix,'rxfifo.'~fifo_number~'.int_mode')}}" != "enum.driver.canfd.fifo.int_mode.disabled") && ("{{deref_id(id_prefix,'rxfifo.'~fifo_number~'.enable')}}" === "{{id_prefix}}.driver.{{ id_name() }}.rxfifo.{{fifo_number}}.enable.enabled")) ||{% endfor %} + (("{{deref_id(id_prefix,'rxfifo.'~(num_fifos-1)~'.int_mode')}}" != "enum.driver.canfd.fifo.int_mode.disabled") && ("{{deref_id(id_prefix,'rxfifo.'~(num_fifos-1)~'.enable')}}" === "{{id_prefix}}.driver.{{ id_name() }}.rxfifo.{{(num_fifos-1)}}.enable.enabled")))) + + + ("${interface.mcu.feature_set.b}" > "0") || + (("{{deref_id(id_prefix,'fd.overflow')}}" === "{{id_prefix}}.driver.{{ id_name() }}.fd.overflow.reject") && + (!testOption("{{deref_id(id_prefix,'global_err.sources')}}", "{{id_prefix}}.driver.{{ id_name() }}.global_err.sources.overflow"))) + +{% endmacro %} + + + + + + + + + + + + + + +{%- if 'r_canfd' == module_variant %}{{ global_config('config',8) }}{%- endif %} + + testInteger("${config.driver.{{ id_name() }}.afl.ch0_num}") && (("${config.driver.{{ id_name() }}.afl.ch0_num}" >= 0) && ("${config.driver.{{ id_name() }}.afl.ch0_num}" <= 128)) + + + testInteger("${config.driver.{{ id_name() }}.afl.ch1_num}") && (("${config.driver.{{ id_name() }}.afl.ch1_num}" >= 0) && ("${config.driver.{{ id_name() }}.afl.ch1_num}" <= 128)) + + + #ifdef __cplusplus + extern "C" { + #endif + + #define CANFD_CFG_PARAM_CHECKING_ENABLE (${config.driver.{{ id_name() }}.param_checking_enable}) + + #define CANFD_CFG_AFL_CH0_RULE_NUM (${config.driver.{{ id_name() }}.afl.ch0_num}) + #define CANFD_CFG_AFL_CH1_RULE_NUM (${config.driver.{{ id_name() }}.afl.ch1_num}) + + #define CANFD_CFG_GLOBAL_ERROR_CH (${config.driver.{{ id_name() }}.global_err.cb_channel}) + + #define CANFD_CFG_FD_STANDARD (${config.driver.{{ id_name() }}.fd.standard}) + #define CANFD_CFG_FD_PROTOCOL_EXCEPTION (${config.driver.{{ id_name() }}.fd.protocol_exception}) + #define CANFD_CFG_GLOBAL_ERR_IPL (${config.driver.{{ id_name() }}.global_err.ipl}) + #define CANFD_CFG_RX_FIFO_IPL (${config.driver.{{ id_name() }}.rxfifo.ipl}) + +{%- if 'r_canfd' == module_variant %} + #define CANFD_CFG_GLOBAL_ERR_SOURCES (${config.driver.{{ id_name() }}.global_err.sources} 0x3) + #define CANFD_CFG_TX_PRIORITY (${config.driver.{{ id_name() }}.tx_priority}) + #define CANFD_CFG_DLC_CHECK (${config.driver.{{ id_name() }}.dlc_check}) + #define CANFD_CFG_FD_OVERFLOW (${config.driver.{{ id_name() }}.fd.overflow}) + #define CANFD_CFG_RXMB_NUMBER (${config.driver.{{ id_name() }}.rxmb.number}) + #define CANFD_CFG_RXMB_SIZE (${config.driver.{{ id_name() }}.rxmb.size}) + + {%- for index in range(8) %} + #define CANFD_CFG_RXFIFO{{ index }}_INT_THRESHOLD (${config.driver.{{ id_name() }}.rxfifo.{{ index }}.int_threshold}) + #define CANFD_CFG_RXFIFO{{ index }}_DEPTH (${config.driver.{{ id_name() }}.rxfifo.{{ index }}.depth}) + #define CANFD_CFG_RXFIFO{{ index }}_PAYLOAD (${config.driver.{{ id_name() }}.rxfifo.{{ index }}.payload}) + #define CANFD_CFG_RXFIFO{{ index }}_INT_MODE (${config.driver.{{ id_name() }}.rxfifo.{{ index }}.int_mode}) + #define CANFD_CFG_RXFIFO{{ index }}_ENABLE (${config.driver.{{ id_name() }}.rxfifo.{{ index }}.enable}){{ '\r\n' }} + {%- endfor %} +{%- endif %} + + #ifdef __cplusplus + } + #endif + + + + + "${module.driver.{{ id_name() }}.p_callback}" != "NULL" + +{%- if 'r_canfd' == module_variant %} +{{ global_config_constraints('config', 8) }} + + ("${config.bsp.fsp.mcu.canfd.rx_fifos}" === "8") || + ({% for fifo_number in range(2, 8 - 1) %}("${config.driver.{{ id_name() }}.rxfifo.{{ fifo_number }}.enable}" == "config.driver.{{ id_name() }}.rxfifo.{{ fifo_number }}.enable.disabled") && + {% endfor %}("${config.driver.{{ id_name() }}.rxfifo.{{ 8 - 1 }}.enable}" == "config.driver.{{ id_name() }}.rxfifo.{{ 8 - 1 }}.enable.disabled")) + +{%- else %} +{{ global_config_constraints('module', 2) }} +{%- endif %} + + "${interface.driver.{{ id_name() }}.${module.driver.{{ id_name() }}.channel}}" === "1" + + + "${interface.driver.{{ id_name() }}.${module.driver.{{ id_name() }}.name}}" === "1" + + + "${interface.mcu.canfd.external}" === "1" + + + testExists("${board.clock.peripheral.canfd}") && (${board.clock.peripheral.canfd} > 0) + + + ("${config.bsp.fsp.mcu.canfd.num_channels}" === "2") || !(("${module.driver.{{ id_name() }}.channel}" > 0) || ("${config.driver.{{ id_name() }}.afl.ch1_num}" > 0) || ("${config.driver.{{ id_name() }}.global_err.cb_channel}" > 0)) + + + ((${config.driver.{{ id_name() }}.afl.ch0_num} + ${config.driver.{{ id_name() }}.afl.ch1_num}) <= ${config.bsp.fsp.mcu.canfd.afl_rules}) || ${config.bsp.fsp.mcu.canfd.afl_rules_independent} == 1 + + + (${config.driver.{{ id_name() }}.afl.ch0_num} <= ${config.bsp.fsp.mcu.canfd.afl_rules} && ${config.driver.{{ id_name() }}.afl.ch1_num} <= ${config.bsp.fsp.mcu.canfd.afl_rules}) || ${config.bsp.fsp.mcu.canfd.afl_rules_independent} == 0 + + + (("${module.driver.{{ id_name() }}.channel}" === "0") && ("${config.driver.{{ id_name() }}.afl.ch0_num}" > "0")) || (("${module.driver.{{ id_name() }}.channel}" === "1") && ("${config.driver.{{ id_name() }}.afl.ch1_num}" > "0")) + + + "${module.driver.{{ id_name() }}.bitrate.automatic.data_rate}" <= (${config.bsp.fsp.mcu.canfd.max_data_rate_hz} * 1000000) + + + (("${module.driver.{{ id_name() }}.bitrate.manual.use_manual}" === "module.driver.{{ id_name() }}.bitrate.manual.use_manual.disabled") || (Number("${module.driver.{{ id_name() }}.manual.nominal.time_segment_1}") > Number("${module.driver.{{ id_name() }}.manual.nominal.time_segment_2}"))) + + + (("${module.driver.{{ id_name() }}.bitrate.manual.use_manual}" === "module.driver.{{ id_name() }}.bitrate.manual.use_manual.disabled") || (Number("${module.driver.{{ id_name() }}.manual.nominal.time_segment_2}") >= Number("${module.driver.{{ id_name() }}.manual.nominal.sync_jump_width}"))) + + + (("${module.driver.{{ id_name() }}.bitrate.manual.use_manual}" === "module.driver.{{ id_name() }}.bitrate.manual.use_manual.disabled") || ((Number("${module.driver.{{ id_name() }}.manual.nominal.time_segment_1}") + Number("${module.driver.{{ id_name() }}.manual.nominal.time_segment_2}")) >= 7)) + + + (("${module.driver.{{ id_name() }}.bitrate.manual.use_manual}" === "module.driver.{{ id_name() }}.bitrate.manual.use_manual.disabled") || (Number("${module.driver.{{ id_name() }}.manual.data.time_segment_1}") >= Number("${module.driver.{{ id_name() }}.manual.data.time_segment_2}"))) + + + (("${module.driver.{{ id_name() }}.bitrate.manual.use_manual}" === "module.driver.{{ id_name() }}.bitrate.manual.use_manual.disabled") || (Number("${module.driver.{{ id_name() }}.manual.data.time_segment_2}") >= Number("${module.driver.{{ id_name() }}.manual.data.sync_jump_width}"))) + + + (("${module.driver.{{ id_name() }}.bitrate.manual.use_manual}" === "module.driver.{{ id_name() }}.bitrate.manual.use_manual.disabled") || (Number("${module.driver.{{ id_name() }}.manual.nominal.prescaler}") >= Number("${module.driver.{{ id_name() }}.manual.data.prescaler}"))) + + + + + + + + + + + + + testSymbol("${module.driver.{{ id_name() }}.name}") + + + testInteger("${module.driver.{{ id_name() }}.channel}") && (("${module.driver.{{ id_name() }}.channel}" >= 0) && ("${module.driver.{{ id_name() }}.channel}" < 2)) + + + + + testInteger("${module.driver.{{ id_name() }}.bitrate.automatic.nominal_rate}") && ("${module.driver.{{ id_name() }}.bitrate.automatic.nominal_rate}" > 0) && ("${module.driver.{{ id_name() }}.bitrate.automatic.nominal_rate}" <= 1000000) + + + testInteger("${module.driver.{{ id_name() }}.bitrate.automatic.data_rate}") && ("${module.driver.{{ id_name() }}.bitrate.automatic.data_rate}" >= 1000000) + + + testInteger("${module.driver.{{ id_name() }}.bitrate.automatic.sample_point}") && ("${module.driver.{{ id_name() }}.bitrate.automatic.sample_point}" > 60) && ("${module.driver.{{ id_name() }}.bitrate.automatic.sample_point}" <= 99) + + + + + + + testInteger("${module.driver.{{ id_name() }}.manual.nominal.prescaler}") && (("${module.driver.{{ id_name() }}.manual.nominal.prescaler}" >= 1) && ("${module.driver.{{ id_name() }}.manual.nominal.prescaler}" <= 1024)) + + + testInteger("${module.driver.{{ id_name() }}.manual.nominal.time_segment_1}") && (("${module.driver.{{ id_name() }}.manual.nominal.time_segment_1}" >= 2) && ("${module.driver.{{ id_name() }}.manual.nominal.time_segment_1}" <= 256)) + + + testInteger("${module.driver.{{ id_name() }}.manual.nominal.time_segment_2}") && (("${module.driver.{{ id_name() }}.manual.nominal.time_segment_2}" >= 2) && ("${module.driver.{{ id_name() }}.manual.nominal.time_segment_2}" <= 128)) + + + testInteger("${module.driver.{{ id_name() }}.manual.nominal.sync_jump_width}") && (("${module.driver.{{ id_name() }}.manual.nominal.sync_jump_width}" >= 1) && ("${module.driver.{{ id_name() }}.manual.nominal.sync_jump_width}" <= 128)) + + + testInteger("${module.driver.{{ id_name() }}.manual.data.prescaler}") && (("${module.driver.{{ id_name() }}.manual.data.prescaler}" >= 1) && ("${module.driver.{{ id_name() }}.manual.data.prescaler}" <= 1024)) + + + testInteger("${module.driver.{{ id_name() }}.manual.data.time_segment_1}") && (("${module.driver.{{ id_name() }}.manual.data.time_segment_1}" >= 2) && ("${module.driver.{{ id_name() }}.manual.data.time_segment_1}" <= 32)) + + + testInteger("${module.driver.{{ id_name() }}.manual.data.time_segment_2}") && (("${module.driver.{{ id_name() }}.manual.data.time_segment_2}" >= 2) && ("${module.driver.{{ id_name() }}.manual.data.time_segment_2}" <= 16)) + + + testInteger("${module.driver.{{ id_name() }}.manual.data.sync_jump_width}") && (("${module.driver.{{ id_name() }}.manual.data.sync_jump_width}" >= 1) && ("${module.driver.{{ id_name() }}.manual.data.sync_jump_width}" <= 16)) + + + + + + + 256) || (nominal.tseg2 > 128))' + +' {' + +' /* Skip out-of-range time segment values */' + +' nominal_better = false;' + +' nominal_delta = 1;' + +' }' + +' else' + +' {' + +' /* Calculate remaining parameters and auxiliary info */' + +' nominal.sjw = (nominal.tseg2 >= 10) ? 4 : 1;' + +' nominal.bitrate = bit_clock / nominal_tq;' + +' nominal.ratio = (nominal.tseg1 + 1) / (nominal.tseg1 + nominal.tseg2 + 1);' + +' nominal_delta = Math.abs(nominal.bitrate - nominal_rate_requested);' + +' nominal_better = nominal_delta < Math.abs(nominal_best.bitrate - nominal_rate_requested);' + +' }' + +' ' + +' /* Calculate data bitrate parameters */' + +' data.prescaler = prescaler;' + +' data_tq = Math.round(bit_clock / data_rate_requested);' + +' data.tseg1 = Math.round(data_tq * (req_ratio / 100.0)) - 1;' + +' data.tseg2 = data_tq - (data.tseg1 + 1);' + +' ' + +' /* Adjust time segments if segment 2 is too small */' + +' if(data.tseg2 < 2)' + +' {' + +' data.tseg1 -= 2 - data.tseg2;' + +' data.tseg2 += 2 - data.tseg2;' + +' }' + +' ' + +' if((data.tseg1 > 32) || (data.tseg2 > 16) || (bit_clock < (5 * data_rate_requested)) || (prescaler > 256))' + +' {' + +' /* Skip out-of-range values */' + +' data_better = false;' + +' data_delta = 1;' + +' }' + +' else' + +' {' + +' /* Calculate remaining parameters and auxiliary info */' + +' data.sjw = (data.tseg2 >= 10) ? 4 : 1;' + +' data.bitrate = bit_clock / data_tq;' + +' data.ratio = (data.tseg1 + 1) / (data.tseg1 + data.tseg2 + 1);' + +' data_delta = Math.abs(data.bitrate - data_rate_requested);' + +' data_better = data_delta < Math.abs(data_best.bitrate - data_rate_requested);' + +' ' + +' /* If a higher prescaler results in a better data bitrate then update nominal as well to ensure data prescaler <= nominal */' + +' nominal_better = nominal_better | data_better;' + +' }' + +' ' + +' if(data_better)' + +' {' + +' /* When delay compensation is on only update data rate parameters when prescaler is <= 2 */' + +' if(!(delay_compensation && (prescaler > 2)))' + +' {' + +' BitSettingsCopy(data_best, data);' + +' }' + +' }' + +' ' + +' if(nominal_better)' + +' {' + +' BitSettingsCopy(nominal_best, nominal);' + +' }' + +' ' + +' /* Check to see if all required bitrates are exact */' + +' if((0 == nominal_delta) && (0 == data_delta))' + +' {' + +' break;' + +' }' + +' }' + +'}' + +'' + +'bit_timing_cfg = "" +' + +' "can_bit_timing_cfg_t ${module.driver.{{ id_name() }}.name}_bit_timing_cfg =\\n" +' + +' "{\\n" +' + +' " /* Actual bitrate: " + nominal_best.bitrate.toFixed(0) + " Hz. Actual sample point: "+ nominal_best.ratio.toFixed(2) * 100 +" %. */\\n" + ' + +' " .baud_rate_prescaler = " + nominal_best.prescaler.toString() + ",\\n" +' + +' " .time_segment_1 = " + nominal_best.tseg1.toString() + ",\\n" +' + +' " .time_segment_2 = " + nominal_best.tseg2.toString() + ",\\n" +' + +' " .synchronization_jump_width = " + nominal_best.sjw.toString() + "\\n" +' + +' "};\\n" +' + +' "\\n" +' + +' "#if BSP_FEATURE_CANFD_FD_SUPPORT\\n" +' + +' "can_bit_timing_cfg_t ${module.driver.{{ id_name() }}.name}_data_timing_cfg =\\n" +' + +' "{\\n" +' + +' " /* Actual bitrate: " + data_best.bitrate.toFixed(0) + " Hz. Actual sample point: "+ data_best.ratio.toFixed(2) * 100 +" %. */\\n" + ' + +' " .baud_rate_prescaler = " + data_best.prescaler.toString() + ",\\n" +' + +' " .time_segment_1 = " + data_best.tseg1.toString() + ",\\n" +' + +' " .time_segment_2 = " + data_best.tseg2.toString() + ",\\n" +' + +' " .synchronization_jump_width = " + data_best.sjw.toString() + "\\n" +' + +' "};\\n" +' + +' "#endif\\n";' + +'' + +'bit_timing_cfg' + +'') +]]> + + + + + testSymbol("${module.driver.{{ id_name() }}.p_callback}") + + + + + + + + + + + + + + testSymbol("${module.driver.{{ id_name() }}.afl_array}") + + +{%- if 'r_canfdlite' == module_variant %}{{ global_config('module',2) }}{%- endif %} + + + + + + + + + + + + + + + + + + + + + + + + + +
+/** CANFD on CANFD Instance. */ +extern const can_instance_t ${module.driver.{{ id_name() }}.name}; +/** Access the CANFD instance using these structures when calling API functions directly (::p_api is not used). */ +extern canfd_instance_ctrl_t ${module.driver.{{ id_name() }}.name}_ctrl; +extern const can_cfg_t ${module.driver.{{ id_name() }}.name}_cfg; +extern const canfd_extended_cfg_t ${module.driver.{{ id_name() }}.name}_cfg_extend; + +#ifndef ${module.driver.{{ id_name() }}.p_callback} +void ${module.driver.{{ id_name() }}.p_callback}(can_callback_args_t * p_args); +#endif + +/* Global configuration (referenced by all instances) */ +extern canfd_global_cfg_t g_canfd_global_cfg; +
+ #include "r_canfd.h" +#include "r_can_api.h" + + +/* Nominal and Data bit timing configuration */ + +${module.driver.{{ id_name() }}.bitrate.generated_data} + +extern const canfd_afl_entry_t ${module.driver.{{ id_name() }}.afl_array}[CANFD_CFG_AFL_CH${module.driver.{{ id_name() }}.channel}_RULE_NUM]; + +{%- if 'r_canfd' == module_variant %} +#ifndef CANFD_PRV_GLOBAL_CFG +#define CANFD_PRV_GLOBAL_CFG + +/* Buffer RAM used: ${config.driver.{{ id_name() }}.buffer_ram_used} bytes */ +canfd_global_cfg_t g_canfd_global_cfg = +{ + .global_interrupts = CANFD_CFG_GLOBAL_ERR_SOURCES, + .global_config = (CANFD_CFG_TX_PRIORITY | CANFD_CFG_DLC_CHECK | (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC ? R_CANFD_CFDGCFG_DCS_Msk : 0U) | CANFD_CFG_FD_OVERFLOW), + .rx_mb_config = (CANFD_CFG_RXMB_NUMBER | (CANFD_CFG_RXMB_SIZE << R_CANFD_CFDRMNB_RMPLS_Pos)), + .global_err_ipl = CANFD_CFG_GLOBAL_ERR_IPL, + .rx_fifo_ipl = CANFD_CFG_RX_FIFO_IPL, + .rx_fifo_config = + { + ((CANFD_CFG_RXFIFO0_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO0_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO0_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO0_INT_MODE) | (CANFD_CFG_RXFIFO0_ENABLE)), + ((CANFD_CFG_RXFIFO1_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO1_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO1_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO1_INT_MODE) | (CANFD_CFG_RXFIFO1_ENABLE)), +#if !BSP_FEATURE_CANFD_LITE + ((CANFD_CFG_RXFIFO2_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO2_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO2_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO2_INT_MODE) | (CANFD_CFG_RXFIFO2_ENABLE)), + ((CANFD_CFG_RXFIFO3_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO3_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO3_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO3_INT_MODE) | (CANFD_CFG_RXFIFO3_ENABLE)), + ((CANFD_CFG_RXFIFO4_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO4_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO4_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO4_INT_MODE) | (CANFD_CFG_RXFIFO4_ENABLE)), + ((CANFD_CFG_RXFIFO5_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO5_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO5_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO5_INT_MODE) | (CANFD_CFG_RXFIFO5_ENABLE)), + ((CANFD_CFG_RXFIFO6_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO6_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO6_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO6_INT_MODE) | (CANFD_CFG_RXFIFO6_ENABLE)), + ((CANFD_CFG_RXFIFO7_INT_THRESHOLD << R_CANFD_CFDRFCC_RFIGCV_Pos) | (CANFD_CFG_RXFIFO7_DEPTH << R_CANFD_CFDRFCC_RFDC_Pos) | (CANFD_CFG_RXFIFO7_PAYLOAD << R_CANFD_CFDRFCC_RFPLS_Pos) | (CANFD_CFG_RXFIFO7_INT_MODE) | (CANFD_CFG_RXFIFO7_ENABLE)), +#endif + }, +}; +#endif +{%- else %} + +/* Buffer RAM used: ${module.driver.{{ id_name() }}.buffer_ram_used} bytes */ +canfd_global_cfg_t ${module.driver.{{ id_name() }}.name}_global_cfg = +{ + .global_interrupts = (${module.driver.{{ id_name() }}.global_err.sources} 0x3), + .global_config = (${module.driver.{{ id_name() }}.tx_priority} | ${module.driver.{{ id_name() }}.dlc_check} | (BSP_CFG_CANFDCLK_SOURCE == BSP_CLOCKS_SOURCE_CLOCK_MAIN_OSC ? R_CANFD_CFDGCFG_DCS_Msk : 0U) | ${module.driver.{{ id_name() }}.fd.overflow}), + .rx_mb_config = (${module.driver.{{ id_name() }}.rxmb.number} | (${module.driver.{{ id_name() }}.rxmb.size} << R_CANFD_CFDRMNB_RMPLS_Pos)), + .global_err_ipl = CANFD_CFG_GLOBAL_ERR_IPL, + .rx_fifo_ipl = CANFD_CFG_RX_FIFO_IPL, + .rx_fifo_config = + { + (${module.driver.{{ id_name() }}.rxfifo.0.int_threshold} << R_CANFD_CFDRFCC_RFIGCV_Pos) | (${module.driver.{{ id_name() }}.rxfifo.0.depth} << R_CANFD_CFDRFCC_RFDC_Pos) | (${module.driver.{{ id_name() }}.rxfifo.0.payload} << R_CANFD_CFDRFCC_RFPLS_Pos) | (${module.driver.{{ id_name() }}.rxfifo.0.int_mode}) | (${module.driver.{{ id_name() }}.rxfifo.0.enable}), + (${module.driver.{{ id_name() }}.rxfifo.1.int_threshold} << R_CANFD_CFDRFCC_RFIGCV_Pos) | (${module.driver.{{ id_name() }}.rxfifo.1.depth} << R_CANFD_CFDRFCC_RFDC_Pos) | (${module.driver.{{ id_name() }}.rxfifo.1.payload} << R_CANFD_CFDRFCC_RFPLS_Pos) | (${module.driver.{{ id_name() }}.rxfifo.1.int_mode}) | (${module.driver.{{ id_name() }}.rxfifo.1.enable}) + } +}; +{%- endif %} + +canfd_extended_cfg_t ${module.driver.{{ id_name() }}.name}_extended_cfg = +{ + .p_afl = ${module.driver.{{ id_name() }}.afl_array}, + .txmb_txi_enable = (${module.driver.{{ id_name() }}.txmb.int} 0ULL), + .error_interrupts = (${module.driver.{{ id_name() }}.ch_err.int} 0U), +#if BSP_FEATURE_CANFD_FD_SUPPORT + .p_data_timing = &${module.driver.{{ id_name() }}.name}_data_timing_cfg, +#else + .p_data_timing = NULL, +#endif + .delay_compensation = ${module.driver.{{ id_name() }}.bitrate.automatic.delay_compensation}, + +{%- if 'r_canfd' == module_variant %} + .p_global_cfg = &g_canfd_global_cfg, +{%- else %} + .p_global_cfg = &${module.driver.{{ id_name() }}.name}_global_cfg, +{%- endif %} +}; + +canfd_instance_ctrl_t ${module.driver.{{ id_name() }}.name}_ctrl; +const can_cfg_t ${module.driver.{{ id_name() }}.name}_cfg = +{ + .channel = ${module.driver.{{ id_name() }}.channel}, + .p_bit_timing = &${module.driver.{{ id_name() }}.name}_bit_timing_cfg, + .p_callback = ${module.driver.{{ id_name() }}.p_callback}, + .p_extend = &${module.driver.{{ id_name() }}.name}_extended_cfg, + .p_context = NULL, + .ipl = ${module.driver.{{ id_name() }}.ipl}, +#if defined(VECTOR_NUMBER_CAN${module.driver.{{ id_name() }}.channel}_TX) + .tx_irq = VECTOR_NUMBER_CAN${module.driver.{{ id_name() }}.channel}_TX, +#else + .tx_irq = FSP_INVALID_VECTOR, +#endif +#if defined(VECTOR_NUMBER_CAN${module.driver.{{ id_name() }}.channel}_CHERR) + .error_irq = VECTOR_NUMBER_CAN${module.driver.{{ id_name() }}.channel}_CHERR, +#else + .error_irq = FSP_INVALID_VECTOR, +#endif +}; +/* Instance structure to use this module. */ +const can_instance_t ${module.driver.{{ id_name() }}.name} = +{ + .p_ctrl = &${module.driver.{{ id_name() }}.name}_ctrl, + .p_cfg = &${module.driver.{{ id_name() }}.name}_cfg, + .p_api = &g_canfd_on_canfd +}; + + + +
+ +BSP_CMSE_NONSECURE_ENTRY fsp_err_t ${module.driver.{{ id_name() }}.name}_open_guard(can_ctrl_t *const p_api_ctrl, can_cfg_t const *const p_cfg); + +BSP_CMSE_NONSECURE_ENTRY fsp_err_t ${module.driver.{{ id_name() }}.name}_close_guard(can_ctrl_t *const p_api_ctrl); + +BSP_CMSE_NONSECURE_ENTRY fsp_err_t ${module.driver.{{ id_name() }}.name}_write_guard(can_ctrl_t *const p_api_ctrl, uint32_t buffer, can_frame_t *const p_frame); + +BSP_CMSE_NONSECURE_ENTRY fsp_err_t ${module.driver.{{ id_name() }}.name}_read_guard(can_ctrl_t *const p_api_ctrl, uint32_t buffer, can_frame_t *const p_frame); + +BSP_CMSE_NONSECURE_ENTRY fsp_err_t ${module.driver.{{ id_name() }}.name}_mode_transition_guard(can_ctrl_t *const p_api_ctrl, can_operation_mode_t operation_mode, can_test_mode_t test_mode); + +BSP_CMSE_NONSECURE_ENTRY fsp_err_t ${module.driver.{{ id_name() }}.name}_info_get_guard(can_ctrl_t *const p_api_ctrl, can_info_t *const p_info); + +BSP_CMSE_NONSECURE_ENTRY fsp_err_t ${module.driver.{{ id_name() }}.name}_callback_set_guard(can_ctrl_t *const p_api_ctrl, void(*p_callback)(can_callback_args_t *), void const *const p_context, can_callback_args_t *const p_callback_memory); + +
+ + + +
+ +#define FSP_GUARD_${module.driver.{{ id_name() }}.name}_R_CANFD_Open() ${module.driver.{{ id_name() }}.name}_open_guard(FSP_SECURE_ARGUMENT, FSP_SECURE_ARGUMENT) + +#define FSP_GUARD_${module.driver.{{ id_name() }}.name}_R_CANFD_Close() ${module.driver.{{ id_name() }}.name}_close_guard(FSP_SECURE_ARGUMENT) + +#define FSP_GUARD_${module.driver.{{ id_name() }}.name}_R_CANFD_Write(buffer, p_frame) ${module.driver.{{ id_name() }}.name}_write_guard(FSP_SECURE_ARGUMENT, buffer, p_frame) + +#define FSP_GUARD_${module.driver.{{ id_name() }}.name}_R_CANFD_Read(buffer, p_frame) ${module.driver.{{ id_name() }}.name}_read_guard(FSP_SECURE_ARGUMENT, buffer, p_frame) + +#define FSP_GUARD_${module.driver.{{ id_name() }}.name}_R_CANFD_ModeTransition(operation_mode, test_mode) ${module.driver.{{ id_name() }}.name}_mode_transition_guard(FSP_SECURE_ARGUMENT, operation_mode, test_mode) + +#define FSP_GUARD_${module.driver.{{ id_name() }}.name}_R_CANFD_InfoGet(p_info) ${module.driver.{{ id_name() }}.name}_info_get_guard(FSP_SECURE_ARGUMENT, p_info) + +#define FSP_GUARD_${module.driver.{{ id_name() }}.name}_R_CANFD_CallbackSet(p_callback, p_context, p_callback_memory) ${module.driver.{{ id_name() }}.name}_callback_set_guard(FSP_SECURE_ARGUMENT, p_callback, p_context, p_callback_memory) + + + +BSP_CMSE_NONSECURE_ENTRY fsp_err_t ${module.driver.{{ id_name() }}.name}_open_guard(can_ctrl_t *const p_api_ctrl, can_cfg_t const *const p_cfg); + +BSP_CMSE_NONSECURE_ENTRY fsp_err_t ${module.driver.{{ id_name() }}.name}_close_guard(can_ctrl_t *const p_api_ctrl); + +BSP_CMSE_NONSECURE_ENTRY fsp_err_t ${module.driver.{{ id_name() }}.name}_write_guard(can_ctrl_t *const p_api_ctrl, uint32_t buffer, can_frame_t *const p_frame); + +BSP_CMSE_NONSECURE_ENTRY fsp_err_t ${module.driver.{{ id_name() }}.name}_read_guard(can_ctrl_t *const p_api_ctrl, uint32_t buffer, can_frame_t *const p_frame); + +BSP_CMSE_NONSECURE_ENTRY fsp_err_t ${module.driver.{{ id_name() }}.name}_mode_transition_guard(can_ctrl_t *const p_api_ctrl, can_operation_mode_t operation_mode, can_test_mode_t test_mode); + +BSP_CMSE_NONSECURE_ENTRY fsp_err_t ${module.driver.{{ id_name() }}.name}_info_get_guard(can_ctrl_t *const p_api_ctrl, can_info_t *const p_info); + +BSP_CMSE_NONSECURE_ENTRY fsp_err_t ${module.driver.{{ id_name() }}.name}_callback_set_guard(can_ctrl_t *const p_api_ctrl, void(*p_callback)(can_callback_args_t *), void const *const p_context, can_callback_args_t *const p_callback_memory); + + +extern const can_instance_t ${module.driver.{{ id_name() }}.name}; +
+ + + + + + ra/fsp/inc/instances/r_canfd.h + ra/fsp/inc/api/r_can_api.h + + + + + + + diff --git a/ra/fsp/src/r_canfd/.util/canfd_gen.py b/ra/fsp/src/r_canfd/.util/canfd_gen.py new file mode 100644 index 000000000..fe77dec67 --- /dev/null +++ b/ra/fsp/src/r_canfd/.util/canfd_gen.py @@ -0,0 +1,13 @@ +from jinja2 import Template +import pathlib +import os +import re +output_dir = '../../../../../data/.module_descriptions' + +if __name__ == "__main__": + os.chdir(pathlib.Path(__file__).parent.resolve()) + for c in ['r_canfd', 'r_canfdlite']: + with open('Renesas##HAL Drivers##all##r_canfd####x.xx.xx.xml.j2') as temp: + t = Template(temp.read()) + with open(os.path.join(output_dir, 'Renesas##HAL Drivers##all##{}####x.xx.xx.xml').format(c), 'w+') as f: + f.write(re.sub(r' *\r?\n', r'\r\n', t.render(module_variant=c).strip(),flags=re.M)) diff --git a/ra/fsp/src/r_canfd/r_canfd.c b/ra/fsp/src/r_canfd/r_canfd.c index f89ceba78..7ae155e27 100644 --- a/ra/fsp/src/r_canfd/r_canfd.c +++ b/ra/fsp/src/r_canfd/r_canfd.c @@ -28,30 +28,52 @@ * Macro definitions **********************************************************************************************************************/ -#define CANFD_OPEN (0x52434644U) // "RCFD" in ASCII +#define CANFD_OPEN (0x52434644U) // "RCFD" in ASCII -#define CANFD_BAUD_RATE_PRESCALER_MIN (1U) -#define CANFD_BAUD_RATE_PRESCALER_MAX (1024U) +#define CANFD_BAUD_RATE_PRESCALER_MIN (1U) +#define CANFD_BAUD_RATE_PRESCALER_MAX (1024U) -#define CANFD_PRV_CTR_MODE_MASK (R_CANFD_CFDGCTR_GSLPR_Msk + R_CANFD_CFDGCTR_GMDC_Msk) -#define CANFD_PRV_CTR_RESET_BIT (1U) -#define CANFD_PRV_RXMB_MAX (32U) -#define CANFD_PRV_TXMB_OFFSET (32U) -#define CANFD_PRV_TXMB_CHANNEL_OFFSET (64U) -#define CANFD_PRV_STANDARD_ID_MAX (0x7FFU) +#define CANFD_PRV_CTR_MODE_MASK (R_CANFD_CFDGCTR_GSLPR_Msk + R_CANFD_CFDGCTR_GMDC_Msk) +#define CANFD_PRV_CTR_RESET_BIT (1U) +#define CANFD_PRV_RXMB_MAX (32U) +#define CANFD_PRV_TXMB_OFFSET (32U) +#define CANFD_PRV_TXMB_CHANNEL_OFFSET (64U) +#define CANFD_PRV_STANDARD_ID_MAX (0x7FFU) #if BSP_FEATURE_CANFD_LITE - #define CANFD_PRV_RXMB_PTR(buffer) ((volatile R_CANFD_CFDRM_Type *) &R_CANFD->CFDRMC[buffer >> 3].RM[buffer & 7U]) - #define CANFD_PRV_RX_FIFO_MAX (2U) - #define CANFD_PRV_RX_FIFO_STATUS_MASK (R_CANFDL_CFDFESTS_RFXEMP_Msk) - #define CANFD_PRV_AFL_CAST (volatile R_CANFD_CFDGAFL_Type *) - #define CANFD_PRV_CFDTMIEC_LENGTH (1) + #define R_CANFD_CFDRM_RM_TYPE R_CANFD_CFDRM_RM_Type + + #define CANFD_PRV_RXMB_PTR(buffer) ((volatile R_CANFD_CFDRM_RM_TYPE *) &p_reg->CFDRM[buffer >> 3].RM[buffer & 7U]) + #define CANFD_PRV_RX_FIFO_MAX (2U) + #define CANFD_PRV_CFDTMIEC_LENGTH (1) + #define CANFD_PRV_RMID_POSITION (R_CANFD_CFDRM_RM_ID_RMID_Pos) + #define CANFD_PRV_RMID_MASK (R_CANFD_CFDRM_RM_ID_RMID_Msk) + #define CANFD_PRV_RMRTR_POSITION (R_CANFD_CFDRM_RM_ID_RMRTR_Pos) + #define CANFD_PRV_RMRTR_MASK (R_CANFD_CFDRM_RM_ID_RMRTR_Msk) + #define CANFD_PRV_RMIDE_POSITION (R_CANFD_CFDRM_RM_ID_RMIDE_Pos) + #define CANFD_PRV_RMIDE_MASK (R_CANFD_CFDRM_RM_ID_RMIDE_Msk) + #define CANFD_PRV_RMDLC_POSITION (R_CANFD_CFDRM_RM_PTR_RMDLC_Pos) + #define CANFD_PRV_RMDLC_MASK (R_CANFD_CFDRM_RM_PTR_RMDLC_Msk) #else - #define CANFD_PRV_RXMB_PTR(buffer) (&R_CANFD->CFDRM[buffer]) - #define CANFD_PRV_RX_FIFO_MAX (8U) - #define CANFD_PRV_RX_FIFO_STATUS_MASK (R_CANFD_CFDFESTS_RFXEMP_Msk) - #define CANFD_PRV_AFL_CAST - #define CANFD_PRV_CFDTMIEC_LENGTH (2) + #define R_CANFD_CFDRM_RM_TYPE R_CANFD_CFDRM_Type + + #define CANFD_PRV_RXMB_PTR(buffer) (&p_reg->CFDRM[buffer]) + #define CANFD_PRV_RX_FIFO_MAX (8U) + #define CANFD_PRV_CFDTMIEC_LENGTH (2) + #define CANFD_PRV_RMID_POSITION (R_CANFD_CFDRM_ID_RMID_Pos) + #define CANFD_PRV_RMID_MASK (R_CANFD_CFDRM_ID_RMID_Msk) + #define CANFD_PRV_RMRTR_POSITION (R_CANFD_CFDRM_ID_RMRTR_Pos) + #define CANFD_PRV_RMRTR_MASK (R_CANFD_CFDRM_ID_RMRTR_Msk) + #define CANFD_PRV_RMIDE_POSITION (R_CANFD_CFDRM_ID_RMIDE_Pos) + #define CANFD_PRV_RMIDE_MASK (R_CANFD_CFDRM_ID_RMIDE_Msk) + #define CANFD_PRV_RMDLC_POSITION (R_CANFD_CFDRM_PTR_RMDLC_Pos) + #define CANFD_PRV_RMDLC_MASK (R_CANFD_CFDRM_PTR_RMDLC_Msk) +#endif + +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + #define CANFD_INTER_CH(channel) (0U) +#else + #define CANFD_INTER_CH(channel) (channel) #endif /*********************************************************************************************************************** @@ -89,7 +111,9 @@ static uint8_t r_canfd_bytes_to_dlc(uint8_t bytes); #endif -static void r_canfd_mb_read(uint32_t buffer, can_frame_t * const frame); +static void r_candfd_global_error_handler(uint32_t instance); +static void r_canfd_rx_fifo_handler(uint32_t instance); +static void r_canfd_mb_read(R_CANFD_Type * p_reg, uint32_t buffer, can_frame_t * const frame); static void r_canfd_call_callback(canfd_instance_ctrl_t * p_ctrl, can_callback_args_t * p_args); static void r_canfd_mode_transition(canfd_instance_ctrl_t * p_ctrl, can_operation_mode_t operation_mode); static void r_canfd_mode_ctr_set(volatile uint32_t * p_ctr_reg, can_operation_mode_t operation_mode); @@ -110,7 +134,7 @@ void canfd_channel_tx_isr(void); **********************************************************************************************************************/ /* Channel control struct array */ -static canfd_instance_ctrl_t * gp_ctrl[BSP_FEATURE_CANFD_NUM_CHANNELS] = {NULL}; +static canfd_instance_ctrl_t * gp_ctrl[BSP_FEATURE_CANFD_NUM_INSTANCES * BSP_FEATURE_CANFD_NUM_CHANNELS] = {NULL}; /* CAN function pointers */ const can_api_t g_canfd_on_canfd = @@ -162,7 +186,8 @@ fsp_err_t R_CANFD_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p /* Check that the module is not open, the channel is present and that it is not in use */ FSP_ERROR_RETURN(CANFD_OPEN != p_ctrl->open, FSP_ERR_ALREADY_OPEN); - FSP_ERROR_RETURN(channel < BSP_FEATURE_CANFD_NUM_CHANNELS, FSP_ERR_IP_CHANNEL_NOT_PRESENT); + FSP_ERROR_RETURN(channel < BSP_FEATURE_CANFD_NUM_CHANNELS * BSP_FEATURE_CANFD_NUM_INSTANCES, + FSP_ERR_IP_CHANNEL_NOT_PRESENT); FSP_ERROR_RETURN(NULL == gp_ctrl[channel], FSP_ERR_IN_USE); /* Check that mandatory interrupts are enabled */ @@ -208,6 +233,15 @@ fsp_err_t R_CANFD_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p fsp_err_t err = FSP_SUCCESS; + /* Save the base register for this channel. */ +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + R_CANFD_Type * p_reg = + (R_CANFD_Type *) ((uint32_t) R_CANFD0 + (channel * ((uint32_t) R_CANFD1 - (uint32_t) R_CANFD0))); +#else + R_CANFD_Type * p_reg = R_CANFD; +#endif + p_ctrl->p_reg = p_reg; + /* Initialize the control block */ p_ctrl->p_cfg = p_cfg; @@ -220,53 +254,65 @@ fsp_err_t R_CANFD_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p canfd_global_cfg_t * p_global_cfg = p_extend->p_global_cfg; /* Start module */ +#if BSP_FEATURE_CANFD_LITE + R_BSP_MODULE_START(FSP_IP_CANFD, channel); +#else R_BSP_MODULE_START(FSP_IP_CANFD, 0); +#endif /* Perform global config only if the module is in Global Sleep or Global Reset */ - if (R_CANFD->CFDGSTS & R_CANFD_CFDGSTS_GRSTSTS_Msk) +#if !BSP_FEATURE_CANFD_LITE + if (p_reg->CFDGSTS & R_CANFD_CFDGSTS_GRSTSTS_Msk) +#endif { /* Wait for RAM initialization (see RA6M5 User's Manual (R01UH0891EJ0100) section 32.3.4.1 Note 2) */ - FSP_HARDWARE_REGISTER_WAIT((R_CANFD->CFDGSTS & R_CANFD_CFDGSTS_GRAMINIT_Msk), 0); + FSP_HARDWARE_REGISTER_WAIT((p_reg->CFDGSTS & R_CANFD_CFDGSTS_GRAMINIT_Msk), 0); /* Cancel Global Sleep and wait for transition to Global Reset */ r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_GLOBAL_RESET); /* Configure global TX priority, DLC check/replace functions, external/internal clock select and payload * overflow behavior */ - R_CANFD->CFDGCFG = p_global_cfg->global_config; + p_reg->CFDGCFG = p_global_cfg->global_config; /* Configure rule count for both channels */ - R_CANFD->CFDGAFLCFG0 = (CANFD_CFG_AFL_CH0_RULE_NUM << R_CANFD_CFDGAFLCFG0_RNC0_Pos) | - CANFD_CFG_AFL_CH1_RULE_NUM; +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + p_reg->CFDGAFLCFG0 = (CANFD_CFG_AFL_CH0_RULE_NUM << R_CANFD_CFDGAFLCFG0_RNC0_Pos); +#else + p_reg->CFDGAFLCFG0 = (CANFD_CFG_AFL_CH0_RULE_NUM << R_CANFD_CFDGAFLCFG0_RNC0_Pos) | + CANFD_CFG_AFL_CH1_RULE_NUM; +#endif /* Set CAN FD Protocol Exception response (ISO exception state or send error frame) */ - R_CANFD->CFDGFDCFG = CANFD_CFG_FD_PROTOCOL_EXCEPTION; + p_reg->CFDGFDCFG = CANFD_CFG_FD_PROTOCOL_EXCEPTION; #if !BSP_FEATURE_CANFD_LITE /* Set CAN FD standard (ISO or Bosch) */ - R_CANFD->CFDGCRCCFG = CANFD_CFG_FD_STANDARD; + p_reg->CFDGCRCCFG = CANFD_CFG_FD_STANDARD; #endif /* Set number and size of RX message buffers */ - R_CANFD->CFDRMNB = p_global_cfg->rx_mb_config; + p_reg->CFDRMNB = p_global_cfg->rx_mb_config; /* Configure RX FIFOs and interrupt */ for (uint32_t i = 0; i < CANFD_PRV_RX_FIFO_MAX; i++) { - R_CANFD->CFDRFCC[i] = p_global_cfg->rx_fifo_config[i]; + p_reg->CFDRFCC[i] = p_global_cfg->rx_fifo_config[i]; } R_BSP_IrqCfgEnable(VECTOR_NUMBER_CAN_RXF, p_global_cfg->rx_fifo_ipl, NULL); /* Set global error interrupts */ - R_CANFD->CFDGCTR = p_global_cfg->global_interrupts; + p_reg->CFDGCTR = p_global_cfg->global_interrupts; } +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 if (CANFD_CFG_GLOBAL_ERROR_CH == channel) +#endif { /* Configure global error interrupt */ - R_BSP_IrqCfgEnable(VECTOR_NUMBER_CAN_GLERR, p_global_cfg->global_err_ipl, NULL); + R_BSP_IrqCfgEnable(VECTOR_NUMBER_CAN_GLERR, p_global_cfg->global_err_ipl, p_ctrl); } /* Track ctrl struct */ @@ -274,15 +320,24 @@ fsp_err_t R_CANFD_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p /* Get AFL entry and limit */ uint32_t afl_entry = 0; - uint32_t afl_max = CANFD_CFG_AFL_CH0_RULE_NUM; +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + uint32_t afl_max = CANFD_CFG_AFL_CH0_RULE_NUM; + if (1U == channel) + { + afl_max = CANFD_CFG_AFL_CH1_RULE_NUM; + } + +#else + uint32_t afl_max = CANFD_CFG_AFL_CH0_RULE_NUM; if (1U == channel) { afl_entry += CANFD_CFG_AFL_CH0_RULE_NUM; afl_max += CANFD_CFG_AFL_CH1_RULE_NUM; } +#endif /* Unlock AFL */ - R_CANFD->CFDGAFLECTR = R_CANFD_CFDGAFLECTR_AFLDAE_Msk; + p_reg->CFDGAFLECTR = R_CANFD_CFDGAFLECTR_AFLDAE_Msk; /* Write all configured AFL entries */ R_CANFD_CFDGAFL_Type * p_afl = (R_CANFD_CFDGAFL_Type *) p_extend->p_afl; @@ -292,10 +347,10 @@ fsp_err_t R_CANFD_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p * Entries in the AFL" in the RA6M5 User's Manual (R01UH0891EJ010) for more details. */ /* Set AFL page */ - R_CANFD->CFDGAFLECTR = (afl_entry >> 4) | R_CANFD_CFDGAFLECTR_AFLDAE_Msk; + p_reg->CFDGAFLECTR = (afl_entry >> 4) | R_CANFD_CFDGAFLECTR_AFLDAE_Msk; /* Get pointer to current AFL rule and set it to the rule pointed to by p_afl */ - volatile R_CANFD_CFDGAFL_Type * cfdgafl = CANFD_PRV_AFL_CAST & R_CANFD->CFDGAFL[afl_entry & 0xF]; + volatile R_CANFD_CFDGAFL_Type * cfdgafl = &p_reg->CFDGAFL[afl_entry & 0xF]; *cfdgafl = *p_afl++; /* Set Information Label 0 to the channel being configured */ @@ -303,13 +358,15 @@ fsp_err_t R_CANFD_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p } /* Lock AFL */ - R_CANFD->CFDGAFLECTR = 0; + p_reg->CFDGAFLECTR = 0; /* Cancel Channel Sleep and wait for transition to Channel Reset */ r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_RESET); + uint32_t interlaced_channel = CANFD_INTER_CH(channel); + /* Configure bitrate */ - R_CANFD->CFDC[channel].NCFG = + p_reg->CFDC[interlaced_channel].NCFG = (uint32_t) (((p_cfg->p_bit_timing->baud_rate_prescaler - 1) & R_CANFD_CFDC_NCFG_NBRP_Msk) << R_CANFD_CFDC_NCFG_NBRP_Pos) | ((p_cfg->p_bit_timing->time_segment_1 - 1U) << R_CANFD_CFDC_NCFG_NTSEG1_Pos) | @@ -319,7 +376,7 @@ fsp_err_t R_CANFD_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p #if BSP_FEATURE_CANFD_FD_SUPPORT /* Configure data bitrate for rate switching on FD frames */ - R_CANFD->CFDC2[channel].DCFG = + p_reg->CFDC2[interlaced_channel].DCFG = (uint32_t) (((p_extend->p_data_timing->baud_rate_prescaler - 1) & R_CANFD_CFDC2_DCFG_DBRP_Msk) << R_CANFD_CFDC2_DCFG_DBRP_Pos) | ((p_extend->p_data_timing->time_segment_1 - 1U) << R_CANFD_CFDC2_DCFG_DTSEG1_Pos) | @@ -334,19 +391,19 @@ fsp_err_t R_CANFD_Open (can_ctrl_t * const p_api_ctrl, can_cfg_t const * const p } /* Configure transceiver delay compensation; allow user to set ESI bit manually */ - R_CANFD->CFDC2[channel].FDCFG = + p_reg->CFDC2[interlaced_channel].FDCFG = (tdco << R_CANFD_CFDC2_FDCFG_TDCO_Pos) | (uint32_t) (p_extend->delay_compensation << R_CANFD_CFDC2_FDCFG_TDCE_Pos) | R_CANFD_CFDC2_FDCFG_ESIC_Msk | 1U; #endif /* Write TX message buffer interrupt enable bits */ - memcpy((void *) &R_CANFD->CFDTMIEC[channel * CANFD_PRV_CFDTMIEC_LENGTH], + memcpy((void *) &p_reg->CFDTMIEC[interlaced_channel * CANFD_PRV_CFDTMIEC_LENGTH], &p_extend->txmb_txi_enable, CANFD_PRV_CFDTMIEC_LENGTH * sizeof(uint32_t)); /* Configure channel error interrupts */ - R_CANFD->CFDC[channel].CTR = p_extend->error_interrupts | R_CANFD_CFDC_CTR_CHMDC_Msk; + p_reg->CFDC[interlaced_channel].CTR = p_extend->error_interrupts | R_CANFD_CFDC_CTR_CHMDC_Msk; /* Enable channel interrupts */ @@ -411,9 +468,21 @@ fsp_err_t R_CANFD_Close (can_ctrl_t * const p_api_ctrl) } /* Disable Global Error interrupt if the handler channel is being closed */ +#if !BSP_FEATURE_CANFD_LITE if (CANFD_CFG_GLOBAL_ERROR_CH == p_cfg->channel) +#elif BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + + /* Only disable the Global Error interrupt if both channels are closed. */ + if (NULL == gp_ctrl[!p_cfg->channel]) +#endif { R_BSP_IrqDisable(VECTOR_NUMBER_CAN_GLERR); + +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + + /* Disable RX FIFO interrupt */ + R_BSP_IrqDisable(VECTOR_NUMBER_CAN_RXF); +#endif } #if !BSP_FEATURE_CANFD_LITE @@ -426,15 +495,22 @@ fsp_err_t R_CANFD_Close (can_ctrl_t * const p_api_ctrl) else #endif { +#if BSP_FEATURE_CANFD_NUM_INSTANCES == 1 + /* Disable RX FIFO interrupt */ R_BSP_IrqDisable(VECTOR_NUMBER_CAN_RXF); +#endif /* Transition to Global Sleep */ r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_GLOBAL_RESET); r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_GLOBAL_SLEEP); /* Stop CANFD module */ +#if BSP_FEATURE_CANFD_LITE + R_BSP_MODULE_STOP(FSP_IP_CANFD, p_cfg->channel); +#else R_BSP_MODULE_STOP(FSP_IP_CANFD, 0); +#endif } /* Reset global control struct pointer */ @@ -501,32 +577,34 @@ fsp_err_t R_CANFD_Write (can_ctrl_t * const p_api_ctrl, uint32_t buffer, can_fra canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; #endif + uint32_t interlaced_channel = CANFD_INTER_CH(p_ctrl->p_cfg->channel); + /* Calculate global TX message buffer number */ - uint32_t txmb = buffer + (p_ctrl->p_cfg->channel * CANFD_PRV_TXMB_CHANNEL_OFFSET); + uint32_t txmb = buffer + (interlaced_channel * CANFD_PRV_TXMB_CHANNEL_OFFSET); /* Ensure MB is ready */ - FSP_ERROR_RETURN(0U == R_CANFD->CFDTMSTS_b[txmb].TMTSTS, FSP_ERR_CAN_TRANSMIT_NOT_READY); + FSP_ERROR_RETURN(0U == p_ctrl->p_reg->CFDTMSTS_b[txmb].TMTSTS, FSP_ERR_CAN_TRANSMIT_NOT_READY); /* Set ID */ - R_CANFD->CFDTM[txmb].ID = p_frame->id | ((uint32_t) p_frame->type << R_CANFD_CFDTM_ID_TMRTR_Pos) | - ((uint32_t) p_frame->id_mode << R_CANFD_CFDTM_ID_TMIDE_Pos); + p_ctrl->p_reg->CFDTM[txmb].ID = p_frame->id | ((uint32_t) p_frame->type << R_CANFD_CFDTM_ID_TMRTR_Pos) | + ((uint32_t) p_frame->id_mode << R_CANFD_CFDTM_ID_TMIDE_Pos); #if BSP_FEATURE_CANFD_FD_SUPPORT /* Set DLC */ - R_CANFD->CFDTM[txmb].PTR = (uint32_t) r_canfd_bytes_to_dlc(p_frame->data_length_code) << - R_CANFD_CFDTM_PTR_TMDLC_Pos; + p_ctrl->p_reg->CFDTM[txmb].PTR = (uint32_t) r_canfd_bytes_to_dlc(p_frame->data_length_code) << + R_CANFD_CFDTM_PTR_TMDLC_Pos; /* Set FD bits (ESI, BRS and FDF) */ - R_CANFD->CFDTM[txmb].FDCTR = p_frame->options & 7U; + p_ctrl->p_reg->CFDTM[txmb].FDCTR = p_frame->options & 7U; #else /* Set DLC */ - R_CANFD->CFDTM[txmb].PTR = (uint32_t) p_frame->data_length_code << R_CANFD_CFDTM_PTR_TMDLC_Pos; + p_ctrl->p_reg->CFDTM[txmb].PTR = (uint32_t) p_frame->data_length_code << R_CANFD_CFDTM_PTR_TMDLC_Pos; #endif /* Copy data to register buffer */ uint32_t len = p_frame->data_length_code; - uint8_t * p_dest = (uint8_t *) R_CANFD->CFDTM[txmb].DF; + uint8_t * p_dest = (uint8_t *) p_ctrl->p_reg->CFDTM[txmb].DF; uint8_t * p_src = p_frame->data; while (len--) { @@ -534,7 +612,7 @@ fsp_err_t R_CANFD_Write (can_ctrl_t * const p_api_ctrl, uint32_t buffer, can_fra } /* Request transmission */ - R_CANFD->CFDTMC[txmb] = 1; + p_ctrl->p_reg->CFDTMC[txmb] = 1; return FSP_SUCCESS; } @@ -553,14 +631,12 @@ fsp_err_t R_CANFD_Write (can_ctrl_t * const p_api_ctrl, uint32_t buffer, can_fra *****************************************************************************************************************/ fsp_err_t R_CANFD_Read (can_ctrl_t * const p_api_ctrl, uint32_t buffer, can_frame_t * const p_frame) { -#if CANFD_CFG_PARAM_CHECKING_ENABLE canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; +#if CANFD_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_ctrl); FSP_ASSERT(NULL != p_frame); FSP_ERROR_RETURN(p_ctrl->open == CANFD_OPEN, FSP_ERR_NOT_OPEN); FSP_ERROR_RETURN(buffer < CANFD_PRV_RXMB_MAX + CANFD_PRV_RX_FIFO_MAX, FSP_ERR_INVALID_ARGUMENT); -#else - FSP_PARAMETER_NOT_USED(p_api_ctrl); #endif uint32_t not_empty; @@ -568,17 +644,17 @@ fsp_err_t R_CANFD_Read (can_ctrl_t * const p_api_ctrl, uint32_t buffer, can_fram /* Return an error if the buffer or FIFO is empty */ if (buffer < CANFD_PRV_RXMB_MAX) { - not_empty = R_CANFD->CFDRMND0 & (1U << buffer); + not_empty = p_ctrl->p_reg->CFDRMND0 & (1U << buffer); } else { - not_empty = !(R_CANFD->CFDFESTS & (1U << (buffer - CANFD_PRV_RXMB_MAX))); + not_empty = !(p_ctrl->p_reg->CFDFESTS & (1U << (buffer - CANFD_PRV_RXMB_MAX))); } FSP_ERROR_RETURN(not_empty, FSP_ERR_BUFFER_EMPTY); /* Retrieve message from buffer */ - r_canfd_mb_read(buffer, p_frame); + r_canfd_mb_read(p_ctrl->p_reg, buffer, p_frame); return FSP_SUCCESS; } @@ -605,7 +681,7 @@ fsp_err_t R_CANFD_ModeTransition (can_ctrl_t * const p_api_ctrl, FSP_ERROR_RETURN(p_ctrl->open == CANFD_OPEN, FSP_ERR_NOT_OPEN); /* Get Global Status */ - uint32_t cfdgsts = R_CANFD->CFDGSTS; + uint32_t cfdgsts = p_ctrl->p_reg->CFDGSTS; #if !BSP_FEATURE_CANFD_LITE @@ -636,7 +712,7 @@ fsp_err_t R_CANFD_ModeTransition (can_ctrl_t * const p_api_ctrl, } #endif - uint32_t channel = p_ctrl->p_cfg->channel; + uint32_t interlaced_channel = CANFD_INTER_CH(p_ctrl->p_cfg->channel); if (p_ctrl->test_mode != test_mode) { @@ -647,13 +723,13 @@ fsp_err_t R_CANFD_ModeTransition (can_ctrl_t * const p_api_ctrl, if (CAN_TEST_MODE_INTERNAL_BUS == test_mode) { /* Disable channel test mode */ - R_CANFD->CFDC[channel].CTR_b.CTME = 0; + p_ctrl->p_reg->CFDC[interlaced_channel].CTR_b.CTME = 0; /* Link channel to internal bus */ - R_CANFD->CFDGTSTCFG |= 1U << channel; + p_ctrl->p_reg->CFDGTSTCFG |= 1U << interlaced_channel; /* Enable internal bus test mode */ - R_CANFD->CFDGTSTCTR = 1; + p_ctrl->p_reg->CFDGTSTCTR = 1; } else #endif @@ -662,12 +738,12 @@ fsp_err_t R_CANFD_ModeTransition (can_ctrl_t * const p_api_ctrl, if (p_ctrl->test_mode == CAN_TEST_MODE_INTERNAL_BUS) { /* Unlink channel from internal bus */ - R_CANFD->CFDGTSTCFG &= ~(1U << channel); + p_ctrl->p_reg->CFDGTSTCFG &= ~(1U << interlaced_channel); /* Disable global test mode if no channels are linked */ - if (!R_CANFD->CFDGTSTCFG) + if (!p_ctrl->p_reg->CFDGTSTCFG) { - R_CANFD->CFDGTSTCTR = 0; + p_ctrl->p_reg->CFDGTSTCTR = 0; } } #endif @@ -676,9 +752,10 @@ fsp_err_t R_CANFD_ModeTransition (can_ctrl_t * const p_api_ctrl, r_canfd_mode_transition(p_ctrl, CAN_OPERATION_MODE_HALT); /* Set channel test mode */ - uint32_t cfdcnctr = R_CANFD->CFDC[channel].CTR; + uint32_t cfdcnctr = p_ctrl->p_reg->CFDC[interlaced_channel].CTR; cfdcnctr &= ~(R_CANFD_CFDC_CTR_CTME_Msk | R_CANFD_CFDC_CTR_CTMS_Msk); - R_CANFD->CFDC[channel].CTR = cfdcnctr | ((uint32_t) test_mode << R_CANFD_CFDC_CTR_CTME_Pos); + p_ctrl->p_reg->CFDC[interlaced_channel].CTR = cfdcnctr | + ((uint32_t) test_mode << R_CANFD_CFDC_CTR_CTME_Pos); } p_ctrl->test_mode = test_mode; @@ -714,18 +791,18 @@ fsp_err_t R_CANFD_InfoGet (can_ctrl_t * const p_api_ctrl, can_info_t * const p_i canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) p_api_ctrl; #endif - uint32_t channel = p_ctrl->p_cfg->channel; + uint32_t interlaced_channel = CANFD_INTER_CH(p_ctrl->p_cfg->channel); - uint32_t cfdcnsts = R_CANFD->CFDC[channel].STS; + uint32_t cfdcnsts = p_ctrl->p_reg->CFDC[interlaced_channel].STS; p_info->status = cfdcnsts & UINT16_MAX; p_info->error_count_receive = (uint8_t) ((cfdcnsts & R_CANFD_CFDC_STS_REC_Msk) >> R_CANFD_CFDC_STS_REC_Pos); p_info->error_count_transmit = (uint8_t) ((cfdcnsts & R_CANFD_CFDC_STS_TEC_Msk) >> R_CANFD_CFDC_STS_TEC_Pos); - p_info->error_code = R_CANFD->CFDC[channel].ERFL & UINT16_MAX; - p_info->rx_mb_status = R_CANFD->CFDRMND0; - p_info->rx_fifo_status = (~R_CANFD->CFDFESTS) & CANFD_PRV_RX_FIFO_STATUS_MASK; + p_info->error_code = p_ctrl->p_reg->CFDC[interlaced_channel].ERFL & UINT16_MAX; + p_info->rx_mb_status = p_ctrl->p_reg->CFDRMND0; + p_info->rx_fifo_status = (~p_ctrl->p_reg->CFDFESTS) & R_CANFD_CFDFESTS_RFXEMP_Msk; /* Clear error flags */ - R_CANFD->CFDC[channel].ERFL &= ~((uint32_t) UINT16_MAX); + p_ctrl->p_reg->CFDC[interlaced_channel].ERFL &= ~((uint32_t) UINT16_MAX); return FSP_SUCCESS; } @@ -815,23 +892,24 @@ static bool r_canfd_bit_timing_parameter_check (can_bit_timing_cfg_t * const p_b * * NOTE: Does not index FIFOs. * + * @param[in] p_reg Pointer to the CANFD registers * @param[in] buffer Index of buffer to read from (MBs 0-31, FIFOs 32+) * @param[in] frame Pointer to CAN frame to write to **********************************************************************************************************************/ -static void r_canfd_mb_read (uint32_t buffer, can_frame_t * const frame) +static void r_canfd_mb_read (R_CANFD_Type * p_reg, uint32_t buffer, can_frame_t * const frame) { bool is_mb = buffer < CANFD_PRV_RXMB_MAX; /* Get pointer to message buffer (FIFOs use the same buffer structure) */ - volatile R_CANFD_CFDRM_Type * mb_regs = + volatile R_CANFD_CFDRM_RM_TYPE * mb_regs = (is_mb) ? CANFD_PRV_RXMB_PTR(buffer) : - (volatile R_CANFD_CFDRM_Type *) &(R_CANFD->CFDRF[buffer - CANFD_PRV_RXMB_MAX]); + (volatile R_CANFD_CFDRM_RM_TYPE *) &(p_reg->CFDRF[buffer - CANFD_PRV_RXMB_MAX]); /* Get frame data. */ uint32_t id = mb_regs->ID; /* Get the frame type */ - frame->type = (can_frame_type_t) ((id & R_CANFD_CFDRM_ID_RMRTR_Msk) >> R_CANFD_CFDRM_ID_RMRTR_Pos); + frame->type = (can_frame_type_t) ((id & CANFD_PRV_RMRTR_MASK) >> CANFD_PRV_RMRTR_POSITION); #if BSP_FEATURE_CANFD_FD_SUPPORT @@ -842,13 +920,13 @@ static void r_canfd_mb_read (uint32_t buffer, can_frame_t * const frame) #endif /* Get the frame ID */ - frame->id = id & R_CANFD_CFDRM_ID_RMID_Msk; + frame->id = id & CANFD_PRV_RMID_MASK; /* Get the frame ID mode (IDE bit) */ - frame->id_mode = (can_id_mode_t) (id >> R_CANFD_CFDRM_ID_RMIDE_Pos); + frame->id_mode = (can_id_mode_t) (id >> CANFD_PRV_RMIDE_POSITION); /* Get the frame data length code */ - frame->data_length_code = dlc_to_bytes[mb_regs->PTR >> R_CANFD_CFDRM_PTR_RMDLC_Pos]; + frame->data_length_code = dlc_to_bytes[mb_regs->PTR >> CANFD_PRV_RMDLC_POSITION]; /* Copy data to frame */ uint32_t len = frame->data_length_code; @@ -862,12 +940,12 @@ static void r_canfd_mb_read (uint32_t buffer, can_frame_t * const frame) if (is_mb) { /* Clear RXMB New Data bit */ - R_CANFD->CFDRMND0 &= ~(1U << buffer); + p_reg->CFDRMND0 &= ~(1U << buffer); } else { /* Increment RX FIFO pointer */ - R_CANFD->CFDRFPCTR[buffer - CANFD_PRV_RXMB_MAX] = UINT8_MAX; + p_reg->CFDRFPCTR[buffer - CANFD_PRV_RXMB_MAX] = UINT8_MAX; } } @@ -926,6 +1004,43 @@ static void r_canfd_call_callback (canfd_instance_ctrl_t * p_ctrl, can_callback_ } } +/*******************************************************************************************************************//** + * Global Error Handler. + * + * Handles the Global Error IRQ for a given instance of CANFD. + **********************************************************************************************************************/ +static void r_candfd_global_error_handler (uint32_t instance) +{ + canfd_instance_ctrl_t * p_ctrl = gp_ctrl[instance]; + + can_callback_args_t args = {0U}; + + args.event = CAN_EVENT_ERR_GLOBAL; + + /* Read global error flags. */ + uint32_t cfdgerfl = p_ctrl->p_reg->CFDGERFL; + + /* Global errors are in the top halfword of canfd_error_t; move and preserve ECC error flags. */ + args.error = ((cfdgerfl & UINT16_MAX) << 16) + ((cfdgerfl >> 16) << 28); + + /* Clear global error flags. */ + p_ctrl->p_reg->CFDGERFL = 0; + + if (args.error & CANFD_ERROR_GLOBAL_MESSAGE_LOST) + { + /* Get lowest RX FIFO with Message Lost condition and clear the flag */ + args.buffer = __CLZ(__RBIT(p_ctrl->p_reg->CFDFMSTS)); + p_ctrl->p_reg->CFDRFSTS[args.buffer] &= ~R_CANFD_CFDRFSTS_RFMLT_Msk; + } + + /* Set channel and context based on selected global error handler channel. */ + args.channel = CANFD_CFG_GLOBAL_ERROR_CH; + args.p_context = p_ctrl->p_context; + + /* Set remaining arguments and call callback */ + r_canfd_call_callback(p_ctrl, &args); +} + /*******************************************************************************************************************//** * Error ISR. * @@ -937,58 +1052,50 @@ void canfd_error_isr (void) FSP_CONTEXT_SAVE /* Get IRQ and context */ - IRQn_Type irq = R_FSP_CurrentIrqGet(); - canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) R_FSP_IsrContextGet(irq); - - can_callback_args_t args = {0U}; - canfd_instance_ctrl_t * p_callback_ctrl; + IRQn_Type irq = R_FSP_CurrentIrqGet(); if (VECTOR_NUMBER_CAN_GLERR == irq) { - args.event = CAN_EVENT_ERR_GLOBAL; - - /* Read global error flags. */ - uint32_t cfdgerfl = R_CANFD->CFDGERFL; - - /* Global errors are in the top halfword of canfd_error_t; move and preserve ECC error flags. */ - args.error = ((cfdgerfl & UINT16_MAX) << 16) + ((cfdgerfl >> 16) << 28); +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 - /* Clear global error flags. */ - R_CANFD->CFDGERFL = 0; - - if (args.error & CANFD_ERROR_GLOBAL_MESSAGE_LOST) + /* If there are seperate instances of CANFD, then loop over each instance to handle the source of the global + * error IRQ. */ + for (uint32_t i = 0; i < BSP_FEATURE_CANFD_NUM_INSTANCES; i++) { - /* Get lowest RX FIFO with Message Lost condition and clear the flag */ - args.buffer = __CLZ(__RBIT(R_CANFD->CFDFMSTS)); - R_CANFD->CFDRFSTS[args.buffer] &= ~R_CANFD_CFDRFSTS_RFMLT_Msk; + if (NULL != gp_ctrl[i]) + { + r_candfd_global_error_handler(i); + } } - /* Choose ctrl block for the selected global error handler channel. */ - p_callback_ctrl = gp_ctrl[CANFD_CFG_GLOBAL_ERROR_CH]; - - /* Set channel and context based on selected global error handler channel. */ - args.channel = CANFD_CFG_GLOBAL_ERROR_CH; - args.p_context = p_callback_ctrl->p_context; +#else + r_candfd_global_error_handler(CANFD_CFG_GLOBAL_ERROR_CH); +#endif } else { + canfd_instance_ctrl_t * p_ctrl = (canfd_instance_ctrl_t *) R_FSP_IsrContextGet(irq); + + can_callback_args_t args = {0U}; + canfd_instance_ctrl_t * p_callback_ctrl; + args.event = CAN_EVENT_ERR_CHANNEL; /* Read and clear channel error flags. */ - uint32_t channel = p_ctrl->p_cfg->channel; - args.error = R_CANFD->CFDC[channel].ERFL & UINT16_MAX; // Upper halfword contains latest CRC - R_CANFD->CFDC[channel].ERFL = 0; + uint32_t interlaced_channel = CANFD_INTER_CH(p_ctrl->p_cfg->channel); + args.error = p_ctrl->p_reg->CFDC[interlaced_channel].ERFL & UINT16_MAX; // Upper halfword contains latest CRC + p_ctrl->p_reg->CFDC[interlaced_channel].ERFL = 0; /* Choose the channel provided by the interrupt context. */ p_callback_ctrl = p_ctrl; - args.channel = channel; + args.channel = interlaced_channel; args.p_context = p_ctrl->p_context; args.buffer = 0U; - } - /* Set remaining arguments and call callback */ - r_canfd_call_callback(p_callback_ctrl, &args); + /* Set remaining arguments and call callback */ + r_canfd_call_callback(p_callback_ctrl, &args); + } /* Clear IRQ */ R_BSP_IrqStatusClear(irq); @@ -998,20 +1105,23 @@ void canfd_error_isr (void) } /*******************************************************************************************************************//** - * Receive ISR. + * Receive FIFO handler. * - * Saves context if RTOS is used, clears interrupts, calls common receive function - * and restores context if RTOS is used. + * Handles the Receive IRQ for a given instance of CANFD. **********************************************************************************************************************/ -void canfd_rx_fifo_isr (void) +static void r_canfd_rx_fifo_handler (uint32_t instance) { - /* Save context if RTOS is used */ - FSP_CONTEXT_SAVE - can_callback_args_t args; +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + R_CANFD_Type * p_reg = + (R_CANFD_Type *) ((uint32_t) R_CANFD0 + (instance * ((uint32_t) R_CANFD1 - (uint32_t) R_CANFD0))); +#else + FSP_PARAMETER_NOT_USED(instance); + R_CANFD_Type * p_reg = R_CANFD; +#endif /* Get lowest FIFO requesting interrupt */ - uint32_t fifo = __CLZ(__RBIT(R_CANFD->CFDRFISTS)); + uint32_t fifo = __CLZ(__RBIT(p_reg->CFDRFISTS)); /* Only perform ISR duties if a FIFO has requested it */ if (fifo < CANFD_PRV_RX_FIFO_MAX) @@ -1021,13 +1131,17 @@ void canfd_rx_fifo_isr (void) args.buffer = fifo + CANFD_PRV_RXMB_MAX; /* Read from the FIFO until it is empty */ - while (!(R_CANFD->CFDFESTS & (1U << fifo))) + while (!(p_reg->CFDFESTS & (1U << fifo))) { /* Get channel associated with the AFL entry */ - args.channel = R_CANFD->CFDRF[fifo].FDSTS_b.RFIFL; +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + args.channel = instance; +#else + args.channel = p_reg->CFDRF[fifo].FDSTS_b.RFIFL; +#endif /* Read and index FIFO */ - r_canfd_mb_read(fifo + CANFD_PRV_RXMB_MAX, &args.frame); + r_canfd_mb_read(p_reg, fifo + CANFD_PRV_RXMB_MAX, &args.frame); /* Set the remaining callback arguments */ args.p_context = gp_ctrl[args.channel]->p_context; @@ -1035,14 +1149,42 @@ void canfd_rx_fifo_isr (void) } /* Clear RX FIFO Interrupt Flag */ - R_CANFD->CFDRFSTS[fifo] &= ~R_CANFD_CFDRFSTS_RFIF_Msk; + p_reg->CFDRFSTS[fifo] &= ~R_CANFD_CFDRFSTS_RFIF_Msk; } - if (!R_CANFD->CFDRFISTS) + if (!p_reg->CFDRFISTS) { /* Clear interrupt in NVIC if there are no pending RX FIFO IRQs */ R_BSP_IrqStatusClear(VECTOR_NUMBER_CAN_RXF); } +} + +/*******************************************************************************************************************//** + * Receive ISR. + * + * Saves context if RTOS is used, clears interrupts, calls common receive function + * and restores context if RTOS is used. + **********************************************************************************************************************/ +void canfd_rx_fifo_isr (void) +{ + /* Save context if RTOS is used */ + FSP_CONTEXT_SAVE + +#if BSP_FEATURE_CANFD_NUM_INSTANCES > 1 + + /* If there are seperate instances of CANFD, then loop over each instance to handle the source of the global + * receive IRQ. */ + for (uint32_t i = 0; i < BSP_FEATURE_CANFD_NUM_INSTANCES; i++) + { + if (NULL != gp_ctrl[i]) + { + r_canfd_rx_fifo_handler(i); + } + } + +#else + r_canfd_rx_fifo_handler(0U); +#endif /* Restore context if RTOS is used */ FSP_CONTEXT_RESTORE @@ -1068,42 +1210,44 @@ void canfd_channel_tx_isr (void) args.channel = channel; args.p_context = p_ctrl->p_context; + uint32_t interlaced_channel = CANFD_INTER_CH(channel); + /* Check the byte of CFDGTINTSTS0 that corresponds to the interrupting channel */ - uint32_t cfdgtintsts = *((uint8_t *) (&R_CANFD->CFDGTINTSTS0) + channel); + uint32_t cfdgtintsts = *((volatile uint8_t *) (&p_ctrl->p_reg->CFDGTINTSTS0) + interlaced_channel); while (cfdgtintsts) { uint32_t txmb; volatile uint32_t * cfdtm_sts; - channel <<= 1; + interlaced_channel <<= 1; /* Get relevant TX status register bank */ if (cfdgtintsts & R_CANFD_CFDGTINTSTS0_TSIF0_Msk) { - cfdtm_sts = (volatile uint32_t *) &R_CANFD->CFDTMTCSTS[channel]; + cfdtm_sts = (volatile uint32_t *) &p_ctrl->p_reg->CFDTMTCSTS[interlaced_channel]; args.event = CAN_EVENT_TX_COMPLETE; } else { - cfdtm_sts = (volatile uint32_t *) &R_CANFD->CFDTMTASTS[channel]; + cfdtm_sts = (volatile uint32_t *) &p_ctrl->p_reg->CFDTMTASTS[interlaced_channel]; args.event = CAN_EVENT_TX_ABORTED; } - channel >>= 1; + interlaced_channel >>= 1; /* Calculate lowest TXMB with the specified event */ txmb = __CLZ(__RBIT(*cfdtm_sts)); txmb = (txmb < 8) ? txmb : __CLZ(__RBIT(*(cfdtm_sts + 1))) + CANFD_PRV_TXMB_OFFSET; /* Clear TX complete/abort flags */ - R_CANFD->CFDTMSTS_b[txmb + (CANFD_PRV_TXMB_CHANNEL_OFFSET * channel)].TMTRF = 0; + p_ctrl->p_reg->CFDTMSTS_b[txmb + (CANFD_PRV_TXMB_CHANNEL_OFFSET * interlaced_channel)].TMTRF = 0; /* Set the callback arguments */ args.buffer = txmb; r_canfd_call_callback(p_ctrl, &args); /* Check for more interrupts on this channel */ - cfdgtintsts = *((uint8_t *) (&R_CANFD->CFDGTINTSTS0) + channel); + cfdgtintsts = *((volatile uint8_t *) (&p_ctrl->p_reg->CFDGTINTSTS0) + interlaced_channel); } /* Clear interrupt */ @@ -1120,7 +1264,7 @@ void canfd_channel_tx_isr (void) **********************************************************************************************************************/ static void r_canfd_mode_transition (canfd_instance_ctrl_t * p_ctrl, can_operation_mode_t operation_mode) { - uint32_t channel = p_ctrl->p_cfg->channel; + uint32_t interlaced_channel = CANFD_INTER_CH(p_ctrl->p_cfg->channel); /* Get bit 7 from operation_mode to determine if this is a global mode change request */ bool global_mode = (bool) (operation_mode >> 7); @@ -1128,9 +1272,9 @@ static void r_canfd_mode_transition (canfd_instance_ctrl_t * p_ctrl, can_operati if (global_mode) { - uint32_t cfdgctr = R_CANFD->CFDGCTR; + uint32_t cfdgctr = p_ctrl->p_reg->CFDGCTR; - r_canfd_mode_ctr_set(&R_CANFD->CFDGCTR, operation_mode); + r_canfd_mode_ctr_set(&p_ctrl->p_reg->CFDGCTR, operation_mode); /* If CANFD is transitioning out of Reset the FIFOs need to be enabled. */ if ((cfdgctr & R_CANFD_CFDGSTS_GRSTSTS_Msk) && !(operation_mode & CAN_OPERATION_MODE_RESET)) @@ -1142,27 +1286,28 @@ static void r_canfd_mode_transition (canfd_instance_ctrl_t * p_ctrl, can_operati /* Enable RX FIFOs */ for (uint32_t i = 0; i < CANFD_PRV_RX_FIFO_MAX; i++) { - R_CANFD->CFDRFCC[i] = p_global_cfg->rx_fifo_config[i]; + p_ctrl->p_reg->CFDRFCC[i] = p_global_cfg->rx_fifo_config[i]; } } } else { - uint32_t cfdcnctr = R_CANFD->CFDC[channel].CTR; + uint32_t cfdcnctr = p_ctrl->p_reg->CFDC[interlaced_channel].CTR; if (((cfdcnctr & R_CANFD_CFDC_CTR_CSLPR_Msk) && (!(CAN_OPERATION_MODE_RESET & operation_mode))) || ((!(cfdcnctr & CANFD_PRV_CTR_RESET_BIT)) && (CAN_OPERATION_MODE_SLEEP == operation_mode))) { /* Transition channel to Reset if a transition to/from Sleep is requested (see Section 32.3.3 "Channel * Modes" in the RA6M5 User's Manual (R01UH0891EJ0100) for details) */ - r_canfd_mode_ctr_set(&R_CANFD->CFDC[channel].CTR, CAN_OPERATION_MODE_RESET); + r_canfd_mode_ctr_set(&p_ctrl->p_reg->CFDC[interlaced_channel].CTR, CAN_OPERATION_MODE_RESET); } /* Request transition to selected mode */ - r_canfd_mode_ctr_set(&R_CANFD->CFDC[channel].CTR, operation_mode); + r_canfd_mode_ctr_set(&p_ctrl->p_reg->CFDC[interlaced_channel].CTR, operation_mode); } - p_ctrl->operation_mode = (can_operation_mode_t) (R_CANFD->CFDC[channel].CTR & CANFD_PRV_CTR_MODE_MASK); + p_ctrl->operation_mode = + (can_operation_mode_t) (p_ctrl->p_reg->CFDC[interlaced_channel].CTR & CANFD_PRV_CTR_MODE_MASK); } /*******************************************************************************************************************//** diff --git a/ra/fsp/src/r_cgc/r_cgc.c b/ra/fsp/src/r_cgc/r_cgc.c index 4287005f2..8850e0528 100644 --- a/ra/fsp/src/r_cgc/r_cgc.c +++ b/ra/fsp/src/r_cgc/r_cgc.c @@ -49,6 +49,10 @@ /* PLLMULNF in PLLCCR starts at bit 6. */ #define CGC_PRV_PLLCCR_PLLMULNF_BIT (6U) +/* PLLMUL in PLLCCR is 8 bits wide. */ + #define CGC_PRV_PLLCCR_PLLMUL_MASK (0xFFU) +#elif 4U == BSP_FEATURE_CGC_PLLCCR_TYPE + /* PLLMUL in PLLCCR is 8 bits wide. */ #define CGC_PRV_PLLCCR_PLLMUL_MASK (0xFFU) #else @@ -63,6 +67,9 @@ /* PLSRCSEL in PLLCCR starts at bit 4. */ #define CGC_PRV_PLLCCR_PLSRCSEL_BIT (4U) +/* PLSET in PLLCCR starts at bit 6. */ +#define CGC_PRV_PLLCCR_PLSET_BIT (6U) + /* PLLMUL in PLLCCR2 is 5 bits wide. */ #define CGC_PRV_PLLCCR2_PLLMUL_MASK (0x1FU) @@ -121,6 +128,8 @@ /* Specifications for PLL on MCUs with PLLCCR. */ #if 3U == BSP_FEATURE_CGC_PLLCCR_TYPE #define CGC_PRV_PLLCCR_PLL_MIN_HZ (40000000U) +#elif 4U == BSP_FEATURE_CGC_PLLCCR_TYPE + #define CGC_PRV_PLLCCR_PLL_MIN_HZ (11000000U) #else #define CGC_PRV_PLLCCR_PLL_MIN_HZ (120000000U) #endif @@ -141,6 +150,9 @@ /* Mask of the uppermost bit of all dividers in SCKDIVCR that are valid when oscillation stop detection is enabled. */ #define CGC_PRV_SCKDIVCR_UPPER_BIT (BSP_PRV_SCKDIVCR_MASK & 0x44444444U) +/* Offset factor to convert PLL MUL values to register values. */ +#define CGC_PRV_PLLCCR_TYPE4_PLLMUL_OFFSET (574U) + /*********************************************************************************************************************** * Typedef definitions **********************************************************************************************************************/ @@ -1778,6 +1790,19 @@ static fsp_err_t r_cgc_pll_parameter_check (cgc_pll_cfg_t const * const p_pll_cf * 180.50 is larger than 180.66 in the integer representation of the enum. */ FSP_ASSERT(p_pll_cfg->multiplier >= CGC_PLL_MUL_26_0); FSP_ASSERT(p_pll_cfg->multiplier <= CGC_PLL_MUL_180_5); + #elif 4U == BSP_FEATURE_CGC_PLLCCR_TYPE + + /* Ensure PLL configuration is supported on this MCU (MREF_INTERNAL_006). */ + + /* PLLCCR clock source can only be the subclock. */ + FSP_ASSERT(CGC_CLOCK_SUBCLOCK == p_pll_cfg->source_clock); + + /* Divider of 2 is the only supported value for PLLCCR. */ + FSP_ASSERT(CGC_PLL_DIV_2 == p_pll_cfg->divider); + + /* PLLCCR multiplier must be between 732 and 781. */ + FSP_ASSERT(p_pll_cfg->multiplier >= CGC_PLL_MUL_732_0); + FSP_ASSERT(p_pll_cfg->multiplier <= CGC_PLL_MUL_781_0); #else /* Ensure PLL configuration is supported on this MCU (see Section 8.2.3 "PLL Clock Control Register 2 (PLLCCR2)" in @@ -1915,7 +1940,7 @@ static fsp_err_t r_cgc_pll_hz_calculate (cgc_pll_cfg_t const * const p_pll_cfg, FSP_ASSERT(pll_hz >= CGC_PRV_PLLCCR_PLL_MIN_HZ); FSP_ASSERT(pll_hz <= BSP_FEATURE_CGC_PLLCCR_MAX_HZ); #endif - #else // 2U == BSP_FEATURE_CGC_PLLCCR_TYPE + #else // 2U == BSP_FEATURE_CGC_PLLCCR_TYPE || 4U == BSP_FEATURE_CGC_PLLCCR_TYPE FSP_PARAMETER_NOT_USED(pll_out); uint32_t multiplier = (p_pll_cfg->multiplier + 1U) >> 1; @@ -1990,6 +2015,12 @@ static uint32_t r_cgc_pllccr_calculate (cgc_pll_cfg_t const * const p_pll_cfg) ((pllmulnf & CGC_PRV_PLLCCR_PLLMULNF_MASK) << CGC_PRV_PLLCCR_PLLMULNF_BIT) | (uint32_t) (plsrcsel << CGC_PRV_PLLCCR_PLSRCSEL_BIT)) | plidiv); + return register_value; + #elif 4U == BSP_FEATURE_CGC_PLLCCR_TYPE + uint8_t pllmul = (uint8_t) ((p_pll_cfg->multiplier >> 1) - CGC_PRV_PLLCCR_TYPE4_PLLMUL_OFFSET); + + uint32_t register_value = ((pllmul & CGC_PRV_PLLCCR_PLLMUL_MASK) << CGC_PRV_PLLCCR_PLLMUL_BIT); + return register_value; #else // 2U == BSP_FEATURE_CGC_PLLCCR_TYPE uint8_t pllmul = (uint8_t) p_pll_cfg->multiplier >> 1; diff --git a/ra/fsp/src/r_ctsu/r_ctsu.c b/ra/fsp/src/r_ctsu/r_ctsu.c index 24ca75cfc..c3fe74bbc 100644 --- a/ra/fsp/src/r_ctsu/r_ctsu.c +++ b/ra/fsp/src/r_ctsu/r_ctsu.c @@ -56,7 +56,6 @@ #define CTSU_TUNING_MIN (0x0000) #define CTSU_TUNING_VALUE_SELF (15360) #define CTSU_TUNING_VALUE_MUTUAL (10240) -#define CTSU_TUNING_OT_COUNT (25) #if (BSP_FEATURE_CTSU_VERSION == 2) #define CTSU_SST_RECOMMEND (0x1F) // The recommend value of SST @@ -307,11 +306,11 @@ static void ctsu_correction_fleq(ctsu_correction_multi_t * p_multi, uint16_t * p static void ctsu_correction_multi(ctsu_correction_multi_t * p_multi, uint16_t * p_pri, uint16_t * p_snd); #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) -static void ctsu_correction_scan_start(void); -static void ctsu_correction_data_get(ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data); +static void ctsu_correction_scan_start(void); +static fsp_err_t ctsu_correction_data_get(ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data); #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) -static void ctsu_correction_calib_rtrim(ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data); +static fsp_err_t ctsu_correction_calib_rtrim(ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data); #endif #endif @@ -356,7 +355,7 @@ static fsp_err_t ctsu_diag_data_get1(void); static void ctsu_diag_regi_store2(void); static void ctsu_diag_regi_restore2(void); -static void ctsu_diag_output_voltage_scan_start(ctsu_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t ctsu_diag_output_voltage_scan_start(ctsu_instance_ctrl_t * const p_instance_ctrl); static fsp_err_t ctsu_diag_output_voltage_result(void); static void ctsu_diag_over_voltage_scan_start(void); @@ -388,7 +387,7 @@ static void ctsu_diag_cfc_gain_data_get(void); #endif -static void ctsu_diag_scan_start2(ctsu_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t ctsu_diag_scan_start2(ctsu_instance_ctrl_t * const p_instance_ctrl); static fsp_err_t ctsu_diag_data_get2(uint16_t * p_data); #endif @@ -398,8 +397,11 @@ static fsp_err_t ctsu_diag_data_get2(uint16_t * p_data); * Private global variables **********************************************************************************************************************/ -static uint16_t g_ctsu_element_index = 0; -static uint8_t g_ctsu_tuning_count[CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MUTUAL_ELEMENTS]; +static uint16_t g_ctsu_element_index = 0; +static uint8_t g_ctsu_element_complete_flag[CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MUTUAL_ELEMENTS]; +#if (BSP_FEATURE_CTSU_VERSION == 2) +static uint8_t g_ctsu_frequency_complete_flag[CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MUTUAL_ELEMENTS]; +#endif static int32_t g_ctsu_tuning_diff[CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MUTUAL_ELEMENTS]; static ctsu_ctsuwr_t g_ctsu_ctsuwr[(CTSU_CFG_NUM_SELF_ELEMENTS + CTSU_CFG_NUM_MUTUAL_ELEMENTS) * CTSU_CFG_NUM_SUMULTI]; #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) @@ -434,7 +436,9 @@ static ctsu_corrcfc_info_t g_ctsu_corrcfc_info; static ctsu_diag_info_t g_ctsu_diag_info; static ctsu_diag_save_reg_t g_ctsu_diag_reg; #endif - + #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) +static uint32_t g_ctsu_temp_reg_ctsucra; + #endif #if (BSP_FEATURE_CTSU_VERSION == 2) #if (CTSU_CFG_NUM_SELF_ELEMENTS != 0) uint8_t g_ctsu_selected_freq_self[CTSU_CFG_NUM_SELF_ELEMENTS]; @@ -443,7 +447,6 @@ uint8_t g_ctsu_selected_freq_self[CTSU_CFG_NUM_SELF_ELEMENTS]; uint8_t g_ctsu_selected_freq_mutual[CTSU_CFG_NUM_MUTUAL_ELEMENTS]; #endif #endif - #endif static ioport_instance_ctrl_t g_ctsu_tscap_ioport_ctrl; @@ -633,7 +636,10 @@ fsp_err_t R_CTSU_Open (ctsu_ctrl_t * const p_ctrl, ctsu_cfg_t const * const p_cf #endif } #endif - p_instance_ctrl->p_tuning_count = &g_ctsu_tuning_count[g_ctsu_element_index]; + p_instance_ctrl->p_element_complete_flag = &g_ctsu_element_complete_flag[g_ctsu_element_index]; +#if (BSP_FEATURE_CTSU_VERSION == 2) + p_instance_ctrl->p_frequency_complete_flag = &g_ctsu_frequency_complete_flag[g_ctsu_element_index]; +#endif p_instance_ctrl->p_tuning_diff = &g_ctsu_tuning_diff[g_ctsu_element_index]; p_instance_ctrl->p_ctsuwr = &g_ctsu_ctsuwr[g_ctsu_element_index * CTSU_CFG_NUM_SUMULTI]; g_ctsu_element_index = (uint8_t) (g_ctsu_element_index + p_instance_ctrl->num_elements); @@ -718,8 +724,11 @@ fsp_err_t R_CTSU_Open (ctsu_ctrl_t * const p_ctrl, ctsu_cfg_t const * const p_cf #endif for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) { - p_instance_ctrl->p_tuning_count[element_id] = 0; - p_instance_ctrl->p_tuning_diff[element_id] = 0; + p_instance_ctrl->p_element_complete_flag[element_id] = 0; +#if (BSP_FEATURE_CTSU_VERSION == 2) + p_instance_ctrl->p_frequency_complete_flag[element_id] = 0; +#endif + p_instance_ctrl->p_tuning_diff[element_id] = 0; element_cfgs = (p_cfg->p_elements + element_id); #if (BSP_FEATURE_CTSU_VERSION == 2) if (CTSU_MODE_CURRENT_SCAN == p_cfg->md) @@ -1145,7 +1154,7 @@ fsp_err_t R_CTSU_ScanStart (ctsu_ctrl_t * const p_ctrl) #if (CTSU_CFG_DIAG_SUPPORT_ENABLE == 1) if (CTSU_MODE_DIAGNOSIS_SCAN == p_instance_ctrl->md) { - ctsu_diag_scan_start2(p_instance_ctrl); + err = ctsu_diag_scan_start2(p_instance_ctrl); } #endif #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) @@ -1226,6 +1235,7 @@ fsp_err_t R_CTSU_ScanStart (ctsu_ctrl_t * const p_ctrl) * @retval FSP_ERR_CTSU_SCANNING Scanning this instance. * @retval FSP_ERR_CTSU_INCOMPLETE_TUNING Incomplete initial offset tuning. * @retval FSP_ERR_CTSU_DIAG_NOT_YET Diagnosis of data collected no yet. + * @retval FSP_ERR_ABORTED Operate error of Diagnosis ADC data collection ,since ADC use other **********************************************************************************************************************/ fsp_err_t R_CTSU_DataGet (ctsu_ctrl_t * const p_ctrl, uint16_t * p_data) { @@ -1244,7 +1254,7 @@ fsp_err_t R_CTSU_DataGet (ctsu_ctrl_t * const p_ctrl, uint16_t * p_data) #if (CTSU_CFG_TEMP_CORRECTION_SUPPORT == 1) if (CTSU_MODE_CORRECTION_SCAN == p_instance_ctrl->md) { - ctsu_correction_data_get(p_instance_ctrl, p_data); + err = ctsu_correction_data_get(p_instance_ctrl, p_data); p_instance_ctrl->state = CTSU_STATE_IDLE; return err; @@ -1260,6 +1270,10 @@ fsp_err_t R_CTSU_DataGet (ctsu_ctrl_t * const p_ctrl, uint16_t * p_data) { err = FSP_ERR_CTSU_DIAG_NOT_YET; } + else if (FSP_ERR_ABORTED == err) + { + err = FSP_ERR_ABORTED; + } else { err = FSP_SUCCESS; @@ -1385,8 +1399,11 @@ fsp_err_t R_CTSU_OffsetTuning (ctsu_ctrl_t * const p_ctrl) for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) { /* Counter clear for re-offset tuning */ - *(p_instance_ctrl->p_tuning_count + element_id) = 0; - *(p_instance_ctrl->p_tuning_diff + element_id) = 0; + *(p_instance_ctrl->p_element_complete_flag + element_id) = 0; +#if (BSP_FEATURE_CTSU_VERSION == 2) + *(p_instance_ctrl->p_frequency_complete_flag + element_id) = 0; +#endif + *(p_instance_ctrl->p_tuning_diff + element_id) = 0; } } @@ -2226,7 +2243,7 @@ void ctsu_initial_offset_tuning (ctsu_instance_ctrl_t * const p_instance_ctrl) /* element_id through each element for control block */ for (element_id = 0; element_id < p_instance_ctrl->num_elements; element_id++) { - if (CTSU_TUNING_OT_COUNT != *(p_instance_ctrl->p_tuning_count + element_id)) + if (0 == *(p_instance_ctrl->p_element_complete_flag + element_id)) { #if (BSP_FEATURE_CTSU_VERSION == 1) if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) @@ -2316,63 +2333,66 @@ void ctsu_initial_offset_tuning (ctsu_instance_ctrl_t * const p_instance_ctrl) element_top = (uint16_t) (element_id * CTSU_CFG_NUM_SUMULTI); for (i = 0; i < CTSU_CFG_NUM_SUMULTI; i++) { - if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) - { - target_val = (p_instance_ctrl->tuning_self_target_value / 2); - } - else + /* Adjust only frequencies for which offset tuning is not completed */ + if (0 == (p_instance_ctrl->p_frequency_complete_flag[element_id] & (1 << i))) { - target_val = (p_instance_ctrl->tuning_mutual_target_value / 2); - } + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) + { + target_val = (p_instance_ctrl->tuning_self_target_value / 2); + } + else + { + target_val = (p_instance_ctrl->tuning_mutual_target_value / 2); + } - if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) - { - corr_data[i] = p_instance_ctrl->p_self_corr[element_top + i]; - } - else - { - corr_data[i] = p_instance_ctrl->p_mutual_pri_corr[element_top + i]; - } + if (CTSU_MODE_SELF_MULTI_SCAN == p_instance_ctrl->md) + { + corr_data[i] = p_instance_ctrl->p_self_corr[element_top + i]; + } + else + { + corr_data[i] = p_instance_ctrl->p_mutual_pri_corr[element_top + i]; + } - snum = (p_instance_ctrl->p_ctsuwr[(element_id * CTSU_CFG_NUM_SUMULTI)].ctsuso >> 10) & - CTSU_SNUM_MAX; - target_val = (uint16_t) (((uint32_t) target_val * (snum + 1)) / (CTSU_SNUM_RECOMMEND + 1)); - offset_unit = (int32_t) ((CTSU_CORRECTION_OFFSET_UNIT * (snum + 1)) / (CTSU_SNUM_RECOMMEND + 1)); + snum = (p_instance_ctrl->p_ctsuwr[(element_id * CTSU_CFG_NUM_SUMULTI)].ctsuso >> 10) & + CTSU_SNUM_MAX; + target_val = (uint16_t) (((uint32_t) target_val * (snum + 1)) / (CTSU_SNUM_RECOMMEND + 1)); + offset_unit = (int32_t) ((CTSU_CORRECTION_OFFSET_UNIT * (snum + 1)) / (CTSU_SNUM_RECOMMEND + 1)); - /* Calculate CTSUSO equivalent difference between current value and target value */ - diff = (int32_t) ((int32_t) corr_data[i] - (int32_t) target_val) / - (offset_unit >> p_instance_ctrl->range); + /* Calculate CTSUSO equivalent difference between current value and target value */ + diff = (int32_t) ((int32_t) corr_data[i] - (int32_t) target_val) / + (offset_unit >> p_instance_ctrl->range); - ctsuso = (int32_t) (p_instance_ctrl->p_ctsuwr[element_top + i].ctsuso & CTSU_TUNING_MAX); - ctsuso += diff; + ctsuso = (int32_t) (p_instance_ctrl->p_ctsuwr[element_top + i].ctsuso & CTSU_TUNING_MAX); + ctsuso += diff; - /* If the CTSUSO exceeds the minimum value or the maximum value, tuning complete */ - if (ctsuso < 0) - { - ctsuso = 0; - complete_flag++; - } - else if (ctsuso > CTSU_TUNING_MAX) - { - ctsuso = CTSU_TUNING_MAX; - complete_flag++; - } - else - { - /* If the difference is large, tuning value may not be able to match, so create the next opportunity */ - if (0 == diff) + /* If the CTSUSO exceeds the minimum value or the maximum value, tuning complete */ + if (ctsuso < 0) + { + ctsuso = 0; + p_instance_ctrl->p_frequency_complete_flag[element_id] += (uint8_t) (1 << i); + } + else if (ctsuso > CTSU_TUNING_MAX) { - complete_flag++; + ctsuso = CTSU_TUNING_MAX; + p_instance_ctrl->p_frequency_complete_flag[element_id] += (uint8_t) (1 << i); } else { - (*(p_instance_ctrl->p_tuning_count + element_id))++; + /* If the difference is large, tuning value may not be able to match, so create the next opportunity */ + if (0 == diff) + { + p_instance_ctrl->p_frequency_complete_flag[element_id] += (uint8_t) (1 << i); + } } + + /* Set the result of the calculated CTSUSO */ + p_instance_ctrl->p_ctsuwr[element_top + i].ctsuso &= (uint32_t) (~CTSU_TUNING_MAX); + p_instance_ctrl->p_ctsuwr[element_top + i].ctsuso |= (uint32_t) ctsuso; } - /* Set the result of the calculated CTSUSO */ - p_instance_ctrl->p_ctsuwr[element_top + i].ctsuso &= (uint32_t) (~CTSU_TUNING_MAX); - p_instance_ctrl->p_ctsuwr[element_top + i].ctsuso |= (uint32_t) ctsuso; + /* Add completion status for each frequency */ + complete_flag += ((p_instance_ctrl->p_frequency_complete_flag[element_id] >> i) & 1); } #endif } @@ -2383,10 +2403,11 @@ void ctsu_initial_offset_tuning (ctsu_instance_ctrl_t * const p_instance_ctrl) if (CTSU_CFG_NUM_SUMULTI == complete_flag) { - complete_flag = 0; num_complete++; - *(p_instance_ctrl->p_tuning_count + element_id) = CTSU_TUNING_OT_COUNT; + *(p_instance_ctrl->p_element_complete_flag + element_id) = 1; } + + complete_flag = 0; } if (num_complete == p_instance_ctrl->num_elements) @@ -3186,6 +3207,8 @@ void ctsu_correction_measurement (ctsu_instance_ctrl_t * const p_instance_ctrl, ***********************************************************************************************************************/ void ctsu_correction_scan_start (void) { + g_ctsu_temp_reg_ctsucra = R_CTSU->CTSUCRA; + R_CTSU->CTSUCRA_b.MD0 = 1; R_CTSU->CTSUCRA_b.MD1 = 0; R_CTSU->CTSUCRA_b.MD2 = 0; @@ -3248,15 +3271,19 @@ void ctsu_correction_scan_start (void) /*********************************************************************************************************************** * ctsu_correction_data_get ***********************************************************************************************************************/ -void ctsu_correction_data_get (ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data) +fsp_err_t ctsu_correction_data_get (ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data) { - uint32_t i; - uint32_t j; - uint16_t base_value; - uint16_t base_conv_dac; - int32_t x0; - int32_t x1; - int32_t y0; + #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) + adc_instance_t const * p_adc = p_instance_ctrl->p_ctsu_cfg->p_adc_instance; + #endif + uint32_t i; + uint32_t j; + uint16_t base_value; + uint16_t base_conv_dac; + int32_t x0; + int32_t x1; + int32_t y0; + fsp_err_t err = FSP_SUCCESS; if (g_ctsu_correction_info.scan_index < CTSU_CORRECTION_POINT_NUM) { @@ -3321,7 +3348,16 @@ void ctsu_correction_data_get (ctsu_instance_ctrl_t * const p_instance_ctrl, uin g_ctsu_correction_info.update_counter = 0; #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) - ctsu_correction_calib_rtrim(p_instance_ctrl, p_data); + err = ctsu_correction_calib_rtrim(p_instance_ctrl, p_data); + if (FSP_ERR_ALREADY_OPEN != err) + { + p_adc->p_api->close(p_adc->p_ctrl); + } + + if (FSP_SUCCESS != err) + { + err = FSP_ERR_ABORTED; + } #endif } else @@ -3329,6 +3365,10 @@ void ctsu_correction_data_get (ctsu_instance_ctrl_t * const p_instance_ctrl, uin /* Indicates that ADC measurement was not performed. */ *p_data = CTSU_COUNT_MAX; } + + R_CTSU->CTSUCRA = g_ctsu_temp_reg_ctsucra; + + return err; } #if (CTSU_CFG_CALIB_RTRIM_SUPPORT == 1) @@ -3336,7 +3376,7 @@ void ctsu_correction_data_get (ctsu_instance_ctrl_t * const p_instance_ctrl, uin /*********************************************************************************************************************** * ctsu_correction_calib_rtrim ***********************************************************************************************************************/ -void ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data) +fsp_err_t ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl, uint16_t * p_data) { adc_status_t status; adc_instance_t const * p_adc = p_instance_ctrl->p_ctsu_cfg->p_adc_instance; @@ -3347,10 +3387,14 @@ void ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl, int16_t diff; int16_t dir = 0; uint16_t comp = 0; + fsp_err_t err; /* Initialize ADC for CTSU TSCAP */ - p_adc->p_api->open(p_adc->p_ctrl, p_adc->p_cfg); - p_adc->p_api->scanCfg(p_adc->p_ctrl, p_adc->p_channel_cfg); + err = p_adc->p_api->open(p_adc->p_ctrl, p_adc->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + err = p_adc->p_api->scanCfg(p_adc->p_ctrl, p_adc->p_channel_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); R_ADC0->ADSSTRL = CTSU_CALIB_ADSSTRL; /* Self single scan mode */ @@ -3383,17 +3427,20 @@ void ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl, for (i = 0; i < CTSU_CALIB_AVERAGE_TIME; i++) { /* Software trigger start scan */ - p_adc->p_api->scanStart(p_adc->p_ctrl); + err = p_adc->p_api->scanStart(p_adc->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); /* Wait for conversion to complete. */ status.state = ADC_STATE_SCAN_IN_PROGRESS; while (ADC_STATE_SCAN_IN_PROGRESS == status.state) { - p_adc->p_api->scanStatusGet(p_adc->p_ctrl, &status); + err = p_adc->p_api->scanStatusGet(p_adc->p_ctrl, &status); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); } /* Read A/D data then scan normal end */ - p_adc->p_api->read(p_adc->p_ctrl, ADC_CHANNEL_16, &adctdr_result); + err = p_adc->p_api->read(p_adc->p_ctrl, ADC_CHANNEL_16, &adctdr_result); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); adctdr_sum += adctdr_result; } @@ -3442,6 +3489,8 @@ void ctsu_correction_calib_rtrim (ctsu_instance_ctrl_t * const p_instance_ctrl, /* Close ADC for CTSU TSCAP */ p_adc->p_api->close(p_adc->p_ctrl); + + return err; } #endif @@ -4953,7 +5002,7 @@ static void ctsu_diag_dac_initial_tuning (void) if (CTSU_CFG_NUM_SUMULTI == complete_flag) { - g_ctsu_diag_info.tuning_diff = CTSU_TUNING_OT_COUNT; + g_ctsu_diag_info.tuning_diff = 0; g_ctsu_diag_info.so0_4uc_val = ctsuso; g_ctsu_diag_info.dac_init = 3; g_ctsu_diag_info.tuning = CTSU_TUNING_COMPLETE; @@ -5119,8 +5168,11 @@ static fsp_err_t ctsu_diag_dac_result (void) /*********************************************************************************************************************** * ctsu_diag_scan_start2 ***********************************************************************************************************************/ -static void ctsu_diag_scan_start2 (ctsu_instance_ctrl_t * const p_instance_ctrl) +static fsp_err_t ctsu_diag_scan_start2 (ctsu_instance_ctrl_t * const p_instance_ctrl) { + adc_instance_t const * p_adc = p_instance_ctrl->p_ctsu_cfg->p_adc_instance; + fsp_err_t err = FSP_SUCCESS; + /* initial state change*/ if (CTSU_DIAG_INIT == g_ctsu_diag_info.state) { @@ -5133,8 +5185,36 @@ static void ctsu_diag_scan_start2 (ctsu_instance_ctrl_t * const p_instance_ctrl) /* scan register setting */ if (CTSU_DIAG_OUTPUT_VOLTAGE == g_ctsu_diag_info.state) { - ctsu_diag_output_voltage_scan_start(p_instance_ctrl); - g_ctsu_diag_info.state = CTSU_DIAG_OVER_VOLTAGE; + err = ctsu_diag_output_voltage_scan_start(p_instance_ctrl); + if (FSP_SUCCESS == err) + { + g_ctsu_diag_info.state = CTSU_DIAG_OVER_VOLTAGE; + } + else + { + if (FSP_ERR_ALREADY_OPEN != err) + { + p_adc->p_api->close(p_adc->p_ctrl); + } + + err = FSP_SUCCESS; + + g_ctsu_diag_info.state = CTSU_DIAG_OUTPUT_VOLTAGE; + R_CTSU->CTSUCRA_b.ATUNE1 = 0; + R_CTSU->CTSUCRA_b.ATUNE2 = 0; + R_CTSU->CTSUCRA_b.LOAD = 0; + R_CTSU->CTSUMCH_b.MCA0 = 1; + R_CTSU->CTSUMCH_b.MCA1 = 0; + R_CTSU->CTSUMCH_b.MCA2 = 0; + R_CTSU->CTSUMCH_b.MCA3 = 0; + R_CTSU->CTSUCHACA = g_ctsu_diag_info.chaca; + R_CTSU->CTSUCHACB = g_ctsu_diag_info.chacb; + R_CTSU->CTSUCHTRC0 = 0; + R_CTSU->CTSUCHTRC1 = 0; + R_CTSU->CTSUCHTRC2 = 0; + R_CTSU->CTSUCHTRC3 = 0; + R_CTSU->CTSUCHTRC4 = 0; + } } if (CTSU_DIAG_OVER_VOLTAGE == g_ctsu_diag_info.state) @@ -5179,6 +5259,8 @@ static void ctsu_diag_scan_start2 (ctsu_instance_ctrl_t * const p_instance_ctrl) ctsu_diag_cfc_gain_scan_start(); } #endif + + return err; } /*********************************************************************************************************************** @@ -5285,6 +5367,11 @@ static fsp_err_t ctsu_diag_data_get2 (uint16_t * p_data) { err = FSP_SUCCESS; } + else if (CTSU_DIAG_OUTPUT_VOLTAGE == g_ctsu_diag_info.state) + { + err = FSP_ERR_ABORTED; + g_ctsu_diag_info.state = CTSU_DIAG_INIT; + } else { err = FSP_ERR_CTSU_DIAG_NOT_YET; @@ -5322,15 +5409,19 @@ static void ctsu_diag_regi_restore2 (void) R_CTSU->CTSUSUCLKB = g_ctsu_diag_reg.ctsusuclkb; } -static void ctsu_diag_output_voltage_scan_start (ctsu_instance_ctrl_t * const p_instance_ctrl) +static fsp_err_t ctsu_diag_output_voltage_scan_start (ctsu_instance_ctrl_t * const p_instance_ctrl) { uint8_t k; adc_status_t status; adc_instance_t const * p_adc = p_instance_ctrl->p_ctsu_cfg->p_adc_instance; + fsp_err_t err; /* Initialize ADC for CTSU TSCAP */ - p_adc->p_api->open(p_adc->p_ctrl, p_adc->p_cfg); - p_adc->p_api->scanCfg(p_adc->p_ctrl, p_adc->p_channel_cfg); + err = p_adc->p_api->open(p_adc->p_ctrl, p_adc->p_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); + + err = p_adc->p_api->scanCfg(p_adc->p_ctrl, p_adc->p_channel_cfg); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); R_ADC0->ADSSTRL = CTSU_DIAG_ADSSTRL; /* CTSU setting */ @@ -5456,20 +5547,25 @@ static void ctsu_diag_output_voltage_scan_start (ctsu_instance_ctrl_t * const p_ R_CTSU->CTSUCALIB_b.DRV = 1; /* Measure TSCAP Voltage with ADC */ - p_adc->p_api->scanStart(p_adc->p_ctrl); + err = p_adc->p_api->scanStart(p_adc->p_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); /* Wait for conversion to complete. */ status.state = ADC_STATE_SCAN_IN_PROGRESS; while (ADC_STATE_SCAN_IN_PROGRESS == status.state) { - p_adc->p_api->scanStatusGet(p_adc->p_ctrl, &status); + err = p_adc->p_api->scanStatusGet(p_adc->p_ctrl, &status); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); } - p_adc->p_api->read(p_adc->p_ctrl, ADC_CHANNEL_16, &g_ctsu_diag_info.output_voltage_cnt[k]); + err = p_adc->p_api->read(p_adc->p_ctrl, ADC_CHANNEL_16, &g_ctsu_diag_info.output_voltage_cnt[k]); + FSP_ERROR_RETURN(FSP_SUCCESS == err, err); } /* Close ADC for CTSU TSCAP */ p_adc->p_api->close(p_adc->p_ctrl); + + return err; } static fsp_err_t ctsu_diag_output_voltage_result (void) @@ -5794,6 +5890,9 @@ static void ctsu_diag_current_source_scan_start (void) R_CTSU->CTSUCALIB_b.DACMSEL = 1; R_CTSU->CTSUCALIB_b.DACCARRY = 1; + R_CTSU->CTSUCRA_b.DCMODE = 0; + R_CTSU->CTSUCRA_b.DCBACK = 0; + if (15 >= g_ctsu_diag_info.loop_count) { /* Upper Current source setting (10uA) */ diff --git a/ra/fsp/src/r_dac/r_dac.c b/ra/fsp/src/r_dac/r_dac.c index 6f22349c2..7545779a2 100644 --- a/ra/fsp/src/r_dac/r_dac.c +++ b/ra/fsp/src/r_dac/r_dac.c @@ -33,13 +33,17 @@ #define DAC_OPEN (0x44414300) #define DAC_VREF_AVCC0_AVSS0 (0x01U) #define DAC_DAADSCR_REG_DAADST_BIT_POS (0x07U) -#define DAC_DAADUSR_REG_MASK (0x02U) +#define DAC_DAADUSR_REG_MASK BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK #define DAC_DADPR_REG_DPSEL_BIT_POS (0x07U) #define DAC_DAAMPCR_AMP_CTRL_BITS (0x06U) /* 6th bit for channel 0; 7th bit for channel 1 */ #define DAC_DACR_DAOE_BITS (0x06U) /* 6th bit for channel 0; 7th bit for channel 1 */ #define DAC_DAASWCR_DAASW0_MASK (0x40) #define DAC_DAASWCR_DAASW1_MASK (0x80) -#define DAC_ADC_UNIT_1 (0x01) +#if 0x01U == BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK + #define DAC_ADC_UNIT (0) +#elif 0x02U == BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK + #define DAC_ADC_UNIT (1) +#endif #define DAC_MAX_CHANNELS_PER_UNIT (2U) /* Conversion time with Output Amplifier. See hardware manual (see Table 60.44 @@ -143,17 +147,17 @@ fsp_err_t R_DAC_Open (dac_ctrl_t * p_api_ctrl, dac_cfg_t const * const p_cfg) p_ctrl->p_reg->DADPR = (uint8_t) ((uint8_t) p_extend->data_format << (uint8_t) DAC_DADPR_REG_DPSEL_BIT_POS); #if BSP_FEATURE_DAC_HAS_DA_AD_SYNCHRONIZE - #if BSP_FEATURE_ADC_UNIT_1_CHANNELS + #if BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK /* DA/AD Synchronization. Described in hardware manual (see Section 48.2.7 * 'D/A A/D Synchronous Unit Select Register (DAADUSR)' and Section 48.2.4 * 'D/A A/D Synchronous Start Control Register (DAADSCR)'of the RA6M3 manual R01UH0886EJ0100). */ - /* D/A A/D Synchronous Unit Select Register: Select ADC Unit 1 for synchronization with this DAC channel */ + /* D/A A/D Synchronous Unit Select Register: Select ADC Unit for synchronization with this DAC channel */ if ((0U == p_ctrl->p_reg->DAADSCR) && (p_cfg->ad_da_synchronized)) { /* For correctly writing to this register: - * 1. ADC (unit 1) module stop bit must be cleared. + * 1. ADC module stop bit must be cleared. * 2. DAADSCR.DAADST must be cleared. * * If ADC module is started, this will have no effect. @@ -162,9 +166,9 @@ fsp_err_t R_DAC_Open (dac_ctrl_t * p_api_ctrl, dac_cfg_t const * const p_cfg) * Since the ad_da_synchronized is set to true in the configuration structure * the ADC module is believed to be started at a later point in the application. */ - R_BSP_MODULE_START(FSP_IP_ADC, (uint16_t) DAC_ADC_UNIT_1); + R_BSP_MODULE_START(FSP_IP_ADC, (uint16_t) DAC_ADC_UNIT); - p_ctrl->p_reg->DAADUSR = (uint8_t) DAC_DAADUSR_REG_MASK; + p_ctrl->p_reg->DAADUSR = (uint8_t) BSP_FEATURE_DAC_AD_SYNC_UNIT_MASK; /* Configure D/A-A/D Synchronous Start Control Register(DAADSCR). */ p_ctrl->p_reg->DAADSCR = (uint8_t) (1U << (uint8_t) DAC_DAADSCR_REG_DAADST_BIT_POS); diff --git a/ra/fsp/src/r_flash_lp/r_flash_lp.c b/ra/fsp/src/r_flash_lp/r_flash_lp.c index dbff50197..78be83d88 100644 --- a/ra/fsp/src/r_flash_lp/r_flash_lp.c +++ b/ra/fsp/src/r_flash_lp/r_flash_lp.c @@ -1743,7 +1743,7 @@ static void r_flash_lp_process_command (const uint32_t start_addr, uint32_t num_ R_FACI_LP->FSARL = (uint16_t) (start_addr); /* BlankCheck end address setting */ - R_FACI_LP->FEARH = ((end_addr_idx >> 16)); + R_FACI_LP->FEARH = (uint16_t) ((end_addr_idx >> 16)); R_FACI_LP->FEARL = (uint16_t) (end_addr_idx); /* Execute BlankCheck command */ diff --git a/ra/fsp/src/r_lpm/r_lpm.c b/ra/fsp/src/r_lpm/r_lpm.c index abbdc77db..0e7a8522b 100644 --- a/ra/fsp/src/r_lpm/r_lpm.c +++ b/ra/fsp/src/r_lpm/r_lpm.c @@ -29,32 +29,40 @@ * Macro definitions **********************************************************************************************************************/ +#define LPM_LPSCR_SYSTEM_ACTIVE (0x0U) +#define LPM_LPSCR_SOFTWARE_STANDBY_MODE (0x4U) +#define LPM_LPSCR_DEEP_SOFTWARE_STANDBY_MODE1 (0x8U) +#define LPM_LPSCR_DEEP_SOFTWARE_STANDBY_MODE2 (0x9U) +#define LPM_LPSCR_DEEP_SOFTWARE_STANDBY_MODE3 (0xAU) + /* Clock control register addresses */ -#define LPM_CLOCK_HOCOCR ((uint8_t *) 0x4001E036U) -#define LPM_CLOCK_MOCOCR ((uint8_t *) 0x4001E038U) -#define LPM_CLOCK_LOCOCR ((uint8_t *) 0x4001E490U) -#define LPM_CLOCK_MOSCCR ((uint8_t *) 0x4001E032U) -#define LPM_CLOCK_SOSCCR ((uint8_t *) 0x4001E480U) -#define LPM_CLOCK_PLLCR ((uint8_t *) 0x4001E02AU) -#define LPM_CLOCK_HOCO 0 // The high speed on chip oscillator. -#define LPM_CLOCK_MOCO 1 // The middle speed on chip oscillator. -#define LPM_CLOCK_LOCO 2 // The low speed on chip oscillator. -#define LPM_CLOCK_MAIN_OSC 3 // The main oscillator. -#define LPM_CLOCK_SUBCLOCK 4 // The subclock oscillator. -#define LPM_CLOCK_PLL 5 // The PLL oscillator. +#define LPM_CLOCK_HOCOCR ((uint8_t *) 0x4001E036U) +#define LPM_CLOCK_MOCOCR ((uint8_t *) 0x4001E038U) +#define LPM_CLOCK_LOCOCR ((uint8_t *) 0x4001E490U) +#define LPM_CLOCK_MOSCCR ((uint8_t *) 0x4001E032U) +#define LPM_CLOCK_SOSCCR ((uint8_t *) 0x4001E480U) +#define LPM_CLOCK_PLLCR ((uint8_t *) 0x4001E02AU) +#define LPM_CLOCK_PLL2CR ((uint8_t *) 0x4001E04AU) +#define LPM_CLOCK_HOCO 0 // The high speed on chip oscillator. +#define LPM_CLOCK_MOCO 1 // The middle speed on chip oscillator. +#define LPM_CLOCK_LOCO 2 // The low speed on chip oscillator. +#define LPM_CLOCK_MAIN_OSC 3 // The main oscillator. +#define LPM_CLOCK_SUBCLOCK 4 // The subclock oscillator. +#define LPM_CLOCK_PLL 5 // The PLL oscillator. +#define LPM_CLOCK_PLL2 6 // The PLL2 oscillator. /* From user's manual and discussions with hardware group, * using the maximum is safe for all MCUs, will be updated and restored in LPM when entering * low power mode on RA6 MCUs (lowPowerModeEnter()) */ -#define LPM_SW_STANDBY_STCONR (0x0U) -#define LPM_SW_STANDBY_WAKE_STCONR (0x3U) +#define LPM_SW_STANDBY_STCONR (0x0U) +#define LPM_SW_STANDBY_WAKE_STCONR (0x3U) -#define LPM_SNZREQCR1_OFFSET (32ULL) -#define LPM_WUPEN1_OFFSET (32ULL) +#define LPM_SNZREQCR1_OFFSET (32ULL) +#define LPM_WUPEN1_OFFSET (32ULL) -#define LPM_OPEN (0x524c504d) +#define LPM_OPEN (0x524c504d) /*********************************************************************************************************************** * Typedef definitions @@ -64,6 +72,8 @@ * Private global variables **********************************************************************************************************************/ +#if BSP_FEATURE_LPM_HAS_SNOOZE + /* This array stores the address of the register containing the stop bit for each clock. All of these registers are * 8-bit registers and only bit 0 is valid. All other bits are read as 0 and should be written to 0. Bit 0 of each * of these registers indicates that the corresponding clock is stopped when set, or that the corresponding clock @@ -75,10 +85,14 @@ static uint8_t volatile * const gp_lpm_clock_stp_registers[] = [LPM_CLOCK_LOCO] = LPM_CLOCK_LOCOCR, [LPM_CLOCK_MAIN_OSC] = LPM_CLOCK_MOSCCR, [LPM_CLOCK_SUBCLOCK] = LPM_CLOCK_SOSCCR, -#if BSP_FEATURE_CGC_HAS_PLL + #if BSP_FEATURE_CGC_HAS_PLL [LPM_CLOCK_PLL] = LPM_CLOCK_PLLCR, -#endif + #endif + #if BSP_FEATURE_CGC_HAS_PLL2 + [LPM_CLOCK_PLL2] = LPM_CLOCK_PLL2CR, + #endif }; +#endif /*********************************************************************************************************************** * Global Variables @@ -101,9 +115,17 @@ const lpm_api_t g_lpm_on_lpm = **********************************************************************************************************************/ static fsp_err_t r_lpm_configure(lpm_cfg_t const * const p_cfg); static fsp_err_t r_lpm_low_power_enter(lpm_instance_ctrl_t * const p_instance_ctrl); + +#if BSP_FEATURE_LPM_HAS_SNOOZE static fsp_err_t r_lpm_check_clocks(uint32_t clock_source); -static void r_lpm_wait_for_operating_mode_flags(void); +#endif +static void r_lpm_wait_for_operating_mode_flags(void); + +#if BSP_FEATURE_LPM_HAS_LPSCR +static uint8_t r_lpm_lpscr_calculate(lpm_cfg_t const * p_cfg); + +#endif #if LPM_CFG_PARAM_CHECKING_ENABLE static fsp_err_t r_lpm_mcu_specific_low_power_check(lpm_cfg_t const * const p_cfg); @@ -200,7 +222,7 @@ fsp_err_t R_LPM_LowPowerReconfigure (lpm_ctrl_t * const p_api_ctrl, lpm_cfg_t co } /*******************************************************************************************************************//** - * Enter low power mode (sleep/standby/deep standby) using WFI macro. + * Enter low power mode (sleep/deep sleep/standby/deep standby) using WFI macro. * * Function will return after waking from low power mode. * @@ -221,6 +243,15 @@ fsp_err_t R_LPM_LowPowerModeEnter (lpm_ctrl_t * const p_api_ctrl) #if LPM_CFG_PARAM_CHECKING_ENABLE FSP_ASSERT(NULL != p_ctrl); FSP_ERROR_RETURN(LPM_OPEN == p_ctrl->lpm_open, FSP_ERR_NOT_OPEN); + + #if BSP_FEATURE_LPM_STANDBY_MOCO_REQUIRED + + /* The MOCO must be running when entering standby mode. */ + if (LPM_MODE_STANDBY <= p_ctrl->p_cfg->low_power_mode) + { + FSP_ERROR_RETURN(0 == R_SYSTEM->MOCOCR, FSP_ERR_INVALID_MODE); + } + #endif #endif /* Wait for ongoing operating mode transition (OPCMTSF, SOPCMTSF) */ @@ -229,19 +260,33 @@ fsp_err_t R_LPM_LowPowerModeEnter (lpm_ctrl_t * const p_api_ctrl) /* Must enable writing to Low Power Mode register prior to entering Low Power Mode. */ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); #if LPM_CFG_STANDBY_LIMIT + #if BSP_FEATURE_LPM_HAS_LPSCR + R_SYSTEM->LPSCR = r_lpm_lpscr_calculate(p_ctrl->p_cfg); + #endif + + #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY if (LPM_MODE_SLEEP != p_ctrl->p_cfg->low_power_mode) { R_SYSTEM->SBYCR |= (1U << R_SYSTEM_SBYCR_SSBY_Pos); } + #endif #endif fsp_err_t err = r_lpm_low_power_enter(p_ctrl); #if LPM_CFG_STANDBY_LIMIT + #if BSP_FEATURE_LPM_HAS_LPSCR + if ((LPM_MODE_SLEEP != p_ctrl->p_cfg->low_power_mode) && (LPM_MODE_DEEP_SLEEP != p_ctrl->p_cfg->low_power_mode)) + { + R_SYSTEM->LPSCR = 0; + } + #endif + #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY if (LPM_MODE_SLEEP != p_ctrl->p_cfg->low_power_mode) { R_SYSTEM->SBYCR &= (uint16_t) (~(1U << R_SYSTEM_SBYCR_SSBY_Pos)); } + #endif #endif R_BSP_RegisterProtectEnable(BSP_REG_PROTECT_OM_LPC_BATT); @@ -324,14 +369,27 @@ fsp_err_t R_LPM_Close (lpm_ctrl_t * const p_api_ctrl) **********************************************************************************************************************/ fsp_err_t r_lpm_mcu_specific_low_power_check (lpm_cfg_t const * const p_cfg) { + #if !BSP_FEATURE_LPM_HAS_DEEP_SLEEP + FSP_ERROR_RETURN(LPM_MODE_DEEP_SLEEP != p_cfg->low_power_mode, FSP_ERR_UNSUPPORTED) + #endif + #if !BSP_FEATURE_LPM_HAS_SNOOZE + FSP_ERROR_RETURN(LPM_MODE_STANDBY_SNOOZE != p_cfg->low_power_mode, FSP_ERR_UNSUPPORTED) + #endif + + #if BSP_FEATURE_LPM_HAS_DEEP_SLEEP + if ((LPM_MODE_SLEEP != p_cfg->low_power_mode) && (LPM_MODE_DEEP_SLEEP != p_cfg->low_power_mode)) + #else if (LPM_MODE_SLEEP != p_cfg->low_power_mode) + #endif { if (LPM_MODE_STANDBY_SNOOZE == p_cfg->low_power_mode) { + #if BSP_FEATURE_LPM_HAS_SNOOZE FSP_ERROR_RETURN(0U == ((uint64_t) p_cfg->snooze_request_source & (~BSP_FEATURE_LPM_SNZREQCR_MASK)), FSP_ERR_INVALID_ARGUMENT); FSP_ERROR_RETURN(0U == ((uint32_t) p_cfg->snooze_end_sources & (~BSP_FEATURE_LPM_SNZEDCR_MASK)), FSP_ERR_INVALID_ARGUMENT); + #endif } else if (LPM_MODE_DEEP == p_cfg->low_power_mode) { @@ -402,12 +460,24 @@ fsp_err_t r_lpm_configure (lpm_cfg_t const * const p_cfg) fsp_err_t err = r_lpm_mcu_specific_low_power_check(p_cfg); FSP_ERROR_RETURN(FSP_SUCCESS == err, err); #endif +#if BSP_FEATURE_LPM_HAS_SNOOZE uint32_t snzcr = 0; +#endif uint32_t sbycr = 0; #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY uint32_t dpsbycr = 0; #endif +#if BSP_FEATURE_LPM_HAS_LDO_CONTROL + if ((R_SYSTEM->PLL1LDOCR_b.SKEEP != p_cfg->ldo_standby_cfg.pll1_ldo) || + (R_SYSTEM->PLL2LDOCR_b.SKEEP != p_cfg->ldo_standby_cfg.pll2_ldo) || + (R_SYSTEM->HOCOLDOCR_b.SKEEP != p_cfg->ldo_standby_cfg.hoco_ldo)) + { + /* Writing to PLL1LDOCR, PLL2LDOCR and HOCOLDOCR registers is only allowed in High Speed Mode. */ + FSP_ERROR_RETURN(R_SYSTEM->OPCCR_b.OPCM == 0, FSP_ERR_INVALID_MODE); + } +#endif + R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_OM_LPC_BATT); /* Wait for ongoing operating mode transition (OPCMTSF, SOPCMTSF) */ @@ -430,14 +500,19 @@ fsp_err_t r_lpm_configure (lpm_cfg_t const * const p_cfg) R_SYSTEM->DPSIEGR1 = (uint8_t) (p_cfg->deep_standby_cancel_edge >> 8U); R_SYSTEM->DPSIEGR2 = (uint8_t) (p_cfg->deep_standby_cancel_edge >> 16U); - dpsbycr = (R_SYSTEM_DPSBYCR_DPSBY_Msk | - (((uint32_t) p_cfg->io_port_state << R_SYSTEM_DPSBYCR_IOKEEP_Pos) & - R_SYSTEM_DPSBYCR_IOKEEP_Msk) | - (((uint32_t) p_cfg->power_supply_state << R_SYSTEM_DPSBYCR_DEEPCUT_Pos) & - R_SYSTEM_DPSBYCR_DEEPCUT_Msk)); + #if BSP_FEATURE_LPM_HAS_DPSBYCR_DPSBY + dpsbycr |= R_SYSTEM_DPSBYCR_DPSBY_Msk; + #endif + #if BSP_FEATURE_LPM_HAS_DPSBYCR_DEEPCUT + dpsbycr |= ((uint32_t) p_cfg->power_supply_state << R_SYSTEM_DPSBYCR_DEEPCUT_Pos) & + R_SYSTEM_DPSBYCR_DEEPCUT_Msk; + #endif + dpsbycr |= ((uint32_t) p_cfg->io_port_state << R_SYSTEM_DPSBYCR_IOKEEP_Pos) & R_SYSTEM_DPSBYCR_IOKEEP_Msk; } #endif +#if BSP_FEATURE_LPM_HAS_SNOOZE + /* Configure Snooze registers */ if (LPM_MODE_STANDBY_SNOOZE == p_cfg->low_power_mode) { @@ -450,9 +525,9 @@ fsp_err_t r_lpm_configure (lpm_cfg_t const * const p_cfg) /* Set the request condition that can trigger entry in to snooze mode */ R_SYSTEM->SNZREQCR = (uint32_t) p_cfg->snooze_request_source & UINT32_MAX; -#if BSP_FEATURE_LPM_HAS_SNZREQCR1 == 1 + #if BSP_FEATURE_LPM_HAS_SNZREQCR1 == 1 R_SYSTEM->SNZREQCR1 = (uint32_t) (p_cfg->snooze_request_source >> LPM_SNZREQCR1_OFFSET) & UINT32_MAX; -#endif + #endif /* Enable/disable DTC operation */ snzcr |= (uint32_t) (p_cfg->dtc_state_in_snooze << R_SYSTEM_SNZCR_SNZDTCEN_Pos); @@ -463,20 +538,76 @@ fsp_err_t r_lpm_configure (lpm_cfg_t const * const p_cfg) /* Set all sources that can cause an exit from snooze mode to software standby. */ R_SYSTEM->SNZEDCR = (uint8_t) p_cfg->snooze_end_sources & UINT8_MAX; -#if BSP_FEATURE_LPM_HAS_SNZEDCR1 == 1 + #if BSP_FEATURE_LPM_HAS_SNZEDCR1 == 1 R_SYSTEM->SNZEDCR1 = (uint8_t) (p_cfg->snooze_end_sources >> 8U) & UINT8_MAX; -#endif + #endif } +#endif - /* Set SBYCR to Standby/Deep Standby. */ +#if BSP_FEATURE_LPM_HAS_DEEP_SLEEP + if (LPM_MODE_DEEP_SLEEP != p_cfg->low_power_mode) +#endif + { + /* Set SBYCR to Standby/Deep Standby. */ #if BSP_FEATURE_LPM_HAS_SBYCR_OPE - sbycr = (((uint32_t) p_cfg->output_port_enable) << R_SYSTEM_SBYCR_OPE_Pos) | (1U << R_SYSTEM_SBYCR_SSBY_Pos); + sbycr = ((uint32_t) p_cfg->output_port_enable) << R_SYSTEM_SBYCR_OPE_Pos; #elif BSP_FEATURE_LPM_SBYCR_WRITE1_B14 - sbycr = (1U << R_SYSTEM_SBYCR_OPE_Pos) | (1U << R_SYSTEM_SBYCR_SSBY_Pos); -#else - sbycr = (1U << R_SYSTEM_SBYCR_SSBY_Pos); + sbycr = R_SYSTEM_SBYCR_OPE_Msk; #endif +#if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + sbycr |= R_SYSTEM_SBYCR_SSBY_Msk; +#endif + +#if BSP_FEATURE_LPM_HAS_DPSBYCR_SRKEEP + + /* Configure Standby RAM retention in software standby and deep software standby modes. */ + dpsbycr |= (uint8_t) (p_cfg->ram_retention_cfg.standby_ram_retention << R_SYSTEM_DPSBYCR_SRKEEP_Pos); +#endif + } + + if ((LPM_MODE_DEEP_SLEEP == p_cfg->low_power_mode) || (LPM_MODE_STANDBY == p_cfg->low_power_mode)) + { +#if BSP_FEATURE_LPM_HAS_PDRAMSCR + + /* Configure TCM retention settings in deep sleep or standby mode. */ + R_SYSTEM->PDRAMSCR1 = p_cfg->ram_retention_cfg.tcm_retention; +#endif + } + + if (LPM_MODE_STANDBY == p_cfg->low_power_mode) + { +#if BSP_FEATURE_LPM_HAS_PDRAMSCR + + /* Configure RAM retention settings in standby mode. */ + R_SYSTEM->PDRAMSCR0 = p_cfg->ram_retention_cfg.ram_retention; +#endif + +#if BSP_FEATURE_LPM_HAS_LDO_CONTROL + + /* PLL1LDOCR may only be written in High Speed Mode. If PLL1DOCR setting is not changed, then skip + * writing to it. */ + if (R_SYSTEM->PLL1LDOCR_b.SKEEP != p_cfg->ldo_standby_cfg.pll1_ldo) + { + R_SYSTEM->PLL1LDOCR_b.SKEEP = (uint8_t) (p_cfg->ldo_standby_cfg.pll1_ldo & 0x01); + } + + /* PLL2LDOCR may only be written in High Speed Mode. If PLL2DOCR setting is not changed, then skip + * writing to it. */ + if (R_SYSTEM->PLL2LDOCR_b.SKEEP != p_cfg->ldo_standby_cfg.pll2_ldo) + { + R_SYSTEM->PLL2LDOCR_b.SKEEP = (uint8_t) (p_cfg->ldo_standby_cfg.pll2_ldo & 0x01); + } + + /* HOCOLDOCR may only be written in High Speed Mode. If HOCOLDOCR setting is not changed, then skip + * writing to it. */ + if (R_SYSTEM->HOCOLDOCR_b.SKEEP != p_cfg->ldo_standby_cfg.hoco_ldo) + { + R_SYSTEM->HOCOLDOCR_b.SKEEP = (uint8_t) (p_cfg->ldo_standby_cfg.hoco_ldo & 0x01); + } +#endif + } + R_ICU->WUPEN = (uint32_t) p_cfg->standby_wake_sources & UINT32_MAX; #if BSP_FEATURE_ICU_HAS_WUPEN1 == 1 R_ICU->WUPEN1 = (uint32_t) (p_cfg->standby_wake_sources >> LPM_WUPEN1_OFFSET) & UINT32_MAX; @@ -492,13 +623,27 @@ fsp_err_t r_lpm_configure (lpm_cfg_t const * const p_cfg) #endif } -#if LPM_CFG_STANDBY_LIMIT +#if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + #if LPM_CFG_STANDBY_LIMIT R_SYSTEM->SBYCR = (uint16_t) (sbycr & ~(1U << R_SYSTEM_SBYCR_SSBY_Pos)); -#else + #else R_SYSTEM->SBYCR = (uint16_t) sbycr; + #endif +#else + R_SYSTEM->SBYCR = (uint8_t) sbycr; +#endif + +#if BSP_FEATURE_LPM_HAS_LPSCR + #if !LPM_CFG_STANDBY_LIMIT + R_SYSTEM->LPSCR = r_lpm_lpscr_calculate(p_cfg); + #else + R_SYSTEM->LPSCR = 0; + #endif #endif +#if BSP_FEATURE_LPM_HAS_SNOOZE R_SYSTEM->SNZCR = (uint8_t) snzcr; +#endif #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY R_SYSTEM->DPSBYCR = (uint8_t) dpsbycr; @@ -509,6 +654,8 @@ fsp_err_t r_lpm_configure (lpm_cfg_t const * const p_cfg) return FSP_SUCCESS; } +#if BSP_FEATURE_LPM_HAS_SNOOZE + /*******************************************************************************************************************//** * Check the clock settings * @@ -521,6 +668,7 @@ fsp_err_t r_lpm_configure (lpm_cfg_t const * const p_cfg) * - MOCO was running when using snooze mode with SCI0/RXD0. * - MAIN OSCILLATOR was running when using snooze mode with SCI0/RXD0. * - PLL was running when using snooze mode with SCI0/RXD0. + * - PLL2 was running when using snooze mode with SCI0/RXD0. **********************************************************************************************************************/ fsp_err_t r_lpm_check_clocks (uint32_t clock_source) { @@ -530,13 +678,18 @@ fsp_err_t r_lpm_check_clocks (uint32_t clock_source) /* Verify Moco, Main Osc and PLL are stopped. */ FSP_ERROR_RETURN(1U == (*gp_lpm_clock_stp_registers[LPM_CLOCK_MOCO]), FSP_ERR_INVALID_MODE); FSP_ERROR_RETURN(1U == (*gp_lpm_clock_stp_registers[LPM_CLOCK_MAIN_OSC]), FSP_ERR_INVALID_MODE); -#if BSP_FEATURE_CGC_HAS_PLL + #if BSP_FEATURE_CGC_HAS_PLL FSP_ERROR_RETURN(1U == (*gp_lpm_clock_stp_registers[LPM_CLOCK_PLL]), FSP_ERR_INVALID_MODE); -#endif + #endif + #if BSP_FEATURE_CGC_HAS_PLL2 + FSP_ERROR_RETURN(1U == (*gp_lpm_clock_stp_registers[LPM_CLOCK_PLL2]), FSP_ERR_INVALID_MODE); + #endif return FSP_SUCCESS; } +#endif + /*******************************************************************************************************************//** * Perform pre-WFI execution tasks, enter low power mode, Perform post-WFI execution tasks * @@ -555,8 +708,10 @@ fsp_err_t r_lpm_check_clocks (uint32_t clock_source) fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) { #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY - uint32_t saved_opccr = 0U; - uint32_t saved_sopccr = 0U; + uint32_t saved_opccr = 0U; + #if BSP_FEATURE_CGC_HAS_SOPCCR + uint32_t saved_sopccr = 0U; + #endif uint32_t saved_ostdcr_ostde = 0U; #if BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE > 0 uint32_t saved_hocowtcr = 0U; @@ -570,7 +725,11 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) bsp_power_mode_t power_mode = BSP_POWER_MODE_LDO; #endif +#if BSP_FEATURE_LPM_HAS_SBYCR_SSBY if (1U == R_SYSTEM->SBYCR_b.SSBY) +#else + if (LPM_LPSCR_SOFTWARE_STANDBY_MODE <= R_SYSTEM->LPSCR) +#endif { /* Execute pre-wfi standby tasks */ @@ -580,26 +739,32 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) FSP_ERROR_RETURN(0U == R_SYSTEM->FLLCR1, FSP_ERR_INVALID_MODE); #endif +#if BSP_FEATURE_LPM_HAS_SNOOZE + /* Get system clock */ uint32_t clock_source = R_SYSTEM->SCKSCR; +#endif #if !BSP_FEATURE_LPM_HAS_DEEP_STANDBY + #if BSP_FEATURE_LPM_HAS_SNOOZE if (1U == R_SYSTEM->SNZCR_b.RXDREQEN) { /* Verify clock settings. */ FSP_ERROR_RETURN(FSP_SUCCESS == r_lpm_check_clocks(clock_source), FSP_ERR_INVALID_MODE); } + #endif /* Enable writing to CGC register. */ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); #else - /* RA6 Series Only: - * Save the OPCCR and SOPCCR registers. When transitioning from Software Standby mode to Normal or Snooze mode + /* Save the OPCCR and SOPCCR registers. When transitioning from Software Standby mode to Normal or Snooze mode * these registers are overwritten. See Section 11.2.6 "Operating Power Control Register" in the RA6M3 manual * R01UM0004EU0110 */ - saved_opccr = R_SYSTEM->OPCCR_b.OPCM; + saved_opccr = R_SYSTEM->OPCCR_b.OPCM; + #if BSP_FEATURE_CGC_HAS_SOPCCR saved_sopccr = R_SYSTEM->SOPCCR_b.SOPCM; + #endif #if BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE > 0 @@ -607,24 +772,35 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) saved_hocowtcr = R_SYSTEM->HOCOWTCR_b.HSTS; #endif + #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY if (0U == R_SYSTEM->DPSBYCR_b.DPSBY) + #else + if (LPM_LPSCR_DEEP_SOFTWARE_STANDBY_MODE1 > R_SYSTEM->LPSCR) + #endif { - /* RA6 Series Only: - * Check Snooze configuration settings. Set HOCOWTCR based on current configuration. See Section 11.2.1 + #if BSP_FEATURE_LPM_HAS_SNOOZE + + /* Check Snooze configuration settings. Set HOCOWTCR based on current configuration. See Section 11.2.1 * "Standby Control Register" in the RA6M3 manual R01UM0004EU0110 */ if (1U == R_SYSTEM->SNZCR_b.RXDREQEN) { /* Verify clock settings. */ FSP_ERROR_RETURN(FSP_SUCCESS == r_lpm_check_clocks(clock_source), FSP_ERR_INVALID_MODE); - #if BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE > 0 + #if BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE > 0 new_hocowtcr = BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE; } else { new_hocowtcr = BSP_FEATURE_CGC_HOCOWTCR_VALUE; - #endif + #endif } + #else + #if BSP_FEATURE_CGC_HAS_HOCOWTCR == 1 + new_hocowtcr = LPM_SW_STANDBY_HOCOWTCR_HSTS; + #endif + #endif + /* Enable writing to CGC register. */ R_BSP_RegisterProtectDisable(BSP_REG_PROTECT_CGC); @@ -697,6 +873,7 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) #endif } +#if BSP_FEATURE_LPM_HAS_SNOOZE if (LPM_MODE_STANDBY_SNOOZE == p_instance_ctrl->p_cfg->low_power_mode) { /* Enable Snooze mode (SNZCR.SNZE = 1) immediately before entering to Software Standby mode. @@ -707,6 +884,15 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) * infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHICBGB.html */ R_SYSTEM->SNZCR; } +#endif + +#if BSP_FEATURE_LPM_HAS_DEEP_SLEEP + if (LPM_MODE_SLEEP != p_instance_ctrl->p_cfg->low_power_mode) + { + /* Set the SLEEPDEEP bit. */ + SCB->SCR |= SCB_SCR_SLEEPDEEP_Msk; + } +#endif /* DSB should be last instruction executed before WFI * infocenter.arm.com/help/index.jsp?topic=/com.arm.doc.dai0321a/BIHICBGB.html */ @@ -714,12 +900,27 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) __WFI(); +#if BSP_FEATURE_LPM_HAS_DEEP_SLEEP + if (LPM_MODE_SLEEP != p_instance_ctrl->p_cfg->low_power_mode) + { + /* Clear the SLEEPDEEP bit. */ + SCB->SCR &= ~SCB_SCR_SLEEPDEEP_Msk; + } +#endif + +#if BSP_FEATURE_LPM_HAS_SNOOZE + /* Disable Snooze mode (SNZCR.SNZE = 0) immediately after canceling Snooze mode. * See Section 11.8.2 "Canceling Snooze Mode" in the RA6M3 manual R01UM0004EU0110 */ R_SYSTEM->SNZCR_b.SNZE = 0; +#endif #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY || (BSP_PRV_POWER_USE_DCDC) + #if BSP_FEATURE_LPM_HAS_SBYCR_SSBY if (1U == R_SYSTEM->SBYCR_b.SSBY) + #else + if (LPM_LPSCR_SOFTWARE_STANDBY_MODE <= R_SYSTEM->LPSCR) + #endif { #if BSP_FEATURE_LPM_HAS_DEEP_STANDBY @@ -727,8 +928,12 @@ fsp_err_t r_lpm_low_power_enter (lpm_instance_ctrl_t * const p_instance_ctrl) r_lpm_wait_for_operating_mode_flags(); /* Restore system registers to the values prior to entering standby. */ - R_SYSTEM->OPCCR = saved_opccr & R_SYSTEM_OPCCR_OPCM_Msk; - R_SYSTEM->SOPCCR = saved_sopccr & R_SYSTEM_SOPCCR_SOPCM_Msk; + R_SYSTEM->OPCCR = saved_opccr & R_SYSTEM_OPCCR_OPCM_Msk; + + #if BSP_FEATURE_CGC_HAS_SOPCCR + R_SYSTEM->SOPCCR = saved_sopccr & R_SYSTEM_SOPCCR_SOPCM_Msk; + #endif + R_SYSTEM->OSTDCR_b.OSTDE = 0x1U & saved_ostdcr_ostde; #if BSP_FEATURE_CGC_HOCOWTCR_SCI_SNOOZE_VALUE > 0 R_SYSTEM->HOCOWTCR_b.HSTS = R_SYSTEM_HOCOWTCR_HSTS_Msk & (saved_hocowtcr << R_SYSTEM_HOCOWTCR_HSTS_Pos); @@ -762,6 +967,56 @@ void r_lpm_wait_for_operating_mode_flags (void) /* Wait for transition to complete. */ FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->OPCCR_b.OPCMTSF, 0U); +#if BSP_FEATURE_CGC_HAS_SOPCCR + /* Wait for transition to complete. */ FSP_HARDWARE_REGISTER_WAIT(R_SYSTEM->SOPCCR_b.SOPCMTSF, 0U); +#endif } + +#if BSP_FEATURE_LPM_HAS_LPSCR + +/*******************************************************************************************************************//** + * Calculate the correct value of LPSCR based on the mode. + **********************************************************************************************************************/ +static uint8_t r_lpm_lpscr_calculate (lpm_cfg_t const * p_cfg) +{ + uint8_t lpscr = 0; + + switch (p_cfg->low_power_mode) + { + case LPM_MODE_SLEEP: + { + lpscr = LPM_LPSCR_SYSTEM_ACTIVE; + break; + } + + case LPM_MODE_DEEP_SLEEP: + { + lpscr = LPM_LPSCR_SYSTEM_ACTIVE; + break; + } + + case LPM_MODE_STANDBY: + { + lpscr = LPM_LPSCR_SOFTWARE_STANDBY_MODE; + break; + } + + case LPM_MODE_DEEP: + { + lpscr = LPM_LPSCR_DEEP_SOFTWARE_STANDBY_MODE1; + lpscr |= p_cfg->power_supply_state; + break; + } + + default: + { + break; + } + } + + return lpscr; +} + +#endif diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/adaptors/r_sce_adapt.c new file mode 100644 index 000000000..02db59a6f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/adaptors/r_sce_adapt.c @@ -0,0 +1,181 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "../private/inc/SCE_ProcCommon.h" +#include "hw_sce_ra_private.h" +#include "hw_sce_private.h" +#include "hw_sce_trng_private.h" + +/*********************************************************************************************************************** + * Macro definitions + **********************************************************************************************************************/ + +#define SCE_RSIP7_LITTLE_ENDIAN_MODE (0x00CF00CF) + +uint32_t S_RAM[HW_SCE_SRAM_WORD_SIZE]; +uint32_t S_HEAP[HW_SCE_SHEAP_WORD_SIZE]; +uint32_t S_INST[HW_SCE_SINST_WORD_SIZE]; +uint32_t S_INST2[HW_SCE_SINST2_WORD_SIZE]; + +uint32_t INST_DATA_SIZE; +uint32_t KEY_INDEX_SIZE; + +/******************************************************* + * The following are valid SCE lifecycle states: + * + * CM1(Lifecycle state) + * + * CM2(Lifecycle state) + * + * SSD(Lifecycle state) + * + * NSECSD(Lifecycle state) + * + * DPL(Lifecycle state) + * + * LCK_DBG(Lifecycle state) + * + * LCK_BOOT(Lifecycle state) + * + * RMA_REQ(Lifecycle state) + * + * RMA_ACK(Lifecycle state) + ****************************************************/ + +#define FSP_SCE_DLMMON_MASK 0x0000000F /* for lcs in stored in R_PSCU->DLMMON */ + +const uint32_t sce_oem_key_size[SCE_OEM_CMD_NUM] = +{ + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES128_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES192_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES256_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES128_XTS_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_AES256_XTS_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA1024_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA1024_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA2048_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA2048_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA3072_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA3072_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA4096_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_RSA4096_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP192_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP192_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP224_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP224_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_HMAC_SHA224_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_HMAC_SHA256_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256R1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP256R1_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384R1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP384R1_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP512R1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCP512R1_PRIVATE_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCSECP256K1_PUBLICK_KEY_INST_DATA_WORD, + SCE_OEM_KEY_SIZE_ECCSECP256K1_PRIVATE_KEY_INST_DATA_WORD, +}; + +/* Find the lifecycle state load the hardware unique key */ +/* returns fsp_err_t */ + +fsp_err_t HW_SCE_HUK_Load_LCS (void) +{ + uint32_t lc_state = R_PSCU->DLMMON & FSP_SCE_DLMMON_MASK; + + return HW_SCE_LoadHukSub(&lc_state); +} + +/* SCE9 specific initialization functions */ +/* returns fsp_err_t */ + +fsp_err_t HW_SCE_McuSpecificInit (void) +{ + fsp_err_t iret = FSP_ERR_CRYPTO_SCE_FAIL; + +// power on the SCE module  + HW_SCE_PowerOn(); + + HW_SCE_SoftwareResetSub(); + iret = HW_SCE_SelfCheck1Sub(); + if (FSP_SUCCESS == iret) + { + /* Change SCE to little endian mode */ + SCE->REG_1424H = SCE_RSIP7_LITTLE_ENDIAN_MODE; + SCE->REG_1428H = SCE_RSIP7_LITTLE_ENDIAN_MODE; + + /* This check is moved from before the endian setting for the updated fastboot procedures */ + iret = HW_SCE_SelfCheck2Sub(); + } + + if (FSP_SUCCESS == iret) + { + iret = HW_SCE_HUK_Load_LCS(/* please try OEM mode when HUK load primitive executing */); + } + + return iret; +} + +fsp_err_t HW_SCE_RNG_Read (uint32_t * OutData_Text) +{ + if (FSP_SUCCESS != HW_SCE_GenerateRandomNumberSub(OutData_Text)) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + + return FSP_SUCCESS; +} + +fsp_err_t HW_SCE_GenerateOemKeyIndexPrivate (const sce_oem_key_type_t key_type, + const sce_oem_cmd_t cmd, + const uint8_t * encrypted_provisioning_key, + const uint8_t * iv, + const uint8_t * encrypted_oem_key, + uint32_t * key_index) +{ + uint32_t indata_key_type[1] = {0}; + uint32_t indata_cmd[1] = {0}; + uint32_t install_key_ring_index[1] = {0}; + indata_key_type[0] = key_type; + indata_cmd[0] = (cmd); + install_key_ring_index[0] = 0U; + + INST_DATA_SIZE = sce_oem_key_size[cmd] - 4U; + + /* Casting uint32_t pointer is used for address. */ + return HW_SCE_GenerateOemKeyIndexSub(indata_key_type, + indata_cmd, + install_key_ring_index, + (uint32_t *) encrypted_provisioning_key, + (uint32_t *) iv, + (uint32_t *) encrypted_oem_key, + key_index); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/change_endian_long.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/change_endian_long.c new file mode 100644 index 000000000..aee2c0738 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/change_endian_long.c @@ -0,0 +1,26 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +uint32_t change_endian_long (uint32_t data) +{ + return __REV(data); +} diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func008.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func008.c new file mode 100644 index 000000000..a0f03133a --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func008.c @@ -0,0 +1,106 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func008 (void) +{ + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x04040001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000890U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000008e0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x04040001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func027.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func027.c new file mode 100644 index 000000000..1a6c644f3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func027.c @@ -0,0 +1,133 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func027 (uint32_t ARG1) +{ + WR1_PROG(REG_1600H, 0x38000f5aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01305c44U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0142859dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1404H, 0x10400000U); + WR1_PROG(REG_1444H, 0x000047c2U); + WR1_PROG(REG_1A2CH, 0x00001100U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 28]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 32]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 36]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x13600000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 40]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 44]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 48]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x18600000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 52]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 56]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 60]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x18b00000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 64]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 68]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 72]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10900000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 76]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 80]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 84]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x18100000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 88]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 92]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 96]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 100]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func028.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func028.c new file mode 100644 index 000000000..707b4c951 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func028.c @@ -0,0 +1,89 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func028 (uint32_t ARG1) +{ + WR1_PROG(REG_1600H, 0x38000f5aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01166403U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x013659ffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1404H, 0x11b00000U); + WR1_PROG(REG_1444H, 0x000017c2U); + WR1_PROG(REG_1A2CH, 0x00000500U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 4]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 8]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11e80000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 12]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 16]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 20]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 24]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func031.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func031.c new file mode 100644 index 000000000..9d44fd04f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func031.c @@ -0,0 +1,118 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func031 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_1600H, 0x0000356aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0420a960U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0001696bU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00036d6bU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00009160U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000042U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00186d6bU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008c60U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000106bU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000010c9U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1824H, 0x08000105U); + WR1_PROG(REG_1608H, 0x81040060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[0]); + WR1_PROG(REG_1608H, 0x80040180U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b560U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01906d6cU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01906d8dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000009adU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000009ceU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1824H, 0x08000105U); + WR1_PROG(REG_1608H, 0x81040160U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_182CH, 0x00000100U); + WR1_PROG(REG_1824H, 0xf8008007U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func043.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func043.c new file mode 100644 index 000000000..9058aeb08 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func043.c @@ -0,0 +1,134 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func043(void) +{ + HW_SCE_p_func100(0xaffe4824U, 0x3460ee8bU, 0x2f9b1eb2U, 0xa0fcd369U); + WR1_PROG(REG_1600H, 0x0000b540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000001d0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8188000aU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x6e02b97aU, 0x014ffeb6U, 0x317871e1U, 0xe40dd388U); + WR1_PROG(REG_1A24H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xe6c9c9fcU, 0x39f5c78fU, 0xb9fdd600U, 0x7598ab78U); + + WR1_PROG(REG_1600H, 0x0000b540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000001c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8184000aU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x080000c5U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x0b040104U); + WR1_PROG(REG_1608H, 0x810100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1608H, 0x80040140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009105U); + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x02000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009045U); + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func100(0xb6fcaf33U, 0x61d8d3e6U, 0xd264fd38U, 0x580fe0c4U); + WR1_PROG(REG_1A24H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x53f94e00U, 0x5cea04dbU, 0x47205603U, 0xbdc55dc0U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000094U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func044.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func044.c new file mode 100644 index 000000000..a1c51f454 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func044.c @@ -0,0 +1,88 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func044(void) +{ + WR1_PROG(REG_1600H, 0x00008ce0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000090e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009104U); + WR1_PROG(REG_1608H, 0x810100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00008ce0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000090e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x02000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009044U); + WR1_PROG(REG_1608H, 0x810100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func100(0xff03bc3fU, 0x83a2992aU, 0xa00481cfU, 0xfb707422U); + WR1_PROG(REG_1A24H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x5bbbaa93U, 0x9311382fU, 0xcbc7874dU, 0xf48a3409U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000094U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func048.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func048.c new file mode 100644 index 000000000..abc6106f3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func048.c @@ -0,0 +1,32 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func048 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(ARG1[0])); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func049.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func049.c new file mode 100644 index 000000000..ceedd13b6 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func049.c @@ -0,0 +1,32 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func049 (const uint32_t ARG1[]) +{ + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010080U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, ARG1[0]); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func057.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func057.c new file mode 100644 index 000000000..5e3537000 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func057.c @@ -0,0 +1,423 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func057 (const uint32_t ARG1[], const uint32_t ARG2[], uint32_t ARG3[]) +{ + uint32_t iLoop = 0U; + uint32_t oLoop = 0U; + + HW_SCE_p_func100(0x014fc442U, 0x7fb45e76U, 0x2e7fbef3U, 0x70d8c890U); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[0]); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000ffU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x97c16b1aU, 0xcab4e1e0U, 0xe83dc919U, 0x63d1c089U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x000034e4U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000feU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x81188bcdU, 0xd465cb3aU, 0x5460ee88U, 0xfa6e9d6dU); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xea88f7e8U, 0x8c73c3daU, 0xada49d15U, 0xe6e78f26U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1000H, 0x00010000U); + + HW_SCE_p_func081(); + + WR1_PROG(REG_1600H, 0x00007c01U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + oLoop = 0x00000000U; + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + for (iLoop = 0U; iLoop < (INST_DATA_SIZE - 4U); ) + { + HW_SCE_p_func100(0xabaeb1d2U, 0xdbce3d0aU, 0x2b27fdf2U, 0x45abd5cbU); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0xd900090dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1400H, 0x00810011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG3[1 + iLoop]); + + HW_SCE_p_func101(0x0c156d4aU, 0x4726e434U, 0xc9151a06U, 0x39ab66f1U); + iLoop = iLoop + 4U; + } + + oLoop = iLoop; + + HW_SCE_p_func101(0x55094f4dU, 0x5dc73591U, 0xa8ee2f55U, 0xade97968U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000aU) + { + HW_SCE_p_func100(0x0a501155U, 0x1a1f7ec3U, 0x26602d39U, 0x83084874U); + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func061(0U, ARG2); + iLoop = 32U; + + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func065(0U, ARG3); + HW_SCE_p_func100(0x150c4f50U, 0x44b7a9a3U, 0x78e48b23U, 0x9c62b9e7U); + HW_SCE_p_func065(8U, ARG3); + HW_SCE_p_func100(0x05e508ceU, 0x3c07de0aU, 0x7c89e370U, 0xb9503bedU); + HW_SCE_p_func065(16U, ARG3); + HW_SCE_p_func100(0x2e100529U, 0x3308d50fU, 0xd9c51be6U, 0x659036b2U); + HW_SCE_p_func065(24U, ARG3); + oLoop = oLoop + 32U; + + HW_SCE_p_func100(0xc502c2c0U, 0x70f468d9U, 0x7a0d28efU, 0x0b986501U); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0xd900090dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + iLoop = iLoop + 4U; + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00810011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG3[1 + oLoop]); + + WAIT_STS(REG_1A28H, 6, 0); + + HW_SCE_p_func100(0x7caf20d1U, 0xe59a5be5U, 0xf70e3425U, 0x2162d703U); + HW_SCE_p_func060(); + + WR1_PROG(REG_1404H, 0x11180000U); + HW_SCE_p_func062(36U, ARG3); + HW_SCE_p_func100(0x8e65434eU, 0xf9ee6df3U, 0x05296722U, 0x60353489U); + HW_SCE_p_func062(44U, ARG3); + HW_SCE_p_func100(0x0253ea51U, 0x38f6d4b6U, 0x637263ecU, 0xcf8f3ed0U); + HW_SCE_p_func062(52U, ARG3); + HW_SCE_p_func100(0x9290b786U, 0xc813031aU, 0xb1cbb901U, 0xa6f4b465U); + HW_SCE_p_func062(60U, ARG3); + oLoop = 36U + 32U; + + HW_SCE_p_func101(0x505df6faU, 0xb9fa0edbU, 0x3c31bfd4U, 0x042e7292U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000bU) + { + HW_SCE_p_func100(0x69ed3d1aU, 0x35bb8c57U, 0x079e21f7U, 0xac20d974U); + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func061(0U, ARG2); + iLoop = 32U; + + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func062(0U, ARG3); + HW_SCE_p_func100(0x34543cc0U, 0x37999e77U, 0x0508ded5U, 0xb1b65e73U); + HW_SCE_p_func062(8U, ARG3); + HW_SCE_p_func100(0x937c954eU, 0x7a67ef9dU, 0x371ad5a4U, 0x3bbab049U); + HW_SCE_p_func062(16U, ARG3); + HW_SCE_p_func100(0xa58bd013U, 0x0efa64a6U, 0x2d5bd251U, 0xa7b7908aU); + HW_SCE_p_func062(24U, ARG3); + oLoop = oLoop + 32U; + + HW_SCE_p_func100(0xd42979e7U, 0xc4b53fa8U, 0x3dcc256eU, 0xe76e10cbU); + WR1_PROG(REG_1404H, 0x11100000U); + HW_SCE_p_func061(32U, ARG2); + iLoop = 32U + 32U; + + WR1_PROG(REG_1404H, 0x11100000U); + HW_SCE_p_func062(32U, ARG3); + HW_SCE_p_func100(0xd06106c1U, 0x19b7bb2aU, 0x65b22396U, 0x9fa6494fU); + HW_SCE_p_func062(40U, ARG3); + HW_SCE_p_func100(0xd0851840U, 0x4b4c5260U, 0x13248d04U, 0xd1912639U); + HW_SCE_p_func062(48U, ARG3); + HW_SCE_p_func100(0x6ec3050aU, 0x3ae09ab9U, 0xeabb2db6U, 0xfbf3de81U); + HW_SCE_p_func062(56U, ARG3); + oLoop = oLoop + 32U; + + HW_SCE_p_func100(0xacf194b9U, 0x84383146U, 0xec2d6c29U, 0x88026692U); + HW_SCE_p_func060(); + + WR1_PROG(REG_1404H, 0x11180000U); + HW_SCE_p_func062(64U, ARG3); + HW_SCE_p_func100(0x25b1416eU, 0xdff23336U, 0xfdeaa105U, 0x9efde552U); + HW_SCE_p_func062(72U, ARG3); + HW_SCE_p_func100(0x0311d7daU, 0xb5663fbaU, 0xbaaddda8U, 0x13c8f516U); + HW_SCE_p_func062(80U, ARG3); + HW_SCE_p_func100(0x4a84a314U, 0x900dd898U, 0x034b241bU, 0xc3225d84U); + HW_SCE_p_func062(88U, ARG3); + oLoop = 64U + 32U; + + HW_SCE_p_func101(0x103683c8U, 0x497bf486U, 0xe02b6b4aU, 0xe4323d0aU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000cU) + { + HW_SCE_p_func100(0xc408c4beU, 0x50c4375bU, 0xdaacc884U, 0xda0c28c2U); + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func063(0U, ARG2); + iLoop = 64U; + + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func065(0U, ARG3); + HW_SCE_p_func100(0xba8c7f77U, 0x06385d3eU, 0x6abfcee5U, 0xfb7ee248U); + HW_SCE_p_func065(8U, ARG3); + HW_SCE_p_func100(0x7475812aU, 0xe09edbb1U, 0x10fbf3b6U, 0xa1c9018eU); + HW_SCE_p_func065(16U, ARG3); + HW_SCE_p_func100(0x839ddf35U, 0x5cefd93dU, 0x76abad37U, 0x4f1607ffU); + HW_SCE_p_func065(24U, ARG3); + HW_SCE_p_func100(0x9cc4f463U, 0x42cd7f68U, 0xb8b4c48cU, 0x11f223beU); + HW_SCE_p_func065(32U, ARG3); + HW_SCE_p_func100(0x042ed769U, 0xcfd046dbU, 0x69edcc25U, 0x27361e6aU); + HW_SCE_p_func065(40U, ARG3); + HW_SCE_p_func100(0xa55d021dU, 0xc4f07f79U, 0x3ef983b8U, 0x8cd5a80bU); + HW_SCE_p_func065(48U, ARG3); + HW_SCE_p_func100(0x82d51100U, 0xd69b1239U, 0x268dcc2aU, 0xd8fab087U); + HW_SCE_p_func065(56U, ARG3); + oLoop = oLoop + 64U; + + HW_SCE_p_func100(0x6110b2b8U, 0xcfa5c11eU, 0x2f430ac2U, 0x77386c4aU); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0xd900090dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + iLoop = iLoop + 4U; + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00810011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG3[1 + oLoop]); + + WAIT_STS(REG_1A28H, 6, 0); + + HW_SCE_p_func100(0x451c42b3U, 0x0706c49bU, 0x8747d30cU, 0x852579a5U); + HW_SCE_p_func066(); + + WR1_PROG(REG_1404H, 0x11180000U); + HW_SCE_p_func062(68U, ARG3); + HW_SCE_p_func100(0x9553b5f1U, 0xac77ca51U, 0x848543d0U, 0xe55d60eaU); + HW_SCE_p_func062(76U, ARG3); + HW_SCE_p_func100(0x88501696U, 0x567cf779U, 0xc1d8cd77U, 0x728e8bb9U); + HW_SCE_p_func062(84U, ARG3); + HW_SCE_p_func100(0x092082f7U, 0x6155d1a3U, 0xc73057d8U, 0x0b0bdb12U); + HW_SCE_p_func062(92U, ARG3); + HW_SCE_p_func100(0xf1fbc9e4U, 0x230d7cdaU, 0xcefb4b87U, 0x6a8c2a0eU); + HW_SCE_p_func062(100U, ARG3); + HW_SCE_p_func100(0x837eb59cU, 0x4c9d208aU, 0x168303daU, 0xdabcb6cbU); + HW_SCE_p_func062(108U, ARG3); + HW_SCE_p_func100(0x2e4d7684U, 0xbf9edc91U, 0x0c555029U, 0xb34d1d45U); + HW_SCE_p_func062(116U, ARG3); + HW_SCE_p_func100(0xc5fda8f6U, 0x5cfbd5a3U, 0xb4ceaafdU, 0x0582633cU); + HW_SCE_p_func062(124U, ARG3); + oLoop = 68U + 64U; + + HW_SCE_p_func101(0x5569a977U, 0xc21a575aU, 0xe8630117U, 0x7e7da593U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000dU) + { + HW_SCE_p_func100(0x1107c72cU, 0x29affbb5U, 0x90f19911U, 0x1fb07f92U); + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func063(0U, ARG2); + iLoop = 64U; + + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func062(0U, ARG3); + HW_SCE_p_func100(0x30c29bdfU, 0x4f879100U, 0x6b612180U, 0xe4f537daU); + HW_SCE_p_func062(8U, ARG3); + HW_SCE_p_func100(0x5c3a3e31U, 0x86b9e9c7U, 0xac219169U, 0x98806278U); + HW_SCE_p_func062(16U, ARG3); + HW_SCE_p_func100(0x453f9a6fU, 0xc6f5ad0bU, 0x37993f8eU, 0xe3aee985U); + HW_SCE_p_func062(24U, ARG3); + HW_SCE_p_func100(0xfe27efbcU, 0x58063c69U, 0x738af859U, 0x2692b69cU); + HW_SCE_p_func062(32U, ARG3); + HW_SCE_p_func100(0x8362c470U, 0x3fdb04d5U, 0x1df6b336U, 0xb77f3d0aU); + HW_SCE_p_func062(40U, ARG3); + HW_SCE_p_func100(0xacfe300cU, 0xf031c137U, 0x08123200U, 0xb9e65507U); + HW_SCE_p_func062(48U, ARG3); + HW_SCE_p_func100(0x593ef93bU, 0xc0f95a4fU, 0x78112f36U, 0x4d694a95U); + HW_SCE_p_func062(56U, ARG3); + oLoop = oLoop + 64U; + + HW_SCE_p_func100(0x8df7f9f4U, 0xb5dd3cdbU, 0x9ca3751cU, 0x293567b0U); + WR1_PROG(REG_1404H, 0x11100000U); + HW_SCE_p_func063(64U, ARG2); + iLoop = 64U + 64U; + + WR1_PROG(REG_1404H, 0x11100000U); + HW_SCE_p_func062(64U, ARG3); + HW_SCE_p_func100(0xd7ce96f9U, 0x19570512U, 0xcb401159U, 0x830e068eU); + HW_SCE_p_func062(72U, ARG3); + HW_SCE_p_func100(0x4964b85dU, 0x1d0d6c23U, 0x4dee545dU, 0x94d7b6b7U); + HW_SCE_p_func062(80U, ARG3); + HW_SCE_p_func100(0x4f0af471U, 0x6f5faa44U, 0xdaea5248U, 0x3788c037U); + HW_SCE_p_func062(88U, ARG3); + HW_SCE_p_func100(0xea18875aU, 0xe99995b8U, 0x13e976b3U, 0x8c909715U); + HW_SCE_p_func062(96U, ARG3); + HW_SCE_p_func100(0xb8ce7a2cU, 0x06255c78U, 0x13832e71U, 0xf9f467b3U); + HW_SCE_p_func062(104U, ARG3); + HW_SCE_p_func100(0x8b9693d8U, 0xfd19485dU, 0x5a8d43e3U, 0x2d8ba186U); + HW_SCE_p_func062(112U, ARG3); + HW_SCE_p_func100(0x4e68bef9U, 0x8023a9c8U, 0x081034a4U, 0x7ce84db2U); + HW_SCE_p_func062(120U, ARG3); + oLoop = oLoop + 64U; + + HW_SCE_p_func100(0xa5a0bc56U, 0x9d0ebe56U, 0x5f3936f3U, 0xa177265bU); + HW_SCE_p_func066(); + + WR1_PROG(REG_1404H, 0x11180000U); + HW_SCE_p_func062(128U, ARG3); + HW_SCE_p_func100(0xa32e41b5U, 0xc68c0895U, 0x8070876eU, 0xb20e473dU); + HW_SCE_p_func062(136U, ARG3); + HW_SCE_p_func100(0x908f9fa9U, 0x3300540aU, 0x0aae4c8dU, 0x8f88ec0bU); + HW_SCE_p_func062(144U, ARG3); + HW_SCE_p_func100(0xc84a5121U, 0x1c99a6b5U, 0x8af88d7dU, 0xa19bf292U); + HW_SCE_p_func062(152U, ARG3); + HW_SCE_p_func100(0x7cbfc8b8U, 0x7330e2ceU, 0x229bcf44U, 0x4c1a68b8U); + HW_SCE_p_func062(160U, ARG3); + HW_SCE_p_func100(0x82417d19U, 0xd15cad02U, 0xb1766c82U, 0x3d940834U); + HW_SCE_p_func062(168U, ARG3); + HW_SCE_p_func100(0xece00fa4U, 0x96d62db7U, 0x77c6dbdaU, 0x9f2f6164U); + HW_SCE_p_func062(176U, ARG3); + HW_SCE_p_func100(0x23d59a6aU, 0x35ae4a7aU, 0x75b21fecU, 0x64512fc4U); + HW_SCE_p_func062(184U, ARG3); + oLoop = 128U + 64U; + + HW_SCE_p_func101(0xe8f064f9U, 0xcabf1265U, 0x5e619833U, 0x0a27de1aU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000012U) + { + for (iLoop = 0U; iLoop < (INST_DATA_SIZE - 4U); ) + { + HW_SCE_p_func100(0x5935f015U, 0xa7faa697U, 0x6daffbd8U, 0x7553f5d3U); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0xd900090dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00810011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG3[1 + iLoop]); + + HW_SCE_p_func101(0xdfabf01bU, 0x30fc4e73U, 0xe6281d2cU, 0xa33fadfdU); + iLoop = iLoop + 4U; + } + + oLoop = iLoop; + + HW_SCE_p_func101(0x7f3a87bfU, 0x4e796887U, 0x2b420216U, 0xe3d834a7U); + } + + HW_SCE_p_func100(0xb9028d29U, 0x37d0a3b6U, 0x99afb95bU, 0x5e729e90U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG3[1 + oLoop]); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x0900090dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c1cU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func058.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func058.c new file mode 100644 index 000000000..1e1c7a38f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func058.c @@ -0,0 +1,92 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func058 (const uint32_t ARG1[], uint32_t ARG2) +{ + HW_SCE_p_func100(0x5ffef0baU, 0x29cc50fbU, 0x46eaa5d1U, 0xaae7ba36U); + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0174d08aU)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + HW_SCE_p_func100(0x0b0b069bU, 0xb768d818U, 0x57c67938U, 0x97df6f2bU); + WR1_PROG(REG_1600H, 0x00009020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x4a040044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0404c4U); + WR1_PROG(REG_1608H, 0x81010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + HW_SCE_p_func100(0x16d28814U, 0x6fb40c69U, 0x262842e8U, 0x76ce53adU); + WR1_PROG(REG_1824H, 0xf7041cb5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG2]); + WAIT_STS(REG_1828H, 6, 0); + WR1_PROG(REG_143CH, 0x00000500U); + + HW_SCE_p_func100(0x88f86088U, 0x7542378aU, 0x654b3834U, 0x345fad2cU); + WR1_PROG(REG_1824H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG2 + 4]); + + WR1_PROG(REG_1824H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x0a03008dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[0]); + WAIT_STS(REG_1828H, 6, 0); + WR1_PROG(REG_143CH, 0x00000500U); + + HW_SCE_p_func100(0x10ea72b3U, 0xaee0c0a3U, 0x6d1c6e86U, 0x60057644U); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x0a03009dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[4]); + WAIT_STS(REG_1828H, 6, 0); + WR1_PROG(REG_143CH, 0x00000500U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func059.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func059.c new file mode 100644 index 000000000..da6b30707 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func059.c @@ -0,0 +1,69 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func059(void) +{ + HW_SCE_p_func100(0xecc408d6U, 0x9ee5a12aU, 0xefdd1e6cU, 0x8c5de19aU); + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x4a060044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e060085U); + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x475d134aU, 0xb42dfd89U, 0x4ed20990U, 0x01a39314U); + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x02000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0e060095U); + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func060.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func060.c new file mode 100644 index 000000000..8a10065c7 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func060.c @@ -0,0 +1,43 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func060(void) +{ + WR1_PROG(REG_101CH, 0x00000080U); + + WR1_PROG(REG_1010H, 0x00000108U); + + WR1_PROG(REG_1004H, 0x10100010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1020H, 0x00000198U); + + WR1_PROG(REG_1024H, 0x000003b8U); + + WR1_PROG(REG_1004H, 0x10100003U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00000d00U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func061.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func061.c new file mode 100644 index 000000000..69572bb44 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func061.c @@ -0,0 +1,43 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func061 (uint32_t ARG1, const uint32_t ARG2[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00001fc1U); + WR1_PROG(REG_182CH, 0x00000700U); + WR1_PROG(REG_1824H, 0xd900890fU); + + for (iLoop = ARG1; iLoop < ARG1 + 32U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c10021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func062.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func062.c new file mode 100644 index 000000000..346884111 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func062.c @@ -0,0 +1,37 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func062 (uint32_t ARG1, uint32_t ARG2[]) +{ + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7008d07U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG2[ARG1 + 1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG2[ARG1 + 5]); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func063.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func063.c new file mode 100644 index 000000000..d7d910cff --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func063.c @@ -0,0 +1,43 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func063 (uint32_t ARG1, const uint32_t ARG2[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00003fc1U); + WR1_PROG(REG_182CH, 0x00000f00U); + WR1_PROG(REG_1824H, 0xd900890fU); + + for (iLoop = ARG1; iLoop < ARG1 + 64U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c10021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func065.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func065.c new file mode 100644 index 000000000..e23d3c220 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func065.c @@ -0,0 +1,37 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func065 (uint32_t ARG1, uint32_t ARG2[]) +{ + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe8008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG2[ARG1 + 1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG2[ARG1 + 5]); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func066.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func066.c new file mode 100644 index 000000000..2d42d94ea --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func066.c @@ -0,0 +1,43 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func066(void) +{ + WR1_PROG(REG_101CH, 0x00000100U); + + WR1_PROG(REG_1010H, 0x00000108U); + + WR1_PROG(REG_1004H, 0x20200010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1020H, 0x00000218U); + + WR1_PROG(REG_1024H, 0x00000538U); + + WR1_PROG(REG_1004H, 0x20200003U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00000d00U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func068.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func068.c new file mode 100644 index 000000000..591dcccb2 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func068.c @@ -0,0 +1,69 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func068(void) +{ + HW_SCE_p_func100(0xea193119U, 0x2fe6d551U, 0xc90c49e2U, 0x0660e905U); + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x4a060044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e060084U); + WR1_PROG(REG_1608H, 0x81010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x235613b1U, 0x1afbc29dU, 0x0b2a3381U, 0xc6990e63U); + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x02000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0e060094U); + WR1_PROG(REG_1608H, 0x81010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func070.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func070.c new file mode 100644 index 000000000..b5fda8442 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func070.c @@ -0,0 +1,145 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func070 (uint32_t ARG1) +{ + WR1_PROG(REG_1600H, 0x30003340U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0131ec45U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x014bb610U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01542614U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01ba24feU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01bb59d6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1404H, 0x10500000U); + WR1_PROG(REG_1444H, 0x00002fc2U); + WR1_PROG(REG_1A2CH, 0x00000b00U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 20]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 24]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x13700000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 28]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 32]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x18700000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 36]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 40]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x18c00000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 44]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 48]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10a00000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 52]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 56]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x18200000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 60]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 64]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 68]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func071.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func071.c new file mode 100644 index 000000000..ecb68db36 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func071.c @@ -0,0 +1,109 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func071 (uint32_t ARG1) +{ + WR1_PROG(REG_1600H, 0x30003340U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x017d423aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0163c737U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x017c67d8U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0126ddb5U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01bcfa36U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x00000300U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 4]); + WR1_PROG(REG_1404H, 0x11e00000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 8]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 12]); + WR1_PROG(REG_1404H, 0x12080000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 16]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func073.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func073.c new file mode 100644 index 000000000..2c15550e5 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func073.c @@ -0,0 +1,531 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func073 (uint32_t ARG1) +{ + uint32_t OFS_ADR = 0U; + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + OFS_ADR = ARG1; + HW_SCE_p_func100(0x84a0931eU, 0x6c7aafe2U, 0x0a6f4210U, 0x9b60601aU); + HW_SCE_p_func070(OFS_ADR); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000930U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000980U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xcef9e393U, 0xcd8c9be9U, 0x737c5a63U, 0x54ee8832U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x7a0abe3dU, 0xb6905c72U, 0xeade8244U, 0x2a5ecb1bU); + } + else + { + HW_SCE_p_func100(0x55ccd8e6U, 0xa6604119U, 0xaa733535U, 0xe4bd3110U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x0404000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8188001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0xdd6e45eeU, 0x7399eae8U, 0xc1e73523U, 0x74e2de2fU); + + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1404H, 0x11600000U); + WR1_PROG(REG_1400H, 0x00c000f1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func071(OFS_ADR); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000890U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000002c8U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x456987efU, 0xbdc11544U, 0x9350089eU, 0xb1f1e00dU); + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000340U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x04040015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x11e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x69486d91U, 0x0fac49f9U, 0x0871536dU, 0xe2762828U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x244247baU, 0x175c90d0U, 0xd88ce241U, 0x9100b730U); + } + else + { + HW_SCE_p_func100(0x9051c8f9U, 0x177313c4U, 0x76d1835cU, 0xb8a75443U); + WR1_PROG(REG_1404H, 0x11e00000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1608H, 0x81880001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1600H, 0x000037e1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8188001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000228U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000340U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x04040015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x11e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xfe7e8a73U, 0xefaa119aU, 0xd6a24166U, 0x06ec1cedU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x2d8a493eU, 0x15de4696U, 0xb8809e2fU, 0x511ee184U); + } + else + { + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040013U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xe80eb3b9U, 0xade40605U, 0xe0d9a345U, 0x951c6f53U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xaa4ea13eU, 0x96b111b7U, 0xa973c928U, 0x556ef0a7U); + } + else + { + HW_SCE_p_func100(0xdbc95198U, 0x91ef89edU, 0xd0998d9fU, 0x2a18af1aU); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0404000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000930U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xbc688a4fU, 0x6faa1a70U, 0xe8996f18U, 0x84878e0eU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x9ddb780bU, 0x6fef47bfU, 0x63cf2a87U, 0x4d98abb5U); + } + else + { + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x797935bbU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x712129c2U, 0xe52bc100U, 0xaf209cc6U, 0xe78960efU); + } + } + } + } + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x797935bbU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func074.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func074.c new file mode 100644 index 000000000..c399577ec --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func074.c @@ -0,0 +1,66 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func074 (void) +{ + WR1_PROG(REG_1600H, 0x30003340U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000023U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000017U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000015U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000013U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func075.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func075.c new file mode 100644 index 000000000..fa5c5d8a3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func075.c @@ -0,0 +1,66 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func075 (void) +{ + WR1_PROG(REG_1600H, 0x30003340U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000022U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001cU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000016U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000014U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000012U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func076.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func076.c new file mode 100644 index 000000000..0602b8c3a --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func076.c @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func076 (void) +{ + WR1_PROG(REG_1600H, 0x38000f5aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000019U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func077.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func077.c new file mode 100644 index 000000000..10a064a72 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func077.c @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func077 (void) +{ + WR1_PROG(REG_1600H, 0x38000f5aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000018U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func078.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func078.c new file mode 100644 index 000000000..7c4e9e489 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func078.c @@ -0,0 +1,128 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func078 (uint32_t ARG1) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x018d3a5eU)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x00005fc2U); + WR1_PROG(REG_1A2CH, 0x00001700U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + + WR1_PROG(REG_1404H, 0x10300000U); + for (iLoop = ARG1 + 36U; iLoop < ARG1 + 52U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1404H, 0x13500000U); + for (iLoop = ARG1 + 52U; iLoop < ARG1 + 68U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1404H, 0x18500000U); + for (iLoop = ARG1 + 68U; iLoop < ARG1 + 84U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1404H, 0x18a00000U); + for (iLoop = ARG1 + 84U; iLoop < ARG1 + 100U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1404H, 0x10800000U); + for (iLoop = ARG1 + 100U; iLoop < ARG1 + 116U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1404H, 0x18000000U); + for (iLoop = ARG1 + 116U; iLoop < ARG1 + 132U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func079.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func079.c new file mode 100644 index 000000000..c734b584f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func079.c @@ -0,0 +1,72 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func079 (uint32_t ARG1) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x01a9d8a8U)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x00001fc2U); + WR1_PROG(REG_1A2CH, 0x00000700U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + + WR1_PROG(REG_1404H, 0x11800000U); + for (iLoop = ARG1 + 0U; iLoop < ARG1 + 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1404H, 0x11c80000U); + for (iLoop = ARG1 + 16U; iLoop < ARG1 + 32U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 32]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func081.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func081.c new file mode 100644 index 000000000..9027064c0 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func081.c @@ -0,0 +1,121 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func081(void) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1600H, 0x00003424U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10000821U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x342028e4U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10000821U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000feU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000cU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000012U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000ba7U); + WR1_PROG(REG_1608H, 0x808c001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000012U)); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000014U)); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000016U)); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000018U)); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000001cU)); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000001eU)); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000020U)); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000000eU)); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000010U)); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000022U)); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000024U)); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000026U)); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 12U; iLoop++) + { + WR1_PROG(REG_1600H, 0x00003bdfU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3800089eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10003427U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000027fdU); + WR1_PROG(REG_1458H, 0x00000000U); + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func082.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func082.c new file mode 100644 index 000000000..69eb289df --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func082.c @@ -0,0 +1,126 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func082(void) +{ + HW_SCE_p_func100(0xba93eaa7U, 0x05671b49U, 0xd69de0acU, 0x9938cae4U); + WR1_PROG(REG_1600H, 0x0000b540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000001d0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8188000aU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xf56d641fU, 0x601a496cU, 0xb43e7e34U, 0xe6012455U); + WR1_PROG(REG_1A24H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x2c08e111U, 0xe9a4d5ceU, 0xfba49718U, 0x1b648022U); + + WR1_PROG(REG_1600H, 0x0000b540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000001c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8184000aU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x080000c5U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x0b040104U); + WR1_PROG(REG_1608H, 0x810100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1608H, 0x80040140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009105U); + + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x02000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009105U); + + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1400H, 0x01420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func086.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func086.c new file mode 100644 index 000000000..1127deff6 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func086.c @@ -0,0 +1,116 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func086 (uint32_t ARG1) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0123ba68U)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000077c2U); + WR1_PROG(REG_1A2CH, 0x00001d00U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + + WR1_PROG(REG_1404H, 0x10200000U); + for (iLoop = ARG1 + 44U; iLoop < ARG1 + 64U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1404H, 0x13400000U); + for (iLoop = ARG1 + 64U; iLoop < ARG1 + 84U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1404H, 0x18400000U); + for (iLoop = ARG1 + 84U; iLoop < ARG1 + 104U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1404H, 0x18900000U); + for (iLoop = ARG1 + 104U; iLoop < ARG1 + 124U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1404H, 0x10700000U); + for (iLoop = ARG1 + 124U; iLoop < ARG1 + 144U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1404H, 0x17f00000U); + for (iLoop = ARG1 + 144U; iLoop < ARG1 + 164U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func087.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func087.c new file mode 100644 index 000000000..68b484010 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func087.c @@ -0,0 +1,72 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func087 (uint32_t ARG1) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1A24H, 0x4a070044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e0704c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x01783e10U)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000027c2U); + WR1_PROG(REG_1A2CH, 0x00000900U); + WR1_PROG(REG_1A24H, 0xf7049d07U); + + WR1_PROG(REG_1404H, 0x11600000U); + for (iLoop = ARG1 + 00U; iLoop < ARG1 + 20U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1404H, 0x11b00000U); + for (iLoop = ARG1 + 20U; iLoop < ARG1 + 40U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1A24H, 0x07040d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_FLASH2[ARG1 + 40]); + + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func088.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func088.c new file mode 100644 index 000000000..a1359801b --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func088.c @@ -0,0 +1,186 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func088 (void) +{ + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x14100000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000890U); + WR1_PROG(REG_1018H, 0x00000430U); + WR1_PROG(REG_1020H, 0x000002c8U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000430U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x903ecd30U, 0x9ce27232U, 0x261042a7U, 0x7effdf98U); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000340U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x04040015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x701c2144U, 0xec3ffd09U, 0x15df70ecU, 0x15af5febU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x7f8bdea1U, 0xe5aa8672U, 0x74eb67cfU, 0x582e73d6U); + } + else + { + HW_SCE_p_func100(0x8e1a28afU, 0xd1b48bf6U, 0xd9689a57U, 0x065f1a84U); + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0404000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000520U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000548U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x618c5618U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xe15d3f11U, 0x0ed5085aU, 0x06021daeU, 0x7584162cU); + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x618c5618U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func089.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func089.c new file mode 100644 index 000000000..8326416f3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func089.c @@ -0,0 +1,186 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func089 (void) +{ + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1004H, 0x06060004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x13e00000U); + WR1_PROG(REG_1400H, 0x00c00031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000890U); + WR1_PROG(REG_1018H, 0x00000410U); + WR1_PROG(REG_1020H, 0x000002b8U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000410U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0xeceaf027U, 0x5426581dU, 0x7c6a346cU, 0xe7937e52U); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000340U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x06060015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xf5cc2279U, 0x978d2af4U, 0x4ee83633U, 0x79eba0e0U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x121d0955U, 0xec6251a1U, 0x5163e16fU, 0x9d8cc130U); + } + else + { + HW_SCE_p_func100(0xb1f3b369U, 0x8682c0bdU, 0xdbbd26b7U, 0x07fb636dU); + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x06060004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0606000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000500U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000538U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1714dcbaU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x55dc6348U, 0x416e89a4U, 0xd902dfa3U, 0xebb87567U); + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1714dcbaU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func090.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func090.c new file mode 100644 index 000000000..41d8132a2 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func090.c @@ -0,0 +1,186 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func090 (void) +{ + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1004H, 0x08080004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x13b00000U); + WR1_PROG(REG_1400H, 0x00c00041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000890U); + WR1_PROG(REG_1018H, 0x000003f0U); + WR1_PROG(REG_1020H, 0x000002a8U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x000003f0U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0xc1b6fc67U, 0x7365ef93U, 0x97006987U, 0x4ad15b75U); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000340U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x08080015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x0b0c9e4fU, 0x7cdde83eU, 0x9fab7db2U, 0x56baa29aU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x7a5d4290U, 0x67f5f466U, 0x6abae8d6U, 0x1c75e2a4U); + } + else + { + HW_SCE_p_func100(0x52732853U, 0x1b1602baU, 0x8f7ded13U, 0x91e36d97U); + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x08080004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0808000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000004e0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000528U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1b8be139U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xe532ea92U, 0x3bf36fceU, 0x8fbe6ac4U, 0xea94ae20U); + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1b8be139U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func091.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func091.c new file mode 100644 index 000000000..454f1b35e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func091.c @@ -0,0 +1,186 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func091 (void) +{ + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1004H, 0x09090004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x13980000U); + WR1_PROG(REG_1400H, 0x00c00049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000890U); + WR1_PROG(REG_1018H, 0x000003e0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x000003e0U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x41a2423dU, 0x84f6f754U, 0x9097392bU, 0x0315efb9U); + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000340U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x09090015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x8bf2558eU, 0x360fc160U, 0x423639a3U, 0x78b81201U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xd7ae3207U, 0xb65d2a58U, 0xab771a50U, 0x8baa5842U); + } + else + { + HW_SCE_p_func100(0x23a77542U, 0x399d08b4U, 0xfaa02d18U, 0x60c6b60cU); + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x09090004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0909000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000004d0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000520U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x313622d7U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x96ca2e68U, 0x2ddf7892U, 0xe05637edU, 0x4db857f4U); + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x313622d7U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func092.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func092.c new file mode 100644 index 000000000..0326bae83 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func092.c @@ -0,0 +1,208 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func092(void) +{ + HW_SCE_p_func100(0xc44d0685U, 0x40ec3827U, 0xb39c48c7U, 0xa3f024e9U); + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x4a060044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e060084U); + WR1_PROG(REG_1608H, 0x81010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xf1028bd2U, 0xb77e5d87U, 0xe7778d66U, 0xc636da10U); + WR1_PROG(REG_1600H, 0x00008d40U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00009140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x02000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0e060094U); + WR1_PROG(REG_1608H, 0x81010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x300032a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b6e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1204c99cU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b6e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0xa9ed4879U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b6e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x7c182e99U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008ee0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000092e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009104U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00008ee0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000092e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x02000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009044U); + WR1_PROG(REG_1608H, 0x810102e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func100(0x48696e70U, 0x4231f173U, 0xa4b4af7fU, 0x7ea89931U); + WR1_PROG(REG_1A24H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xe06a79bcU, 0x1ce2e33fU, 0xe7eccb45U, 0xa9d21b9fU); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000094U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1600H, 0x00008ec0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000092c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009104U); + WR1_PROG(REG_1608H, 0x810102c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1600H, 0x00008ec0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000092c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x02000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x30009044U); + WR1_PROG(REG_1608H, 0x810102c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func100(0xfec810d2U, 0x9e5c86e3U, 0x0b181c4dU, 0xa8d502f9U); + WR1_PROG(REG_1A24H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x0b510eabU, 0xc6d8662eU, 0x2d9aa488U, 0xcf10b94aU); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000094U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1600H, 0x00007c1dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func093.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func093.c new file mode 100644 index 000000000..cd5b6a67e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func093.c @@ -0,0 +1,403 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func093 (const uint32_t ARG1[], uint32_t ARG2[]) +{ + uint32_t iLoop = 0U; + uint32_t oLoop = 0U; + + HW_SCE_p_func100(0x700d45a4U, 0xc88e4b39U, 0xfb9a3a88U, 0xcb7bd92eU); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000ffU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x5a6fa76cU, 0xc3f5a279U, 0x76947271U, 0xac64b2fcU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x000034e4U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000feU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x81188bcdU, 0xd465cb3aU, 0x5460ee88U, 0xfa6e9d6dU); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xea88f7e8U, 0x8c73c3daU, 0xada49d15U, 0xe6e78f26U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1000H, 0x00010000U); + + HW_SCE_p_func081(); + + WR1_PROG(REG_1600H, 0x00007c01U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + oLoop = 0; + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + for (iLoop = 0U; iLoop < (INST_DATA_SIZE); ) + { + HW_SCE_p_func100(0xcaf0e3ddU, 0x2bafaf44U, 0x2d6379ccU, 0x634d5e35U); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1400H, 0x00810011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG2[1 + iLoop]); + + HW_SCE_p_func101(0xfd2a99ceU, 0xa2612117U, 0x1267722aU, 0x67fddc1fU); + iLoop = iLoop + 4U; + } + + oLoop = iLoop; + + HW_SCE_p_func101(0x2f8b022fU, 0xd4fcbf20U, 0x268da526U, 0xa0043c95U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000aU) + { + HW_SCE_p_func100(0x883efbd9U, 0x10be4127U, 0x9e42ed06U, 0x2a6f8bccU); + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func094(0U, ARG1); + iLoop = 32U; + + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func065(0U, ARG2); + HW_SCE_p_func100(0x0e7fe377U, 0x0057afc8U, 0x955969efU, 0x7faefecaU); + HW_SCE_p_func065(8U, ARG2); + HW_SCE_p_func100(0x7c53609cU, 0x4adc0feeU, 0xc88f44c3U, 0x5486ffadU); + HW_SCE_p_func065(16U, ARG2); + HW_SCE_p_func100(0x95c3d45eU, 0x645838d0U, 0x7e7729e0U, 0xfb7646e7U); + HW_SCE_p_func065(24U, ARG2); + oLoop = oLoop + 32U; + + HW_SCE_p_func100(0x4a0cb2b5U, 0x7eeb4cb4U, 0x150c3bf0U, 0xc0d1c58bU); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + iLoop = iLoop + 4U; + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00810011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG2[1 + oLoop]); + + WAIT_STS(REG_1A28H, 6, 0); + + HW_SCE_p_func100(0xe4427ea5U, 0xb923a279U, 0xf20e1de6U, 0xcc2db4fbU); + HW_SCE_p_func060(); + + WR1_PROG(REG_1404H, 0x11180000U); + HW_SCE_p_func062(36U, ARG2); + HW_SCE_p_func100(0x697637e6U, 0xab9f06a8U, 0x7c17be0dU, 0xa727a23cU); + HW_SCE_p_func062(44U, ARG2); + HW_SCE_p_func100(0xc9262b8aU, 0x047cd05bU, 0x3e8f12b2U, 0xc31d9b1dU); + HW_SCE_p_func062(52U, ARG2); + HW_SCE_p_func100(0xa1206d57U, 0xc68191cdU, 0xc9b3bddcU, 0xae966368U); + HW_SCE_p_func062(60U, ARG2); + oLoop = 36U + 32U; + + HW_SCE_p_func101(0xa6054347U, 0xfebb0bd4U, 0xebca76feU, 0x51a0bb78U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000bU) + { + HW_SCE_p_func100(0x465fc8d1U, 0x400001a6U, 0x424d5e49U, 0x2078dcf6U); + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func094(0U, ARG1); + iLoop = 32U; + + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func062(0U, ARG2); + HW_SCE_p_func100(0xf10a8e46U, 0xe3002cabU, 0x0f086e01U, 0xb264a8edU); + HW_SCE_p_func062(8U, ARG2); + HW_SCE_p_func100(0x59eaca4dU, 0xb8d66c8eU, 0xf38fe05aU, 0x594803c7U); + HW_SCE_p_func062(16U, ARG2); + HW_SCE_p_func100(0x860a541eU, 0xc1d26135U, 0xfd4a7c66U, 0x108a8ac3U); + HW_SCE_p_func062(24U, ARG2); + oLoop = oLoop + 32U; + + HW_SCE_p_func100(0x118a2be6U, 0xec5ba1d7U, 0xa6767038U, 0xe95230eeU); + WR1_PROG(REG_1404H, 0x11100000U); + HW_SCE_p_func094(32U, ARG1); + iLoop = 32U + 32U; + + WR1_PROG(REG_1404H, 0x11100000U); + HW_SCE_p_func062(32U, ARG2); + HW_SCE_p_func100(0x6d22b147U, 0x256e53d1U, 0xbf01a614U, 0xcae8cf46U); + HW_SCE_p_func062(40U, ARG2); + HW_SCE_p_func100(0xd5d5a40cU, 0x06d07f06U, 0x4c86d89aU, 0x1f69f627U); + HW_SCE_p_func062(48U, ARG2); + HW_SCE_p_func100(0x466fe75aU, 0x43adda6cU, 0xc3c67be2U, 0x102a971fU); + HW_SCE_p_func062(56U, ARG2); + oLoop = oLoop + 32U; + + HW_SCE_p_func100(0x2ef43445U, 0x37f6a287U, 0x7db606edU, 0x63813895U); + HW_SCE_p_func060(); + + WR1_PROG(REG_1404H, 0x11180000U); + HW_SCE_p_func062(64U, ARG2); + HW_SCE_p_func100(0xea83f41aU, 0x2b7e8254U, 0x33e0fc5bU, 0x322613c6U); + HW_SCE_p_func062(72U, ARG2); + HW_SCE_p_func100(0x14724698U, 0x3314682bU, 0x0f4ce1dbU, 0x2370fa3cU); + HW_SCE_p_func062(80U, ARG2); + HW_SCE_p_func100(0x62949a4dU, 0xca452050U, 0x525d9a06U, 0x408bab26U); + HW_SCE_p_func062(88U, ARG2); + oLoop = 64U + 32U; + + HW_SCE_p_func101(0x810607edU, 0xfa0c2f3bU, 0x4adfa484U, 0xc4b5bfbdU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000cU) + { + HW_SCE_p_func100(0xf4df8689U, 0x7e905961U, 0x770489d9U, 0x42bea35bU); + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func095(0U, ARG1); + iLoop = 64U; + + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func065(0U, ARG2); + HW_SCE_p_func100(0x82f0d2eaU, 0x9ac9e7a8U, 0xd15dcca9U, 0xa5f34f08U); + HW_SCE_p_func065(8U, ARG2); + HW_SCE_p_func100(0x22e8b5eaU, 0x3273f226U, 0xdde0b5a8U, 0xfeff2cd3U); + HW_SCE_p_func065(16U, ARG2); + HW_SCE_p_func100(0x83e15e6cU, 0x4d25fc27U, 0x7810be5bU, 0xafd1e06aU); + HW_SCE_p_func065(24U, ARG2); + HW_SCE_p_func100(0x70a3caacU, 0x5d1b46e5U, 0x7186268bU, 0x1608ad09U); + HW_SCE_p_func065(32U, ARG2); + HW_SCE_p_func100(0x1869fa48U, 0x803c5e42U, 0x537d7bc3U, 0x73ed45e9U); + HW_SCE_p_func065(40U, ARG2); + HW_SCE_p_func100(0x1999ad95U, 0x89516147U, 0x346608bdU, 0xbf8c0b0aU); + HW_SCE_p_func065(48U, ARG2); + HW_SCE_p_func100(0xa8853929U, 0x80f97c28U, 0xb883e053U, 0x7e31fcd3U); + HW_SCE_p_func065(56U, ARG2); + oLoop = oLoop + 64U; + + HW_SCE_p_func100(0xefdbccb9U, 0xcaf62151U, 0x59a90bb3U, 0x233f618fU); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + iLoop = iLoop + 4U; + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00810011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG2[1 + oLoop]); + + WAIT_STS(REG_1A28H, 6, 0); + + HW_SCE_p_func100(0xa45b4f5fU, 0x26a39228U, 0x401ef2ccU, 0x4dd2f366U); + HW_SCE_p_func066(); + + WR1_PROG(REG_1404H, 0x11180000U); + HW_SCE_p_func062(68U, ARG2); + HW_SCE_p_func100(0x711a9774U, 0xa483956dU, 0x7ee799f8U, 0xa5e0da1fU); + HW_SCE_p_func062(76U, ARG2); + HW_SCE_p_func100(0xfc30c578U, 0x905bcbeeU, 0x57c84f4bU, 0xec2c4ee9U); + HW_SCE_p_func062(84U, ARG2); + HW_SCE_p_func100(0x86c104cfU, 0x983f80b5U, 0x9ed08ba8U, 0x389b1a32U); + HW_SCE_p_func062(92U, ARG2); + HW_SCE_p_func100(0x85e63e4bU, 0xc51ba1a8U, 0xde52085dU, 0x86ac5bc7U); + HW_SCE_p_func062(100U, ARG2); + HW_SCE_p_func100(0x179c9b1aU, 0x1f605dbbU, 0x0712d896U, 0x1dfbb1a6U); + HW_SCE_p_func062(108U, ARG2); + HW_SCE_p_func100(0x35484559U, 0xf5a5c5e9U, 0xd09af002U, 0xca781271U); + HW_SCE_p_func062(116U, ARG2); + HW_SCE_p_func100(0xcf259f52U, 0x9fd2f79dU, 0x5e15ef07U, 0xdae4bebeU); + HW_SCE_p_func062(124U, ARG2); + oLoop = 68U + 64U; + + HW_SCE_p_func101(0xc754a252U, 0xfd1be47cU, 0xdfd985acU, 0xf333779fU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000dU) + { + HW_SCE_p_func100(0x4f2061c5U, 0xfd862feeU, 0x1ac89a20U, 0x5e422cf1U); + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func095(0U, ARG1); + iLoop = 64U; + + WR1_PROG(REG_1404H, 0x10000000U); + HW_SCE_p_func062(0U, ARG2); + HW_SCE_p_func100(0x9742b7fdU, 0xf0763297U, 0x51e50993U, 0x5cf76f91U); + HW_SCE_p_func062(8U, ARG2); + HW_SCE_p_func100(0x8de602aeU, 0x08168872U, 0x7f34367aU, 0xe8c1cbe9U); + HW_SCE_p_func062(16U, ARG2); + HW_SCE_p_func100(0xd4376114U, 0x46d10b9dU, 0xa59e6636U, 0xf45e8609U); + HW_SCE_p_func062(24U, ARG2); + HW_SCE_p_func100(0x0813c025U, 0xc87a6178U, 0xa8e78ad8U, 0x10fe30abU); + HW_SCE_p_func062(32U, ARG2); + HW_SCE_p_func100(0x053e1561U, 0xe46a349bU, 0xfa597c68U, 0x2770d863U); + HW_SCE_p_func062(40U, ARG2); + HW_SCE_p_func100(0x124a3edfU, 0x87b92b32U, 0xef781c02U, 0xdcc7ec46U); + HW_SCE_p_func062(48U, ARG2); + HW_SCE_p_func100(0x202debbaU, 0xa85a68d8U, 0xc6c868d1U, 0x70f0c9fdU); + HW_SCE_p_func062(56U, ARG2); + oLoop = oLoop + 64U; + + HW_SCE_p_func100(0x240f1facU, 0xf7d9b6e0U, 0xfe6fe211U, 0xbf082b84U); + WR1_PROG(REG_1404H, 0x11100000U); + HW_SCE_p_func095(64U, ARG1); + iLoop = 64U + 64U; + + WR1_PROG(REG_1404H, 0x11100000U); + HW_SCE_p_func062(64U, ARG2); + HW_SCE_p_func100(0xc92d660cU, 0x44467a53U, 0x81cdebd7U, 0x49f7ae62U); + HW_SCE_p_func062(72U, ARG2); + HW_SCE_p_func100(0x80e9dcabU, 0x7b970d10U, 0x0c6af314U, 0xd5761810U); + HW_SCE_p_func062(80U, ARG2); + HW_SCE_p_func100(0x86f337eeU, 0x7e11979bU, 0x7059287bU, 0x851bd86fU); + HW_SCE_p_func062(88U, ARG2); + HW_SCE_p_func100(0x7d3d7152U, 0x6fb85144U, 0x53556a56U, 0x42967bceU); + HW_SCE_p_func062(96U, ARG2); + HW_SCE_p_func100(0x2df9b663U, 0x4db2038fU, 0x4c816069U, 0x8ba89da3U); + HW_SCE_p_func062(104U, ARG2); + HW_SCE_p_func100(0xa1271485U, 0x7021b6afU, 0x89e6df79U, 0x200a15afU); + HW_SCE_p_func062(112U, ARG2); + HW_SCE_p_func100(0x5ce0eff0U, 0x07847ed5U, 0x419ce2a2U, 0xf6882a81U); + HW_SCE_p_func062(120U, ARG2); + oLoop = oLoop + 64U; + + HW_SCE_p_func100(0x1670048eU, 0x1d65f7e4U, 0xcb782416U, 0x77e06f17U); + HW_SCE_p_func066(); + + WR1_PROG(REG_1404H, 0x11180000U); + HW_SCE_p_func062(128U, ARG2); + HW_SCE_p_func100(0x07379295U, 0x96be1f33U, 0x781df0f3U, 0x3644a5d6U); + HW_SCE_p_func062(136U, ARG2); + HW_SCE_p_func100(0xd0efa1f3U, 0x1c515ecbU, 0x3b3bb1eeU, 0x2ac2f752U); + HW_SCE_p_func062(144U, ARG2); + HW_SCE_p_func100(0x56b8287bU, 0x20fb42c9U, 0x91e58c77U, 0x9299a6f9U); + HW_SCE_p_func062(152U, ARG2); + HW_SCE_p_func100(0x386ee0ddU, 0x90e2b77eU, 0x0da4cf4aU, 0x39625da9U); + HW_SCE_p_func062(160U, ARG2); + HW_SCE_p_func100(0xe8bbb2c8U, 0x618c05b7U, 0x178c8491U, 0x57741c31U); + HW_SCE_p_func062(168U, ARG2); + HW_SCE_p_func100(0x2ba2c379U, 0x2128d84eU, 0xcacaa775U, 0xc6b911ebU); + HW_SCE_p_func062(176U, ARG2); + HW_SCE_p_func100(0x214e604dU, 0x85f45d5aU, 0xe8b6d0acU, 0x66afb1d3U); + HW_SCE_p_func062(184U, ARG2); + oLoop = 128U + 64U; + + HW_SCE_p_func101(0xd2ce4facU, 0x11d07619U, 0x308989b3U, 0x5523843fU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000012U) + { + for (iLoop = 0U; iLoop < (INST_DATA_SIZE); ) + { + HW_SCE_p_func100(0x6d1d8addU, 0x003a7380U, 0x8a196597U, 0xeda48acdU); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG1[iLoop]); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00810011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG2[1 + iLoop]); + + HW_SCE_p_func101(0x7a3f3191U, 0x6fb2bf7eU, 0x8ae82f99U, 0xe9a29251U); + iLoop = iLoop + 4U; + } + + oLoop = iLoop; + + HW_SCE_p_func101(0xb6e01d24U, 0x495319dfU, 0xbae6fc17U, 0x164fd4e8U); + } + + HW_SCE_p_func100(0x5f7f7e31U, 0x738c66fdU, 0x3c478859U, 0xab9d49b1U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &ARG2[1 + oLoop]); + + WR1_PROG(REG_1600H, 0x00007c1cU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func094.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func094.c new file mode 100644 index 000000000..ab37a8d15 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func094.c @@ -0,0 +1,43 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func094 (uint32_t ARG1, const uint32_t ARG2[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00001fc1U); + WR1_PROG(REG_182CH, 0x00000700U); + WR1_PROG(REG_1824H, 0x08008107U); + + for (iLoop = ARG1; iLoop < ARG1 + 32U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c10021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func095.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func095.c new file mode 100644 index 000000000..adb4b2a5e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func095.c @@ -0,0 +1,43 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func095 (uint32_t ARG1, const uint32_t ARG2[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00003fc1U); + WR1_PROG(REG_182CH, 0x00000f00U); + WR1_PROG(REG_1824H, 0x08008107U); + + for (iLoop = ARG1; iLoop < ARG1 + 64U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &ARG2[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c10021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func100.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func100.c new file mode 100644 index 000000000..963f8a5d2 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func100.c @@ -0,0 +1,30 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func100(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + WR1_PROG(REG_1A24H, 0x0a0701f5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, change_endian_long(ARG1), change_endian_long(ARG2), change_endian_long(ARG3), change_endian_long(ARG4)); + WAIT_STS(REG_1A28H, 16, 0); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func101.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func101.c new file mode 100644 index 000000000..375808b14 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func101.c @@ -0,0 +1,30 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func101(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + WR1_PROG(REG_1A24H, 0x0a0701e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, change_endian_long(ARG1), change_endian_long(ARG2), change_endian_long(ARG3), change_endian_long(ARG4)); + WAIT_STS(REG_1A28H, 17, 0); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func102.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func102.c new file mode 100644 index 000000000..a88d7e888 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func102.c @@ -0,0 +1,29 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func102(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4) +{ + WR1_PROG(REG_1A24H, 0x0a0701d5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, change_endian_long(ARG1), change_endian_long(ARG2), change_endian_long(ARG3), change_endian_long(ARG4)); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func103.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func103.c new file mode 100644 index 000000000..182865d86 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func103.c @@ -0,0 +1,53 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func103(void) +{ + WR1_PROG(REG_1444H, 0x000002a2U); + WR1_PROG(REG_1A24H, 0x07330c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x07330d04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x07330d04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x06330074U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x080000b5U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func202.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func202.c new file mode 100644 index 000000000..8579b1b88 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func202.c @@ -0,0 +1,35 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func202(void) +{ + WR1_PROG(REG_1408H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000000U); + WR1_PROG(REG_1824H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00000000U); + WR1_PROG(REG_1A24H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00000900U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func209.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func209.c new file mode 100644 index 000000000..b3092e538 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func209.c @@ -0,0 +1,33 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func209 (void) +{ + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000800U); + WR1_PROG(REG_143CH, 0x00000a00U); + WR1_PROG(REG_143CH, 0x00000900U); + WR1_PROG(REG_1A24H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func214.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func214.c new file mode 100644 index 000000000..eb6417b45 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func214.c @@ -0,0 +1,33 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func214(void) +{ + WR1_PROG(REG_1408H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00000400U); + WR1_PROG(REG_143CH, 0x00000600U); + WR1_PROG(REG_143CH, 0x00000500U); + WR1_PROG(REG_1824H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func215.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func215.c new file mode 100644 index 000000000..2d3e20fa2 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func215.c @@ -0,0 +1,35 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func215(void) +{ + WR1_PROG(REG_1408H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_1828H, 6, 0); + + WR1_PROG(REG_143CH, 0x00000400U); + WR1_PROG(REG_143CH, 0x00000600U); + WR1_PROG(REG_143CH, 0x00000500U); + WR1_PROG(REG_1824H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func216.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func216.c new file mode 100644 index 000000000..d762cffc9 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_func216.c @@ -0,0 +1,33 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_p_func216(void) +{ + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_1828H, 6, 0); + WR1_PROG(REG_143CH, 0x00000400U); + WR1_PROG(REG_143CH, 0x00000600U); + WR1_PROG(REG_143CH, 0x00000500U); + WR1_PROG(REG_1824H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p00.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p00.c new file mode 100644 index 000000000..1f2acb9b3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p00.c @@ -0,0 +1,30 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_SoftwareResetSub (void) +{ + WR1_PROG(REG_140CH, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p07.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p07.c new file mode 100644 index 000000000..c435167e0 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p07.c @@ -0,0 +1,127 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00070001U); + WR1_PROG(REG_144CH, 0x00000000U); + + HW_SCE_p_func100(0x2cbcb901U, 0x075c5d65U, 0xdc13fd9bU, 0x34e52d2fU); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000007U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xa96a345eU, 0x6df67a43U, 0xa26c3c6aU, 0x1d9e2a89U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000007U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x1367b071U, 0x72c3a34bU, 0x2d4adfeeU, 0xe9bd39a9U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x2944a216U, 0xe4f4c031U, 0xc6aee970U, 0xc1ff5abaU); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + HW_SCE_p_func100(0x194b5554U, 0x5a11380dU, 0xda8593efU, 0xca27984dU); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7009d45U); + WR1_PROG(REG_1608H, 0x81040000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x2d13bf85U, 0x2ce07eb5U, 0x8c1df081U, 0xc5f34b1dU); + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, change_endian_long(0x00000000U), change_endian_long(0x00000000U), change_endian_long(0x00000000U), change_endian_long(0x00000001U)); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + + HW_SCE_p_func102(0x36e6ce1cU, 0xb026eb80U, 0xcf6fc2baU, 0x247d5109U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p08.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p08.c new file mode 100644 index 000000000..885a4c1fa --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p08.c @@ -0,0 +1,138 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00080001U); + WR1_PROG(REG_144CH, 0x00000000U); + + HW_SCE_p_func100(0x76e553b2U, 0x47c322a9U, 0x2cd9d68aU, 0x5d708cbeU); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000008U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x983a092bU, 0x0423b378U, 0xea9ce53dU, 0x87be131fU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000008U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x5eb0ecd6U, 0x9a72a00cU, 0xc57c1c73U, 0xff4a5e75U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x9be8a114U, 0xc41d36b4U, 0x4b3f15daU, 0xf17379e2U); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + HW_SCE_p_func100(0xca4e6244U, 0x9573c2cbU, 0x38df5866U, 0x7a05e1d4U); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1608H, 0x80080000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + HW_SCE_p_func100(0xe81dfabbU, 0xf84a0569U, 0xc2b69680U, 0x4d1a65dcU); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + HW_SCE_p_func100(0xe84cb1b5U, 0xc4a0a5e7U, 0x4c7d30a0U, 0xd44d7159U); + + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d47U); + WR1_PROG(REG_1608H, 0x81080000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, change_endian_long(0x00000000U), change_endian_long(0x00000000U), change_endian_long(0x00000000U), change_endian_long(0x00000002U)); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[9]); + + HW_SCE_p_func102(0x93554d8fU, 0x29458b55U, 0xd7434f09U, 0xe4c435cfU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p11.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p11.c new file mode 100644 index 000000000..bfe3639a7 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p11.c @@ -0,0 +1,504 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_EcdsaP521SignatureGenerateSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00110001U); + WR1_PROG(REG_144CH, 0x00000000U); + + HW_SCE_p_func100(0xf44d61f9U, 0x5fbd7bfbU, 0x1007b221U, 0xbfa2dee7U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000340U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + HW_SCE_p_func100(0x74c2a521U, 0x3e7f1449U, 0x3495ed04U, 0xbcaab147U); + HW_SCE_p_func086(OFS_ADR); + + HW_SCE_p_func100(0x3483dc18U, 0x4f9f6a41U, 0x769a1342U, 0xf9097f41U); + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c80000U); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x93b2483bU, 0xb4727143U, 0x83d1af2dU, 0x9e5513c9U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0xf2d51ce5U, 0xb724d49aU, 0xf040ac18U, 0x5d6148daU); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0xc1d401b7U, 0xf96d52faU, 0xaed130b0U, 0xa25354fbU); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0x44200db3U, 0x92194f62U, 0xc375d14fU, 0xd255049bU); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000340U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x09090004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x3c55a513U, 0x1cda2531U, 0xed27f9e5U, 0x82c173a8U); + HW_SCE_p_func087(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000011U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xf018511dU, 0x755a9b55U, 0x63dad1ebU, 0xf5f42f49U); + HW_SCE_p_func091(); + + HW_SCE_p_func100(0xc63852aeU, 0xfbace8f9U, 0x58e51de6U, 0xc8d2f946U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x1687c0a9U, 0x7b8e91d6U, 0x698e02c9U, 0xbe73fb38U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002f0U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x09090004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000140U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xa78b2d30U, 0x56ae0843U, 0xe21a1f63U, 0x21ae187eU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x7efaf277U, 0x22ba3e8bU, 0x24fcfa10U, 0xb63e1c28U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xa025b778U, 0xf03c721cU, 0xc399b704U, 0xc4a38812U); + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0909000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11100000U); + WR1_PROG(REG_1400H, 0x00c00011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x00000300U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x11200000U); + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MsgDgst[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000011U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xdcdcf122U, 0x8f8e637eU, 0xda600049U, 0x6d12ce1aU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000025U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000011U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x5ad1c802U, 0x4f354f59U, 0xeba0456aU, 0xd7dcfac6U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000013c2U); + WR1_PROG(REG_1A2CH, 0x40000400U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1404H, 0x11b00000U); + + for (iLoop = 0U; iLoop < 20U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x56737c62U, 0x13c32467U, 0x8404ae8cU, 0xca573a96U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x76526186U, 0x7c621166U, 0xeb71a1eaU, 0x9a781be8U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000140U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x97ba58beU, 0x7d2d8ae0U, 0xb851c78dU, 0x23a552ffU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xebe84c04U, 0x549e44feU, 0x82d9493cU, 0x5bf7b9daU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x4474302eU, 0x8986c869U, 0x797f925eU, 0x4d15b129U); + WR1_PROG(REG_1404H, 0x12500000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[0]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[4]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[8]); + + HW_SCE_p_func100(0xaff3cac1U, 0xbfedbab7U, 0x9daeadf6U, 0xcc9ead5dU); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[12]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[16]); + + HW_SCE_p_func100(0x01617084U, 0x430c1582U, 0x231c7b8bU, 0x5c4544a0U); + WR1_PROG(REG_1404H, 0x11b00000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[20]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[24]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[28]); + + HW_SCE_p_func100(0x00fab011U, 0xf0475686U, 0xaf4cb7f7U, 0xd7f07673U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[32]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[36]); + + HW_SCE_p_func102(0x3c42933aU, 0xb08e617bU, 0x7cd2f6fdU, 0xb0c28fc4U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p12.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p12.c new file mode 100644 index 000000000..28b2499be --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p12.c @@ -0,0 +1,758 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_EcdsaP521SignatureVerificationSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00120001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000012U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x4b31cc30U, 0x6aa52f12U, 0x0d57121dU, 0xab5ba459U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000024U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000012U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x59811c69U, 0xd18fe4fdU, 0xf222ef65U, 0xbce94b0dU); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000027c2U); + WR1_PROG(REG_1A2CH, 0x40000900U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80a80001U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + WR1_PROG(REG_1400H, 0x03420031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[13]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[17]); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[21]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[25]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[29]); + WR1_PROG(REG_1400H, 0x03420031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[33]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[37]); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[41]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x3ae21972U, 0xfe7e0ed2U, 0x431b4ef3U, 0xf5f5b7f3U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x4277a790U, 0x07d8f252U, 0xfcb90aabU, 0xdcee39d4U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x00000fc7U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8090001fU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MsgDgst[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000012U)); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + HW_SCE_p_func100(0xda41b249U, 0x980f137bU, 0xfaed7a72U, 0xb732414eU); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000340U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + HW_SCE_p_func100(0x6cf612fcU, 0x36d498dfU, 0x381077a8U, 0x46fd7aabU); + HW_SCE_p_func086(OFS_ADR); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x18e00000U); + WR1_PROG(REG_1444H, 0x000027c2U); + WR1_PROG(REG_1A2CH, 0x00000900U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[4]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[8]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[12]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[16]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19300000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[20]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[24]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[28]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[32]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[36]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11b80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000930U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000980U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xd485d508U, 0xaf40748eU, 0x497d6e1eU, 0xdcc3c792U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xaacf972cU, 0x7d787eccU, 0xa4d192ccU, 0xd4c38cc0U); + } + else + { + HW_SCE_p_func100(0xdf847ce1U, 0xf02f0d90U, 0xcbc63a0dU, 0xd086afb3U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x0909000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c00000U); + WR1_PROG(REG_1400H, 0x00c00011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8190001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00c90041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x9feda671U, 0x8ef4d7cfU, 0x4b027f6eU, 0x9123ffcdU); + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1404H, 0x11600000U); + WR1_PROG(REG_1400H, 0x00c000f1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func087(OFS_ADR); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x09090004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1400H, 0x00c00049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000890U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0xb2fcec2bU, 0x3d5bc03aU, 0xc30be8d1U, 0x4acff2c1U); + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000340U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x09090015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x11b80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x260362a0U, 0x353622f0U, 0x77ec2e3aU, 0x562ca0d8U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x77ae8b87U, 0x893e27e2U, 0x39370cfdU, 0x27d39af9U); + } + else + { + HW_SCE_p_func100(0x1fe391a8U, 0xbbf81946U, 0x7ad99f77U, 0xd2ac4406U); + WR1_PROG(REG_1404H, 0x11680000U); + WR1_PROG(REG_1400H, 0x00c00049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c00000U); + WR1_PROG(REG_1608H, 0x81940001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00c90051U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c00000U); + WR1_PROG(REG_1600H, 0x000037e1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000050U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8194001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00c90051U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000340U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x09090015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x11b80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x80e90a2aU, 0xe1b8a6a6U, 0x1dde06eeU, 0xcc661d1aU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xf10c44c0U, 0x8e00c022U, 0xb5f75631U, 0xc5983211U); + } + else + { + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x09090013U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x12580000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xf523dcbfU, 0xa0d5e8edU, 0xacf65d67U, 0xfc70a625U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x4c455fe8U, 0x7dccef52U, 0xf77bb68fU, 0x69a8c95eU); + } + else + { + HW_SCE_p_func100(0x5013b99eU, 0x2ea09b35U, 0x3c0fbc36U, 0x57590177U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x09090004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0909000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000930U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x134f4b18U, 0x27e16601U, 0x8ae7fc72U, 0xa504e1a0U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xf945c1d9U, 0xeab24859U, 0x6cea408eU, 0xceee1151U); + } + else + { + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x797935bbU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xe338f5c0U, 0x27d56af9U, 0x1728a974U, 0xed369e18U); + } + } + } + } + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x797935bbU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00007c1bU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x9cd3c688U, 0x50cc9514U, 0x8f2e2154U, 0xe215834bU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x194339d4U, 0xa15ef339U, 0xf21fa673U, 0x81e761ddU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0x421d7944U, 0xd73e71d7U, 0x21f8400cU, 0x6ec594dbU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p13.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p13.c new file mode 100644 index 000000000..41eba872b --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p13.c @@ -0,0 +1,670 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateEccP521RandomKeyIndexSub (uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x007f0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + HW_SCE_p_func100(0x8bdf5198U, 0x9a4e2a55U, 0xb46001aaU, 0x6fd4d15aU); + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000340U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + HW_SCE_p_func100(0xedf9bbf0U, 0x0b6cfc9bU, 0xbcc184f3U, 0xe64112d1U); + HW_SCE_p_func086(OFS_ADR); + + HW_SCE_p_func100(0x6eaf1608U, 0x3fe68451U, 0x06e3c513U, 0x544dcb20U); + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12a00000U); + HW_SCE_p_func103(); + HW_SCE_p_func100(0xb7375aadU, 0x1732cf60U, 0x69a6de37U, 0x662ffe05U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1608H, 0x80020000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008c20U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000001ffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81020000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00c90009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0xfad4788eU, 0x26b5ddaeU, 0x6fa92ffeU, 0x3f3aee05U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0x79890f5bU, 0xc0b08978U, 0xd983bff3U, 0xbd0e27e8U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0xfb6349b7U, 0x92c9a98eU, 0xa5d0cdcdU, 0x161d364fU); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x09090007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x7b5cf435U, 0x816520d5U, 0x0c484482U, 0x7f65dc67U); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x12000000U); + WR1_PROG(REG_1608H, 0x80940001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03430051U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + for (iLoop = 0U; iLoop < 20U; iLoop++) + { + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x20000842U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10003841U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x3800585eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x20003460U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10002c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x100033c0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1404H, 0x14300000U); + WR1_PROG(REG_1400H, 0x00c00051U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0a0a0009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0004dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00003403U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003060U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0a0a0007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0a0a0009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00003060U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xe88d8134U, 0x63a40da9U, 0x0c296f32U, 0xc9925b74U); + } + + WR1_PROG(REG_1600H, 0x00007c03U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10c00000U); + WR1_PROG(REG_1400H, 0x00c00051U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x7600e764U, 0x5f42bc8aU, 0xb4f9f309U, 0x14f285fbU); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0a0a000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + HW_SCE_p_func100(0xc0294141U, 0xe8913182U, 0xa28f0b1bU, 0x9ee3c9a3U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x0a0a0009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func101(0x21992a22U, 0x59bb65dcU, 0x6a235b60U, 0x2781295fU); + } + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0a0a000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0a0a0009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1600H, 0x00003000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x55db461fU, 0xf9a92663U, 0xe2dff381U, 0xc7633c9bU); + } + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x23f1f377U, 0x17a727f2U, 0x5fe8df61U, 0x6481697dU); + + HW_SCE_p_func087(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000013U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xb39e420aU, 0xadbff639U, 0x30527fe5U, 0xbc39e66eU); + HW_SCE_p_func091(); + + HW_SCE_p_func100(0x5161bfa7U, 0xfdd54d7bU, 0xc7bfefddU, 0x8b03faa2U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x23e74447U, 0x828fd48bU, 0xd940fa4cU, 0x40769013U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x63db03c5U, 0x9217e3fbU, 0x03cac1d1U, 0x7c93279bU); + HW_SCE_p_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000013U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x99a74a06U, 0x8ae14976U, 0xb5d0bca7U, 0x651674f6U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000025U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000013U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x1afd7321U, 0xcad64c3aU, 0x04e03ecbU, 0x18e21d06U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x573c3c2bU, 0x0eb8b4efU, 0x6871f7ebU, 0xf9453bddU); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1404H, 0x12f80000U); + WR1_PROG(REG_1400H, 0x00800009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00830029U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func100(0xfe45bfbcU, 0x176eebb4U, 0x371a9225U, 0x12c8d6eeU); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7008d07U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[iLoop + 1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[iLoop + 5]); + + HW_SCE_p_func100(0x21de683eU, 0xe30a75dfU, 0x161294ebU, 0xde1a059aU); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[iLoop + 9]); + + HW_SCE_p_func100(0x93c7ef26U, 0xbe63fe45U, 0x10b91501U, 0x0e12ac20U); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PrivKeyIndex[0]); + + HW_SCE_p_func100(0xd12aa79dU, 0x2c0a4149U, 0x46cd9ea5U, 0xef18f15dU); + HW_SCE_p_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000113U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x5384b58dU, 0xfe97d280U, 0x9634ee9fU, 0x03fc24e6U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000024U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000113U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x18eae45cU, 0x4569f5f0U, 0x3f77bb3eU, 0x046031b7U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xfdf8c860U, 0xd403e07eU, 0xdeb67024U, 0x582666e9U); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8009107U); + WR1_PROG(REG_1404H, 0x12580000U); + WR1_PROG(REG_1400H, 0x00800009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00830029U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func100(0x93053703U, 0xc7b64904U, 0x3e295b75U, 0x1a0640efU); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x12a80000U); + WR1_PROG(REG_1400H, 0x00800009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00830009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = iLoop; iLoop < 24U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func100(0x8be7234aU, 0x740d1796U, 0x9851b370U, 0xccb889aeU); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = iLoop; iLoop < 36U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func100(0xe27eb68aU, 0xf84522cfU, 0x66d55b79U, 0x58a7ee08U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + + HW_SCE_p_func100(0x9986d06cU, 0x4bdc6d92U, 0xcebe0074U, 0xfe0152d9U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 5]); + + HW_SCE_p_func100(0xcc4c41ebU, 0xd0825671U, 0x6c0c0ffaU, 0x1da9bd18U); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PubKeyIndex[0]); + + HW_SCE_p_func102(0x810f7e0dU, 0xd728649fU, 0x909a63ffU, 0xcd7c7ba5U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p14.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p14.c new file mode 100644 index 000000000..86d4f7a89 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p14.c @@ -0,0 +1,450 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Ecc521ScalarMultiplicationSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_PubKey[], + uint32_t OutData_R[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00140001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000027c7U); + WR1_PROG(REG_1608H, 0x80a8001eU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 40U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_PubKey[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bbdU); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 2U; iLoop++) + { + for (jLoop = 0U; jLoop < 3U; jLoop++) + { + WR1_PROG(REG_1600H, 0x0000381eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x100053fdU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002fa0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000a7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x0000381eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0xfffffe00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x100053fdU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002fa0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000050U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000ffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x2fdb53b5U, 0x4c4e6e45U, 0x5dfb16d9U, 0xbbdcfb5bU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xeefaf335U, 0x68bb8237U, 0xf1b0ce1cU, 0x984480f7U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000014U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x0ba227e1U, 0x37c6c9bfU, 0x658f228cU, 0x338075d9U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000025U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000014U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xde586d4dU, 0xe221cfa1U, 0x9e3d7ab0U, 0xa1951439U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000013c2U); + WR1_PROG(REG_1A2CH, 0x40000400U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1404H, 0x12f00000U); + + for (iLoop = 0U; iLoop < 20U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xdd3b4331U, 0x6be56c3cU, 0xd6f35230U, 0xa003e5fdU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x10970d87U, 0x1cdc8ed2U, 0x9983d7edU, 0x3b62203dU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0xa9a76adbU, 0xa3ffd4c1U, 0x85857600U, 0xa4f99bf4U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000340U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + HW_SCE_p_func100(0xb3cc917eU, 0x688d3994U, 0xa034ea15U, 0x4f5900e4U); + HW_SCE_p_func086(OFS_ADR); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x09090010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81a8001eU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10c00000U); + WR1_PROG(REG_1400H, 0x00c90051U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11100000U); + WR1_PROG(REG_1400H, 0x00c90051U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x09090001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000890U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x09090005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x09090002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000008e0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x09090005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x09090001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x990484aaU, 0xa79c9600U, 0xf79c27d7U, 0x13492c76U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x6d5722fdU, 0x1f20a700U, 0xe074f769U, 0x1c4cc1edU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1400H, 0x00c00049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000014U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x2a30d970U, 0xd4104df7U, 0xa7ba2922U, 0x1e02e871U); + HW_SCE_p_func091(); + + HW_SCE_p_func100(0x0e2edb98U, 0xe815f177U, 0x4d827278U, 0xc3c25f58U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xd0fb95ffU, 0xd9969eefU, 0x8a63179eU, 0x7da0a139U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xfb283ff1U, 0xc35dea02U, 0xab097e8fU, 0x30dee908U); + WR1_PROG(REG_1404H, 0x12500000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[0]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[4]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[8]); + + HW_SCE_p_func100(0x12661751U, 0xf07d1e85U, 0xa4213ef6U, 0x3a457f67U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[12]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[16]); + + HW_SCE_p_func100(0x9448be0aU, 0x49223d04U, 0x559baed6U, 0x2e18486dU); + WR1_PROG(REG_1404H, 0x12a00000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[20]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[24]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[28]); + + HW_SCE_p_func100(0x8852687dU, 0xb1a4d26aU, 0xb572c9ddU, 0x7dbb26d2U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[32]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[36]); + + HW_SCE_p_func102(0x80bced55U, 0xa4422b79U, 0x145cabccU, 0x1913587aU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p15.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p15.c new file mode 100644 index 000000000..728bcbb68 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p15.c @@ -0,0 +1,141 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateAes192RandomKeyIndexSub (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00150001U); + WR1_PROG(REG_144CH, 0x00000000U); + + HW_SCE_p_func100(0x52e1abf2U, 0x61d0e163U, 0x57516416U, 0x80aacc3fU); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000015U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x1bda7d91U, 0xfd415514U, 0xe472a114U, 0x22ed3104U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000015U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x2043b815U, 0x768035ffU, 0xcae6c42bU, 0x9c21f547U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xe33a9ebdU, 0xc302ca05U, 0x772d76f4U, 0xa0bd901aU); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + HW_SCE_p_func100(0xd9e9ce04U, 0xc26ebd09U, 0xe5fe7d83U, 0xfd5b130aU); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1608H, 0x80080000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + HW_SCE_p_func100(0x7e6aa56bU, 0xc5171038U, 0xd1aa76acU, 0x4e184405U); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x24a7d071U, 0xf078aef3U, 0x818219feU, 0xf63f5e6aU); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d47U); + WR1_PROG(REG_1608H, 0x81060000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890019U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00800009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, change_endian_long(0x00000000U), change_endian_long(0x00000000U), change_endian_long(0x00000000U), change_endian_long(0x00000002U)); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[9]); + + HW_SCE_p_func102(0xe5af211aU, 0xaebb66f5U, 0xd5e09583U, 0xccee7cbdU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p16.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p16.c new file mode 100644 index 000000000..e6ad98259 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p16.c @@ -0,0 +1,139 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateAes128XtsRandomKeyIndexSub (uint32_t OutData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00160001U); + WR1_PROG(REG_144CH, 0x00000000U); + + HW_SCE_p_func100(0x1b4a9f9cU, 0x4a4f852bU, 0xa929cee1U, 0x1774bb85U); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000016U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xac07fb5cU, 0x8465d091U, 0x76d3220dU, 0xeb9928aaU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000008U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000016U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xbe68f671U, 0xfadb396eU, 0x92ea74d6U, 0x5a89ffc3U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xcb50a92aU, 0x36fd00acU, 0x743152d8U, 0x1208459fU); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + HW_SCE_p_func100(0xaf97e5dfU, 0x546d8bbdU, 0xa276df74U, 0xf317b6e1U); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1608H, 0x80080000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x9466cd2fU, 0xf0bdc933U, 0x7ede7f81U, 0x07f9c658U); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xe9d22f08U, 0xb2f124bdU, 0x036aced6U, 0xf450d21cU); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d47U); + WR1_PROG(REG_1608H, 0x81080000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, change_endian_long(0x00000000U), change_endian_long(0x00000000U), change_endian_long(0x00000000U), change_endian_long(0x00000002U)); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[9]); + + HW_SCE_p_func102(0x94f8f3ebU, 0xbc495b16U, 0x8df44231U, 0x0a567101U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p17.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p17.c new file mode 100644 index 000000000..e5868fde3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p17.c @@ -0,0 +1,179 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateAes256XtsRandomKeyIndexSub (uint32_t OutData_KeyIndex[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00170001U); + WR1_PROG(REG_144CH, 0x00000000U); + + HW_SCE_p_func100(0x5ee8216bU, 0xad10783eU, 0x0bcf53c4U, 0x0da3f597U); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000017U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x0fe02ae6U, 0xdf675f03U, 0xe378f613U, 0x8726c14eU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000009U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000017U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xc5b57de4U, 0x01f67fd8U, 0xee8bd72cU, 0x38e0c189U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x13d961d9U, 0x4c70b2afU, 0x9c95dc82U, 0xb20386f8U); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + HW_SCE_p_func100(0x47c9c46eU, 0x9a28c680U, 0x2d89e442U, 0x23012634U); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1608H, 0x80100000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x54203e19U, 0x9fc27cd7U, 0xed304328U, 0x81f72ec9U); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xa87e01aeU, 0x3912c44aU, 0x1517237fU, 0x6c5cffd5U); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x1a116a1cU, 0xb390208eU, 0xf73f5c68U, 0xf4f079dfU); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xa2b972bfU, 0x43428f4bU, 0x8a245a0aU, 0x7bf174d7U); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d47U); + WR1_PROG(REG_1608H, 0x810c0000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = 1U; iLoop < 13U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func100(0x56d8f435U, 0x55c3e76aU, 0xb1e8d466U, 0x0720c506U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d47U); + WR1_PROG(REG_1608H, 0x81040180U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[iLoop]); + + HW_SCE_p_func100(0x25a14e3aU, 0x1555b36fU, 0x76979b74U, 0xc7f16913U); + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, change_endian_long(0x00000000U), change_endian_long(0x00000000U), change_endian_long(0x00000000U), change_endian_long(0x00000004U)); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_KeyIndex[iLoop + 4]); + + HW_SCE_p_func102(0xc27a71cbU, 0x65147e4aU, 0xdbe834d2U, 0x2895b1eaU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p20.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p20.c new file mode 100644 index 000000000..a88b80f81 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p20.c @@ -0,0 +1,56 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateRandomNumberSub (uint32_t OutData_Text[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00200002U); + WR1_PROG(REG_144CH, 0x00000000U); + + HW_SCE_p_func100(0xe25318a3U, 0x229ebf87U, 0x708a27e0U, 0xbecefc17U); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x84a1c95cU, 0xa4971b99U, 0xa27dafd1U, 0x105e9526U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[0]); + + HW_SCE_p_func102(0x5195cd2cU, 0xfc7ff93bU, 0x5e36f409U, 0xc20cf9ecU); + + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p21.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p21.c new file mode 100644 index 000000000..b9d762340 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p21.c @@ -0,0 +1,84 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GhashSub (const uint32_t InData_HV[], + const uint32_t InData_IV[], + const uint32_t InData_Text[], + uint32_t OutData_DataT[], + const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00210001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x00070000U); + WR1_PROG(REG_1824H, 0x08008005U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_HV[0]); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000025U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a058006U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + HW_SCE_p_func100(0x12a89875U, 0x2f76a7d8U, 0xcb51754bU, 0x7cff2dccU); + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00400000U); + WR1_PROG(REG_1824H, 0x0c008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_DataT[0]); + + HW_SCE_p_func102(0xf56e0086U, 0x71517d6dU, 0x01c7a7d6U, 0xc1c2166cU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p26.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p26.c new file mode 100644 index 000000000..94480c711 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p26.c @@ -0,0 +1,163 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_IntegrityCheckSub(const uint32_t InData_Data[], + const uint32_t InData_DataLen[], + const uint32_t InData_MAC[], + const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00260001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_2004H, 0x00000050U); + + WR1_PROG(REG_2008H, 0x00000013U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01522594U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000026U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x85aa7c53U, 0x6a60994eU, 0xc863ce5aU, 0x7e94b22eU); + HW_SCE_p_func082(); + + if ((InData_DataLen[0] == 0) && (InData_DataLen[1] == 0)) + { + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000080U); + + WR1_PROG(REG_200CH, 0x00000001U); + + WAIT_STS(REG_2030H, 8, 0); + + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000000U); + + WR1_PROG(REG_200CH, 0x00000100U); + + HW_SCE_p_func101(0xd65948e6U, 0x872fd9d3U, 0x078314b5U, 0x0b50f513U); + } + else + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, InData_DataLen[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, InData_DataLen[1]); + + WR1_PROG(REG_200CH, 0x00000001U); + + HW_SCE_p_func101(0x0c365d2aU, 0x60a4403fU, 0x3d6f75faU, 0x2ce996c1U); + } + + WAIT_STS(REG_2030H, 0, 1); + + WR1_PROG(REG_1444H, 0x00020064U); + + for (iLoop = 0U; iLoop < (MAX_CNT & 0xfffffff0U);) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Data[iLoop]); + WR4_ADDR(REG_1420H, &InData_Data[iLoop+4]); + WR4_ADDR(REG_1420H, &InData_Data[iLoop+8]); + WR4_ADDR(REG_1420H, &InData_Data[iLoop+12]); + + iLoop = iLoop + 16U; + } + + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = (MAX_CNT & 0xfffffff0U); iLoop < MAX_CNT; iLoop++) + { + WR1_PROG(REG_1420H, InData_Data[iLoop]); + } + + WR1_PROG(REG_1444H, 0x00000000U); + + WAIT_STS(REG_2030H, 8, 0); + WR1_PROG(REG_143CH, 0x00001600U); + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1A24H, 0x08000045U); + WR1_PROG(REG_1400H, 0x00850011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A24H, 0x9c000005U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MAC[0]); + + WR1_PROG(REG_1A24H, 0x08000055U); + WR1_PROG(REG_1400H, 0x00850011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A24H, 0x9c100005U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MAC[4]); + + HW_SCE_p_func100(0x8ccb1c59U, 0x090c8c4fU, 0xb730060bU, 0xb825c7bfU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xb212867cU, 0x7f962a54U, 0xb4550c73U, 0x57d07809U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0x355c0de4U, 0x47c65d12U, 0x4525524fU, 0x7e29e30fU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29a.c new file mode 100644 index 000000000..82d0b8956 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29a.c @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128GcmEncryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008006U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + HW_SCE_p_func101(0x8c330d5aU, 0xe64c6559U, 0xa52c2eaeU, 0x315c7074U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29f.c new file mode 100644 index 000000000..036d6f1ba --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29f.c @@ -0,0 +1,223 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128GcmEncryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataALen[], + uint32_t OutData_Text[], + uint32_t OutData_DataT[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1600H, 0x000035c8U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020100U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a9c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xad277f39U, 0xee75a3c4U, 0x438be929U, 0x103dbc2dU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x0000b580U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007FU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0xFFFFFF00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0c0029a9U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x04a02988U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func101(0xa7db2f45U, 0x9c71c6c3U, 0x8e7a5731U, 0xc92470e6U); + } + else + { + WR1_PROG(REG_1600H, 0x0000b580U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00020800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0c0029a9U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x04a02988U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func101(0x555e30aaU, 0xf0f30a1cU, 0x1a3fee52U, 0x927f7ed5U); + } + + HW_SCE_p_func100(0xd247e180U, 0xdee58485U, 0x9945e194U, 0x9c17530eU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x72ca3a04U, 0x8db4e592U, 0xb6fb3ab7U, 0xddc98eafU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003409U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00036800U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x08008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x761b70e2U, 0x93900df9U, 0xbf6f72a1U, 0x6e29caeeU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func100(0x74955fa3U, 0x8fc47408U, 0x9a13d864U, 0xb720a83fU); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + HW_SCE_p_func101(0x9d9f770bU, 0xf0377511U, 0xd19fa172U, 0xc7b1911dU); + } + + HW_SCE_p_func100(0x04acc937U, 0x8cd0ae82U, 0x96b15db3U, 0xda02d9dbU); + WR1_PROG(REG_1444H, 0x000001c1U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + WAIT_STS(REG_1444H, 31, 1); + WR2_ADDR(REG_1420H, &InData_DataALen[0]); + + WR1_PROG(REG_1608H, 0x81020100U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_182CH, 0x00400000U); + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_DataT[0]); + + HW_SCE_p_func102(0x504a897dU, 0x82f6aca7U, 0x18d5e8dbU, 0xafdcaaaaU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29i.c new file mode 100644 index 000000000..10ae6c844 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29i.c @@ -0,0 +1,512 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128GcmEncryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_SeqNum[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00290001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010100U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008900U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x52b4989aU, 0xc1ef8024U, 0x7285bb36U, 0xc4b20851U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x2999e95cU, 0xbdd6030fU, 0xdde611b6U, 0xc81cce1dU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x38000d08U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008900U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x89178998U, 0x57459db1U, 0x960c89a6U, 0xfbeaaa7bU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000d08U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x332b90b9U, 0x29d75eb5U, 0x4c515a6eU, 0xa6707267U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000029U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xb5658baeU, 0xae36560dU, 0x3d086b9eU, 0x07197643U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xdd8019e5U, 0x99502274U, 0x40956e2cU, 0xf585e05bU); + } + else + { + WR1_PROG(REG_1600H, 0x00003547U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000029U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xfc5f8ed3U, 0x3a016dfcU, 0x7bb50746U, 0xc4d62c53U); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2a46c04bU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xe0764891U, 0xe54d722bU, 0xfb88e91aU, 0x9366254cU); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000029U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x41de7c4bU, 0xf2f82ba5U, 0x38aa8e35U, 0x0d47a12cU); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xe624a352U, 0x83586522U, 0xf41e0ce3U, 0x3dfd9f94U); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[1]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[2]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xc2696419U, 0xc638c638U, 0x75e99917U, 0x533d2540U); + } + else + { + WR1_PROG(REG_1600H, 0x38008900U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x2725413fU, 0xe3d7c947U, 0x26d4d665U, 0x938463e7U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[1]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[2]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ff0000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00120000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3c0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3800d80fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000d3c1U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000feU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3c2U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008bc0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00003540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003561U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003582U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000035a3U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000029U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x5dec78cbU, 0x373900b7U, 0x38d8a9c0U, 0xa1212a38U); + HW_SCE_p_func059(); + + HW_SCE_p_func100(0x8871df3aU, 0x5954f2ecU, 0xc48b2cadU, 0xf9d22a20U); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[4]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[8]); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[12]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + HW_SCE_p_func101(0x6416762eU, 0x5336ee43U, 0x1760f87cU, 0xbd80b2d3U); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c21U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x0fdd919dU, 0xd4e3360bU, 0x712f21e2U, 0x10b56e5dU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000036a0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b6c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x4cc18a1aU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000029U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x4e2a649cU, 0x68f794f0U, 0x58744ffeU, 0x4f036123U); + HW_SCE_p_func092(); + + HW_SCE_p_func101(0x59729d8aU, 0x10b21704U, 0x3d243346U, 0x454766afU); + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000edU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x85eb4644U, 0xc01983e2U, 0x491d1737U, 0xe71ca4a6U); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x6ad6575eU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000edU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x18b4070eU, 0xb8d45aefU, 0x8827a44aU, 0xafb7d939U); + HW_SCE_p_func044(); + + HW_SCE_p_func101(0xbfe2bf29U, 0xc0906037U, 0x9be3c863U, 0xac6feae7U); + } + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020360U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_SeqNum[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_SeqNum[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x993e70b0U, 0xbeabd698U, 0xfec3691eU, 0x9656faebU); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0x77ab0c42U, 0xbb1e2195U, 0x12627fe3U, 0xfa15aeb4U); + } + + HW_SCE_p_func101(0xd53250cfU, 0xcb67142cU, 0x3e92ebb4U, 0x65067810U); + } + + HW_SCE_p_func100(0xb6574844U, 0x6a7967b7U, 0x7542a6e1U, 0xf57c1473U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xaf3f6031U, 0x94383906U, 0xea11e5e3U, 0x55f3a4acU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x3000a900U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000008bbU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000008dcU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000024U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00070000U); + WR1_PROG(REG_1824H, 0x0a008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29t.c new file mode 100644 index 000000000..b1dc43e89 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29t.c @@ -0,0 +1,38 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128GcmEncryptUpdateTransitionSub (void) +{ + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x07008c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29u.c new file mode 100644 index 000000000..9c20bd9a0 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p29u.c @@ -0,0 +1,63 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128GcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x598bd788U, 0xe7f0afe8U, 0x93bf6e19U, 0x7d89d54fU); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x00020020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[0]); + + HW_SCE_p_func100(0x7dd76ba3U, 0x62079169U, 0x6d061fc4U, 0x5aecbaa0U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00028020U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func202(); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00028000U); + WR1_PROG(REG_1824H, 0x08008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func101(0x957d163fU, 0xc80bbcacU, 0x34087b11U, 0x49e6a8f0U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32a.c new file mode 100644 index 000000000..3523456d9 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32a.c @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128GcmDecryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008006U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + HW_SCE_p_func101(0x4919b699U, 0xd3927209U, 0xa6776717U, 0xe7e35c59U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32f.c new file mode 100644 index 000000000..7d33ac357 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32f.c @@ -0,0 +1,285 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128GcmDecryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataALen[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1600H, 0x000035c8U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020100U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a9c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xaf6c3e31U, 0x5b24d3fcU, 0x93ac0889U, 0xa08f49caU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x0000b580U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007FU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0xFFFFFF00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0c0029a9U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x04a02988U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func101(0xd902171eU, 0x3e855f92U, 0x2465bbf8U, 0x7a5365bcU); + } + else + { + WR1_PROG(REG_1600H, 0x0000b580U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00020800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0c0029a9U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x04a02988U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func101(0x3106ed66U, 0xed26f40dU, 0x1414ae9eU, 0xf8377afeU); + } + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataTLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x34202beaU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x937934e3U, 0x84e3f7dbU, 0xadcbaeffU, 0xd10904e9U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xee7e7258U, 0xebc5abd6U, 0x0f8ed4bcU, 0x7cc4c1ddU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003409U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00036800U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x08008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x4e98c9a3U, 0xab8abbb7U, 0x63bb7539U, 0xd5a5c028U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func100(0xaf38a7b1U, 0x946d3db0U, 0x44900169U, 0xa9622074U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x00018020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + HW_SCE_p_func101(0x4e312142U, 0x45cb420dU, 0x8c4a2e7fU, 0x93ecc6f0U); + } + + WR1_PROG(REG_1444H, 0x000001c1U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + WAIT_STS(REG_1444H, 31, 1); + WR2_ADDR(REG_1420H, &InData_DataALen[0]); + + WR1_PROG(REG_1608H, 0x81020100U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_182CH, 0x00400000U); + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002beaU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000055U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataT[0]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1824H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x870956afU, 0x6afb2376U, 0x5daf9d0fU, 0x63ff55ddU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x4f0f195eU, 0x745851f1U, 0x74ef11dbU, 0xaa04efbbU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_p_func102(0x9ce2b9e2U, 0x13607232U, 0x5395c259U, 0x5531055cU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32i.c new file mode 100644 index 000000000..949ea0dfe --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32i.c @@ -0,0 +1,544 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128GcmDecryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_SeqNum[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00320001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010100U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000d08U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008900U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x49f6ff8bU, 0x0adcae23U, 0x49e5e3c1U, 0x6d8e46ecU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000d08U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xf25e1e0cU, 0xabb41ad9U, 0x405f211aU, 0xbb02ed33U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000032U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xba8fd14dU, 0x5b120508U, 0x5a8e85dcU, 0x000663dfU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x71ace550U, 0x4ad891b5U, 0x4163901aU, 0x77dba43bU); + } + else + { + WR1_PROG(REG_1600H, 0x00003547U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000032U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xa51097e9U, 0x6bae328aU, 0xf45d597bU, 0x02fbeebaU); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2a46c04bU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xeb91cdc8U, 0xa5979a89U, 0xb94700e7U, 0xf8571fb1U); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000032U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xbbafaa86U, 0x4c11a922U, 0xc4662789U, 0xffd88408U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[1]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[2]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xd12b3962U, 0x652b62cfU, 0x3cd43046U, 0x3d45473fU); + } + else + { + WR1_PROG(REG_1600H, 0x38008900U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x66907df2U, 0xd1495a7eU, 0xf73a72f7U, 0xa47aa2bbU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[1]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[2]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ff0000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00120000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3c0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3800d80eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000d3c1U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000feU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3c2U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008bc0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00003540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003561U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003582U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000035a3U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000032U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xc6bb82b1U, 0x768a0b36U, 0x7610009fU, 0xa617a970U); + HW_SCE_p_func059(); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[4]); + + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[8]); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[12]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0x358c44b7U, 0x7eedb999U, 0xe7cd5692U, 0x14c3d26eU); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3800a900U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xa44a1575U, 0xf6693530U, 0x1c27fc91U, 0x2b9458f2U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000005U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x38b824a8U, 0xba1c1d45U, 0x7ca2d014U, 0xf0ce626cU); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01ad8717U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000005U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x306d9c10U, 0x2f8ec0deU, 0xc585fda1U, 0x08fdc8e9U); + HW_SCE_p_func044(); + + HW_SCE_p_func101(0xfef2fa45U, 0xe3a336c9U, 0x05d1cbc4U, 0x0355792cU); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c21U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xbe0d2557U, 0xbdc95bafU, 0x6b93363dU, 0x088366a7U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000036a0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b6c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x8026ee7fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000032U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xb3554679U, 0x5d800038U, 0x2b19771bU, 0xd6290d1bU); + HW_SCE_p_func092(); + + HW_SCE_p_func101(0xe64610d6U, 0x9ea43e7dU, 0xf24a953dU, 0x64955343U); + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000ecU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xb1b242e2U, 0xdff95090U, 0x7cc9b514U, 0x0feb33a1U); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x98bae316U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000ecU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x84cfcaacU, 0x0141415eU, 0x4c534a21U, 0xb8eda236U); + HW_SCE_p_func044(); + + HW_SCE_p_func101(0x3a665ea0U, 0x51e41fe3U, 0x2efbf14eU, 0xb8b1fea1U); + } + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020360U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_SeqNum[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_SeqNum[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xbf92fd39U, 0xf3cdabd7U, 0xcf4acd48U, 0xf5ec2a14U); + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0x2c3aa771U, 0x4535a9c7U, 0x593e8a83U, 0x637c5afbU); + } + + HW_SCE_p_func101(0x08ce720dU, 0xdaa6cb16U, 0x097d89dbU, 0x714922efU); + } + + HW_SCE_p_func100(0x5c9e1f22U, 0x6815b48eU, 0xb3327a3dU, 0x3274ea6eU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xc81a7d36U, 0x4dd6c85aU, 0x949435c2U, 0x3f174c4fU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x246535fbU, 0x0d2016c9U, 0xcffad8d6U, 0x671db5fdU); + WR1_PROG(REG_1600H, 0x3000a900U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000008bbU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000008dcU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81040000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000024U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00070000U); + WR1_PROG(REG_1824H, 0x0a008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32t.c new file mode 100644 index 000000000..33afe3d23 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32t.c @@ -0,0 +1,38 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128GcmDecryptUpdateTransitionSub (void) +{ + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x07008c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32u.c new file mode 100644 index 000000000..774fea513 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p32u.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128GcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0xa4a57ffbU, 0x255e5ab8U, 0x8cdd131eU, 0xd202720dU); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018020U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + + HW_SCE_p_func202(); + + HW_SCE_p_func101(0x05fa92b2U, 0xcd538548U, 0x0f21e78cU, 0xf9b8322eU); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34a.c new file mode 100644 index 000000000..3b4b483f5 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34a.c @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256GcmEncryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008006U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + HW_SCE_p_func101(0x6ab8ececU, 0x382c8b3bU, 0x0a7cfa38U, 0x3b716fb3U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34f.c new file mode 100644 index 000000000..7535271f4 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34f.c @@ -0,0 +1,186 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256GcmEncryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataALen[], + uint32_t OutData_Text[], + uint32_t OutData_DataT[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020100U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b580U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007FU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0xFFFFFF00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0c0029a9U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x04a02988U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xe2ea70cdU, 0xd776bfa8U, 0xbf38a30dU, 0x1ed70bedU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xf4680a67U, 0xc36b9da9U, 0x7383107dU, 0x56dd6695U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003409U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00036800U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x08008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x6c9780daU, 0x34924041U, 0x29528d6cU, 0xd2f3cb67U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func100(0x7b48b4aaU, 0x287007a1U, 0xb10f8d46U, 0xfec66f3fU); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + HW_SCE_p_func101(0x9cd0929bU, 0xf1ce93a2U, 0xca822daaU, 0xb401cae1U); + } + + HW_SCE_p_func100(0xce083d57U, 0xa6b1c2b7U, 0x9e7ea576U, 0x42e5bda0U); + WR1_PROG(REG_1444H, 0x000001c1U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + WAIT_STS(REG_1444H, 31, 1); + WR2_ADDR(REG_1420H, &InData_DataALen[0]); + + WR1_PROG(REG_1608H, 0x81020100U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00400000U); + WR1_PROG(REG_1824H, 0x0c008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_DataT[0]); + + HW_SCE_p_func102(0x22f22c82U, 0x70cac744U, 0x31e5a7b5U, 0xe1e68f41U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34i.c new file mode 100644 index 000000000..043dda92e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34i.c @@ -0,0 +1,221 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256GcmEncryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00340001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x3f782a5cU, 0x04ab7dadU, 0xe5e67bc7U, 0xb1d95df1U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x65e6c314U, 0x565014afU, 0x66b22cc2U, 0x232bbf61U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x2e39b78cU, 0xddbe75e9U, 0x0fa5377dU, 0x38d09a55U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000034U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x8214e228U, 0x5b4dce41U, 0x01b2cbdcU, 0x1cae8082U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x3741a694U, 0x0b898a68U, 0x7aca8efdU, 0x6432e633U); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000034U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xab84e5efU, 0xf940c9d9U, 0xbd0707eaU, 0xba9e8836U); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x85d04999U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x3748c1a2U, 0xb55d89abU, 0x50576b76U, 0x120c31efU); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000034U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x857cea2fU, 0x2006f9c9U, 0x580cd15dU, 0x2291ee99U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xc56b3e5eU, 0x295705c0U, 0x8695b0b7U, 0xa7dcea4aU); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x44635c20U, 0xd3131bddU, 0xc645a6a7U, 0x74b0620fU); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x33bb35c0U, 0xe037e4bdU, 0xf1c7ab52U, 0x4d7cc46fU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xc46d2126U, 0x77eef4f7U, 0x5154c06aU, 0x5de447a9U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[1]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[2]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000024U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40070000U); + WR1_PROG(REG_1824H, 0x0a008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34t.c new file mode 100644 index 000000000..1c253f5d3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34t.c @@ -0,0 +1,38 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256GcmEncryptUpdateTransitionSub (void) +{ + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x07008c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34u.c new file mode 100644 index 000000000..a7e0cf436 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p34u.c @@ -0,0 +1,64 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256GcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x704127dbU, 0x3aff0a5eU, 0xb5430fdaU, 0x3dd67f14U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40020020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[0]); + + HW_SCE_p_func100(0xbbdc6e22U, 0xa8d25a59U, 0xdc93d46cU, 0xc3e7b01cU); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40028020U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func202(); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00028000U); + WR1_PROG(REG_1824H, 0x08008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func101(0xe21f4c4dU, 0x26bf1a2dU, 0x25b14e38U, 0x54be453bU); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36a.c new file mode 100644 index 000000000..feaa2b6e2 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36a.c @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256GcmDecryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008006U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + HW_SCE_p_func101(0x54abd53fU, 0xc6d3e9feU, 0xb169d890U, 0xd5a8cf48U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36f.c new file mode 100644 index 000000000..5691d4988 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36f.c @@ -0,0 +1,250 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256GcmDecryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataALen[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020100U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b580U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007FU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0xFFFFFF00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0c0029a9U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x04a02988U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataTLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x34202beaU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x91eb0248U, 0x7b3cb5f1U, 0xec525139U, 0x949bd158U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x63fc7854U, 0x6e11ff5dU, 0x056c3c91U, 0x3a5060b1U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003409U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00036800U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x08008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x0d028c06U, 0x485b3b78U, 0x22517aafU, 0x918f55bdU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func100(0xb52a1421U, 0xfe17f96fU, 0x57f99900U, 0x6c46c4f1U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40018020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + HW_SCE_p_func101(0x0c2b62f9U, 0x20d0c90bU, 0x1e04b0c8U, 0xbd8a4125U); + } + else + { + } + + WR1_PROG(REG_1444H, 0x000001c1U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + WAIT_STS(REG_1444H, 31, 1); + WR2_ADDR(REG_1420H, &InData_DataALen[0]); + + WR1_PROG(REG_1608H, 0x81020100U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_182CH, 0x00400000U); + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x07008d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002beaU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000055U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataT[0]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1824H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x11e900d9U, 0x22859cc5U, 0x74b435f8U, 0x490d783eU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xf5b40977U, 0xddb7df38U, 0x0370d101U, 0x21c6b35aU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_p_func102(0x66750055U, 0xe3ae3578U, 0xaf10aee6U, 0xad2bbd2dU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36i.c new file mode 100644 index 000000000..e7b6a41d3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36i.c @@ -0,0 +1,229 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256GcmDecryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00360001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x45d2d811U, 0x8598303dU, 0xe6dba618U, 0x9aad82a2U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x79262bc8U, 0x5cd4e87cU, 0x3001b44cU, 0xc5ddbf12U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x43aa03eaU, 0x4f89645cU, 0x21cf5cfeU, 0xb1ded202U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000036U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x2dd76243U, 0x64ec75c7U, 0x66b00189U, 0xc33a4563U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xd84cc869U, 0x9393f9d9U, 0x3d74bf83U, 0x3daafaf2U); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000036U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x94494e9eU, 0x266170b4U, 0x4168071bU, 0x64e90283U); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x85d04999U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xda6e1f9fU, 0x24522a42U, 0xe546ef0cU, 0x08fdcee1U); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000036U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x7af2a93eU, 0x7e07ac9eU, 0xa132f81cU, 0x4ea28e81U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1608H, 0x80080000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xb89396b2U, 0xd634dc1dU, 0xb3a40ec7U, 0xfe24cbabU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x7f7c1ce5U, 0xf01c4bcaU, 0xb8853259U, 0xccd90609U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x99d6a151U, 0xad099ad7U, 0x5e7ac24cU, 0xba292ff3U); + WR1_PROG(REG_1608H, 0x81080000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x54166397U, 0x7316b54cU, 0x6f1209b6U, 0xd1437d6aU); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[1]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[2]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000024U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40070000U); + WR1_PROG(REG_1824H, 0x0a008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36t.c new file mode 100644 index 000000000..3b87120f1 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36t.c @@ -0,0 +1,38 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256GcmDecryptUpdateTransitionSub (void) +{ + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x07008c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36u.c new file mode 100644 index 000000000..406dc5cb4 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p36u.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256GcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x6ab2f6f4U, 0x3a1a914cU, 0xcb2f64baU, 0xfe313a40U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40018020U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + + HW_SCE_p_func202(); + + HW_SCE_p_func101(0x70e0ceacU, 0x3af902f1U, 0x1d564123U, 0x7cc88e3eU); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p40.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p40.c new file mode 100644 index 000000000..e4212203f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p40.c @@ -0,0 +1,285 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_LoadHukSub (const uint32_t InData_LC[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00400001U); + WR1_PROG(REG_144CH, 0x00000000U); + + HW_SCE_p_func048(InData_LC); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000aU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10003401U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10003401U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10003401U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x34202801U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x20003401U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (InData_LC[0] == 0x00000000U) + { + WR1_PROG(REG_143CH, 0x00b80000U); + + HW_SCE_p_func101(0xd79669fbU, 0x9d346923U, 0x3a14355fU, 0x358484d1U); + } + else if (InData_LC[0] == 0x00000001U) + { + WR1_PROG(REG_143CH, 0x00b00000U); + + HW_SCE_p_func101(0xf20d07e1U, 0xec188734U, 0x209ee85dU, 0xbb5e2fc1U); + } + else if (InData_LC[0] == 0x00000004U) + { + WR1_PROG(REG_143CH, 0x00b30000U); + + HW_SCE_p_func101(0x97eebde0U, 0x8d60c103U, 0x9347fdb4U, 0xe03c0d68U); + } + else if (InData_LC[0] == 0x00000006U) + { + WR1_PROG(REG_143CH, 0x00b50000U); + + HW_SCE_p_func101(0xd4cebd6bU, 0x8f82c577U, 0x5086ee81U, 0x87898155U); + } + else if (InData_LC[0] == 0x00000007U) + { + WR1_PROG(REG_143CH, 0x00b60000U); + + HW_SCE_p_func101(0x3ecf5357U, 0x09080fb2U, 0x13b715a0U, 0x18249bdcU); + } + else if (InData_LC[0] == 0x00000008U) + { + WR1_PROG(REG_143CH, 0x00b70000U); + + HW_SCE_p_func101(0xa9faa165U, 0xcb8f5381U, 0xd75fb2a1U, 0x13b1e47cU); + } + else if (InData_LC[0] == 0x00000009U) + { + WR1_PROG(REG_143CH, 0x00b90000U); + + HW_SCE_p_func101(0x05540a4eU, 0x1d8683ebU, 0xdc87d36dU, 0x6320823aU); + } + else + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func101(0xe886da82U, 0xa450ca98U, 0xd30e97e4U, 0xfe7111bdU); + } + + HW_SCE_p_func100(0x641e93fcU, 0x3ed85bd2U, 0x9363798aU, 0x421abaecU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xf3dcebe3U, 0xc3489b64U, 0x7ba32bc8U, 0xb4539034U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A24H, 0x0a0700f5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, change_endian_long(0x05818b2aU), change_endian_long(0x0adf0d83U), change_endian_long(0x0c37adbdU), change_endian_long(0xaaae696bU)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1A24H, 0x30471084U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x01ea725dU)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x30471094U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x02ea725dU)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A24H, 0x0a0700f5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, change_endian_long(0x1d571b38U), change_endian_long(0x1dee8c72U), change_endian_long(0xced283ddU), change_endian_long(0x6ec23923U)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + HW_SCE_p_func100(0x17eec9f9U, 0xb5b49c21U, 0xcb562a8aU, 0x262105cdU); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WR1_PROG(REG_1438H, 0x20000000U); + WR1_PROG(REG_1400H, 0x00880011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WR1_PROG(REG_1438H, 0x20000010U); + WR1_PROG(REG_1400H, 0x00880011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x3b3d0dc9U, 0x06a05f96U, 0x9a2e898aU, 0x9cc211d5U); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000001b0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003c01U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WR1_PROG(REG_1438H, 0x20000020U); + WR1_PROG(REG_1400H, 0x00880011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1A24H, 0x8c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000002a1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x4a008044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x018beba7U)); + + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x028beba7U)); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000001d0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80880001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x92d5f40cU, 0xfd9f676aU, 0x1ae780c8U, 0xa24b4c0fU); + WR1_PROG(REG_1A24H, 0x4a470044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e4704c4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0152db38U)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1A24H, 0x4a040044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A24H, 0x0e040504U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x01f7370eU)); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000001c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1B08H, 0x00000202U); + + HW_SCE_p_func102(0x9fdddef9U, 0x2400849cU, 0x1e2b4c8aU, 0xc2382107U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41f.c new file mode 100644 index 000000000..035d99c9c --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41f.c @@ -0,0 +1,230 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128CmacFinalSub (const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]) +{ + uint32_t iLoop = 0U; + + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000002U)) + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x4a000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func101(0x014ca09cU, 0x0a309a4dU, 0x4b036787U, 0x560503d6U); + } + else + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x5a000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func101(0x6242d217U, 0x1bb7c1b3U, 0xe2e59f40U, 0xa15b050fU); + } + + WR1_PROG(REG_1824H, 0x0c000045U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000001U)) + { + HW_SCE_p_func100(0x8245ae0dU, 0x815caaebU, 0x019eea8aU, 0x526a9f8eU); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x0e000505U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_DataT[0]); + + HW_SCE_p_func102(0x8951549aU, 0xce520176U, 0x1cf60ba6U, 0x1453367cU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010040U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataTLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a840U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x34202862U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xcce2937cU, 0x3b04fc4dU, 0x0cbf409bU, 0xaa7bbd9bU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x8b1e1ec6U, 0x9117aaf9U, 0x0c0a673dU, 0x03ecd8ffU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x0e000505U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e2U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000568e7U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00026ce7U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003827U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003402U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000028c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008cc0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00004406U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007421U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00007821U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003c27U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000034c2U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000a4c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000568c6U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000034e6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00026ce7U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 4U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3420a8e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10003c27U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x1000a4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x9c000005U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataT[0]); + + HW_SCE_p_func100(0xc3220594U, 0x34d5ae98U, 0x3c9400fcU, 0x1e6088d5U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x7758be04U, 0x8391d62cU, 0x06885f73U, 0xd1f36b60U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_p_func102(0xd3341aa1U, 0xd4fd8a50U, 0xa3136383U, 0xae07a322U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41i.c new file mode 100644 index 000000000..eff29c2ef --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41i.c @@ -0,0 +1,189 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128CmacInitSub (const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00410001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x38891bfaU, 0xbc2fec1cU, 0xd4ee315bU, 0x821d47f3U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x9f1dd112U, 0x46077a44U, 0x11557531U, 0xca3ee7efU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x975e4d6dU, 0x3111ed8aU, 0x635ccfdfU, 0x8977a63dU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000041U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x5893d64fU, 0x79be8eb5U, 0x23b3eb7eU, 0x80705c3eU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x8b83d6d9U, 0xdbe7b548U, 0x627127f1U, 0x69f8cf97U); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000041U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x308ac8bdU, 0xd5ce0f7dU, 0x3e0a9e2bU, 0xec36bd60U); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2a46c04bU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x0b2eb70cU, 0xb454acb3U, 0x9d60a63bU, 0xc708479aU); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000041U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x54a15d7aU, 0xf7480cb8U, 0x01cb7905U, 0x422294f4U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x65e1eb2fU, 0x1d6b32a8U, 0xc47954ffU, 0xd8806ee6U); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xe51d18ccU, 0x624923ebU, 0xcb571428U, 0x19393d96U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x665e536cU, 0xdc80d026U, 0x2fe09d44U, 0xee06a3bdU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41u.c new file mode 100644 index 000000000..5b145e2f5 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p41u.c @@ -0,0 +1,41 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128CmacUpdateSub (const uint32_t InData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0x0e000406U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + HW_SCE_p_func101(0x2c64c38aU, 0x55045820U, 0x06f0a23bU, 0xad839602U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44f.c new file mode 100644 index 000000000..f7741e08e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44f.c @@ -0,0 +1,234 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256CmacFinalSub (const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]) +{ + uint32_t iLoop = 0U; + + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000002U)) + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x4a008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func101(0xb3458adbU, 0xbdfbfd36U, 0xc687b67eU, 0x1cf6554aU); + } + else + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x5a008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func101(0x262f3244U, 0xd6aaa54dU, 0xc0aa5ffbU, 0xc352a9faU); + } + + WR1_PROG(REG_1824H, 0x0c000045U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000001U)) + { + HW_SCE_p_func100(0x3601f463U, 0xec9c354aU, 0x3709dcf1U, 0x4abb8a0fU); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e008505U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_DataT[0]); + + HW_SCE_p_func102(0x94bb0536U, 0x7ab7d942U, 0xf8d26060U, 0x01992d7fU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010040U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataTLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a840U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x34202862U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xea4d30aeU, 0x83aa7385U, 0x3aa85822U, 0xac773950U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xd8c3a568U, 0x1f3adc37U, 0x0f42d86cU, 0x1e20896cU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e008505U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e2U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000568e7U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00026ce7U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003827U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003402U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000028c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008cc0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00004406U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007421U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00007821U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003c27U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000034c2U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000a4c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000568c6U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000034e6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00026ce7U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 4U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3420a8e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10003c27U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x1000a4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x9c000005U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataT[0]); + + HW_SCE_p_func100(0xfa93240bU, 0x14ad8332U, 0xf1b374ebU, 0x71fc6c42U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x6a502d73U, 0x601e6f62U, 0xe7365b07U, 0xaabd2595U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_p_func102(0xc73db6d5U, 0x52998f78U, 0xc5bc2d1cU, 0x9b206637U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44i.c new file mode 100644 index 000000000..c211128a5 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44i.c @@ -0,0 +1,197 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256CmacInitSub (const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00440001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x40390a51U, 0x8301c5daU, 0xeca95638U, 0x2f564c0eU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x4c080ce8U, 0x9b5e7dd1U, 0xaad95886U, 0xb7d85e47U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x8bb01a6aU, 0x9b74d58fU, 0x55796ef6U, 0x6c39962aU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000044U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x17663d7aU, 0x8df82601U, 0x974566e6U, 0xad90788eU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x4f2e2dfaU, 0x32f08966U, 0xe526acfeU, 0x03674436U); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000044U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xb7a83047U, 0xac12a7fbU, 0x3e7d6d4fU, 0x89266ca6U); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x85d04999U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x7265045bU, 0x80e60f19U, 0x31c093f6U, 0x9b8c8ccdU); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000044U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xaa734a04U, 0x760368a6U, 0xfed6749aU, 0xe480c33bU); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x523adc4bU, 0x12688b0bU, 0x7cf0a7e5U, 0xf4fa6f5bU); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xaa6a7975U, 0x462b90f1U, 0x37230ce9U, 0x97b3bb49U); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x80b5cbb1U, 0xd86422acU, 0x3de151a7U, 0x24f51e0bU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xc814a01cU, 0x95fb0a16U, 0x649dbc6dU, 0xda3dd2baU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44u.c new file mode 100644 index 000000000..ae5fbb6ee --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p44u.c @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256CmacUpdateSub (const uint32_t InData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e008406U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + HW_SCE_p_func101(0x9d1cd063U, 0x46774709U, 0x997bf5b8U, 0x6b86f641U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47f.c new file mode 100644 index 000000000..1ff070773 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47f.c @@ -0,0 +1,56 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub (void) +{ + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func101(0x21dc6aa3U, 0x017e4d31U, 0x46bbcfb7U, 0xe0f6e464U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func101(0xa54452d6U, 0x60a6e71fU, 0xbe6efe10U, 0x7d733132U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + HW_SCE_p_func101(0x1cd30caeU, 0xf5872021U, 0x2340e41eU, 0xc5f390f0U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + HW_SCE_p_func101(0x9fdae256U, 0x46508d25U, 0x45091d6bU, 0x117e4230U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + HW_SCE_p_func101(0x443d2831U, 0x4c64d2a9U, 0x554c54d4U, 0xe68f937fU); + } + else + { + ; + } + + HW_SCE_p_func102(0xb611ddefU, 0xee31bfa6U, 0xee97e815U, 0xd5a7c6a1U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47i.c new file mode 100644 index 000000000..ad70b70b6 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47i.c @@ -0,0 +1,389 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00470001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1608H, 0x80020000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1444H, 0x000001c7U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008820U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x291677a4U, 0x2117f7c8U, 0xf22770e0U, 0xdb8e1daaU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x09da2a79U, 0x9f17681bU, 0xf73a99c1U, 0x2d83f9cbU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x3000a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xb70cdcb3U, 0x17dde89dU, 0xcd478f44U, 0xbd8f5820U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x38000c21U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xf18fec27U, 0xc7675c4aU, 0xa8d3fd15U, 0x66beae1fU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000047U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x5235462dU, 0xa0b9f181U, 0x8be19848U, 0x0d1b803aU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xd0c60563U, 0xe8311128U, 0x3892416fU, 0x4d65b0bfU); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000047U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x92830939U, 0x53c9f211U, 0xf4ee58a1U, 0x32fba10aU); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2a46c04bU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x7d0be759U, 0x0b5a42d7U, 0xe0ca4611U, 0xbf9c5bd9U); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000047U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x4058c560U, 0x03149f44U, 0xb2ba741fU, 0x536df022U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x9469623dU, 0x35a17357U, 0xcd71faa8U, 0xf555a97bU); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0x47c90679U, 0xe181f9ffU, 0xab7c9e7cU, 0x6fe21993U); + } + else + { + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040040U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[1]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[2]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e2U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ff0000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3c0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000b540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000b540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000eU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3800584aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000d3c1U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e2U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000feU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3c2U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008bc0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x0000a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003542U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003563U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003584U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000035a5U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000047U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x0e900cb8U, 0x11c57a3eU, 0xc1c84c6fU, 0xe7a6a665U); + HW_SCE_p_func059(); + + HW_SCE_p_func100(0xfb58974dU, 0x7c1618eeU, 0x316fd381U, 0x972730bfU); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[4]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[8]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0x60bdba69U, 0x1018b900U, 0x626e6771U, 0x96f5e96aU); + } + + HW_SCE_p_func100(0x6e64546eU, 0x5d16aba8U, 0xec5a66ffU, 0x2f3497a6U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xa6bd4176U, 0x64efd6beU, 0xf5eb9386U, 0x15c6bf7bU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0xbf18d2b4U, 0xf10ed05dU, 0x8130e031U, 0xd62273c1U); + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func101(0xe0a8faabU, 0x1728276bU, 0x87dc748dU, 0x18e9f16aU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func101(0x9d79bc67U, 0x9c71b49aU, 0x73935154U, 0xe8972f5cU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + HW_SCE_p_func101(0x74ac8c62U, 0x6cf70e01U, 0x0e7c2be7U, 0x93c144bcU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + HW_SCE_p_func101(0x56893593U, 0x7acb301eU, 0xf5e295fdU, 0x07ce3eb9U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + HW_SCE_p_func101(0x841043f2U, 0xf0a2d1e1U, 0x8b39c9beU, 0x5cdb00d5U); + } + else + { + ; + } + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47u.c new file mode 100644 index 000000000..3b49e3e47 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p47u.c @@ -0,0 +1,127 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128EncryptDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], + const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + HW_SCE_p_func100(0xb0459582U, 0x8570d5e7U, 0x694e1965U, 0x8a8ee9a3U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0x0a000106U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + HW_SCE_p_func100(0x959b2113U, 0xa138783dU, 0xaf5a9beeU, 0x69cd5459U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0x0a00010eU); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + HW_SCE_p_func100(0x4a566684U, 0x41af7e85U, 0xd4967198U, 0x55baff73U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0x0e000506U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + HW_SCE_p_func100(0x02b36b33U, 0xcbc50b6bU, 0xa4dcff7fU, 0x60e64a0fU); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0x0900090eU); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + HW_SCE_p_func100(0x246969d4U, 0x27d11a33U, 0x47e89be3U, 0x9dd5a6b3U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0x07000d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else + { + ; + } + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func214(); + + HW_SCE_p_func101(0x01c06606U, 0x8f00ce3aU, 0x958f7c69U, 0xf2f6d685U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func214(); + + HW_SCE_p_func101(0x319a1775U, 0xa2d7f61bU, 0x30ef6c53U, 0xb5cb66dbU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + HW_SCE_p_func214(); + + HW_SCE_p_func101(0xd9360414U, 0xe932a8d5U, 0x71e383a0U, 0xd39bf838U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + HW_SCE_p_func214(); + + HW_SCE_p_func101(0x596adfc2U, 0x7fe38e33U, 0x436bb0cbU, 0xb4d8fe76U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + HW_SCE_p_func214(); + + HW_SCE_p_func101(0x8c7570f3U, 0x40d317ccU, 0x6e82fb51U, 0x91cf9b9fU); + } + else + { + ; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50f.c new file mode 100644 index 000000000..ed6890b9a --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50f.c @@ -0,0 +1,56 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub (void) +{ + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func101(0xe4ec614aU, 0xaac97f18U, 0x2ac4c921U, 0xb5b87360U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func101(0x9c0e15eeU, 0x891035a1U, 0xd6d1ed99U, 0x3602acc9U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + HW_SCE_p_func101(0x66392e50U, 0x3c40fec7U, 0x2f314b29U, 0x4c59ac7eU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + HW_SCE_p_func101(0xa91c3852U, 0x89b8df26U, 0x322b45eaU, 0xeaa6514dU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + HW_SCE_p_func101(0xfb4050a0U, 0xa2bd35ceU, 0x1090dc04U, 0x6d100b16U); + } + else + { + ; + } + + HW_SCE_p_func102(0x2689350fU, 0x6eafcef9U, 0x7c4ebbd6U, 0xe6183d3aU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50i.c new file mode 100644 index 000000000..587ffe48c --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50i.c @@ -0,0 +1,405 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00500001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1608H, 0x80020000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1444H, 0x000001c7U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008820U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x23db72d7U, 0x79b6984dU, 0x12cc5289U, 0xe404717dU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x866a228aU, 0xabbad488U, 0x5f3b142fU, 0xd97dc5e4U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x3000a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x67a55dffU, 0x03b185f6U, 0xb7377998U, 0xc418cbbfU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x38000c21U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xf6191896U, 0xcd40978dU, 0x9eb3ec88U, 0xe194991cU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000050U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x691eb393U, 0x7b50715bU, 0xe42ef0ecU, 0xa743ed22U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x45f53acdU, 0xc1680679U, 0x58e2377dU, 0xf324b3f9U); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000050U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x2b6564bbU, 0xe7c49cd2U, 0xf09065e5U, 0x5e436f2aU); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x85d04999U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x22e1dc8aU, 0xb2694425U, 0xa81fb838U, 0x691e9f80U); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000050U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x9bd3f0b2U, 0xceee41edU, 0xe2a34b4cU, 0x949de8a1U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x7f5580afU, 0x794bae21U, 0x059a5fb3U, 0x8b55f20bU); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xbf67d194U, 0x0696efe3U, 0xc1714eceU, 0x09082bc4U); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0xc021b602U, 0xc53b683cU, 0x1f349663U, 0xb5dc40b6U); + } + else + { + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040040U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[1]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[2]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e2U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ff0000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3c0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000b540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000b540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000eU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3800584aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000d3c1U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e2U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000feU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3c2U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008bc0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x0000a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003542U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003563U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003584U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000035a5U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000050U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x4c900dfcU, 0x75d8b7a1U, 0x330c9c7cU, 0x02533a3dU); + HW_SCE_p_func059(); + + HW_SCE_p_func100(0x189bb226U, 0x6271308aU, 0x58ef370bU, 0x05e2d4f6U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[4]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[8]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x18f78776U, 0xd7484567U, 0x12ccce43U, 0x162323ecU); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[12]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0x3a6c0578U, 0xe5fbe622U, 0x2b22f817U, 0x4d14f67cU); + } + + HW_SCE_p_func100(0x574fc4a0U, 0xaac286b8U, 0x7aeb2ef4U, 0x91abfd16U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x7865289dU, 0xdcf654c9U, 0x62e31c96U, 0xbe628241U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x78ac61b3U, 0x2dd80de7U, 0xfd93df39U, 0x51e86098U); + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func101(0x7ff132d6U, 0xc5015014U, 0xb7b0da80U, 0x4c7f5deeU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func101(0x3292bcf6U, 0x8b4c7ce8U, 0x3ab1c258U, 0x752e3672U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + HW_SCE_p_func101(0x7548ae11U, 0x0e24fba6U, 0xb36deb1cU, 0x3522c3e2U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + HW_SCE_p_func101(0x7f7eff23U, 0x03b59cecU, 0x6ad0653eU, 0xa118eeceU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + HW_SCE_p_func101(0xdc727fabU, 0xc0c57f88U, 0x61f5c69eU, 0xcbab7047U); + } + else + { + ; + } + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50u.c new file mode 100644 index 000000000..bb89ac2f6 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p50u.c @@ -0,0 +1,132 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256EncryptDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], + const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + HW_SCE_p_func100(0x9acee02dU, 0x08503b73U, 0xfd139ed3U, 0x05024045U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0a008106U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + HW_SCE_p_func100(0x75b1a20bU, 0x7ce002b1U, 0xffdfd808U, 0xe65cbfeeU); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0a00810eU); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + HW_SCE_p_func100(0x658ab3dcU, 0xea94142dU, 0xb8f3ef14U, 0x8b5e5761U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e008506U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + HW_SCE_p_func100(0x7ac16ba5U, 0xd29598bbU, 0xfe05567aU, 0xe6400bebU); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0900890eU); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + HW_SCE_p_func100(0x3e59c297U, 0x6df0b3b1U, 0x0cf8e94bU, 0x27c94c2dU); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else + { + ; + } + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func214(); + + HW_SCE_p_func101(0x407566e7U, 0x19a25946U, 0x15d37e05U, 0x081506b8U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func214(); + + HW_SCE_p_func101(0xab1c0648U, 0x79eba40dU, 0xca654264U, 0xf9234295U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + HW_SCE_p_func214(); + + HW_SCE_p_func101(0xbed343b1U, 0xde27515dU, 0x3afd2421U, 0x29769355U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + HW_SCE_p_func214(); + + HW_SCE_p_func101(0xbbcf2a77U, 0x57e19d51U, 0x097510b4U, 0xe0f31b32U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + HW_SCE_p_func214(); + + HW_SCE_p_func101(0x705c47ecU, 0xc3ba119bU, 0x4bf2ffafU, 0x20ff89a9U); + } + else + { + ; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p53.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p53.c new file mode 100644 index 000000000..ea8117c2d --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p53.c @@ -0,0 +1,326 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Rsa1024ModularExponentEncryptSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_Text[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00530001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000053U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xe3e942d3U, 0xfdc84f23U, 0xd8533811U, 0x094c869fU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000aU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000053U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xbbdc0f8eU, 0xc3eec6f6U, 0xcdcb4708U, 0x15a9bdc5U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000043c2U); + WR1_PROG(REG_1A2CH, 0x40000700U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1404H, 0x15b00000U); + for (iLoop = 0U; iLoop < 32U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[33]); + + WR1_PROG(REG_1404H, 0x12200000U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A2CH, 0x40000700U); + WR1_PROG(REG_1A24H, 0xf7008c07U); + + for (iLoop = 36U; iLoop < 68U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[69]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x90285408U, 0x74b38580U, 0xfd790b9aU, 0x3badb21cU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x893d1235U, 0x97050c7dU, 0x23a09b9bU, 0x8757524eU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x10100010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00001fc2U); + WR1_PROG(REG_1A2CH, 0x40000700U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x11a00000U); + for (iLoop = 0U; iLoop < 32U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800dbe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xc74b3b3eU, 0x37b7bcfaU, 0xd16f1709U, 0x8cc5359eU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x2d041d92U, 0xe9bf7ddeU, 0xf3ce33e9U, 0xc829989eU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xb6e1532fU, 0x74281da9U, 0x32b067dbU, 0x9a55c1feU); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000228U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x0110000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + HW_SCE_p_func100(0x80488d7fU, 0x107c3f18U, 0xdb178126U, 0xcf84bbd5U); + WR1_PROG(REG_1404H, 0x17b80000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[4]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[8]); + + HW_SCE_p_func100(0xc27abb57U, 0x98aeb703U, 0x7377c9deU, 0x4ac40081U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[12]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[16]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[20]); + + HW_SCE_p_func100(0x16aaa567U, 0x88632585U, 0x76a70e58U, 0xb31089e3U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[24]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[28]); + + HW_SCE_p_func102(0xe826fb2aU, 0xa65b814bU, 0x1970cbbdU, 0x5c578fa9U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p54.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p54.c new file mode 100644 index 000000000..c980b96b6 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p54.c @@ -0,0 +1,327 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Rsa1024ModularExponentDecryptSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_Text[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00540001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000054U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xd92fde0aU, 0x8abb58e2U, 0x5c96d67dU, 0x3103b584U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000bU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000054U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xdc875852U, 0x757b1272U, 0x4944683fU, 0x1e52d59aU); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00005fc2U); + WR1_PROG(REG_1A2CH, 0x40000700U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1404H, 0x15b00000U); + for (iLoop = 0U; iLoop < 32U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1A2CH, 0x40000700U); + WR1_PROG(REG_1A24H, 0xf7008d07U); + + WR1_PROG(REG_1404H, 0x13a80000U); + for (iLoop = 32U; iLoop < 64U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1A2CH, 0x40000700U); + WR1_PROG(REG_1A24H, 0xf7008c07U); + + for (iLoop = 64U; iLoop < 96U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[97]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xf295e74bU, 0x7fdd3f9cU, 0x65358493U, 0x0e41b5a1U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xe81484fbU, 0x43e58dafU, 0x714f2d7eU, 0xf9200d3eU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x10100010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00001fc2U); + WR1_PROG(REG_1A2CH, 0x40000700U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x11a00000U); + for (iLoop = 0U; iLoop < 32U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800dbe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1404H, 0x19c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0007dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x1010000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x1d182cbdU, 0x50b31359U, 0x1786beadU, 0x023b3635U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xf0f99243U, 0x50c646c6U, 0x4c4b9776U, 0xa0198169U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xf11587eaU, 0x54c3616fU, 0x9e145cbeU, 0x77924ea0U); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000428U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x10100000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + HW_SCE_p_func100(0x4c5be0faU, 0x8dc7b132U, 0xfcabe18eU, 0xb2b0017aU); + WR1_PROG(REG_1404H, 0x17b80000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[4]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[8]); + + HW_SCE_p_func100(0x3d4cdfb2U, 0x87d2ba98U, 0xcc5eea4cU, 0x45b3c5d1U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[12]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[16]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[20]); + + HW_SCE_p_func100(0xbd6d0fc4U, 0x952817afU, 0xcc63b752U, 0x0e3a14f6U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[24]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[28]); + + HW_SCE_p_func102(0x7299d035U, 0x70e9356dU, 0x463e4e5aU, 0x8231d29aU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p56.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p56.c new file mode 100644 index 000000000..6f49540fc --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p56.c @@ -0,0 +1,338 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Rsa2048ModularExponentEncryptSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_Text[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00560001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000056U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xaedbd233U, 0xb3967ea5U, 0x4b8882b2U, 0xd3e10d68U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000cU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000056U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x2fca5c49U, 0xc9132cafU, 0x1ec4e732U, 0xacafb0f5U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000083c2U); + WR1_PROG(REG_1A2CH, 0x40000f00U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1404H, 0x15300000U); + for (iLoop = 0U; iLoop < 64U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[65]); + + WR1_PROG(REG_1404H, 0x12200000U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A2CH, 0x40000f00U); + WR1_PROG(REG_1A24H, 0xf7008c07U); + + for (iLoop = 68U; iLoop < 132U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[133]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x9a0c7d6cU, 0x81b1aebbU, 0xbca9cf59U, 0xfdf6dcd0U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x14a304dcU, 0xc64dcbc2U, 0x3c2d6fc7U, 0x032a787bU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x20200010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00003fc2U); + WR1_PROG(REG_1A2CH, 0x40000f00U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x11200000U); + for (iLoop = 0U; iLoop < 64U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800dbe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xefd2ddefU, 0x05c53649U, 0x2212e8baU, 0x0cb1daabU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x4fa808d2U, 0x65af2913U, 0xff8fdff4U, 0x1d88826eU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xfbcaa96bU, 0x9678d6a7U, 0x8c19340dU, 0x2f9c58b8U); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000228U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x0120000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x17380000U); + + for (iLoop = 0U; iLoop < 64U; ) + { + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x34202be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000d3c0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c1eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x663332e7U, 0x6b54ef0cU, 0xc1e8ff49U, 0xd5c4d3a0U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000008U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x1a3d6677U, 0xb48d4a11U, 0x63487566U, 0x313adc80U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1600H, 0x38000be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x2b9be288U, 0x7db40899U, 0x2de745e1U, 0xf9fb1f32U); + WR1_PROG(REG_1408H, 0x00020000U); + + HW_SCE_p_func102(0x7ace1358U, 0x7080deb5U, 0xd07afc33U, 0x0cf5776bU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p57.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p57.c new file mode 100644 index 000000000..bcee0457e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p57.c @@ -0,0 +1,339 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Rsa2048ModularExponentDecryptSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_Text[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00570001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000057U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xf8a9b604U, 0xe954d71eU, 0xe375c680U, 0x9c2533e4U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000dU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000057U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xbdc1ea09U, 0xb947f061U, 0x25bd3901U, 0x644683f7U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x0000bfc2U); + WR1_PROG(REG_1A2CH, 0x40000f00U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1404H, 0x15300000U); + for (iLoop = 0U; iLoop < 64U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1A2CH, 0x40000f00U); + WR1_PROG(REG_1A24H, 0xf7008d07U); + + WR1_PROG(REG_1404H, 0x13280000U); + for (iLoop = 64U; iLoop < 128U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1A2CH, 0x40000f00U); + WR1_PROG(REG_1A24H, 0xf7008c07U); + + for (iLoop = 128U; iLoop < 192U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[193]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x946e7cbdU, 0x94d66cddU, 0xb0adc2f6U, 0xaaf65083U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xf987e890U, 0x8ff76f83U, 0x7c425a21U, 0xb4169e9aU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x20200010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00003fc2U); + WR1_PROG(REG_1A2CH, 0x40000f00U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x11200000U); + for (iLoop = 0U; iLoop < 64U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800dbe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1404H, 0x19400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c000fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x2020000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xce40f933U, 0x3b533deaU, 0x1543c66aU, 0xee80456fU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xf41fc7b0U, 0x4dfdc83fU, 0x00720b59U, 0xa91aafccU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xf21a3da8U, 0xddf1a9a9U, 0xc1633d9fU, 0x59716f88U); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000428U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x20200000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x17380000U); + + for (iLoop = 0U; iLoop < 64U; ) + { + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x34202be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000d3c0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c1eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x9e67b854U, 0xfff89d4bU, 0xe2c3decaU, 0xb5189859U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000008U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x8bf17266U, 0x14c0ee24U, 0x209ff2d3U, 0x15f24d5eU); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1600H, 0x38000be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x3bb85d03U, 0xa5a6d428U, 0x60b06801U, 0x7421e2fcU); + WR1_PROG(REG_1408H, 0x00020000U); + + HW_SCE_p_func102(0x05c4fa07U, 0x13ec4f39U, 0x31ca88f9U, 0x9624a306U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p6e.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p6e.c new file mode 100644 index 000000000..912ec10e4 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p6e.c @@ -0,0 +1,277 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateOemKeyIndexSub (const uint32_t InData_KeyType[], + const uint32_t InData_Cmd[], + const uint32_t InData_SharedKeyIndex[], + const uint32_t InData_SessionKey[], + const uint32_t InData_IV[], + const uint32_t InData_InstData[], + uint32_t OutData_KeyIndex[]) +{ + uint32_t OFS_ADR = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x006e0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000fffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x27a1a378U, 0xb1e702c6U, 0xc089e2ccU, 0x03beb809U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func049(InData_Cmd); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(InData_SharedKeyIndex[0])); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000094aU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e4U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3000a880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x3000a880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000027U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00040020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000ffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000b480U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000feU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000b480U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a820U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x405fbba3U, 0xaba657d1U, 0x76aa21f2U, 0x1be8d53dU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x4c1fe336U, 0xfa156845U, 0x4d6499e6U, 0xea194839U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x0000349fU); + WR1_PROG(REG_1458H, 0x00000000U); + + OFS_ADR = InData_SharedKeyIndex[0] << 3; + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000006eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x796e174dU, 0x653915feU, 0xcba6aae0U, 0x765a94f7U); + HW_SCE_p_func058(InData_SessionKey, OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x80010380U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000006eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x0665b394U, 0x90038d3eU, 0x72c89813U, 0x3bd5d9e7U); + HW_SCE_p_func057(InData_IV, InData_InstData, OutData_KeyIndex); + + HW_SCE_p_func100(0xfbc657a3U, 0xcb4f283fU, 0x447eb3e5U, 0x43e8473dU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x3dc32268U, 0xea40c066U, 0x38de8720U, 0xc6bf2474U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x117b1137U, 0xf873bbffU, 0x5bac2524U, 0x7588c157U); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + HW_SCE_p_func102(0x8ec70a83U, 0x18f8da3cU, 0x16aa90aeU, 0x99f49cddU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } + } + else + { + HW_SCE_p_func049(InData_Cmd); + + WR1_PROG(REG_1600H, 0x000037e4U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3000a880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x3000a880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000027U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00040020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000feU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000b480U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x4813131eU, 0x1d3ea963U, 0x98032a0bU, 0x796c6ee3U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xbe4b9607U, 0x66b0c433U, 0x427f559fU, 0x6cc9f722U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x0000349fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x80010380U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000006eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x85945877U, 0xe5a02e2fU, 0x399d78e7U, 0xd6de2658U); + HW_SCE_p_func093(InData_InstData, OutData_KeyIndex); + + HW_SCE_p_func100(0x0d2f063dU, 0x46218b25U, 0x5d0a343dU, 0xb387cb82U); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_KeyIndex[0]); + + HW_SCE_p_func102(0x81a1e749U, 0x1f4f87e5U, 0x33f337a0U, 0x7fd9a798U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p70.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p70.c new file mode 100644 index 000000000..a0c09a48f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p70.c @@ -0,0 +1,333 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_OemKeyIndexValidationSub (const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00700001U); + WR1_PROG(REG_144CH, 0x00000000U); + + HW_SCE_p_func049(InData_Cmd); + + WR1_PROG(REG_1600H, 0x0000094aU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e4U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3000a880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x3000a880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000027U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00040020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000ffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000b480U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000feU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000b480U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x3420a880U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000028U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x0d68e83fU, 0xb2e2696eU, 0x264d2195U, 0xfcdce7adU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xdfa53e99U, 0xc8d4ea09U, 0x00570085U, 0xf631213cU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x0000349fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000070U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xe9bc5f86U, 0x6e6f14b0U, 0xea9c5f38U, 0x6ae063fdU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x000034e4U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000070U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x413394fbU, 0x902f3acaU, 0xaabc9135U, 0x888c1d81U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x1624914aU, 0xcc48fd3dU, 0xa4678fb4U, 0x125844daU); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func081(); + + WR1_PROG(REG_1600H, 0x00007c01U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1444H, 0x00020062U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009c06U); + + for (iLoop = 0U; iLoop < (KEY_INDEX_SIZE - 5); ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func209(); + + HW_SCE_p_func101(0x2412a5bcU, 0x7632e858U, 0x1c4a7f40U, 0xc438f315U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000aU) + { + WR1_PROG(REG_1444H, 0x000023c2U); + WR1_PROG(REG_1A2CH, 0x40000800U); + WR1_PROG(REG_1A24H, 0xe8009007U); + + for (iLoop = 0U; iLoop < 36U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x00001fc2U); + WR1_PROG(REG_1A2CH, 0x40000700U); + WR1_PROG(REG_1A24H, 0xf7008c07U); + + for (iLoop = 36U; iLoop < 68U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func101(0x4507e9d2U, 0x2c6bb3f6U, 0x6b5d4166U, 0xc04fc143U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000bU) + { + WR1_PROG(REG_1444H, 0x00001fc2U); + WR1_PROG(REG_1A2CH, 0x40000700U); + WR1_PROG(REG_1A24H, 0xf7009c07U); + + for (iLoop = 0U; iLoop < 32U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x00003fc2U); + WR1_PROG(REG_1A2CH, 0x40000f00U); + WR1_PROG(REG_1A24H, 0xf7008c07U); + + for (iLoop = 32U; iLoop < 96U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func101(0x86bf6087U, 0x380f4308U, 0xabbe01c4U, 0xbe7f8f14U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000cU) + { + WR1_PROG(REG_1444H, 0x000043c2U); + WR1_PROG(REG_1A2CH, 0x40001000U); + WR1_PROG(REG_1A24H, 0xe8009007U); + + for (iLoop = 0U; iLoop < 68U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x00003fc2U); + WR1_PROG(REG_1A2CH, 0x40000f00U); + WR1_PROG(REG_1A24H, 0xf7008c07U); + + for (iLoop = 68U; iLoop < 132U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func101(0x806c0a7eU, 0xda9f2525U, 0x183989cdU, 0x6cc4cfd7U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x0000000dU) + { + WR1_PROG(REG_1444H, 0x00003fc2U); + WR1_PROG(REG_1A2CH, 0x40000f00U); + WR1_PROG(REG_1A24H, 0xf7009c07U); + + for (iLoop = 0U; iLoop < 64U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x00007fc2U); + WR1_PROG(REG_1A2CH, 0x40001f00U); + WR1_PROG(REG_1A24H, 0xf7008c07U); + + for (iLoop = 64U; iLoop < 192U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func101(0xa0451e9cU, 0xe8e012fbU, 0xcadc55c3U, 0xdad8a2efU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000012U) + { + WR1_PROG(REG_1444H, 0x00020062U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8009006U); + + for (iLoop = 0U; iLoop < (KEY_INDEX_SIZE - 5); ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func209(); + + HW_SCE_p_func101(0x6a40712bU, 0x2ac99247U, 0x50a74dd6U, 0x8874f964U); + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1 + iLoop]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x7adcd9bcU, 0x5487c2a5U, 0x97e3cd7fU, 0x5b141035U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xe5864acdU, 0x64829e6dU, 0x0365855eU, 0xa095d679U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func102(0xf6ffd952U, 0x5cd8b580U, 0xf8dc2619U, 0xd4e88ddeU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p72.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p72.c new file mode 100644 index 000000000..f4f617594 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p72.c @@ -0,0 +1,391 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_ShaGenerateMessageDigestSub (const uint32_t InData_HashType[], + const uint32_t InData_Cmd[], + const uint32_t InData_Msg[], + const uint32_t InData_MsgLen[], + const uint32_t InData_State[], + uint32_t OutData_MsgDigest[], + uint32_t OutData_State[], + const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00720001U); + WR1_PROG(REG_144CH, 0x00000000U); + + HW_SCE_p_func100(0x5cc7a738U, 0x90dc8200U, 0x34171e23U, 0xd831d306U); + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_HashType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a820U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00046fffU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000013e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c1fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_2004H, 0x00000000U); + + HW_SCE_p_func101(0x567bd220U, 0xe387700aU, 0xb93858c6U, 0xd4c52eabU); + } + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000020U) + { + WR1_PROG(REG_2004H, 0x00001000U); + + HW_SCE_p_func101(0x722d1de3U, 0x779cee14U, 0xc58e7e64U, 0xeb3620ebU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_2004H, 0x00000040U); + + HW_SCE_p_func101(0xb7b4d935U, 0x46c22addU, 0xa5558401U, 0x4607a89dU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000021U) + { + WR1_PROG(REG_2004H, 0x00001040U); + + HW_SCE_p_func101(0x67442591U, 0x786e30bbU, 0x93902f5cU, 0x578d3adaU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_2004H, 0x00000050U); + + HW_SCE_p_func101(0xf518e2aeU, 0x8e1b36f8U, 0x70ecea7aU, 0xca9d23f4U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000022U) + { + WR1_PROG(REG_2004H, 0x00001050U); + + HW_SCE_p_func101(0xda089660U, 0x18025d26U, 0xddcd1998U, 0x896953edU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_2004H, 0x00000080U); + + HW_SCE_p_func101(0x26b0b178U, 0x1d0fe47eU, 0x45e58734U, 0x6215c917U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000023U) + { + WR1_PROG(REG_2004H, 0x00001080U); + + HW_SCE_p_func101(0xc47858b3U, 0x4995e6faU, 0x7896f678U, 0xd71e6cdcU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_2004H, 0x00000090U); + + HW_SCE_p_func101(0x42732d61U, 0x8cecb6baU, 0x16bf231aU, 0xb034c5cbU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000024U) + { + WR1_PROG(REG_2004H, 0x00001090U); + + HW_SCE_p_func101(0x581caea6U, 0x596410d2U, 0x082546efU, 0x23d25de0U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000005U) + { + WR1_PROG(REG_2004H, 0x000000a0U); + + HW_SCE_p_func101(0xf95267a0U, 0x018e70c5U, 0x5aab4063U, 0xb34b9005U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000025U) + { + WR1_PROG(REG_2004H, 0x000010a0U); + + HW_SCE_p_func101(0xe43eff9dU, 0x68a1f827U, 0xeb746affU, 0xbb50f3c5U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) + { + WR1_PROG(REG_2004H, 0x000000b0U); + + HW_SCE_p_func101(0xee47d997U, 0xb5114802U, 0xf7d566b7U, 0x57a414a3U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000026U) + { + WR1_PROG(REG_2004H, 0x000010b0U); + + HW_SCE_p_func101(0xe976cebfU, 0x9ee6f387U, 0x4cabc998U, 0xcca0c4e3U); + } + + WR1_PROG(REG_1600H, 0x38008c20U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x7e733a2fU, 0x1c43d408U, 0x48cf0d5dU, 0xc2578cc4U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + if ((InData_MsgLen[0] == 0) && (InData_MsgLen[1] == 0)) + { + WR1_PROG(REG_200CH, 0x00000100U); + + HW_SCE_p_func101(0x17b8a614U, 0xe92389f4U, 0x4f5c2c06U, 0x36fc165fU); + } + else + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, InData_MsgLen[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, InData_MsgLen[1]); + + HW_SCE_p_func101(0x69c2380cU, 0xf7dddb4cU, 0x5a26f049U, 0xc9c08de7U); + } + } + else + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, InData_State[18]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, InData_State[19]); + + for (iLoop = 0U; iLoop < 18; ) + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2028H, InData_State[iLoop]); + iLoop = iLoop + 1U; + } + + HW_SCE_p_func101(0x3548bbb4U, 0x3723cbd6U, 0x5f1d925aU, 0x32561ea2U); + } + + WR1_PROG(REG_1444H, 0x00020064U); + + for (iLoop = 0U; iLoop < (MAX_CNT & 0xfffffff0U); ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Msg[iLoop]); + WR4_ADDR(REG_1420H, &InData_Msg[iLoop + 4]); + WR4_ADDR(REG_1420H, &InData_Msg[iLoop + 8]); + WR4_ADDR(REG_1420H, &InData_Msg[iLoop + 12]); + + iLoop = iLoop + 16U; + } + + WAIT_STS(REG_1444H, 31, 1); + for (iLoop = (MAX_CNT & 0xfffffff0U); iLoop < MAX_CNT; ) + { + WR1_PROG(REG_1420H, InData_Msg[iLoop]); + + iLoop = iLoop + 1U; + } + + WR1_PROG(REG_1444H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008820U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008820U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x567e410eU, 0x371ac929U, 0xfe0d7c0aU, 0xc213adfcU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WAIT_STS(REG_2030H, 8, 0); + for (iLoop = 0U; iLoop < 18; ) + { + RD1_ADDR(REG_202CH, &OutData_State[iLoop]); + iLoop = iLoop + 1U; + } + + RD1_ADDR(REG_2014H, &OutData_State[18]); + RD1_ADDR(REG_2010H, &OutData_State[19]); + + HW_SCE_p_func102(0xbb9650efU, 0xc4147094U, 0xc3d6d0a4U, 0x7263ee45U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + else + { + WAIT_STS(REG_2030H, 4, 1); + + HW_SCE_p_func100(0xb44467ddU, 0x4d8301f1U, 0xad44168aU, 0x3967754cU); + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func100(0xab266e93U, 0x312561ffU, 0xfb522dbaU, 0x43e512b4U); + WR1_PROG(REG_1408H, 0x00004016U); + for (iLoop = 0U; iLoop < 5; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[iLoop]); + iLoop = iLoop + 1U; + } + + HW_SCE_p_func102(0x0038d5aeU, 0x8385b01eU, 0x036509f6U, 0x1e4afdf1U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func100(0xb7a47235U, 0x7be6565eU, 0xe534067fU, 0x33a2c499U); + WR1_PROG(REG_1408H, 0x0000401eU); + for (iLoop = 0U; iLoop < 7; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[iLoop]); + iLoop = iLoop + 1U; + } + + HW_SCE_p_func102(0x34a7120fU, 0xaa6f4261U, 0x68591b80U, 0x8c81cdbbU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + HW_SCE_p_func100(0x2ce178f3U, 0xa1cc3febU, 0xc1949a5aU, 0x21497d09U); + WR1_PROG(REG_1408H, 0x00004022U); + for (iLoop = 0U; iLoop < 8; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[iLoop]); + iLoop = iLoop + 1U; + } + + HW_SCE_p_func102(0x172c0899U, 0x95e1cb98U, 0x8dc08fa0U, 0xc8dd378eU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000005U) + { + HW_SCE_p_func100(0x287bea2eU, 0x1df2e96fU, 0x4dbcb393U, 0x4c9d6cccU); + WR1_PROG(REG_1408H, 0x00004032U); + for (iLoop = 0U; iLoop < 12; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[iLoop]); + iLoop = iLoop + 1U; + } + + HW_SCE_p_func102(0x0e16e5aaU, 0x050a18f3U, 0x63018b80U, 0x9957231fU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000006U) + { + HW_SCE_p_func100(0x2fa2bc81U, 0xdfaebf75U, 0x92eafb33U, 0x9fceb828U); + WR1_PROG(REG_1408H, 0x00004042U); + for (iLoop = 0U; iLoop < 16; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_MsgDigest[iLoop]); + iLoop = iLoop + 1U; + } + + HW_SCE_p_func102(0xc4b453dfU, 0x18f97805U, 0x06a53817U, 0x5d2a0d9aU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + } + } + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76f.c new file mode 100644 index 000000000..ade87b175 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76f.c @@ -0,0 +1,198 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Sha256HmacFinalSub (const uint32_t InData_Cmd[], + const uint32_t InData_MAC[], + const uint32_t InData_MACLength[], + uint32_t OutData_MAC[]) +{ + uint32_t iLoop = 0U; + + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1444H, 0x000000c7U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000b780U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000b780U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00001000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000f9bU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x407397d5U, 0x5d29ab6aU, 0x0b0273e0U, 0x1e09991dU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x9bee7614U, 0x61e89e4aU, 0xbdbbfed8U, 0x8d9a4020U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x30f21789U, 0xcea3f161U, 0x6a4222f4U, 0x76742727U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func100(0xe93eff7dU, 0xf2107aa1U, 0x93c84bc9U, 0xf7aa32c5U); + WR1_PROG(REG_1408H, 0x00004022U); + for (iLoop = 0U; iLoop < 8U; iLoop++) + { + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_MAC[iLoop]); + } + + HW_SCE_p_func102(0xc6478cf9U, 0xf188132aU, 0xb513e95dU, 0xae761889U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MACLength[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a820U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x3420a820U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000021U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0xb17c651fU, 0x27a93aa4U, 0x8ee95100U, 0xd50a1038U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xb141c4fcU, 0x5a12c64bU, 0x9369d2e1U, 0xd7ec6592U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8088001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03450021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 32U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c1fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8188001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000055U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000007c1U); + WR1_PROG(REG_1824H, 0x9c000005U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MAC[0]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MAC[4]); + + HW_SCE_p_func100(0xb8ee34ccU, 0x09bbfd48U, 0x7476f64dU, 0x9c367c20U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x57175126U, 0xfd5324c9U, 0x9fdb84cdU, 0xfcebd5c5U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0x3dda05f2U, 0x13593a36U, 0xd2c915eaU, 0x5ff0576aU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76i.c new file mode 100644 index 000000000..cd581332d --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76i.c @@ -0,0 +1,448 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Sha256HmacInitSub (const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[], const uint32_t InData_Cmd[], const uint32_t InData_MsgLen[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00760001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_2004H, 0x00000050U); + + WR1_PROG(REG_2008H, 0x00000013U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xd7403fbeU, 0x1450b501U, 0x1185220cU, 0x60e0be31U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x384a67c9U, 0x93a38a97U, 0x1aaba0e7U, 0x9e90bdceU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x1ce5a9ddU, 0x110ccdb1U, 0x3c8a10e1U, 0xd0d49d65U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x5f414bd8U, 0x1a7aaf2cU, 0x3b3643bdU, 0x9880ea1aU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000076U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x2bd3eb66U, 0xcf901062U, 0xea16091fU, 0x0e7e8720U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001bU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x8330600fU, 0x5eb345a4U, 0xc358baffU, 0x30bbd80cU); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000076U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x8f022ab5U, 0xfd513cc0U, 0x38e50ccdU, 0x49fa4f4aU); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0xb6e3697fU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xc20c85f1U, 0x6c08e2b6U, 0x04158dc0U, 0x162ccec1U); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000076U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x0b07b776U, 0x799de06aU, 0xaf4578b3U, 0x043c88dbU); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1400H, 0x01420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b760U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xdfdb3940U, 0x6a18dd37U, 0x0f42d739U, 0x09b88f2cU); + } + else + { + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x012558dbU, 0x2f9d56bdU, 0x8fce8850U, 0x78c51279U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[1]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[2]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00ff0000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00020000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3c0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000d3c1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003760U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008f60U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000feU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3c2U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008bc0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00003540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003561U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003582U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000035a3U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000076U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x9844abd1U, 0x6b869e44U, 0x6a6ac7a2U, 0x2021f671U); + HW_SCE_p_func059(); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[4]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[8]); + + WR1_PROG(REG_1400H, 0x01420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[12]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0xb00e7028U, 0xb6a01584U, 0xb29674ccU, 0xbdb19aaeU); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010280U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003554U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000036a0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b6c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01249674U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000076U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x0a71da85U, 0x8131e6b3U, 0xb002e027U, 0xd8e8b1dcU); + HW_SCE_p_func092(); + + WR1_PROG(REG_1600H, 0x0000b760U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1400H, 0x01420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0x71fd1862U, 0xe26be3e6U, 0x4508977cU, 0xb4829f16U); + } + + HW_SCE_p_func101(0x01d9eda1U, 0x4f1ab3cdU, 0x8f734c7fU, 0xc5272f73U); + } + + HW_SCE_p_func100(0x207c754bU, 0x9c341ed8U, 0x5f359042U, 0x85ecf528U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x8799e705U, 0xbe7e68faU, 0xf9d5d3a3U, 0xa32a5c37U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + if ((InData_MsgLen[0] == 0) && (InData_MsgLen[1] == 0)) + { + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000080U); + + WR1_PROG(REG_200CH, 0x00000001U); + + WAIT_STS(REG_2030H, 8, 0); + + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000000U); + + WR1_PROG(REG_200CH, 0x00000100U); + + HW_SCE_p_func101(0x312ac86dU, 0x2b203894U, 0x320feb06U, 0x229c4e25U); + } + else + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, InData_MsgLen[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, InData_MsgLen[1]); + + WR1_PROG(REG_200CH, 0x00000001U); + + HW_SCE_p_func101(0x1aac2855U, 0x37843e26U, 0x1e2e9891U, 0xc13a84f3U); + } + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76u.c new file mode 100644 index 000000000..c2f0f8941 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p76u.c @@ -0,0 +1,54 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Sha256HmacUpdateSub (const uint32_t InData_Msg[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WAIT_STS(REG_2030H, 0, 1); + + WR1_PROG(REG_1444H, 0x00020064U); + + for (iLoop = 0U; iLoop < (MAX_CNT & 0xfffffff0U);) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Msg[iLoop]); + WR4_ADDR(REG_1420H, &InData_Msg[iLoop + 4]); + WR4_ADDR(REG_1420H, &InData_Msg[iLoop + 8]); + WR4_ADDR(REG_1420H, &InData_Msg[iLoop + 12]); + + iLoop = iLoop + 16U; + } + + for (iLoop = (MAX_CNT & 0xfffffff0U); iLoop < MAX_CNT; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Msg[iLoop]); + } + + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_2030H, 8, 0); + WR1_PROG(REG_143CH, 0x00001600U); + + HW_SCE_p_func101(0x46a867ecU, 0x9a2e09c5U, 0x9d8722e5U, 0x48b2a484U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p79.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p79.c new file mode 100644 index 000000000..6dbd2be54 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p79.c @@ -0,0 +1,326 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Rsa3072ModularExponentEncryptSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_Text[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00790001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000079U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x0915a7b6U, 0xaf6cbf0aU, 0x21134652U, 0x70c3e203U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000eU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000079U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xcaaff484U, 0xf3d64157U, 0x08f18170U, 0xb3ead2ebU); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000063c2U); + WR1_PROG(REG_1A2CH, 0x40001800U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1404H, 0x14b00000U); + for (iLoop = 0U; iLoop < 96U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1404H, 0x12200000U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x19069f6bU, 0x51d634f9U, 0x5e78aa03U, 0x9841f352U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x475e1bf5U, 0xde0ff3bfU, 0xccacc0b0U, 0xa72cf086U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x30300010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00005fc2U); + WR1_PROG(REG_1A2CH, 0x40001700U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x10a00000U); + for (iLoop = 0U; iLoop < 96U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800dbe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1404H, 0x18c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0017dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1404H, 0x18c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0017dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x8617eedfU, 0x84b9848cU, 0xff23ec2dU, 0xc6ad32b4U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xe9cc1b75U, 0x92c319b7U, 0xaca47790U, 0x7264a510U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x1a37752eU, 0x160eda7cU, 0xd43f0e38U, 0x35ed3c61U); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000228U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x0130000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x16b80000U); + + for (iLoop = 0U; iLoop < 96U; ) + { + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x34202be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000d3c0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c1eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x8cb8e41fU, 0xe7142edfU, 0x96619833U, 0xd00de614U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000008U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xd0090c90U, 0xe0785e21U, 0x3d817c81U, 0x62951e7bU); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1600H, 0x38000be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0xa23534d8U, 0xa0414251U, 0x8abcca05U, 0x1cb946bbU); + WR1_PROG(REG_1408H, 0x00020000U); + + HW_SCE_p_func102(0x1052126eU, 0x3a6fbd3eU, 0x6e8c3200U, 0x5ca2699dU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7a.c new file mode 100644 index 000000000..010a7d3e5 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7a.c @@ -0,0 +1,329 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Rsa3072ModularExponentDecryptSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_Text[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x007a0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000007aU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x5a8a2359U, 0x943c9117U, 0xdf879ba9U, 0xd1fc6ddeU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000007aU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x93ba7f5cU, 0xad11200aU, 0x74a345afU, 0x71d47de3U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x0000bfc2U); + WR1_PROG(REG_1A2CH, 0x40001700U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1404H, 0x14b00000U); + for (iLoop = 0U; iLoop < 96U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1A2CH, 0x40001700U); + WR1_PROG(REG_1A24H, 0xf7008d07U); + + WR1_PROG(REG_1404H, 0x12a80000U); + for (iLoop = 96U; iLoop < 192U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xec343e65U, 0xf88a6ae3U, 0x148e80fbU, 0x4f478b7aU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x8999ab21U, 0x7e9a4e5bU, 0xee62c661U, 0xd216e031U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x30300010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00005fc2U); + WR1_PROG(REG_1A2CH, 0x40001700U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x10a00000U); + for (iLoop = 0U; iLoop < 96U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800dbe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1404H, 0x18c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0017dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1404H, 0x18c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0017dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x3030000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x3cf3e725U, 0x58c250a6U, 0x6790e2ffU, 0xa73e9832U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x875be366U, 0x2cf9ec46U, 0xdc93114cU, 0x3db9438aU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x930a6449U, 0x0e006525U, 0xa6afddbcU, 0xdbbec0c8U); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000428U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x30300000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x16b80000U); + + for (iLoop = 0U; iLoop < 96U; ) + { + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x34202be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000d3c0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c1eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x483c164aU, 0x8a397a0cU, 0x7ffbf075U, 0x62210565U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000008U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xfdf861e7U, 0xe880802cU, 0xb627f622U, 0x535b1bb1U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1600H, 0x38000be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x575c5a80U, 0x1f2219f5U, 0x65047769U, 0x1e106b40U); + WR1_PROG(REG_1408H, 0x00020000U); + + HW_SCE_p_func102(0xe403e68bU, 0x90dcbd2fU, 0xd252a604U, 0x05d107d4U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7b.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7b.c new file mode 100644 index 000000000..dac1b6020 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7b.c @@ -0,0 +1,329 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Rsa4096ModularExponentEncryptSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_Text[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x007b0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000007bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xbf370ba4U, 0x986940bcU, 0x6d0f58f4U, 0x263d9690U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000007bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x757e01ffU, 0xa1e48bdeU, 0xa636d0ceU, 0x65b688f1U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00007fc2U); + WR1_PROG(REG_1A2CH, 0x40001f00U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1404H, 0x14300000U); + for (iLoop = 0U; iLoop < 128U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1404H, 0x12200000U); + WR1_PROG(REG_1400H, 0x00c00005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x692791eeU, 0x6bdedca1U, 0x39c83facU, 0x010cfa33U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x3d22e439U, 0xf85d6146U, 0x973f4b8bU, 0xa075ee44U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x40400010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00007fc2U); + WR1_PROG(REG_1A2CH, 0x40001f00U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x10200000U); + for (iLoop = 0U; iLoop < 128U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800dbe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1404H, 0x18400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c001fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1404H, 0x18400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c001fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x2f223c56U, 0x7a6d5116U, 0xb6853092U, 0xee9730dcU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x4f470cb2U, 0x2dfba817U, 0xdd7b495eU, 0xae0d458dU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xa36591acU, 0x57d9e270U, 0x6da4aed1U, 0x381ef1d0U); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000228U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x0140000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x16380000U); + + for (iLoop = 0U; iLoop < 128U; ) + { + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x34202be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000d3c0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c1eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x6dc22715U, 0x064867b6U, 0x8bf9ee28U, 0xc3e805ebU); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000008U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x1548f8f0U, 0x93f28dd5U, 0x1e4e8104U, 0x01eb3fceU); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1600H, 0x38000be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x03ef30e7U, 0xc038f14cU, 0x79a2cd31U, 0x3caeb369U); + WR1_PROG(REG_1408H, 0x00020000U); + + HW_SCE_p_func102(0xb6d81cb6U, 0x8dcab554U, 0x33c29636U, 0xc6d4f3eeU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7c.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7c.c new file mode 100644 index 000000000..b59c36145 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7c.c @@ -0,0 +1,329 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Rsa4096ModularExponentDecryptSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_Text[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x007c0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x00000e50U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000007cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xd116cbf8U, 0x362f47d4U, 0x4cbe4cb5U, 0x9a2fdc4cU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000011U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000007cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x358c9135U, 0x4653de86U, 0xc9a74fceU, 0xc9f4a4d6U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x0000ffc2U); + WR1_PROG(REG_1A2CH, 0x40001f00U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1404H, 0x14300000U); + for (iLoop = 0U; iLoop < 128U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1A2CH, 0x40001f00U); + WR1_PROG(REG_1A24H, 0xf7008d07U); + + WR1_PROG(REG_1404H, 0x12280000U); + for (iLoop = 128U; iLoop < 256U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x7ea1f133U, 0x7c117241U, 0x556347e9U, 0xe3561280U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x643692e0U, 0xacd12f50U, 0xff899e4fU, 0xb0f22656U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x00000630U); + + WR1_PROG(REG_1004H, 0x40400010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00007fc2U); + WR1_PROG(REG_1A2CH, 0x40001f00U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x10200000U); + for (iLoop = 0U; iLoop < 128U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop + 4]); + WR1_PROG(REG_1400H, 0x00c20021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1404H, 0x16280000U); + WR1_PROG(REG_1608H, 0x800103e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00030005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x03430005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x3800dbe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1404H, 0x18400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c001fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000a40U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + WR1_PROG(REG_1404H, 0x18400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c001fdU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000630U); + WR1_PROG(REG_1018H, 0x00000a40U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000838U); + WR1_PROG(REG_1018H, 0x00000220U); + WR1_PROG(REG_1020H, 0x00000a40U); + + WR1_PROG(REG_1004H, 0x4040000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x125e5cdbU, 0x1408324cU, 0x36f84efaU, 0x9d864fb5U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x9f3d1319U, 0x98d354c6U, 0xed0b508eU, 0xe26631caU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xd9bd9a20U, 0x3dce0474U, 0xc56244c4U, 0x726c9d65U); + WR1_PROG(REG_1014H, 0x00000220U); + WR1_PROG(REG_1018H, 0x00000428U); + WR1_PROG(REG_101CH, 0x00000630U); + WR1_PROG(REG_1020H, 0x00000838U); + + WR1_PROG(REG_1004H, 0x40400000U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x16380000U); + + for (iLoop = 0U; iLoop < 128U; ) + { + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x34202be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000d3c0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007c1eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x2b84d1d6U, 0x7aa3b3c0U, 0xa521d217U, 0x8cff796bU); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000008U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x29c55687U, 0xad0d3ad3U, 0xca53f18bU, 0xc59aa702U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1600H, 0x38000be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0xf6dfef6aU, 0xedb32297U, 0x3c4514a8U, 0x21febec3U); + WR1_PROG(REG_1408H, 0x00020000U); + + HW_SCE_p_func102(0xd481cc5cU, 0xa03ccbf8U, 0x2a7bbf87U, 0x53c4a983U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7d.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7d.c new file mode 100644 index 000000000..529be383e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7d.c @@ -0,0 +1,480 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_EcdsaP512SignatureGenerateSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x007d0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + HW_SCE_p_func100(0xb1d18d00U, 0xc6480669U, 0xab8bb25eU, 0x76b06d73U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000270U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + HW_SCE_p_func100(0xfc280c75U, 0x20e74569U, 0x57b7bd54U, 0xbf02130aU); + HW_SCE_p_func078(OFS_ADR); + HW_SCE_p_func100(0xc050cef8U, 0xae277dd5U, 0x11441d63U, 0x500f6fb2U); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10d00000U); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x3feb20cbU, 0xb4482323U, 0x1b69e3e3U, 0x9c72d205U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0xdd542e90U, 0x01c6b675U, 0xb4d8facdU, 0xc1858b68U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0x08cc7c2cU, 0x6b2dfb59U, 0x65e339bcU, 0x180c2234U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000340U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x08080004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x87a25addU, 0xe2646ef1U, 0xe1534db8U, 0xd798ecb7U); + HW_SCE_p_func079(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000007dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xbc777d7eU, 0x3d07fccbU, 0xb2d18bd5U, 0xf85cbdefU); + HW_SCE_p_func090(); + + HW_SCE_p_func100(0x99aace2fU, 0xffc8148cU, 0xc113485bU, 0xa8adbb2fU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x658b0e9fU, 0x9355a40aU, 0xb785b85fU, 0xf8722862U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002f0U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x08080004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000140U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x1c4b0b26U, 0xc68012acU, 0x54454912U, 0xf801fb0dU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xd87746ceU, 0x2c704c5fU, 0x4831746bU, 0xa4420a46U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xcad570b6U, 0x4837afdfU, 0x88dca004U, 0xdba62212U); + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0808000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x00000300U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x11200000U); + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MsgDgst[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000007dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x5012fea0U, 0xa96776dcU, 0x40d23862U, 0x4817dbceU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000021U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000007dU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xdcd318c9U, 0x32565fdbU, 0xb4648aa6U, 0x5967389aU); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x40000300U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1404H, 0x11c00000U); + + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x0ff18934U, 0x6e7f77a4U, 0x662b87b7U, 0x3301fdc9U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x188155f2U, 0x81be6c48U, 0x54756a27U, 0x419e118bU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x08080005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000140U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x96c2a3a9U, 0xb9eec4a0U, 0x22ee31a9U, 0x40578679U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x71e40d07U, 0xe63fa3ceU, 0x7c6bc339U, 0x9920a7eaU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x3119e886U, 0xdcf4c5cfU, 0x89ef8248U, 0xcb09df26U); + WR1_PROG(REG_1404H, 0x12600000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[0]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[4]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[8]); + + HW_SCE_p_func100(0x9d429aadU, 0x5ca691acU, 0xa4c1e188U, 0xd08a3b6dU); + WR1_PROG(REG_1A24H, 0x08000105U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[12]); + + HW_SCE_p_func100(0xd3c18561U, 0x01d31a11U, 0xde221541U, 0xf454d0a3U); + WR1_PROG(REG_1404H, 0x11c00000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[16]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[20]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[24]); + + HW_SCE_p_func100(0xa7f9b3a6U, 0x1b4a7050U, 0xe5107339U, 0x6fbf254fU); + WR1_PROG(REG_1A24H, 0x08000105U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[28]); + + HW_SCE_p_func102(0xd56043d0U, 0x7eb57570U, 0x175cef51U, 0xa7fa5c5cU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7e.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7e.c new file mode 100644 index 000000000..141498ac4 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7e.c @@ -0,0 +1,733 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_EcdsaP512SignatureVerificationSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x007e0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000007eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xb746c054U, 0xe581f3acU, 0x80c1a421U, 0x871de6b8U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000007eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xf03b4119U, 0xde1eb383U, 0xc8d68218U, 0x7bc5d1deU); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00001fc2U); + WR1_PROG(REG_1A2CH, 0x40000700U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80a00001U); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 17]); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[33]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x5ee36677U, 0xbafd2fffU, 0xf81821dfU, 0xfeadc77aU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xe54ea67dU, 0x411d826dU, 0x3761d5bfU, 0xafae9898U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x00000fc7U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8090001fU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MsgDgst[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000007eU)); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + HW_SCE_p_func100(0xbe2c9489U, 0x2b85cd29U, 0xa4ef8160U, 0x3cbfda71U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000270U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + HW_SCE_p_func100(0x37acd9c8U, 0x59a8c6a0U, 0xa423f788U, 0x9e45fca7U); + HW_SCE_p_func078(OFS_ADR); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x18f00000U); + WR1_PROG(REG_1444H, 0x00001fc2U); + WR1_PROG(REG_1A2CH, 0x00000700U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[4]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[8]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[12]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19400000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[16]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[20]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[24]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[28]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000930U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000980U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x7812bcb7U, 0x9e5ed5efU, 0xf01fb28bU, 0x87ab5a74U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xce0d89a5U, 0xab773285U, 0x80501a1cU, 0x0bd8f0c1U); + } + else + { + HW_SCE_p_func100(0xbd5bb4b6U, 0x279b7d74U, 0x6f881cefU, 0x311d3d86U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x0808000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8190001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00c90041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x4045b29bU, 0x58a72eb3U, 0x2a8882dcU, 0xf2b9facbU); + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1404H, 0x11600000U); + WR1_PROG(REG_1400H, 0x00c000f1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func079(OFS_ADR); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x08080004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1400H, 0x00c00041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000890U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000002a8U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x6c340799U, 0x3b1bd78dU, 0x3544a977U, 0x04a55c4fU); + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000340U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x08080015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x11c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x70f1f88bU, 0x9435b402U, 0x6fe7d1c2U, 0x9eaeeecaU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x941d2338U, 0xf58e9855U, 0x24f12d7bU, 0x281a64d7U); + } + else + { + HW_SCE_p_func100(0x4042e5dcU, 0x0bb511fcU, 0x475323a2U, 0xcc262939U); + WR1_PROG(REG_1404H, 0x11800000U); + WR1_PROG(REG_1400H, 0x00c00041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000001c0U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1608H, 0x81900001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00c90041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000001c0U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1600H, 0x000037e1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8190001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00c90041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000208U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000340U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x08080015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x11c00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x0d6720c9U, 0xee48d2c2U, 0xd47c00b0U, 0xa00387b6U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x185fdc7aU, 0xd5d55621U, 0x038820edU, 0x27a8f3dcU); + } + else + { + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x08080013U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x12600000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xbc6fc267U, 0xc3c2904eU, 0xf242c321U, 0x3c0c1ebdU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xd115d0f6U, 0x53f07113U, 0xb18d748bU, 0xff1e8f53U); + } + else + { + HW_SCE_p_func100(0xe6dd9046U, 0x154253e1U, 0xddc760b4U, 0x371c6320U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x08080004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0808000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000001c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000930U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xa64ca8c0U, 0x28b252ebU, 0x69f5ff56U, 0x4fb9398dU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x60f3dbe4U, 0x957ca780U, 0x4aee27e4U, 0xc5f43059U); + } + else + { + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x797935bbU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x1c1f8dbbU, 0x87d0e4bbU, 0x6629f3b7U, 0xda35538cU); + } + } + } + } + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x797935bbU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00007c1bU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0xfb795218U, 0x81152a78U, 0x54cdacc0U, 0x6715d108U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xee6a4ca7U, 0x5e354fe3U, 0x477f2504U, 0x71c39cffU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0xf8007f76U, 0xdce4555dU, 0x87229698U, 0x7f2632adU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7f.c new file mode 100644 index 000000000..385e273df --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p7f.c @@ -0,0 +1,636 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateEccP512RandomKeyIndexSub (uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x007f0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + HW_SCE_p_func100(0xeb5653a9U, 0xeb87ae35U, 0x561ec671U, 0x518d4674U); + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000270U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0] ; + + HW_SCE_p_func100(0x93e2120cU, 0x84619745U, 0x76116d12U, 0x703c06deU); + HW_SCE_p_func078(OFS_ADR); + + HW_SCE_p_func100(0x5e61bba3U, 0x58e23da9U, 0x10974131U, 0x3d02df87U); + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12a80000U); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x714b9828U, 0x3a3ee05dU, 0x47efe395U, 0xf7a9e87cU); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0x21077545U, 0x41462ba1U, 0x03572746U, 0x76075846U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0x4fdb3c15U, 0xfbdcd473U, 0x97bf3a4cU, 0x77d060b4U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0x53dc7806U, 0x6c967c3cU, 0x52a36d51U, 0x48f055c3U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1400H, 0x00c20009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11180000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x08080007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x7e6c4b2aU, 0x22162a36U, 0xfcbeb49dU, 0xe8b3d986U); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x12080000U); + WR1_PROG(REG_1608H, 0x80920001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03430049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + for (iLoop = 0U; iLoop < 18U; iLoop++) + { + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x20000842U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10003841U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x3800585eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x20003460U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10002c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x100033c0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1404H, 0x14380000U); + WR1_PROG(REG_1400H, 0x00c00049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c00045U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00003403U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003060U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x09090007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00003060U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xc682cdd9U, 0x2b346a26U, 0x692bf961U, 0xf6739782U); + } + + WR1_PROG(REG_1600H, 0x00007c03U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10c80000U); + WR1_PROG(REG_1400H, 0x00c00049U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xec9e3885U, 0x414bd6d2U, 0x410fa3e0U, 0x4d9af617U); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0909000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + HW_SCE_p_func100(0x13c4ee25U, 0xb6ad173aU, 0xff7e7ffbU, 0x5750eba9U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func101(0xf17fda6dU, 0xf3f8144cU, 0x4865d69fU, 0xbc9dc0feU); + } + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0909000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x09090009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1600H, 0x00003000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x9f8307a2U, 0x5331cd63U, 0x812f45f7U, 0xb3cab933U); + } + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0003dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x6f3812faU, 0x25ab5fa4U, 0xf0852ffeU, 0x9453ab8fU); + + HW_SCE_p_func079(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000007fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x21d14fd8U, 0x18e44927U, 0x4292704eU, 0xf9dd785cU); + HW_SCE_p_func090(); + + HW_SCE_p_func100(0xf37bbaa8U, 0x74c1aefdU, 0x885677f1U, 0xeab4227fU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x02b8f959U, 0x5afeaed3U, 0xbce82567U, 0x500ea3dfU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x76b60d76U, 0x9b51e081U, 0x290e5488U, 0x9fd382d6U); + HW_SCE_p_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000007fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xb1ce5e52U, 0xeb2510baU, 0xfeddc904U, 0x50eea20fU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000021U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000007fU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x9095a027U, 0xc2a6fd1fU, 0xff0b385dU, 0x3d4261c2U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x097f16a5U, 0x2dadcff5U, 0x3e569534U, 0x66dae6d4U); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1404H, 0x13000000U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func100(0x7cb6f59cU, 0x4ca414d0U, 0x1a9c5109U, 0x7baa5d64U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe7008d05U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[iLoop + 1]); + + HW_SCE_p_func100(0x5a2cd602U, 0x11444c6eU, 0x3f63919fU, 0x4dadbf8bU); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[iLoop + 5]); + + HW_SCE_p_func100(0x71747d61U, 0xe1111755U, 0xcec37b33U, 0x09d5372aU); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PrivKeyIndex[0]); + + HW_SCE_p_func100(0xf102628aU, 0xcb0da2e1U, 0xfe125f7dU, 0x9788dcd6U); + HW_SCE_p_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000009U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xb85abf2dU, 0x57438962U, 0xa292c694U, 0x50f89a5dU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000009U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xb9ca1acdU, 0x0ea3504aU, 0xf81e5781U, 0xf3dbdf22U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xad062cbbU, 0xac90b416U, 0x7148d60fU, 0x34f4b3e7U); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8009107U); + WR1_PROG(REG_1404H, 0x12600000U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func100(0x624ecc5eU, 0x2c49561fU, 0xcf928386U, 0x8a864eefU); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8008107U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x12b00000U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + for (iLoop = iLoop; iLoop < 24U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func100(0x7b452c8dU, 0xd026d7e6U, 0x4f24cae9U, 0x736006a2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe8008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + for (iLoop = iLoop; iLoop < 32U; ) + { + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func100(0xdaec2770U, 0x6fe075edU, 0x84d26be2U, 0xe48387d1U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[iLoop + 1]); + + HW_SCE_p_func100(0x0eb58136U, 0x918c3f75U, 0x19adb510U, 0xa310c369U); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PubKeyIndex[0]); + + HW_SCE_p_func102(0xf091d15cU, 0xb7cf23fcU, 0x598410dfU, 0x16f00bb6U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p81.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p81.c new file mode 100644 index 000000000..21badd8d7 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p81.c @@ -0,0 +1,101 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_SelfCheck1Sub (void) +{ + WR1_PROG(REG_1D04H, 0x00043cb3U); + WR1_PROG(REG_1D08H, 0x000d5151U); + + WR1_PROG(REG_1D00H, 0x00000001U); + + WAIT_STS(REG_1D00H, 1, 0); + + if (RD1_MASK(REG_1D00H, 0x00030000U) != 0x00000000U) + { + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_140CH, 0x38c60eedU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1448H, 0x00000000U); + + WR1_PROG(REG_1408H, 0x00000001U); + WR1_PROG(REG_1414H, 0x00001601U); + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1800H, 0x00000001U); + WR1_PROG(REG_1700H, 0x00000001U); + + WR1_PROG(REG_1B00H, 0x00818001U); + WR1_PROG(REG_1B08H, 0x00000d00U); + + WR1_PROG(REG_1804H, 0x00008002U); + + WR1_PROG(REG_1444H, 0x000003a2U); + HW_SCE_p_func101(change_endian_long(0x761c3212U), change_endian_long(0x5929b561U), change_endian_long(0x41d63d71U), change_endian_long(0xc203e20eU)); + WR1_PROG(REG_1804H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A24H, 0x0a0700f5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, 0xb45a1978U, 0x5a5a637bU, 0xe29d7bddU, 0x6d004e9bU); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + HW_SCE_p_func101(change_endian_long(0xf9e62180U), change_endian_long(0x81a998d0U), change_endian_long(0x19561115U), change_endian_long(0x985f70c1U)); + + HW_SCE_p_func100(change_endian_long(0x0c85360bU), change_endian_long(0x8794147aU), change_endian_long(0x9fe177e4U), change_endian_long(0x38d62ae4U)); + + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_142CH, 13, 0)) + { + WR1_PROG(REG_14BCH, 0x00000020U); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1430H, 0x0000FFFFU); + + WR1_PROG(REG_1B08H, 0x00000220U); + + HW_SCE_p_func102(change_endian_long(0x3ef67e43U), change_endian_long(0xbf82d536U), change_endian_long(0x648d23c9U), change_endian_long(0xabad7ea7U)); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p82.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p82.c new file mode 100644 index 000000000..7572ea67d --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p82.c @@ -0,0 +1,401 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_SelfCheck2Sub (void) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00820001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0b070194U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x01c7ba56U)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000074U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1600H, 0x3000a820U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WAIT_STS(REG_1708H, 0, 0); + WAIT_STS(REG_1708H, 0, 0); + WR1_PROG(REG_1704H, 0x00000080U); + + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000884U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000008a5U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000013U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000348U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b500U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000b7U); + WR1_PROG(REG_1458H, 0x00000000U); + + for (jLoop = 0U; jLoop < 1U; jLoop++) + { + HW_SCE_p_func100(0x368a065cU, 0x897501c5U, 0xf71f5072U, 0x093ad3a5U); + WR1_PROG(REG_1600H, 0x00007c01U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WAIT_STS(REG_1708H, 0, 0); + WAIT_STS(REG_1708H, 0, 0); + WR1_PROG(REG_1704H, 0x00200017U); + + HW_SCE_p_func101(0x98f53c8dU, 0x47509f6dU, 0x200190e6U, 0x2ca421fdU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WAIT_STS(REG_1708H, 0, 0); + WAIT_STS(REG_1708H, 0, 0); + WR1_PROG(REG_1704H, 0x00200015U); + + HW_SCE_p_func101(0x4b4e2f44U, 0x2dd587ccU, 0x8ff064d9U, 0x370e66b2U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WAIT_STS(REG_1708H, 0, 0); + WAIT_STS(REG_1708H, 0, 0); + WR1_PROG(REG_1704H, 0x00200016U); + + HW_SCE_p_func101(0xfc3c43e9U, 0xe1b21c6fU, 0x6b2dd802U, 0x17abbe34U); + } + + WR1_PROG(REG_1A2CH, 0x00000700U); + WR1_PROG(REG_1A24H, 0x0e3d8407U); + WR1_PROG(REG_1400H, 0x00840081U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WAIT_STS(REG_1708H, 2, 1); + WR1_PROG(REG_143CH, 0x00001200U); + + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000a00U); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x808a0000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03440029U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000038a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003405U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002804U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x342028e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10005066U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x34202808U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10005066U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003485U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xf19b3623U, 0xffe0ede4U, 0x1388e7fdU, 0x86df531bU); + } + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000005AU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000842U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x01003804U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x342028e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10005066U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002440U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002cc0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002485U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x00002c20U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008840U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000100U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000033U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000024U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x01003804U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x342028e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10005066U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00002cc0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000026U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x01003804U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x342028e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10005066U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008860U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x9ad77a94U, 0x89a8905aU, 0x0392f17eU, 0x96cf854bU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xc3df8315U, 0x55bf355fU, 0xdd051e65U, 0x85bb4afeU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_RETRY; + } + else + { + HW_SCE_p_func100(0xbe6b3f7dU, 0x4b81b482U, 0x1ca97b85U, 0xdf5addc7U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c300104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A2CH, 0x00000600U); + WR1_PROG(REG_1A24H, 0x0e3d9407U); + WAIT_STS(REG_1708H, 0, 0); + WAIT_STS(REG_1708H, 0, 0); + WR1_PROG(REG_1704H, 0x001c0013U); + WR1_PROG(REG_1400H, 0x00840071U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1A24H, 0x0e3d0505U); + WAIT_STS(REG_1708H, 0, 0); + WAIT_STS(REG_1708H, 0, 0); + WR1_PROG(REG_1704H, 0x00040013U); + WR1_PROG(REG_1400H, 0x00840011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1708H, 3, 0); + WR1_PROG(REG_1700H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x080000b4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + HW_SCE_p_func100(0x884318faU, 0xe93761efU, 0xbdcb75f3U, 0x25eff0cfU); + WR1_PROG(REG_1444H, 0x000003a2U); + WR1_PROG(REG_1A24H, 0x08000075U); + WAIT_STS(REG_1444H, 31, 1); + WR4_PROG(REG_1420H, change_endian_long(0x00000000U), change_endian_long(0x00000000U), change_endian_long(0x00000000U), change_endian_long(0x00000001U)); + + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x07338d07U); + WR1_PROG(REG_1608H, 0x81080000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A24H, 0x080000b5U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x456c7d49U, 0x6ad8ddacU, 0x9a1c5ff4U, 0x7fbb071fU); + WR1_PROG(REG_1A24H, 0x08000075U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0x4ab34523U, 0xef6d4fbdU, 0xa0b5ef49U, 0xd39b8c66U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c2000d4U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + HW_SCE_p_func100(0x13d77c79U, 0xbd48bfffU, 0x50b1dd72U, 0x7ccd58c9U); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x6ecfa4f5U, 0x73219c01U, 0x2d9191acU, 0x55af48c3U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &S_RAM[16]); + S_RAM[16] = change_endian_long(S_RAM[16]); + S_RAM[17] = change_endian_long(S_RAM[17]); + S_RAM[18] = change_endian_long(S_RAM[18]); + S_RAM[19] = change_endian_long(S_RAM[19]); + + HW_SCE_p_func100(0x5156bc8fU, 0xdfdcc33dU, 0x3bc06385U, 0xed6e6f33U); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1404H, 0x20000000U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10000000U); + WR1_PROG(REG_1400H, 0x00c01001U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1B00H, 0x00008002U); + WR1_PROG(REG_1B08H, 0x00000d01U); + + WR1_PROG(REG_1B00H, 0x00008001U); + + WR1_PROG(REG_1B08H, 0x00000214U); + + HW_SCE_p_func102(0x9aa4c9acU, 0x55329054U, 0xa4b6055cU, 0xc461945eU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83a.c new file mode 100644 index 000000000..74d9a4a8e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83a.c @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes192GcmEncryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008006U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + HW_SCE_p_func101(0x5c7b9219U, 0x1ab6cb38U, 0xbb1f809cU, 0x553a5cb5U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83f.c new file mode 100644 index 000000000..603d6aba8 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83f.c @@ -0,0 +1,185 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes192GcmEncryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataALen[], + uint32_t OutData_Text[], + uint32_t OutData_DataT[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020100U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b580U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007FU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0xFFFFFF00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0c0029a9U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x04a02988U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x0dd41153U, 0x89eb42ebU, 0x72cf7ae3U, 0x589537d1U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xb0eac53eU, 0xffddbd77U, 0x5c509351U, 0x18165724U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003409U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00036800U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x08008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0xb2e7e224U, 0xa0655de1U, 0xb49298a6U, 0xde79b1d2U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000030U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + HW_SCE_p_func100(0xa9aca012U, 0xd9dfd992U, 0xd727b9b2U, 0xbd119d4aU); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + HW_SCE_p_func101(0x5860fed0U, 0xcfa40aa6U, 0xba1666a0U, 0x7e8ede48U); + } + + HW_SCE_p_func100(0xdd2f93cbU, 0x7fb9e8a6U, 0x10f13213U, 0x3b0d8ad8U); + WR1_PROG(REG_1444H, 0x000001c1U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + WAIT_STS(REG_1444H, 31, 1); + WR2_ADDR(REG_1420H, &InData_DataALen[0]); + + WR1_PROG(REG_1608H, 0x81020100U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_182CH, 0x00400000U); + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_182CH, 0x40000030U); + WR1_PROG(REG_1824H, 0x07008d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_DataT[0]); + + HW_SCE_p_func102(0x5ce7d9d7U, 0x87bf804cU, 0x8c6cec26U, 0xbd80b029U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83i.c new file mode 100644 index 000000000..ab36c0940 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83i.c @@ -0,0 +1,144 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes192GcmEncryptInitSub (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00830001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000083U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x1ead83e5U, 0x58e7e77bU, 0x793a8fb3U, 0xdc1ea079U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000083U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x60bbf361U, 0xf4a0a20eU, 0x73fd0589U, 0x90b35706U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x51df951cU, 0x7c1cbd32U, 0x1263d4ddU, 0xd169d223U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x450eec23U, 0x6ed96665U, 0x951583aeU, 0xc1fea8ddU); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xfea45e3cU, 0xa5ea1508U, 0xbf5af8e9U, 0xa88c1ae9U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xbac7f318U, 0xf06f6eadU, 0x2156fa4dU, 0xdf9eb4e0U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[1]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[2]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000024U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40070010U); + WR1_PROG(REG_1824H, 0x0a008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83t.c new file mode 100644 index 000000000..dc242cdc6 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83t.c @@ -0,0 +1,38 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes192GcmEncryptUpdateTransitionSub (void) +{ + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000030U); + WR1_PROG(REG_1824H, 0x07008c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83u.c new file mode 100644 index 000000000..10fbcd4d6 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p83u.c @@ -0,0 +1,63 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes192GcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x85a2fcf4U, 0x4d857859U, 0xd5ae377fU, 0xe12bc3d7U); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40020030U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[0]); + + HW_SCE_p_func100(0x70a6cae8U, 0xfe3c55a7U, 0x724436d8U, 0x7df499fbU); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40028030U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func202(); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00028000U); + WR1_PROG(REG_1824H, 0x08008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func101(0x0ab0cae0U, 0x4c418484U, 0x6b467c14U, 0xf55f177dU); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85a.c new file mode 100644 index 000000000..eb1766e30 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85a.c @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes192GcmDecryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008006U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataA[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + HW_SCE_p_func101(0x948d33ecU, 0x287acf7cU, 0xaef93ad5U, 0xccf604a0U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85f.c new file mode 100644 index 000000000..cd6787d85 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85f.c @@ -0,0 +1,247 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes192GcmDecryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_DataALen[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x80020100U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b580U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007FU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b5a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0xFFFFFF00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0c0029a9U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x04a02988U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataTLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x34202beaU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xf2d5caeaU, 0xa95a8e2eU, 0x38631688U, 0xf8f091feU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x9e7eecabU, 0xcff542d8U, 0xc6b4f0c2U, 0xe3dcca93U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003409U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00036800U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x08008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x584722dcU, 0x09f345fbU, 0x5371b07aU, 0xa9edfc74U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func100(0xa474b93cU, 0x2023d9b5U, 0x1df27035U, 0x23482c09U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40018030U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + HW_SCE_p_func101(0xcf856c9aU, 0xcf5f6b6aU, 0x841b155aU, 0x8a4b85c1U); + } + + WR1_PROG(REG_1444H, 0x000001c1U); + WR1_PROG(REG_182CH, 0x00018000U); + WR1_PROG(REG_1824H, 0x0a008005U); + WAIT_STS(REG_1444H, 31, 1); + WR2_ADDR(REG_1420H, &InData_DataALen[0]); + + WR1_PROG(REG_1608H, 0x81020100U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_182CH, 0x00400000U); + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_182CH, 0x40000030U); + WR1_PROG(REG_1824H, 0x07008d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002beaU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000055U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataT[0]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1824H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x2396ecc0U, 0x46860decU, 0x1ecc1d95U, 0xb9834e89U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x228d120cU, 0xfa8fb72eU, 0xabd4f72dU, 0x15c7ff79U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_p_func102(0x3adf254bU, 0xf1d8e7b1U, 0x09e369a4U, 0x3431286cU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85i.c new file mode 100644 index 000000000..2112ed9dd --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85i.c @@ -0,0 +1,152 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes192GcmDecryptInitSub (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00850001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000085U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x363656d3U, 0x2cdb129cU, 0xda1c10c4U, 0x44b1013dU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000085U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x941519ecU, 0x28844452U, 0xa8d3a243U, 0xa538cf82U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1608H, 0x80080000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x77f313a0U, 0xc7d41f3eU, 0x8452656cU, 0x81da047fU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x7ccc082dU, 0xb1684a21U, 0x2673d7c6U, 0xdfe9fbc9U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x42152549U, 0x3aa0e973U, 0x2d18ac66U, 0x7a587c79U); + WR1_PROG(REG_1608H, 0x81080000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x3608b489U, 0xac04a021U, 0x2b3a23b4U, 0xac85a3fcU); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[1]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[2]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_IV[3]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000024U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40070010U); + WR1_PROG(REG_1824H, 0x0a008004U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85t.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85t.c new file mode 100644 index 000000000..800d03089 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85t.c @@ -0,0 +1,38 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes192GcmDecryptUpdateTransitionSub (void) +{ + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000030U); + WR1_PROG(REG_1824H, 0x07008c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85u.c new file mode 100644 index 000000000..d78592104 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p85u.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes192GcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x45dc191bU, 0x87b71836U, 0xc1e09c9dU, 0x37a11a8dU); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40018030U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + + HW_SCE_p_func202(); + + HW_SCE_p_func101(0x842ef562U, 0x93104d9eU, 0x4e69bfceU, 0x7119083fU); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87f.c new file mode 100644 index 000000000..28cee107b --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87f.c @@ -0,0 +1,249 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes192CmacFinalSub (const uint32_t InData_Cmd[], + const uint32_t InData_Text[], + const uint32_t InData_DataT[], + const uint32_t InData_DataTLen[], + uint32_t OutData_DataT[]) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x66be57d7U, 0xb77cca83U, 0xb4141efeU, 0xd53e8e37U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x5daac97fU, 0x02950695U, 0xf71fbe9fU, 0x6e049669U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000002U)) + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x4a008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func101(0xc918b3c1U, 0x48a11686U, 0x6762c0c1U, 0xb5c442d4U); + } + else + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x5a008104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func101(0x44b859eeU, 0x3a095d51U, 0x716b9713U, 0x6ccd6203U); + } + + WR1_PROG(REG_1824H, 0x0c000045U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + if ((InData_Cmd[0] == 0x00000000U) || (InData_Cmd[0] == 0x00000001U)) + { + HW_SCE_p_func100(0xede50bdbU, 0x93d4269cU, 0x37363131U, 0xba9c2632U); + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0e008505U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_DataT[0]); + + HW_SCE_p_func102(0xfbce1a04U, 0x51148e36U, 0x92e9abd8U, 0xa590b94cU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010040U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataTLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a840U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x34202862U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xb326af84U, 0x8d3ff170U, 0xafde495aU, 0x531bdb96U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x520dee03U, 0xe1b712f0U, 0x9aeebe49U, 0x231075eeU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0e008505U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e2U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000568e7U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00026ce7U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003827U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b4c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003402U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000028c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008cc0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00004406U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00007421U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00007821U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003c27U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000034c2U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000a4c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000568c6U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000034e6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00026ce7U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 4U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3420a8e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10003c27U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x1000a4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x9c000005U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_DataT[0]); + + HW_SCE_p_func100(0xf9f0d3b1U, 0xcd660a5eU, 0x68e01d67U, 0xe2794294U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xeb0108b1U, 0x8bbff7c4U, 0x58090e47U, 0x91bd1b8fU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_AUTHENTICATION; + } + else + { + HW_SCE_p_func102(0x4b5024d2U, 0x45c98896U, 0x1d6ecc98U, 0x8d3bbc05U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87i.c new file mode 100644 index 000000000..47a96df08 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87i.c @@ -0,0 +1,122 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes192CmacInitSub (const uint32_t InData_KeyIndex[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00870001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000087U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xa48897d0U, 0xe1cd729aU, 0xe4009a4aU, 0x556dc284U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000087U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x82c1ae2bU, 0x8a73a8c8U, 0x4a6db0e4U, 0x67aecfabU); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x05c444d0U, 0xb938e8fcU, 0x302d578dU, 0x94ad284dU); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xb6f3c2d8U, 0x84dde31aU, 0x3249cbb3U, 0x6c668fdaU); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xf6aef608U, 0xd7855c26U, 0x0dda7c4aU, 0x18b63c4fU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xc7b75225U, 0xa3abe2e4U, 0x3ed3b9ffU, 0x41e2884aU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87u.c new file mode 100644 index 000000000..aa8700e6d --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p87u.c @@ -0,0 +1,42 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes192CmacUpdateSub (const uint32_t InData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0e008406U); + + for (iLoop = 0U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + HW_SCE_p_func101(0x90128629U, 0x406ebc9fU, 0x4f4b9978U, 0xfbd0afe1U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89f.c new file mode 100644 index 000000000..ab4a6a149 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89f.c @@ -0,0 +1,56 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub (void) +{ + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func101(0x3fc2a091U, 0xa58443b0U, 0x3453d34aU, 0x7c364da4U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func101(0xf629e0d0U, 0x4f88a95aU, 0x464333d5U, 0x9587ea79U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + HW_SCE_p_func101(0xd44edda9U, 0x77a3dd8cU, 0x4d7bfe12U, 0x04cd1a24U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + HW_SCE_p_func101(0x156c06cdU, 0x9dce9f3eU, 0xdeac5c7eU, 0x39e25debU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + HW_SCE_p_func101(0x1c3627d0U, 0x9e52f952U, 0xd84eaeeaU, 0x9239b06dU); + } + else + { + ; + } + + HW_SCE_p_func102(0x19bdc039U, 0xfb31d0d7U, 0xed8525d6U, 0x6d927bd2U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89i.c new file mode 100644 index 000000000..ad4120890 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89i.c @@ -0,0 +1,185 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub (const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00890001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000089U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xf14e00a3U, 0x203b8b78U, 0x148c5f9aU, 0xd44d4816U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000089U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x1c0dd126U, 0xc79b5e85U, 0x62cbee5dU, 0xc6d79c18U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xf2dfd8dbU, 0x14924ad8U, 0xde27abb3U, 0x0e967146U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x1fde489bU, 0x2adfa882U, 0xb5fd23e9U, 0x3dcc4a4fU); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x5d906894U, 0xcdf6df19U, 0x7bf941caU, 0xaa9c5d4eU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xa77c1e32U, 0xa3568223U, 0xd62729cbU, 0xe54979ccU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1444H, 0x000000c7U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3000a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0xdd28d020U, 0xb86c6029U, 0xaaa83a0fU, 0xfd64e31bU); + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func101(0x12677c0bU, 0x836cde26U, 0x320254e3U, 0x5e002c96U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func101(0x8352fb29U, 0x4416a550U, 0xc3c465bcU, 0x3fb7e2b5U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + HW_SCE_p_func101(0x59db0670U, 0x254d6a45U, 0x25aee0beU, 0xd864ca6eU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + HW_SCE_p_func101(0xfc761030U, 0xb82dbd88U, 0x973c6165U, 0x173ca485U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + HW_SCE_p_func101(0x1ea4a4d5U, 0xd72adfc4U, 0x04dee08aU, 0xb6ca7b9cU); + } + else + { + ; + } + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89u.c new file mode 100644 index 000000000..81441efec --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p89u.c @@ -0,0 +1,137 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes192EncryptDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], + const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + HW_SCE_p_func100(0x7f928370U, 0xaa486c0aU, 0x4e8f5fe7U, 0x6171b8b4U); + + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0a008106U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + HW_SCE_p_func100(0xcc66d49aU, 0x9acbaa84U, 0x4cf367f8U, 0x34270eccU); + + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0a00810eU); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + HW_SCE_p_func100(0xe05f0c6aU, 0xc134cd35U, 0x8e587a55U, 0xcdb81fb1U); + + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0e008506U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + HW_SCE_p_func100(0x8407e485U, 0xf9751c03U, 0x694deeb4U, 0x6fbe56a6U); + + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0900890eU); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + WR1_PROG(REG_1444H, 0x000003c2U); + HW_SCE_p_func100(0x83e882d3U, 0x1c9dda4aU, 0x8c43c698U, 0xf60f3092U); + + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + } + else + { + ; + } + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func214(); + + HW_SCE_p_func101(0x24247570U, 0xb24cbc7dU, 0x409c2091U, 0xd5962a9eU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func214(); + + HW_SCE_p_func101(0x8bcb030cU, 0xfe165fedU, 0xe1b21f39U, 0xf291783fU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + HW_SCE_p_func214(); + + HW_SCE_p_func101(0x094c1352U, 0x27fc39d7U, 0x0b1cfbfeU, 0x694a734fU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000003U) + { + HW_SCE_p_func214(); + + HW_SCE_p_func101(0xf0408e8eU, 0xf8249f96U, 0x418f0479U, 0x485cc893U); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000004U) + { + HW_SCE_p_func214(); + + HW_SCE_p_func101(0xadad7da5U, 0x03181adbU, 0xd2c507abU, 0x747dee88U); + } + else + { + ; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95f.c new file mode 100644 index 000000000..9324ee105 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95f.c @@ -0,0 +1,132 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128CcmEncryptFinalSub (const uint32_t InData_Text[], uint32_t OutData_Text[], + uint32_t OutData_MAC[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1600H, 0x00003409U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0xb2c8d267U, 0x517f7ccaU, 0xecaffe5cU, 0xe43e03b7U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0xe7000d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + HW_SCE_p_func100(0x911400ceU, 0x33b379e8U, 0x0ea93c0fU, 0x7c91edfbU); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + HW_SCE_p_func101(0xe786b42bU, 0xfe29ba28U, 0x379a9912U, 0x2b6e625eU); + } + else + { + HW_SCE_p_func101(0x83507393U, 0x4c4a36fcU, 0xcf7afedeU, 0xc69d4400U); + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func100(0x5511abefU, 0xda819ca3U, 0xe7271e35U, 0x2d44fb05U); + WR1_PROG(REG_1824H, 0x09100105U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_MAC[0]); + + HW_SCE_p_func102(0x0be57111U, 0xfcf8af02U, 0x5c4e41adU, 0xc3763781U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95i.c new file mode 100644 index 000000000..074b51f4f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95i.c @@ -0,0 +1,483 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128CcmEncryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + const uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00950001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003640U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010120U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xcce3d5daU, 0x7263ebddU, 0x78348d7bU, 0x4243c26fU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x3420a920U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00004101U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func101(0x6b8f3652U, 0x13e294e9U, 0xf98d52d8U, 0x446d6857U); + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x3176fbe0U, 0xe796c497U, 0x4acc5defU, 0x446047c4U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xf7d12600U, 0xd26bd1ddU, 0xcf63c462U, 0x4842b854U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x5b4ff64fU, 0xc4982f5bU, 0x4aa2b616U, 0xf9e33c54U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x6535439bU, 0xadb90e16U, 0x1e48cadcU, 0x0b555965U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000095U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x202b6f86U, 0x15b2f897U, 0x741b82f8U, 0xcdcc6e98U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xac87cfa6U, 0x5f41e750U, 0x1e06d53cU, 0x744bddb0U); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000095U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x43bfffc8U, 0xcb4fd517U, 0x81d5f18cU, 0xb12a2e44U); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2a46c04bU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x089e8dbeU, 0xf912b5d4U, 0x16ead5cdU, 0xe1410e56U); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000095U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xab1950e7U, 0x7dd6710cU, 0x0f8a7c37U, 0xfcc92a7aU); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xe546d9a6U, 0x63c61cc5U, 0xc1b98c0cU, 0x59c8628fU); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0xb2314b73U, 0x083c3953U, 0x2514299bU, 0xb516a548U); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c21U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x41840b85U, 0x89d72108U, 0x8536bc36U, 0xff952fb2U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000036a0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b6c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x4cc18a1aU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000095U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xce27a41aU, 0x08777c5eU, 0x04719e5fU, 0x30216a31U); + HW_SCE_p_func092(); + + HW_SCE_p_func101(0x70cba9e5U, 0x0241f10aU, 0x10b08b3cU, 0xd994a19cU); + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000dfU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x9cf6a453U, 0x16386708U, 0xf296b018U, 0x167c9839U); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x6ad6575eU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000ebU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xe9330368U, 0xc030281eU, 0x7ef78ae8U, 0x62378b0eU); + HW_SCE_p_func044(); + + HW_SCE_p_func101(0xfbf11408U, 0x717315e5U, 0xbb700056U, 0xda1062d6U); + } + + HW_SCE_p_func100(0x868b306cU, 0x3c61eaa0U, 0x4acfa9f9U, 0xc3d97dfbU); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0xf532253fU, 0x51d61c48U, 0x65defbddU, 0xbb4fe824U); + } + + HW_SCE_p_func100(0x336cbb6dU, 0x23294fb5U, 0xca772c88U, 0x8bef780eU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x7f8a90c6U, 0x30115eabU, 0x5e107297U, 0xed681289U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003412U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xd27b4cebU, 0x6db03e44U, 0xd9952c9bU, 0xdccf84c2U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000145U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0xf8000006U); + + for (iLoop = 0U; iLoop < Header_Len; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Header[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + HW_SCE_p_func101(0x575a523dU, 0x95befc80U, 0xb9126ef9U, 0xbdfcc3d0U); + } + else + { + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x800201c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_SeqNum[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_SeqNum[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000008aeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000008cfU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x01986c64U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01986c85U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01986ca6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00186cc6U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1824H, 0x08000145U); + WR1_PROG(REG_1608H, 0x81040060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1600H, 0x0000b540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + HW_SCE_p_func031(InData_Header); + + HW_SCE_p_func101(0xa9bf5748U, 0x874ac031U, 0xc35100dfU, 0x52b9b7dfU); + } + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95u.c new file mode 100644 index 000000000..732ed0cd7 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p95u.c @@ -0,0 +1,51 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128CcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x8a129773U, 0x0113efdfU, 0x49b2c662U, 0xb30a21d3U); + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_1824H, 0xe7000d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + HW_SCE_p_func215(); + + HW_SCE_p_func101(0x907dedefU, 0xbe3f64dcU, 0xfa703911U, 0x11445ec9U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98f.c new file mode 100644 index 000000000..212505b2d --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98f.c @@ -0,0 +1,234 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128CcmDecryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_MAC[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x34202beaU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x9bf5d656U, 0x2b520507U, 0x34d84488U, 0x62481fbaU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x42526949U, 0x5064f863U, 0xac99e1dcU, 0x97acceb9U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003409U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x122828f4U, 0x6d02b3e8U, 0x08fa2bd7U, 0x45e4f8f6U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x07000d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + HW_SCE_p_func100(0x960082e9U, 0x9ed561d4U, 0x401cd86fU, 0xa0158186U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + WR1_PROG(REG_1824H, 0x0e100405U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0x14f351ebU, 0xf290d80bU, 0x749de29cU, 0x87246bc3U); + } + else + { + HW_SCE_p_func101(0x5d3756b2U, 0x9ea604acU, 0x3edb4fc1U, 0x06564046U); + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c100104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1824H, 0x07200d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002beaU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000055U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MAC[0]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1824H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0xbe219e40U, 0x61d4e73fU, 0x36acc95cU, 0xcda20a02U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x2a9a1fb2U, 0xbc912f20U, 0xee917904U, 0xda21a9f6U); + + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0x315e9d2bU, 0xe00aef51U, 0xdf32117aU, 0x4f5e2b2fU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98i.c new file mode 100644 index 000000000..0dcaf683d --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98i.c @@ -0,0 +1,508 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128CcmDecryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_DataType[], + const uint32_t InData_Cmd[], + const uint32_t InData_TextLen[], + const uint32_t InData_MACLength[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t InData_SeqNum[], + const uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00980001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003640U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010120U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003689U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x895c92b4U, 0xb172ed9bU, 0xc9931c48U, 0x4131d19eU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MACLength[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xdfdaf5a7U, 0x21cd0abaU, 0x7685c781U, 0x1f50d883U); + } + else + { + WR1_PROG(REG_1600H, 0x0000b540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a920U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00004101U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func101(0x066c6f3bU, 0xc82cc5e9U, 0xca0ffc71U, 0x981f65bbU); + } + + WR1_PROG(REG_1600H, 0x0000366aU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xf5a5f0c2U, 0xfb80f1e7U, 0x1eb3b84aU, 0xf7f23ec7U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xa7d3d8e9U, 0xbdbb5ca9U, 0xf554388cU, 0x6cbdcaa4U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xd7a396b0U, 0x4ba265c9U, 0xb2410861U, 0xb69ec622U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xd15ae930U, 0x9cab87a5U, 0x07acd3e8U, 0x02a4a296U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000098U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x78137d2fU, 0x3cff59deU, 0x21b038f2U, 0x66464ea6U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x679f2fffU, 0xb0840152U, 0x27baa956U, 0xb823077eU); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000098U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x798697c6U, 0x18441b11U, 0xdb88ed2dU, 0x5e65e035U); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2a46c04bU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x352d828cU, 0xcdd74883U, 0x4bc05a3dU, 0x4e3dd827U); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000098U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xf02bfb28U, 0x08c5790dU, 0x22ddf482U, 0xbaa94f09U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x5d7e2f5bU, 0x115a9eb2U, 0x24ffda95U, 0xb7bbc8adU); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0x0302ae4eU, 0x07a093adU, 0x8948722bU, 0x91307b75U); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_DataType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c21U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x1df82688U, 0x94e7ccbeU, 0x61742becU, 0x7cb96874U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000036a0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b6c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x8026ee7fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000098U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x4443987bU, 0x78cb2bfeU, 0x56e74fddU, 0x74dc843dU); + HW_SCE_p_func092(); + + HW_SCE_p_func101(0xc627f0e0U, 0x6523cf8cU, 0x5c7e8dcdU, 0x3c20d197U); + } + else + { + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000003U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x2a7ce433U, 0x9aa4cfd0U, 0xf719afcbU, 0x2ccc6180U); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x98bae316U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000ccU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x1c6c94a9U, 0xfdb30059U, 0x942359c1U, 0x9fc771b6U); + HW_SCE_p_func044(); + + HW_SCE_p_func101(0xc0de8b40U, 0xa83aad6bU, 0xcdfb2420U, 0xfe26f9d7U); + } + + HW_SCE_p_func100(0xb599fe6eU, 0xdb680de0U, 0x2d9b6f5dU, 0x22089984U); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1608H, 0x80040080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0xdff9a5e7U, 0x4ec735b6U, 0xcb48b076U, 0xa7e3b04aU); + } + + HW_SCE_p_func100(0x86f965c6U, 0xa3ce271fU, 0xb7fd1ff5U, 0x43dae454U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x5b7203a3U, 0xb4a47420U, 0x3fbc29e1U, 0x026d3895U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00003534U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003553U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003412U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xf2eeab2eU, 0x4b61ae25U, 0xd964018bU, 0x81979456U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000145U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_1824H, 0xf8000006U); + + for (iLoop = 0U; iLoop < Header_Len; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Header[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + HW_SCE_p_func101(0xe18d6f6dU, 0xb3246c6fU, 0x728bd90aU, 0x3e08a01fU); + } + else + { + WR1_PROG(REG_1444H, 0x000001c7U); + WR1_PROG(REG_1608H, 0x800201c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_SeqNum[0]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_SeqNum[1]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000008aeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000008cfU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b460U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x01986c64U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01986c85U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x01986ca6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00186cc6U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1824H, 0x08000145U); + WR1_PROG(REG_1608H, 0x81040060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func031(InData_Header); + + HW_SCE_p_func101(0xcbb26a03U, 0x9ea71d6aU, 0x8a910aefU, 0x3e8ad20cU); + } + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98u.c new file mode 100644 index 000000000..c9f6e85af --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p98u.c @@ -0,0 +1,51 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128CcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x602a878aU, 0xfe5e4e37U, 0x134f8381U, 0xe8641febU); + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_1824H, 0xf7000d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + HW_SCE_p_func215(); + + HW_SCE_p_func101(0xc6f4fac0U, 0x287bc8a9U, 0x09000831U, 0x0f511110U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9a.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9a.c new file mode 100644 index 000000000..93ec6b0b3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9a.c @@ -0,0 +1,413 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSub (const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_PubKey[], + uint32_t OutData_R[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x009a0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010380U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x00000fc7U); + WR1_PROG(REG_1608H, 0x8090001eU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_PubKey[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + } + + for (iLoop = 0U; iLoop < 2U; iLoop++) + { + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000d3e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000381eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000381eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000037beU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000a7a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000383dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38001001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000fffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000a7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x30000f5aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000d3e1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000f9cU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3e1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x5aa4bbf8U, 0xbc0b49d0U, 0xc9084846U, 0x540a8890U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xfdcb5f0fU, 0x3aed7143U, 0x90da5e43U, 0xfe7c7f76U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000009aU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xa5a8873bU, 0xb0326e70U, 0x4649c07bU, 0x35ed2382U); + HW_SCE_p_func043(); + + HW_SCE_p_func074(); + + WR1_PROG(REG_1600H, 0x000034feU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000009aU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x5320325fU, 0x035dde1eU, 0xbbab2420U, 0x79dcd198U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + for (iLoop = 0U; iLoop < 8U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1404H, 0x13200000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xc23ed2bcU, 0xff59eec6U, 0x6a419ba8U, 0x19356bc3U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x6fd0922dU, 0xc44bc19bU, 0x0fafc087U, 0x155743e0U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0xd7ce3dbaU, 0xd8cdae97U, 0x4ea069abU, 0xefa35814U); + WR1_PROG(REG_1600H, 0x30003340U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000002F8U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000001C0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000C8U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000110U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + HW_SCE_p_func100(0x484b97acU, 0x84661bafU, 0xd9c2cf27U, 0xa0615ae1U); + HW_SCE_p_func070(OFS_ADR); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8190001eU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func008(); + + HW_SCE_p_func100(0xfb40fe8eU, 0xc1abe4e4U, 0xbf2d2b44U, 0xe45250f1U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x998644d8U, 0x02b33d50U, 0x679dfd13U, 0x097f8691U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1400H, 0x00c00021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000228U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000009aU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x09ea783cU, 0x5fd0bfa8U, 0xfa70fe5dU, 0x697a11acU); + HW_SCE_p_func088(); + + HW_SCE_p_func100(0xed8515b2U, 0x722a7d11U, 0x3652fd90U, 0x1006f47dU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x8b6e3aeeU, 0xa4314376U, 0x0b4461d4U, 0x42669883U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xf1952344U, 0x13725da0U, 0xa9539708U, 0x6ca2f264U); + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[0]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[4]); + + HW_SCE_p_func100(0xfee89de8U, 0x2d768e5cU, 0x6b741038U, 0x1f481647U); + WR1_PROG(REG_1404H, 0x12d00000U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[8]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[12]); + + HW_SCE_p_func102(0x769c2d07U, 0xe3660406U, 0x7943a021U, 0x892e160aU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9b.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9b.c new file mode 100644 index 000000000..4a33231a6 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9b.c @@ -0,0 +1,378 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSub (const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_PubKey[], + uint32_t OutData_R[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x009b0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000009bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x56f55492U, 0x7dc9cebeU, 0x41e32218U, 0xb745bc1bU); + HW_SCE_p_func043(); + + HW_SCE_p_func076(); + + WR1_PROG(REG_1600H, 0x000034feU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000009bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x7983bab9U, 0x37dfa862U, 0x1e789385U, 0xc4b22d2dU); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x00000bc2U); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1404H, 0x13100000U); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x4429aabfU, 0xfbb1aa79U, 0x84ab4cb0U, 0x23478b9aU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x60a676f4U, 0x444af909U, 0xbdaa020dU, 0xd356052eU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x8281dce6U, 0x43e6b7d8U, 0x4957da59U, 0x5163942fU); + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000017c7U); + WR1_PROG(REG_1608H, 0x8098001eU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 24U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_PubKey[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x38000f5aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000158U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000208U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + HW_SCE_p_func100(0x2963c4ceU, 0x1f3d2ef2U, 0xccd4a8d9U, 0x59810c83U); + HW_SCE_p_func027(OFS_ADR); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8198001eU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1400H, 0x00c90031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1400H, 0x00c90031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x06060001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000890U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x06060005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000008e0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x06060005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x06060001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x9bcde72fU, 0x56fbe2c3U, 0x705cc74eU, 0xfc28836fU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x3529bdd1U, 0x672059d3U, 0x797ddd1fU, 0x3ba97de4U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1400H, 0x00c00031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000218U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001e0U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000009bU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x3e0f5752U, 0x7274363fU, 0xedbc2f7eU, 0xedaa8358U); + HW_SCE_p_func089(); + + HW_SCE_p_func100(0x1e2d13e1U, 0xc893d908U, 0xda19b2a2U, 0x9e3f2821U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x76a8148dU, 0xce5b9dc9U, 0x9d56c5b0U, 0xeca4a0ddU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x1b6f5168U, 0x884c2065U, 0x47e94d03U, 0xae8a2949U); + WR1_PROG(REG_1404H, 0x12700000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[0]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[4]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[8]); + + HW_SCE_p_func100(0x229e74feU, 0x5bd396b1U, 0xe1d19990U, 0xdfb3a3acU); + WR1_PROG(REG_1404H, 0x12c00000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[12]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[16]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[20]); + + HW_SCE_p_func102(0xa61a9a8fU, 0xa5f0fb01U, 0xe15d9c29U, 0x97ec30d9U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9c.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9c.c new file mode 100644 index 000000000..5dbfd71ef --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_p9c.c @@ -0,0 +1,380 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Ecc512ScalarMultiplicationSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_PubKey[], + uint32_t OutData_R[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x009c0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000009cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xda368b45U, 0xf52a4b70U, 0x8099d3d9U, 0x6a980112U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000021U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000009cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x3e0b13b3U, 0x28c41d56U, 0x5ad054bdU, 0xb0fc1228U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x40000300U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + WR1_PROG(REG_1404H, 0x13000000U); + + for (iLoop = 0U; iLoop < 16U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 5]); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 8U; + } + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x7edc919dU, 0xca6f5b7eU, 0x56ceac96U, 0xcd52bd3eU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x9f733c98U, 0x34a821cfU, 0xed647778U, 0xd3cbe9deU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x5a771ffeU, 0xa06e199cU, 0x9ff1acbaU, 0x7e2630b9U); + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x00001fc7U); + WR1_PROG(REG_1608H, 0x80a0001eU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 32U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_PubKey[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000270U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + HW_SCE_p_func100(0xf168cfabU, 0x94e6ec29U, 0x6f4f7719U, 0xa0798b7cU); + HW_SCE_p_func078(OFS_ADR); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x08080010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81a0001eU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1400H, 0x00c90041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11200000U); + WR1_PROG(REG_1400H, 0x00c90041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x08080001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000890U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x08080005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x08080002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000008e0U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x08080005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x08080001U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0808000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xa9b35604U, 0x4ba20032U, 0xc414fdf1U, 0xdeb8ebddU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x57dabd43U, 0xd59eed2dU, 0xb42c0115U, 0x29f46f1bU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1404H, 0x10d00000U); + WR1_PROG(REG_1400H, 0x00c00041U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000208U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001c0U); + + WR1_PROG(REG_1004H, 0x08080009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x0000009cU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x94dd00c0U, 0x85056105U, 0x556ef1c5U, 0x6f58b5a3U); + HW_SCE_p_func090(); + + HW_SCE_p_func100(0x965a70feU, 0xae3a771dU, 0xafeed9a0U, 0x456adf9eU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xf12db6b7U, 0x7b574a86U, 0xcfcc8341U, 0x80976db9U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x04add3cbU, 0x9b153c65U, 0x1056f9e5U, 0xbd220eadU); + WR1_PROG(REG_1404H, 0x12600000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[0]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[4]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[8]); + + HW_SCE_p_func100(0xb539bd18U, 0xd01c4558U, 0x1f071b61U, 0x1d32f4fcU); + WR1_PROG(REG_1A24H, 0x08000105U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[12]); + + HW_SCE_p_func100(0xf49fd387U, 0x798012bcU, 0xc55ec0a0U, 0xd30f6c74U); + WR1_PROG(REG_1404H, 0x12b00000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[16]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[20]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[24]); + + HW_SCE_p_func100(0xcee76b9eU, 0xcacb554aU, 0x7dfcd2a2U, 0x7118a373U); + WR1_PROG(REG_1A24H, 0x08000105U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_R[28]); + + HW_SCE_p_func102(0xb55902bcU, 0x93ad6bc3U, 0x7e5071dcU, 0x9d210b20U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1f.c new file mode 100644 index 000000000..ba451dcbb --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1f.c @@ -0,0 +1,140 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256CcmEncryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + uint32_t OutData_Text[], + uint32_t OutData_MAC[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x43314394U, 0xe1a714eeU, 0x57dc0f43U, 0xe774c926U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0xe7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + HW_SCE_p_func100(0x127f4232U, 0x0f93d127U, 0x4d82c79aU, 0xcffaab88U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + HW_SCE_p_func101(0x407b0301U, 0x744a4ef1U, 0xab373766U, 0x2861d46dU); + } + else + { + HW_SCE_p_func101(0x013cda64U, 0x39f84f0cU, 0x3ec60defU, 0x9cb9827dU); + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func100(0x02cb3ee4U, 0xe638aaf9U, 0xe11aff99U, 0x7050decdU); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_MAC[0]); + + HW_SCE_p_func102(0xa978a0e1U, 0x2d98c3c2U, 0xe829a86aU, 0x8463f308U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1i.c new file mode 100644 index 000000000..ed671fd76 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1i.c @@ -0,0 +1,231 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256CcmEncryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00a10001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x30f79cefU, 0xb92b4426U, 0xb04efc1dU, 0x914e47b7U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x50cfd29cU, 0xc632df1bU, 0x0a774737U, 0xd4b07d7eU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x529b74beU, 0x7ea3d6bbU, 0x45036679U, 0x1d566e2eU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000a1U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x59e63b7fU, 0x7c65c976U, 0xe1b58568U, 0xa2d856ceU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xd9b3bc2bU, 0xd3956d18U, 0x4360ce5aU, 0x9248c198U); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000041U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x12083853U, 0x1d926552U, 0x9794e252U, 0x6c880176U); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x85d04999U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x1f77a5e2U, 0xedf30d91U, 0x93fb0c9bU, 0xd01870a7U); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000a1U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x4077f4cdU, 0x59179728U, 0xd8ece703U, 0x08ad7e74U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x924e4ca3U, 0xf82af642U, 0x2df9aa0cU, 0x1f4f90cfU); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xd674db57U, 0xb0778208U, 0xb7e130fcU, 0x3602aba0U); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xd084a795U, 0xaf9776ecU, 0xa69028a8U, 0xe73c23b7U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xc1eefc88U, 0x539bb343U, 0xbf0e281eU, 0x2bc00116U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000145U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e108406U); + + for (iLoop = 0U; iLoop < Header_Len; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Header[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1u.c new file mode 100644 index 000000000..b92265d1e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa1u.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256CcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x5e68f2b7U, 0xf708b742U, 0x56e61b79U, 0x6a56fc3aU); + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0xe7008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + HW_SCE_p_func215(); + + HW_SCE_p_func101(0xa7c575e2U, 0x4c48b249U, 0xd229ebd3U, 0xd96bccabU); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4f.c new file mode 100644 index 000000000..1eb91a972 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4f.c @@ -0,0 +1,249 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256CcmDecryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_MAC[], + const uint32_t InData_MACLength[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MACLength[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x34202beaU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x96010a66U, 0x66d60c3fU, 0x210dceffU, 0xd4ca098aU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xc90ddef0U, 0xac7a0e9bU, 0x6cd96516U, 0x2047f5e1U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x807835ceU, 0x16dbb5deU, 0x086fd360U, 0xdadc74bcU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + HW_SCE_p_func100(0xf4eb2b33U, 0x1b3fe838U, 0xa1fa334aU, 0xb22bb424U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e108405U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0xa56a96f2U, 0x0a2bdaf3U, 0x8ed58a18U, 0xf4b6f120U); + } + else + { + HW_SCE_p_func101(0x2f780300U, 0x37d566c8U, 0xa29c2518U, 0x0be83819U); + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c100104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x07208d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002beaU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000055U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MAC[0]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1824H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x7cc27054U, 0x7a04b9a7U, 0xf4a3d8dbU, 0xc654031cU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xf6c6067dU, 0xc0442ddaU, 0xde54f441U, 0xd9514aa9U); + + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0x5b2f94e0U, 0x1db1d69aU, 0x7fe2e974U, 0xe9e9eae9U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4i.c new file mode 100644 index 000000000..8e42dc809 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4i.c @@ -0,0 +1,231 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256CcmDecryptInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00a40001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xed97275dU, 0xac49b932U, 0xfdd617adU, 0x84c0fd7cU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x93f751b3U, 0x4fd3cba9U, 0x67fa2c0fU, 0xd9f7aa63U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x3f7dc3caU, 0x7e47557aU, 0x3c0f6441U, 0x9a7469a5U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000a4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xdc225078U, 0x2507f149U, 0x87fbbb69U, 0x81af3feeU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xf4b13558U, 0x4da2ccffU, 0x4e55d48dU, 0xf5e890bbU); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000a4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x0a89acd1U, 0x3730925aU, 0x797a0346U, 0x21dfbe54U); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x85d04999U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xfa7f40efU, 0xde9386aeU, 0x0f4aa682U, 0xb056c1a8U); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000a4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xedd1226dU, 0xe89673afU, 0xebd25f11U, 0xdbb45f5dU); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x7e4f1290U, 0xb2700370U, 0x744997ccU, 0x50c0fd52U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x8da6185eU, 0xe4e7e256U, 0x7e2839caU, 0xfd5831a1U); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x3acd920dU, 0x22a58ad3U, 0x884aaa0cU, 0xbb736313U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xde25d67aU, 0x70d71d54U, 0x35eae998U, 0x0842d425U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000145U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0e108406U); + + for (iLoop = 0U; iLoop < Header_Len; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Header[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4u.c new file mode 100644 index 000000000..0c8a8bff8 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa4u.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256CcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x9dd43b1bU, 0xcf86f64cU, 0xfb459acdU, 0xc9a815b9U); + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0xf7008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + HW_SCE_p_func215(); + + HW_SCE_p_func101(0xc6299a49U, 0x6003f4e8U, 0x96b78399U, 0x3273fe18U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7f.c new file mode 100644 index 000000000..bdb0e063e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7f.c @@ -0,0 +1,140 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes192CcmEncryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + uint32_t OutData_Text[], + uint32_t OutData_MAC[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x11b0efbdU, 0x32a9ad80U, 0xbc2fb0beU, 0xe90e0ceeU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0xe7008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + HW_SCE_p_func100(0xb4fe4515U, 0xdf0a5d11U, 0x86585885U, 0x0205b12fU); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + HW_SCE_p_func101(0x6d482a8cU, 0x606b1407U, 0x06caf142U, 0x503dbcddU); + } + else + { + HW_SCE_p_func101(0xc65c2c4fU, 0x496cbfd8U, 0xecbdf466U, 0x7e778e4eU); + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func100(0xbd7164d7U, 0x0dcd0993U, 0x7e5caaf7U, 0x12b9c764U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_MAC[0]); + + HW_SCE_p_func102(0xb85eae9cU, 0x75671eb4U, 0x212d5fddU, 0x4c60e9f1U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7i.c new file mode 100644 index 000000000..2b95117de --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7i.c @@ -0,0 +1,155 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes192CcmEncryptInitSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00a70001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000a7U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xdf694422U, 0x881780f5U, 0xb473aee0U, 0xf91c7fefU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000a7U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x0e3521fbU, 0xaf4928a2U, 0x599fb2a7U, 0x3bb2d11fU); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x94b7e779U, 0xe3a4ed74U, 0x4490b221U, 0x487a6181U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x693a9b48U, 0x8e6cffc8U, 0xa369e021U, 0x6e069864U); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x6c53d2aaU, 0x166c502cU, 0xc3077b12U, 0x71809000U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xe76f3bc0U, 0x2f4d8789U, 0x2308bd82U, 0x91fbef1cU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000145U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0e108456U); + + for (iLoop = 0U; iLoop < Header_Len; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Header[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7u.c new file mode 100644 index 000000000..1878e91ea --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pa7u.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes192CcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x62908716U, 0xa135b7f2U, 0x421b0e69U, 0x39fa03dcU); + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0xe7008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + HW_SCE_p_func215(); + + HW_SCE_p_func101(0xb2156043U, 0xe7cec7d6U, 0x7ca84ed2U, 0x45ce4563U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0f.c new file mode 100644 index 000000000..66b68dbca --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0f.c @@ -0,0 +1,249 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes192CcmDecryptFinalSub (const uint32_t InData_Text[], + const uint32_t InData_TextLen[], + const uint32_t InData_MAC[], + const uint32_t InData_MACLength[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MACLength[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008940U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x34202beaU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x9126afbfU, 0x10353be1U, 0x98fb2bf9U, 0x7cce296aU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xca84b101U, 0xbc0aa93bU, 0x873cfa22U, 0x1dc110dbU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x39acbbd2U, 0x513975a3U, 0xa85db4e3U, 0x52679a20U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + HW_SCE_p_func100(0x4d01cbdcU, 0xb00d97f2U, 0x1647379aU, 0x8a804321U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[0]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[1]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[2]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[3]); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0e108405U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0xfa2a9a14U, 0x10ab7edfU, 0xac1eafdfU, 0x341c6e23U); + } + else + { + HW_SCE_p_func101(0x306db0cbU, 0xf6ce79bcU, 0x1a54f33dU, 0xeec7dc91U); + } + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c100104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x07208d05U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000a540U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002beaU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c3fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000055U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MAC[0]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1824H, 0x00000000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0xd8e1a306U, 0x8859a910U, 0x8ae58b3fU, 0x33c000acU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xe68453d3U, 0x64e494bbU, 0xeb4c701cU, 0x624844c8U); + + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0x66e71dbcU, 0x07c4fa33U, 0xb8449876U, 0xa1c54512U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0i.c new file mode 100644 index 000000000..fa54d0a4c --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0i.c @@ -0,0 +1,155 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes192CcmDecryptInitSub (const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[], + const uint32_t InData_Header[], + const uint32_t Header_Len) +{ + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00b00001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000b0U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x28c6e924U, 0xfff8df2cU, 0xb30e5d14U, 0x073e40f6U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000b0U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x3f8aa167U, 0x1b1745e1U, 0x53d69b9eU, 0x2d44e452U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xa91f0e2eU, 0xda1de2d7U, 0xf9ff6407U, 0xfa90bb3dU); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x6586c26cU, 0x5ce12267U, 0xb83d269bU, 0xca218b29U); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x3a9005d3U, 0x2291b8d0U, 0x5574b6ddU, 0x7439e09bU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xf4af7df1U, 0x5c2d0c80U, 0x89d300f5U, 0xfd6fdf07U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000145U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + WR1_PROG(REG_1824H, 0x08000065U); + WR1_PROG(REG_1400H, 0x00410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x07000c04U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x08000054U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0x0e108406U); + + for (iLoop = 0U; iLoop < Header_Len; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Header[iLoop]); + iLoop = iLoop + 4U; + } + + HW_SCE_p_func216(); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0u.c new file mode 100644 index 000000000..84d4bb514 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb0u.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes192CcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x8798079aU, 0x5a88663eU, 0x7d7eef52U, 0x9e59ce6bU); + WR1_PROG(REG_1444H, 0x00020061U); + + WR1_PROG(REG_182CH, 0x40000010U); + WR1_PROG(REG_1824H, 0xf7008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + HW_SCE_p_func215(); + + HW_SCE_p_func101(0x1004f6a0U, 0x38b0eed1U, 0x900cac63U, 0xf87f4468U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3f.c new file mode 100644 index 000000000..6e56ec599 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3f.c @@ -0,0 +1,364 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128XtsEncryptFinalSub (const uint32_t InData_TextBitLen[], + const uint32_t InData_Text[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextBitLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00076bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00026fdeU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00020020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000abc0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000fffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x6fec1e13U, 0xc28702a4U, 0x2427bdbaU, 0xd671c7daU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xf111ac52U, 0xf3285cbcU, 0x356d9413U, 0x53260bf0U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x9ea63d34U, 0x018fb463U, 0xb844b469U, 0x4e5a17b9U); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + HW_SCE_p_func100(0x543960c0U, 0x4e8062a7U, 0xe1092c3fU, 0x83327a95U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d008906U); + WR1_PROG(REG_1408H, 0x000c1000U); + + iLoop = 0; + if (S_RAM[0] >= 4) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < S_RAM[0]; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + } + + HW_SCE_p_func214(); + + WR1_PROG(REG_1600H, 0x38008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x58a07a22U, 0x9c501a0cU, 0xc3d2a8a3U, 0xfee20616U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d008905U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840006U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80840007U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 4]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 5]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 6]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 7]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003500U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00036908U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008d00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000cU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000024c8U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000024e8U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003826U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003847U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003460U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008c60U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0xffffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00004403U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00007484U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000c24U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00001484U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000c44U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00001041U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003c47U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000a7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002bdfU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00056bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000353eU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0xecc4e3d1U, 0xba13d146U, 0x8fde1755U, 0xc3522de6U); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + for (jLoop = 0U; jLoop < S_RAM[0]; jLoop++) + { + WR1_PROG(REG_1600H, 0x000024c5U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000024e5U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003ba6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003fa7U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000033c0U); + WR1_PROG(REG_1458H, 0x00000000U); + HW_SCE_p_func101(0xbc21da86U, 0x3dd1aa2cU, 0xb2ee018cU, 0xb75cbb99U); + } + + WR1_PROG(REG_1600H, 0x38000fdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x0490e73aU, 0xc1f99430U, 0xc97c9eb0U, 0x131ce324U); + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d008905U); + WR1_PROG(REG_1608H, 0x81840007U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000024c8U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003826U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000c24U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003c26U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + + for (jLoop = 0U; jLoop < S_RAM[0]; jLoop++) + { + WR1_PROG(REG_1600H, 0x000024c5U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003fe6U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003120U); + WR1_PROG(REG_1458H, 0x00000000U); + HW_SCE_p_func101(0xc3ff7336U, 0xd01aac90U, 0x671c420aU, 0xe8dfb675U); + } + + HW_SCE_p_func100(0x83175315U, 0x6d92d319U, 0x4d75cde3U, 0xead1bcedU); + WR1_PROG(REG_1600H, 0x38000d29U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840006U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 5]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 6]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 7]); + + HW_SCE_p_func101(0xb4cc9cbbU, 0x8d5589c4U, 0xdda87811U, 0xb2d2004fU); + } + + HW_SCE_p_func102(0xd7e3f1ffU, 0xa0323e93U, 0x502a9463U, 0x4118e101U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3i.c new file mode 100644 index 000000000..f379339e9 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3i.c @@ -0,0 +1,122 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128XtsEncryptInitSub (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00b30001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000b3U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xb4222e1eU, 0x7485e7aeU, 0x9933fa18U, 0x5bc82502U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000008U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000b3U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xfbe18f57U, 0xddb60dd1U, 0xede64390U, 0x186daf88U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xbd349f3bU, 0x0cbe6d3dU, 0xc4cd1d9bU, 0x7e823738U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xf2006497U, 0xfed6a5faU, 0x50abf552U, 0xc7e538f7U); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x5c0a3a0eU, 0x4417ab05U, 0xac9ef887U, 0xf2785edaU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xf44a877dU, 0x49251171U, 0xfc970526U, 0xc236c2bfU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x0a010045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3u.c new file mode 100644 index 000000000..51713d4b4 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb3u.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128XtsEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x880c271fU, 0x2e7a9c0cU, 0x4b1cdf44U, 0xee6a9296U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d008906U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + + HW_SCE_p_func214(); + + HW_SCE_p_func101(0x072909a7U, 0x3cc6274fU, 0x7aa3908aU, 0xdc3125c4U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6f.c new file mode 100644 index 000000000..379fdd8a1 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6f.c @@ -0,0 +1,390 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128XtsDecryptFinalSub (const uint32_t InData_TextBitLen[], + const uint32_t InData_Text[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextBitLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00076bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00026fdeU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00020020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000abc0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000fffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x8491871dU, 0x9cd10ab0U, 0x394371ecU, 0xd0d2a005U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x01257514U, 0x66e2e019U, 0xce4b458bU, 0xfff12702U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x1b0f5d99U, 0x5bda39d8U, 0x50726fe0U, 0x6759f009U); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + HW_SCE_p_func100(0x6a3b5347U, 0x85f48a10U, 0xc3ed1f6bU, 0xf099e893U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d00890eU); + WR1_PROG(REG_1408H, 0x000c1000U); + + iLoop = 0; + if (S_RAM[0] >= 4) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < S_RAM[0]; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + } + + HW_SCE_p_func214(); + + WR1_PROG(REG_1600H, 0x38008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x9756ba93U, 0x6f298de4U, 0xee949061U, 0x4e0cfac8U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func100(0x17d2f8cdU, 0x4a2f50ceU, 0x18a1ac1aU, 0xf5b729afU); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d00880cU); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d00890dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840006U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80840007U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 4]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 5]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 6]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 7]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003500U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00036908U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008d00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000cU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000024c8U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000024e8U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003826U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003847U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003460U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008c60U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0xffffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00004403U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00007484U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000c24U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00001484U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000c44U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00001041U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003c47U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000a7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002bdfU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00056bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000353eU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + for (jLoop = 0U; jLoop < S_RAM[0]; jLoop++) + { + WR1_PROG(REG_1600H, 0x000024c5U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000024e5U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003ba6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003fa7U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000033c0U); + WR1_PROG(REG_1458H, 0x00000000U); + HW_SCE_p_func101(0x219a89e9U, 0x00d9eee6U, 0x71e01a38U, 0xaf153bf3U); + } + + HW_SCE_p_func100(0xae4fd891U, 0x3ca24b17U, 0x5d287206U, 0x02569766U); + + WR1_PROG(REG_1600H, 0x38000fdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d00890dU); + WR1_PROG(REG_1608H, 0x81840007U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000024c8U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003826U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000c24U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003c26U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + + for (jLoop = 0U; jLoop < S_RAM[0]; jLoop++) + { + WR1_PROG(REG_1600H, 0x000024c5U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003fe6U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003120U); + WR1_PROG(REG_1458H, 0x00000000U); + HW_SCE_p_func101(0x3662b8d9U, 0xba810783U, 0x154c1531U, 0x1d793dcaU); + } + + HW_SCE_p_func100(0x9d410020U, 0xccf25039U, 0xa0c4eee4U, 0x6e1e3bbfU); + + WR1_PROG(REG_1600H, 0x38000d29U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840006U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 5]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 6]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 7]); + + HW_SCE_p_func101(0x9b2f328cU, 0x6932132aU, 0xe6e14221U, 0x83411541U); + } + + HW_SCE_p_func102(0xf2f1b573U, 0x0349cc0cU, 0x8e639e02U, 0xca2f5960U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6i.c new file mode 100644 index 000000000..801cf7c37 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6i.c @@ -0,0 +1,122 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128XtsDecryptInitSub (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00b60001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000b6U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xd664ea90U, 0x0f50a0a3U, 0x10c78349U, 0xcc2f349eU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000008U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000b6U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xe1817380U, 0x1700d850U, 0xdae22da2U, 0xa9622eefU); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xc0afcfb0U, 0xc4d28a69U, 0x504cd2edU, 0x2b223f63U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x0016e846U, 0x4170bba4U, 0xf7197312U, 0xa867a1afU); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xe4aaead9U, 0xac3a20d4U, 0x92669307U, 0x1aa0335cU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xafc84ec8U, 0x1adfd57fU, 0x8ed758f6U, 0x49e55282U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x0a010045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6u.c new file mode 100644 index 000000000..64500b9e8 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb6u.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128XtsDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x814e94aeU, 0xc512f08eU, 0xa3fadbeeU, 0xd4dbaedcU); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x0d00890eU); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + + HW_SCE_p_func214(); + + HW_SCE_p_func101(0xf42434beU, 0x94733dd3U, 0xaaaa5364U, 0x7775f26bU); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9f.c new file mode 100644 index 000000000..f29fc40af --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9f.c @@ -0,0 +1,364 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256XtsEncryptFinalSub (const uint32_t InData_TextBitLen[], + const uint32_t InData_Text[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextBitLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00076bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00026fdeU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00020020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000abc0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000fffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x81447098U, 0x89e36c58U, 0x825a2607U, 0xdf24e2c9U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x44c1c161U, 0x108d7934U, 0x083070a5U, 0x62171815U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xb423785eU, 0x8b8867e8U, 0x8819b49cU, 0xe0513489U); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + HW_SCE_p_func100(0x2794a9c7U, 0xab82d8feU, 0xc96ff224U, 0x0ee000b7U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d008906U); + WR1_PROG(REG_1408H, 0x000c1000U); + + iLoop = 0; + if (S_RAM[0] >= 4) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < S_RAM[0]; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + } + + HW_SCE_p_func214(); + + WR1_PROG(REG_1600H, 0x38008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x0dcda53eU, 0xe27d5418U, 0x6752fab9U, 0x02996b49U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d008905U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840006U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80840007U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 4]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 5]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 6]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 7]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003500U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00036908U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008d00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000cU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000024c8U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000024e8U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003826U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003847U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003460U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008c60U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0xffffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00004403U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00007484U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000c24U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00001484U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000c44U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00001041U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003c47U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000a7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002bdfU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00056bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000353eU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x811213f9U, 0x57b49d8bU, 0x6ae181a5U, 0xf61ff4c4U); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + for (jLoop = 0U; jLoop < S_RAM[0]; jLoop++) + { + WR1_PROG(REG_1600H, 0x000024c5U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000024e5U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003ba6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003fa7U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000033c0U); + WR1_PROG(REG_1458H, 0x00000000U); + HW_SCE_p_func101(0x98ea92b4U, 0x56c22a7dU, 0x154de3d4U, 0x04478e99U); + } + + WR1_PROG(REG_1600H, 0x38000fdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + HW_SCE_p_func100(0xa822b6f6U, 0xeb681d5fU, 0xd1d72a3fU, 0x8de346d8U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d008905U); + WR1_PROG(REG_1608H, 0x81840007U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000024c8U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003826U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000c24U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003c26U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + + for (jLoop = 0U; jLoop < S_RAM[0]; jLoop++) + { + WR1_PROG(REG_1600H, 0x000024c5U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003fe6U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003120U); + WR1_PROG(REG_1458H, 0x00000000U); + HW_SCE_p_func101(0xce4abe8dU, 0x0fb82907U, 0xdb24ee7bU, 0x2a45f7beU); + } + + WR1_PROG(REG_1600H, 0x38000d29U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0xbfa462a0U, 0x06d364f9U, 0x27c8c942U, 0xfcf8414dU); + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840006U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 5]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 6]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 7]); + + HW_SCE_p_func101(0x9cac5714U, 0x1a8d88f3U, 0x042ae983U, 0x54d7fb22U); + } + + HW_SCE_p_func102(0x2eb01363U, 0x1c30dd31U, 0x3035f60eU, 0xfee89dbbU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9i.c new file mode 100644 index 000000000..792a7712a --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9i.c @@ -0,0 +1,143 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256XtsEncryptInitSub (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00b90001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000b9U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x6eea8798U, 0x44a75759U, 0x1569683eU, 0x0129996bU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000009U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000b9U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x0799277dU, 0x3c88442fU, 0xd8be6ed1U, 0xd44daf38U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xa330b9a2U, 0xe1a198b2U, 0xf6dd35d5U, 0x367a69a7U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x64605020U, 0xdcc2def1U, 0x10b31eccU, 0xf6f31b83U); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x2b257193U, 0xe3bbc658U, 0x5989cbd6U, 0x927077d1U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7008d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[13]); + + WR1_PROG(REG_1824H, 0x080000a5U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x68f047ccU, 0xf949f365U, 0xa3e8c723U, 0x461eec73U); + WR1_PROG(REG_1824H, 0x080000b5U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[17]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x53e904d1U, 0xf4cb5c01U, 0x5df5c17cU, 0xd40ee756U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xcefbd001U, 0x39484998U, 0x46e09deaU, 0x86315211U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0a028045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9u.c new file mode 100644 index 000000000..411435a66 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pb9u.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256XtsEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x78e7f2ffU, 0xeb04c4b5U, 0x5753e2e6U, 0x86c1697eU); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d008906U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + + HW_SCE_p_func214(); + + HW_SCE_p_func101(0xdc26b10fU, 0x11df9189U, 0x2ba3f778U, 0xbcb5d957U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2f.c new file mode 100644 index 000000000..e55158c4c --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2f.c @@ -0,0 +1,389 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256XtsDecryptFinalSub (const uint32_t InData_TextBitLen[], + const uint32_t InData_Text[], + uint32_t OutData_Text[]) +{ + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_TextBitLen[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00076bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00026fdeU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00020020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x3420a800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2000abc0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000fffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0xbf6e9bbaU, 0xfbb3fd2dU, 0x361ff51fU, 0xe337ff25U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xbf44d826U, 0x8eaf7418U, 0x56df3fbcU, 0xbd5bfd1dU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x41b80281U, 0x890057afU, 0x20136bb4U, 0x414a050fU); + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + HW_SCE_p_func100(0x69abf3e5U, 0x611493a3U, 0xb959c158U, 0x93ca3a14U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d00890eU); + WR1_PROG(REG_1408H, 0x000c1000U); + + iLoop = 0; + if (S_RAM[0] >= 4) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < S_RAM[0]; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + } + + HW_SCE_p_func214(); + + WR1_PROG(REG_1600H, 0x38008c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0xef49075eU, 0xb09740feU, 0xfa7294e7U, 0xbd8daf8bU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func100(0x2b11bae1U, 0x599a47d2U, 0x050f2516U, 0x26729a70U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_1824H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1608H, 0x80040140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a1U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d00880cU); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d00890dU); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80840006U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03410011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1444H, 0x000003c7U); + WR1_PROG(REG_1608H, 0x80840007U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 4]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 5]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 6]); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Text[iLoop + 7]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b4a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003500U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00036908U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008d00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000000cU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000024c8U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000024e8U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003826U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003847U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003460U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008c60U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b480U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0xffffffffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00004403U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00007484U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000c24U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00001484U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000c44U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00001041U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003c47U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000037e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000007fU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000a7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002bdfU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00056bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000353eU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x810103c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + for (jLoop = 0U; jLoop < S_RAM[0]; jLoop++) + { + WR1_PROG(REG_1600H, 0x000024c5U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000024e5U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003ba6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00003fa7U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000033c0U); + WR1_PROG(REG_1458H, 0x00000000U); + HW_SCE_p_func101(0x71689ea6U, 0x30f1c1ecU, 0x0fd348fbU, 0xc18716f7U); + } + + HW_SCE_p_func100(0xfce69136U, 0xc4e5b382U, 0x1900776eU, 0x57ee8ae5U); + + WR1_PROG(REG_1600H, 0x38000fdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1608H, 0x81040140U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000010U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d00890dU); + WR1_PROG(REG_1608H, 0x81840007U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00001012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop]); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000024c8U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003826U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000c24U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003c26U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + + for (jLoop = 0U; jLoop < S_RAM[0]; jLoop++) + { + WR1_PROG(REG_1600H, 0x000024c5U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003fe6U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003120U); + WR1_PROG(REG_1458H, 0x00000000U); + HW_SCE_p_func101(0x573f09e9U, 0xd45247b9U, 0x211a4625U, 0xfd0cc7aeU); + } + + HW_SCE_p_func100(0x5befa306U, 0xaf83e205U, 0xf8b79326U, 0xeabdcd18U); + WR1_PROG(REG_1600H, 0x38000d29U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_143CH, 0x00402000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x000008c6U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x81840006U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005012U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 4]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 5]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 6]); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_Text[iLoop + 7]); + + HW_SCE_p_func101(0x003da0ffU, 0x38ede82dU, 0x395a1db8U, 0x62b964cfU); + } + + HW_SCE_p_func102(0xd6ef5360U, 0xf2145319U, 0xf9bbaa94U, 0x69dc2fa4U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2i.c new file mode 100644 index 000000000..db8fc19b6 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2i.c @@ -0,0 +1,143 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256XtsDecryptInitSub (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00c20001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000c2U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x32da2adbU, 0x0676b9a3U, 0x9a9d7785U, 0xb4bfaf94U); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000009U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000c2U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xda226a65U, 0x44ace6b3U, 0x37aec6bdU, 0xada71590U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x096ed48eU, 0x526ae11eU, 0x6f203addU, 0x8ba56759U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xe23657b4U, 0xb724fb3dU, 0xa02f7c5cU, 0xff025323U); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x9b1e1bd3U, 0x4425433cU, 0x1bba2630U, 0xc4a8f1bdU); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7008d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[13]); + + WR1_PROG(REG_1824H, 0x080000a5U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xe0501d1fU, 0xb6dcd4cdU, 0x8619c7d2U, 0xeed7612cU); + WR1_PROG(REG_1824H, 0x080000b5U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[17]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x2228f979U, 0x62e272bcU, 0xbe1ff2ecU, 0x281e5214U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x0f746abcU, 0x3de26c48U, 0x69477201U, 0xa9354859U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_182CH, 0x40000000U); + WR1_PROG(REG_1824H, 0x0a028045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2u.c new file mode 100644 index 000000000..ff27f635f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc2u.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256XtsDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0xe1692201U, 0x96535e43U, 0x49bd6d89U, 0x73365ba4U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x0d00890eU); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + + HW_SCE_p_func214(); + + HW_SCE_p_func101(0x9af7dd0dU, 0x4c7dab78U, 0xa5cf9583U, 0x816edeeeU); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5f.c new file mode 100644 index 000000000..abbd803c7 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5f.c @@ -0,0 +1,31 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128GctrFinalSub (void) +{ + HW_SCE_p_func102(0xbf582994U, 0x01110ccfU, 0xdae5e248U, 0xe162ad5fU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5i.c new file mode 100644 index 000000000..fb3596de3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5i.c @@ -0,0 +1,191 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes128GctrInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00c50001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x57f715b5U, 0xa2f1923cU, 0x62c92bd4U, 0x47dbb4f8U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x1277c918U, 0x77fdac3fU, 0x9efc67c6U, 0x3775b3d8U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xc1882f33U, 0xf47f527dU, 0x08eed0b3U, 0x91d751a0U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000c5U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xa254553eU, 0x237fbb74U, 0x755459cdU, 0xa1dcd51fU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000005U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x5bf5d66dU, 0xd3ee6932U, 0xdf374c34U, 0x4efa88d2U); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000c5U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x08faeeb0U, 0x8b3f986aU, 0xc4bd76f8U, 0x2a4b9e4bU); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x2a46c04bU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xb737c797U, 0xd710739fU, 0x75a5af87U, 0x57ac2e15U); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000c5U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x3c5782f4U, 0x83fe0b13U, 0x83b85d7dU, 0xce5cab26U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x40f35507U, 0xb5b0138aU, 0x9dd130bfU, 0xc4ffa8a9U); + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xf7009d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xdc7c8052U, 0xbb3134f9U, 0xa39195dfU, 0xfc6d5988U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xb8c78004U, 0x14ea49ceU, 0x98cd81bfU, 0x1a2efecfU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5u.c new file mode 100644 index 000000000..e26b3eb12 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc5u.c @@ -0,0 +1,51 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes128GctrUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x6423c44cU, 0x4c2db55dU, 0x75985270U, 0xac273783U); + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x00000020U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + HW_SCE_p_func214(); + + HW_SCE_p_func101(0xe3319894U, 0x26ea0ca4U, 0x6f77e888U, 0x26098bc5U); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8f.c new file mode 100644 index 000000000..aa7532027 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8f.c @@ -0,0 +1,31 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256GctrFinalSub (void) +{ + HW_SCE_p_func102(0x59ff28f9U, 0xeb463409U, 0x7de73c58U, 0x7c0cc6c3U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8i.c new file mode 100644 index 000000000..85ec163b9 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8i.c @@ -0,0 +1,199 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes256GctrInitSub (const uint32_t InData_KeyType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00c80001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1A24H, 0x0a4500e5U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &S_RAM[16 + 0]); + WAIT_STS(REG_1A28H, 6, 0); + WR1_PROG(REG_143CH, 0x00000900U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x318ec770U, 0xd5bfabd1U, 0x112ca5afU, 0xb3cfb7c2U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x89ac9a6bU, 0xf4d83a79U, 0x02c924f9U, 0x73f19540U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0x021865a0U, 0x0307e017U, 0x389f2ee2U, 0x30810692U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000c8U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x80de3e67U, 0x343656a0U, 0xd656c8ccU, 0x41a4742bU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000007U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x6e3d81a2U, 0x772565c6U, 0x3032a62dU, 0xa05bfa3eU); + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010140U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000c8U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x4f60af14U, 0xab0c7858U, 0x3de826c3U, 0x82bd1941U); + HW_SCE_p_func068(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x85d04999U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x038ce127U, 0x011f20abU, 0x3c1e874bU, 0x93472009U); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000c8U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xc3a19802U, 0x4484d6d5U, 0x31e62315U, 0x4f2f7e2cU); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x0308a82eU, 0x098c1c94U, 0x1e19d890U, 0x61922c26U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x4299bf9eU, 0x9badd882U, 0xbe3a2527U, 0xa9f77e98U); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x94836ef3U, 0x2084f684U, 0x53b92c5bU, 0xef56c719U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xe61c053aU, 0xa3ebb492U, 0xc404737cU, 0x29a354cfU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8u.c new file mode 100644 index 000000000..a87ef73b4 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pc8u.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes256GctrUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x08740140U, 0x8ab6c813U, 0xbebf8090U, 0x352101b7U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000020U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + HW_SCE_p_func214(); + + HW_SCE_p_func101(0xeeb79cb4U, 0x365dddc6U, 0x50233260U, 0x9350a06dU); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1f.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1f.c new file mode 100644 index 000000000..c156ca9f0 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1f.c @@ -0,0 +1,31 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes192GctrFinalSub (void) +{ + HW_SCE_p_func102(0xbcf94eebU, 0x45e4d971U, 0x8bdb15b4U, 0x1ea708eaU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1i.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1i.c new file mode 100644 index 000000000..4945e4285 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1i.c @@ -0,0 +1,122 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Aes192GctrInitSub (const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00d10001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000d1U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x328ade4cU, 0x77d104faU, 0xc7e3cc33U, 0xe88e74cfU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000006U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000d1U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xe63dbbadU, 0xe63ffe51U, 0xb79db575U, 0x2bea9dddU); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xa55d7ad1U, 0x389634d8U, 0x9cdd71b2U, 0x0b069bb6U); + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1824H, 0x08000085U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x441a423aU, 0x85626511U, 0x0e0a74a6U, 0xcb9fe8afU); + WR1_PROG(REG_1824H, 0x08000095U); + WR1_PROG(REG_1400H, 0x00420011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xbd66796eU, 0x98024929U, 0x7248a0a6U, 0xb7d693e7U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x791d71e5U, 0x90ceeafcU, 0xe79b9220U, 0x780b68acU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x000003c1U); + WR1_PROG(REG_1824H, 0x08000045U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_IV[0]); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1u.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1u.c new file mode 100644 index 000000000..1d54db018 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pd1u.c @@ -0,0 +1,52 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Aes192GctrUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + HW_SCE_p_func100(0x564e9c5fU, 0xb254edb4U, 0x71b6916cU, 0x88cf2102U); + + WR1_PROG(REG_1444H, 0x00020061U); + WR1_PROG(REG_182CH, 0x40000030U); + WR1_PROG(REG_1824H, 0x07008d06U); + WR1_PROG(REG_1408H, 0x000c1000U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[0]); + for (iLoop = 4U; iLoop < MAX_CNT; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Text[iLoop]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[iLoop - 4]); + iLoop = iLoop + 4U; + } + + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Text[MAX_CNT - 4]); + + HW_SCE_p_func214(); + + HW_SCE_p_func101(0xfdfa4950U, 0xb552b6daU, 0xbb4b63c3U, 0x25f3567cU); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdcf.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdcf.c new file mode 100644 index 000000000..6bf6905d1 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdcf.c @@ -0,0 +1,172 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Sha224HmacFinalSub (const uint32_t InData_Cmd[], + const uint32_t InData_MAC[], + const uint32_t InData_MACLength[], + uint32_t OutData_MAC[]) +{ + uint32_t iLoop = 0U; + + WAIT_STS(REG_2030H, 4, 1); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1444H, 0x000000c7U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + HW_SCE_p_func100(0xab85de68U, 0xaf014be3U, 0xc32647eaU, 0x21141bdeU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func100(0xfaa90b04U, 0xdb05fc45U, 0xf116e179U, 0x4c563193U); + WR1_PROG(REG_1408H, 0x0000401eU); + for (iLoop = 0U; iLoop < 7U; iLoop++) + { + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_MAC[iLoop]); + } + + HW_SCE_p_func102(0xda7dea0eU, 0x084e3f18U, 0x60567062U, 0x73ce8591U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + else + { + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010020U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MACLength[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3420a820U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x3420a820U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0xb33b47c0U, 0x878649d1U, 0xc4fc729cU, 0xa6bb2640U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xa7a3d327U, 0xdf977905U, 0x4920feabU, 0x27d0b64dU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8087001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x0345001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 32U; iLoop++) + { + WR1_PROG(REG_1600H, 0x3c002be1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x12003c1fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00002fe0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1824H, 0x08000045U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8188001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1824H, 0x08000055U); + WR1_PROG(REG_1400H, 0x00490011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000006c1U); + WR1_PROG(REG_1824H, 0x9c000005U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MAC[0]); + + WR1_PROG(REG_1824H, 0x9c100005U); + WAIT_STS(REG_1444H, 31, 1); + WR1_ADDR(REG_1420H, &InData_MAC[4]); + WR1_ADDR(REG_1420H, &InData_MAC[5]); + WR1_ADDR(REG_1420H, &InData_MAC[6]); + WR1_PROG(REG_1444H, 0x000000a1U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + HW_SCE_p_func100(0x04d8d90cU, 0x6b96c9c6U, 0x9e0e4e93U, 0xf0794cdaU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xb094a8fbU, 0xa137bccbU, 0x7277d755U, 0x65b717e2U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0x405ebcaeU, 0xb4555f29U, 0x19437680U, 0x1f1d8e16U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdci.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdci.c new file mode 100644 index 000000000..f43c5b675 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdci.c @@ -0,0 +1,147 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_Sha224HmacInitSub (const uint32_t InData_KeyIndex[], const uint32_t InData_MsgLen[]) +{ + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00dc0001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_2000H, 0x00000001U); + + WR1_PROG(REG_2004H, 0x00000040U); + + WR1_PROG(REG_2008H, 0x00000013U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000dcU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x9e779a23U, 0x088fb152U, 0x33f456b8U, 0x53a708bfU); + HW_SCE_p_func043(); + + WR1_PROG(REG_1600H, 0x0000b4e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001aU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000dcU)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xf46f84b6U, 0x61eb31d8U, 0xcf7a353eU, 0x47650c05U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + + WR1_PROG(REG_1400H, 0x01420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xfe7c0f49U, 0x302ff127U, 0x2a71a300U, 0xacad07dcU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xd0779a3eU, 0xb42754c2U, 0xa17661d4U, 0x6c8739adU); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + if ((InData_MsgLen[0] == 0) && (InData_MsgLen[1] == 0)) + { + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000080U); + + WR1_PROG(REG_200CH, 0x00000001U); + + WAIT_STS(REG_2030H, 8, 0); + + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2014H, 0x00000000U); + WR1_PROG(REG_1444H, 0x00000020U); + WR1_PROG(REG_2010H, 0x00000000U); + + WR1_PROG(REG_200CH, 0x00000100U); + + HW_SCE_p_func101(0xa4204b02U, 0xad55e563U, 0x62f762dbU, 0xcabb08beU); + } + else + { + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2014H, InData_MsgLen[0]); + WR1_PROG(REG_1444H, 0x00000040U); + WR1_PROG(REG_2010H, InData_MsgLen[1]); + + WR1_PROG(REG_200CH, 0x00000001U); + + HW_SCE_p_func101(0xc04a118aU, 0xf2fde612U, 0x849c870dU, 0xb484b286U); + } + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdcu.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdcu.c new file mode 100644 index 000000000..5e96fe562 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pdcu.c @@ -0,0 +1,54 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +void HW_SCE_Sha224HmacUpdateSub (const uint32_t InData_Msg[], const uint32_t MAX_CNT) +{ + uint32_t iLoop = 0U; + + WAIT_STS(REG_2030H, 0, 1); + + WR1_PROG(REG_1444H, 0x00020064U); + + for (iLoop = 0U; iLoop < (MAX_CNT & 0xfffffff0U);) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Msg[iLoop]); + WR4_ADDR(REG_1420H, &InData_Msg[iLoop + 4]); + WR4_ADDR(REG_1420H, &InData_Msg[iLoop + 8]); + WR4_ADDR(REG_1420H, &InData_Msg[iLoop + 12]); + + iLoop = iLoop + 16U; + } + + for (iLoop = (MAX_CNT & 0xfffffff0U); iLoop < MAX_CNT; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Msg[iLoop]); + } + + WR1_PROG(REG_1444H, 0x00000000U); + WAIT_STS(REG_2030H, 8, 0); + WR1_PROG(REG_143CH, 0x00001600U); + + HW_SCE_p_func101(0x1e0a6afeU, 0xa2781091U, 0xd107e3e7U, 0xd365206aU); +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf0.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf0.c new file mode 100644 index 000000000..3b85dea27 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf0.c @@ -0,0 +1,568 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_EcdsaSignatureGenerateSub (const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00f00001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010380U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000007c7U); + WR1_PROG(REG_1608H, 0x8088001eU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 8U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MsgDgst[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000d3e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000381eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000381eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000037beU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000a7a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000383dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38001001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x30000f5aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000d3e1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000f9cU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3e1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x9f63ba50U, 0xc6f10b13U, 0x5443a939U, 0x2335590eU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x8728e799U, 0x0980b959U, 0xc9de3998U, 0xdac0cc1fU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x6b0789f4U, 0x98979788U, 0x1df7351fU, 0xcbaaeaedU); + + WR1_PROG(REG_1600H, 0x30003340U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000002F8U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000001C0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000C8U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000110U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + HW_SCE_p_func100(0xd7f4a86cU, 0x29025887U, 0x66aeaed2U, 0x346c2bb4U); + HW_SCE_p_func070(OFS_ADR); + + HW_SCE_p_func100(0x3d8480a5U, 0xcb2496a5U, 0x0cad6498U, 0xa2c596b1U); + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10f00000U); + HW_SCE_p_func103(); + HW_SCE_p_func100(0xf60090baU, 0xb7f83697U, 0x65a03b4eU, 0x56c72ceaU); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000340U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0xb3927c80U, 0x3a418d99U, 0x5ee330c6U, 0x44582d3cU); + HW_SCE_p_func071(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f0U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x464eee40U, 0xf6540225U, 0x5b002130U, 0xef41bc4bU); + HW_SCE_p_func088(); + + HW_SCE_p_func100(0x866ae4f7U, 0xaf825411U, 0x62152033U, 0x4fe91948U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xaee06646U, 0x068d15c0U, 0x0cff73bfU, 0xea9476afU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002f0U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x04040004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000140U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x0caa0c87U, 0xa5762ff2U, 0x7feb5b1cU, 0x8f3e9e2fU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x21e4d6eaU, 0x3301e1fbU, 0x7889b018U, 0x1197a856U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x1a5644dcU, 0x1bb07e7bU, 0xe6388aecU, 0xf13e2df6U); + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0404000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8188001eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1404H, 0x11400000U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f0U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x1e527673U, 0x8501dbf1U, 0x11bb11e2U, 0x7b538897U); + HW_SCE_p_func043(); + + HW_SCE_p_func074(); + + WR1_PROG(REG_1600H, 0x000034feU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f0U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xc02865afU, 0x418c835aU, 0x74d8def9U, 0x979af91cU); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000007c2U); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + for (iLoop = 0U; iLoop < 8U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1404H, 0x11e00000U); + WR1_PROG(REG_1400H, 0x00c20021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xe072b933U, 0x55738e7fU, 0x00dd81deU, 0x8681cd12U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x5f2dbbe3U, 0xb8a497bdU, 0x3449733aU, 0xe3e1e1ffU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x04040005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x04040002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000140U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xf9f52d05U, 0x7e682a3cU, 0xc80ea63cU, 0xfb921b10U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x3a80871bU, 0x5a352fb8U, 0xe3f71bd6U, 0xcaf77f5cU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xa389884cU, 0xca56ea3bU, 0x2634b6fdU, 0x9fc3d37fU); + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[0]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[4]); + + HW_SCE_p_func100(0x316a9908U, 0x22e7259bU, 0x2aa430efU, 0x534f9994U); + WR1_PROG(REG_1404H, 0x11e00000U); + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[8]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[12]); + + HW_SCE_p_func102(0x00a8333eU, 0x216b7d7cU, 0x364f8b44U, 0xd627438eU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } + } + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf1.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf1.c new file mode 100644 index 000000000..32beca63e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf1.c @@ -0,0 +1,376 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_EcdsaSignatureVerificationSub (const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14BCH, 0x0000001fU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00f10001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010380U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000017c7U); + WR1_PROG(REG_1608H, 0x8098001eU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 16U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Signature[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + } + + for (iLoop = 0U; iLoop < 8U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MsgDgst[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + } + + for (iLoop = 0U; iLoop < 3U; iLoop++) + { + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000d3e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000381eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000381eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000037beU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000a7a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000383dU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38001001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000fffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00260000U); + + WR1_PROG(REG_1600H, 0x0000a7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000020U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x30000f5aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000d3e1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000f9cU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3e1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x81d72457U, 0xc993847eU, 0xc6b8ef93U, 0x477ab4e9U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xfa93a391U, 0x96cf70f4U, 0x04d16822U, 0x72688da6U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8190001eU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x19100000U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19600000U); + WR1_PROG(REG_1400H, 0x00c90021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1A2CH, 0x00000100U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8188001eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00890021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00000bdeU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x8088001eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f1U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xb0a6bb0eU, 0xa546e81aU, 0xe0b9b2aeU, 0xf2fad0e5U); + HW_SCE_p_func043(); + + HW_SCE_p_func075(); + + WR1_PROG(REG_1600H, 0x000034feU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f1U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xed38d678U, 0xebc41b20U, 0xc6866a89U, 0x5e37bb02U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x00000fc2U); + WR1_PROG(REG_1A2CH, 0x40000300U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80900001U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + WR1_PROG(REG_1400H, 0x03420021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[13]); + WR1_PROG(REG_1400H, 0x03420021U); + + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[17]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xa0742a70U, 0x365ef872U, 0x5d462717U, 0x6ff9abf4U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xcc298b29U, 0x33daf946U, 0x5428dc2fU, 0x418fd6e4U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x82fa3780U, 0x83fac1baU, 0xbe0fd36fU, 0x8412faf2U); + + WR1_PROG(REG_1600H, 0x30003340U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000002F8U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000001C0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000C8U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000110U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f1U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x46cc77c8U, 0xefe9b8c8U, 0x9b014857U, 0x3ba3f178U); + HW_SCE_p_func073(OFS_ADR); + + HW_SCE_p_func100(0xc91ddcdbU, 0x385b1e23U, 0x1736e586U, 0x70e9b6ecU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x55746b00U, 0x616b0d97U, 0xabfdbafaU, 0x5a600e40U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0x3c29c893U, 0xe125d83fU, 0xc68dce3cU, 0x367fae96U); + WR1_PROG(REG_14BCH, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf4.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf4.c new file mode 100644 index 000000000..1984eeddd --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf4.c @@ -0,0 +1,728 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub (const uint32_t InData_CurveType[], + const uint32_t InData_Cmd[], + uint32_t OutData_PubKeyIndex[], + uint32_t OutData_PrivKeyIndex[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00f40001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010380U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_Cmd[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x3020ab80U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000003U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00060020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b780U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x30000f5aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000d3e1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x38000f9cU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x1000d3e1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38008be0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000002U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + HW_SCE_p_func100(0x3bb02596U, 0xc76587d8U, 0x2bcc2d3eU, 0x64d63cc7U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xc6593416U, 0xf47a7361U, 0x9a6b3284U, 0x0ddc48abU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x51a185ceU, 0xe75a21cfU, 0x86cb31ceU, 0x718dae7cU); + + WR1_PROG(REG_1600H, 0x30003340U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000002F8U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000001C0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x30003380U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00070020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x000000C8U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00050040U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000110U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + HW_SCE_p_func100(0x99b4ed6bU, 0x4d105e95U, 0x079b7f1dU, 0x1948c634U); + HW_SCE_p_func070(OFS_ADR); + HW_SCE_p_func100(0x151dc59dU, 0xbea9a9baU, 0xfef31733U, 0x87c6fcffU); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x04040010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1404H, 0x12c80000U); + + WR1_PROG(REG_1600H, 0x00007c1cU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00600000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000000U) + { + HW_SCE_p_func100(0x5359447cU, 0x0023871dU, 0xf250736fU, 0x37598daaU); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0x7f5c3a66U, 0x84c46422U, 0x3e56f966U, 0xefb27f6dU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000001U) + { + HW_SCE_p_func100(0xf6bb6ca1U, 0xd9025197U, 0xb10afc7eU, 0xa698c1dbU); + WR1_PROG(REG_1400H, 0x00c0000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0x1034e7cfU, 0x4c1f3a2bU, 0x900cdca9U, 0x30273f6aU); + } + else if (RD1_MASK(REG_1440H, 0xffffffffU) == 0x00000002U) + { + WR1_PROG(REG_1400H, 0x00c00011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func101(0x9125ec9fU, 0x73dda841U, 0x2b657109U, 0x074a8efcU); + } + + HW_SCE_p_func100(0xda0a2eb6U, 0xf8e1ba42U, 0x5ddf9c67U, 0x5b70dd2aU); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x1a610e49U, 0xace0f63dU, 0x46685e8aU, 0x2f5b1723U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0404000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11380000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x04040007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x91ac231dU, 0xda665267U, 0xb91c7f9fU, 0xe3db4034U); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x12280000U); + WR1_PROG(REG_1608H, 0x808a0001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03430029U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + for (iLoop = 0U; iLoop < 10U; iLoop++) + { + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x20000842U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10003841U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x3800585eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x20003460U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10002c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x100033c0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1404H, 0x14580000U); + WR1_PROG(REG_1400H, 0x00c00029U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x05050009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10e80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c00025U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00003403U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003060U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x05050007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x05050009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00003060U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xb24f6eabU, 0xe48a2b08U, 0xaedcdb3fU, 0xc9136660U); + } + + WR1_PROG(REG_1600H, 0x00007c03U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10e80000U); + WR1_PROG(REG_1400H, 0x00c00029U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x5c0020d7U, 0x8a66dde4U, 0x3928222dU, 0x8c32ca03U); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0505000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + HW_SCE_p_func100(0xb432d8eeU, 0xb8396280U, 0x6691ebd1U, 0x72bacb42U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x05050009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func101(0x469986e3U, 0x75d4d7c6U, 0x81e4e403U, 0x695af59eU); + } + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0505000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x05050009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1600H, 0x00003000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xa37ba5f0U, 0x120c3209U, 0xcff7c408U, 0x30039e0cU); + } + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10f00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0001dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x04040009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x3cf4c830U, 0x82d10b6dU, 0x6bb8d45fU, 0x8122b08fU); + HW_SCE_p_func071(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xb01f8b5bU, 0x99ca3f01U, 0x06563c5fU, 0x6c3a52faU); + HW_SCE_p_func088(); + + HW_SCE_p_func100(0x5432fae7U, 0x37910ff4U, 0x7bdeb094U, 0xd13eff76U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x9def6038U, 0xa56139f8U, 0x1b204a65U, 0x2e9fc54eU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x5fff60ffU, 0x650fb329U, 0xb0e821dfU, 0x5f655976U); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xf8bb4203U, 0x0c734f0cU, 0xe545944fU, 0x5125fc2bU); + HW_SCE_p_func043(); + + HW_SCE_p_func074(); + + WR1_PROG(REG_1600H, 0x000034feU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f4U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x8da11265U, 0x948b1cf6U, 0x208e3474U, 0x1890c7b4U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x5d76ffb4U, 0x109edb45U, 0xd459e80fU, 0xb196c3dbU); + WR1_PROG(REG_1A2CH, 0x40000100U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1404H, 0x13200000U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[5]); + + HW_SCE_p_func100(0x06e4f0beU, 0xb97eac54U, 0x042c496bU, 0x8938e7cbU); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[9]); + + HW_SCE_p_func100(0x879e8ef8U, 0xf6ab99b3U, 0x62f427a4U, 0x32bc17b1U); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PrivKeyIndex[0]); + + HW_SCE_p_func100(0x71ae8ca7U, 0x128bf4fcU, 0x5b6a4179U, 0xe8c292ecU); + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x59df78fcU, 0x4eeb361fU, 0xec07c31cU, 0x56bb80d2U); + HW_SCE_p_func043(); + + HW_SCE_p_func075(); + + WR1_PROG(REG_1600H, 0x000034feU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xfffbd8e4U, 0x8650ca05U, 0x1737f30cU, 0x5c78792eU); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0x1bc83e02U, 0xc239c64fU, 0xa4f1cb5cU, 0xa139db47U); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8009107U); + WR1_PROG(REG_1404H, 0x12800000U); + WR1_PROG(REG_1400H, 0x00830021U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1404H, 0x12d00000U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[9]); + + HW_SCE_p_func100(0x939de9b0U, 0x7272e484U, 0x211d0397U, 0xb55d4bc8U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0xe8008105U); + WR1_PROG(REG_1400H, 0x00830011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1408H, 0x00002022U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[13]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[17]); + + HW_SCE_p_func100(0xc69687d7U, 0xf7b35fb0U, 0x65f03846U, 0x62b40192U); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PubKeyIndex[0]); + + HW_SCE_p_func102(0x97da3c5fU, 0x29a7bb8fU, 0xd79698ffU, 0x9aef700bU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf5.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf5.c new file mode 100644 index 000000000..22992055f --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf5.c @@ -0,0 +1,469 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_EcdsaP384SignatureGenerateSub (const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + uint32_t OutData_Signature[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00f50001U); + WR1_PROG(REG_144CH, 0x00000000U); + + HW_SCE_p_func100(0x2aa3030aU, 0xf85fadfbU, 0xaa7f67f3U, 0xbfd28ea4U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000f5aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000158U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000208U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + HW_SCE_p_func100(0xefd61928U, 0x173773d9U, 0x2fb2a587U, 0x8940a5eaU); + HW_SCE_p_func027(OFS_ADR); + HW_SCE_p_func100(0x7637cc12U, 0x728c9923U, 0x9c2082b5U, 0x2d6a77b3U); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10e00000U); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x807e76b4U, 0x56e6d220U, 0xa84ad0ccU, 0x94d7cc42U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0x9b1d54d6U, 0xe985e6f0U, 0xab952736U, 0xe73d6b60U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x06060004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x4e2e7966U, 0x7c689961U, 0x3207aa28U, 0x0b0fe81cU); + HW_SCE_p_func028(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f5U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xf29e8983U, 0x93e83028U, 0x30fb1742U, 0xfe826721U); + HW_SCE_p_func089(); + + HW_SCE_p_func100(0xed847215U, 0x78c03924U, 0x84b217f5U, 0x10f3f254U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x221e077cU, 0x73db8c40U, 0x1f1ca672U, 0x8b0cd487U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002f0U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x06060004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000140U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x88f94951U, 0x1c1197c2U, 0xad23d2eeU, 0xc24fd94aU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x8bc5138fU, 0x247cd4fcU, 0x61e2ed03U, 0x06f8eebdU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xf4664f22U, 0xb74c56c7U, 0xb33b278fU, 0x157f3213U); + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000340U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0606000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1444H, 0x00000bc2U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + + WR1_PROG(REG_1404H, 0x11300000U); + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_MsgDgst[iLoop]); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f5U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xce0c9adfU, 0xfcb73bf3U, 0xc591083cU, 0x63fc4e99U); + HW_SCE_p_func043(); + + HW_SCE_p_func076(); + + WR1_PROG(REG_1600H, 0x000034feU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f5U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x2d2d6a65U, 0xc0f7ddbbU, 0x645c86ccU, 0x76665fcaU); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x00000bc2U); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xf7009d07U); + + for (iLoop = 0U; iLoop < 12U; ) + { + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + iLoop = iLoop + 4U; + } + + WR1_PROG(REG_1404H, 0x11d00000U); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[iLoop + 1]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0x80fa4829U, 0xb3bbb87eU, 0xbb25e37bU, 0xd8c61a17U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x5323d9f3U, 0x7281b847U, 0x16c301feU, 0x01d581e3U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x06060005U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000200U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000200U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000140U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x09b4ab22U, 0x4fb099e6U, 0x65a5558cU, 0x9663bf74U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x8c3bb4f9U, 0x15fe7418U, 0x3968baf6U, 0xfcfbcc4aU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xa8f1c210U, 0x97f61315U, 0x0feefab7U, 0xdbeb571fU); + WR1_PROG(REG_1404H, 0x12700000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[0]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[4]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[8]); + + HW_SCE_p_func100(0x6fad12c5U, 0x60b71d76U, 0xfb4ddaecU, 0xf306a774U); + WR1_PROG(REG_1404H, 0x11d00000U); + WR1_PROG(REG_1A2CH, 0x00000200U); + WR1_PROG(REG_1A24H, 0x08008107U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[12]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[16]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_Signature[20]); + + HW_SCE_p_func102(0x1be1372aU, 0x22005f45U, 0x122f9aadU, 0x86dd3b9aU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf6.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf6.c new file mode 100644 index 000000000..67885f9d3 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf6.c @@ -0,0 +1,743 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_EcdsaP384SignatureVerificationSub (const uint32_t InData_CurveType[], + const uint32_t InData_KeyIndex[], + const uint32_t InData_MsgDgst[], + const uint32_t InData_Signature[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00f60001U); + WR1_PROG(REG_144CH, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x800100e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_KeyIndex[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f6U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x8e154ae7U, 0x3298eb8dU, 0xe8be6798U, 0x083848b5U); + HW_SCE_p_func043(); + + HW_SCE_p_func077(); + + WR1_PROG(REG_1600H, 0x000034feU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f6U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x437460f9U, 0x504ba536U, 0xb4362b46U, 0xb38716c3U); + HW_SCE_p_func044(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000044U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1444H, 0x000017c2U); + WR1_PROG(REG_1A2CH, 0x40000500U); + WR1_PROG(REG_1A24H, 0xe8009107U); + + WR1_PROG(REG_1600H, 0x0000b420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x80980001U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[1]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[5]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[9]); + WR1_PROG(REG_1400H, 0x03420031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[13]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[17]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[21]); + WR1_PROG(REG_1400H, 0x03420031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1444H, 0x000003c2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x07008d05U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_KeyIndex[25]); + + WR1_PROG(REG_1A24H, 0x9c100005U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xc75cbf96U, 0xb8e1c2dcU, 0x1880d74bU, 0x05c32ce5U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xcd3c27a3U, 0xb8b2e571U, 0xe3095351U, 0xf8d78904U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + WR1_PROG(REG_1444H, 0x00000bc7U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x808c001fU); + WR1_PROG(REG_1458H, 0x00000000U); + for (iLoop = 0U; iLoop < 12U; iLoop++) + { + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_MsgDgst[iLoop]); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x80010360U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f6U)); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + HW_SCE_p_func100(0x12b341a6U, 0x34b5f214U, 0xc5996329U, 0x4871f9c7U); + + WR1_PROG(REG_1600H, 0x38000f5aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000158U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000208U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + HW_SCE_p_func100(0x075caa26U, 0xad350f03U, 0x03b6da99U, 0x5c48631cU); + HW_SCE_p_func027(OFS_ADR); + + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x19000000U); + WR1_PROG(REG_1444H, 0x000017c2U); + WR1_PROG(REG_1A2CH, 0x00000500U); + WR1_PROG(REG_1A24H, 0x08008107U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[0]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[4]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[8]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x19500000U); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[12]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[16]); + WAIT_STS(REG_1444H, 31, 1); + WR4_ADDR(REG_1420H, &InData_Signature[20]); + WR1_PROG(REG_1400H, 0x00c20031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x11d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000930U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000980U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x27c7f36eU, 0xd8f23dbdU, 0xeb5375bfU, 0xc9ffb9f3U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xd47493bbU, 0x90eb3bc9U, 0x0755340bU, 0x5e3a93f3U); + } + else + { + HW_SCE_p_func100(0x0be27cd5U, 0x42eea78eU, 0xd8def01aU, 0x6d155b6fU); + + WR1_PROG(REG_1014H, 0x00000160U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000980U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + WR1_PROG(REG_1010H, 0x00000020U); + + WR1_PROG(REG_1004H, 0x0606000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000840U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1600H, 0x00000bffU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x818c001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00c90031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x000000c0U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x198a94d0U, 0xfc6d5e60U, 0x1867967cU, 0x016a4be6U); + WR1_PROG(REG_1010H, 0x00000018U); + + WR1_PROG(REG_1404H, 0x11600000U); + WR1_PROG(REG_1400H, 0x00c000f1U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func028(OFS_ADR); + + WR1_PROG(REG_1014H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x06060004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1400H, 0x00c00031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000890U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000002b8U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x180b0c72U, 0x3acb0bebU, 0xf9b73a00U, 0xe7c956c9U); + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000340U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000480U); + + WR1_PROG(REG_1004H, 0x06060015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x11d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x27ae2ac8U, 0x9b102d65U, 0xd4d65f6bU, 0xc2ecd7f4U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xffc29c8dU, 0x2fe4bf20U, 0x73be19daU, 0x383eb419U); + } + else + { + HW_SCE_p_func100(0xfd6e5c73U, 0x857a641eU, 0xf0aba45bU, 0x75181e76U); + WR1_PROG(REG_1404H, 0x11b00000U); + WR1_PROG(REG_1400H, 0x00c00031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x000001e0U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1608H, 0x818c0001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00c90031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000001e0U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1600H, 0x000037e1U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000a7e0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000030U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x818c001fU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x00c90031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000110U); + WR1_PROG(REG_1018H, 0x00000390U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000218U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000340U); + WR1_PROG(REG_101CH, 0x000002f0U); + WR1_PROG(REG_1020H, 0x00000570U); + + WR1_PROG(REG_1004H, 0x06060015U); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x11d00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000570U); + WR1_PROG(REG_1018H, 0x00000200U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xc965548eU, 0x25b8f076U, 0xe75a3112U, 0x19d25e5bU); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x59f32118U, 0xb890f414U, 0x6bf6e250U, 0x1b9cfa71U); + } + else + { + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x00000570U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x06060013U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1404H, 0x12700000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000480U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0x5d58e9f2U, 0x544e6bf8U, 0xa3cf6707U, 0x5527b2d8U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xdcdea964U, 0xe2497bf3U, 0xdcf54b31U, 0xf889a735U); + } + else + { + HW_SCE_p_func100(0x8bd6311cU, 0x19ce5adeU, 0xa236db70U, 0x6d542c23U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x06060004U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11300000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000070U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000110U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x00000160U); + + WR1_PROG(REG_1004H, 0x0606000fU); + WR1_PROG(REG_1408H, 0x00020000U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_143CH, 0x00000d00U); + + WR1_PROG(REG_1014H, 0x000001e0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_101CH, 0x00000070U); + WR1_PROG(REG_1020H, 0x000002a0U); + + WR1_PROG(REG_1004H, 0x06060002U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x000002a0U); + WR1_PROG(REG_1018H, 0x00000930U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + WR1_PROG(REG_1014H, 0x00000930U); + WR1_PROG(REG_1018H, 0x000002a0U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00210000U); + + HW_SCE_p_func100(0xb0f16f8cU, 0xe246becdU, 0x65c78995U, 0x317d8929U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x752d1c73U, 0xae8256c3U, 0x605cc9ddU, 0x0c80f8ecU); + } + else + { + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x797935bbU); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xb9a81c05U, 0x89970b42U, 0x30b6d17aU, 0xc5e9bb78U); + } + } + } + } + } + + WR1_PROG(REG_1600H, 0x38008800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x797935bbU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1608H, 0x00000080U); + WR1_PROG(REG_143CH, 0x00A60000U); + + WR1_PROG(REG_1600H, 0x00007c1bU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func100(0x3e6f6a94U, 0x1df59ef0U, 0xd3f24b65U, 0x338a4016U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0xb8fc4686U, 0xbb5f4265U, 0xa9d02530U, 0x5bc6eb06U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0xe175cb09U, 0xda1f11ebU, 0x37721350U, 0x421c9c01U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf9.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf9.c new file mode 100644 index 000000000..01732afaf --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/hw_sce_p_pf9.c @@ -0,0 +1,618 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSub (const uint32_t InData_CurveType[], + uint32_t OutData_PubKeyIndex[], + uint32_t OutData_PrivKeyIndex[]) +{ + uint32_t OFS_ADR = 0U; + uint32_t iLoop = 0U; + uint32_t jLoop = 0U; + + if (RD1_MASK(REG_14B8H, 0x0000001eU) != 0) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + else + { + ; + } + + WR1_PROG(REG_1B00H, 0x00f90001U); + WR1_PROG(REG_144CH, 0x00000000U); + + HW_SCE_p_func100(0x303f83d7U, 0x771a986aU, 0xaedc9f84U, 0xf0dd29c3U); + + WR1_PROG(REG_1000H, 0x00010000U); + WR1_PROG(REG_1024H, 0x000007f0U); + + WR1_PROG(REG_1444H, 0x000000c7U); + WR1_PROG(REG_1608H, 0x80010340U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, InData_CurveType[0]); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x38000f5aU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00030020U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000158U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000b400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000208U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000080U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + OFS_ADR = S_RAM[0]; + + HW_SCE_p_func100(0x2b7eab5aU, 0x19552c02U, 0x669f30f7U, 0xcab6e0cfU); + HW_SCE_p_func027(OFS_ADR); + + HW_SCE_p_func100(0x7b70d739U, 0x7bca35daU, 0x787e0e66U, 0xfaf8eb48U); + WR1_PROG(REG_1010H, 0x00000020U); + WR1_PROG(REG_101CH, 0x000000c0U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1010H, 0x00000018U); + WR1_PROG(REG_101CH, 0x00000070U); + + WR1_PROG(REG_1004H, 0x06060010U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x12b80000U); + HW_SCE_p_func103(); + HW_SCE_p_func100(0xc229f873U, 0x4429acaaU, 0xe5f6eee1U, 0x104ceb71U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0x94751e5cU, 0x21c70878U, 0x0f79e6d8U, 0x57864974U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + HW_SCE_p_func100(0xd33bc9a7U, 0x9f58b623U, 0xbc1e0453U, 0x5089c3d3U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + WR1_PROG(REG_1400H, 0x00c20011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func103(); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1400H, 0x00c20009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00020009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000000c0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x0606000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x11280000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c00031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c00009U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000160U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x06060007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0x8b127ea4U, 0x542d4638U, 0xeb26bc67U, 0x8dcbc35aU); + WR1_PROG(REG_1600H, 0x00000800U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000821U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000863U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x12180000U); + WR1_PROG(REG_1608H, 0x808e0001U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03430039U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + for (iLoop = 0U; iLoop < 14U; iLoop++) + { + WR1_PROG(REG_1600H, 0x38000c63U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x20000842U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10003841U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x0000b7c0U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x0000001fU); + WR1_PROG(REG_1458H, 0x00000000U); + + for (jLoop = 0U; jLoop < 32U; jLoop++) + { + WR1_PROG(REG_1600H, 0x3800585eU); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x20003460U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x20002c60U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x10002c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x100033c0U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1600H, 0x0000a420U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000004U); + WR1_PROG(REG_1458H, 0x00000000U); + } + + WR1_PROG(REG_1404H, 0x14480000U); + WR1_PROG(REG_1400H, 0x00c00039U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x07070009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1404H, 0x10d80000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000002U)); + WR1_PROG(REG_1400H, 0x00c00035U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x00003403U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1600H, 0x00003060U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010060U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x07070007U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000480U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x07070009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1600H, 0x00003060U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x60faf7cfU, 0x183edbd1U, 0x491e7e93U, 0xda5f003cU); + } + + WR1_PROG(REG_1600H, 0x00007c03U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10d80000U); + WR1_PROG(REG_1400H, 0x00c00039U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + HW_SCE_p_func100(0xc153fa60U, 0x9e8279eaU, 0x1e97ac9bU, 0x4fe3540eU); + WR1_PROG(REG_1600H, 0x0000a400U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1600H, 0x00000040U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &S_RAM[0]); + S_RAM[0] = change_endian_long(S_RAM[0]); + + for (iLoop = 0U; iLoop < S_RAM[0]; iLoop++) + { + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0707000aU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_143CH, 0x00a10000U); + + HW_SCE_p_func100(0xffb00f67U, 0x71df71cfU, 0x1f73b4f9U, 0x2c1d74f1U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000002f0U); + + WR1_PROG(REG_1004H, 0x07070009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func101(0xd1389f0cU, 0x62cecba9U, 0x03505911U, 0x06d7a8b5U); + } + + WR1_PROG(REG_1014H, 0x000001b0U); + WR1_PROG(REG_1020H, 0x00000250U); + + WR1_PROG(REG_1004H, 0x0707000cU); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + WR1_PROG(REG_1014H, 0x00000250U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x000001b0U); + + WR1_PROG(REG_1004H, 0x07070009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + WR1_PROG(REG_1600H, 0x00003000U); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x959a8afdU, 0xbdfa2eafU, 0xf4cf7a7dU, 0x98adb947U); + } + + WR1_PROG(REG_1600H, 0x00007c00U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_143CH, 0x00602000U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1404H, 0x10e00000U); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x08000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000001U)); + WR1_PROG(REG_1400H, 0x00c0002dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x00c20005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1014H, 0x000002f0U); + WR1_PROG(REG_1018H, 0x00000110U); + WR1_PROG(REG_1020H, 0x00000340U); + + WR1_PROG(REG_1004H, 0x06060009U); + WR1_PROG(REG_1000H, 0x00010001U); + WAIT_STS(REG_1000H, 0, 0); + + HW_SCE_p_func100(0xb589b85dU, 0x33b66f18U, 0x1ebb3a51U, 0xf15800deU); + HW_SCE_p_func028(OFS_ADR); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f9U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xba1979daU, 0x0dc01d9bU, 0x734b5f3eU, 0x09477300U); + HW_SCE_p_func089(); + + HW_SCE_p_func100(0xada0da3eU, 0xd49f342bU, 0x04bf46b2U, 0xde8ee021U); + WR1_PROG(REG_143CH, 0x00400000U); + WR1_PROG(REG_1458H, 0x00000000U); + + if (CHCK_STS(REG_143CH, 22, 1)) + { + HW_SCE_p_func102(0x262f89dcU, 0x6001fcecU, 0x86dbabd0U, 0xb5222f5cU); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xc2210d01U, 0x73327e6bU, 0x71d9d553U, 0xf62fbf6aU); + HW_SCE_p_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f9U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xc195f0caU, 0x6a82bf97U, 0x6a603f1aU, 0x94981a57U); + HW_SCE_p_func043(); + + HW_SCE_p_func076(); + + WR1_PROG(REG_1600H, 0x000034feU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x000000f9U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xa12b0613U, 0x74d98fa5U, 0x4f4bf1c6U, 0x0886e961U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xbe2df369U, 0x084a3dbeU, 0xb374aeadU, 0x6dc7a942U); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe7009d07U); + WR1_PROG(REG_1404H, 0x13100000U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[9]); + + HW_SCE_p_func100(0xd2e80054U, 0x15be6d3bU, 0xce69ea55U, 0x9575c9cfU); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c000104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108105U); + WR1_PROG(REG_1400H, 0x00820011U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PrivKeyIndex[13]); + + HW_SCE_p_func100(0x57cc4616U, 0xff3a6ff7U, 0x258a2ebdU, 0xb4435777U); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PrivKeyIndex[0]); + + HW_SCE_p_func100(0xd30fec86U, 0xfa2124abU, 0xf4f2f85aU, 0x61f858cfU); + HW_SCE_p_func103(); + + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A24H, 0x0c200104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1608H, 0x80010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1400H, 0x03420005U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + WR1_PROG(REG_1400H, 0x0002000dU); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1600H, 0x000034e0U); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000027U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0x5aed0138U, 0x6ae892c6U, 0x3fbe09c9U, 0x21d701deU); + HW_SCE_p_func043(); + + HW_SCE_p_func077(); + + WR1_PROG(REG_1600H, 0x000034feU); + WR1_PROG(REG_1458H, 0x00000000U); + + WR1_PROG(REG_1444H, 0x000000a7U); + WR1_PROG(REG_1608H, 0x800103a0U); + WR1_PROG(REG_1458H, 0x00000000U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000028U)); + WR1_PROG(REG_1458H, 0x00000000U); + + HW_SCE_p_func101(0xaf72abd1U, 0xba752e53U, 0x5ab67e46U, 0xe2637628U); + HW_SCE_p_func044(); + + HW_SCE_p_func100(0xa17d3930U, 0xd2ddbc73U, 0xc00f0d88U, 0xd16dd81fU); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8009107U); + WR1_PROG(REG_1404H, 0x12700000U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[1]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[5]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[9]); + + HW_SCE_p_func100(0x0e3eeab6U, 0x09a0aa4bU, 0xe71b77cfU, 0xe6dff70cU); + WR1_PROG(REG_1A2CH, 0x40000200U); + WR1_PROG(REG_1A24H, 0xe8008107U); + WR1_PROG(REG_1404H, 0x12c00000U); + WR1_PROG(REG_1400H, 0x00830031U); + WAIT_STS(REG_1404H, 30, 0); + WR1_PROG(REG_143CH, 0x00001800U); + + WR1_PROG(REG_1408H, 0x00002032U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[13]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[17]); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[21]); + + HW_SCE_p_func100(0x724b1395U, 0x87f234a6U, 0x31fed8a4U, 0x7148489aU); + WR1_PROG(REG_1444H, 0x000000a2U); + WR1_PROG(REG_1A2CH, 0x40000000U); + WR1_PROG(REG_1A24H, 0x09108104U); + WAIT_STS(REG_1444H, 31, 1); + WR1_PROG(REG_1420H, change_endian_long(0x00000000U)); + + WR1_PROG(REG_1408H, 0x00002012U); + WAIT_STS(REG_1408H, 30, 1); + RD4_ADDR(REG_1420H, &OutData_PubKeyIndex[25]); + + HW_SCE_p_func100(0xf48a789eU, 0x00776473U, 0x56520405U, 0xff6a5ecdU); + WR1_PROG(REG_1608H, 0x81010000U); + WR1_PROG(REG_1458H, 0x00000000U); + WR1_PROG(REG_1408H, 0x00005006U); + WAIT_STS(REG_1408H, 30, 1); + RD1_ADDR(REG_1420H, &OutData_PubKeyIndex[0]); + + HW_SCE_p_func102(0x69c55476U, 0x8005afeeU, 0xafd9e99cU, 0x12ba5e24U); + WR1_PROG(REG_14B8H, 0x00000040U); + WAIT_STS(REG_142CH, 12, 0); + + return FSP_SUCCESS; + } +} + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/s_flash2.c b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/s_flash2.c new file mode 100644 index 000000000..28efb5059 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/primitive/s_flash2.c @@ -0,0 +1,531 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#include "hw_sce_ra_private.h" + +uint32_t const S_FLASH2[] = + { +#ifndef __ARMEB__ /* Little endian */ + + 0xc5ec05a5, 0xc8ca236c, 0xc44ad334, 0x7e02d9e1, + 0xf4400e92, 0x946e7917, 0x6c48056d, 0x91dc38dd, + 0xf863d885, 0x3f3b5872, 0x163e495b, 0x7bcbd88f, + 0xd679aa1d, 0x67e38d5f, 0x73ff9fb5, 0x12afb738, + 0x5164cae7, 0xdadbbfdd, 0x1c090801, 0xb01f0939, + 0x6c02a2a3, 0xecf004a3, 0x3b7a9a41, 0x15a1721a, + 0x4566d9e3, 0x8585af51, 0x132a82a9, 0x75c1d73e, + 0x59367cda, 0x1b6e3d41, 0x21185036, 0x45a3869d, + 0x4d89b4d0, 0x0c252e62, 0xb1f775e0, 0x25fe6461, + 0x6ea557ca, 0x72de24da, 0x7afe7167, 0xf903c177, + 0xfb3b5df6, 0x53ae314e, 0x12b3c269, 0x410530f9, + 0xefb12775, 0xd9f9b5a8, 0xc65bb923, 0x974a487a, + 0x8f22da37, 0x7a5e01b4, 0x62fa524f, 0x52935264, + 0x33566bf9, 0x81cdadf8, 0x486aca16, 0x44c554a8, + 0x29154ec7, 0xda27a364, 0x5572e97c, 0x6ba66481, + 0x444a0976, 0x31fddee2, 0xc83d9f6b, 0xdf64aba6, + 0xf1899c17, 0x0f5ac882, 0x14fef665, 0xadc18fd5, + 0x12c87422, 0xd46b3903, 0x27d81e56, 0xb2152aa1, + 0x8c125d4e, 0x50c9789f, 0x58cfa12c, 0xd9d713fd, + 0x0a7eadbd, 0xa8ec8502, 0x2c4c2782, 0xd6ab6211, + 0x26ffd388, 0x9e32fc4e, 0x907b3da4, 0xd2da4a5e, + 0x1852d599, 0xe275c3cb, 0x0199c46d, 0x84362043, + 0xb943e1c1, 0x07caf7fd, 0xd1e76143, 0x69f45753, + 0x3ed9e32f, 0x094a146d, 0x350d62cd, 0x0e4e82ec, + 0x046a72ad, 0x260a7cfe, 0xcf1b1b01, 0x0c47e3b7, + 0x39d8b04d, 0x12b7f841, 0xdb817c0b, 0xf6eddea9, + 0x5ae7e99a, 0x6b14bcff, 0xa218a9d3, 0x26ddce0e, + 0xa181cf83, 0xf397776d, 0xcd658f3d, 0x2dc20acd, + 0x1cdadd8f, 0xc3162f29, 0x0c2e8ea5, 0x68ac7a34, + 0x907be502, 0x30e36c33, 0x2be0152c, 0x07313162, + 0x4aa04ea1, 0x41ab4f70, 0xf081c972, 0x40236060, + 0x8e12abf4, 0x87011de0, 0x23e9a233, 0x69196db9, + 0xee730d17, 0x4f76f309, 0x230a4ed3, 0x762fc229, + 0x81f05cff, 0x158bf887, 0xeb797082, 0xcdc4b233, + 0x2a95bcc6, 0xca31ae95, 0xa08b0641, 0xf7afd5c3, + 0xe897fe64, 0x8f4b6700, 0xbdc16cb3, 0xcbd1f21c, + 0x010dc4db, 0x7564ee3c, 0x4f72e548, 0x2eb570be, + 0xb9a591cd, 0xb0464c00, 0x403a220e, 0xdba99ade, + 0xde2f3296, 0xf52435ec, 0xf1cad50f, 0xab7f1d23, + 0xd5b39959, 0x386e283c, 0xa05b3100, 0x4fbe5996, + 0xbb843f3e, 0xb5201b7f, 0x58128d14, 0x76dc989a, + 0xe22cb087, 0x5e35abff, 0x4e78da65, 0x9b52b9d3, + 0xdfaab4ec, 0x88fc21b3, 0x962c95db, 0x57f03c10, + 0x715b215b, 0xb21e8b61, 0x33e407c4, 0xbb47e2ad, + 0x00f66ba8, 0x6d9938a2, 0x8a5a2463, 0x533c8f1b, + 0x29a86ded, 0x3f9db30c, 0xad4d6c99, 0xdd49bbde, + 0xf2c5f2e1, 0xdfdabd6d, 0x7f2c0b19, 0xcc530e26, + 0xd6cc02da, 0x9be9c049, 0x32696ef0, 0x10249045, + 0x740358e3, 0x5e5897b9, 0xfde98d91, 0x6fb03f8b, + 0x00ed5554, 0x32682ea8, 0x7a4f8c67, 0x278298b2, + 0xe9be3802, 0x90796634, 0xcffeb5da, 0x0fc3a8ad, + 0x1d343257, 0xc287c137, 0xe454ad5c, 0x22dc184a, + 0x8d004fb8, 0xbf351b1a, 0xe2b495bb, 0x7ad715ec, + 0xbcf2626b, 0x63d000fb, 0x55df8518, 0x5498af42, + 0x9576e995, 0x93dc9c6d, 0x02f0a5fb, 0xd02c362f, + 0x4080199d, 0x6e000422, 0xf6d5cdf8, 0x1823883d, + 0xa5aeb6e8, 0x4aae7d06, 0xac1a7a81, 0x057daf57, + 0x8a59c175, 0x1ec74c3a, 0xdeb98b1e, 0xd0c81758, + 0x6b9f371b, 0x051038ca, 0xdcdf6141, 0x41afd3e5, + 0x4eb7eb28, 0x2e6db21e, 0x84ba2871, 0xf23f18b1, + 0xa61aa210, 0xf5da7d15, 0x74e610fe, 0x62643380, + 0x30337d81, 0x83fa408e, 0x11ba665e, 0x570b5820, + 0x544e3bd9, 0x94c4b5ea, 0x1248124f, 0xffb700b7, + 0xf652b383, 0x94e6752a, 0x34a2b6fe, 0x56d44674, + 0x35f81c5f, 0x4b341590, 0x1e05b531, 0x733dc637, + 0xe94070ab, 0x0711157a, 0x3510f6f5, 0xd278861e, + 0x2dd16729, 0xcb1506e9, 0xf9fc19bd, 0xe254035f, + 0xa331c089, 0xebebe6ba, 0x1ef423f2, 0x84f0d6a5, + 0x6b27a0a2, 0x06c30ad0, 0xbc4488f8, 0x85ba9523, + 0xa4bbc7ab, 0x54e55344, 0x046b2e6d, 0x3d0a9d4a, + 0x0f028c91, 0x82829d85, 0xea1bb2b3, 0xd066ab69, + 0x0626118c, 0x2b92d309, 0xf839aba7, 0xf9707a09, + 0xa958657d, 0x8d1c4bd7, 0x161330fb, 0xdae35b80, + 0xb9d1468c, 0xe256973a, 0x81151c52, 0x67ea2f7e, + 0xbe73b2ad, 0x998c32e5, 0x165ed2c3, 0xe2906b51, + 0x22c391c6, 0x6f72b24a, 0x91f2995a, 0x787f505b, + 0x4e60be80, 0x76d83d97, 0xbf096ed7, 0x84b0c455, + 0x2deea5b0, 0x717eccc3, 0x556cdc2e, 0xd16d8d63, + 0xcf37deb5, 0xb27afc09, 0xfdbdd1f3, 0xfc2d5241, + 0x7472f9fb, 0xe02a83b6, 0xae6e1d1b, 0xefb10c9d, + 0xef71e35b, 0x27028987, 0x4faddb26, 0x3dfdc2c9, + 0x844b666a, 0xbbe7e5f9, 0xa4bd432d, 0xcb03c2b7, + 0xea674d4c, 0xce4c1bef, 0xb960a15c, 0x634ac15e, + 0x141d4c99, 0x4a1d2fe8, 0xee41186e, 0xbbfec82c, + 0x268a8c09, 0x8fe242f3, 0x8e69b6bb, 0x59abb962, + 0x9d807b9c, 0x49255edd, 0x07cbf040, 0x897de163, + 0x11296620, 0x37d2d827, 0x832f6bb8, 0x851b9fda, + 0xac78c049, 0x4741660c, 0x2562c4c7, 0x8d6084fd, + 0x49cd08e4, 0x5216df79, 0x90ab8ac8, 0x75f11260, + 0xa4479a71, 0x30f1c0dd, 0xd4fd02ef, 0x7c6261f4, + 0x481f0394, 0x1dd3e399, 0x8d186637, 0xb80b74b5, + 0x7779c554, 0x3e528b01, 0x6833a961, 0x8a606c5f, + 0x4c69b595, 0xa4460ee7, 0xf9b90146, 0xe39f674e, + 0x33eb34fa, 0xc9671029, 0xa1cbd84b, 0x13414da3, + 0xb737ca61, 0xd6b9350a, 0xe7304d09, 0xe3e8fbae, + 0x63dc5e6d, 0x76257731, 0x5e80208f, 0x476b22e5, + 0xf8ac2367, 0xeadd85f3, 0x5d571889, 0x982f7132, + 0xebfc9ac8, 0xf214633a, 0xb023efb7, 0x952b4086, + 0xb886c81c, 0xd255f5d0, 0x41f08f64, 0x5e218efd, + 0x3116a9f2, 0x9dea7e8b, 0x26f6b324, 0x5b497baa, + 0x6370fd01, 0xe490f76d, 0x78481f39, 0xf5da7981, + 0x37268740, 0xb4403434, 0x044a6553, 0x5fdafee8, + 0xd9410ec2, 0xf719a281, 0x0ea4a312, 0x99686113, + 0xd3ec543c, 0x50ec7001, 0x10157efd, 0xee2f670a, + 0xbafc17e1, 0x3d18ddcb, 0xe245b888, 0x14e97e11, + 0xd62931eb, 0x95bc0362, 0x84c8c67b, 0xfec11642, + 0x76ba2423, 0xc6b26d69, 0xd8d5f21f, 0xe8d5c5d4, + 0x32e59438, 0xd53cd657, 0xaac468e3, 0x195cedd2, + 0xb6308766, 0xb248621e, 0x58ceb77f, 0x95091c29, + 0x783a0d93, 0xd1b7bf05, 0xfad79ca2, 0xb345de4f, + 0xccb9b316, 0x29100335, 0x579e38c3, 0x8d8d9792, + 0x49885605, 0xa925977c, 0x9233ce16, 0x8e216279, + 0xd43432bd, 0x5fb5391b, 0x77b3ee64, 0x993475b2, + 0xacd60cfe, 0x5d29b7a4, 0xfcd90541, 0x1bd605cc, + 0x644818e9, 0x3c70f039, 0x95b6c48f, 0xbc996b75, + 0xe0d26366, 0xbf745df8, 0x5b25ac82, 0x97fb1f3c, + 0x12278a9a, 0xf6468512, 0x19302bac, 0xe40dbc1d, + 0x3000f8af, 0x29e72ce0, 0x94473f6c, 0xfc953c2b, + 0x2e510d85, 0x854ee094, 0x1ff29d32, 0x273ee4a2, + 0x6a8a3111, 0x90081e2d, 0xba4cf2fb, 0x09787a35, + 0x0eac960c, 0x26c72a4d, 0x215fc5f4, 0xeb7cdaa6, + 0xf9f12153, 0xe2612ad4, 0x87d59c40, 0xbe547721, + 0xb97a79af, 0x84275cb2, 0x90a8043e, 0xf399eeb0, + 0xed4f0140, 0xabf06984, 0xb1c986bc, 0xc52a097c, + 0x6ab39eb2, 0x10b839d3, 0x1d4f8421, 0xe0acc983, + 0x642a48d3, 0x55477c83, 0xdb6a434a, 0xe16a144b, + 0x54f798a2, 0x5c4bb893, 0x7430ff0d, 0x0c148990, + 0x1dcf7a77, 0xe5eccdc8, 0x6b89978d, 0x59611b9d, + 0x7f152a6c, 0xceaf0993, 0x603f3294, 0x490493f6, + 0xfa21b3b4, 0x6eac05dc, 0xf445927a, 0x27d27aad, + 0x3c6ecb49, 0xfed8c21f, 0x03abb3fb, 0x36053db2, + 0x0b56acc2, 0xe42c3a13, 0x8e3eda55, 0x3c0303b8, + 0x6d10a1ea, 0x056c5fb0, 0xeae73bd4, 0x1b210654, + 0x6b4158d3, 0x2f5cbcd3, 0x10a2526a, 0x2192b8f4, + 0x3fe8a26e, 0xe1633585, 0xc999beaf, 0xa47fbde8, + 0x86749a43, 0x3d589a94, 0x24b48495, 0xc300cd16, + 0x67e0d514, 0xc32f2e04, 0x5251537d, 0xf97ad3de, + 0x526db56d, 0xecb36dbc, 0xdaf8cfdc, 0x8fc8023a, + 0xd9761a13, 0xc328a3fa, 0xcb40468e, 0x1c034b70, + 0x4fed5260, 0x37f3949b, 0xebbd66bf, 0x3e098c74, + 0x9b46d2d3, 0x7f50df4e, 0x09e1d50c, 0x3e9e7fe9, + 0x3a6d8044, 0x5ffc8eca, 0x0a379483, 0xa631f53b, + 0xb31c40ec, 0x68f6049a, 0xa2874420, 0x675b6dfc, + 0x0f678b6e, 0x1713ae7b, 0x983740f7, 0x8517a68a, + 0x634368b8, 0x456f0ef4, 0x8825dc99, 0x43228040, + 0x057ad0e3, 0x9a3fcf9b, 0xf5edf5ec, 0x6907b863, + 0x4bbbdb88, 0x8285df62, 0x92a72a6f, 0xbae4db92, + 0x03c8140c, 0x190ca181, 0x498626d7, 0x341735de, + 0xda7a1c38, 0x2cde8027, 0x3ee499d8, 0xbac79e65, + 0xed6327ed, 0x02b0fae6, 0x9b7e7d27, 0xe20cd851, + 0x8d3c6cbe, 0xf73efa7c, 0x0ae22cad, 0x02655922, + 0xbb39e248, 0x12c5ad75, 0xc9bf9fd2, 0x7aab9ede, + 0x9d4ad3b9, 0xbd86bed0, 0xd195dd59, 0x3f40c949, + 0x170fc4ed, 0x67e8b251, 0x27cfb5bb, 0x878e086e, + 0x26978ef1, 0x5641ce60, 0x35ed9ee2, 0xf1573d78, + 0xb38c597c, 0x26eaca4a, 0x7cbb1ffc, 0x97ab5665, + 0xf77f3895, 0xe75e3cd1, 0xa1539199, 0x2f95841b, + 0xc1c9f557, 0x0cc092d7, 0x0198ab46, 0xc715c99c, + 0xf32ea94a, 0xd238ab3c, 0xbbc72b3e, 0xd5f0c114, + 0x245069f6, 0x5b038f4e, 0xa02cefaf, 0x0d6d00ef, + 0xec0997a0, 0xebd8154a, 0xe61c2dbc, 0x03df4ad7, + 0x7691e287, 0x587c8e64, 0x26a9357b, 0xf749f82b, + 0xfd616b96, 0xee2052ba, 0xc40641cb, 0x97349e2b, + 0xbbf18705, 0xcd3b419d, 0x590d24aa, 0x20c062cb, + 0xbba6b8ad, 0x447d93ee, 0x027d5cde, 0x0b9c23e2, + 0xe3900004, 0xedaaab8b, 0xd7b38db6, 0xba844d4d, + 0x92558f8a, 0xfe621e13, 0x213cb29c, 0x29993007, + 0xb438d781, 0x0fc20d8c, 0xa09f0015, 0x3c07197c, + 0x0cefeaac, 0xd4de71e7, 0xdb26ec49, 0xc2df8c07, + 0x028fae43, 0x209ccc99, 0xa2da8940, 0xf877bfed, + 0x63a09535, 0xe1644b8f, 0x073af648, 0xf6514463, + 0x57435bcd, 0x9751d9d2, 0xd689317c, 0xf48f7e2b, + 0xa76a5318, 0x3e0af0a2, 0x61cdae90, 0x2627309c, + 0x29803090, 0xca240a7e, 0x8727b59f, 0x84a937ef, + 0x4c328f24, 0xaf8745fa, 0x3f0d11e8, 0xc5cf0654, + 0x60ff52f6, 0xfd2acc06, 0xbde069f3, 0x057ab2a2, + 0xab858324, 0x165f0e76, 0xe5cbb35c, 0xfbee56df, + 0xc38ecdbf, 0x199d6427, 0xdc225664, 0x529f5559, + 0x18a3ad06, 0x76c3beb0, 0x26f5977a, 0x9d4cda55, + 0x9b56d5fd, 0x6523056b, 0x7efd4a07, 0x76a20158, + 0xa442251f, 0x45bcf18c, 0xcf7775bc, 0x243b9895, + 0xb6a684f9, 0x9affd53c, 0x72dee665, 0xa1d56f3f, + 0x81999ff3, 0x0f24f2f2, 0x1dbc12ca, 0x3b3200c5, + 0x299738a1, 0x8b666079, 0xfa30a81a, 0x187d74b3, + 0x2b6df7c9, 0xeea35aa4, 0x2fc5e5e1, 0xb8012839, + 0x5af6c5f6, 0xf799bbe4, 0xce094606, 0x30b33ffc, + 0xb44886b1, 0xdbf56004, 0x0c40a419, 0xa0ab4bfd, + 0x124c455d, 0x61ec6909, 0x018870b3, 0xc39f9766, + 0x963872f8, 0xd42bc6d0, 0xf67f9879, 0x02cd871d, + 0xc1d5637a, 0xd6c96978, 0x529741ed, 0x44be5dd0, + 0xf3ec45eb, 0x9f376f69, 0x6973eaba, 0x25b0dba7, + 0x0637fda1, 0x8cb68991, 0xac46cb0a, 0x565158e1, + 0xb28f7c57, 0x3eb4f15a, 0x72950c88, 0x6a619bad, + 0x148b76dc, 0xa09ea3e4, 0x9c193546, 0xa25b117a, + 0x37f8bc08, 0xfd64f530, 0xcd68fc93, 0xb9e0ddd1, + 0xb5b6ff25, 0xabe2f486, 0x996a37c6, 0x7d4dce22, + 0x387fb3f5, 0x52aa26db, 0x68974e38, 0x33565eb1, + 0xb8c8da3e, 0xb6738101, 0xb4649e75, 0xcf40f52d, + 0xf284c2f5, 0x32a88e0d, 0x1c0ac5eb, 0xe7278fe9, + 0xefa1a48d, 0x86548057, 0x1b5eee70, 0xc7ae86f9, + 0xce9cc7b8, 0x051e2c9d, 0xdd51ab4b, 0xcd958b36, + 0x6684eec9, 0x36c0818b, 0x731ef23f, 0x484eb066, + 0x971ecdbc, 0x8f62ca15, 0x887b3c1f, 0x23a530f0, + 0xb8571c8d, 0xfd2e203f, 0xa4d9b532, 0x3670b7e5, + 0x48aca979, 0x5c6da253, 0xda40e623, 0xccd03cf2, + 0x7195a73c, 0x9c14664c, 0x96edf703, 0x978068ac, + 0x4de690d5, 0x82477b24, 0x0b0bbb57, 0xda6cca18, + 0x3b27980b, 0xf3420afe, 0xfe948a75, 0xc7f4bbf7, + 0xbb2dacbf, 0x5bebd870, 0x7cb24760, 0x549d633a, + 0x0f4c3073, 0x5b291739, 0x2898f98e, 0x9da196d6, + 0x99e2ceed, 0xe73d2862, 0xc1b888b7, 0xcc7a4be7, + 0x9533d4b0, 0x743c4b0e, 0xbd956640, 0x5f4bee9c, + 0x52c7e7f6, 0xe7939211, 0x02adf5bd, 0xeb7474cc, + 0x2595d910, 0xe5bb3450, 0xe9ef73e4, 0xfdee31f9, + 0xc9fc4af9, 0x73c6146e, 0x114a1886, 0x951ffda8, + 0x47527801, 0x4c6d7318, 0x04084f88, 0x9cd54119, + 0xe338b72c, 0xeecbef0a, 0x3b239d1d, 0x90fb59fc, + 0x3a34983c, 0x0399530f, 0x8082622e, 0x3f88b59c, + 0x7d42358c, 0xd49a0b4e, 0xbd6448c6, 0x12790e7a, + 0x14a1289f, 0x4a9254e0, 0x8dce08db, 0xe028f15c, + 0x92bfc22d, 0x7126b931, 0xa20e4b32, 0x3d4490a1, + 0xd2782790, 0x9ba62cd5, 0x412c5365, 0xd4da688b, + 0xebe54bbe, 0x2072bbfb, 0xe3b9f9aa, 0xc74eaa7e, + 0x11686f30, 0xd16b5eea, 0x101e34a9, 0xad67eaeb, + 0xf4270864, 0xec48dbd5, 0xd721d62f, 0x825dac1d, + 0x1d47483e, 0x1b77d264, 0xe8a377e7, 0xf87f5507, + 0x1f86b80e, 0x5e7a72aa, 0x0590c0cc, 0x880671ca, + 0x74cbe820, 0x515a490f, 0xe84f0908, 0x680c4d66, + 0x48ab1a6d, 0xee76c420, 0x5167b090, 0x22edd2a2, + 0xe7cbd936, 0x067475a0, 0xed376b1d, 0xa27789ef, + 0x6d0e3287, 0x3378e79f, 0x75eec67c, 0xd8763174, + 0x457722c3, 0x0c24138c, 0xaf6a5b6a, 0x18de8027, + 0x8b4aab64, 0x8f941c60, 0x86e1139c, 0xbf933f85, + 0x320f7acb, 0xa2f15469, 0x920bac0b, 0x767525e4, + 0x442c7330, 0x019b4724, 0x021fdb7e, 0x4dd8eb46, + 0x6cfbfcb7, 0x6ccc49eb, 0x62fa83a4, 0xce0001ac, + 0x25e8d0d2, 0x3f13db90, 0x436d0158, 0x28af7681, + 0xe823940b, 0xb0ab1540, 0x4cf64341, 0x632e81aa, + 0x1e0fa8f4, 0xfbfe12c3, 0x19ff0563, 0xb8a8da95, + 0xc72db188, 0x97cdc50e, 0x0b4fa832, 0x4e701009, + 0x13b707a0, 0x14b608b4, 0x33304e41, 0xc935ae8b, + 0x57f495f1, 0x850b3117, 0x25d217b6, 0x38b9f25e, + 0x87c6abad, 0x3c5d1438, 0x24fe34a6, 0xc3a9edae, + 0xa3274c62, 0x7ac0fdd2, 0xc17a551d, 0x75cc9499, + 0x34b9fac9, 0x344835af, 0x098d8328, 0x1ea621cc, + 0xc23e2822, 0xc227d7ca, 0x9220c07c, 0xa6f83db4, + 0x95c0f54d, 0x4ec39d38, 0x2796dbc1, 0x8ee3a2bb, + 0xe9be030b, 0x664319d0, 0x46fa2f02, 0x2c777f4a, + 0x17d50776, 0xf24d9bd5, 0xc8ef9a1b, 0x5a7a4209, + 0xbf6a8d1a, 0xe662c92c, 0x0f9a0d4e, 0xcd550b8a, + +#else /* Big endian */ + 0xa505ecc5, 0x6c23cac8, 0x34d34ac4, 0xe1d9027e, + 0x920e40f4, 0x17796e94, 0x6d05486c, 0xdd38dc91, + 0x85d863f8, 0x72583b3f, 0x5b493e16, 0x8fd8cb7b, + 0x1daa79d6, 0x5f8de367, 0xb59fff73, 0x38b7af12, + 0xe7ca6451, 0xddbfdbda, 0x0108091c, 0x39091fb0, + 0xa3a2026c, 0xa304f0ec, 0x419a7a3b, 0x1a72a115, + 0xe3d96645, 0x51af8585, 0xa9822a13, 0x3ed7c175, + 0xda7c3659, 0x413d6e1b, 0x36501821, 0x9d86a345, + 0xd0b4894d, 0x622e250c, 0xe075f7b1, 0x6164fe25, + 0xca57a56e, 0xda24de72, 0x6771fe7a, 0x77c103f9, + 0xf65d3bfb, 0x4e31ae53, 0x69c2b312, 0xf9300541, + 0x7527b1ef, 0xa8b5f9d9, 0x23b95bc6, 0x7a484a97, + 0x37da228f, 0xb4015e7a, 0x4f52fa62, 0x64529352, + 0xf96b5633, 0xf8adcd81, 0x16ca6a48, 0xa854c544, + 0xc74e1529, 0x64a327da, 0x7ce97255, 0x8164a66b, + 0x76094a44, 0xe2defd31, 0x6b9f3dc8, 0xa6ab64df, + 0x179c89f1, 0x82c85a0f, 0x65f6fe14, 0xd58fc1ad, + 0x2274c812, 0x03396bd4, 0x561ed827, 0xa12a15b2, + 0x4e5d128c, 0x9f78c950, 0x2ca1cf58, 0xfd13d7d9, + 0xbdad7e0a, 0x0285eca8, 0x82274c2c, 0x1162abd6, + 0x88d3ff26, 0x4efc329e, 0xa43d7b90, 0x5e4adad2, + 0x99d55218, 0xcbc375e2, 0x6dc49901, 0x43203684, + 0xc1e143b9, 0xfdf7ca07, 0x4361e7d1, 0x5357f469, + 0x2fe3d93e, 0x6d144a09, 0xcd620d35, 0xec824e0e, + 0xad726a04, 0xfe7c0a26, 0x011b1bcf, 0xb7e3470c, + 0x4db0d839, 0x41f8b712, 0x0b7c81db, 0xa9deedf6, + 0x9ae9e75a, 0xffbc146b, 0xd3a918a2, 0x0ecedd26, + 0x83cf81a1, 0x6d7797f3, 0x3d8f65cd, 0xcd0ac22d, + 0x8fddda1c, 0x292f16c3, 0xa58e2e0c, 0x347aac68, + 0x02e57b90, 0x336ce330, 0x2c15e02b, 0x62313107, + 0xa14ea04a, 0x704fab41, 0x72c981f0, 0x60602340, + 0xf4ab128e, 0xe01d0187, 0x33a2e923, 0xb96d1969, + 0x170d73ee, 0x09f3764f, 0xd34e0a23, 0x29c22f76, + 0xff5cf081, 0x87f88b15, 0x827079eb, 0x33b2c4cd, + 0xc6bc952a, 0x95ae31ca, 0x41068ba0, 0xc3d5aff7, + 0x64fe97e8, 0x00674b8f, 0xb36cc1bd, 0x1cf2d1cb, + 0xdbc40d01, 0x3cee6475, 0x48e5724f, 0xbe70b52e, + 0xcd91a5b9, 0x004c46b0, 0x0e223a40, 0xde9aa9db, + 0x96322fde, 0xec3524f5, 0x0fd5caf1, 0x231d7fab, + 0x5999b3d5, 0x3c286e38, 0x00315ba0, 0x9659be4f, + 0x3e3f84bb, 0x7f1b20b5, 0x148d1258, 0x9a98dc76, + 0x87b02ce2, 0xffab355e, 0x65da784e, 0xd3b9529b, + 0xecb4aadf, 0xb321fc88, 0xdb952c96, 0x103cf057, + 0x5b215b71, 0x618b1eb2, 0xc407e433, 0xade247bb, + 0xa86bf600, 0xa238996d, 0x63245a8a, 0x1b8f3c53, + 0xed6da829, 0x0cb39d3f, 0x996c4dad, 0xdebb49dd, + 0xe1f2c5f2, 0x6dbddadf, 0x190b2c7f, 0x260e53cc, + 0xda02ccd6, 0x49c0e99b, 0xf06e6932, 0x45902410, + 0xe3580374, 0xb997585e, 0x918de9fd, 0x8b3fb06f, + 0x5455ed00, 0xa82e6832, 0x678c4f7a, 0xb2988227, + 0x0238bee9, 0x34667990, 0xdab5fecf, 0xada8c30f, + 0x5732341d, 0x37c187c2, 0x5cad54e4, 0x4a18dc22, + 0xb84f008d, 0x1a1b35bf, 0xbb95b4e2, 0xec15d77a, + 0x6b62f2bc, 0xfb00d063, 0x1885df55, 0x42af9854, + 0x95e97695, 0x6d9cdc93, 0xfba5f002, 0x2f362cd0, + 0x9d198040, 0x2204006e, 0xf8cdd5f6, 0x3d882318, + 0xe8b6aea5, 0x067dae4a, 0x817a1aac, 0x57af7d05, + 0x75c1598a, 0x3a4cc71e, 0x1e8bb9de, 0x5817c8d0, + 0x1b379f6b, 0xca381005, 0x4161dfdc, 0xe5d3af41, + 0x28ebb74e, 0x1eb26d2e, 0x7128ba84, 0xb1183ff2, + 0x10a21aa6, 0x157ddaf5, 0xfe10e674, 0x80336462, + 0x817d3330, 0x8e40fa83, 0x5e66ba11, 0x20580b57, + 0xd93b4e54, 0xeab5c494, 0x4f124812, 0xb700b7ff, + 0x83b352f6, 0x2a75e694, 0xfeb6a234, 0x7446d456, + 0x5f1cf835, 0x9015344b, 0x31b5051e, 0x37c63d73, + 0xab7040e9, 0x7a151107, 0xf5f61035, 0x1e8678d2, + 0x2967d12d, 0xe90615cb, 0xbd19fcf9, 0x5f0354e2, + 0x89c031a3, 0xbae6ebeb, 0xf223f41e, 0xa5d6f084, + 0xa2a0276b, 0xd00ac306, 0xf88844bc, 0x2395ba85, + 0xabc7bba4, 0x4453e554, 0x6d2e6b04, 0x4a9d0a3d, + 0x918c020f, 0x859d8282, 0xb3b21bea, 0x69ab66d0, + 0x8c112606, 0x09d3922b, 0xa7ab39f8, 0x097a70f9, + 0x7d6558a9, 0xd74b1c8d, 0xfb301316, 0x805be3da, + 0x8c46d1b9, 0x3a9756e2, 0x521c1581, 0x7e2fea67, + 0xadb273be, 0xe5328c99, 0xc3d25e16, 0x516b90e2, + 0xc691c322, 0x4ab2726f, 0x5a99f291, 0x5b507f78, + 0x80be604e, 0x973dd876, 0xd76e09bf, 0x55c4b084, + 0xb0a5ee2d, 0xc3cc7e71, 0x2edc6c55, 0x638d6dd1, + 0xb5de37cf, 0x09fc7ab2, 0xf3d1bdfd, 0x41522dfc, + 0xfbf97274, 0xb6832ae0, 0x1b1d6eae, 0x9d0cb1ef, + 0x5be371ef, 0x87890227, 0x26dbad4f, 0xc9c2fd3d, + 0x6a664b84, 0xf9e5e7bb, 0x2d43bda4, 0xb7c203cb, + 0x4c4d67ea, 0xef1b4cce, 0x5ca160b9, 0x5ec14a63, + 0x994c1d14, 0xe82f1d4a, 0x6e1841ee, 0x2cc8febb, + 0x098c8a26, 0xf342e28f, 0xbbb6698e, 0x62b9ab59, + 0x9c7b809d, 0xdd5e2549, 0x40f0cb07, 0x63e17d89, + 0x20662911, 0x27d8d237, 0xb86b2f83, 0xda9f1b85, + 0x49c078ac, 0x0c664147, 0xc7c46225, 0xfd84608d, + 0xe408cd49, 0x79df1652, 0xc88aab90, 0x6012f175, + 0x719a47a4, 0xddc0f130, 0xef02fdd4, 0xf461627c, + 0x94031f48, 0x99e3d31d, 0x3766188d, 0xb5740bb8, + 0x54c57977, 0x018b523e, 0x61a93368, 0x5f6c608a, + 0x95b5694c, 0xe70e46a4, 0x4601b9f9, 0x4e679fe3, + 0xfa34eb33, 0x291067c9, 0x4bd8cba1, 0xa34d4113, + 0x61ca37b7, 0x0a35b9d6, 0x094d30e7, 0xaefbe8e3, + 0x6d5edc63, 0x31772576, 0x8f20805e, 0xe5226b47, + 0x6723acf8, 0xf385ddea, 0x8918575d, 0x32712f98, + 0xc89afceb, 0x3a6314f2, 0xb7ef23b0, 0x86402b95, + 0x1cc886b8, 0xd0f555d2, 0x648ff041, 0xfd8e215e, + 0xf2a91631, 0x8b7eea9d, 0x24b3f626, 0xaa7b495b, + 0x01fd7063, 0x6df790e4, 0x391f4878, 0x8179daf5, + 0x40872637, 0x343440b4, 0x53654a04, 0xe8feda5f, + 0xc20e41d9, 0x81a219f7, 0x12a3a40e, 0x13616899, + 0x3c54ecd3, 0x0170ec50, 0xfd7e1510, 0x0a672fee, + 0xe117fcba, 0xcbdd183d, 0x88b845e2, 0x117ee914, + 0xeb3129d6, 0x6203bc95, 0x7bc6c884, 0x4216c1fe, + 0x2324ba76, 0x696db2c6, 0x1ff2d5d8, 0xd4c5d5e8, + 0x3894e532, 0x57d63cd5, 0xe368c4aa, 0xd2ed5c19, + 0x668730b6, 0x1e6248b2, 0x7fb7ce58, 0x291c0995, + 0x930d3a78, 0x05bfb7d1, 0xa29cd7fa, 0x4fde45b3, + 0x16b3b9cc, 0x35031029, 0xc3389e57, 0x92978d8d, + 0x05568849, 0x7c9725a9, 0x16ce3392, 0x7962218e, + 0xbd3234d4, 0x1b39b55f, 0x64eeb377, 0xb2753499, + 0xfe0cd6ac, 0xa4b7295d, 0x4105d9fc, 0xcc05d61b, + 0xe9184864, 0x39f0703c, 0x8fc4b695, 0x756b99bc, + 0x6663d2e0, 0xf85d74bf, 0x82ac255b, 0x3c1ffb97, + 0x9a8a2712, 0x128546f6, 0xac2b3019, 0x1dbc0de4, + 0xaff80030, 0xe02ce729, 0x6c3f4794, 0x2b3c95fc, + 0x850d512e, 0x94e04e85, 0x329df21f, 0xa2e43e27, + 0x11318a6a, 0x2d1e0890, 0xfbf24cba, 0x357a7809, + 0x0c96ac0e, 0x4d2ac726, 0xf4c55f21, 0xa6da7ceb, + 0x5321f1f9, 0xd42a61e2, 0x409cd587, 0x217754be, + 0xaf797ab9, 0xb25c2784, 0x3e04a890, 0xb0ee99f3, + 0x40014fed, 0x8469f0ab, 0xbc86c9b1, 0x7c092ac5, + 0xb29eb36a, 0xd339b810, 0x21844f1d, 0x83c9ace0, + 0xd3482a64, 0x837c4755, 0x4a436adb, 0x4b146ae1, + 0xa298f754, 0x93b84b5c, 0x0dff3074, 0x9089140c, + 0x777acf1d, 0xc8cdece5, 0x8d97896b, 0x9d1b6159, + 0x6c2a157f, 0x9309afce, 0x94323f60, 0xf6930449, + 0xb4b321fa, 0xdc05ac6e, 0x7a9245f4, 0xad7ad227, + 0x49cb6e3c, 0x1fc2d8fe, 0xfbb3ab03, 0xb23d0536, + 0xc2ac560b, 0x133a2ce4, 0x55da3e8e, 0xb803033c, + 0xeaa1106d, 0xb05f6c05, 0xd43be7ea, 0x5406211b, + 0xd358416b, 0xd3bc5c2f, 0x6a52a210, 0xf4b89221, + 0x6ea2e83f, 0x853563e1, 0xafbe99c9, 0xe8bd7fa4, + 0x439a7486, 0x949a583d, 0x9584b424, 0x16cd00c3, + 0x14d5e067, 0x042e2fc3, 0x7d535152, 0xded37af9, + 0x6db56d52, 0xbc6db3ec, 0xdccff8da, 0x3a02c88f, + 0x131a76d9, 0xfaa328c3, 0x8e4640cb, 0x704b031c, + 0x6052ed4f, 0x9b94f337, 0xbf66bdeb, 0x748c093e, + 0xd3d2469b, 0x4edf507f, 0x0cd5e109, 0xe97f9e3e, + 0x44806d3a, 0xca8efc5f, 0x8394370a, 0x3bf531a6, + 0xec401cb3, 0x9a04f668, 0x204487a2, 0xfc6d5b67, + 0x6e8b670f, 0x7bae1317, 0xf7403798, 0x8aa61785, + 0xb8684363, 0xf40e6f45, 0x99dc2588, 0x40802243, + 0xe3d07a05, 0x9bcf3f9a, 0xecf5edf5, 0x63b80769, + 0x88dbbb4b, 0x62df8582, 0x6f2aa792, 0x92dbe4ba, + 0x0c14c803, 0x81a10c19, 0xd7268649, 0xde351734, + 0x381c7ada, 0x2780de2c, 0xd899e43e, 0x659ec7ba, + 0xed2763ed, 0xe6fab002, 0x277d7e9b, 0x51d80ce2, + 0xbe6c3c8d, 0x7cfa3ef7, 0xad2ce20a, 0x22596502, + 0x48e239bb, 0x75adc512, 0xd29fbfc9, 0xde9eab7a, + 0xb9d34a9d, 0xd0be86bd, 0x59dd95d1, 0x49c9403f, + 0xedc40f17, 0x51b2e867, 0xbbb5cf27, 0x6e088e87, + 0xf18e9726, 0x60ce4156, 0xe29eed35, 0x783d57f1, + 0x7c598cb3, 0x4acaea26, 0xfc1fbb7c, 0x6556ab97, + 0x95387ff7, 0xd13c5ee7, 0x999153a1, 0x1b84952f, + 0x57f5c9c1, 0xd792c00c, 0x46ab9801, 0x9cc915c7, + 0x4aa92ef3, 0x3cab38d2, 0x3e2bc7bb, 0x14c1f0d5, + 0xf6695024, 0x4e8f035b, 0xafef2ca0, 0xef006d0d, + 0xa09709ec, 0x4a15d8eb, 0xbc2d1ce6, 0xd74adf03, + 0x87e29176, 0x648e7c58, 0x7b35a926, 0x2bf849f7, + 0x966b61fd, 0xba5220ee, 0xcb4106c4, 0x2b9e3497, + 0x0587f1bb, 0x9d413bcd, 0xaa240d59, 0xcb62c020, + 0xadb8a6bb, 0xee937d44, 0xde5c7d02, 0xe2239c0b, + 0x040090e3, 0x8babaaed, 0xb68db3d7, 0x4d4d84ba, + 0x8a8f5592, 0x131e62fe, 0x9cb23c21, 0x07309929, + 0x81d738b4, 0x8c0dc20f, 0x15009fa0, 0x7c19073c, + 0xaceaef0c, 0xe771ded4, 0x49ec26db, 0x078cdfc2, + 0x43ae8f02, 0x99cc9c20, 0x4089daa2, 0xedbf77f8, + 0x3595a063, 0x8f4b64e1, 0x48f63a07, 0x634451f6, + 0xcd5b4357, 0xd2d95197, 0x7c3189d6, 0x2b7e8ff4, + 0x18536aa7, 0xa2f00a3e, 0x90aecd61, 0x9c302726, + 0x90308029, 0x7e0a24ca, 0x9fb52787, 0xef37a984, + 0x248f324c, 0xfa4587af, 0xe8110d3f, 0x5406cfc5, + 0xf652ff60, 0x06cc2afd, 0xf369e0bd, 0xa2b27a05, + 0x248385ab, 0x760e5f16, 0x5cb3cbe5, 0xdf56eefb, + 0xbfcd8ec3, 0x27649d19, 0x645622dc, 0x59559f52, + 0x06ada318, 0xb0bec376, 0x7a97f526, 0x55da4c9d, + 0xfdd5569b, 0x6b052365, 0x074afd7e, 0x5801a276, + 0x1f2542a4, 0x8cf1bc45, 0xbc7577cf, 0x95983b24, + 0xf984a6b6, 0x3cd5ff9a, 0x65e6de72, 0x3f6fd5a1, + 0xf39f9981, 0xf2f2240f, 0xca12bc1d, 0xc500323b, + 0xa1389729, 0x7960668b, 0x1aa830fa, 0xb3747d18, + 0xc9f76d2b, 0xa45aa3ee, 0xe1e5c52f, 0x392801b8, + 0xf6c5f65a, 0xe4bb99f7, 0x064609ce, 0xfc3fb330, + 0xb18648b4, 0x0460f5db, 0x19a4400c, 0xfd4baba0, + 0x5d454c12, 0x0969ec61, 0xb3708801, 0x66979fc3, + 0xf8723896, 0xd0c62bd4, 0x79987ff6, 0x1d87cd02, + 0x7a63d5c1, 0x7869c9d6, 0xed419752, 0xd05dbe44, + 0xeb45ecf3, 0x696f379f, 0xbaea7369, 0xa7dbb025, + 0xa1fd3706, 0x9189b68c, 0x0acb46ac, 0xe1585156, + 0x577c8fb2, 0x5af1b43e, 0x880c9572, 0xad9b616a, + 0xdc768b14, 0xe4a39ea0, 0x4635199c, 0x7a115ba2, + 0x08bcf837, 0x30f564fd, 0x93fc68cd, 0xd1dde0b9, + 0x25ffb6b5, 0x86f4e2ab, 0xc6376a99, 0x22ce4d7d, + 0xf5b37f38, 0xdb26aa52, 0x384e9768, 0xb15e5633, + 0x3edac8b8, 0x018173b6, 0x759e64b4, 0x2df540cf, + 0xf5c284f2, 0x0d8ea832, 0xebc50a1c, 0xe98f27e7, + 0x8da4a1ef, 0x57805486, 0x70ee5e1b, 0xf986aec7, + 0xb8c79cce, 0x9d2c1e05, 0x4bab51dd, 0x368b95cd, + 0xc9ee8466, 0x8b81c036, 0x3ff21e73, 0x66b04e48, + 0xbccd1e97, 0x15ca628f, 0x1f3c7b88, 0xf030a523, + 0x8d1c57b8, 0x3f202efd, 0x32b5d9a4, 0xe5b77036, + 0x79a9ac48, 0x53a26d5c, 0x23e640da, 0xf23cd0cc, + 0x3ca79571, 0x4c66149c, 0x03f7ed96, 0xac688097, + 0xd590e64d, 0x247b4782, 0x57bb0b0b, 0x18ca6cda, + 0x0b98273b, 0xfe0a42f3, 0x758a94fe, 0xf7bbf4c7, + 0xbfac2dbb, 0x70d8eb5b, 0x6047b27c, 0x3a639d54, + 0x73304c0f, 0x3917295b, 0x8ef99828, 0xd696a19d, + 0xedcee299, 0x62283de7, 0xb788b8c1, 0xe74b7acc, + 0xb0d43395, 0x0e4b3c74, 0x406695bd, 0x9cee4b5f, + 0xf6e7c752, 0x119293e7, 0xbdf5ad02, 0xcc7474eb, + 0x10d99525, 0x5034bbe5, 0xe473efe9, 0xf931eefd, + 0xf94afcc9, 0x6e14c673, 0x86184a11, 0xa8fd1f95, + 0x01785247, 0x18736d4c, 0x884f0804, 0x1941d59c, + 0x2cb738e3, 0x0aefcbee, 0x1d9d233b, 0xfc59fb90, + 0x3c98343a, 0x0f539903, 0x2e628280, 0x9cb5883f, + 0x8c35427d, 0x4e0b9ad4, 0xc64864bd, 0x7a0e7912, + 0x9f28a114, 0xe054924a, 0xdb08ce8d, 0x5cf128e0, + 0x2dc2bf92, 0x31b92671, 0x324b0ea2, 0xa190443d, + 0x902778d2, 0xd52ca69b, 0x65532c41, 0x8b68dad4, + 0xbe4be5eb, 0xfbbb7220, 0xaaf9b9e3, 0x7eaa4ec7, + 0x306f6811, 0xea5e6bd1, 0xa9341e10, 0xebea67ad, + 0x640827f4, 0xd5db48ec, 0x2fd621d7, 0x1dac5d82, + 0x3e48471d, 0x64d2771b, 0xe777a3e8, 0x07557ff8, + 0x0eb8861f, 0xaa727a5e, 0xccc09005, 0xca710688, + 0x20e8cb74, 0x0f495a51, 0x08094fe8, 0x664d0c68, + 0x6d1aab48, 0x20c476ee, 0x90b06751, 0xa2d2ed22, + 0x36d9cbe7, 0xa0757406, 0x1d6b37ed, 0xef8977a2, + 0x87320e6d, 0x9fe77833, 0x7cc6ee75, 0x743176d8, + 0xc3227745, 0x8c13240c, 0x6a5b6aaf, 0x2780de18, + 0x64ab4a8b, 0x601c948f, 0x9c13e186, 0x853f93bf, + 0xcb7a0f32, 0x6954f1a2, 0x0bac0b92, 0xe4257576, + 0x30732c44, 0x24479b01, 0x7edb1f02, 0x46ebd84d, + 0xb7fcfb6c, 0xeb49cc6c, 0xa483fa62, 0xac0100ce, + 0xd2d0e825, 0x90db133f, 0x58016d43, 0x8176af28, + 0x0b9423e8, 0x4015abb0, 0x4143f64c, 0xaa812e63, + 0xf4a80f1e, 0xc312fefb, 0x6305ff19, 0x95daa8b8, + 0x88b12dc7, 0x0ec5cd97, 0x32a84f0b, 0x0910704e, + 0xa007b713, 0xb408b614, 0x414e3033, 0x8bae35c9, + 0xf195f457, 0x17310b85, 0xb617d225, 0x5ef2b938, + 0xadabc687, 0x38145d3c, 0xa634fe24, 0xaeeda9c3, + 0x624c27a3, 0xd2fdc07a, 0x1d557ac1, 0x9994cc75, + 0xc9fab934, 0xaf354834, 0x28838d09, 0xcc21a61e, + 0x22283ec2, 0xcad727c2, 0x7cc02092, 0xb43df8a6, + 0x4df5c095, 0x389dc34e, 0xc1db9627, 0xbba2e38e, + 0x0b03bee9, 0xd0194366, 0x022ffa46, 0x4a7f772c, + 0x7607d517, 0xd59b4df2, 0x1b9aefc8, 0x09427a5a, + 0x1a8d6abf, 0x2cc962e6, 0x4e0d9a0f, 0x8a0b55cd +#endif /* defined __ARMEB__ */ +}; + diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/SCE_ProcCommon.h b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/SCE_ProcCommon.h new file mode 100644 index 000000000..a550903d0 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/SCE_ProcCommon.h @@ -0,0 +1,93089 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef __SCE_ProcCommon_h__ +#define __SCE_ProcCommon_h__ + +#include + +#include "bsp_api.h" /* For Crypto Error codes */ +#include "SCE_module.h" + +/* ================================================================================ */ +/* ================ SCE ================ */ +/* ================================================================================ */ + +/** + * @brief Trusted Security IP (SCE) + */ +typedef struct +{ + union + { + __IOM uint32_t REG_00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_00H_b; + }; + union + { + __IOM uint32_t REG_04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_04H_b; + }; + union + { + __IOM uint32_t REG_08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_08H_b; + }; + union + { + __IOM uint32_t REG_0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_0CH_b; + }; + union + { + __IOM uint32_t REG_10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10H_b; + }; + union + { + __IOM uint32_t REG_14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14H_b; + }; + union + { + __IOM uint32_t REG_18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18H_b; + }; + union + { + __IOM uint32_t REG_1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CH_b; + }; + union + { + __IOM uint32_t REG_20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20H_b; + }; + union + { + __IOM uint32_t REG_24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24H_b; + }; + union + { + __IOM uint32_t REG_28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_28H_b; + }; + union + { + __IOM uint32_t REG_2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2CH_b; + }; + union + { + __IOM uint32_t REG_30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_30H_b; + }; + union + { + __IOM uint32_t REG_34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_34H_b; + }; + union + { + __IOM uint32_t REG_38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_38H_b; + }; + union + { + __IOM uint32_t REG_3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3CH_b; + }; + union + { + __IOM uint32_t REG_40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_40H_b; + }; + union + { + __IOM uint32_t REG_44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_44H_b; + }; + union + { + __IOM uint32_t REG_48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_48H_b; + }; + union + { + __IOM uint32_t REG_4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4CH_b; + }; + union + { + __IOM uint32_t REG_50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_50H_b; + }; + union + { + __IOM uint32_t REG_54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_54H_b; + }; + union + { + __IOM uint32_t REG_58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_58H_b; + }; + union + { + __IOM uint32_t REG_5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5CH_b; + }; + union + { + __IOM uint32_t REG_60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_60H_b; + }; + union + { + __IOM uint32_t REG_64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_64H_b; + }; + union + { + __IOM uint32_t REG_68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_68H_b; + }; + union + { + __IOM uint32_t REG_6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6CH_b; + }; + union + { + __IOM uint32_t REG_70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_70H_b; + }; + union + { + __IOM uint32_t REG_74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_74H_b; + }; + union + { + __IOM uint32_t REG_78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_78H_b; + }; + union + { + __IOM uint32_t REG_7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7CH_b; + }; + union + { + __IOM uint32_t REG_80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_80H_b; + }; + union + { + __IOM uint32_t REG_84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_84H_b; + }; + union + { + __IOM uint32_t REG_88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_88H_b; + }; + union + { + __IOM uint32_t REG_8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8CH_b; + }; + union + { + __IOM uint32_t REG_90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_90H_b; + }; + union + { + __IOM uint32_t REG_94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_94H_b; + }; + union + { + __IOM uint32_t REG_98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_98H_b; + }; + union + { + __IOM uint32_t REG_9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9CH_b; + }; + union + { + __IOM uint32_t REG_A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A0H_b; + }; + union + { + __IOM uint32_t REG_A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A4H_b; + }; + union + { + __IOM uint32_t REG_A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A8H_b; + }; + union + { + __IOM uint32_t REG_ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ACH_b; + }; + union + { + __IOM uint32_t REG_B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B0H_b; + }; + union + { + __IOM uint32_t REG_B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B4H_b; + }; + union + { + __IOM uint32_t REG_B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B8H_b; + }; + union + { + __IOM uint32_t REG_BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BCH_b; + }; + union + { + __IOM uint32_t REG_C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C0H_b; + }; + union + { + __IOM uint32_t REG_C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C4H_b; + }; + union + { + __IOM uint32_t REG_C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C8H_b; + }; + union + { + __IOM uint32_t REG_CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CCH_b; + }; + union + { + __IOM uint32_t REG_D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D0H_b; + }; + union + { + __IOM uint32_t REG_D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D4H_b; + }; + union + { + __IOM uint32_t REG_D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D8H_b; + }; + union + { + __IOM uint32_t REG_DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DCH_b; + }; + union + { + __IOM uint32_t REG_E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E0H_b; + }; + union + { + __IOM uint32_t REG_E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E4H_b; + }; + union + { + __IOM uint32_t REG_E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E8H_b; + }; + union + { + __IOM uint32_t REG_ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ECH_b; + }; + union + { + __IOM uint32_t REG_F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F0H_b; + }; + union + { + __IOM uint32_t REG_F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F4H_b; + }; + union + { + __IOM uint32_t REG_F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F8H_b; + }; + union + { + __IOM uint32_t REG_FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FCH_b; + }; + union + { + __IOM uint32_t REG_100H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_100H_b; + }; + union + { + __IOM uint32_t REG_104H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_104H_b; + }; + union + { + __IOM uint32_t REG_108H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_108H_b; + }; + union + { + __IOM uint32_t REG_10CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10CH_b; + }; + union + { + __IOM uint32_t REG_110H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_110H_b; + }; + union + { + __IOM uint32_t REG_114H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_114H_b; + }; + union + { + __IOM uint32_t REG_118H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_118H_b; + }; + union + { + __IOM uint32_t REG_11CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11CH_b; + }; + union + { + __IOM uint32_t REG_120H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_120H_b; + }; + union + { + __IOM uint32_t REG_124H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_124H_b; + }; + union + { + __IOM uint32_t REG_128H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_128H_b; + }; + union + { + __IOM uint32_t REG_12CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12CH_b; + }; + union + { + __IOM uint32_t REG_130H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_130H_b; + }; + union + { + __IOM uint32_t REG_134H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_134H_b; + }; + union + { + __IOM uint32_t REG_138H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_138H_b; + }; + union + { + __IOM uint32_t REG_13CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13CH_b; + }; + union + { + __IOM uint32_t REG_140H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_140H_b; + }; + union + { + __IOM uint32_t REG_144H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_144H_b; + }; + union + { + __IOM uint32_t REG_148H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_148H_b; + }; + union + { + __IOM uint32_t REG_14CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14CH_b; + }; + union + { + __IOM uint32_t REG_150H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_150H_b; + }; + union + { + __IOM uint32_t REG_154H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_154H_b; + }; + union + { + __IOM uint32_t REG_158H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_158H_b; + }; + union + { + __IOM uint32_t REG_15CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15CH_b; + }; + union + { + __IOM uint32_t REG_160H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_160H_b; + }; + union + { + __IOM uint32_t REG_164H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_164H_b; + }; + union + { + __IOM uint32_t REG_168H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_168H_b; + }; + union + { + __IOM uint32_t REG_16CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16CH_b; + }; + union + { + __IOM uint32_t REG_170H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_170H_b; + }; + union + { + __IOM uint32_t REG_174H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_174H_b; + }; + union + { + __IOM uint32_t REG_178H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_178H_b; + }; + union + { + __IOM uint32_t REG_17CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17CH_b; + }; + union + { + __IOM uint32_t REG_180H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_180H_b; + }; + union + { + __IOM uint32_t REG_184H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_184H_b; + }; + union + { + __IOM uint32_t REG_188H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_188H_b; + }; + union + { + __IOM uint32_t REG_18CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18CH_b; + }; + union + { + __IOM uint32_t REG_190H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_190H_b; + }; + union + { + __IOM uint32_t REG_194H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_194H_b; + }; + union + { + __IOM uint32_t REG_198H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_198H_b; + }; + union + { + __IOM uint32_t REG_19CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19CH_b; + }; + union + { + __IOM uint32_t REG_1A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A0H_b; + }; + union + { + __IOM uint32_t REG_1A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A4H_b; + }; + union + { + __IOM uint32_t REG_1A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A8H_b; + }; + union + { + __IOM uint32_t REG_1ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ACH_b; + }; + union + { + __IOM uint32_t REG_1B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B0H_b; + }; + union + { + __IOM uint32_t REG_1B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B4H_b; + }; + union + { + __IOM uint32_t REG_1B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B8H_b; + }; + union + { + __IOM uint32_t REG_1BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BCH_b; + }; + union + { + __IOM uint32_t REG_1C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C0H_b; + }; + union + { + __IOM uint32_t REG_1C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C4H_b; + }; + union + { + __IOM uint32_t REG_1C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C8H_b; + }; + union + { + __IOM uint32_t REG_1CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CCH_b; + }; + union + { + __IOM uint32_t REG_1D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D0H_b; + }; + union + { + __IOM uint32_t REG_1D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D4H_b; + }; + union + { + __IOM uint32_t REG_1D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D8H_b; + }; + union + { + __IOM uint32_t REG_1DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DCH_b; + }; + union + { + __IOM uint32_t REG_1E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E0H_b; + }; + union + { + __IOM uint32_t REG_1E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E4H_b; + }; + union + { + __IOM uint32_t REG_1E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E8H_b; + }; + union + { + __IOM uint32_t REG_1ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ECH_b; + }; + union + { + __IOM uint32_t REG_1F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F0H_b; + }; + union + { + __IOM uint32_t REG_1F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F4H_b; + }; + union + { + __IOM uint32_t REG_1F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F8H_b; + }; + union + { + __IOM uint32_t REG_1FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FCH_b; + }; + union + { + __IOM uint32_t REG_200H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_200H_b; + }; + union + { + __IOM uint32_t REG_204H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_204H_b; + }; + union + { + __IOM uint32_t REG_208H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_208H_b; + }; + union + { + __IOM uint32_t REG_20CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20CH_b; + }; + union + { + __IOM uint32_t REG_210H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_210H_b; + }; + union + { + __IOM uint32_t REG_214H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_214H_b; + }; + union + { + __IOM uint32_t REG_218H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_218H_b; + }; + union + { + __IOM uint32_t REG_21CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21CH_b; + }; + union + { + __IOM uint32_t REG_220H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_220H_b; + }; + union + { + __IOM uint32_t REG_224H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_224H_b; + }; + union + { + __IOM uint32_t REG_228H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_228H_b; + }; + union + { + __IOM uint32_t REG_22CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22CH_b; + }; + union + { + __IOM uint32_t REG_230H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_230H_b; + }; + union + { + __IOM uint32_t REG_234H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_234H_b; + }; + union + { + __IOM uint32_t REG_238H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_238H_b; + }; + union + { + __IOM uint32_t REG_23CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23CH_b; + }; + union + { + __IOM uint32_t REG_240H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_240H_b; + }; + union + { + __IOM uint32_t REG_244H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_244H_b; + }; + union + { + __IOM uint32_t REG_248H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_248H_b; + }; + union + { + __IOM uint32_t REG_24CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24CH_b; + }; + union + { + __IOM uint32_t REG_250H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_250H_b; + }; + union + { + __IOM uint32_t REG_254H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_254H_b; + }; + union + { + __IOM uint32_t REG_258H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_258H_b; + }; + union + { + __IOM uint32_t REG_25CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_25CH_b; + }; + union + { + __IOM uint32_t REG_260H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_260H_b; + }; + union + { + __IOM uint32_t REG_264H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_264H_b; + }; + union + { + __IOM uint32_t REG_268H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_268H_b; + }; + union + { + __IOM uint32_t REG_26CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_26CH_b; + }; + union + { + __IOM uint32_t REG_270H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_270H_b; + }; + union + { + __IOM uint32_t REG_274H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_274H_b; + }; + union + { + __IOM uint32_t REG_278H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_278H_b; + }; + union + { + __IOM uint32_t REG_27CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_27CH_b; + }; + union + { + __IOM uint32_t REG_280H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_280H_b; + }; + union + { + __IOM uint32_t REG_284H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_284H_b; + }; + union + { + __IOM uint32_t REG_288H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_288H_b; + }; + union + { + __IOM uint32_t REG_28CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_28CH_b; + }; + union + { + __IOM uint32_t REG_290H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_290H_b; + }; + union + { + __IOM uint32_t REG_294H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_294H_b; + }; + union + { + __IOM uint32_t REG_298H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_298H_b; + }; + union + { + __IOM uint32_t REG_29CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_29CH_b; + }; + union + { + __IOM uint32_t REG_2A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2A0H_b; + }; + union + { + __IOM uint32_t REG_2A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2A4H_b; + }; + union + { + __IOM uint32_t REG_2A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2A8H_b; + }; + union + { + __IOM uint32_t REG_2ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2ACH_b; + }; + union + { + __IOM uint32_t REG_2B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2B0H_b; + }; + union + { + __IOM uint32_t REG_2B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2B4H_b; + }; + union + { + __IOM uint32_t REG_2B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2B8H_b; + }; + union + { + __IOM uint32_t REG_2BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2BCH_b; + }; + union + { + __IOM uint32_t REG_2C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2C0H_b; + }; + union + { + __IOM uint32_t REG_2C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2C4H_b; + }; + union + { + __IOM uint32_t REG_2C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2C8H_b; + }; + union + { + __IOM uint32_t REG_2CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2CCH_b; + }; + union + { + __IOM uint32_t REG_2D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2D0H_b; + }; + union + { + __IOM uint32_t REG_2D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2D4H_b; + }; + union + { + __IOM uint32_t REG_2D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2D8H_b; + }; + union + { + __IOM uint32_t REG_2DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2DCH_b; + }; + union + { + __IOM uint32_t REG_2E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2E0H_b; + }; + union + { + __IOM uint32_t REG_2E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2E4H_b; + }; + union + { + __IOM uint32_t REG_2E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2E8H_b; + }; + union + { + __IOM uint32_t REG_2ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2ECH_b; + }; + union + { + __IOM uint32_t REG_2F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2F0H_b; + }; + union + { + __IOM uint32_t REG_2F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2F4H_b; + }; + union + { + __IOM uint32_t REG_2F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2F8H_b; + }; + union + { + __IOM uint32_t REG_2FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2FCH_b; + }; + union + { + __IOM uint32_t REG_300H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_300H_b; + }; + union + { + __IOM uint32_t REG_304H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_304H_b; + }; + union + { + __IOM uint32_t REG_308H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_308H_b; + }; + union + { + __IOM uint32_t REG_30CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_30CH_b; + }; + union + { + __IOM uint32_t REG_310H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_310H_b; + }; + union + { + __IOM uint32_t REG_314H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_314H_b; + }; + union + { + __IOM uint32_t REG_318H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_318H_b; + }; + union + { + __IOM uint32_t REG_31CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_31CH_b; + }; + union + { + __IOM uint32_t REG_320H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_320H_b; + }; + union + { + __IOM uint32_t REG_324H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_324H_b; + }; + union + { + __IOM uint32_t REG_328H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_328H_b; + }; + union + { + __IOM uint32_t REG_32CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_32CH_b; + }; + union + { + __IOM uint32_t REG_330H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_330H_b; + }; + union + { + __IOM uint32_t REG_334H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_334H_b; + }; + union + { + __IOM uint32_t REG_338H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_338H_b; + }; + union + { + __IOM uint32_t REG_33CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_33CH_b; + }; + union + { + __IOM uint32_t REG_340H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_340H_b; + }; + union + { + __IOM uint32_t REG_344H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_344H_b; + }; + union + { + __IOM uint32_t REG_348H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_348H_b; + }; + union + { + __IOM uint32_t REG_34CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_34CH_b; + }; + union + { + __IOM uint32_t REG_350H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_350H_b; + }; + union + { + __IOM uint32_t REG_354H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_354H_b; + }; + union + { + __IOM uint32_t REG_358H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_358H_b; + }; + union + { + __IOM uint32_t REG_35CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_35CH_b; + }; + union + { + __IOM uint32_t REG_360H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_360H_b; + }; + union + { + __IOM uint32_t REG_364H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_364H_b; + }; + union + { + __IOM uint32_t REG_368H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_368H_b; + }; + union + { + __IOM uint32_t REG_36CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_36CH_b; + }; + union + { + __IOM uint32_t REG_370H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_370H_b; + }; + union + { + __IOM uint32_t REG_374H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_374H_b; + }; + union + { + __IOM uint32_t REG_378H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_378H_b; + }; + union + { + __IOM uint32_t REG_37CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_37CH_b; + }; + union + { + __IOM uint32_t REG_380H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_380H_b; + }; + union + { + __IOM uint32_t REG_384H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_384H_b; + }; + union + { + __IOM uint32_t REG_388H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_388H_b; + }; + union + { + __IOM uint32_t REG_38CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_38CH_b; + }; + union + { + __IOM uint32_t REG_390H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_390H_b; + }; + union + { + __IOM uint32_t REG_394H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_394H_b; + }; + union + { + __IOM uint32_t REG_398H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_398H_b; + }; + union + { + __IOM uint32_t REG_39CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_39CH_b; + }; + union + { + __IOM uint32_t REG_3A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3A0H_b; + }; + union + { + __IOM uint32_t REG_3A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3A4H_b; + }; + union + { + __IOM uint32_t REG_3A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3A8H_b; + }; + union + { + __IOM uint32_t REG_3ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3ACH_b; + }; + union + { + __IOM uint32_t REG_3B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3B0H_b; + }; + union + { + __IOM uint32_t REG_3B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3B4H_b; + }; + union + { + __IOM uint32_t REG_3B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3B8H_b; + }; + union + { + __IOM uint32_t REG_3BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3BCH_b; + }; + union + { + __IOM uint32_t REG_3C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3C0H_b; + }; + union + { + __IOM uint32_t REG_3C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3C4H_b; + }; + union + { + __IOM uint32_t REG_3C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3C8H_b; + }; + union + { + __IOM uint32_t REG_3CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3CCH_b; + }; + union + { + __IOM uint32_t REG_3D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3D0H_b; + }; + union + { + __IOM uint32_t REG_3D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3D4H_b; + }; + union + { + __IOM uint32_t REG_3D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3D8H_b; + }; + union + { + __IOM uint32_t REG_3DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3DCH_b; + }; + union + { + __IOM uint32_t REG_3E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3E0H_b; + }; + union + { + __IOM uint32_t REG_3E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3E4H_b; + }; + union + { + __IOM uint32_t REG_3E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3E8H_b; + }; + union + { + __IOM uint32_t REG_3ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3ECH_b; + }; + union + { + __IOM uint32_t REG_3F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3F0H_b; + }; + union + { + __IOM uint32_t REG_3F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3F4H_b; + }; + union + { + __IOM uint32_t REG_3F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3F8H_b; + }; + union + { + __IOM uint32_t REG_3FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_3FCH_b; + }; + union + { + __IOM uint32_t REG_400H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_400H_b; + }; + union + { + __IOM uint32_t REG_404H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_404H_b; + }; + union + { + __IOM uint32_t REG_408H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_408H_b; + }; + union + { + __IOM uint32_t REG_40CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_40CH_b; + }; + union + { + __IOM uint32_t REG_410H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_410H_b; + }; + union + { + __IOM uint32_t REG_414H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_414H_b; + }; + union + { + __IOM uint32_t REG_418H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_418H_b; + }; + union + { + __IOM uint32_t REG_41CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_41CH_b; + }; + union + { + __IOM uint32_t REG_420H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_420H_b; + }; + union + { + __IOM uint32_t REG_424H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_424H_b; + }; + union + { + __IOM uint32_t REG_428H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_428H_b; + }; + union + { + __IOM uint32_t REG_42CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_42CH_b; + }; + union + { + __IOM uint32_t REG_430H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_430H_b; + }; + union + { + __IOM uint32_t REG_434H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_434H_b; + }; + union + { + __IOM uint32_t REG_438H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_438H_b; + }; + union + { + __IOM uint32_t REG_43CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_43CH_b; + }; + union + { + __IOM uint32_t REG_440H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_440H_b; + }; + union + { + __IOM uint32_t REG_444H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_444H_b; + }; + union + { + __IOM uint32_t REG_448H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_448H_b; + }; + union + { + __IOM uint32_t REG_44CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_44CH_b; + }; + union + { + __IOM uint32_t REG_450H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_450H_b; + }; + union + { + __IOM uint32_t REG_454H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_454H_b; + }; + union + { + __IOM uint32_t REG_458H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_458H_b; + }; + union + { + __IOM uint32_t REG_45CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_45CH_b; + }; + union + { + __IOM uint32_t REG_460H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_460H_b; + }; + union + { + __IOM uint32_t REG_464H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_464H_b; + }; + union + { + __IOM uint32_t REG_468H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_468H_b; + }; + union + { + __IOM uint32_t REG_46CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_46CH_b; + }; + union + { + __IOM uint32_t REG_470H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_470H_b; + }; + union + { + __IOM uint32_t REG_474H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_474H_b; + }; + union + { + __IOM uint32_t REG_478H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_478H_b; + }; + union + { + __IOM uint32_t REG_47CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_47CH_b; + }; + union + { + __IOM uint32_t REG_480H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_480H_b; + }; + union + { + __IOM uint32_t REG_484H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_484H_b; + }; + union + { + __IOM uint32_t REG_488H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_488H_b; + }; + union + { + __IOM uint32_t REG_48CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_48CH_b; + }; + union + { + __IOM uint32_t REG_490H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_490H_b; + }; + union + { + __IOM uint32_t REG_494H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_494H_b; + }; + union + { + __IOM uint32_t REG_498H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_498H_b; + }; + union + { + __IOM uint32_t REG_49CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_49CH_b; + }; + union + { + __IOM uint32_t REG_4A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4A0H_b; + }; + union + { + __IOM uint32_t REG_4A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4A4H_b; + }; + union + { + __IOM uint32_t REG_4A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4A8H_b; + }; + union + { + __IOM uint32_t REG_4ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4ACH_b; + }; + union + { + __IOM uint32_t REG_4B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4B0H_b; + }; + union + { + __IOM uint32_t REG_4B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4B4H_b; + }; + union + { + __IOM uint32_t REG_4B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4B8H_b; + }; + union + { + __IOM uint32_t REG_4BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4BCH_b; + }; + union + { + __IOM uint32_t REG_4C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4C0H_b; + }; + union + { + __IOM uint32_t REG_4C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4C4H_b; + }; + union + { + __IOM uint32_t REG_4C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4C8H_b; + }; + union + { + __IOM uint32_t REG_4CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4CCH_b; + }; + union + { + __IOM uint32_t REG_4D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4D0H_b; + }; + union + { + __IOM uint32_t REG_4D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4D4H_b; + }; + union + { + __IOM uint32_t REG_4D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4D8H_b; + }; + union + { + __IOM uint32_t REG_4DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4DCH_b; + }; + union + { + __IOM uint32_t REG_4E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4E0H_b; + }; + union + { + __IOM uint32_t REG_4E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4E4H_b; + }; + union + { + __IOM uint32_t REG_4E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4E8H_b; + }; + union + { + __IOM uint32_t REG_4ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4ECH_b; + }; + union + { + __IOM uint32_t REG_4F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4F0H_b; + }; + union + { + __IOM uint32_t REG_4F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4F4H_b; + }; + union + { + __IOM uint32_t REG_4F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4F8H_b; + }; + union + { + __IOM uint32_t REG_4FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_4FCH_b; + }; + union + { + __IOM uint32_t REG_500H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_500H_b; + }; + union + { + __IOM uint32_t REG_504H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_504H_b; + }; + union + { + __IOM uint32_t REG_508H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_508H_b; + }; + union + { + __IOM uint32_t REG_50CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_50CH_b; + }; + union + { + __IOM uint32_t REG_510H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_510H_b; + }; + union + { + __IOM uint32_t REG_514H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_514H_b; + }; + union + { + __IOM uint32_t REG_518H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_518H_b; + }; + union + { + __IOM uint32_t REG_51CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_51CH_b; + }; + union + { + __IOM uint32_t REG_520H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_520H_b; + }; + union + { + __IOM uint32_t REG_524H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_524H_b; + }; + union + { + __IOM uint32_t REG_528H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_528H_b; + }; + union + { + __IOM uint32_t REG_52CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_52CH_b; + }; + union + { + __IOM uint32_t REG_530H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_530H_b; + }; + union + { + __IOM uint32_t REG_534H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_534H_b; + }; + union + { + __IOM uint32_t REG_538H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_538H_b; + }; + union + { + __IOM uint32_t REG_53CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_53CH_b; + }; + union + { + __IOM uint32_t REG_540H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_540H_b; + }; + union + { + __IOM uint32_t REG_544H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_544H_b; + }; + union + { + __IOM uint32_t REG_548H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_548H_b; + }; + union + { + __IOM uint32_t REG_54CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_54CH_b; + }; + union + { + __IOM uint32_t REG_550H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_550H_b; + }; + union + { + __IOM uint32_t REG_554H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_554H_b; + }; + union + { + __IOM uint32_t REG_558H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_558H_b; + }; + union + { + __IOM uint32_t REG_55CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_55CH_b; + }; + union + { + __IOM uint32_t REG_560H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_560H_b; + }; + union + { + __IOM uint32_t REG_564H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_564H_b; + }; + union + { + __IOM uint32_t REG_568H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_568H_b; + }; + union + { + __IOM uint32_t REG_56CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_56CH_b; + }; + union + { + __IOM uint32_t REG_570H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_570H_b; + }; + union + { + __IOM uint32_t REG_574H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_574H_b; + }; + union + { + __IOM uint32_t REG_578H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_578H_b; + }; + union + { + __IOM uint32_t REG_57CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_57CH_b; + }; + union + { + __IOM uint32_t REG_580H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_580H_b; + }; + union + { + __IOM uint32_t REG_584H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_584H_b; + }; + union + { + __IOM uint32_t REG_588H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_588H_b; + }; + union + { + __IOM uint32_t REG_58CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_58CH_b; + }; + union + { + __IOM uint32_t REG_590H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_590H_b; + }; + union + { + __IOM uint32_t REG_594H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_594H_b; + }; + union + { + __IOM uint32_t REG_598H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_598H_b; + }; + union + { + __IOM uint32_t REG_59CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_59CH_b; + }; + union + { + __IOM uint32_t REG_5A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5A0H_b; + }; + union + { + __IOM uint32_t REG_5A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5A4H_b; + }; + union + { + __IOM uint32_t REG_5A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5A8H_b; + }; + union + { + __IOM uint32_t REG_5ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5ACH_b; + }; + union + { + __IOM uint32_t REG_5B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5B0H_b; + }; + union + { + __IOM uint32_t REG_5B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5B4H_b; + }; + union + { + __IOM uint32_t REG_5B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5B8H_b; + }; + union + { + __IOM uint32_t REG_5BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5BCH_b; + }; + union + { + __IOM uint32_t REG_5C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5C0H_b; + }; + union + { + __IOM uint32_t REG_5C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5C4H_b; + }; + union + { + __IOM uint32_t REG_5C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5C8H_b; + }; + union + { + __IOM uint32_t REG_5CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5CCH_b; + }; + union + { + __IOM uint32_t REG_5D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5D0H_b; + }; + union + { + __IOM uint32_t REG_5D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5D4H_b; + }; + union + { + __IOM uint32_t REG_5D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5D8H_b; + }; + union + { + __IOM uint32_t REG_5DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5DCH_b; + }; + union + { + __IOM uint32_t REG_5E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5E0H_b; + }; + union + { + __IOM uint32_t REG_5E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5E4H_b; + }; + union + { + __IOM uint32_t REG_5E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5E8H_b; + }; + union + { + __IOM uint32_t REG_5ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5ECH_b; + }; + union + { + __IOM uint32_t REG_5F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5F0H_b; + }; + union + { + __IOM uint32_t REG_5F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5F4H_b; + }; + union + { + __IOM uint32_t REG_5F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5F8H_b; + }; + union + { + __IOM uint32_t REG_5FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_5FCH_b; + }; + union + { + __IOM uint32_t REG_600H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_600H_b; + }; + union + { + __IOM uint32_t REG_604H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_604H_b; + }; + union + { + __IOM uint32_t REG_608H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_608H_b; + }; + union + { + __IOM uint32_t REG_60CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_60CH_b; + }; + union + { + __IOM uint32_t REG_610H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_610H_b; + }; + union + { + __IOM uint32_t REG_614H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_614H_b; + }; + union + { + __IOM uint32_t REG_618H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_618H_b; + }; + union + { + __IOM uint32_t REG_61CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_61CH_b; + }; + union + { + __IOM uint32_t REG_620H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_620H_b; + }; + union + { + __IOM uint32_t REG_624H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_624H_b; + }; + union + { + __IOM uint32_t REG_628H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_628H_b; + }; + union + { + __IOM uint32_t REG_62CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_62CH_b; + }; + union + { + __IOM uint32_t REG_630H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_630H_b; + }; + union + { + __IOM uint32_t REG_634H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_634H_b; + }; + union + { + __IOM uint32_t REG_638H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_638H_b; + }; + union + { + __IOM uint32_t REG_63CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_63CH_b; + }; + union + { + __IOM uint32_t REG_640H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_640H_b; + }; + union + { + __IOM uint32_t REG_644H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_644H_b; + }; + union + { + __IOM uint32_t REG_648H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_648H_b; + }; + union + { + __IOM uint32_t REG_64CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_64CH_b; + }; + union + { + __IOM uint32_t REG_650H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_650H_b; + }; + union + { + __IOM uint32_t REG_654H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_654H_b; + }; + union + { + __IOM uint32_t REG_658H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_658H_b; + }; + union + { + __IOM uint32_t REG_65CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_65CH_b; + }; + union + { + __IOM uint32_t REG_660H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_660H_b; + }; + union + { + __IOM uint32_t REG_664H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_664H_b; + }; + union + { + __IOM uint32_t REG_668H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_668H_b; + }; + union + { + __IOM uint32_t REG_66CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_66CH_b; + }; + union + { + __IOM uint32_t REG_670H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_670H_b; + }; + union + { + __IOM uint32_t REG_674H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_674H_b; + }; + union + { + __IOM uint32_t REG_678H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_678H_b; + }; + union + { + __IOM uint32_t REG_67CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_67CH_b; + }; + union + { + __IOM uint32_t REG_680H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_680H_b; + }; + union + { + __IOM uint32_t REG_684H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_684H_b; + }; + union + { + __IOM uint32_t REG_688H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_688H_b; + }; + union + { + __IOM uint32_t REG_68CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_68CH_b; + }; + union + { + __IOM uint32_t REG_690H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_690H_b; + }; + union + { + __IOM uint32_t REG_694H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_694H_b; + }; + union + { + __IOM uint32_t REG_698H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_698H_b; + }; + union + { + __IOM uint32_t REG_69CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_69CH_b; + }; + union + { + __IOM uint32_t REG_6A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6A0H_b; + }; + union + { + __IOM uint32_t REG_6A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6A4H_b; + }; + union + { + __IOM uint32_t REG_6A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6A8H_b; + }; + union + { + __IOM uint32_t REG_6ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6ACH_b; + }; + union + { + __IOM uint32_t REG_6B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6B0H_b; + }; + union + { + __IOM uint32_t REG_6B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6B4H_b; + }; + union + { + __IOM uint32_t REG_6B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6B8H_b; + }; + union + { + __IOM uint32_t REG_6BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6BCH_b; + }; + union + { + __IOM uint32_t REG_6C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6C0H_b; + }; + union + { + __IOM uint32_t REG_6C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6C4H_b; + }; + union + { + __IOM uint32_t REG_6C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6C8H_b; + }; + union + { + __IOM uint32_t REG_6CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6CCH_b; + }; + union + { + __IOM uint32_t REG_6D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6D0H_b; + }; + union + { + __IOM uint32_t REG_6D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6D4H_b; + }; + union + { + __IOM uint32_t REG_6D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6D8H_b; + }; + union + { + __IOM uint32_t REG_6DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6DCH_b; + }; + union + { + __IOM uint32_t REG_6E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6E0H_b; + }; + union + { + __IOM uint32_t REG_6E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6E4H_b; + }; + union + { + __IOM uint32_t REG_6E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6E8H_b; + }; + union + { + __IOM uint32_t REG_6ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6ECH_b; + }; + union + { + __IOM uint32_t REG_6F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6F0H_b; + }; + union + { + __IOM uint32_t REG_6F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6F4H_b; + }; + union + { + __IOM uint32_t REG_6F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6F8H_b; + }; + union + { + __IOM uint32_t REG_6FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_6FCH_b; + }; + union + { + __IOM uint32_t REG_700H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_700H_b; + }; + union + { + __IOM uint32_t REG_704H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_704H_b; + }; + union + { + __IOM uint32_t REG_708H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_708H_b; + }; + union + { + __IOM uint32_t REG_70CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_70CH_b; + }; + union + { + __IOM uint32_t REG_710H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_710H_b; + }; + union + { + __IOM uint32_t REG_714H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_714H_b; + }; + union + { + __IOM uint32_t REG_718H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_718H_b; + }; + union + { + __IOM uint32_t REG_71CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_71CH_b; + }; + union + { + __IOM uint32_t REG_720H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_720H_b; + }; + union + { + __IOM uint32_t REG_724H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_724H_b; + }; + union + { + __IOM uint32_t REG_728H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_728H_b; + }; + union + { + __IOM uint32_t REG_72CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_72CH_b; + }; + union + { + __IOM uint32_t REG_730H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_730H_b; + }; + union + { + __IOM uint32_t REG_734H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_734H_b; + }; + union + { + __IOM uint32_t REG_738H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_738H_b; + }; + union + { + __IOM uint32_t REG_73CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_73CH_b; + }; + union + { + __IOM uint32_t REG_740H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_740H_b; + }; + union + { + __IOM uint32_t REG_744H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_744H_b; + }; + union + { + __IOM uint32_t REG_748H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_748H_b; + }; + union + { + __IOM uint32_t REG_74CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_74CH_b; + }; + union + { + __IOM uint32_t REG_750H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_750H_b; + }; + union + { + __IOM uint32_t REG_754H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_754H_b; + }; + union + { + __IOM uint32_t REG_758H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_758H_b; + }; + union + { + __IOM uint32_t REG_75CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_75CH_b; + }; + union + { + __IOM uint32_t REG_760H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_760H_b; + }; + union + { + __IOM uint32_t REG_764H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_764H_b; + }; + union + { + __IOM uint32_t REG_768H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_768H_b; + }; + union + { + __IOM uint32_t REG_76CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_76CH_b; + }; + union + { + __IOM uint32_t REG_770H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_770H_b; + }; + union + { + __IOM uint32_t REG_774H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_774H_b; + }; + union + { + __IOM uint32_t REG_778H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_778H_b; + }; + union + { + __IOM uint32_t REG_77CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_77CH_b; + }; + union + { + __IOM uint32_t REG_780H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_780H_b; + }; + union + { + __IOM uint32_t REG_784H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_784H_b; + }; + union + { + __IOM uint32_t REG_788H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_788H_b; + }; + union + { + __IOM uint32_t REG_78CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_78CH_b; + }; + union + { + __IOM uint32_t REG_790H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_790H_b; + }; + union + { + __IOM uint32_t REG_794H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_794H_b; + }; + union + { + __IOM uint32_t REG_798H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_798H_b; + }; + union + { + __IOM uint32_t REG_79CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_79CH_b; + }; + union + { + __IOM uint32_t REG_7A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7A0H_b; + }; + union + { + __IOM uint32_t REG_7A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7A4H_b; + }; + union + { + __IOM uint32_t REG_7A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7A8H_b; + }; + union + { + __IOM uint32_t REG_7ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7ACH_b; + }; + union + { + __IOM uint32_t REG_7B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7B0H_b; + }; + union + { + __IOM uint32_t REG_7B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7B4H_b; + }; + union + { + __IOM uint32_t REG_7B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7B8H_b; + }; + union + { + __IOM uint32_t REG_7BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7BCH_b; + }; + union + { + __IOM uint32_t REG_7C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7C0H_b; + }; + union + { + __IOM uint32_t REG_7C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7C4H_b; + }; + union + { + __IOM uint32_t REG_7C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7C8H_b; + }; + union + { + __IOM uint32_t REG_7CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7CCH_b; + }; + union + { + __IOM uint32_t REG_7D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7D0H_b; + }; + union + { + __IOM uint32_t REG_7D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7D4H_b; + }; + union + { + __IOM uint32_t REG_7D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7D8H_b; + }; + union + { + __IOM uint32_t REG_7DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7DCH_b; + }; + union + { + __IOM uint32_t REG_7E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7E0H_b; + }; + union + { + __IOM uint32_t REG_7E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7E4H_b; + }; + union + { + __IOM uint32_t REG_7E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7E8H_b; + }; + union + { + __IOM uint32_t REG_7ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7ECH_b; + }; + union + { + __IOM uint32_t REG_7F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7F0H_b; + }; + union + { + __IOM uint32_t REG_7F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7F4H_b; + }; + union + { + __IOM uint32_t REG_7F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7F8H_b; + }; + union + { + __IOM uint32_t REG_7FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_7FCH_b; + }; + union + { + __IOM uint32_t REG_800H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_800H_b; + }; + union + { + __IOM uint32_t REG_804H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_804H_b; + }; + union + { + __IOM uint32_t REG_808H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_808H_b; + }; + union + { + __IOM uint32_t REG_80CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_80CH_b; + }; + union + { + __IOM uint32_t REG_810H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_810H_b; + }; + union + { + __IOM uint32_t REG_814H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_814H_b; + }; + union + { + __IOM uint32_t REG_818H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_818H_b; + }; + union + { + __IOM uint32_t REG_81CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_81CH_b; + }; + union + { + __IOM uint32_t REG_820H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_820H_b; + }; + union + { + __IOM uint32_t REG_824H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_824H_b; + }; + union + { + __IOM uint32_t REG_828H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_828H_b; + }; + union + { + __IOM uint32_t REG_82CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_82CH_b; + }; + union + { + __IOM uint32_t REG_830H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_830H_b; + }; + union + { + __IOM uint32_t REG_834H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_834H_b; + }; + union + { + __IOM uint32_t REG_838H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_838H_b; + }; + union + { + __IOM uint32_t REG_83CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_83CH_b; + }; + union + { + __IOM uint32_t REG_840H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_840H_b; + }; + union + { + __IOM uint32_t REG_844H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_844H_b; + }; + union + { + __IOM uint32_t REG_848H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_848H_b; + }; + union + { + __IOM uint32_t REG_84CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_84CH_b; + }; + union + { + __IOM uint32_t REG_850H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_850H_b; + }; + union + { + __IOM uint32_t REG_854H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_854H_b; + }; + union + { + __IOM uint32_t REG_858H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_858H_b; + }; + union + { + __IOM uint32_t REG_85CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_85CH_b; + }; + union + { + __IOM uint32_t REG_860H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_860H_b; + }; + union + { + __IOM uint32_t REG_864H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_864H_b; + }; + union + { + __IOM uint32_t REG_868H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_868H_b; + }; + union + { + __IOM uint32_t REG_86CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_86CH_b; + }; + union + { + __IOM uint32_t REG_870H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_870H_b; + }; + union + { + __IOM uint32_t REG_874H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_874H_b; + }; + union + { + __IOM uint32_t REG_878H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_878H_b; + }; + union + { + __IOM uint32_t REG_87CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_87CH_b; + }; + union + { + __IOM uint32_t REG_880H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_880H_b; + }; + union + { + __IOM uint32_t REG_884H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_884H_b; + }; + union + { + __IOM uint32_t REG_888H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_888H_b; + }; + union + { + __IOM uint32_t REG_88CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_88CH_b; + }; + union + { + __IOM uint32_t REG_890H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_890H_b; + }; + union + { + __IOM uint32_t REG_894H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_894H_b; + }; + union + { + __IOM uint32_t REG_898H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_898H_b; + }; + union + { + __IOM uint32_t REG_89CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_89CH_b; + }; + union + { + __IOM uint32_t REG_8A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8A0H_b; + }; + union + { + __IOM uint32_t REG_8A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8A4H_b; + }; + union + { + __IOM uint32_t REG_8A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8A8H_b; + }; + union + { + __IOM uint32_t REG_8ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8ACH_b; + }; + union + { + __IOM uint32_t REG_8B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8B0H_b; + }; + union + { + __IOM uint32_t REG_8B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8B4H_b; + }; + union + { + __IOM uint32_t REG_8B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8B8H_b; + }; + union + { + __IOM uint32_t REG_8BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8BCH_b; + }; + union + { + __IOM uint32_t REG_8C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8C0H_b; + }; + union + { + __IOM uint32_t REG_8C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8C4H_b; + }; + union + { + __IOM uint32_t REG_8C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8C8H_b; + }; + union + { + __IOM uint32_t REG_8CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8CCH_b; + }; + union + { + __IOM uint32_t REG_8D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8D0H_b; + }; + union + { + __IOM uint32_t REG_8D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8D4H_b; + }; + union + { + __IOM uint32_t REG_8D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8D8H_b; + }; + union + { + __IOM uint32_t REG_8DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8DCH_b; + }; + union + { + __IOM uint32_t REG_8E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8E0H_b; + }; + union + { + __IOM uint32_t REG_8E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8E4H_b; + }; + union + { + __IOM uint32_t REG_8E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8E8H_b; + }; + union + { + __IOM uint32_t REG_8ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8ECH_b; + }; + union + { + __IOM uint32_t REG_8F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8F0H_b; + }; + union + { + __IOM uint32_t REG_8F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8F4H_b; + }; + union + { + __IOM uint32_t REG_8F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8F8H_b; + }; + union + { + __IOM uint32_t REG_8FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_8FCH_b; + }; + union + { + __IOM uint32_t REG_900H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_900H_b; + }; + union + { + __IOM uint32_t REG_904H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_904H_b; + }; + union + { + __IOM uint32_t REG_908H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_908H_b; + }; + union + { + __IOM uint32_t REG_90CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_90CH_b; + }; + union + { + __IOM uint32_t REG_910H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_910H_b; + }; + union + { + __IOM uint32_t REG_914H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_914H_b; + }; + union + { + __IOM uint32_t REG_918H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_918H_b; + }; + union + { + __IOM uint32_t REG_91CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_91CH_b; + }; + union + { + __IOM uint32_t REG_920H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_920H_b; + }; + union + { + __IOM uint32_t REG_924H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_924H_b; + }; + union + { + __IOM uint32_t REG_928H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_928H_b; + }; + union + { + __IOM uint32_t REG_92CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_92CH_b; + }; + union + { + __IOM uint32_t REG_930H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_930H_b; + }; + union + { + __IOM uint32_t REG_934H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_934H_b; + }; + union + { + __IOM uint32_t REG_938H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_938H_b; + }; + union + { + __IOM uint32_t REG_93CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_93CH_b; + }; + union + { + __IOM uint32_t REG_940H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_940H_b; + }; + union + { + __IOM uint32_t REG_944H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_944H_b; + }; + union + { + __IOM uint32_t REG_948H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_948H_b; + }; + union + { + __IOM uint32_t REG_94CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_94CH_b; + }; + union + { + __IOM uint32_t REG_950H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_950H_b; + }; + union + { + __IOM uint32_t REG_954H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_954H_b; + }; + union + { + __IOM uint32_t REG_958H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_958H_b; + }; + union + { + __IOM uint32_t REG_95CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_95CH_b; + }; + union + { + __IOM uint32_t REG_960H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_960H_b; + }; + union + { + __IOM uint32_t REG_964H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_964H_b; + }; + union + { + __IOM uint32_t REG_968H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_968H_b; + }; + union + { + __IOM uint32_t REG_96CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_96CH_b; + }; + union + { + __IOM uint32_t REG_970H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_970H_b; + }; + union + { + __IOM uint32_t REG_974H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_974H_b; + }; + union + { + __IOM uint32_t REG_978H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_978H_b; + }; + union + { + __IOM uint32_t REG_97CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_97CH_b; + }; + union + { + __IOM uint32_t REG_980H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_980H_b; + }; + union + { + __IOM uint32_t REG_984H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_984H_b; + }; + union + { + __IOM uint32_t REG_988H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_988H_b; + }; + union + { + __IOM uint32_t REG_98CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_98CH_b; + }; + union + { + __IOM uint32_t REG_990H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_990H_b; + }; + union + { + __IOM uint32_t REG_994H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_994H_b; + }; + union + { + __IOM uint32_t REG_998H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_998H_b; + }; + union + { + __IOM uint32_t REG_99CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_99CH_b; + }; + union + { + __IOM uint32_t REG_9A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9A0H_b; + }; + union + { + __IOM uint32_t REG_9A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9A4H_b; + }; + union + { + __IOM uint32_t REG_9A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9A8H_b; + }; + union + { + __IOM uint32_t REG_9ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9ACH_b; + }; + union + { + __IOM uint32_t REG_9B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9B0H_b; + }; + union + { + __IOM uint32_t REG_9B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9B4H_b; + }; + union + { + __IOM uint32_t REG_9B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9B8H_b; + }; + union + { + __IOM uint32_t REG_9BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9BCH_b; + }; + union + { + __IOM uint32_t REG_9C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9C0H_b; + }; + union + { + __IOM uint32_t REG_9C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9C4H_b; + }; + union + { + __IOM uint32_t REG_9C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9C8H_b; + }; + union + { + __IOM uint32_t REG_9CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9CCH_b; + }; + union + { + __IOM uint32_t REG_9D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9D0H_b; + }; + union + { + __IOM uint32_t REG_9D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9D4H_b; + }; + union + { + __IOM uint32_t REG_9D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9D8H_b; + }; + union + { + __IOM uint32_t REG_9DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9DCH_b; + }; + union + { + __IOM uint32_t REG_9E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9E0H_b; + }; + union + { + __IOM uint32_t REG_9E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9E4H_b; + }; + union + { + __IOM uint32_t REG_9E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9E8H_b; + }; + union + { + __IOM uint32_t REG_9ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9ECH_b; + }; + union + { + __IOM uint32_t REG_9F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9F0H_b; + }; + union + { + __IOM uint32_t REG_9F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9F4H_b; + }; + union + { + __IOM uint32_t REG_9F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9F8H_b; + }; + union + { + __IOM uint32_t REG_9FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_9FCH_b; + }; + union + { + __IOM uint32_t REG_A00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A00H_b; + }; + union + { + __IOM uint32_t REG_A04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A04H_b; + }; + union + { + __IOM uint32_t REG_A08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A08H_b; + }; + union + { + __IOM uint32_t REG_A0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A0CH_b; + }; + union + { + __IOM uint32_t REG_A10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A10H_b; + }; + union + { + __IOM uint32_t REG_A14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A14H_b; + }; + union + { + __IOM uint32_t REG_A18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A18H_b; + }; + union + { + __IOM uint32_t REG_A1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A1CH_b; + }; + union + { + __IOM uint32_t REG_A20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A20H_b; + }; + union + { + __IOM uint32_t REG_A24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A24H_b; + }; + union + { + __IOM uint32_t REG_A28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A28H_b; + }; + union + { + __IOM uint32_t REG_A2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A2CH_b; + }; + union + { + __IOM uint32_t REG_A30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A30H_b; + }; + union + { + __IOM uint32_t REG_A34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A34H_b; + }; + union + { + __IOM uint32_t REG_A38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A38H_b; + }; + union + { + __IOM uint32_t REG_A3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A3CH_b; + }; + union + { + __IOM uint32_t REG_A40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A40H_b; + }; + union + { + __IOM uint32_t REG_A44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A44H_b; + }; + union + { + __IOM uint32_t REG_A48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A48H_b; + }; + union + { + __IOM uint32_t REG_A4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A4CH_b; + }; + union + { + __IOM uint32_t REG_A50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A50H_b; + }; + union + { + __IOM uint32_t REG_A54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A54H_b; + }; + union + { + __IOM uint32_t REG_A58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A58H_b; + }; + union + { + __IOM uint32_t REG_A5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A5CH_b; + }; + union + { + __IOM uint32_t REG_A60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A60H_b; + }; + union + { + __IOM uint32_t REG_A64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A64H_b; + }; + union + { + __IOM uint32_t REG_A68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A68H_b; + }; + union + { + __IOM uint32_t REG_A6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A6CH_b; + }; + union + { + __IOM uint32_t REG_A70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A70H_b; + }; + union + { + __IOM uint32_t REG_A74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A74H_b; + }; + union + { + __IOM uint32_t REG_A78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A78H_b; + }; + union + { + __IOM uint32_t REG_A7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A7CH_b; + }; + union + { + __IOM uint32_t REG_A80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A80H_b; + }; + union + { + __IOM uint32_t REG_A84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A84H_b; + }; + union + { + __IOM uint32_t REG_A88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A88H_b; + }; + union + { + __IOM uint32_t REG_A8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A8CH_b; + }; + union + { + __IOM uint32_t REG_A90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A90H_b; + }; + union + { + __IOM uint32_t REG_A94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A94H_b; + }; + union + { + __IOM uint32_t REG_A98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A98H_b; + }; + union + { + __IOM uint32_t REG_A9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_A9CH_b; + }; + union + { + __IOM uint32_t REG_AA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AA0H_b; + }; + union + { + __IOM uint32_t REG_AA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AA4H_b; + }; + union + { + __IOM uint32_t REG_AA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AA8H_b; + }; + union + { + __IOM uint32_t REG_AACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AACH_b; + }; + union + { + __IOM uint32_t REG_AB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AB0H_b; + }; + union + { + __IOM uint32_t REG_AB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AB4H_b; + }; + union + { + __IOM uint32_t REG_AB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AB8H_b; + }; + union + { + __IOM uint32_t REG_ABCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ABCH_b; + }; + union + { + __IOM uint32_t REG_AC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AC0H_b; + }; + union + { + __IOM uint32_t REG_AC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AC4H_b; + }; + union + { + __IOM uint32_t REG_AC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AC8H_b; + }; + union + { + __IOM uint32_t REG_ACCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ACCH_b; + }; + union + { + __IOM uint32_t REG_AD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AD0H_b; + }; + union + { + __IOM uint32_t REG_AD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AD4H_b; + }; + union + { + __IOM uint32_t REG_AD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AD8H_b; + }; + union + { + __IOM uint32_t REG_ADCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ADCH_b; + }; + union + { + __IOM uint32_t REG_AE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AE0H_b; + }; + union + { + __IOM uint32_t REG_AE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AE4H_b; + }; + union + { + __IOM uint32_t REG_AE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AE8H_b; + }; + union + { + __IOM uint32_t REG_AECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AECH_b; + }; + union + { + __IOM uint32_t REG_AF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AF0H_b; + }; + union + { + __IOM uint32_t REG_AF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AF4H_b; + }; + union + { + __IOM uint32_t REG_AF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AF8H_b; + }; + union + { + __IOM uint32_t REG_AFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_AFCH_b; + }; + union + { + __IOM uint32_t REG_B00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B00H_b; + }; + union + { + __IOM uint32_t REG_B04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B04H_b; + }; + union + { + __IOM uint32_t REG_B08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B08H_b; + }; + union + { + __IOM uint32_t REG_B0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B0CH_b; + }; + union + { + __IOM uint32_t REG_B10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B10H_b; + }; + union + { + __IOM uint32_t REG_B14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B14H_b; + }; + union + { + __IOM uint32_t REG_B18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B18H_b; + }; + union + { + __IOM uint32_t REG_B1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B1CH_b; + }; + union + { + __IOM uint32_t REG_B20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B20H_b; + }; + union + { + __IOM uint32_t REG_B24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B24H_b; + }; + union + { + __IOM uint32_t REG_B28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B28H_b; + }; + union + { + __IOM uint32_t REG_B2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B2CH_b; + }; + union + { + __IOM uint32_t REG_B30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B30H_b; + }; + union + { + __IOM uint32_t REG_B34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B34H_b; + }; + union + { + __IOM uint32_t REG_B38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B38H_b; + }; + union + { + __IOM uint32_t REG_B3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B3CH_b; + }; + union + { + __IOM uint32_t REG_B40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B40H_b; + }; + union + { + __IOM uint32_t REG_B44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B44H_b; + }; + union + { + __IOM uint32_t REG_B48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B48H_b; + }; + union + { + __IOM uint32_t REG_B4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B4CH_b; + }; + union + { + __IOM uint32_t REG_B50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B50H_b; + }; + union + { + __IOM uint32_t REG_B54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B54H_b; + }; + union + { + __IOM uint32_t REG_B58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B58H_b; + }; + union + { + __IOM uint32_t REG_B5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B5CH_b; + }; + union + { + __IOM uint32_t REG_B60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B60H_b; + }; + union + { + __IOM uint32_t REG_B64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B64H_b; + }; + union + { + __IOM uint32_t REG_B68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B68H_b; + }; + union + { + __IOM uint32_t REG_B6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B6CH_b; + }; + union + { + __IOM uint32_t REG_B70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B70H_b; + }; + union + { + __IOM uint32_t REG_B74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B74H_b; + }; + union + { + __IOM uint32_t REG_B78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B78H_b; + }; + union + { + __IOM uint32_t REG_B7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B7CH_b; + }; + union + { + __IOM uint32_t REG_B80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B80H_b; + }; + union + { + __IOM uint32_t REG_B84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B84H_b; + }; + union + { + __IOM uint32_t REG_B88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B88H_b; + }; + union + { + __IOM uint32_t REG_B8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B8CH_b; + }; + union + { + __IOM uint32_t REG_B90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B90H_b; + }; + union + { + __IOM uint32_t REG_B94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B94H_b; + }; + union + { + __IOM uint32_t REG_B98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B98H_b; + }; + union + { + __IOM uint32_t REG_B9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_B9CH_b; + }; + union + { + __IOM uint32_t REG_BA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BA0H_b; + }; + union + { + __IOM uint32_t REG_BA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BA4H_b; + }; + union + { + __IOM uint32_t REG_BA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BA8H_b; + }; + union + { + __IOM uint32_t REG_BACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BACH_b; + }; + union + { + __IOM uint32_t REG_BB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BB0H_b; + }; + union + { + __IOM uint32_t REG_BB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BB4H_b; + }; + union + { + __IOM uint32_t REG_BB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BB8H_b; + }; + union + { + __IOM uint32_t REG_BBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BBCH_b; + }; + union + { + __IOM uint32_t REG_BC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BC0H_b; + }; + union + { + __IOM uint32_t REG_BC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BC4H_b; + }; + union + { + __IOM uint32_t REG_BC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BC8H_b; + }; + union + { + __IOM uint32_t REG_BCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BCCH_b; + }; + union + { + __IOM uint32_t REG_BD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BD0H_b; + }; + union + { + __IOM uint32_t REG_BD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BD4H_b; + }; + union + { + __IOM uint32_t REG_BD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BD8H_b; + }; + union + { + __IOM uint32_t REG_BDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BDCH_b; + }; + union + { + __IOM uint32_t REG_BE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BE0H_b; + }; + union + { + __IOM uint32_t REG_BE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BE4H_b; + }; + union + { + __IOM uint32_t REG_BE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BE8H_b; + }; + union + { + __IOM uint32_t REG_BECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BECH_b; + }; + union + { + __IOM uint32_t REG_BF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BF0H_b; + }; + union + { + __IOM uint32_t REG_BF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BF4H_b; + }; + union + { + __IOM uint32_t REG_BF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BF8H_b; + }; + union + { + __IOM uint32_t REG_BFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_BFCH_b; + }; + union + { + __IOM uint32_t REG_C00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C00H_b; + }; + union + { + __IOM uint32_t REG_C04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C04H_b; + }; + union + { + __IOM uint32_t REG_C08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C08H_b; + }; + union + { + __IOM uint32_t REG_C0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C0CH_b; + }; + union + { + __IOM uint32_t REG_C10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C10H_b; + }; + union + { + __IOM uint32_t REG_C14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C14H_b; + }; + union + { + __IOM uint32_t REG_C18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C18H_b; + }; + union + { + __IOM uint32_t REG_C1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C1CH_b; + }; + union + { + __IOM uint32_t REG_C20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C20H_b; + }; + union + { + __IOM uint32_t REG_C24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C24H_b; + }; + union + { + __IOM uint32_t REG_C28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C28H_b; + }; + union + { + __IOM uint32_t REG_C2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C2CH_b; + }; + union + { + __IOM uint32_t REG_C30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C30H_b; + }; + union + { + __IOM uint32_t REG_C34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C34H_b; + }; + union + { + __IOM uint32_t REG_C38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C38H_b; + }; + union + { + __IOM uint32_t REG_C3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C3CH_b; + }; + union + { + __IOM uint32_t REG_C40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C40H_b; + }; + union + { + __IOM uint32_t REG_C44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C44H_b; + }; + union + { + __IOM uint32_t REG_C48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C48H_b; + }; + union + { + __IOM uint32_t REG_C4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C4CH_b; + }; + union + { + __IOM uint32_t REG_C50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C50H_b; + }; + union + { + __IOM uint32_t REG_C54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C54H_b; + }; + union + { + __IOM uint32_t REG_C58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C58H_b; + }; + union + { + __IOM uint32_t REG_C5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C5CH_b; + }; + union + { + __IOM uint32_t REG_C60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C60H_b; + }; + union + { + __IOM uint32_t REG_C64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C64H_b; + }; + union + { + __IOM uint32_t REG_C68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C68H_b; + }; + union + { + __IOM uint32_t REG_C6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C6CH_b; + }; + union + { + __IOM uint32_t REG_C70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C70H_b; + }; + union + { + __IOM uint32_t REG_C74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C74H_b; + }; + union + { + __IOM uint32_t REG_C78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C78H_b; + }; + union + { + __IOM uint32_t REG_C7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C7CH_b; + }; + union + { + __IOM uint32_t REG_C80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C80H_b; + }; + union + { + __IOM uint32_t REG_C84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C84H_b; + }; + union + { + __IOM uint32_t REG_C88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C88H_b; + }; + union + { + __IOM uint32_t REG_C8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C8CH_b; + }; + union + { + __IOM uint32_t REG_C90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C90H_b; + }; + union + { + __IOM uint32_t REG_C94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C94H_b; + }; + union + { + __IOM uint32_t REG_C98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C98H_b; + }; + union + { + __IOM uint32_t REG_C9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_C9CH_b; + }; + union + { + __IOM uint32_t REG_CA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CA0H_b; + }; + union + { + __IOM uint32_t REG_CA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CA4H_b; + }; + union + { + __IOM uint32_t REG_CA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CA8H_b; + }; + union + { + __IOM uint32_t REG_CACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CACH_b; + }; + union + { + __IOM uint32_t REG_CB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CB0H_b; + }; + union + { + __IOM uint32_t REG_CB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CB4H_b; + }; + union + { + __IOM uint32_t REG_CB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CB8H_b; + }; + union + { + __IOM uint32_t REG_CBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CBCH_b; + }; + union + { + __IOM uint32_t REG_CC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CC0H_b; + }; + union + { + __IOM uint32_t REG_CC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CC4H_b; + }; + union + { + __IOM uint32_t REG_CC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CC8H_b; + }; + union + { + __IOM uint32_t REG_CCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CCCH_b; + }; + union + { + __IOM uint32_t REG_CD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CD0H_b; + }; + union + { + __IOM uint32_t REG_CD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CD4H_b; + }; + union + { + __IOM uint32_t REG_CD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CD8H_b; + }; + union + { + __IOM uint32_t REG_CDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CDCH_b; + }; + union + { + __IOM uint32_t REG_CE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CE0H_b; + }; + union + { + __IOM uint32_t REG_CE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CE4H_b; + }; + union + { + __IOM uint32_t REG_CE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CE8H_b; + }; + union + { + __IOM uint32_t REG_CECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CECH_b; + }; + union + { + __IOM uint32_t REG_CF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CF0H_b; + }; + union + { + __IOM uint32_t REG_CF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CF4H_b; + }; + union + { + __IOM uint32_t REG_CF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CF8H_b; + }; + union + { + __IOM uint32_t REG_CFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_CFCH_b; + }; + union + { + __IOM uint32_t REG_D00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D00H_b; + }; + union + { + __IOM uint32_t REG_D04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D04H_b; + }; + union + { + __IOM uint32_t REG_D08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D08H_b; + }; + union + { + __IOM uint32_t REG_D0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D0CH_b; + }; + union + { + __IOM uint32_t REG_D10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D10H_b; + }; + union + { + __IOM uint32_t REG_D14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D14H_b; + }; + union + { + __IOM uint32_t REG_D18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D18H_b; + }; + union + { + __IOM uint32_t REG_D1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D1CH_b; + }; + union + { + __IOM uint32_t REG_D20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D20H_b; + }; + union + { + __IOM uint32_t REG_D24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D24H_b; + }; + union + { + __IOM uint32_t REG_D28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D28H_b; + }; + union + { + __IOM uint32_t REG_D2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D2CH_b; + }; + union + { + __IOM uint32_t REG_D30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D30H_b; + }; + union + { + __IOM uint32_t REG_D34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D34H_b; + }; + union + { + __IOM uint32_t REG_D38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D38H_b; + }; + union + { + __IOM uint32_t REG_D3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D3CH_b; + }; + union + { + __IOM uint32_t REG_D40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D40H_b; + }; + union + { + __IOM uint32_t REG_D44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D44H_b; + }; + union + { + __IOM uint32_t REG_D48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D48H_b; + }; + union + { + __IOM uint32_t REG_D4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D4CH_b; + }; + union + { + __IOM uint32_t REG_D50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D50H_b; + }; + union + { + __IOM uint32_t REG_D54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D54H_b; + }; + union + { + __IOM uint32_t REG_D58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D58H_b; + }; + union + { + __IOM uint32_t REG_D5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D5CH_b; + }; + union + { + __IOM uint32_t REG_D60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D60H_b; + }; + union + { + __IOM uint32_t REG_D64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D64H_b; + }; + union + { + __IOM uint32_t REG_D68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D68H_b; + }; + union + { + __IOM uint32_t REG_D6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D6CH_b; + }; + union + { + __IOM uint32_t REG_D70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D70H_b; + }; + union + { + __IOM uint32_t REG_D74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D74H_b; + }; + union + { + __IOM uint32_t REG_D78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D78H_b; + }; + union + { + __IOM uint32_t REG_D7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D7CH_b; + }; + union + { + __IOM uint32_t REG_D80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D80H_b; + }; + union + { + __IOM uint32_t REG_D84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D84H_b; + }; + union + { + __IOM uint32_t REG_D88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D88H_b; + }; + union + { + __IOM uint32_t REG_D8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D8CH_b; + }; + union + { + __IOM uint32_t REG_D90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D90H_b; + }; + union + { + __IOM uint32_t REG_D94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D94H_b; + }; + union + { + __IOM uint32_t REG_D98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D98H_b; + }; + union + { + __IOM uint32_t REG_D9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_D9CH_b; + }; + union + { + __IOM uint32_t REG_DA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DA0H_b; + }; + union + { + __IOM uint32_t REG_DA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DA4H_b; + }; + union + { + __IOM uint32_t REG_DA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DA8H_b; + }; + union + { + __IOM uint32_t REG_DACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DACH_b; + }; + union + { + __IOM uint32_t REG_DB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DB0H_b; + }; + union + { + __IOM uint32_t REG_DB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DB4H_b; + }; + union + { + __IOM uint32_t REG_DB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DB8H_b; + }; + union + { + __IOM uint32_t REG_DBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DBCH_b; + }; + union + { + __IOM uint32_t REG_DC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DC0H_b; + }; + union + { + __IOM uint32_t REG_DC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DC4H_b; + }; + union + { + __IOM uint32_t REG_DC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DC8H_b; + }; + union + { + __IOM uint32_t REG_DCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DCCH_b; + }; + union + { + __IOM uint32_t REG_DD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DD0H_b; + }; + union + { + __IOM uint32_t REG_DD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DD4H_b; + }; + union + { + __IOM uint32_t REG_DD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DD8H_b; + }; + union + { + __IOM uint32_t REG_DDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DDCH_b; + }; + union + { + __IOM uint32_t REG_DE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DE0H_b; + }; + union + { + __IOM uint32_t REG_DE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DE4H_b; + }; + union + { + __IOM uint32_t REG_DE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DE8H_b; + }; + union + { + __IOM uint32_t REG_DECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DECH_b; + }; + union + { + __IOM uint32_t REG_DF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DF0H_b; + }; + union + { + __IOM uint32_t REG_DF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DF4H_b; + }; + union + { + __IOM uint32_t REG_DF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DF8H_b; + }; + union + { + __IOM uint32_t REG_DFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_DFCH_b; + }; + union + { + __IOM uint32_t REG_E00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E00H_b; + }; + union + { + __IOM uint32_t REG_E04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E04H_b; + }; + union + { + __IOM uint32_t REG_E08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E08H_b; + }; + union + { + __IOM uint32_t REG_E0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E0CH_b; + }; + union + { + __IOM uint32_t REG_E10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E10H_b; + }; + union + { + __IOM uint32_t REG_E14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E14H_b; + }; + union + { + __IOM uint32_t REG_E18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E18H_b; + }; + union + { + __IOM uint32_t REG_E1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E1CH_b; + }; + union + { + __IOM uint32_t REG_E20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E20H_b; + }; + union + { + __IOM uint32_t REG_E24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E24H_b; + }; + union + { + __IOM uint32_t REG_E28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E28H_b; + }; + union + { + __IOM uint32_t REG_E2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E2CH_b; + }; + union + { + __IOM uint32_t REG_E30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E30H_b; + }; + union + { + __IOM uint32_t REG_E34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E34H_b; + }; + union + { + __IOM uint32_t REG_E38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E38H_b; + }; + union + { + __IOM uint32_t REG_E3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E3CH_b; + }; + union + { + __IOM uint32_t REG_E40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E40H_b; + }; + union + { + __IOM uint32_t REG_E44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E44H_b; + }; + union + { + __IOM uint32_t REG_E48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E48H_b; + }; + union + { + __IOM uint32_t REG_E4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E4CH_b; + }; + union + { + __IOM uint32_t REG_E50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E50H_b; + }; + union + { + __IOM uint32_t REG_E54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E54H_b; + }; + union + { + __IOM uint32_t REG_E58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E58H_b; + }; + union + { + __IOM uint32_t REG_E5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E5CH_b; + }; + union + { + __IOM uint32_t REG_E60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E60H_b; + }; + union + { + __IOM uint32_t REG_E64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E64H_b; + }; + union + { + __IOM uint32_t REG_E68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E68H_b; + }; + union + { + __IOM uint32_t REG_E6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E6CH_b; + }; + union + { + __IOM uint32_t REG_E70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E70H_b; + }; + union + { + __IOM uint32_t REG_E74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E74H_b; + }; + union + { + __IOM uint32_t REG_E78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E78H_b; + }; + union + { + __IOM uint32_t REG_E7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E7CH_b; + }; + union + { + __IOM uint32_t REG_E80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E80H_b; + }; + union + { + __IOM uint32_t REG_E84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E84H_b; + }; + union + { + __IOM uint32_t REG_E88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E88H_b; + }; + union + { + __IOM uint32_t REG_E8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E8CH_b; + }; + union + { + __IOM uint32_t REG_E90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E90H_b; + }; + union + { + __IOM uint32_t REG_E94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E94H_b; + }; + union + { + __IOM uint32_t REG_E98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E98H_b; + }; + union + { + __IOM uint32_t REG_E9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_E9CH_b; + }; + union + { + __IOM uint32_t REG_EA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EA0H_b; + }; + union + { + __IOM uint32_t REG_EA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EA4H_b; + }; + union + { + __IOM uint32_t REG_EA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EA8H_b; + }; + union + { + __IOM uint32_t REG_EACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EACH_b; + }; + union + { + __IOM uint32_t REG_EB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EB0H_b; + }; + union + { + __IOM uint32_t REG_EB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EB4H_b; + }; + union + { + __IOM uint32_t REG_EB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EB8H_b; + }; + union + { + __IOM uint32_t REG_EBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EBCH_b; + }; + union + { + __IOM uint32_t REG_EC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EC0H_b; + }; + union + { + __IOM uint32_t REG_EC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EC4H_b; + }; + union + { + __IOM uint32_t REG_EC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EC8H_b; + }; + union + { + __IOM uint32_t REG_ECCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ECCH_b; + }; + union + { + __IOM uint32_t REG_ED0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ED0H_b; + }; + union + { + __IOM uint32_t REG_ED4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ED4H_b; + }; + union + { + __IOM uint32_t REG_ED8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_ED8H_b; + }; + union + { + __IOM uint32_t REG_EDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EDCH_b; + }; + union + { + __IOM uint32_t REG_EE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EE0H_b; + }; + union + { + __IOM uint32_t REG_EE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EE4H_b; + }; + union + { + __IOM uint32_t REG_EE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EE8H_b; + }; + union + { + __IOM uint32_t REG_EECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EECH_b; + }; + union + { + __IOM uint32_t REG_EF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EF0H_b; + }; + union + { + __IOM uint32_t REG_EF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EF4H_b; + }; + union + { + __IOM uint32_t REG_EF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EF8H_b; + }; + union + { + __IOM uint32_t REG_EFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_EFCH_b; + }; + union + { + __IOM uint32_t REG_F00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F00H_b; + }; + union + { + __IOM uint32_t REG_F04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F04H_b; + }; + union + { + __IOM uint32_t REG_F08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F08H_b; + }; + union + { + __IOM uint32_t REG_F0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F0CH_b; + }; + union + { + __IOM uint32_t REG_F10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F10H_b; + }; + union + { + __IOM uint32_t REG_F14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F14H_b; + }; + union + { + __IOM uint32_t REG_F18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F18H_b; + }; + union + { + __IOM uint32_t REG_F1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F1CH_b; + }; + union + { + __IOM uint32_t REG_F20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F20H_b; + }; + union + { + __IOM uint32_t REG_F24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F24H_b; + }; + union + { + __IOM uint32_t REG_F28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F28H_b; + }; + union + { + __IOM uint32_t REG_F2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F2CH_b; + }; + union + { + __IOM uint32_t REG_F30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F30H_b; + }; + union + { + __IOM uint32_t REG_F34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F34H_b; + }; + union + { + __IOM uint32_t REG_F38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F38H_b; + }; + union + { + __IOM uint32_t REG_F3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F3CH_b; + }; + union + { + __IOM uint32_t REG_F40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F40H_b; + }; + union + { + __IOM uint32_t REG_F44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F44H_b; + }; + union + { + __IOM uint32_t REG_F48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F48H_b; + }; + union + { + __IOM uint32_t REG_F4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F4CH_b; + }; + union + { + __IOM uint32_t REG_F50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F50H_b; + }; + union + { + __IOM uint32_t REG_F54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F54H_b; + }; + union + { + __IOM uint32_t REG_F58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F58H_b; + }; + union + { + __IOM uint32_t REG_F5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F5CH_b; + }; + union + { + __IOM uint32_t REG_F60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F60H_b; + }; + union + { + __IOM uint32_t REG_F64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F64H_b; + }; + union + { + __IOM uint32_t REG_F68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F68H_b; + }; + union + { + __IOM uint32_t REG_F6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F6CH_b; + }; + union + { + __IOM uint32_t REG_F70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F70H_b; + }; + union + { + __IOM uint32_t REG_F74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F74H_b; + }; + union + { + __IOM uint32_t REG_F78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F78H_b; + }; + union + { + __IOM uint32_t REG_F7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F7CH_b; + }; + union + { + __IOM uint32_t REG_F80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F80H_b; + }; + union + { + __IOM uint32_t REG_F84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F84H_b; + }; + union + { + __IOM uint32_t REG_F88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F88H_b; + }; + union + { + __IOM uint32_t REG_F8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F8CH_b; + }; + union + { + __IOM uint32_t REG_F90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F90H_b; + }; + union + { + __IOM uint32_t REG_F94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F94H_b; + }; + union + { + __IOM uint32_t REG_F98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F98H_b; + }; + union + { + __IOM uint32_t REG_F9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_F9CH_b; + }; + union + { + __IOM uint32_t REG_FA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FA0H_b; + }; + union + { + __IOM uint32_t REG_FA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FA4H_b; + }; + union + { + __IOM uint32_t REG_FA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FA8H_b; + }; + union + { + __IOM uint32_t REG_FACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FACH_b; + }; + union + { + __IOM uint32_t REG_FB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FB0H_b; + }; + union + { + __IOM uint32_t REG_FB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FB4H_b; + }; + union + { + __IOM uint32_t REG_FB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FB8H_b; + }; + union + { + __IOM uint32_t REG_FBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FBCH_b; + }; + union + { + __IOM uint32_t REG_FC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FC0H_b; + }; + union + { + __IOM uint32_t REG_FC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FC4H_b; + }; + union + { + __IOM uint32_t REG_FC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FC8H_b; + }; + union + { + __IOM uint32_t REG_FCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FCCH_b; + }; + union + { + __IOM uint32_t REG_FD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FD0H_b; + }; + union + { + __IOM uint32_t REG_FD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FD4H_b; + }; + union + { + __IOM uint32_t REG_FD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FD8H_b; + }; + union + { + __IOM uint32_t REG_FDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FDCH_b; + }; + union + { + __IOM uint32_t REG_FE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FE0H_b; + }; + union + { + __IOM uint32_t REG_FE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FE4H_b; + }; + union + { + __IOM uint32_t REG_FE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FE8H_b; + }; + union + { + __IOM uint32_t REG_FECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FECH_b; + }; + union + { + __IOM uint32_t REG_FF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FF0H_b; + }; + union + { + __IOM uint32_t REG_FF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FF4H_b; + }; + union + { + __IOM uint32_t REG_FF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FF8H_b; + }; + union + { + __IOM uint32_t REG_FFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_FFCH_b; + }; + union + { + __IOM uint32_t REG_1000H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1000H_b; + }; + union + { + __IOM uint32_t REG_1004H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1004H_b; + }; + union + { + __IOM uint32_t REG_1008H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1008H_b; + }; + union + { + __IOM uint32_t REG_100CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_100CH_b; + }; + union + { + __IOM uint32_t REG_1010H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1010H_b; + }; + union + { + __IOM uint32_t REG_1014H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1014H_b; + }; + union + { + __IOM uint32_t REG_1018H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1018H_b; + }; + union + { + __IOM uint32_t REG_101CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_101CH_b; + }; + union + { + __IOM uint32_t REG_1020H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1020H_b; + }; + union + { + __IOM uint32_t REG_1024H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1024H_b; + }; + union + { + __IOM uint32_t REG_1028H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1028H_b; + }; + union + { + __IOM uint32_t REG_102CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_102CH_b; + }; + union + { + __IOM uint32_t REG_1030H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1030H_b; + }; + union + { + __IOM uint32_t REG_1034H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1034H_b; + }; + union + { + __IOM uint32_t REG_1038H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1038H_b; + }; + union + { + __IOM uint32_t REG_103CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_103CH_b; + }; + union + { + __IOM uint32_t REG_1040H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1040H_b; + }; + union + { + __IOM uint32_t REG_1044H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1044H_b; + }; + union + { + __IOM uint32_t REG_1048H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1048H_b; + }; + union + { + __IOM uint32_t REG_104CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_104CH_b; + }; + union + { + __IOM uint32_t REG_1050H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1050H_b; + }; + union + { + __IOM uint32_t REG_1054H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1054H_b; + }; + union + { + __IOM uint32_t REG_1058H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1058H_b; + }; + union + { + __IOM uint32_t REG_105CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_105CH_b; + }; + union + { + __IOM uint32_t REG_1060H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1060H_b; + }; + union + { + __IOM uint32_t REG_1064H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1064H_b; + }; + union + { + __IOM uint32_t REG_1068H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1068H_b; + }; + union + { + __IOM uint32_t REG_106CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_106CH_b; + }; + union + { + __IOM uint32_t REG_1070H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1070H_b; + }; + union + { + __IOM uint32_t REG_1074H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1074H_b; + }; + union + { + __IOM uint32_t REG_1078H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1078H_b; + }; + union + { + __IOM uint32_t REG_107CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_107CH_b; + }; + union + { + __IOM uint32_t REG_1080H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1080H_b; + }; + union + { + __IOM uint32_t REG_1084H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1084H_b; + }; + union + { + __IOM uint32_t REG_1088H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1088H_b; + }; + union + { + __IOM uint32_t REG_108CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_108CH_b; + }; + union + { + __IOM uint32_t REG_1090H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1090H_b; + }; + union + { + __IOM uint32_t REG_1094H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1094H_b; + }; + union + { + __IOM uint32_t REG_1098H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1098H_b; + }; + union + { + __IOM uint32_t REG_109CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_109CH_b; + }; + union + { + __IOM uint32_t REG_10A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10A0H_b; + }; + union + { + __IOM uint32_t REG_10A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10A4H_b; + }; + union + { + __IOM uint32_t REG_10A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10A8H_b; + }; + union + { + __IOM uint32_t REG_10ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10ACH_b; + }; + union + { + __IOM uint32_t REG_10B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10B0H_b; + }; + union + { + __IOM uint32_t REG_10B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10B4H_b; + }; + union + { + __IOM uint32_t REG_10B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10B8H_b; + }; + union + { + __IOM uint32_t REG_10BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10BCH_b; + }; + union + { + __IOM uint32_t REG_10C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10C0H_b; + }; + union + { + __IOM uint32_t REG_10C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10C4H_b; + }; + union + { + __IOM uint32_t REG_10C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10C8H_b; + }; + union + { + __IOM uint32_t REG_10CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10CCH_b; + }; + union + { + __IOM uint32_t REG_10D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10D0H_b; + }; + union + { + __IOM uint32_t REG_10D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10D4H_b; + }; + union + { + __IOM uint32_t REG_10D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10D8H_b; + }; + union + { + __IOM uint32_t REG_10DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10DCH_b; + }; + union + { + __IOM uint32_t REG_10E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10E0H_b; + }; + union + { + __IOM uint32_t REG_10E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10E4H_b; + }; + union + { + __IOM uint32_t REG_10E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10E8H_b; + }; + union + { + __IOM uint32_t REG_10ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10ECH_b; + }; + union + { + __IOM uint32_t REG_10F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10F0H_b; + }; + union + { + __IOM uint32_t REG_10F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10F4H_b; + }; + union + { + __IOM uint32_t REG_10F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10F8H_b; + }; + union + { + __IOM uint32_t REG_10FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_10FCH_b; + }; + union + { + __IOM uint32_t REG_1100H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1100H_b; + }; + union + { + __IOM uint32_t REG_1104H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1104H_b; + }; + union + { + __IOM uint32_t REG_1108H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1108H_b; + }; + union + { + __IOM uint32_t REG_110CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_110CH_b; + }; + union + { + __IOM uint32_t REG_1110H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1110H_b; + }; + union + { + __IOM uint32_t REG_1114H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1114H_b; + }; + union + { + __IOM uint32_t REG_1118H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1118H_b; + }; + union + { + __IOM uint32_t REG_111CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_111CH_b; + }; + union + { + __IOM uint32_t REG_1120H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1120H_b; + }; + union + { + __IOM uint32_t REG_1124H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1124H_b; + }; + union + { + __IOM uint32_t REG_1128H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1128H_b; + }; + union + { + __IOM uint32_t REG_112CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_112CH_b; + }; + union + { + __IOM uint32_t REG_1130H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1130H_b; + }; + union + { + __IOM uint32_t REG_1134H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1134H_b; + }; + union + { + __IOM uint32_t REG_1138H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1138H_b; + }; + union + { + __IOM uint32_t REG_113CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_113CH_b; + }; + union + { + __IOM uint32_t REG_1140H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1140H_b; + }; + union + { + __IOM uint32_t REG_1144H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1144H_b; + }; + union + { + __IOM uint32_t REG_1148H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1148H_b; + }; + union + { + __IOM uint32_t REG_114CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_114CH_b; + }; + union + { + __IOM uint32_t REG_1150H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1150H_b; + }; + union + { + __IOM uint32_t REG_1154H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1154H_b; + }; + union + { + __IOM uint32_t REG_1158H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1158H_b; + }; + union + { + __IOM uint32_t REG_115CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_115CH_b; + }; + union + { + __IOM uint32_t REG_1160H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1160H_b; + }; + union + { + __IOM uint32_t REG_1164H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1164H_b; + }; + union + { + __IOM uint32_t REG_1168H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1168H_b; + }; + union + { + __IOM uint32_t REG_116CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_116CH_b; + }; + union + { + __IOM uint32_t REG_1170H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1170H_b; + }; + union + { + __IOM uint32_t REG_1174H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1174H_b; + }; + union + { + __IOM uint32_t REG_1178H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1178H_b; + }; + union + { + __IOM uint32_t REG_117CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_117CH_b; + }; + union + { + __IOM uint32_t REG_1180H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1180H_b; + }; + union + { + __IOM uint32_t REG_1184H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1184H_b; + }; + union + { + __IOM uint32_t REG_1188H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1188H_b; + }; + union + { + __IOM uint32_t REG_118CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_118CH_b; + }; + union + { + __IOM uint32_t REG_1190H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1190H_b; + }; + union + { + __IOM uint32_t REG_1194H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1194H_b; + }; + union + { + __IOM uint32_t REG_1198H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1198H_b; + }; + union + { + __IOM uint32_t REG_119CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_119CH_b; + }; + union + { + __IOM uint32_t REG_11A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11A0H_b; + }; + union + { + __IOM uint32_t REG_11A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11A4H_b; + }; + union + { + __IOM uint32_t REG_11A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11A8H_b; + }; + union + { + __IOM uint32_t REG_11ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11ACH_b; + }; + union + { + __IOM uint32_t REG_11B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11B0H_b; + }; + union + { + __IOM uint32_t REG_11B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11B4H_b; + }; + union + { + __IOM uint32_t REG_11B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11B8H_b; + }; + union + { + __IOM uint32_t REG_11BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11BCH_b; + }; + union + { + __IOM uint32_t REG_11C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11C0H_b; + }; + union + { + __IOM uint32_t REG_11C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11C4H_b; + }; + union + { + __IOM uint32_t REG_11C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11C8H_b; + }; + union + { + __IOM uint32_t REG_11CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11CCH_b; + }; + union + { + __IOM uint32_t REG_11D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11D0H_b; + }; + union + { + __IOM uint32_t REG_11D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11D4H_b; + }; + union + { + __IOM uint32_t REG_11D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11D8H_b; + }; + union + { + __IOM uint32_t REG_11DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11DCH_b; + }; + union + { + __IOM uint32_t REG_11E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11E0H_b; + }; + union + { + __IOM uint32_t REG_11E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11E4H_b; + }; + union + { + __IOM uint32_t REG_11E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11E8H_b; + }; + union + { + __IOM uint32_t REG_11ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11ECH_b; + }; + union + { + __IOM uint32_t REG_11F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11F0H_b; + }; + union + { + __IOM uint32_t REG_11F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11F4H_b; + }; + union + { + __IOM uint32_t REG_11F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11F8H_b; + }; + union + { + __IOM uint32_t REG_11FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_11FCH_b; + }; + union + { + __IOM uint32_t REG_1200H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1200H_b; + }; + union + { + __IOM uint32_t REG_1204H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1204H_b; + }; + union + { + __IOM uint32_t REG_1208H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1208H_b; + }; + union + { + __IOM uint32_t REG_120CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_120CH_b; + }; + union + { + __IOM uint32_t REG_1210H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1210H_b; + }; + union + { + __IOM uint32_t REG_1214H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1214H_b; + }; + union + { + __IOM uint32_t REG_1218H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1218H_b; + }; + union + { + __IOM uint32_t REG_121CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_121CH_b; + }; + union + { + __IOM uint32_t REG_1220H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1220H_b; + }; + union + { + __IOM uint32_t REG_1224H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1224H_b; + }; + union + { + __IOM uint32_t REG_1228H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1228H_b; + }; + union + { + __IOM uint32_t REG_122CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_122CH_b; + }; + union + { + __IOM uint32_t REG_1230H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1230H_b; + }; + union + { + __IOM uint32_t REG_1234H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1234H_b; + }; + union + { + __IOM uint32_t REG_1238H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1238H_b; + }; + union + { + __IOM uint32_t REG_123CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_123CH_b; + }; + union + { + __IOM uint32_t REG_1240H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1240H_b; + }; + union + { + __IOM uint32_t REG_1244H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1244H_b; + }; + union + { + __IOM uint32_t REG_1248H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1248H_b; + }; + union + { + __IOM uint32_t REG_124CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_124CH_b; + }; + union + { + __IOM uint32_t REG_1250H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1250H_b; + }; + union + { + __IOM uint32_t REG_1254H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1254H_b; + }; + union + { + __IOM uint32_t REG_1258H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1258H_b; + }; + union + { + __IOM uint32_t REG_125CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_125CH_b; + }; + union + { + __IOM uint32_t REG_1260H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1260H_b; + }; + union + { + __IOM uint32_t REG_1264H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1264H_b; + }; + union + { + __IOM uint32_t REG_1268H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1268H_b; + }; + union + { + __IOM uint32_t REG_126CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_126CH_b; + }; + union + { + __IOM uint32_t REG_1270H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1270H_b; + }; + union + { + __IOM uint32_t REG_1274H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1274H_b; + }; + union + { + __IOM uint32_t REG_1278H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1278H_b; + }; + union + { + __IOM uint32_t REG_127CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_127CH_b; + }; + union + { + __IOM uint32_t REG_1280H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1280H_b; + }; + union + { + __IOM uint32_t REG_1284H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1284H_b; + }; + union + { + __IOM uint32_t REG_1288H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1288H_b; + }; + union + { + __IOM uint32_t REG_128CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_128CH_b; + }; + union + { + __IOM uint32_t REG_1290H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1290H_b; + }; + union + { + __IOM uint32_t REG_1294H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1294H_b; + }; + union + { + __IOM uint32_t REG_1298H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1298H_b; + }; + union + { + __IOM uint32_t REG_129CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_129CH_b; + }; + union + { + __IOM uint32_t REG_12A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12A0H_b; + }; + union + { + __IOM uint32_t REG_12A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12A4H_b; + }; + union + { + __IOM uint32_t REG_12A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12A8H_b; + }; + union + { + __IOM uint32_t REG_12ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12ACH_b; + }; + union + { + __IOM uint32_t REG_12B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12B0H_b; + }; + union + { + __IOM uint32_t REG_12B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12B4H_b; + }; + union + { + __IOM uint32_t REG_12B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12B8H_b; + }; + union + { + __IOM uint32_t REG_12BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12BCH_b; + }; + union + { + __IOM uint32_t REG_12C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12C0H_b; + }; + union + { + __IOM uint32_t REG_12C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12C4H_b; + }; + union + { + __IOM uint32_t REG_12C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12C8H_b; + }; + union + { + __IOM uint32_t REG_12CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12CCH_b; + }; + union + { + __IOM uint32_t REG_12D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12D0H_b; + }; + union + { + __IOM uint32_t REG_12D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12D4H_b; + }; + union + { + __IOM uint32_t REG_12D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12D8H_b; + }; + union + { + __IOM uint32_t REG_12DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12DCH_b; + }; + union + { + __IOM uint32_t REG_12E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12E0H_b; + }; + union + { + __IOM uint32_t REG_12E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12E4H_b; + }; + union + { + __IOM uint32_t REG_12E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12E8H_b; + }; + union + { + __IOM uint32_t REG_12ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12ECH_b; + }; + union + { + __IOM uint32_t REG_12F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12F0H_b; + }; + union + { + __IOM uint32_t REG_12F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12F4H_b; + }; + union + { + __IOM uint32_t REG_12F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12F8H_b; + }; + union + { + __IOM uint32_t REG_12FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_12FCH_b; + }; + union + { + __IOM uint32_t REG_1300H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1300H_b; + }; + union + { + __IOM uint32_t REG_1304H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1304H_b; + }; + union + { + __IOM uint32_t REG_1308H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1308H_b; + }; + union + { + __IOM uint32_t REG_130CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_130CH_b; + }; + union + { + __IOM uint32_t REG_1310H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1310H_b; + }; + union + { + __IOM uint32_t REG_1314H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1314H_b; + }; + union + { + __IOM uint32_t REG_1318H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1318H_b; + }; + union + { + __IOM uint32_t REG_131CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_131CH_b; + }; + union + { + __IOM uint32_t REG_1320H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1320H_b; + }; + union + { + __IOM uint32_t REG_1324H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1324H_b; + }; + union + { + __IOM uint32_t REG_1328H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1328H_b; + }; + union + { + __IOM uint32_t REG_132CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_132CH_b; + }; + union + { + __IOM uint32_t REG_1330H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1330H_b; + }; + union + { + __IOM uint32_t REG_1334H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1334H_b; + }; + union + { + __IOM uint32_t REG_1338H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1338H_b; + }; + union + { + __IOM uint32_t REG_133CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_133CH_b; + }; + union + { + __IOM uint32_t REG_1340H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1340H_b; + }; + union + { + __IOM uint32_t REG_1344H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1344H_b; + }; + union + { + __IOM uint32_t REG_1348H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1348H_b; + }; + union + { + __IOM uint32_t REG_134CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_134CH_b; + }; + union + { + __IOM uint32_t REG_1350H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1350H_b; + }; + union + { + __IOM uint32_t REG_1354H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1354H_b; + }; + union + { + __IOM uint32_t REG_1358H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1358H_b; + }; + union + { + __IOM uint32_t REG_135CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_135CH_b; + }; + union + { + __IOM uint32_t REG_1360H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1360H_b; + }; + union + { + __IOM uint32_t REG_1364H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1364H_b; + }; + union + { + __IOM uint32_t REG_1368H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1368H_b; + }; + union + { + __IOM uint32_t REG_136CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_136CH_b; + }; + union + { + __IOM uint32_t REG_1370H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1370H_b; + }; + union + { + __IOM uint32_t REG_1374H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1374H_b; + }; + union + { + __IOM uint32_t REG_1378H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1378H_b; + }; + union + { + __IOM uint32_t REG_137CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_137CH_b; + }; + union + { + __IOM uint32_t REG_1380H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1380H_b; + }; + union + { + __IOM uint32_t REG_1384H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1384H_b; + }; + union + { + __IOM uint32_t REG_1388H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1388H_b; + }; + union + { + __IOM uint32_t REG_138CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_138CH_b; + }; + union + { + __IOM uint32_t REG_1390H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1390H_b; + }; + union + { + __IOM uint32_t REG_1394H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1394H_b; + }; + union + { + __IOM uint32_t REG_1398H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1398H_b; + }; + union + { + __IOM uint32_t REG_139CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_139CH_b; + }; + union + { + __IOM uint32_t REG_13A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13A0H_b; + }; + union + { + __IOM uint32_t REG_13A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13A4H_b; + }; + union + { + __IOM uint32_t REG_13A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13A8H_b; + }; + union + { + __IOM uint32_t REG_13ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13ACH_b; + }; + union + { + __IOM uint32_t REG_13B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13B0H_b; + }; + union + { + __IOM uint32_t REG_13B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13B4H_b; + }; + union + { + __IOM uint32_t REG_13B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13B8H_b; + }; + union + { + __IOM uint32_t REG_13BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13BCH_b; + }; + union + { + __IOM uint32_t REG_13C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13C0H_b; + }; + union + { + __IOM uint32_t REG_13C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13C4H_b; + }; + union + { + __IOM uint32_t REG_13C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13C8H_b; + }; + union + { + __IOM uint32_t REG_13CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13CCH_b; + }; + union + { + __IOM uint32_t REG_13D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13D0H_b; + }; + union + { + __IOM uint32_t REG_13D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13D4H_b; + }; + union + { + __IOM uint32_t REG_13D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13D8H_b; + }; + union + { + __IOM uint32_t REG_13DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13DCH_b; + }; + union + { + __IOM uint32_t REG_13E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13E0H_b; + }; + union + { + __IOM uint32_t REG_13E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13E4H_b; + }; + union + { + __IOM uint32_t REG_13E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13E8H_b; + }; + union + { + __IOM uint32_t REG_13ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13ECH_b; + }; + union + { + __IOM uint32_t REG_13F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13F0H_b; + }; + union + { + __IOM uint32_t REG_13F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13F4H_b; + }; + union + { + __IOM uint32_t REG_13F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13F8H_b; + }; + union + { + __IOM uint32_t REG_13FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_13FCH_b; + }; + union + { + __IOM uint32_t REG_1400H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1400H_b; + }; + union + { + __IOM uint32_t REG_1404H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1404H_b; + }; + union + { + __IOM uint32_t REG_1408H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1408H_b; + }; + union + { + __IOM uint32_t REG_140CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_140CH_b; + }; + union + { + __IOM uint32_t REG_1410H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1410H_b; + }; + union + { + __IOM uint32_t REG_1414H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1414H_b; + }; + union + { + __IOM uint32_t REG_1418H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1418H_b; + }; + union + { + __IOM uint32_t REG_141CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_141CH_b; + }; + union + { + __IOM uint32_t REG_1420H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1420H_b; + }; + union + { + __IOM uint32_t REG_1424H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1424H_b; + }; + union + { + __IOM uint32_t REG_1428H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1428H_b; + }; + union + { + __IOM uint32_t REG_142CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_142CH_b; + }; + union + { + __IOM uint32_t REG_1430H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1430H_b; + }; + union + { + __IOM uint32_t REG_1434H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1434H_b; + }; + union + { + __IOM uint32_t REG_1438H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1438H_b; + }; + union + { + __IOM uint32_t REG_143CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_143CH_b; + }; + union + { + __IOM uint32_t REG_1440H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1440H_b; + }; + union + { + __IOM uint32_t REG_1444H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1444H_b; + }; + union + { + __IOM uint32_t REG_1448H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1448H_b; + }; + union + { + __IOM uint32_t REG_144CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_144CH_b; + }; + union + { + __IOM uint32_t REG_1450H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1450H_b; + }; + union + { + __IOM uint32_t REG_1454H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1454H_b; + }; + union + { + __IOM uint32_t REG_1458H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1458H_b; + }; + union + { + __IOM uint32_t REG_145CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_145CH_b; + }; + union + { + __IOM uint32_t REG_1460H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1460H_b; + }; + union + { + __IOM uint32_t REG_1464H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1464H_b; + }; + union + { + __IOM uint32_t REG_1468H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1468H_b; + }; + union + { + __IOM uint32_t REG_146CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_146CH_b; + }; + union + { + __IOM uint32_t REG_1470H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1470H_b; + }; + union + { + __IOM uint32_t REG_1474H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1474H_b; + }; + union + { + __IOM uint32_t REG_1478H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1478H_b; + }; + union + { + __IOM uint32_t REG_147CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_147CH_b; + }; + union + { + __IOM uint32_t REG_1480H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1480H_b; + }; + union + { + __IOM uint32_t REG_1484H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1484H_b; + }; + union + { + __IOM uint32_t REG_1488H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1488H_b; + }; + union + { + __IOM uint32_t REG_148CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_148CH_b; + }; + union + { + __IOM uint32_t REG_1490H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1490H_b; + }; + union + { + __IOM uint32_t REG_1494H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1494H_b; + }; + union + { + __IOM uint32_t REG_1498H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1498H_b; + }; + union + { + __IOM uint32_t REG_149CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_149CH_b; + }; + union + { + __IOM uint32_t REG_14A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14A0H_b; + }; + union + { + __IOM uint32_t REG_14A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14A4H_b; + }; + union + { + __IOM uint32_t REG_14A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14A8H_b; + }; + union + { + __IOM uint32_t REG_14ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14ACH_b; + }; + union + { + __IOM uint32_t REG_14B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14B0H_b; + }; + union + { + __IOM uint32_t REG_14B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14B4H_b; + }; + union + { + __IOM uint32_t REG_14B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14B8H_b; + }; + union + { + __IOM uint32_t REG_14BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14BCH_b; + }; + union + { + __IOM uint32_t REG_14C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14C0H_b; + }; + union + { + __IOM uint32_t REG_14C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14C4H_b; + }; + union + { + __IOM uint32_t REG_14C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14C8H_b; + }; + union + { + __IOM uint32_t REG_14CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14CCH_b; + }; + union + { + __IOM uint32_t REG_14D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14D0H_b; + }; + union + { + __IOM uint32_t REG_14D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14D4H_b; + }; + union + { + __IOM uint32_t REG_14D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14D8H_b; + }; + union + { + __IOM uint32_t REG_14DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14DCH_b; + }; + union + { + __IOM uint32_t REG_14E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14E0H_b; + }; + union + { + __IOM uint32_t REG_14E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14E4H_b; + }; + union + { + __IOM uint32_t REG_14E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14E8H_b; + }; + union + { + __IOM uint32_t REG_14ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14ECH_b; + }; + union + { + __IOM uint32_t REG_14F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14F0H_b; + }; + union + { + __IOM uint32_t REG_14F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14F4H_b; + }; + union + { + __IOM uint32_t REG_14F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14F8H_b; + }; + union + { + __IOM uint32_t REG_14FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_14FCH_b; + }; + union + { + __IOM uint32_t REG_1500H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1500H_b; + }; + union + { + __IOM uint32_t REG_1504H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1504H_b; + }; + union + { + __IOM uint32_t REG_1508H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1508H_b; + }; + union + { + __IOM uint32_t REG_150CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_150CH_b; + }; + union + { + __IOM uint32_t REG_1510H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1510H_b; + }; + union + { + __IOM uint32_t REG_1514H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1514H_b; + }; + union + { + __IOM uint32_t REG_1518H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1518H_b; + }; + union + { + __IOM uint32_t REG_151CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_151CH_b; + }; + union + { + __IOM uint32_t REG_1520H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1520H_b; + }; + union + { + __IOM uint32_t REG_1524H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1524H_b; + }; + union + { + __IOM uint32_t REG_1528H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1528H_b; + }; + union + { + __IOM uint32_t REG_152CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_152CH_b; + }; + union + { + __IOM uint32_t REG_1530H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1530H_b; + }; + union + { + __IOM uint32_t REG_1534H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1534H_b; + }; + union + { + __IOM uint32_t REG_1538H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1538H_b; + }; + union + { + __IOM uint32_t REG_153CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_153CH_b; + }; + union + { + __IOM uint32_t REG_1540H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1540H_b; + }; + union + { + __IOM uint32_t REG_1544H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1544H_b; + }; + union + { + __IOM uint32_t REG_1548H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1548H_b; + }; + union + { + __IOM uint32_t REG_154CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_154CH_b; + }; + union + { + __IOM uint32_t REG_1550H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1550H_b; + }; + union + { + __IOM uint32_t REG_1554H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1554H_b; + }; + union + { + __IOM uint32_t REG_1558H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1558H_b; + }; + union + { + __IOM uint32_t REG_155CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_155CH_b; + }; + union + { + __IOM uint32_t REG_1560H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1560H_b; + }; + union + { + __IOM uint32_t REG_1564H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1564H_b; + }; + union + { + __IOM uint32_t REG_1568H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1568H_b; + }; + union + { + __IOM uint32_t REG_156CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_156CH_b; + }; + union + { + __IOM uint32_t REG_1570H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1570H_b; + }; + union + { + __IOM uint32_t REG_1574H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1574H_b; + }; + union + { + __IOM uint32_t REG_1578H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1578H_b; + }; + union + { + __IOM uint32_t REG_157CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_157CH_b; + }; + union + { + __IOM uint32_t REG_1580H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1580H_b; + }; + union + { + __IOM uint32_t REG_1584H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1584H_b; + }; + union + { + __IOM uint32_t REG_1588H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1588H_b; + }; + union + { + __IOM uint32_t REG_158CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_158CH_b; + }; + union + { + __IOM uint32_t REG_1590H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1590H_b; + }; + union + { + __IOM uint32_t REG_1594H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1594H_b; + }; + union + { + __IOM uint32_t REG_1598H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1598H_b; + }; + union + { + __IOM uint32_t REG_159CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_159CH_b; + }; + union + { + __IOM uint32_t REG_15A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15A0H_b; + }; + union + { + __IOM uint32_t REG_15A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15A4H_b; + }; + union + { + __IOM uint32_t REG_15A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15A8H_b; + }; + union + { + __IOM uint32_t REG_15ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15ACH_b; + }; + union + { + __IOM uint32_t REG_15B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15B0H_b; + }; + union + { + __IOM uint32_t REG_15B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15B4H_b; + }; + union + { + __IOM uint32_t REG_15B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15B8H_b; + }; + union + { + __IOM uint32_t REG_15BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15BCH_b; + }; + union + { + __IOM uint32_t REG_15C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15C0H_b; + }; + union + { + __IOM uint32_t REG_15C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15C4H_b; + }; + union + { + __IOM uint32_t REG_15C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15C8H_b; + }; + union + { + __IOM uint32_t REG_15CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15CCH_b; + }; + union + { + __IOM uint32_t REG_15D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15D0H_b; + }; + union + { + __IOM uint32_t REG_15D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15D4H_b; + }; + union + { + __IOM uint32_t REG_15D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15D8H_b; + }; + union + { + __IOM uint32_t REG_15DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15DCH_b; + }; + union + { + __IOM uint32_t REG_15E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15E0H_b; + }; + union + { + __IOM uint32_t REG_15E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15E4H_b; + }; + union + { + __IOM uint32_t REG_15E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15E8H_b; + }; + union + { + __IOM uint32_t REG_15ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15ECH_b; + }; + union + { + __IOM uint32_t REG_15F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15F0H_b; + }; + union + { + __IOM uint32_t REG_15F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15F4H_b; + }; + union + { + __IOM uint32_t REG_15F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15F8H_b; + }; + union + { + __IOM uint32_t REG_15FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_15FCH_b; + }; + union + { + __IOM uint32_t REG_1600H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1600H_b; + }; + union + { + __IOM uint32_t REG_1604H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1604H_b; + }; + union + { + __IOM uint32_t REG_1608H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1608H_b; + }; + union + { + __IOM uint32_t REG_160CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_160CH_b; + }; + union + { + __IOM uint32_t REG_1610H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1610H_b; + }; + union + { + __IOM uint32_t REG_1614H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1614H_b; + }; + union + { + __IOM uint32_t REG_1618H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1618H_b; + }; + union + { + __IOM uint32_t REG_161CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_161CH_b; + }; + union + { + __IOM uint32_t REG_1620H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1620H_b; + }; + union + { + __IOM uint32_t REG_1624H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1624H_b; + }; + union + { + __IOM uint32_t REG_1628H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1628H_b; + }; + union + { + __IOM uint32_t REG_162CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_162CH_b; + }; + union + { + __IOM uint32_t REG_1630H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1630H_b; + }; + union + { + __IOM uint32_t REG_1634H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1634H_b; + }; + union + { + __IOM uint32_t REG_1638H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1638H_b; + }; + union + { + __IOM uint32_t REG_163CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_163CH_b; + }; + union + { + __IOM uint32_t REG_1640H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1640H_b; + }; + union + { + __IOM uint32_t REG_1644H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1644H_b; + }; + union + { + __IOM uint32_t REG_1648H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1648H_b; + }; + union + { + __IOM uint32_t REG_164CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_164CH_b; + }; + union + { + __IOM uint32_t REG_1650H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1650H_b; + }; + union + { + __IOM uint32_t REG_1654H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1654H_b; + }; + union + { + __IOM uint32_t REG_1658H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1658H_b; + }; + union + { + __IOM uint32_t REG_165CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_165CH_b; + }; + union + { + __IOM uint32_t REG_1660H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1660H_b; + }; + union + { + __IOM uint32_t REG_1664H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1664H_b; + }; + union + { + __IOM uint32_t REG_1668H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1668H_b; + }; + union + { + __IOM uint32_t REG_166CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_166CH_b; + }; + union + { + __IOM uint32_t REG_1670H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1670H_b; + }; + union + { + __IOM uint32_t REG_1674H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1674H_b; + }; + union + { + __IOM uint32_t REG_1678H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1678H_b; + }; + union + { + __IOM uint32_t REG_167CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_167CH_b; + }; + union + { + __IOM uint32_t REG_1680H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1680H_b; + }; + union + { + __IOM uint32_t REG_1684H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1684H_b; + }; + union + { + __IOM uint32_t REG_1688H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1688H_b; + }; + union + { + __IOM uint32_t REG_168CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_168CH_b; + }; + union + { + __IOM uint32_t REG_1690H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1690H_b; + }; + union + { + __IOM uint32_t REG_1694H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1694H_b; + }; + union + { + __IOM uint32_t REG_1698H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1698H_b; + }; + union + { + __IOM uint32_t REG_169CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_169CH_b; + }; + union + { + __IOM uint32_t REG_16A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16A0H_b; + }; + union + { + __IOM uint32_t REG_16A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16A4H_b; + }; + union + { + __IOM uint32_t REG_16A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16A8H_b; + }; + union + { + __IOM uint32_t REG_16ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16ACH_b; + }; + union + { + __IOM uint32_t REG_16B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16B0H_b; + }; + union + { + __IOM uint32_t REG_16B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16B4H_b; + }; + union + { + __IOM uint32_t REG_16B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16B8H_b; + }; + union + { + __IOM uint32_t REG_16BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16BCH_b; + }; + union + { + __IOM uint32_t REG_16C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16C0H_b; + }; + union + { + __IOM uint32_t REG_16C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16C4H_b; + }; + union + { + __IOM uint32_t REG_16C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16C8H_b; + }; + union + { + __IOM uint32_t REG_16CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16CCH_b; + }; + union + { + __IOM uint32_t REG_16D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16D0H_b; + }; + union + { + __IOM uint32_t REG_16D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16D4H_b; + }; + union + { + __IOM uint32_t REG_16D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16D8H_b; + }; + union + { + __IOM uint32_t REG_16DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16DCH_b; + }; + union + { + __IOM uint32_t REG_16E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16E0H_b; + }; + union + { + __IOM uint32_t REG_16E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16E4H_b; + }; + union + { + __IOM uint32_t REG_16E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16E8H_b; + }; + union + { + __IOM uint32_t REG_16ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16ECH_b; + }; + union + { + __IOM uint32_t REG_16F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16F0H_b; + }; + union + { + __IOM uint32_t REG_16F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16F4H_b; + }; + union + { + __IOM uint32_t REG_16F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16F8H_b; + }; + union + { + __IOM uint32_t REG_16FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_16FCH_b; + }; + union + { + __IOM uint32_t REG_1700H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1700H_b; + }; + union + { + __IOM uint32_t REG_1704H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1704H_b; + }; + union + { + __IOM uint32_t REG_1708H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1708H_b; + }; + union + { + __IOM uint32_t REG_170CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_170CH_b; + }; + union + { + __IOM uint32_t REG_1710H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1710H_b; + }; + union + { + __IOM uint32_t REG_1714H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1714H_b; + }; + union + { + __IOM uint32_t REG_1718H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1718H_b; + }; + union + { + __IOM uint32_t REG_171CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_171CH_b; + }; + union + { + __IOM uint32_t REG_1720H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1720H_b; + }; + union + { + __IOM uint32_t REG_1724H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1724H_b; + }; + union + { + __IOM uint32_t REG_1728H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1728H_b; + }; + union + { + __IOM uint32_t REG_172CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_172CH_b; + }; + union + { + __IOM uint32_t REG_1730H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1730H_b; + }; + union + { + __IOM uint32_t REG_1734H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1734H_b; + }; + union + { + __IOM uint32_t REG_1738H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1738H_b; + }; + union + { + __IOM uint32_t REG_173CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_173CH_b; + }; + union + { + __IOM uint32_t REG_1740H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1740H_b; + }; + union + { + __IOM uint32_t REG_1744H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1744H_b; + }; + union + { + __IOM uint32_t REG_1748H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1748H_b; + }; + union + { + __IOM uint32_t REG_174CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_174CH_b; + }; + union + { + __IOM uint32_t REG_1750H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1750H_b; + }; + union + { + __IOM uint32_t REG_1754H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1754H_b; + }; + union + { + __IOM uint32_t REG_1758H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1758H_b; + }; + union + { + __IOM uint32_t REG_175CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_175CH_b; + }; + union + { + __IOM uint32_t REG_1760H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1760H_b; + }; + union + { + __IOM uint32_t REG_1764H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1764H_b; + }; + union + { + __IOM uint32_t REG_1768H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1768H_b; + }; + union + { + __IOM uint32_t REG_176CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_176CH_b; + }; + union + { + __IOM uint32_t REG_1770H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1770H_b; + }; + union + { + __IOM uint32_t REG_1774H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1774H_b; + }; + union + { + __IOM uint32_t REG_1778H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1778H_b; + }; + union + { + __IOM uint32_t REG_177CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_177CH_b; + }; + union + { + __IOM uint32_t REG_1780H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1780H_b; + }; + union + { + __IOM uint32_t REG_1784H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1784H_b; + }; + union + { + __IOM uint32_t REG_1788H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1788H_b; + }; + union + { + __IOM uint32_t REG_178CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_178CH_b; + }; + union + { + __IOM uint32_t REG_1790H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1790H_b; + }; + union + { + __IOM uint32_t REG_1794H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1794H_b; + }; + union + { + __IOM uint32_t REG_1798H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1798H_b; + }; + union + { + __IOM uint32_t REG_179CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_179CH_b; + }; + union + { + __IOM uint32_t REG_17A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17A0H_b; + }; + union + { + __IOM uint32_t REG_17A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17A4H_b; + }; + union + { + __IOM uint32_t REG_17A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17A8H_b; + }; + union + { + __IOM uint32_t REG_17ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17ACH_b; + }; + union + { + __IOM uint32_t REG_17B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17B0H_b; + }; + union + { + __IOM uint32_t REG_17B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17B4H_b; + }; + union + { + __IOM uint32_t REG_17B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17B8H_b; + }; + union + { + __IOM uint32_t REG_17BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17BCH_b; + }; + union + { + __IOM uint32_t REG_17C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17C0H_b; + }; + union + { + __IOM uint32_t REG_17C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17C4H_b; + }; + union + { + __IOM uint32_t REG_17C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17C8H_b; + }; + union + { + __IOM uint32_t REG_17CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17CCH_b; + }; + union + { + __IOM uint32_t REG_17D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17D0H_b; + }; + union + { + __IOM uint32_t REG_17D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17D4H_b; + }; + union + { + __IOM uint32_t REG_17D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17D8H_b; + }; + union + { + __IOM uint32_t REG_17DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17DCH_b; + }; + union + { + __IOM uint32_t REG_17E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17E0H_b; + }; + union + { + __IOM uint32_t REG_17E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17E4H_b; + }; + union + { + __IOM uint32_t REG_17E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17E8H_b; + }; + union + { + __IOM uint32_t REG_17ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17ECH_b; + }; + union + { + __IOM uint32_t REG_17F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17F0H_b; + }; + union + { + __IOM uint32_t REG_17F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17F4H_b; + }; + union + { + __IOM uint32_t REG_17F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17F8H_b; + }; + union + { + __IOM uint32_t REG_17FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_17FCH_b; + }; + union + { + __IOM uint32_t REG_1800H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1800H_b; + }; + union + { + __IOM uint32_t REG_1804H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1804H_b; + }; + union + { + __IOM uint32_t REG_1808H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1808H_b; + }; + union + { + __IOM uint32_t REG_180CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_180CH_b; + }; + union + { + __IOM uint32_t REG_1810H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1810H_b; + }; + union + { + __IOM uint32_t REG_1814H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1814H_b; + }; + union + { + __IOM uint32_t REG_1818H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1818H_b; + }; + union + { + __IOM uint32_t REG_181CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_181CH_b; + }; + union + { + __IOM uint32_t REG_1820H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1820H_b; + }; + union + { + __IOM uint32_t REG_1824H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1824H_b; + }; + union + { + __IOM uint32_t REG_1828H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1828H_b; + }; + union + { + __IOM uint32_t REG_182CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_182CH_b; + }; + union + { + __IOM uint32_t REG_1830H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1830H_b; + }; + union + { + __IOM uint32_t REG_1834H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1834H_b; + }; + union + { + __IOM uint32_t REG_1838H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1838H_b; + }; + union + { + __IOM uint32_t REG_183CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_183CH_b; + }; + union + { + __IOM uint32_t REG_1840H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1840H_b; + }; + union + { + __IOM uint32_t REG_1844H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1844H_b; + }; + union + { + __IOM uint32_t REG_1848H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1848H_b; + }; + union + { + __IOM uint32_t REG_184CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_184CH_b; + }; + union + { + __IOM uint32_t REG_1850H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1850H_b; + }; + union + { + __IOM uint32_t REG_1854H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1854H_b; + }; + union + { + __IOM uint32_t REG_1858H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1858H_b; + }; + union + { + __IOM uint32_t REG_185CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_185CH_b; + }; + union + { + __IOM uint32_t REG_1860H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1860H_b; + }; + union + { + __IOM uint32_t REG_1864H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1864H_b; + }; + union + { + __IOM uint32_t REG_1868H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1868H_b; + }; + union + { + __IOM uint32_t REG_186CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_186CH_b; + }; + union + { + __IOM uint32_t REG_1870H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1870H_b; + }; + union + { + __IOM uint32_t REG_1874H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1874H_b; + }; + union + { + __IOM uint32_t REG_1878H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1878H_b; + }; + union + { + __IOM uint32_t REG_187CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_187CH_b; + }; + union + { + __IOM uint32_t REG_1880H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1880H_b; + }; + union + { + __IOM uint32_t REG_1884H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1884H_b; + }; + union + { + __IOM uint32_t REG_1888H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1888H_b; + }; + union + { + __IOM uint32_t REG_188CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_188CH_b; + }; + union + { + __IOM uint32_t REG_1890H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1890H_b; + }; + union + { + __IOM uint32_t REG_1894H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1894H_b; + }; + union + { + __IOM uint32_t REG_1898H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1898H_b; + }; + union + { + __IOM uint32_t REG_189CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_189CH_b; + }; + union + { + __IOM uint32_t REG_18A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18A0H_b; + }; + union + { + __IOM uint32_t REG_18A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18A4H_b; + }; + union + { + __IOM uint32_t REG_18A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18A8H_b; + }; + union + { + __IOM uint32_t REG_18ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18ACH_b; + }; + union + { + __IOM uint32_t REG_18B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18B0H_b; + }; + union + { + __IOM uint32_t REG_18B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18B4H_b; + }; + union + { + __IOM uint32_t REG_18B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18B8H_b; + }; + union + { + __IOM uint32_t REG_18BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18BCH_b; + }; + union + { + __IOM uint32_t REG_18C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18C0H_b; + }; + union + { + __IOM uint32_t REG_18C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18C4H_b; + }; + union + { + __IOM uint32_t REG_18C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18C8H_b; + }; + union + { + __IOM uint32_t REG_18CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18CCH_b; + }; + union + { + __IOM uint32_t REG_18D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18D0H_b; + }; + union + { + __IOM uint32_t REG_18D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18D4H_b; + }; + union + { + __IOM uint32_t REG_18D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18D8H_b; + }; + union + { + __IOM uint32_t REG_18DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18DCH_b; + }; + union + { + __IOM uint32_t REG_18E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18E0H_b; + }; + union + { + __IOM uint32_t REG_18E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18E4H_b; + }; + union + { + __IOM uint32_t REG_18E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18E8H_b; + }; + union + { + __IOM uint32_t REG_18ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18ECH_b; + }; + union + { + __IOM uint32_t REG_18F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18F0H_b; + }; + union + { + __IOM uint32_t REG_18F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18F4H_b; + }; + union + { + __IOM uint32_t REG_18F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18F8H_b; + }; + union + { + __IOM uint32_t REG_18FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_18FCH_b; + }; + union + { + __IOM uint32_t REG_1900H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1900H_b; + }; + union + { + __IOM uint32_t REG_1904H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1904H_b; + }; + union + { + __IOM uint32_t REG_1908H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1908H_b; + }; + union + { + __IOM uint32_t REG_190CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_190CH_b; + }; + union + { + __IOM uint32_t REG_1910H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1910H_b; + }; + union + { + __IOM uint32_t REG_1914H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1914H_b; + }; + union + { + __IOM uint32_t REG_1918H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1918H_b; + }; + union + { + __IOM uint32_t REG_191CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_191CH_b; + }; + union + { + __IOM uint32_t REG_1920H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1920H_b; + }; + union + { + __IOM uint32_t REG_1924H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1924H_b; + }; + union + { + __IOM uint32_t REG_1928H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1928H_b; + }; + union + { + __IOM uint32_t REG_192CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_192CH_b; + }; + union + { + __IOM uint32_t REG_1930H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1930H_b; + }; + union + { + __IOM uint32_t REG_1934H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1934H_b; + }; + union + { + __IOM uint32_t REG_1938H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1938H_b; + }; + union + { + __IOM uint32_t REG_193CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_193CH_b; + }; + union + { + __IOM uint32_t REG_1940H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1940H_b; + }; + union + { + __IOM uint32_t REG_1944H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1944H_b; + }; + union + { + __IOM uint32_t REG_1948H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1948H_b; + }; + union + { + __IOM uint32_t REG_194CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_194CH_b; + }; + union + { + __IOM uint32_t REG_1950H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1950H_b; + }; + union + { + __IOM uint32_t REG_1954H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1954H_b; + }; + union + { + __IOM uint32_t REG_1958H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1958H_b; + }; + union + { + __IOM uint32_t REG_195CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_195CH_b; + }; + union + { + __IOM uint32_t REG_1960H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1960H_b; + }; + union + { + __IOM uint32_t REG_1964H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1964H_b; + }; + union + { + __IOM uint32_t REG_1968H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1968H_b; + }; + union + { + __IOM uint32_t REG_196CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_196CH_b; + }; + union + { + __IOM uint32_t REG_1970H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1970H_b; + }; + union + { + __IOM uint32_t REG_1974H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1974H_b; + }; + union + { + __IOM uint32_t REG_1978H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1978H_b; + }; + union + { + __IOM uint32_t REG_197CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_197CH_b; + }; + union + { + __IOM uint32_t REG_1980H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1980H_b; + }; + union + { + __IOM uint32_t REG_1984H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1984H_b; + }; + union + { + __IOM uint32_t REG_1988H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1988H_b; + }; + union + { + __IOM uint32_t REG_198CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_198CH_b; + }; + union + { + __IOM uint32_t REG_1990H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1990H_b; + }; + union + { + __IOM uint32_t REG_1994H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1994H_b; + }; + union + { + __IOM uint32_t REG_1998H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1998H_b; + }; + union + { + __IOM uint32_t REG_199CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_199CH_b; + }; + union + { + __IOM uint32_t REG_19A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19A0H_b; + }; + union + { + __IOM uint32_t REG_19A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19A4H_b; + }; + union + { + __IOM uint32_t REG_19A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19A8H_b; + }; + union + { + __IOM uint32_t REG_19ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19ACH_b; + }; + union + { + __IOM uint32_t REG_19B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19B0H_b; + }; + union + { + __IOM uint32_t REG_19B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19B4H_b; + }; + union + { + __IOM uint32_t REG_19B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19B8H_b; + }; + union + { + __IOM uint32_t REG_19BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19BCH_b; + }; + union + { + __IOM uint32_t REG_19C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19C0H_b; + }; + union + { + __IOM uint32_t REG_19C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19C4H_b; + }; + union + { + __IOM uint32_t REG_19C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19C8H_b; + }; + union + { + __IOM uint32_t REG_19CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19CCH_b; + }; + union + { + __IOM uint32_t REG_19D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19D0H_b; + }; + union + { + __IOM uint32_t REG_19D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19D4H_b; + }; + union + { + __IOM uint32_t REG_19D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19D8H_b; + }; + union + { + __IOM uint32_t REG_19DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19DCH_b; + }; + union + { + __IOM uint32_t REG_19E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19E0H_b; + }; + union + { + __IOM uint32_t REG_19E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19E4H_b; + }; + union + { + __IOM uint32_t REG_19E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19E8H_b; + }; + union + { + __IOM uint32_t REG_19ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19ECH_b; + }; + union + { + __IOM uint32_t REG_19F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19F0H_b; + }; + union + { + __IOM uint32_t REG_19F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19F4H_b; + }; + union + { + __IOM uint32_t REG_19F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19F8H_b; + }; + union + { + __IOM uint32_t REG_19FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_19FCH_b; + }; + union + { + __IOM uint32_t REG_1A00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A00H_b; + }; + union + { + __IOM uint32_t REG_1A04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A04H_b; + }; + union + { + __IOM uint32_t REG_1A08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A08H_b; + }; + union + { + __IOM uint32_t REG_1A0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A0CH_b; + }; + union + { + __IOM uint32_t REG_1A10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A10H_b; + }; + union + { + __IOM uint32_t REG_1A14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A14H_b; + }; + union + { + __IOM uint32_t REG_1A18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A18H_b; + }; + union + { + __IOM uint32_t REG_1A1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A1CH_b; + }; + union + { + __IOM uint32_t REG_1A20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A20H_b; + }; + union + { + __IOM uint32_t REG_1A24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A24H_b; + }; + union + { + __IOM uint32_t REG_1A28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A28H_b; + }; + union + { + __IOM uint32_t REG_1A2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A2CH_b; + }; + union + { + __IOM uint32_t REG_1A30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A30H_b; + }; + union + { + __IOM uint32_t REG_1A34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A34H_b; + }; + union + { + __IOM uint32_t REG_1A38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A38H_b; + }; + union + { + __IOM uint32_t REG_1A3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A3CH_b; + }; + union + { + __IOM uint32_t REG_1A40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A40H_b; + }; + union + { + __IOM uint32_t REG_1A44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A44H_b; + }; + union + { + __IOM uint32_t REG_1A48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A48H_b; + }; + union + { + __IOM uint32_t REG_1A4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A4CH_b; + }; + union + { + __IOM uint32_t REG_1A50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A50H_b; + }; + union + { + __IOM uint32_t REG_1A54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A54H_b; + }; + union + { + __IOM uint32_t REG_1A58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A58H_b; + }; + union + { + __IOM uint32_t REG_1A5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A5CH_b; + }; + union + { + __IOM uint32_t REG_1A60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A60H_b; + }; + union + { + __IOM uint32_t REG_1A64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A64H_b; + }; + union + { + __IOM uint32_t REG_1A68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A68H_b; + }; + union + { + __IOM uint32_t REG_1A6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A6CH_b; + }; + union + { + __IOM uint32_t REG_1A70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A70H_b; + }; + union + { + __IOM uint32_t REG_1A74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A74H_b; + }; + union + { + __IOM uint32_t REG_1A78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A78H_b; + }; + union + { + __IOM uint32_t REG_1A7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A7CH_b; + }; + union + { + __IOM uint32_t REG_1A80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A80H_b; + }; + union + { + __IOM uint32_t REG_1A84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A84H_b; + }; + union + { + __IOM uint32_t REG_1A88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A88H_b; + }; + union + { + __IOM uint32_t REG_1A8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A8CH_b; + }; + union + { + __IOM uint32_t REG_1A90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A90H_b; + }; + union + { + __IOM uint32_t REG_1A94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A94H_b; + }; + union + { + __IOM uint32_t REG_1A98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A98H_b; + }; + union + { + __IOM uint32_t REG_1A9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1A9CH_b; + }; + union + { + __IOM uint32_t REG_1AA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AA0H_b; + }; + union + { + __IOM uint32_t REG_1AA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AA4H_b; + }; + union + { + __IOM uint32_t REG_1AA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AA8H_b; + }; + union + { + __IOM uint32_t REG_1AACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AACH_b; + }; + union + { + __IOM uint32_t REG_1AB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AB0H_b; + }; + union + { + __IOM uint32_t REG_1AB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AB4H_b; + }; + union + { + __IOM uint32_t REG_1AB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AB8H_b; + }; + union + { + __IOM uint32_t REG_1ABCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ABCH_b; + }; + union + { + __IOM uint32_t REG_1AC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AC0H_b; + }; + union + { + __IOM uint32_t REG_1AC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AC4H_b; + }; + union + { + __IOM uint32_t REG_1AC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AC8H_b; + }; + union + { + __IOM uint32_t REG_1ACCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ACCH_b; + }; + union + { + __IOM uint32_t REG_1AD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AD0H_b; + }; + union + { + __IOM uint32_t REG_1AD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AD4H_b; + }; + union + { + __IOM uint32_t REG_1AD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AD8H_b; + }; + union + { + __IOM uint32_t REG_1ADCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ADCH_b; + }; + union + { + __IOM uint32_t REG_1AE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AE0H_b; + }; + union + { + __IOM uint32_t REG_1AE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AE4H_b; + }; + union + { + __IOM uint32_t REG_1AE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AE8H_b; + }; + union + { + __IOM uint32_t REG_1AECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AECH_b; + }; + union + { + __IOM uint32_t REG_1AF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AF0H_b; + }; + union + { + __IOM uint32_t REG_1AF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AF4H_b; + }; + union + { + __IOM uint32_t REG_1AF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AF8H_b; + }; + union + { + __IOM uint32_t REG_1AFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1AFCH_b; + }; + union + { + __IOM uint32_t REG_1B00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B00H_b; + }; + union + { + __IOM uint32_t REG_1B04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B04H_b; + }; + union + { + __IOM uint32_t REG_1B08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B08H_b; + }; + union + { + __IOM uint32_t REG_1B0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B0CH_b; + }; + union + { + __IOM uint32_t REG_1B10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B10H_b; + }; + union + { + __IOM uint32_t REG_1B14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B14H_b; + }; + union + { + __IOM uint32_t REG_1B18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B18H_b; + }; + union + { + __IOM uint32_t REG_1B1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B1CH_b; + }; + union + { + __IOM uint32_t REG_1B20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B20H_b; + }; + union + { + __IOM uint32_t REG_1B24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B24H_b; + }; + union + { + __IOM uint32_t REG_1B28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B28H_b; + }; + union + { + __IOM uint32_t REG_1B2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B2CH_b; + }; + union + { + __IOM uint32_t REG_1B30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B30H_b; + }; + union + { + __IOM uint32_t REG_1B34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B34H_b; + }; + union + { + __IOM uint32_t REG_1B38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B38H_b; + }; + union + { + __IOM uint32_t REG_1B3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B3CH_b; + }; + union + { + __IOM uint32_t REG_1B40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B40H_b; + }; + union + { + __IOM uint32_t REG_1B44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B44H_b; + }; + union + { + __IOM uint32_t REG_1B48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B48H_b; + }; + union + { + __IOM uint32_t REG_1B4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B4CH_b; + }; + union + { + __IOM uint32_t REG_1B50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B50H_b; + }; + union + { + __IOM uint32_t REG_1B54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B54H_b; + }; + union + { + __IOM uint32_t REG_1B58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B58H_b; + }; + union + { + __IOM uint32_t REG_1B5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B5CH_b; + }; + union + { + __IOM uint32_t REG_1B60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B60H_b; + }; + union + { + __IOM uint32_t REG_1B64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B64H_b; + }; + union + { + __IOM uint32_t REG_1B68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B68H_b; + }; + union + { + __IOM uint32_t REG_1B6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B6CH_b; + }; + union + { + __IOM uint32_t REG_1B70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B70H_b; + }; + union + { + __IOM uint32_t REG_1B74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B74H_b; + }; + union + { + __IOM uint32_t REG_1B78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B78H_b; + }; + union + { + __IOM uint32_t REG_1B7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B7CH_b; + }; + union + { + __IOM uint32_t REG_1B80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B80H_b; + }; + union + { + __IOM uint32_t REG_1B84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B84H_b; + }; + union + { + __IOM uint32_t REG_1B88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B88H_b; + }; + union + { + __IOM uint32_t REG_1B8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B8CH_b; + }; + union + { + __IOM uint32_t REG_1B90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B90H_b; + }; + union + { + __IOM uint32_t REG_1B94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B94H_b; + }; + union + { + __IOM uint32_t REG_1B98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B98H_b; + }; + union + { + __IOM uint32_t REG_1B9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1B9CH_b; + }; + union + { + __IOM uint32_t REG_1BA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BA0H_b; + }; + union + { + __IOM uint32_t REG_1BA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BA4H_b; + }; + union + { + __IOM uint32_t REG_1BA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BA8H_b; + }; + union + { + __IOM uint32_t REG_1BACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BACH_b; + }; + union + { + __IOM uint32_t REG_1BB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BB0H_b; + }; + union + { + __IOM uint32_t REG_1BB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BB4H_b; + }; + union + { + __IOM uint32_t REG_1BB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BB8H_b; + }; + union + { + __IOM uint32_t REG_1BBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BBCH_b; + }; + union + { + __IOM uint32_t REG_1BC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BC0H_b; + }; + union + { + __IOM uint32_t REG_1BC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BC4H_b; + }; + union + { + __IOM uint32_t REG_1BC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BC8H_b; + }; + union + { + __IOM uint32_t REG_1BCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BCCH_b; + }; + union + { + __IOM uint32_t REG_1BD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BD0H_b; + }; + union + { + __IOM uint32_t REG_1BD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BD4H_b; + }; + union + { + __IOM uint32_t REG_1BD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BD8H_b; + }; + union + { + __IOM uint32_t REG_1BDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BDCH_b; + }; + union + { + __IOM uint32_t REG_1BE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BE0H_b; + }; + union + { + __IOM uint32_t REG_1BE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BE4H_b; + }; + union + { + __IOM uint32_t REG_1BE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BE8H_b; + }; + union + { + __IOM uint32_t REG_1BECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BECH_b; + }; + union + { + __IOM uint32_t REG_1BF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BF0H_b; + }; + union + { + __IOM uint32_t REG_1BF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BF4H_b; + }; + union + { + __IOM uint32_t REG_1BF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BF8H_b; + }; + union + { + __IOM uint32_t REG_1BFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1BFCH_b; + }; + union + { + __IOM uint32_t REG_1C00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C00H_b; + }; + union + { + __IOM uint32_t REG_1C04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C04H_b; + }; + union + { + __IOM uint32_t REG_1C08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C08H_b; + }; + union + { + __IOM uint32_t REG_1C0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C0CH_b; + }; + union + { + __IOM uint32_t REG_1C10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C10H_b; + }; + union + { + __IOM uint32_t REG_1C14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C14H_b; + }; + union + { + __IOM uint32_t REG_1C18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C18H_b; + }; + union + { + __IOM uint32_t REG_1C1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C1CH_b; + }; + union + { + __IOM uint32_t REG_1C20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C20H_b; + }; + union + { + __IOM uint32_t REG_1C24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C24H_b; + }; + union + { + __IOM uint32_t REG_1C28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C28H_b; + }; + union + { + __IOM uint32_t REG_1C2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C2CH_b; + }; + union + { + __IOM uint32_t REG_1C30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C30H_b; + }; + union + { + __IOM uint32_t REG_1C34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C34H_b; + }; + union + { + __IOM uint32_t REG_1C38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C38H_b; + }; + union + { + __IOM uint32_t REG_1C3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C3CH_b; + }; + union + { + __IOM uint32_t REG_1C40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C40H_b; + }; + union + { + __IOM uint32_t REG_1C44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C44H_b; + }; + union + { + __IOM uint32_t REG_1C48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C48H_b; + }; + union + { + __IOM uint32_t REG_1C4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C4CH_b; + }; + union + { + __IOM uint32_t REG_1C50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C50H_b; + }; + union + { + __IOM uint32_t REG_1C54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C54H_b; + }; + union + { + __IOM uint32_t REG_1C58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C58H_b; + }; + union + { + __IOM uint32_t REG_1C5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C5CH_b; + }; + union + { + __IOM uint32_t REG_1C60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C60H_b; + }; + union + { + __IOM uint32_t REG_1C64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C64H_b; + }; + union + { + __IOM uint32_t REG_1C68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C68H_b; + }; + union + { + __IOM uint32_t REG_1C6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C6CH_b; + }; + union + { + __IOM uint32_t REG_1C70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C70H_b; + }; + union + { + __IOM uint32_t REG_1C74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C74H_b; + }; + union + { + __IOM uint32_t REG_1C78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C78H_b; + }; + union + { + __IOM uint32_t REG_1C7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C7CH_b; + }; + union + { + __IOM uint32_t REG_1C80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C80H_b; + }; + union + { + __IOM uint32_t REG_1C84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C84H_b; + }; + union + { + __IOM uint32_t REG_1C88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C88H_b; + }; + union + { + __IOM uint32_t REG_1C8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C8CH_b; + }; + union + { + __IOM uint32_t REG_1C90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C90H_b; + }; + union + { + __IOM uint32_t REG_1C94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C94H_b; + }; + union + { + __IOM uint32_t REG_1C98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C98H_b; + }; + union + { + __IOM uint32_t REG_1C9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1C9CH_b; + }; + union + { + __IOM uint32_t REG_1CA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CA0H_b; + }; + union + { + __IOM uint32_t REG_1CA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CA4H_b; + }; + union + { + __IOM uint32_t REG_1CA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CA8H_b; + }; + union + { + __IOM uint32_t REG_1CACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CACH_b; + }; + union + { + __IOM uint32_t REG_1CB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CB0H_b; + }; + union + { + __IOM uint32_t REG_1CB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CB4H_b; + }; + union + { + __IOM uint32_t REG_1CB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CB8H_b; + }; + union + { + __IOM uint32_t REG_1CBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CBCH_b; + }; + union + { + __IOM uint32_t REG_1CC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CC0H_b; + }; + union + { + __IOM uint32_t REG_1CC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CC4H_b; + }; + union + { + __IOM uint32_t REG_1CC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CC8H_b; + }; + union + { + __IOM uint32_t REG_1CCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CCCH_b; + }; + union + { + __IOM uint32_t REG_1CD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CD0H_b; + }; + union + { + __IOM uint32_t REG_1CD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CD4H_b; + }; + union + { + __IOM uint32_t REG_1CD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CD8H_b; + }; + union + { + __IOM uint32_t REG_1CDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CDCH_b; + }; + union + { + __IOM uint32_t REG_1CE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CE0H_b; + }; + union + { + __IOM uint32_t REG_1CE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CE4H_b; + }; + union + { + __IOM uint32_t REG_1CE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CE8H_b; + }; + union + { + __IOM uint32_t REG_1CECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CECH_b; + }; + union + { + __IOM uint32_t REG_1CF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CF0H_b; + }; + union + { + __IOM uint32_t REG_1CF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CF4H_b; + }; + union + { + __IOM uint32_t REG_1CF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CF8H_b; + }; + union + { + __IOM uint32_t REG_1CFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1CFCH_b; + }; + union + { + __IOM uint32_t REG_1D00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D00H_b; + }; + union + { + __IOM uint32_t REG_1D04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D04H_b; + }; + union + { + __IOM uint32_t REG_1D08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D08H_b; + }; + union + { + __IOM uint32_t REG_1D0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D0CH_b; + }; + union + { + __IOM uint32_t REG_1D10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D10H_b; + }; + union + { + __IOM uint32_t REG_1D14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D14H_b; + }; + union + { + __IOM uint32_t REG_1D18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D18H_b; + }; + union + { + __IOM uint32_t REG_1D1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D1CH_b; + }; + union + { + __IOM uint32_t REG_1D20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D20H_b; + }; + union + { + __IOM uint32_t REG_1D24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D24H_b; + }; + union + { + __IOM uint32_t REG_1D28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D28H_b; + }; + union + { + __IOM uint32_t REG_1D2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D2CH_b; + }; + union + { + __IOM uint32_t REG_1D30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D30H_b; + }; + union + { + __IOM uint32_t REG_1D34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D34H_b; + }; + union + { + __IOM uint32_t REG_1D38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D38H_b; + }; + union + { + __IOM uint32_t REG_1D3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D3CH_b; + }; + union + { + __IOM uint32_t REG_1D40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D40H_b; + }; + union + { + __IOM uint32_t REG_1D44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D44H_b; + }; + union + { + __IOM uint32_t REG_1D48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D48H_b; + }; + union + { + __IOM uint32_t REG_1D4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D4CH_b; + }; + union + { + __IOM uint32_t REG_1D50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D50H_b; + }; + union + { + __IOM uint32_t REG_1D54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D54H_b; + }; + union + { + __IOM uint32_t REG_1D58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D58H_b; + }; + union + { + __IOM uint32_t REG_1D5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D5CH_b; + }; + union + { + __IOM uint32_t REG_1D60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D60H_b; + }; + union + { + __IOM uint32_t REG_1D64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D64H_b; + }; + union + { + __IOM uint32_t REG_1D68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D68H_b; + }; + union + { + __IOM uint32_t REG_1D6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D6CH_b; + }; + union + { + __IOM uint32_t REG_1D70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D70H_b; + }; + union + { + __IOM uint32_t REG_1D74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D74H_b; + }; + union + { + __IOM uint32_t REG_1D78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D78H_b; + }; + union + { + __IOM uint32_t REG_1D7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D7CH_b; + }; + union + { + __IOM uint32_t REG_1D80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D80H_b; + }; + union + { + __IOM uint32_t REG_1D84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D84H_b; + }; + union + { + __IOM uint32_t REG_1D88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D88H_b; + }; + union + { + __IOM uint32_t REG_1D8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D8CH_b; + }; + union + { + __IOM uint32_t REG_1D90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D90H_b; + }; + union + { + __IOM uint32_t REG_1D94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D94H_b; + }; + union + { + __IOM uint32_t REG_1D98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D98H_b; + }; + union + { + __IOM uint32_t REG_1D9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1D9CH_b; + }; + union + { + __IOM uint32_t REG_1DA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DA0H_b; + }; + union + { + __IOM uint32_t REG_1DA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DA4H_b; + }; + union + { + __IOM uint32_t REG_1DA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DA8H_b; + }; + union + { + __IOM uint32_t REG_1DACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DACH_b; + }; + union + { + __IOM uint32_t REG_1DB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DB0H_b; + }; + union + { + __IOM uint32_t REG_1DB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DB4H_b; + }; + union + { + __IOM uint32_t REG_1DB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DB8H_b; + }; + union + { + __IOM uint32_t REG_1DBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DBCH_b; + }; + union + { + __IOM uint32_t REG_1DC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DC0H_b; + }; + union + { + __IOM uint32_t REG_1DC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DC4H_b; + }; + union + { + __IOM uint32_t REG_1DC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DC8H_b; + }; + union + { + __IOM uint32_t REG_1DCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DCCH_b; + }; + union + { + __IOM uint32_t REG_1DD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DD0H_b; + }; + union + { + __IOM uint32_t REG_1DD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DD4H_b; + }; + union + { + __IOM uint32_t REG_1DD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DD8H_b; + }; + union + { + __IOM uint32_t REG_1DDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DDCH_b; + }; + union + { + __IOM uint32_t REG_1DE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DE0H_b; + }; + union + { + __IOM uint32_t REG_1DE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DE4H_b; + }; + union + { + __IOM uint32_t REG_1DE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DE8H_b; + }; + union + { + __IOM uint32_t REG_1DECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DECH_b; + }; + union + { + __IOM uint32_t REG_1DF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DF0H_b; + }; + union + { + __IOM uint32_t REG_1DF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DF4H_b; + }; + union + { + __IOM uint32_t REG_1DF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DF8H_b; + }; + union + { + __IOM uint32_t REG_1DFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1DFCH_b; + }; + union + { + __IOM uint32_t REG_1E00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E00H_b; + }; + union + { + __IOM uint32_t REG_1E04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E04H_b; + }; + union + { + __IOM uint32_t REG_1E08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E08H_b; + }; + union + { + __IOM uint32_t REG_1E0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E0CH_b; + }; + union + { + __IOM uint32_t REG_1E10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E10H_b; + }; + union + { + __IOM uint32_t REG_1E14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E14H_b; + }; + union + { + __IOM uint32_t REG_1E18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E18H_b; + }; + union + { + __IOM uint32_t REG_1E1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E1CH_b; + }; + union + { + __IOM uint32_t REG_1E20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E20H_b; + }; + union + { + __IOM uint32_t REG_1E24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E24H_b; + }; + union + { + __IOM uint32_t REG_1E28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E28H_b; + }; + union + { + __IOM uint32_t REG_1E2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E2CH_b; + }; + union + { + __IOM uint32_t REG_1E30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E30H_b; + }; + union + { + __IOM uint32_t REG_1E34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E34H_b; + }; + union + { + __IOM uint32_t REG_1E38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E38H_b; + }; + union + { + __IOM uint32_t REG_1E3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E3CH_b; + }; + union + { + __IOM uint32_t REG_1E40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E40H_b; + }; + union + { + __IOM uint32_t REG_1E44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E44H_b; + }; + union + { + __IOM uint32_t REG_1E48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E48H_b; + }; + union + { + __IOM uint32_t REG_1E4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E4CH_b; + }; + union + { + __IOM uint32_t REG_1E50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E50H_b; + }; + union + { + __IOM uint32_t REG_1E54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E54H_b; + }; + union + { + __IOM uint32_t REG_1E58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E58H_b; + }; + union + { + __IOM uint32_t REG_1E5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E5CH_b; + }; + union + { + __IOM uint32_t REG_1E60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E60H_b; + }; + union + { + __IOM uint32_t REG_1E64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E64H_b; + }; + union + { + __IOM uint32_t REG_1E68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E68H_b; + }; + union + { + __IOM uint32_t REG_1E6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E6CH_b; + }; + union + { + __IOM uint32_t REG_1E70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E70H_b; + }; + union + { + __IOM uint32_t REG_1E74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E74H_b; + }; + union + { + __IOM uint32_t REG_1E78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E78H_b; + }; + union + { + __IOM uint32_t REG_1E7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E7CH_b; + }; + union + { + __IOM uint32_t REG_1E80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E80H_b; + }; + union + { + __IOM uint32_t REG_1E84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E84H_b; + }; + union + { + __IOM uint32_t REG_1E88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E88H_b; + }; + union + { + __IOM uint32_t REG_1E8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E8CH_b; + }; + union + { + __IOM uint32_t REG_1E90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E90H_b; + }; + union + { + __IOM uint32_t REG_1E94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E94H_b; + }; + union + { + __IOM uint32_t REG_1E98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E98H_b; + }; + union + { + __IOM uint32_t REG_1E9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1E9CH_b; + }; + union + { + __IOM uint32_t REG_1EA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EA0H_b; + }; + union + { + __IOM uint32_t REG_1EA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EA4H_b; + }; + union + { + __IOM uint32_t REG_1EA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EA8H_b; + }; + union + { + __IOM uint32_t REG_1EACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EACH_b; + }; + union + { + __IOM uint32_t REG_1EB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EB0H_b; + }; + union + { + __IOM uint32_t REG_1EB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EB4H_b; + }; + union + { + __IOM uint32_t REG_1EB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EB8H_b; + }; + union + { + __IOM uint32_t REG_1EBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EBCH_b; + }; + union + { + __IOM uint32_t REG_1EC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EC0H_b; + }; + union + { + __IOM uint32_t REG_1EC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EC4H_b; + }; + union + { + __IOM uint32_t REG_1EC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EC8H_b; + }; + union + { + __IOM uint32_t REG_1ECCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ECCH_b; + }; + union + { + __IOM uint32_t REG_1ED0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ED0H_b; + }; + union + { + __IOM uint32_t REG_1ED4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ED4H_b; + }; + union + { + __IOM uint32_t REG_1ED8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1ED8H_b; + }; + union + { + __IOM uint32_t REG_1EDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EDCH_b; + }; + union + { + __IOM uint32_t REG_1EE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EE0H_b; + }; + union + { + __IOM uint32_t REG_1EE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EE4H_b; + }; + union + { + __IOM uint32_t REG_1EE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EE8H_b; + }; + union + { + __IOM uint32_t REG_1EECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EECH_b; + }; + union + { + __IOM uint32_t REG_1EF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EF0H_b; + }; + union + { + __IOM uint32_t REG_1EF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EF4H_b; + }; + union + { + __IOM uint32_t REG_1EF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EF8H_b; + }; + union + { + __IOM uint32_t REG_1EFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1EFCH_b; + }; + union + { + __IOM uint32_t REG_1F00H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F00H_b; + }; + union + { + __IOM uint32_t REG_1F04H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F04H_b; + }; + union + { + __IOM uint32_t REG_1F08H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F08H_b; + }; + union + { + __IOM uint32_t REG_1F0CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F0CH_b; + }; + union + { + __IOM uint32_t REG_1F10H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F10H_b; + }; + union + { + __IOM uint32_t REG_1F14H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F14H_b; + }; + union + { + __IOM uint32_t REG_1F18H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F18H_b; + }; + union + { + __IOM uint32_t REG_1F1CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F1CH_b; + }; + union + { + __IOM uint32_t REG_1F20H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F20H_b; + }; + union + { + __IOM uint32_t REG_1F24H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F24H_b; + }; + union + { + __IOM uint32_t REG_1F28H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F28H_b; + }; + union + { + __IOM uint32_t REG_1F2CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F2CH_b; + }; + union + { + __IOM uint32_t REG_1F30H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F30H_b; + }; + union + { + __IOM uint32_t REG_1F34H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F34H_b; + }; + union + { + __IOM uint32_t REG_1F38H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F38H_b; + }; + union + { + __IOM uint32_t REG_1F3CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F3CH_b; + }; + union + { + __IOM uint32_t REG_1F40H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F40H_b; + }; + union + { + __IOM uint32_t REG_1F44H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F44H_b; + }; + union + { + __IOM uint32_t REG_1F48H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F48H_b; + }; + union + { + __IOM uint32_t REG_1F4CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F4CH_b; + }; + union + { + __IOM uint32_t REG_1F50H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F50H_b; + }; + union + { + __IOM uint32_t REG_1F54H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F54H_b; + }; + union + { + __IOM uint32_t REG_1F58H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F58H_b; + }; + union + { + __IOM uint32_t REG_1F5CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F5CH_b; + }; + union + { + __IOM uint32_t REG_1F60H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F60H_b; + }; + union + { + __IOM uint32_t REG_1F64H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F64H_b; + }; + union + { + __IOM uint32_t REG_1F68H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F68H_b; + }; + union + { + __IOM uint32_t REG_1F6CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F6CH_b; + }; + union + { + __IOM uint32_t REG_1F70H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F70H_b; + }; + union + { + __IOM uint32_t REG_1F74H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F74H_b; + }; + union + { + __IOM uint32_t REG_1F78H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F78H_b; + }; + union + { + __IOM uint32_t REG_1F7CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F7CH_b; + }; + union + { + __IOM uint32_t REG_1F80H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F80H_b; + }; + union + { + __IOM uint32_t REG_1F84H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F84H_b; + }; + union + { + __IOM uint32_t REG_1F88H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F88H_b; + }; + union + { + __IOM uint32_t REG_1F8CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F8CH_b; + }; + union + { + __IOM uint32_t REG_1F90H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F90H_b; + }; + union + { + __IOM uint32_t REG_1F94H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F94H_b; + }; + union + { + __IOM uint32_t REG_1F98H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F98H_b; + }; + union + { + __IOM uint32_t REG_1F9CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1F9CH_b; + }; + union + { + __IOM uint32_t REG_1FA0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FA0H_b; + }; + union + { + __IOM uint32_t REG_1FA4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FA4H_b; + }; + union + { + __IOM uint32_t REG_1FA8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FA8H_b; + }; + union + { + __IOM uint32_t REG_1FACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FACH_b; + }; + union + { + __IOM uint32_t REG_1FB0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FB0H_b; + }; + union + { + __IOM uint32_t REG_1FB4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FB4H_b; + }; + union + { + __IOM uint32_t REG_1FB8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FB8H_b; + }; + union + { + __IOM uint32_t REG_1FBCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FBCH_b; + }; + union + { + __IOM uint32_t REG_1FC0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FC0H_b; + }; + union + { + __IOM uint32_t REG_1FC4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FC4H_b; + }; + union + { + __IOM uint32_t REG_1FC8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FC8H_b; + }; + union + { + __IOM uint32_t REG_1FCCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FCCH_b; + }; + union + { + __IOM uint32_t REG_1FD0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FD0H_b; + }; + union + { + __IOM uint32_t REG_1FD4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FD4H_b; + }; + union + { + __IOM uint32_t REG_1FD8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FD8H_b; + }; + union + { + __IOM uint32_t REG_1FDCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FDCH_b; + }; + union + { + __IOM uint32_t REG_1FE0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FE0H_b; + }; + union + { + __IOM uint32_t REG_1FE4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FE4H_b; + }; + union + { + __IOM uint32_t REG_1FE8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FE8H_b; + }; + union + { + __IOM uint32_t REG_1FECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FECH_b; + }; + union + { + __IOM uint32_t REG_1FF0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FF0H_b; + }; + union + { + __IOM uint32_t REG_1FF4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FF4H_b; + }; + union + { + __IOM uint32_t REG_1FF8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FF8H_b; + }; + union + { + __IOM uint32_t REG_1FFCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_1FFCH_b; + }; + union + { + __IOM uint32_t REG_2000H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2000H_b; + }; + union + { + __IOM uint32_t REG_2004H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2004H_b; + }; + union + { + __IOM uint32_t REG_2008H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2008H_b; + }; + union + { + __IOM uint32_t REG_200CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_200CH_b; + }; + union + { + __IOM uint32_t REG_2010H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2010H_b; + }; + union + { + __IOM uint32_t REG_2014H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2014H_b; + }; + union + { + __IOM uint32_t REG_2018H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2018H_b; + }; + union + { + __IOM uint32_t REG_201CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_201CH_b; + }; + union + { + __IOM uint32_t REG_2020H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2020H_b; + }; + union + { + __IOM uint32_t REG_2024H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2024H_b; + }; + union + { + __IOM uint32_t REG_2028H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2028H_b; + }; + union + { + __IOM uint32_t REG_202CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_202CH_b; + }; + union + { + __IOM uint32_t REG_2030H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2030H_b; + }; + union + { + __IOM uint32_t REG_2034H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2034H_b; + }; + union + { + __IOM uint32_t REG_2038H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2038H_b; + }; + union + { + __IOM uint32_t REG_203CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_203CH_b; + }; + union + { + __IOM uint32_t REG_2040H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2040H_b; + }; + union + { + __IOM uint32_t REG_2044H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2044H_b; + }; + union + { + __IOM uint32_t REG_2048H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2048H_b; + }; + union + { + __IOM uint32_t REG_204CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_204CH_b; + }; + union + { + __IOM uint32_t REG_2050H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2050H_b; + }; + union + { + __IOM uint32_t REG_2054H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2054H_b; + }; + union + { + __IOM uint32_t REG_2058H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2058H_b; + }; + union + { + __IOM uint32_t REG_205CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_205CH_b; + }; + union + { + __IOM uint32_t REG_2060H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2060H_b; + }; + union + { + __IOM uint32_t REG_2064H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2064H_b; + }; + union + { + __IOM uint32_t REG_2068H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2068H_b; + }; + union + { + __IOM uint32_t REG_206CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_206CH_b; + }; + union + { + __IOM uint32_t REG_2070H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2070H_b; + }; + union + { + __IOM uint32_t REG_2074H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2074H_b; + }; + union + { + __IOM uint32_t REG_2078H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2078H_b; + }; + union + { + __IOM uint32_t REG_207CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_207CH_b; + }; + union + { + __IOM uint32_t REG_2080H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2080H_b; + }; + union + { + __IOM uint32_t REG_2084H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2084H_b; + }; + union + { + __IOM uint32_t REG_2088H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2088H_b; + }; + union + { + __IOM uint32_t REG_208CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_208CH_b; + }; + union + { + __IOM uint32_t REG_2090H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2090H_b; + }; + union + { + __IOM uint32_t REG_2094H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2094H_b; + }; + union + { + __IOM uint32_t REG_2098H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2098H_b; + }; + union + { + __IOM uint32_t REG_209CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_209CH_b; + }; + union + { + __IOM uint32_t REG_20A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20A0H_b; + }; + union + { + __IOM uint32_t REG_20A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20A4H_b; + }; + union + { + __IOM uint32_t REG_20A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20A8H_b; + }; + union + { + __IOM uint32_t REG_20ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20ACH_b; + }; + union + { + __IOM uint32_t REG_20B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20B0H_b; + }; + union + { + __IOM uint32_t REG_20B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20B4H_b; + }; + union + { + __IOM uint32_t REG_20B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20B8H_b; + }; + union + { + __IOM uint32_t REG_20BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20BCH_b; + }; + union + { + __IOM uint32_t REG_20C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20C0H_b; + }; + union + { + __IOM uint32_t REG_20C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20C4H_b; + }; + union + { + __IOM uint32_t REG_20C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20C8H_b; + }; + union + { + __IOM uint32_t REG_20CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20CCH_b; + }; + union + { + __IOM uint32_t REG_20D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20D0H_b; + }; + union + { + __IOM uint32_t REG_20D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20D4H_b; + }; + union + { + __IOM uint32_t REG_20D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20D8H_b; + }; + union + { + __IOM uint32_t REG_20DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20DCH_b; + }; + union + { + __IOM uint32_t REG_20E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20E0H_b; + }; + union + { + __IOM uint32_t REG_20E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20E4H_b; + }; + union + { + __IOM uint32_t REG_20E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20E8H_b; + }; + union + { + __IOM uint32_t REG_20ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20ECH_b; + }; + union + { + __IOM uint32_t REG_20F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20F0H_b; + }; + union + { + __IOM uint32_t REG_20F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20F4H_b; + }; + union + { + __IOM uint32_t REG_20F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20F8H_b; + }; + union + { + __IOM uint32_t REG_20FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_20FCH_b; + }; + union + { + __IOM uint32_t REG_2100H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2100H_b; + }; + union + { + __IOM uint32_t REG_2104H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2104H_b; + }; + union + { + __IOM uint32_t REG_2108H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2108H_b; + }; + union + { + __IOM uint32_t REG_210CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_210CH_b; + }; + union + { + __IOM uint32_t REG_2110H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2110H_b; + }; + union + { + __IOM uint32_t REG_2114H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2114H_b; + }; + union + { + __IOM uint32_t REG_2118H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2118H_b; + }; + union + { + __IOM uint32_t REG_211CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_211CH_b; + }; + union + { + __IOM uint32_t REG_2120H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2120H_b; + }; + union + { + __IOM uint32_t REG_2124H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2124H_b; + }; + union + { + __IOM uint32_t REG_2128H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2128H_b; + }; + union + { + __IOM uint32_t REG_212CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_212CH_b; + }; + union + { + __IOM uint32_t REG_2130H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2130H_b; + }; + union + { + __IOM uint32_t REG_2134H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2134H_b; + }; + union + { + __IOM uint32_t REG_2138H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2138H_b; + }; + union + { + __IOM uint32_t REG_213CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_213CH_b; + }; + union + { + __IOM uint32_t REG_2140H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2140H_b; + }; + union + { + __IOM uint32_t REG_2144H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2144H_b; + }; + union + { + __IOM uint32_t REG_2148H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2148H_b; + }; + union + { + __IOM uint32_t REG_214CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_214CH_b; + }; + union + { + __IOM uint32_t REG_2150H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2150H_b; + }; + union + { + __IOM uint32_t REG_2154H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2154H_b; + }; + union + { + __IOM uint32_t REG_2158H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2158H_b; + }; + union + { + __IOM uint32_t REG_215CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_215CH_b; + }; + union + { + __IOM uint32_t REG_2160H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2160H_b; + }; + union + { + __IOM uint32_t REG_2164H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2164H_b; + }; + union + { + __IOM uint32_t REG_2168H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2168H_b; + }; + union + { + __IOM uint32_t REG_216CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_216CH_b; + }; + union + { + __IOM uint32_t REG_2170H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2170H_b; + }; + union + { + __IOM uint32_t REG_2174H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2174H_b; + }; + union + { + __IOM uint32_t REG_2178H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2178H_b; + }; + union + { + __IOM uint32_t REG_217CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_217CH_b; + }; + union + { + __IOM uint32_t REG_2180H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2180H_b; + }; + union + { + __IOM uint32_t REG_2184H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2184H_b; + }; + union + { + __IOM uint32_t REG_2188H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2188H_b; + }; + union + { + __IOM uint32_t REG_218CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_218CH_b; + }; + union + { + __IOM uint32_t REG_2190H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2190H_b; + }; + union + { + __IOM uint32_t REG_2194H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2194H_b; + }; + union + { + __IOM uint32_t REG_2198H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2198H_b; + }; + union + { + __IOM uint32_t REG_219CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_219CH_b; + }; + union + { + __IOM uint32_t REG_21A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21A0H_b; + }; + union + { + __IOM uint32_t REG_21A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21A4H_b; + }; + union + { + __IOM uint32_t REG_21A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21A8H_b; + }; + union + { + __IOM uint32_t REG_21ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21ACH_b; + }; + union + { + __IOM uint32_t REG_21B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21B0H_b; + }; + union + { + __IOM uint32_t REG_21B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21B4H_b; + }; + union + { + __IOM uint32_t REG_21B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21B8H_b; + }; + union + { + __IOM uint32_t REG_21BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21BCH_b; + }; + union + { + __IOM uint32_t REG_21C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21C0H_b; + }; + union + { + __IOM uint32_t REG_21C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21C4H_b; + }; + union + { + __IOM uint32_t REG_21C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21C8H_b; + }; + union + { + __IOM uint32_t REG_21CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21CCH_b; + }; + union + { + __IOM uint32_t REG_21D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21D0H_b; + }; + union + { + __IOM uint32_t REG_21D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21D4H_b; + }; + union + { + __IOM uint32_t REG_21D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21D8H_b; + }; + union + { + __IOM uint32_t REG_21DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21DCH_b; + }; + union + { + __IOM uint32_t REG_21E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21E0H_b; + }; + union + { + __IOM uint32_t REG_21E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21E4H_b; + }; + union + { + __IOM uint32_t REG_21E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21E8H_b; + }; + union + { + __IOM uint32_t REG_21ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21ECH_b; + }; + union + { + __IOM uint32_t REG_21F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21F0H_b; + }; + union + { + __IOM uint32_t REG_21F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21F4H_b; + }; + union + { + __IOM uint32_t REG_21F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21F8H_b; + }; + union + { + __IOM uint32_t REG_21FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_21FCH_b; + }; + union + { + __IOM uint32_t REG_2200H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2200H_b; + }; + union + { + __IOM uint32_t REG_2204H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2204H_b; + }; + union + { + __IOM uint32_t REG_2208H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2208H_b; + }; + union + { + __IOM uint32_t REG_220CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_220CH_b; + }; + union + { + __IOM uint32_t REG_2210H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2210H_b; + }; + union + { + __IOM uint32_t REG_2214H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2214H_b; + }; + union + { + __IOM uint32_t REG_2218H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2218H_b; + }; + union + { + __IOM uint32_t REG_221CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_221CH_b; + }; + union + { + __IOM uint32_t REG_2220H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2220H_b; + }; + union + { + __IOM uint32_t REG_2224H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2224H_b; + }; + union + { + __IOM uint32_t REG_2228H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2228H_b; + }; + union + { + __IOM uint32_t REG_222CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_222CH_b; + }; + union + { + __IOM uint32_t REG_2230H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2230H_b; + }; + union + { + __IOM uint32_t REG_2234H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2234H_b; + }; + union + { + __IOM uint32_t REG_2238H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2238H_b; + }; + union + { + __IOM uint32_t REG_223CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_223CH_b; + }; + union + { + __IOM uint32_t REG_2240H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2240H_b; + }; + union + { + __IOM uint32_t REG_2244H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2244H_b; + }; + union + { + __IOM uint32_t REG_2248H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2248H_b; + }; + union + { + __IOM uint32_t REG_224CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_224CH_b; + }; + union + { + __IOM uint32_t REG_2250H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2250H_b; + }; + union + { + __IOM uint32_t REG_2254H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2254H_b; + }; + union + { + __IOM uint32_t REG_2258H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2258H_b; + }; + union + { + __IOM uint32_t REG_225CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_225CH_b; + }; + union + { + __IOM uint32_t REG_2260H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2260H_b; + }; + union + { + __IOM uint32_t REG_2264H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2264H_b; + }; + union + { + __IOM uint32_t REG_2268H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2268H_b; + }; + union + { + __IOM uint32_t REG_226CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_226CH_b; + }; + union + { + __IOM uint32_t REG_2270H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2270H_b; + }; + union + { + __IOM uint32_t REG_2274H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2274H_b; + }; + union + { + __IOM uint32_t REG_2278H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2278H_b; + }; + union + { + __IOM uint32_t REG_227CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_227CH_b; + }; + union + { + __IOM uint32_t REG_2280H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2280H_b; + }; + union + { + __IOM uint32_t REG_2284H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2284H_b; + }; + union + { + __IOM uint32_t REG_2288H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2288H_b; + }; + union + { + __IOM uint32_t REG_228CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_228CH_b; + }; + union + { + __IOM uint32_t REG_2290H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2290H_b; + }; + union + { + __IOM uint32_t REG_2294H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2294H_b; + }; + union + { + __IOM uint32_t REG_2298H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2298H_b; + }; + union + { + __IOM uint32_t REG_229CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_229CH_b; + }; + union + { + __IOM uint32_t REG_22A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22A0H_b; + }; + union + { + __IOM uint32_t REG_22A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22A4H_b; + }; + union + { + __IOM uint32_t REG_22A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22A8H_b; + }; + union + { + __IOM uint32_t REG_22ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22ACH_b; + }; + union + { + __IOM uint32_t REG_22B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22B0H_b; + }; + union + { + __IOM uint32_t REG_22B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22B4H_b; + }; + union + { + __IOM uint32_t REG_22B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22B8H_b; + }; + union + { + __IOM uint32_t REG_22BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22BCH_b; + }; + union + { + __IOM uint32_t REG_22C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22C0H_b; + }; + union + { + __IOM uint32_t REG_22C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22C4H_b; + }; + union + { + __IOM uint32_t REG_22C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22C8H_b; + }; + union + { + __IOM uint32_t REG_22CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22CCH_b; + }; + union + { + __IOM uint32_t REG_22D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22D0H_b; + }; + union + { + __IOM uint32_t REG_22D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22D4H_b; + }; + union + { + __IOM uint32_t REG_22D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22D8H_b; + }; + union + { + __IOM uint32_t REG_22DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22DCH_b; + }; + union + { + __IOM uint32_t REG_22E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22E0H_b; + }; + union + { + __IOM uint32_t REG_22E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22E4H_b; + }; + union + { + __IOM uint32_t REG_22E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22E8H_b; + }; + union + { + __IOM uint32_t REG_22ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22ECH_b; + }; + union + { + __IOM uint32_t REG_22F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22F0H_b; + }; + union + { + __IOM uint32_t REG_22F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22F4H_b; + }; + union + { + __IOM uint32_t REG_22F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22F8H_b; + }; + union + { + __IOM uint32_t REG_22FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_22FCH_b; + }; + union + { + __IOM uint32_t REG_2300H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2300H_b; + }; + union + { + __IOM uint32_t REG_2304H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2304H_b; + }; + union + { + __IOM uint32_t REG_2308H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2308H_b; + }; + union + { + __IOM uint32_t REG_230CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_230CH_b; + }; + union + { + __IOM uint32_t REG_2310H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2310H_b; + }; + union + { + __IOM uint32_t REG_2314H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2314H_b; + }; + union + { + __IOM uint32_t REG_2318H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2318H_b; + }; + union + { + __IOM uint32_t REG_231CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_231CH_b; + }; + union + { + __IOM uint32_t REG_2320H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2320H_b; + }; + union + { + __IOM uint32_t REG_2324H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2324H_b; + }; + union + { + __IOM uint32_t REG_2328H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2328H_b; + }; + union + { + __IOM uint32_t REG_232CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_232CH_b; + }; + union + { + __IOM uint32_t REG_2330H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2330H_b; + }; + union + { + __IOM uint32_t REG_2334H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2334H_b; + }; + union + { + __IOM uint32_t REG_2338H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2338H_b; + }; + union + { + __IOM uint32_t REG_233CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_233CH_b; + }; + union + { + __IOM uint32_t REG_2340H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2340H_b; + }; + union + { + __IOM uint32_t REG_2344H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2344H_b; + }; + union + { + __IOM uint32_t REG_2348H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2348H_b; + }; + union + { + __IOM uint32_t REG_234CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_234CH_b; + }; + union + { + __IOM uint32_t REG_2350H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2350H_b; + }; + union + { + __IOM uint32_t REG_2354H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2354H_b; + }; + union + { + __IOM uint32_t REG_2358H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2358H_b; + }; + union + { + __IOM uint32_t REG_235CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_235CH_b; + }; + union + { + __IOM uint32_t REG_2360H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2360H_b; + }; + union + { + __IOM uint32_t REG_2364H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2364H_b; + }; + union + { + __IOM uint32_t REG_2368H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2368H_b; + }; + union + { + __IOM uint32_t REG_236CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_236CH_b; + }; + union + { + __IOM uint32_t REG_2370H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2370H_b; + }; + union + { + __IOM uint32_t REG_2374H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2374H_b; + }; + union + { + __IOM uint32_t REG_2378H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2378H_b; + }; + union + { + __IOM uint32_t REG_237CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_237CH_b; + }; + union + { + __IOM uint32_t REG_2380H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2380H_b; + }; + union + { + __IOM uint32_t REG_2384H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2384H_b; + }; + union + { + __IOM uint32_t REG_2388H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2388H_b; + }; + union + { + __IOM uint32_t REG_238CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_238CH_b; + }; + union + { + __IOM uint32_t REG_2390H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2390H_b; + }; + union + { + __IOM uint32_t REG_2394H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2394H_b; + }; + union + { + __IOM uint32_t REG_2398H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2398H_b; + }; + union + { + __IOM uint32_t REG_239CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_239CH_b; + }; + union + { + __IOM uint32_t REG_23A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23A0H_b; + }; + union + { + __IOM uint32_t REG_23A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23A4H_b; + }; + union + { + __IOM uint32_t REG_23A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23A8H_b; + }; + union + { + __IOM uint32_t REG_23ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23ACH_b; + }; + union + { + __IOM uint32_t REG_23B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23B0H_b; + }; + union + { + __IOM uint32_t REG_23B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23B4H_b; + }; + union + { + __IOM uint32_t REG_23B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23B8H_b; + }; + union + { + __IOM uint32_t REG_23BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23BCH_b; + }; + union + { + __IOM uint32_t REG_23C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23C0H_b; + }; + union + { + __IOM uint32_t REG_23C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23C4H_b; + }; + union + { + __IOM uint32_t REG_23C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23C8H_b; + }; + union + { + __IOM uint32_t REG_23CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23CCH_b; + }; + union + { + __IOM uint32_t REG_23D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23D0H_b; + }; + union + { + __IOM uint32_t REG_23D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23D4H_b; + }; + union + { + __IOM uint32_t REG_23D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23D8H_b; + }; + union + { + __IOM uint32_t REG_23DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23DCH_b; + }; + union + { + __IOM uint32_t REG_23E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23E0H_b; + }; + union + { + __IOM uint32_t REG_23E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23E4H_b; + }; + union + { + __IOM uint32_t REG_23E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23E8H_b; + }; + union + { + __IOM uint32_t REG_23ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23ECH_b; + }; + union + { + __IOM uint32_t REG_23F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23F0H_b; + }; + union + { + __IOM uint32_t REG_23F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23F4H_b; + }; + union + { + __IOM uint32_t REG_23F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23F8H_b; + }; + union + { + __IOM uint32_t REG_23FCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_23FCH_b; + }; + union + { + __IOM uint32_t REG_2400H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2400H_b; + }; + union + { + __IOM uint32_t REG_2404H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2404H_b; + }; + union + { + __IOM uint32_t REG_2408H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2408H_b; + }; + union + { + __IOM uint32_t REG_240CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_240CH_b; + }; + union + { + __IOM uint32_t REG_2410H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2410H_b; + }; + union + { + __IOM uint32_t REG_2414H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2414H_b; + }; + union + { + __IOM uint32_t REG_2418H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2418H_b; + }; + union + { + __IOM uint32_t REG_241CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_241CH_b; + }; + union + { + __IOM uint32_t REG_2420H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2420H_b; + }; + union + { + __IOM uint32_t REG_2424H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2424H_b; + }; + union + { + __IOM uint32_t REG_2428H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2428H_b; + }; + union + { + __IOM uint32_t REG_242CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_242CH_b; + }; + union + { + __IOM uint32_t REG_2430H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2430H_b; + }; + union + { + __IOM uint32_t REG_2434H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2434H_b; + }; + union + { + __IOM uint32_t REG_2438H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2438H_b; + }; + union + { + __IOM uint32_t REG_243CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_243CH_b; + }; + union + { + __IOM uint32_t REG_2440H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2440H_b; + }; + union + { + __IOM uint32_t REG_2444H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2444H_b; + }; + union + { + __IOM uint32_t REG_2448H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2448H_b; + }; + union + { + __IOM uint32_t REG_244CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_244CH_b; + }; + union + { + __IOM uint32_t REG_2450H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2450H_b; + }; + union + { + __IOM uint32_t REG_2454H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2454H_b; + }; + union + { + __IOM uint32_t REG_2458H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2458H_b; + }; + union + { + __IOM uint32_t REG_245CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_245CH_b; + }; + union + { + __IOM uint32_t REG_2460H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2460H_b; + }; + union + { + __IOM uint32_t REG_2464H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2464H_b; + }; + union + { + __IOM uint32_t REG_2468H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2468H_b; + }; + union + { + __IOM uint32_t REG_246CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_246CH_b; + }; + union + { + __IOM uint32_t REG_2470H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2470H_b; + }; + union + { + __IOM uint32_t REG_2474H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2474H_b; + }; + union + { + __IOM uint32_t REG_2478H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2478H_b; + }; + union + { + __IOM uint32_t REG_247CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_247CH_b; + }; + union + { + __IOM uint32_t REG_2480H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2480H_b; + }; + union + { + __IOM uint32_t REG_2484H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2484H_b; + }; + union + { + __IOM uint32_t REG_2488H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2488H_b; + }; + union + { + __IOM uint32_t REG_248CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_248CH_b; + }; + union + { + __IOM uint32_t REG_2490H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2490H_b; + }; + union + { + __IOM uint32_t REG_2494H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2494H_b; + }; + union + { + __IOM uint32_t REG_2498H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_2498H_b; + }; + union + { + __IOM uint32_t REG_249CH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_249CH_b; + }; + union + { + __IOM uint32_t REG_24A0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24A0H_b; + }; + union + { + __IOM uint32_t REG_24A4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24A4H_b; + }; + union + { + __IOM uint32_t REG_24A8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24A8H_b; + }; + union + { + __IOM uint32_t REG_24ACH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24ACH_b; + }; + union + { + __IOM uint32_t REG_24B0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24B0H_b; + }; + union + { + __IOM uint32_t REG_24B4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24B4H_b; + }; + union + { + __IOM uint32_t REG_24B8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24B8H_b; + }; + union + { + __IOM uint32_t REG_24BCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24BCH_b; + }; + union + { + __IOM uint32_t REG_24C0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24C0H_b; + }; + union + { + __IOM uint32_t REG_24C4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24C4H_b; + }; + union + { + __IOM uint32_t REG_24C8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24C8H_b; + }; + union + { + __IOM uint32_t REG_24CCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24CCH_b; + }; + union + { + __IOM uint32_t REG_24D0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24D0H_b; + }; + union + { + __IOM uint32_t REG_24D4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24D4H_b; + }; + union + { + __IOM uint32_t REG_24D8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24D8H_b; + }; + union + { + __IOM uint32_t REG_24DCH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24DCH_b; + }; + union + { + __IOM uint32_t REG_24E0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24E0H_b; + }; + union + { + __IOM uint32_t REG_24E4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24E4H_b; + }; + union + { + __IOM uint32_t REG_24E8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24E8H_b; + }; + union + { + __IOM uint32_t REG_24ECH; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24ECH_b; + }; + union + { + __IOM uint32_t REG_24F0H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24F0H_b; + }; + union + { + __IOM uint32_t REG_24F4H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24F4H_b; + }; + union + { + __IOM uint32_t REG_24F8H; + struct + { + __IOM uint32_t B0 : 1; + __IOM uint32_t B1 : 1; + __IOM uint32_t B2 : 1; + __IOM uint32_t B3 : 1; + __IOM uint32_t B4 : 1; + __IOM uint32_t B5 : 1; + __IOM uint32_t B6 : 1; + __IOM uint32_t B7 : 1; + __IOM uint32_t B8 : 1; + __IOM uint32_t B9 : 1; + __IOM uint32_t B10 : 1; + __IOM uint32_t B11 : 1; + __IOM uint32_t B12 : 1; + __IOM uint32_t B13 : 1; + __IOM uint32_t B14 : 1; + __IOM uint32_t B15 : 1; + __IOM uint32_t B16 : 1; + __IOM uint32_t B17 : 1; + __IOM uint32_t B18 : 1; + __IOM uint32_t B19 : 1; + __IOM uint32_t B20 : 1; + __IOM uint32_t B21 : 1; + __IOM uint32_t B22 : 1; + __IOM uint32_t B23 : 1; + __IOM uint32_t B24 : 1; + __IOM uint32_t B25 : 1; + __IOM uint32_t B26 : 1; + __IOM uint32_t B27 : 1; + __IOM uint32_t B28 : 1; + __IOM uint32_t B29 : 1; + __IOM uint32_t B30 : 1; + __IOM uint32_t B31 : 1; + } REG_24F8H_b; + }; +} SCE_Type; + +// for bit access + +/* -------------------------------- SCE.REG_xxxH -------------------------------- */ +#define SCE_REG_0_Pos 0 /*!< SCE REG_xxxH: bit 0 Position */ +#define SCE_REG_0_Msk (0x01UL << SCE_REG_0_Pos) /*!< SCE REG_xxxH: bit 0 Mask */ +#define SCE_REG_1_Pos 1 /*!< SCE REG_xxxH: bit 1 Position */ +#define SCE_REG_1_Msk (0x01UL << SCE_REG_1_Pos) /*!< SCE REG_xxxH: bit 1 Mask */ +#define SCE_REG_2_Pos 2 /*!< SCE REG_xxxH: bit 2 Position */ +#define SCE_REG_2_Msk (0x01UL << SCE_REG_2_Pos) /*!< SCE REG_xxxH: bit 2 Mask */ +#define SCE_REG_3_Pos 3 /*!< SCE REG_xxxH: bit 3 Position */ +#define SCE_REG_3_Msk (0x01UL << SCE_REG_3_Pos) /*!< SCE REG_xxxH: bit 3 Mask */ +#define SCE_REG_4_Pos 4 /*!< SCE REG_xxxH: bit 4 Position */ +#define SCE_REG_4_Msk (0x01UL << SCE_REG_4_Pos) /*!< SCE REG_xxxH: bit 4 Mask */ +#define SCE_REG_5_Pos 5 /*!< SCE REG_xxxH: bit 5 Position */ +#define SCE_REG_5_Msk (0x01UL << SCE_REG_5_Pos) /*!< SCE REG_xxxH: bit 5 Mask */ +#define SCE_REG_6_Pos 6 /*!< SCE REG_xxxH: bit 6 Position */ +#define SCE_REG_6_Msk (0x01UL << SCE_REG_6_Pos) /*!< SCE REG_xxxH: bit 6 Mask */ +#define SCE_REG_7_Pos 7 /*!< SCE REG_xxxH: bit 7 Position */ +#define SCE_REG_7_Msk (0x01UL << SCE_REG_7_Pos) /*!< SCE REG_xxxH: bit 7 Mask */ +#define SCE_REG_8_Pos 8 /*!< SCE REG_xxxH: bit 8 Position */ +#define SCE_REG_8_Msk (0x01UL << SCE_REG_8_Pos) /*!< SCE REG_xxxH: bit 8 Mask */ +#define SCE_REG_9_Pos 9 /*!< SCE REG_xxxH: bit 9 Position */ +#define SCE_REG_9_Msk (0x01UL << SCE_REG_9_Pos) /*!< SCE REG_xxxH: bit 9 Mask */ +#define SCE_REG_10_Pos 10 /*!< SCE REG_xxxH: bit 10 Position */ +#define SCE_REG_10_Msk (0x01UL << SCE_REG_10_Pos) /*!< SCE REG_xxxH: bit 10 Mask */ +#define SCE_REG_11_Pos 11 /*!< SCE REG_xxxH: bit 11 Position */ +#define SCE_REG_11_Msk (0x01UL << SCE_REG_11_Pos) /*!< SCE REG_xxxH: bit 11 Mask */ +#define SCE_REG_12_Pos 12 /*!< SCE REG_xxxH: bit 12 Position */ +#define SCE_REG_12_Msk (0x01UL << SCE_REG_12_Pos) /*!< SCE REG_xxxH: bit 12 Mask */ +#define SCE_REG_13_Pos 13 /*!< SCE REG_xxxH: bit 13 Position */ +#define SCE_REG_13_Msk (0x01UL << SCE_REG_13_Pos) /*!< SCE REG_xxxH: bit 13 Mask */ +#define SCE_REG_14_Pos 14 /*!< SCE REG_xxxH: bit 14 Position */ +#define SCE_REG_14_Msk (0x01UL << SCE_REG_14_Pos) /*!< SCE REG_xxxH: bit 14 Mask */ +#define SCE_REG_15_Pos 15 /*!< SCE REG_xxxH: bit 15 Position */ +#define SCE_REG_15_Msk (0x01UL << SCE_REG_15_Pos) /*!< SCE REG_xxxH: bit 15 Mask */ +#define SCE_REG_16_Pos 16 /*!< SCE REG_xxxH: bit 16 Position */ +#define SCE_REG_16_Msk (0x01UL << SCE_REG_16_Pos) /*!< SCE REG_xxxH: bit 16 Mask */ +#define SCE_REG_17_Pos 17 /*!< SCE REG_xxxH: bit 17 Position */ +#define SCE_REG_17_Msk (0x01UL << SCE_REG_17_Pos) /*!< SCE REG_xxxH: bit 17 Mask */ +#define SCE_REG_18_Pos 18 /*!< SCE REG_xxxH: bit 18 Position */ +#define SCE_REG_18_Msk (0x01UL << SCE_REG_18_Pos) /*!< SCE REG_xxxH: bit 18 Mask */ +#define SCE_REG_19_Pos 19 /*!< SCE REG_xxxH: bit 19 Position */ +#define SCE_REG_19_Msk (0x01UL << SCE_REG_19_Pos) /*!< SCE REG_xxxH: bit 19 Mask */ +#define SCE_REG_20_Pos 20 /*!< SCE REG_xxxH: bit 20 Position */ +#define SCE_REG_20_Msk (0x01UL << SCE_REG_20_Pos) /*!< SCE REG_xxxH: bit 20 Mask */ +#define SCE_REG_21_Pos 21 /*!< SCE REG_xxxH: bit 21 Position */ +#define SCE_REG_21_Msk (0x01UL << SCE_REG_21_Pos) /*!< SCE REG_xxxH: bit 21 Mask */ +#define SCE_REG_22_Pos 22 /*!< SCE REG_xxxH: bit 22 Position */ +#define SCE_REG_22_Msk (0x01UL << SCE_REG_22_Pos) /*!< SCE REG_xxxH: bit 22 Mask */ +#define SCE_REG_23_Pos 23 /*!< SCE REG_xxxH: bit 23 Position */ +#define SCE_REG_23_Msk (0x01UL << SCE_REG_23_Pos) /*!< SCE REG_xxxH: bit 23 Mask */ +#define SCE_REG_24_Pos 24 /*!< SCE REG_xxxH: bit 24 Position */ +#define SCE_REG_24_Msk (0x01UL << SCE_REG_24_Pos) /*!< SCE REG_xxxH: bit 24 Mask */ +#define SCE_REG_25_Pos 25 /*!< SCE REG_xxxH: bit 25 Position */ +#define SCE_REG_25_Msk (0x01UL << SCE_REG_25_Pos) /*!< SCE REG_xxxH: bit 25 Mask */ +#define SCE_REG_26_Pos 26 /*!< SCE REG_xxxH: bit 26 Position */ +#define SCE_REG_26_Msk (0x01UL << SCE_REG_26_Pos) /*!< SCE REG_xxxH: bit 26 Mask */ +#define SCE_REG_27_Pos 27 /*!< SCE REG_xxxH: bit 27 Position */ +#define SCE_REG_27_Msk (0x01UL << SCE_REG_27_Pos) /*!< SCE REG_xxxH: bit 27 Mask */ +#define SCE_REG_28_Pos 28 /*!< SCE REG_xxxH: bit 28 Position */ +#define SCE_REG_28_Msk (0x01UL << SCE_REG_28_Pos) /*!< SCE REG_xxxH: bit 28 Mask */ +#define SCE_REG_29_Pos 29 /*!< SCE REG_xxxH: bit 29 Position */ +#define SCE_REG_29_Msk (0x01UL << SCE_REG_29_Pos) /*!< SCE REG_xxxH: bit 29 Mask */ +#define SCE_REG_30_Pos 30 /*!< SCE REG_xxxH: bit 30 Position */ +#define SCE_REG_30_Msk (0x01UL << SCE_REG_30_Pos) /*!< SCE REG_xxxH: bit 30 Mask */ +#define SCE_REG_31_Pos 31 /*!< SCE REG_xxxH: bit 31 Position */ +#define SCE_REG_31_Msk (0x01UL << SCE_REG_31_Pos) /*!< SCE REG_xxxH: bit 31 Mask */ + +/* ================================================================================ */ +/* ================ Peripheral declaration ================ */ +/* ================================================================================ */ + +#define SCE ((SCE_Type *) SCE_BASE) + +// macro definishion + +#define SCE_DELAY(delay) \ + for (volatile uint32_t count = 0; count < delay; count++) \ + { \ + ; \ + } + +// [R RD 1 B] +#define RD1_PROG(regName) \ + (SCE->regName) + +// [R WR 1 B] +#define WR1_PROG(regName, value) \ + SCE->regName = value + +// [R WR 2 B0 B1] +#define WR2_PROG(regName, value0, value1) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); + +// [R WR 3 B0 B1 B2] +#define WR3_PROG(regName, value0, value1, value2) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2) + +// [R WR 4 B0 B1 B2 B3] +#define WR4_PROG(regName, value0, value1, value2, value3) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2); \ + WR1_PROG(regName, value3) + +// [R WR 16 B0 B1 B2 B3 B4 B5 B6 B7 B8 B9 B10 B11 B12 B13 B14 B15] +#define WR16_PROG(regName, \ + value0, \ + value1, \ + value2, \ + value3, \ + value4, \ + value5, \ + value6, \ + value7, \ + value8, \ + value9, \ + value10, \ + value11, \ + value12, \ + value13, \ + value14, \ + value15) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2); \ + WR1_PROG(regName, value3); \ + WR1_PROG(regName, value4); \ + WR1_PROG(regName, value5); \ + WR1_PROG(regName, value6); \ + WR1_PROG(regName, value7); \ + WR1_PROG(regName, value8); \ + WR1_PROG(regName, value9); \ + WR1_PROG(regName, value10); \ + WR1_PROG(regName, value11); \ + WR1_PROG(regName, value12); \ + WR1_PROG(regName, value13); \ + WR1_PROG(regName, value14); \ + WR1_PROG(regName, value15) + +// [R RD 1 B] +#define RD1_EVAL(regName, value) \ + if (SCE->regname != value) \ + return FSP_ERR_CRYPTO_SCE_FAIL + +// [R CHK_STATUS A B] +#define CHCK_STS(regName, bitPos, value) \ + (((SCE->regName & (0x01UL << bitPos)) >> bitPos) == value) + +// [R CHK_REG A (!= B)] +#define RD1_MASK(regName, maskValue) \ + (SCE->regName & maskValue) + +// [R WAIT_STATUS A B] +#define WAIT_STS(regName, bitPos, value) \ + while (!CHCK_STS(regName, bitPos, value)) + +// [R WR 1 MEM[Ofs]] +#define WR1_ADDR(regName, addr) \ + SCE->regName = *(addr) + +// [R WR 2 MEM[Ofs]] +#define WR2_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); + +// [R WR 3 MEM[Ofs]] +#define WR3_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); + +// [R WR 4 MEM[Ofs]] +#define WR4_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3) + +// [R WR 5 MEM[Ofs]] +#define WR5_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4) + +// [R WR 6 MEM[Ofs]] +#define WR6_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5) + +// [R WR 7 MEM[Ofs]] +#define WR7_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6) + +// [R WR 8 MEM[Ofs]] +#define WR8_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6); \ + WR1_ADDR(regName, (addr) + 7) + +// [R WR 12 MEM[Ofs]] +#define WR12_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6); \ + WR1_ADDR(regName, (addr) + 7); \ + WR1_ADDR(regName, (addr) + 8); \ + WR1_ADDR(regName, (addr) + 9); \ + WR1_ADDR(regName, (addr) + 10); \ + WR1_ADDR(regName, (addr) + 11) + +// [R WR 16 MEM[Ofs]] +#define WR16_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6); \ + WR1_ADDR(regName, (addr) + 7); \ + WR1_ADDR(regName, (addr) + 8); \ + WR1_ADDR(regName, (addr) + 9); \ + WR1_ADDR(regName, (addr) + 10); \ + WR1_ADDR(regName, (addr) + 11); \ + WR1_ADDR(regName, (addr) + 12); \ + WR1_ADDR(regName, (addr) + 13); \ + WR1_ADDR(regName, (addr) + 14); \ + WR1_ADDR(regName, (addr) + 15) + +// [R WR 32 MEM[Ofs]] +#define WR32_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6); \ + WR1_ADDR(regName, (addr) + 7); \ + WR1_ADDR(regName, (addr) + 8); \ + WR1_ADDR(regName, (addr) + 9); \ + WR1_ADDR(regName, (addr) + 10); \ + WR1_ADDR(regName, (addr) + 11); \ + WR1_ADDR(regName, (addr) + 12); \ + WR1_ADDR(regName, (addr) + 13); \ + WR1_ADDR(regName, (addr) + 14); \ + WR1_ADDR(regName, (addr) + 15); \ + WR1_ADDR(regName, (addr) + 16); \ + WR1_ADDR(regName, (addr) + 17); \ + WR1_ADDR(regName, (addr) + 18); \ + WR1_ADDR(regName, (addr) + 19); \ + WR1_ADDR(regName, (addr) + 20); \ + WR1_ADDR(regName, (addr) + 21); \ + WR1_ADDR(regName, (addr) + 22); \ + WR1_ADDR(regName, (addr) + 23); \ + WR1_ADDR(regName, (addr) + 24); \ + WR1_ADDR(regName, (addr) + 25); \ + WR1_ADDR(regName, (addr) + 26); \ + WR1_ADDR(regName, (addr) + 27); \ + WR1_ADDR(regName, (addr) + 28); \ + WR1_ADDR(regName, (addr) + 29); \ + WR1_ADDR(regName, (addr) + 30); \ + WR1_ADDR(regName, (addr) + 31) + +// [R WR 64 MEM[Ofs]] +#define WR64_ADDR(regName, addr) \ + WR1_ADDR(regName, (addr) + 0); \ + WR1_ADDR(regName, (addr) + 1); \ + WR1_ADDR(regName, (addr) + 2); \ + WR1_ADDR(regName, (addr) + 3); \ + WR1_ADDR(regName, (addr) + 4); \ + WR1_ADDR(regName, (addr) + 5); \ + WR1_ADDR(regName, (addr) + 6); \ + WR1_ADDR(regName, (addr) + 7); \ + WR1_ADDR(regName, (addr) + 8); \ + WR1_ADDR(regName, (addr) + 9); \ + WR1_ADDR(regName, (addr) + 10); \ + WR1_ADDR(regName, (addr) + 11); \ + WR1_ADDR(regName, (addr) + 12); \ + WR1_ADDR(regName, (addr) + 13); \ + WR1_ADDR(regName, (addr) + 14); \ + WR1_ADDR(regName, (addr) + 15); \ + WR1_ADDR(regName, (addr) + 16); \ + WR1_ADDR(regName, (addr) + 17); \ + WR1_ADDR(regName, (addr) + 18); \ + WR1_ADDR(regName, (addr) + 19); \ + WR1_ADDR(regName, (addr) + 20); \ + WR1_ADDR(regName, (addr) + 21); \ + WR1_ADDR(regName, (addr) + 22); \ + WR1_ADDR(regName, (addr) + 23); \ + WR1_ADDR(regName, (addr) + 24); \ + WR1_ADDR(regName, (addr) + 25); \ + WR1_ADDR(regName, (addr) + 26); \ + WR1_ADDR(regName, (addr) + 27); \ + WR1_ADDR(regName, (addr) + 28); \ + WR1_ADDR(regName, (addr) + 29); \ + WR1_ADDR(regName, (addr) + 30); \ + WR1_ADDR(regName, (addr) + 31); \ + WR1_ADDR(regName, (addr) + 32); \ + WR1_ADDR(regName, (addr) + 33); \ + WR1_ADDR(regName, (addr) + 34); \ + WR1_ADDR(regName, (addr) + 35); \ + WR1_ADDR(regName, (addr) + 36); \ + WR1_ADDR(regName, (addr) + 37); \ + WR1_ADDR(regName, (addr) + 38); \ + WR1_ADDR(regName, (addr) + 39); \ + WR1_ADDR(regName, (addr) + 40); \ + WR1_ADDR(regName, (addr) + 41); \ + WR1_ADDR(regName, (addr) + 42); \ + WR1_ADDR(regName, (addr) + 43); \ + WR1_ADDR(regName, (addr) + 44); \ + WR1_ADDR(regName, (addr) + 45); \ + WR1_ADDR(regName, (addr) + 46); \ + WR1_ADDR(regName, (addr) + 47); \ + WR1_ADDR(regName, (addr) + 48); \ + WR1_ADDR(regName, (addr) + 49); \ + WR1_ADDR(regName, (addr) + 50); \ + WR1_ADDR(regName, (addr) + 51); \ + WR1_ADDR(regName, (addr) + 52); \ + WR1_ADDR(regName, (addr) + 53); \ + WR1_ADDR(regName, (addr) + 54); \ + WR1_ADDR(regName, (addr) + 55); \ + WR1_ADDR(regName, (addr) + 56); \ + WR1_ADDR(regName, (addr) + 57); \ + WR1_ADDR(regName, (addr) + 58); \ + WR1_ADDR(regName, (addr) + 59); \ + WR1_ADDR(regName, (addr) + 60); \ + WR1_ADDR(regName, (addr) + 61); \ + WR1_ADDR(regName, (addr) + 62); \ + WR1_ADDR(regName, (addr) + 63) + +// [R RD 1 MEM[Ofs]] +#define RD1_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; + +// [R RD 2 MEM[Ofs]] +#define RD2_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; + +// [R RD 3 MEM[Ofs]] +#define RD3_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; + +// [R RD 4 MEM[Ofs]] +#define RD4_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName + +// [R RD 5 MEM[Ofs]] +#define RD5_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName + +// [R RD 6 MEM[Ofs]] +#define RD6_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName + +// [R RD 7 MEM[Ofs]] +#define RD7_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName + +// [R RD 8 MEM[Ofs]] +#define RD8_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName; \ + *((addr) + 7) = SCE->regName + +// [R RD 12 MEM[Ofs]] +#define RD12_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName; \ + *((addr) + 7) = SCE->regName; \ + *((addr) + 8) = SCE->regName; \ + *((addr) + 9) = SCE->regName; \ + *((addr) + 10) = SCE->regName; \ + *((addr) + 11) = SCE->regName + +// [R RD 16 MEM[Ofs]] +#define RD16_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName; \ + *((addr) + 7) = SCE->regName; \ + *((addr) + 8) = SCE->regName; \ + *((addr) + 9) = SCE->regName; \ + *((addr) + 10) = SCE->regName; \ + *((addr) + 11) = SCE->regName; \ + *((addr) + 12) = SCE->regName; \ + *((addr) + 13) = SCE->regName; \ + *((addr) + 14) = SCE->regName; \ + *((addr) + 15) = SCE->regName + +// [R RD 32 MEM[Ofs]] +#define RD32_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName; \ + *((addr) + 7) = SCE->regName; \ + *((addr) + 8) = SCE->regName; \ + *((addr) + 9) = SCE->regName; \ + *((addr) + 10) = SCE->regName; \ + *((addr) + 11) = SCE->regName; \ + *((addr) + 12) = SCE->regName; \ + *((addr) + 13) = SCE->regName; \ + *((addr) + 14) = SCE->regName; \ + *((addr) + 15) = SCE->regName; \ + *((addr) + 16) = SCE->regName; \ + *((addr) + 17) = SCE->regName; \ + *((addr) + 18) = SCE->regName; \ + *((addr) + 19) = SCE->regName; \ + *((addr) + 20) = SCE->regName; \ + *((addr) + 21) = SCE->regName; \ + *((addr) + 22) = SCE->regName; \ + *((addr) + 23) = SCE->regName; \ + *((addr) + 24) = SCE->regName; \ + *((addr) + 25) = SCE->regName; \ + *((addr) + 26) = SCE->regName; \ + *((addr) + 27) = SCE->regName; \ + *((addr) + 28) = SCE->regName; \ + *((addr) + 29) = SCE->regName; \ + *((addr) + 30) = SCE->regName; \ + *((addr) + 31) = SCE->regName + +// [R RD 64 MEM[Ofs]] +#define RD64_ADDR(regName, addr) \ + *((addr) + 0) = SCE->regName; \ + *((addr) + 1) = SCE->regName; \ + *((addr) + 2) = SCE->regName; \ + *((addr) + 3) = SCE->regName; \ + *((addr) + 4) = SCE->regName; \ + *((addr) + 5) = SCE->regName; \ + *((addr) + 6) = SCE->regName; \ + *((addr) + 7) = SCE->regName; \ + *((addr) + 8) = SCE->regName; \ + *((addr) + 9) = SCE->regName; \ + *((addr) + 10) = SCE->regName; \ + *((addr) + 11) = SCE->regName; \ + *((addr) + 12) = SCE->regName; \ + *((addr) + 13) = SCE->regName; \ + *((addr) + 14) = SCE->regName; \ + *((addr) + 15) = SCE->regName; \ + *((addr) + 16) = SCE->regName; \ + *((addr) + 17) = SCE->regName; \ + *((addr) + 18) = SCE->regName; \ + *((addr) + 19) = SCE->regName; \ + *((addr) + 20) = SCE->regName; \ + *((addr) + 21) = SCE->regName; \ + *((addr) + 22) = SCE->regName; \ + *((addr) + 23) = SCE->regName; \ + *((addr) + 24) = SCE->regName; \ + *((addr) + 25) = SCE->regName; \ + *((addr) + 26) = SCE->regName; \ + *((addr) + 27) = SCE->regName; \ + *((addr) + 28) = SCE->regName; \ + *((addr) + 29) = SCE->regName; \ + *((addr) + 30) = SCE->regName; \ + *((addr) + 31) = SCE->regName; \ + *((addr) + 32) = SCE->regName; \ + *((addr) + 33) = SCE->regName; \ + *((addr) + 34) = SCE->regName; \ + *((addr) + 35) = SCE->regName; \ + *((addr) + 36) = SCE->regName; \ + *((addr) + 37) = SCE->regName; \ + *((addr) + 38) = SCE->regName; \ + *((addr) + 39) = SCE->regName; \ + *((addr) + 40) = SCE->regName; \ + *((addr) + 41) = SCE->regName; \ + *((addr) + 42) = SCE->regName; \ + *((addr) + 43) = SCE->regName; \ + *((addr) + 44) = SCE->regName; \ + *((addr) + 45) = SCE->regName; \ + *((addr) + 46) = SCE->regName; \ + *((addr) + 47) = SCE->regName; \ + *((addr) + 48) = SCE->regName; \ + *((addr) + 49) = SCE->regName; \ + *((addr) + 50) = SCE->regName; \ + *((addr) + 51) = SCE->regName; \ + *((addr) + 52) = SCE->regName; \ + *((addr) + 53) = SCE->regName; \ + *((addr) + 54) = SCE->regName; \ + *((addr) + 55) = SCE->regName; \ + *((addr) + 56) = SCE->regName; \ + *((addr) + 57) = SCE->regName; \ + *((addr) + 58) = SCE->regName; \ + *((addr) + 59) = SCE->regName; \ + *((addr) + 60) = SCE->regName; \ + *((addr) + 61) = SCE->regName; \ + *((addr) + 62) = SCE->regName; \ + *((addr) + 63) = SCE->regName + +// [TEST_BUSY WAIT A] +#define WAI_BUSY(value) \ + WAIT_STS(SCE->REG_00H, 31, value) + +void SC32_function001(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void SC32_function002(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void SC32_function003(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); + +void SC327_function001(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void SC327_function002(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void SC327_function003(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); + +// [R WR 32 B0 B1 B2 B3 B4 .... B31] +#define WR32_PROG(regName, \ + value0, value1, value2, value3, value4, value5, value6, value7, value8, value9, \ + value10, value11, value12, value13, value14, value15, value16, value17, value18, value19, \ + value20, value21, value22, value23, value24, value25, value26, value27, value28, value29, \ + value30, value31 \ + ) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2); \ + WR1_PROG(regName, value3); \ + WR1_PROG(regName, value4); \ + WR1_PROG(regName, value5); \ + WR1_PROG(regName, value6); \ + WR1_PROG(regName, value7); \ + WR1_PROG(regName, value8); \ + WR1_PROG(regName, value9); \ + WR1_PROG(regName, value10); \ + WR1_PROG(regName, value11); \ + WR1_PROG(regName, value12); \ + WR1_PROG(regName, value13); \ + WR1_PROG(regName, value14); \ + WR1_PROG(regName, value15); \ + WR1_PROG(regName, value16); \ + WR1_PROG(regName, value17); \ + WR1_PROG(regName, value18); \ + WR1_PROG(regName, value19); \ + WR1_PROG(regName, value20); \ + WR1_PROG(regName, value21); \ + WR1_PROG(regName, value22); \ + WR1_PROG(regName, value23); \ + WR1_PROG(regName, value24); \ + WR1_PROG(regName, value25); \ + WR1_PROG(regName, value26); \ + WR1_PROG(regName, value27); \ + WR1_PROG(regName, value28); \ + WR1_PROG(regName, value29); \ + WR1_PROG(regName, value30); \ + WR1_PROG(regName, value31) + +// [R WR 48 B0 B1 B2 B3 B4 .... B47] +#define WR48_PROG(regName, \ + value0, value1, value2, value3, value4, value5, value6, value7, value8, value9, \ + value10, value11, value12, value13, value14, value15, value16, value17, value18, value19, \ + value20, value21, value22, value23, value24, value25, value26, value27, value28, value29, \ + value30, value31, value32, value33, value34, value35, value36, value37, value38, value39, \ + value40, value41, value42, value43, value44, value45, value46, value47 \ + ) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2); \ + WR1_PROG(regName, value3); \ + WR1_PROG(regName, value4); \ + WR1_PROG(regName, value5); \ + WR1_PROG(regName, value6); \ + WR1_PROG(regName, value7); \ + WR1_PROG(regName, value8); \ + WR1_PROG(regName, value9); \ + WR1_PROG(regName, value10); \ + WR1_PROG(regName, value11); \ + WR1_PROG(regName, value12); \ + WR1_PROG(regName, value13); \ + WR1_PROG(regName, value14); \ + WR1_PROG(regName, value15); \ + WR1_PROG(regName, value16); \ + WR1_PROG(regName, value17); \ + WR1_PROG(regName, value18); \ + WR1_PROG(regName, value19); \ + WR1_PROG(regName, value20); \ + WR1_PROG(regName, value21); \ + WR1_PROG(regName, value22); \ + WR1_PROG(regName, value23); \ + WR1_PROG(regName, value24); \ + WR1_PROG(regName, value25); \ + WR1_PROG(regName, value26); \ + WR1_PROG(regName, value27); \ + WR1_PROG(regName, value28); \ + WR1_PROG(regName, value29); \ + WR1_PROG(regName, value30); \ + WR1_PROG(regName, value31); \ + WR1_PROG(regName, value32); \ + WR1_PROG(regName, value33); \ + WR1_PROG(regName, value34); \ + WR1_PROG(regName, value35); \ + WR1_PROG(regName, value36); \ + WR1_PROG(regName, value37); \ + WR1_PROG(regName, value38); \ + WR1_PROG(regName, value39); \ + WR1_PROG(regName, value40); \ + WR1_PROG(regName, value41); \ + WR1_PROG(regName, value42); \ + WR1_PROG(regName, value43); \ + WR1_PROG(regName, value44); \ + WR1_PROG(regName, value45); \ + WR1_PROG(regName, value46); \ + WR1_PROG(regName, value47) + +// [R WR 48 B0 B1 B2 B3 B4 .... B47] +#define WR64_PROG(regName, \ + value0, value1, value2, value3, value4, value5, value6, value7, value8, value9, \ + value10, value11, value12, value13, value14, value15, value16, value17, value18, value19, \ + value20, value21, value22, value23, value24, value25, value26, value27, value28, value29, \ + value30, value31, value32, value33, value34, value35, value36, value37, value38, value39, \ + value40, value41, value42, value43, value44, value45, value46, value47, value48, value49, \ + value50, value51, value52, value53, value54, value55, value56, value57, value58, value59, \ + value60, value61, value62, value63 \ + ) \ + WR1_PROG(regName, value0); \ + WR1_PROG(regName, value1); \ + WR1_PROG(regName, value2); \ + WR1_PROG(regName, value3); \ + WR1_PROG(regName, value4); \ + WR1_PROG(regName, value5); \ + WR1_PROG(regName, value6); \ + WR1_PROG(regName, value7); \ + WR1_PROG(regName, value8); \ + WR1_PROG(regName, value9); \ + WR1_PROG(regName, value10); \ + WR1_PROG(regName, value11); \ + WR1_PROG(regName, value12); \ + WR1_PROG(regName, value13); \ + WR1_PROG(regName, value14); \ + WR1_PROG(regName, value15); \ + WR1_PROG(regName, value16); \ + WR1_PROG(regName, value17); \ + WR1_PROG(regName, value18); \ + WR1_PROG(regName, value19); \ + WR1_PROG(regName, value20); \ + WR1_PROG(regName, value21); \ + WR1_PROG(regName, value22); \ + WR1_PROG(regName, value23); \ + WR1_PROG(regName, value24); \ + WR1_PROG(regName, value25); \ + WR1_PROG(regName, value26); \ + WR1_PROG(regName, value27); \ + WR1_PROG(regName, value28); \ + WR1_PROG(regName, value29); \ + WR1_PROG(regName, value30); \ + WR1_PROG(regName, value31); \ + WR1_PROG(regName, value32); \ + WR1_PROG(regName, value33); \ + WR1_PROG(regName, value34); \ + WR1_PROG(regName, value35); \ + WR1_PROG(regName, value36); \ + WR1_PROG(regName, value37); \ + WR1_PROG(regName, value38); \ + WR1_PROG(regName, value39); \ + WR1_PROG(regName, value40); \ + WR1_PROG(regName, value41); \ + WR1_PROG(regName, value42); \ + WR1_PROG(regName, value43); \ + WR1_PROG(regName, value44); \ + WR1_PROG(regName, value45); \ + WR1_PROG(regName, value46); \ + WR1_PROG(regName, value47); \ + WR1_PROG(regName, value48); \ + WR1_PROG(regName, value49); \ + WR1_PROG(regName, value50); \ + WR1_PROG(regName, value51); \ + WR1_PROG(regName, value52); \ + WR1_PROG(regName, value53); \ + WR1_PROG(regName, value54); \ + WR1_PROG(regName, value55); \ + WR1_PROG(regName, value56); \ + WR1_PROG(regName, value57); \ + WR1_PROG(regName, value58); \ + WR1_PROG(regName, value59); \ + WR1_PROG(regName, value60); \ + WR1_PROG(regName, value61); \ + WR1_PROG(regName, value62); \ + WR1_PROG(regName, value63) + +#endif // __SCE_ProcCommon_h__ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/SCE_module.h b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/SCE_module.h new file mode 100644 index 000000000..1b7ebeb74 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/SCE_module.h @@ -0,0 +1,30 @@ +/*********************************************************************************************************************** + * Copyright [2020-2021] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +#ifndef HW_SCE_MODULE_H +#define HW_SCE_MODULE_H + +/* ================================================================================ */ +/* ================ Peripheral memory map ================ */ +/* ================================================================================ */ + +#define SCE_BASE 0x403B0000UL + +#endif // HW_SCE_MODULE_H diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/hw_sce_ra_private.h new file mode 100644 index 000000000..a0df11a34 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/private/inc/hw_sce_ra_private.h @@ -0,0 +1,480 @@ +#include "SCE_ProcCommon.h" + +#ifndef HW_SCE_RA_PRIVATE_HEADER_FILE +#define HW_SCE_RA_PRIVATE_HEADER_FILE + +/********************************************************************************************************************** + Macro definitions + *********************************************************************************************************************/ +/* Version Number of API. */ +#define SCE_VERSION_MAJOR (1U) +#define SCE_VERSION_MINOR (9U) + +/* Various information. */ +#define HW_SCE_SRAM_WORD_SIZE (32U) +#define HW_SCE_SINST_WORD_SIZE (140U) +#define HW_SCE_SINST2_WORD_SIZE (16U) +#define HW_SCE_SHEAP_WORD_SIZE (1504U) +#define HW_SCE_MAC_SIZE (16U) + +/* For AES operation. */ +#define HW_SCE_AES128_KEY_INDEX_WORD_SIZE (12U) +#define HW_SCE_AES192_KEY_INDEX_WORD_SIZE (16U) +#define HW_SCE_AES256_KEY_INDEX_WORD_SIZE (16U) +#define HW_SCE_AES128_KEY_WORD_SIZE (4U) +#define HW_SCE_AES192_KEY_WORD_SIZE (8U) +#define HW_SCE_AES256_KEY_WORD_SIZE (8U) +#define HW_SCE_AES128_KEY_BYTE_SIZE (16U) +#define HW_SCE_AES192_KEY_BYTE_SIZE (32U) +#define HW_SCE_AES256_KEY_BYTE_SIZE (32U) +#define HW_SCE_AES_BLOCK_BYTE_SIZE (16U) +#define HW_SCE_AES_BLOCK_BIT_SIZE (128U) +#define HW_SCE_AES_CBC_IV_BYTE_SIZE (16U) +#define HW_SCE_AES_CTR_ICOUNTER_BYTE_SIZE (16U) +#define HW_SCE_AES_GCM_AAD_BLOCK_BYTE_SIZE (16U) +#define HW_SCE_AES_CCM_B_FORMAT_BYTE_SIZE (128U) +#define HW_SCE_AES_CCM_COUNTER_BYTE_SIZE (16U) +#define HW_SCE_AES128XTS_KEY_BYTE_SIZE (32U) +#define HW_SCE_AES256XTS_KEY_BYTE_SIZE (64U) +#define HW_SCE_AES_XTS_IV_BYTE_SIZE (16U) + +/* For TDES operation. */ +#define HW_SCE_TDES_KEY_INDEX_WORD_SIZE (16U) +#define HW_SCE_TDES_BLOCK_BYTE_SIZE (8U) +#define HW_SCE_TDES_CBC_IV_BYTE_SIZE (8U) +#define HW_SCE_TDES_KEY_WORD_SIZE (8U) +#define HW_SCE_TDES_KEY_BYTE_SIZE (32U) + +/* For ARC4 operation. */ +#define HW_SCE_ARC4_KEY_INDEX_WORD_SIZE (72U) +#define HW_SCE_ARC4_KEY_WORD_SIZE (64U) +#define HW_SCE_ARC4_KEY_BYTE_SIZE (256U) +#define HW_SCE_ARC4_BLOCK_BYTE_SIZE (16U) + +/* For SHA operation. */ +#define HW_SCE_SHA1_HASH_LENGTH_BYTE_SIZE (20U) +#define HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE (32U) +#define HW_SCE_SHA384_HASH_LENGTH_BYTE_SIZE (48U) + +/* For MD5 operation. */ +#define HW_SCE_MD5_HASH_LENGTH_BYTE_SIZE (16U) + +/* For HMAC operation. */ +#define HW_SCE_HMAC_KEY_INDEX_BYTE_SIZE (32U) +#define HW_SCE_HMAC_KEY_INDEX_WORD_SIZE (8U) + +/* For RSA operation. */ +#define HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE (128U) +#define HW_SCE_RSA_1024_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_1024_KEY_D_LENGTH_BYTE_SIZE (128U) +#define HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE (256U) +#define HW_SCE_RSA_2048_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_2048_KEY_D_LENGTH_BYTE_SIZE (256U) +#define HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE (96 * 4U) +#define HW_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_3072_KEY_D_LENGTH_BYTE_SIZE (96 * 4U) +#define HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE (128 * 4U) +#define HW_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE (4U) +#define HW_SCE_RSA_4096_KEY_D_LENGTH_BYTE_SIZE (128 * 4U) +#define HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (36U) +#define HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (68U) +#define HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (68U) +#define HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) +#define HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (19U) +#define HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) +#define HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (19U) +#define HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) +#define HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) +#define HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE (12U) +#define HW_SCE_RSA1024_NE_KEY_BYTE_SIZE (144U) +#define HW_SCE_RSA1024_ND_KEY_BYTE_SIZE (256U) +#define HW_SCE_RSA2048_NE_KEY_BYTE_SIZE (272U) +#define HW_SCE_RSA2048_ND_KEY_BYTE_SIZE (512U) +#define HW_SCE_RSA3072_NE_KEY_BYTE_SIZE (96 * 4 + 16U) +#define HW_SCE_RSA3072_ND_KEY_BYTE_SIZE (192 * 4U) +#define HW_SCE_RSA4096_NE_KEY_BYTE_SIZE (128 * 4 + 16U) +#define HW_SCE_RSA4096_ND_KEY_BYTE_SIZE (256 * 4U) +#define HW_SCE_RSA1024_NE_KEY_INDEX_WORD_SIZE (73U) +#define HW_SCE_RSA1024_ND_KEY_INDEX_WORD_SIZE (101U) +#define HW_SCE_RSA2048_NE_KEY_INDEX_WORD_SIZE (137U) +#define HW_SCE_RSA2048_ND_KEY_INDEX_WORD_SIZE (197U) +#define HW_SCE_RSA3072_NE_KEY_INDEX_WORD_SIZE (137U) +#define HW_SCE_RSA3072_ND_KEY_INDEX_WORD_SIZE (197U) +#define HW_SCE_RSA4096_NE_KEY_INDEX_WORD_SIZE (137U) +#define HW_SCE_RSA4096_ND_KEY_INDEX_WORD_SIZE (197U) +#define HW_SCE_RSA1024_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (76U) +#define HW_SCE_RSA1024_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (104U) +#define HW_SCE_RSA2048_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (140U) +#define HW_SCE_RSA2048_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (200U) +//#define HW_SCE_RSA3072_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (140U) +//#define HW_SCE_RSA3072_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (200U) +//#define HW_SCE_RSA4096_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (140U) +//#define HW_SCE_RSA4096_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (200U) +#define HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE (11U) +#define HW_SCE_RSA_1024_DATA_BYTE_SIZE (128U) +#define HW_SCE_RSA_2048_DATA_BYTE_SIZE (256U) +#define HW_SCE_RSA_3072_DATA_BYTE_SIZE (96 * 4U) +#define HW_SCE_RSA_4096_DATA_BYTE_SIZE (128 * 4U) + +/* RSA HASH type. */ +#define HW_SCE_RSA_HASH_MD5 (0x01) /* MD5 */ +#define HW_SCE_RSA_HASH_SHA1 (0x02) /* SHA-1 */ +#define HW_SCE_RSA_HASH_SHA256 (0x03) /* SHA-256 */ + +/* For ECC operation. */ +//#define HW_SCE_ECC_KEY_LENGTH_BYTE_SIZE (32U) +//#define HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (4U) +//#define HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (4U) +//#define HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (4U) +//#define HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (12U) +//#define HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE (64U) +//#define HW_SCE_ECC_P384_PUBLIC_KEY_BYTE_SIZE (96U) +//#define HW_SCE_ECC_PRIVATE_KEY_BYTE_SIZE (32U) +//#define HW_SCE_ECC_P384_PRIVATE_KEY_BYTE_SIZE (48U) +//#define HW_SCE_ECDSA_DATA_BYTE_SIZE (64U) +//#define HW_SCE_ECDSA_P384_DATA_BYTE_SIZE (96U) +//#define HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE (16U) +//#define HW_SCE_ALGORITHM_ID_ENCODED_DATA_BYTE_SIZE (7U) +#define HW_SCE_ECC_KEY_LENGTH_BYTE_SIZE (112U) +#define HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO_WORD_SIZE (4U) +#define HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO_WORD_SIZE (20U) +#define HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE (64U) +#define HW_SCE_ECC_P384_PUBLIC_KEY_BYTE_SIZE (96U) +#define HW_SCE_ECC_PRIVATE_KEY_BYTE_SIZE (32U) +#define HW_SCE_ECC_P384_PRIVATE_KEY_BYTE_SIZE (48U) +#define HW_SCE_ECDSA_DATA_BYTE_SIZE (64U) +#define HW_SCE_ECDSA_P384_DATA_BYTE_SIZE (96U) +#define HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE (16U) +#define HW_SCE_ALGORITHM_ID_ENCODED_DATA_BYTE_SIZE (7U) + +/* For KeyWrap. */ +#define HW_SCE_KEYWRAP_AES128 (0U) +#define HW_SCE_KEYWRAP_AES256 (2U) + +/* For TLS. */ +#define HW_SCE_TLS_RSA_NE_KEY_BYTE_SIZE (272U) +#define HW_SCE_TLS_RSA_NE_KEY_INDEX_WORD_SIZE (140U) +#define HW_SCE_TLS_ROOT_PUBLIC_KEY_WORD_SIZE (140U) +#define HW_SCE_TLS_P256_ECC_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_EPHEMERAL_ECDH_PUBLIC_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_MASTER_SECRET_WORD_SIZE (20U) +#define HW_SCE_TLS_GENERATE_MAC_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_GENERATE_AES128_CRYPTO_KEY_WORD_SIZE (12U) +#define HW_SCE_TLS_GENERATE_AES256_CRYPTO_KEY_WORD_SIZE (16U) +#define HW_SCE_TLS_GENERATE_VERIFY_DATA_BYTE_SIZE (12U) +#define HW_SCE_TLS_RSA_WITH_AES_128_CBC_SHA (0U) +#define HW_SCE_TLS_RSA_WITH_AES_256_CBC_SHA (1U) +#define HW_SCE_TLS_RSA_WITH_AES_128_CBC_SHA256 (2U) +#define HW_SCE_TLS_RSA_WITH_AES_256_CBC_SHA256 (3U) +#define HW_SCE_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 (4U) +#define HW_SCE_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 (5U) +#define HW_SCE_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 (6U) +#define HW_SCE_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (7U) +#define HW_SCE_TLS_GENERATE_CLIENT_VERIFY (0U) +#define HW_SCE_TLS_GENERATE_SERVER_VERIFY (1U) +#define HW_SCE_TLS_PUBLIC_KEY_TYPE_RSA2048 (0U) +#define HW_SCE_TLS_PUBLIC_KEY_TYPE_ECDSA_P256 (2U) + +/* TLS-HMAC. */ +#define HW_SCE_TLS_HMAC_KEY_INDEX_BYTE_SIZE (64U) +#define HW_SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE (16U) + +/* TLS-AES. */ +#define HW_SCE_TLS_AES128_KEY_INDEX_WORD_SIZE (12U) +#define HW_SCE_TLS_AES256_KEY_INDEX_WORD_SIZE (16U) + +/* Key update. */ +#define HW_SCE_UPDATE_KEY_RING_INDEX_WORD_SIZE (16U) + +/* Firmware update. */ +#define HW_SCE_FIRMWARE_MAC_BYTE_SIZE (16U) +#if defined BSP_MCU_RX231 || defined BSP_MCU_RX23W +#define HW_SCE_SECURE_BOOT_AREA_TOP (0xFFFF8000) +#else +#define HW_SCE_SECURE_BOOT_AREA_TOP (0xFFFF0000) +#endif /* defined BSP_MCU_RX231 || defined BSP_MCU_RX23W */ + +#define SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD (0) +#define SCE_OEM_KEY_SIZE_AES128_INST_DATA_WORD (8) +#define SCE_OEM_KEY_SIZE_AES192_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_AES256_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_AES128_XTS_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_AES256_XTS_INST_DATA_WORD (20) + +#define SCE_OEM_KEY_SIZE_RSA1024_PUBLICK_KEY_INST_DATA_WORD (40) +#define SCE_OEM_KEY_SIZE_RSA1024_PRIVATE_KEY_INST_DATA_WORD (68) +#define SCE_OEM_KEY_SIZE_RSA2048_PUBLICK_KEY_INST_DATA_WORD (72) +#define SCE_OEM_KEY_SIZE_RSA2048_PRIVATE_KEY_INST_DATA_WORD (132) +#define SCE_OEM_KEY_SIZE_RSA3072_PUBLICK_KEY_INST_DATA_WORD (104) +#define SCE_OEM_KEY_SIZE_RSA3072_PRIVATE_KEY_INST_DATA_WORD (196) +#define SCE_OEM_KEY_SIZE_RSA4096_PUBLICK_KEY_INST_DATA_WORD (136) +#define SCE_OEM_KEY_SIZE_RSA4096_PRIVATE_KEY_INST_DATA_WORD (260) + +#define SCE_OEM_KEY_SIZE_ECCP192_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP192_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP224_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP224_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP256_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP256_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP384_PUBLICK_KEY_INST_DATA_WORD (28) +#define SCE_OEM_KEY_SIZE_ECCP384_PRIVATE_KEY_INST_DATA_WORD (16) +#define SCE_OEM_KEY_SIZE_HMAC_SHA224_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_HMAC_SHA256_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP256R1_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCP256R1_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP384R1_PUBLICK_KEY_INST_DATA_WORD (28) +#define SCE_OEM_KEY_SIZE_ECCP384R1_PRIVATE_KEY_INST_DATA_WORD (16) +#define SCE_OEM_KEY_SIZE_ECCP512R1_PUBLICK_KEY_INST_DATA_WORD (36) +#define SCE_OEM_KEY_SIZE_ECCP512R1_PRIVATE_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCSECP256K1_PUBLICK_KEY_INST_DATA_WORD (20) +#define SCE_OEM_KEY_SIZE_ECCSECP256K1_PRIVATE_KEY_INST_DATA_WORD (12) +#define SCE_OEM_KEY_SIZE_ECCP521_PUBLICK_KEY_INST_DATA_WORD (44) +#define SCE_OEM_KEY_SIZE_ECCP521_PRIVATE_KEY_INST_DATA_WORD (24) + +/********************************************************************************************************************** + External global variables + *********************************************************************************************************************/ +extern uint32_t const S_FLASH2[]; +extern uint32_t S_INST[HW_SCE_SINST_WORD_SIZE]; +extern uint32_t S_INST2[HW_SCE_SINST2_WORD_SIZE]; +extern uint32_t S_RAM[HW_SCE_SRAM_WORD_SIZE]; +extern uint32_t S_HEAP[HW_SCE_SHEAP_WORD_SIZE]; + + +extern uint32_t INST_DATA_SIZE; +extern uint32_t KEY_INDEX_SIZE; + + /* OEM Command */ + typedef enum e_sce_oem_cmd + { + SCE_OEM_CMD_AES128 = 5, + SCE_OEM_CMD_AES192, + SCE_OEM_CMD_AES256, + SCE_OEM_CMD_AES128_XTS, + SCE_OEM_CMD_AES256_XTS, + SCE_OEM_CMD_RSA1024_PUBLIC, + SCE_OEM_CMD_RSA1024_PRIVATE, + SCE_OEM_CMD_RSA2048_PUBLIC, + SCE_OEM_CMD_RSA2048_PRIVATE, + SCE_OEM_CMD_RSA3072_PUBLIC, + SCE_OEM_CMD_RSA3072_PRIVATE, + SCE_OEM_CMD_RSA4096_PUBLIC, + SCE_OEM_CMD_RSA4096_PRIVATE, + SCE_OEM_CMD_ECC_P192_PUBLIC, + SCE_OEM_CMD_ECC_P192_PRIVATE, + SCE_OEM_CMD_ECC_P224_PUBLIC, + SCE_OEM_CMD_ECC_P224_PRIVATE, + SCE_OEM_CMD_ECC_P256_PUBLIC, + SCE_OEM_CMD_ECC_P256_PRIVATE, + SCE_OEM_CMD_ECC_P384_PUBLIC, + SCE_OEM_CMD_ECC_P384_PRIVATE, + SCE_OEM_CMD_HMAC_SHA224, + SCE_OEM_CMD_HMAC_SHA256, + SCE_OEM_CMD_ECC_P256R1_PUBLIC, + SCE_OEM_CMD_ECC_P256R1_PRIVATE, + SCE_OEM_CMD_ECC_P384R1_PUBLIC, + SCE_OEM_CMD_ECC_P384R1_PRIVATE, + SCE_OEM_CMD_ECC_P512R1_PUBLIC, + SCE_OEM_CMD_ECC_P512R1_PRIVATE, + SCE_OEM_CMD_ECC_SECP256K1_PUBLIC, + SCE_OEM_CMD_ECC_SECP256K1_PRIVATE, + SCE_OEM_CMD_ECC_P521_PUBLIC, + SCE_OEM_CMD_ECC_P521_PRIVATE, + SCE_OEM_CMD_ED25519_PUBLIC, + SCE_OEM_CMD_ED25519_PRIVATE, + SCE_OEM_CMD_RSA2048_PUBLIC_FOR_TLS = 254, + SCE_OEM_CMD_NUM + } sce_oem_cmd_t; + +/* --------------------- SCE control procedure related ---------------------- */ +void HW_SCE_p_func008(void); +void HW_SCE_p_func027(uint32_t ARG1); +void HW_SCE_p_func028(uint32_t ARG1); +void HW_SCE_p_func031(const uint32_t ARG1[]); +void HW_SCE_p_func043(void); +void HW_SCE_p_func044(void); +void HW_SCE_p_func048(const uint32_t ARG1[]); +void HW_SCE_p_func049(const uint32_t ARG1[]); +void HW_SCE_p_func057(const uint32_t ARG1[], const uint32_t ARG2[], uint32_t ARG3[]); +void HW_SCE_p_func058(const uint32_t ARG1[], uint32_t ARG2); +void HW_SCE_p_func059(void); +void HW_SCE_p_func060(void); +void HW_SCE_p_func061(const uint32_t ARG1, const uint32_t ARG2[]); +void HW_SCE_p_func062(const uint32_t ARG1, uint32_t ARG2[]); +void HW_SCE_p_func063(const uint32_t ARG1, const uint32_t ARG2[]); +void HW_SCE_p_func065(const uint32_t ARG1, uint32_t ARG2[]); +void HW_SCE_p_func066(void); +void HW_SCE_p_func068(void); +void HW_SCE_p_func070(uint32_t ARG1); +void HW_SCE_p_func071(uint32_t ARG1); +void HW_SCE_p_func073(uint32_t ARG1); +void HW_SCE_p_func074(void); +void HW_SCE_p_func075(void); +void HW_SCE_p_func076(void); +void HW_SCE_p_func077(void); +void HW_SCE_p_func078(uint32_t ARG1); +void HW_SCE_p_func079(uint32_t ARG1); +void HW_SCE_p_func081(void); +void HW_SCE_p_func082(void); +void HW_SCE_p_func086(uint32_t ARG1); +void HW_SCE_p_func087(uint32_t ARG1); +void HW_SCE_p_func088(void); +void HW_SCE_p_func089(void); +void HW_SCE_p_func090(void); +void HW_SCE_p_func091(void); +void HW_SCE_p_func092(void); +void HW_SCE_p_func093(const uint32_t ARG1[], uint32_t ARG2[]); +void HW_SCE_p_func094(uint32_t ARG1, const uint32_t ARG2[]); +void HW_SCE_p_func095(uint32_t ARG1, const uint32_t ARG2[]); +void HW_SCE_p_func100(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void HW_SCE_p_func101(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void HW_SCE_p_func102(uint32_t ARG1, uint32_t ARG2, uint32_t ARG3, uint32_t ARG4); +void HW_SCE_p_func103(void); +void HW_SCE_p_func202(void); +void HW_SCE_p_func209(void); +void HW_SCE_p_func214(void); +void HW_SCE_p_func215(void); +void HW_SCE_p_func216(void); +void HW_SCE_SoftwareResetSub (void); +void HW_SCE_Aes128GcmEncryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT); +void HW_SCE_Aes128GcmEncryptUpdateTransitionSub (void); +void HW_SCE_Aes128GcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +void HW_SCE_Aes128GcmDecryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT); +void HW_SCE_Aes128GcmDecryptUpdateTransitionSub (void); +void HW_SCE_Aes128GcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +void HW_SCE_Aes192GcmDecryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT); +void HW_SCE_Aes192GcmDecryptUpdateTransitionSub (void); +void HW_SCE_Aes192GcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +void HW_SCE_Aes256GcmEncryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT); +void HW_SCE_Aes256GcmEncryptUpdateTransitionSub (void); +void HW_SCE_Aes256GcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +void HW_SCE_Aes256GcmDecryptUpdateAADSub (const uint32_t InData_DataA[], const uint32_t MAX_CNT); +void HW_SCE_Aes256GcmDecryptUpdateTransitionSub (void); +void HW_SCE_Aes256GcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +void HW_SCE_Aes128EncryptDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +void HW_SCE_Aes256EncryptDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +void HW_SCE_Aes192GcmEncryptUpdateTransitionSub (void); +void HW_SCE_Aes128CcmEncryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +void HW_SCE_Aes128CcmDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GcmEncryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_DataALen[], uint32_t OutData_Text[], uint32_t OutData_DataT[]); +fsp_err_t HW_SCE_Aes128GcmEncryptInitSub(const uint32_t InData_KeyType[], const uint32_t InData_DataType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[], const uint32_t InData_SeqNum[]); +fsp_err_t HW_SCE_Aes128GcmDecryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_DataALen[], const uint32_t InData_DataT[], const uint32_t InData_DataTLen[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Aes128GcmDecryptInitSub(const uint32_t InData_KeyType[], const uint32_t InData_DataType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[], const uint32_t InData_SeqNum[]); +fsp_err_t HW_SCE_Aes192GcmDecryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_DataALen[], const uint32_t InData_DataT[], const uint32_t InData_DataTLen[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Aes192GcmDecryptInitSub(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes256GcmEncryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_DataALen[], uint32_t OutData_Text[], uint32_t OutData_DataT[]); +fsp_err_t HW_SCE_Aes256GcmEncryptInitSub(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes256GcmDecryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_DataALen[], const uint32_t InData_DataT[], const uint32_t InData_DataTLen[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Aes256GcmDecryptInitSub(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +fsp_err_t HW_SCE_LoadHukSub(const uint32_t InData_LC[]); +fsp_err_t HW_SCE_Aes128CmacFinalSub(const uint32_t InData_Cmd[], const uint32_t InData_Text[], const uint32_t InData_DataT[], const uint32_t InData_DataTLen[], uint32_t OutData_DataT[]); +fsp_err_t HW_SCE_Aes128CmacInitSub(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]); +void HW_SCE_Aes128CmacUpdateSub(const uint32_t InData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CmacFinalSub(const uint32_t InData_Cmd[], const uint32_t InData_Text[], const uint32_t InData_DataT[], const uint32_t InData_DataTLen[], uint32_t OutData_DataT[]); +fsp_err_t HW_SCE_Aes256CmacInitSub(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[]); +void HW_SCE_Aes256CmacUpdateSub(const uint32_t InData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128EncryptDecryptFinalSub(void); +fsp_err_t HW_SCE_Aes128EncryptDecryptInitSub (const uint32_t InData_KeyType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +fsp_err_t HW_SCE_Aes256EncryptDecryptFinalSub(void); +fsp_err_t HW_SCE_Aes256EncryptDecryptInitSub (const uint32_t InData_KeyType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +fsp_err_t HW_SCE_GenerateRandomNumberSub (uint32_t OutData_Text[]); +fsp_err_t HW_SCE_GenerateOemKeyIndexSub (const uint32_t InData_KeyType[], const uint32_t InData_Cmd[], const uint32_t InData_SharedKeyIndex[], const uint32_t InData_SessionKey[], const uint32_t InData_IV[], const uint32_t InData_InstData[], uint32_t OutData_KeyIndex[]); +fsp_err_t HW_SCE_OemKeyIndexValidationSub (const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[]); +fsp_err_t HW_SCE_SelfCheck1Sub(void); +fsp_err_t HW_SCE_SelfCheck2Sub(void); +void HW_SCE_Aes192GcmEncryptUpdateAADSub(const uint32_t InData_DataA[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192GcmEncryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_DataALen[], uint32_t OutData_Text[], uint32_t OutData_DataT[]); +fsp_err_t HW_SCE_Aes192GcmEncryptInitSub(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void HW_SCE_Aes192GcmEncryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192CmacFinalSub(const uint32_t InData_Cmd[], const uint32_t InData_Text[], const uint32_t InData_DataT[], const uint32_t InData_DataTLen[], uint32_t OutData_DataT[]); +fsp_err_t HW_SCE_Aes192CmacInitSub(const uint32_t InData_KeyIndex[]); +void HW_SCE_Aes192CmacUpdateSub(const uint32_t InData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192EncryptDecryptFinalSub(void); +fsp_err_t HW_SCE_Aes192EncryptDecryptInitSub (const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void HW_SCE_Aes192EncryptDecryptUpdateSub (const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128CcmEncryptFinalSub(const uint32_t InData_Text[], uint32_t OutData_Text[], uint32_t OutData_MAC[]); +fsp_err_t HW_SCE_Aes128CcmEncryptInitSub(const uint32_t InData_KeyType[], const uint32_t InData_DataType[], const uint32_t InData_Cmd[], const uint32_t InData_TextLen[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[], const uint32_t InData_Header[], const uint32_t InData_SeqNum[], const uint32_t Header_Len); +fsp_err_t HW_SCE_Aes128CcmDecryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_MAC[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Aes128CcmDecryptInitSub(const uint32_t InData_KeyType[], const uint32_t InData_DataType[], const uint32_t InData_Cmd[], const uint32_t InData_TextLen[], const uint32_t InData_MACLength[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[], const uint32_t InData_Header[], const uint32_t InData_SeqNum[], const uint32_t Header_Len); +fsp_err_t HW_SCE_Aes256CcmEncryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], uint32_t OutData_Text[], uint32_t OutData_MAC[]); +fsp_err_t HW_SCE_Aes256CcmEncryptInitSub(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[], const uint32_t InData_Header[], const uint32_t Header_Len); +void HW_SCE_Aes256CcmEncryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256CcmDecryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_MAC[], const uint32_t InData_MACLength[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Aes256CcmDecryptInitSub(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[], const uint32_t InData_Header[], const uint32_t Header_Len); +void HW_SCE_Aes256CcmDecryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192CcmEncryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], uint32_t OutData_Text[], uint32_t OutData_MAC[]); +fsp_err_t HW_SCE_Aes192CcmEncryptInitSub(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[], const uint32_t InData_Header[], const uint32_t Header_Len); +void HW_SCE_Aes192CcmEncryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192CcmDecryptFinalSub(const uint32_t InData_Text[], const uint32_t InData_TextLen[], const uint32_t InData_MAC[], const uint32_t InData_MACLength[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Aes192CcmDecryptInitSub(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[], const uint32_t InData_Header[], const uint32_t Header_Len); +void HW_SCE_Aes192CcmDecryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128XtsEncryptFinalSub(const uint32_t InData_TextBitLen[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Aes128XtsEncryptInitSub(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void HW_SCE_Aes128XtsEncryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128XtsDecryptFinalSub(const uint32_t InData_TextBitLen[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Aes128XtsDecryptInitSub(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void HW_SCE_Aes128XtsDecryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256XtsEncryptFinalSub(const uint32_t InData_TextBitLen[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Aes256XtsEncryptInitSub(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void HW_SCE_Aes256XtsEncryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256XtsDecryptFinalSub(const uint32_t InData_TextBitLen[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Aes256XtsDecryptInitSub(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void HW_SCE_Aes256XtsDecryptUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes128GctrFinalSub(void); +fsp_err_t HW_SCE_Aes128GctrInitSub(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void HW_SCE_Aes128GctrUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes256GctrFinalSub(void); +fsp_err_t HW_SCE_Aes256GctrInitSub(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void HW_SCE_Aes256GctrUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Aes192GctrFinalSub(void); +fsp_err_t HW_SCE_Aes192GctrInitSub(const uint32_t InData_KeyIndex[], const uint32_t InData_IV[]); +void HW_SCE_Aes192GctrUpdateSub(const uint32_t InData_Text[], uint32_t OutData_Text[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_GhashSub (const uint32_t InData_HV[], const uint32_t InData_IV[], const uint32_t InData_Text[], uint32_t OutData_DataT[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_ShaGenerateMessageDigestSub (const uint32_t InData_HashType[], const uint32_t InData_Cmd[], const uint32_t InData_Msg[], const uint32_t InData_MsgLen[], const uint32_t InData_State[], uint32_t OutData_MsgDigest[], uint32_t OutData_State[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_GenerateAes128RandomKeyIndexSub (uint32_t OutData_KeyIndex[]); +fsp_err_t HW_SCE_GenerateAes192RandomKeyIndexSub (uint32_t OutData_KeyIndex[]); +fsp_err_t HW_SCE_GenerateAes256RandomKeyIndexSub (uint32_t OutData_KeyIndex[]); +fsp_err_t HW_SCE_GenerateAes128XtsRandomKeyIndexSub (uint32_t OutData_KeyIndex[]); +fsp_err_t HW_SCE_GenerateAes256XtsRandomKeyIndexSub (uint32_t OutData_KeyIndex[]); +fsp_err_t HW_SCE_Rsa1024ModularExponentEncryptSub(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Rsa1024ModularExponentDecryptSub(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Rsa2048ModularExponentEncryptSub(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Rsa2048ModularExponentDecryptSub(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Rsa3072ModularExponentEncryptSub(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Rsa3072ModularExponentDecryptSub(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Rsa4096ModularExponentEncryptSub(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_Rsa4096ModularExponentDecryptSub(const uint32_t InData_KeyIndex[], const uint32_t InData_Text[], uint32_t OutData_Text[]); +fsp_err_t HW_SCE_EcdsaSignatureGenerateSub(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_MsgDgst[], uint32_t OutData_Signature[]); +fsp_err_t HW_SCE_EcdsaSignatureVerificationSub(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_MsgDgst[], const uint32_t InData_Signature[]); +fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSub(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], const uint32_t InData_KeyIndex[], const uint32_t InData_PubKey[], uint32_t OutData_R[]); +fsp_err_t HW_SCE_EcdsaP384SignatureGenerateSub(const uint32_t InData_CurveType[], const uint32_t InData_KeyIndex[], const uint32_t InData_MsgDgst[], uint32_t OutData_Signature[]); +fsp_err_t HW_SCE_EcdsaP384SignatureVerificationSub(const uint32_t InData_CurveType[], const uint32_t InData_KeyIndex[], const uint32_t InData_MsgDgst[], const uint32_t InData_Signature[]); +fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSub(const uint32_t InData_CurveType[], const uint32_t InData_KeyIndex[], const uint32_t InData_PubKey[], uint32_t OutData_R[]); +fsp_err_t HW_SCE_EcdsaP512SignatureGenerateSub(const uint32_t InData_KeyIndex[], const uint32_t InData_MsgDgst[], uint32_t OutData_Signature[]); +fsp_err_t HW_SCE_EcdsaP512SignatureVerificationSub(const uint32_t InData_KeyIndex[], const uint32_t InData_MsgDgst[], const uint32_t InData_Signature[]); +fsp_err_t HW_SCE_Ecc512ScalarMultiplicationSub(const uint32_t InData_KeyIndex[], const uint32_t InData_PubKey[], uint32_t OutData_R[]); +fsp_err_t HW_SCE_EcdsaP521SignatureGenerateSub(const uint32_t InData_KeyIndex[], const uint32_t InData_MsgDgst[], uint32_t OutData_Signature[]); +fsp_err_t HW_SCE_EcdsaP521SignatureVerificationSub(const uint32_t InData_KeyIndex[], const uint32_t InData_MsgDgst[], const uint32_t InData_Signature[]); +fsp_err_t HW_SCE_Ecc521ScalarMultiplicationSub(const uint32_t InData_KeyIndex[], const uint32_t InData_PubKey[], uint32_t OutData_R[]); +fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub(const uint32_t InData_CurveType[], const uint32_t InData_Cmd[], uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSub(const uint32_t InData_CurveType[], uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +fsp_err_t HW_SCE_GenerateEccP512RandomKeyIndexSub(uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +fsp_err_t HW_SCE_GenerateEccP521RandomKeyIndexSub(uint32_t OutData_PubKeyIndex[], uint32_t OutData_PrivKeyIndex[]); +fsp_err_t HW_SCE_Sha256HmacInitSub(const uint32_t InData_KeyType[], const uint32_t InData_KeyIndex[], const uint32_t InData_Cmd[], const uint32_t InData_MsgLen[]); +void HW_SCE_Sha256HmacUpdateSub(const uint32_t InData_Msg[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Sha256HmacFinalSub(const uint32_t InData_Cmd[], const uint32_t InData_MAC[], const uint32_t InData_MACLength[], uint32_t OutData_MAC[]); +fsp_err_t HW_SCE_Sha224HmacInitSub(const uint32_t InData_KeyIndex[], const uint32_t InData_MsgLen[]); +void HW_SCE_Sha224HmacUpdateSub(const uint32_t InData_Msg[], const uint32_t MAX_CNT); +fsp_err_t HW_SCE_Sha224HmacFinalSub (const uint32_t InData_Cmd[], const uint32_t InData_MAC[], const uint32_t InData_MACLength[], uint32_t OutData_MAC[]); +fsp_err_t HW_SCE_IntegrityCheckSub(const uint32_t InData_Data[], const uint32_t InData_DataLen[], const uint32_t InData_MAC[], const uint32_t MAX_CNT); + +uint32_t change_endian_long (uint32_t data); + +#endif /* HW_SCE_RA_PRIVATE_HEADER_FILE */ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/public/inc/r_sce_if.h b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/public/inc/r_sce_if.h new file mode 100644 index 000000000..af3d6a78b --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/rsip7/plainkey/public/inc/r_sce_if.h @@ -0,0 +1,1596 @@ +/********************************************************************************************************************** + * DISCLAIMER + * This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No + * other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all + * applicable laws, including copyright laws. + * THIS SOFTWARE IS PROVIDED "AS IS" AND RENESAS MAKES NO WARRANTIES REGARDING + * THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, + * FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM + * EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES + * SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO + * THIS SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. + * Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of + * this software. By using this software, you agree to the additional terms and conditions found by accessing the + * following link: + * http://www.renesas.com/disclaimer + * + * Copyright (C) 2015-2020 Renesas Electronics Corporation. All rights reserved. + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * File Name : r_sce_if.h + * Version : 1.09 + * Description : Interface definition for the r_sce module. + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Includes , "Project Includes" + *********************************************************************************************************************/ + +// added for RA6M4 start +// #include "platform.h" +#include "bsp_api.h" +#include "hw_sce_ra_private.h" + +// added for RA6M4 end + +/********************************************************************************************************************** + * Macro definitions + *********************************************************************************************************************/ + +#ifndef R_SCE_IF_HEADER_FILE + #define R_SCE_IF_HEADER_FILE + +// added for RA6M4 start + #if 0 + +// added for RA6M4 end + + #if R_BSP_VERSION_MAJOR < 5 + #error "This module must use BSP module of Rev.5.00 or higher. Please use the BSP module of Rev.5.00 or higher." + #endif + #if (defined BSP_MCU_RX231 || defined BSP_MCU_RX23W) && (BSP_CFG_MCU_PART_VERSION == 0xB) /* B */ + #elif (defined BSP_MCU_RX66T || defined BSP_MCU_RX72T) && ((BSP_CFG_MCU_PART_FUNCTION == 0xE /* E */) || \ + (BSP_CFG_MCU_PART_FUNCTION == 0xF /* F */) || (BSP_CFG_MCU_PART_FUNCTION == 0x10 /* G */)) + #elif (defined BSP_MCU_RX65N || defined BSP_MCU_RX651) && (BSP_CFG_MCU_PART_ENCRYPTION_INCLUDED == true) + #elif (defined BSP_MCU_RX72M || defined BSP_MCU_RX72N || defined BSP_MCU_RX66N) && \ + (BSP_CFG_MCU_PART_FUNCTION == 0x11 /* H */) + #else + #error "Your MCU does not support SCE functions. Please confirm BSP_MCU_xxx macro in r_bsp_config.h." + #endif /* defined BSP_MCU_RX231 || defined BSP_MCU_RX23W && BSP_CFG_MCU_PART_VERSION == 0xB */ + +// added for RA6M4 start + #endif + +// added for RA6M4 end + +/* Version Number of API. */ + #define SCE_VERSION_MAJOR (1U) + #define SCE_VERSION_MINOR (9U) + +/* Various information. */ + #define HW_SCE_SRAM_WORD_SIZE (32U) + #define HW_SCE_SINST_WORD_SIZE (140U) + #define HW_SCE_SINST2_WORD_SIZE (16U) + #define HW_SCE_SHEAP_WORD_SIZE (1504U) + #define HW_SCE_MAC_SIZE (16U) + +/* For AES operation. */ + #define HW_SCE_AES128XTS_KEY_INDEX_WORD_SIZE (13U) + #define HW_SCE_AES256XTS_KEY_INDEX_WORD_SIZE (21U) + #define HW_SCE_AES128_KEY_WORD_SIZE (4U) + #define HW_SCE_AES192_KEY_WORD_SIZE (8U) + #define HW_SCE_AES256_KEY_WORD_SIZE (8U) + #define HW_SCE_AES128_KEY_BYTE_SIZE (16U) + #define HW_SCE_AES192_KEY_BYTE_SIZE (32U) + #define HW_SCE_AES256_KEY_BYTE_SIZE (32U) + #define HW_SCE_AES_BLOCK_BYTE_SIZE (16U) + #define HW_SCE_AES_BLOCK_BIT_SIZE (128U) + #define HW_SCE_AES_CBC_IV_BYTE_SIZE (16U) + #define HW_SCE_AES_CTR_ICOUNTER_BYTE_SIZE (16U) + #define HW_SCE_AES_GCM_AAD_BLOCK_BYTE_SIZE (16U) + #define HW_SCE_AES_CCM_B_FORMAT_BYTE_SIZE (128U) + #define HW_SCE_AES_CCM_COUNTER_BYTE_SIZE (16U) + #define HW_SCE_AES128XTS_KEY_BYTE_SIZE (32U) + #define HW_SCE_AES256XTS_KEY_BYTE_SIZE (64U) + #define HW_SCE_AES_XTS_IV_BYTE_SIZE (16U) + +/* For TDES operation. */ + #define HW_SCE_TDES_KEY_INDEX_WORD_SIZE (16U) + #define HW_SCE_TDES_BLOCK_BYTE_SIZE (8U) + #define HW_SCE_TDES_CBC_IV_BYTE_SIZE (8U) + #define HW_SCE_TDES_KEY_WORD_SIZE (8U) + #define HW_SCE_TDES_KEY_BYTE_SIZE (32U) + +/* For ARC4 operation. */ + #define HW_SCE_ARC4_KEY_INDEX_WORD_SIZE (72U) + #define HW_SCE_ARC4_KEY_WORD_SIZE (64U) + #define HW_SCE_ARC4_KEY_BYTE_SIZE (256U) + #define HW_SCE_ARC4_BLOCK_BYTE_SIZE (16U) + +/* For SHA operation. */ + #define HW_SCE_SHA1_HASH_LENGTH_BYTE_SIZE (20U) + #define HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE (32U) + #define HW_SCE_SHA384_HASH_LENGTH_BYTE_SIZE (48U) + +/* For MD5 operation. */ + #define HW_SCE_MD5_HASH_LENGTH_BYTE_SIZE (16U) + +/* For HMAC operation. */ + #define HW_SCE_HMAC_KEY_BYTE_SIZE (32U) + +/* For RSA operation. */ + #define HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE (128U) + #define HW_SCE_RSA_1024_KEY_E_LENGTH_BYTE_SIZE (4U) + #define HW_SCE_RSA_1024_KEY_D_LENGTH_BYTE_SIZE (128U) + #define HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE (256U) + #define HW_SCE_RSA_2048_KEY_E_LENGTH_BYTE_SIZE (4U) + #define HW_SCE_RSA_2048_KEY_D_LENGTH_BYTE_SIZE (256U) + #define HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE (96 * 4U) + #define HW_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE (4U) + #define HW_SCE_RSA_3072_KEY_D_LENGTH_BYTE_SIZE (96 * 4U) + #define HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE (128 * 4U) + #define HW_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE (4U) + #define HW_SCE_RSA_4096_KEY_D_LENGTH_BYTE_SIZE (128 * 4U) + #define HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (36U) + #define HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (68U) + #define HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (68U) + #define HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) + #define HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) + #define HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (132U) + #define HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE (12U) + #define HW_SCE_RSA1024_NE_KEY_BYTE_SIZE (144U) + #define HW_SCE_RSA1024_ND_KEY_BYTE_SIZE (256U) + #define HW_SCE_RSA2048_NE_KEY_BYTE_SIZE (272U) + #define HW_SCE_RSA2048_ND_KEY_BYTE_SIZE (512U) + #define HW_SCE_RSA3072_NE_KEY_BYTE_SIZE (96 * 4 + 16U) + #define HW_SCE_RSA3072_ND_KEY_BYTE_SIZE (192 * 4U) + #define HW_SCE_RSA4096_NE_KEY_BYTE_SIZE (128 * 4 + 16U) + #define HW_SCE_RSA4096_ND_KEY_BYTE_SIZE (256 * 4U) + #define HW_SCE_RSA1024_NE_KEY_INDEX_WORD_SIZE (73U) + #define HW_SCE_RSA1024_ND_KEY_INDEX_WORD_SIZE (101U) + #define HW_SCE_RSA2048_NE_KEY_INDEX_WORD_SIZE (137U) + #define HW_SCE_RSA2048_ND_KEY_INDEX_WORD_SIZE (197U) + #define HW_SCE_RSA3072_ND_KEY_INDEX_WORD_SIZE (197U) + #define HW_SCE_RSA4096_NE_KEY_INDEX_WORD_SIZE (137U) + +// #define HW_SCE_RSA3072_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (140U) +// #define HW_SCE_RSA3072_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (200U) +// #define HW_SCE_RSA4096_RANDOM_PUBLIC_KEY_INDEX_WORD_SIZE (140U) +// #define HW_SCE_RSA4096_RANDOM_PRIVATE_KEY_INDEX_WORD_SIZE (200U) + #define HW_SCE_RSA_RSAES_PKCS_MIN_KEY_N_BYTE_SIZE (11U) + #define HW_SCE_RSA_1024_DATA_BYTE_SIZE (128U) + #define HW_SCE_RSA_2048_DATA_BYTE_SIZE (256U) + #define HW_SCE_RSA_3072_DATA_BYTE_SIZE (96 * 4U) + #define HW_SCE_RSA_4096_DATA_BYTE_SIZE (128 * 4U) + +/* RSA HASH type. */ + #define HW_SCE_RSA_HASH_MD5 (0x01) /* MD5 */ + #define HW_SCE_RSA_HASH_SHA1 (0x02) /* SHA-1 */ + #define HW_SCE_RSA_HASH_SHA256 (0x03) /* SHA-256 */ + +/* For ECC operation. */ + +// #define HW_SCE_ECC_KEY_LENGTH_BYTE_SIZE (32U) + #define HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE (1U) + #define HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE (4U) + +// #define HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE (4U) +// #define HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE (12U) +// #define HW_SCE_ECC_PUBLIC_KEY_BYTE_SIZE (64U) +// #define HW_SCE_ECC_P384_PUBLIC_KEY_BYTE_SIZE (96U) +// #define HW_SCE_ECC_PRIVATE_KEY_BYTE_SIZE (32U) +// #define HW_SCE_ECC_P384_PRIVATE_KEY_BYTE_SIZE (48U) +// #define HW_SCE_ECDSA_DATA_BYTE_SIZE (64U) +// #define HW_SCE_ECDSA_P384_DATA_BYTE_SIZE (96U) +// #define HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE (16U) +// #define HW_SCE_ALGORITHM_ID_ENCODED_DATA_BYTE_SIZE (7U) + #define HW_SCE_ECC_KEY_LENGTH_BYTE_SIZE (112U) + +// #define HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO_WORD_SIZE (1U) +// #define HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO_WORD_SIZE (17U) + #define HW_SCE_ECC_P192_P224_P256_PUBLIC_KEY_BYTE_SIZE (64U) + #define HW_SCE_ECC_P384_PUBLIC_KEY_BYTE_SIZE (96U) + #define HW_SCE_ECC_PRIVATE_KEY_BYTE_SIZE (32U) + #define HW_SCE_ECC_P384_PRIVATE_KEY_BYTE_SIZE (48U) + #define HW_SCE_ECDSA_DATA_BYTE_SIZE (64U) + #define HW_SCE_ECDSA_P384_DATA_BYTE_SIZE (96U) + +// #define HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE (13U) + #define HW_SCE_PRIVATE_KEY_WRAPPING_WORD_SIZE (5U) + #define HW_SCE_ALGORITHM_ID_ENCODED_DATA_BYTE_SIZE (7U) + +/* For KeyWrap. */ + #define HW_SCE_KEYWRAP_AES128 (0U) + #define HW_SCE_KEYWRAP_AES256 (2U) + +/* For TLS. */ + #define HW_SCE_TLS_RSA_NE_KEY_BYTE_SIZE (272U) + #define HW_SCE_TLS_RSA_NE_KEY_INDEX_WORD_SIZE (140U) + +// #define HW_SCE_TLS_ROOT_PUBLIC_KEY_WORD_SIZE (137U) + #define HW_SCE_TLS_P256_ECC_KEY_WORD_SIZE (16U) + #define HW_SCE_TLS_EPHEMERAL_ECDH_PUBLIC_KEY_WORD_SIZE (16U) + #define HW_SCE_TLS_MASTER_SECRET_WORD_SIZE (20U) + #define HW_SCE_TLS_GENERATE_MAC_KEY_WORD_SIZE (16U) + #define HW_SCE_TLS_GENERATE_AES128_CRYPTO_KEY_WORD_SIZE (12U) + #define HW_SCE_TLS_GENERATE_AES256_CRYPTO_KEY_WORD_SIZE (16U) + #define HW_SCE_TLS_GENERATE_VERIFY_DATA_BYTE_SIZE (12U) + #define HW_SCE_TLS_RSA_WITH_AES_128_CBC_SHA (0U) + #define HW_SCE_TLS_RSA_WITH_AES_256_CBC_SHA (1U) + #define HW_SCE_TLS_RSA_WITH_AES_128_CBC_SHA256 (2U) + #define HW_SCE_TLS_RSA_WITH_AES_256_CBC_SHA256 (3U) + #define HW_SCE_TLS_ECDHE_ECDSA_WITH_AES_128_CBC_SHA256 (4U) + #define HW_SCE_TLS_ECDHE_RSA_WITH_AES_128_CBC_SHA256 (5U) + #define HW_SCE_TLS_ECDHE_ECDSA_WITH_AES_128_GCM_SHA256 (6U) + #define HW_SCE_TLS_ECDHE_RSA_WITH_AES_128_GCM_SHA256 (7U) + #define HW_SCE_TLS_GENERATE_CLIENT_VERIFY (0U) + #define HW_SCE_TLS_GENERATE_SERVER_VERIFY (1U) + #define HW_SCE_TLS_PUBLIC_KEY_TYPE_RSA2048 (0U) + #define HW_SCE_TLS_PUBLIC_KEY_TYPE_ECDSA_P256 (2U) + +/* TLS-HMAC. */ + #define HW_SCE_TLS_HMAC_KEY_INDEX_BYTE_SIZE (64U) + #define HW_SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE (16U) + +/* TLS-AES. */ + #define HW_SCE_TLS_AES128_KEY_INDEX_WORD_SIZE (12U) + #define HW_SCE_TLS_AES256_KEY_INDEX_WORD_SIZE (16U) + +/* Key update. */ + #define HW_SCE_UPDATE_KEY_RING_INDEX_WORD_SIZE (16U) + +/* Firmware update. */ + #define HW_SCE_FIRMWARE_MAC_BYTE_SIZE (16U) + #if defined BSP_MCU_RX231 || defined BSP_MCU_RX23W + #define HW_SCE_SECURE_BOOT_AREA_TOP (0xFFFF8000) + #else + #define HW_SCE_SECURE_BOOT_AREA_TOP (0xFFFF0000) + #endif /* defined BSP_MCU_RX231 || defined BSP_MCU_RX23W */ + + #define SCE_OEM_KEY_SIZE_DUMMY_INST_DATA_WORD (0) + #define SCE_OEM_KEY_SIZE_AES128_INST_DATA_WORD (8) + #define SCE_OEM_KEY_SIZE_AES192_INST_DATA_WORD (12) + #define SCE_OEM_KEY_SIZE_AES256_INST_DATA_WORD (12) + #define SCE_OEM_KEY_SIZE_AES128_XTS_INST_DATA_WORD (12) + #define SCE_OEM_KEY_SIZE_AES256_XTS_INST_DATA_WORD (20) + + #define SCE_OEM_KEY_SIZE_RSA1024_PUBLICK_KEY_INST_DATA_WORD (40) + #define SCE_OEM_KEY_SIZE_RSA1024_PRIVATE_KEY_INST_DATA_WORD (68) + #define SCE_OEM_KEY_SIZE_RSA2048_PUBLICK_KEY_INST_DATA_WORD (72) + #define SCE_OEM_KEY_SIZE_RSA2048_PRIVATE_KEY_INST_DATA_WORD (132) + #define SCE_OEM_KEY_SIZE_RSA3072_PUBLICK_KEY_INST_DATA_WORD (104) + #define SCE_OEM_KEY_SIZE_RSA3072_PRIVATE_KEY_INST_DATA_WORD (196) + #define SCE_OEM_KEY_SIZE_RSA4096_PUBLICK_KEY_INST_DATA_WORD (136) + #define SCE_OEM_KEY_SIZE_RSA4096_PRIVATE_KEY_INST_DATA_WORD (260) + + #define SCE_OEM_KEY_SIZE_ECCP192_PUBLICK_KEY_INST_DATA_WORD (20) + #define SCE_OEM_KEY_SIZE_ECCP192_PRIVATE_KEY_INST_DATA_WORD (12) + #define SCE_OEM_KEY_SIZE_ECCP224_PUBLICK_KEY_INST_DATA_WORD (20) + #define SCE_OEM_KEY_SIZE_ECCP224_PRIVATE_KEY_INST_DATA_WORD (12) + #define SCE_OEM_KEY_SIZE_ECCP256_PUBLICK_KEY_INST_DATA_WORD (20) + #define SCE_OEM_KEY_SIZE_ECCP256_PRIVATE_KEY_INST_DATA_WORD (12) + #define SCE_OEM_KEY_SIZE_ECCP384_PUBLICK_KEY_INST_DATA_WORD (28) + #define SCE_OEM_KEY_SIZE_ECCP384_PRIVATE_KEY_INST_DATA_WORD (16) + #define SCE_OEM_KEY_SIZE_HMAC_SHA224_INST_DATA_WORD (12) + #define SCE_OEM_KEY_SIZE_HMAC_SHA256_INST_DATA_WORD (12) + #define SCE_OEM_KEY_SIZE_ECCP256R1_PUBLICK_KEY_INST_DATA_WORD (20) + #define SCE_OEM_KEY_SIZE_ECCP256R1_PRIVATE_KEY_INST_DATA_WORD (12) + #define SCE_OEM_KEY_SIZE_ECCP384R1_PUBLICK_KEY_INST_DATA_WORD (28) + #define SCE_OEM_KEY_SIZE_ECCP384R1_PRIVATE_KEY_INST_DATA_WORD (16) + #define SCE_OEM_KEY_SIZE_ECCP512R1_PUBLICK_KEY_INST_DATA_WORD (36) + #define SCE_OEM_KEY_SIZE_ECCP512R1_PRIVATE_KEY_INST_DATA_WORD (20) + #define SCE_OEM_KEY_SIZE_ECCSECP256K1_PUBLICK_KEY_INST_DATA_WORD (20) + #define SCE_OEM_KEY_SIZE_ECCSECP256K1_PRIVATE_KEY_INST_DATA_WORD (12) + +/********************************************************************************************************************** + * Global Typedef definitions + *********************************************************************************************************************/ + +/* request type for Callback of firmware update */ +typedef enum +{ + SCE_FW_CB_REQ_PRG_WT = 0U, + SCE_FW_CB_REQ_PRG_RD, + SCE_FW_CB_REQ_BUFF_CNT, + SCE_FW_CB_REQ_PRG_WT_LAST_BLK, + SCE_FW_CB_REQ_GET_UPDATE_PRG_CHKSUM, + SCE_FW_CB_REQ_STORE_MAC, +} SCE_FW_CB_REQ_TYPE; + +/* key index type */ +typedef enum +{ + SCE_KEY_INDEX_TYPE_INVALID = 0U, + SCE_KEY_INDEX_TYPE_AES128, + SCE_KEY_INDEX_TYPE_AES192, + SCE_KEY_INDEX_TYPE_AES256, + SCE_KEY_INDEX_TYPE_TDES, + SCE_KEY_INDEX_TYPE_HMAC_SHA1, + SCE_KEY_INDEX_TYPE_HMAC_SHA256, + SCE_KEY_INDEX_TYPE_RSA1024_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA1024_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA2048_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA2048_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA3072_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA3072_PRIVATE, + SCE_KEY_INDEX_TYPE_RSA4096_PUBLIC, + SCE_KEY_INDEX_TYPE_RSA4096_PRIVATE, + SCE_KEY_INDEX_TYPE_AES128_FOR_TLS, + SCE_KEY_INDEX_TYPE_AES192_FOR_TLS, + SCE_KEY_INDEX_TYPE_AES256_FOR_TLS, + SCE_KEY_INDEX_TYPE_HMAC_SHA1_FOR_TLS, + SCE_KEY_INDEX_TYPE_HMAC_SHA256_FOR_TLS, + SCE_KEY_INDEX_TYPE_UPDATE_KEY_RING, + SCE_KEY_INDEX_TYPE_TLS_CA_CERTIFICATION_PUBLIC_KEY, + SCE_KEY_INDEX_TYPE_TLS_P256_ECC_KEY, + SCE_KEY_INDEX_TYPE_ECC_P192_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P224_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P256_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P384_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P192_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P224_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P256_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P384_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P256R1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P384R1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_P256R1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_P384R1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PUBLIC, + SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PRIVATE, + SCE_KEY_INDEX_TYPE_ECDH_SHARED_SECRET, + SCE_KEY_INDEX_TYPE_AES128_XTS, + SCE_KEY_INDEX_TYPE_AES256_XTS, + SCE_KEY_INDEX_TYPE_AES128_GCM_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES128_KEY_WRAP_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES192_GCM_FOR_DLMS_COSEM, + SCE_KEY_INDEX_TYPE_AES192_KEY_WRAP_FOR_DLMS_COSEM, +} SCE_KEY_INDEX_TYPE; + +// added for RA6M4 start + +/* LIFE CYCLE */ +typedef enum +{ + SCE_CM1 = 0, + SCE_CM2, + SCE_SSD, + SCE_NSECSD, + SCE_DPL, + SCE_LCK_DBG, + SCE_LCK_BOOT, + SCE_RMA_REQ, + SCE_RMA_ACK, +} lifecycle_t; + +// added for RA6M4 end + +typedef enum e_sce_oem_key_type +{ + SCE_OEM_KEY_TYPE_ENCRYPTED = 0, + SCE_OEM_KEY_TYPE_PLAIN = 1 +} sce_oem_key_type_t; + +/* Byte data structure */ +typedef struct sce_byte_data +{ + uint8_t * pdata; + uint32_t data_length; + uint32_t data_type; +} sce_byte_data_t; + +/* RSA byte data structure */ +typedef sce_byte_data_t sce_rsa_byte_data_t; + +/* ECDSA byte data structure */ +typedef sce_byte_data_t sce_ecdsa_byte_data_t; + +/* AES key index data structure */ +typedef struct sce_aes_key_index +{ + uint32_t type; + + /* AES128, AES192, AES256, AES128 for TLS, AES256 for TLS, AES128 for XTS, AES256 for XTS are supported */ + uint32_t value[HW_SCE_AES256XTS_KEY_INDEX_WORD_SIZE]; +} sce_aes_key_index_t; + +/* TDES key index data structure */ +typedef struct sce_tdes_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_TDES_KEY_INDEX_WORD_SIZE]; /* DES/TDES are supported */ +} sce_tdes_key_index_t; + +/* HMAC-SHA key index data structure */ +typedef struct sce_hmac_sha_key_index +{ + uint32_t type; + + /* HMAC-SHA1, HMAC-SHA256, HMAC-SHA for TLS, HMAC-SHA256 for TLS are supported */ + uint32_t value[HW_SCE_TLS_HMAC_KEY_INDEX_WORD_SIZE]; +} sce_hmac_sha_key_index_t; + +/* RSA 1024bit public key index data structure */ +typedef struct sce_rsa1024_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_1024_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_1024_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa1024_public_key_index_t; + +/* RSA 1024bit private key index data structure */ +typedef struct sce_rsa1024_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_1024_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_1024_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa1024_private_key_index_t; + +/* RSA 2048bit public key index data structure */ +typedef struct sce_rsa2048_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_2048_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa2048_public_key_index_t; + +/* RSA 2048bit private key index data structure */ +typedef struct sce_rsa2048_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_2048_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa2048_private_key_index_t; + +/* RSA 3072bit public key index data structure */ +typedef struct sce_rsa3072_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_3072_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_3072_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa3072_public_key_index_t; + +/* RSA 3072bit private key index data structure */ +typedef struct sce_rsa3072_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_3072_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_3072_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa3072_private_key_index_t; + +/* RSA 4096bit public key index data structure */ +typedef struct sce_rsa4096_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t key_e[HW_SCE_RSA_4096_KEY_E_LENGTH_BYTE_SIZE]; /* plaintext */ + uint8_t dummy[HW_SCE_RSA_KEY_GENERATION_DUMMY_BYTE_SIZE]; /* dummy data */ + uint32_t key_management_info2[HW_SCE_RSA_4096_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa4096_public_key_index_t; + +/* RSA 4096bit private key index data structure */ +typedef struct sce_rsa4096_private_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_n[HW_SCE_RSA_4096_KEY_N_LENGTH_BYTE_SIZE]; /* plaintext */ + uint32_t key_management_info2[HW_SCE_RSA_4096_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; +} sce_rsa4096_private_key_index_t; + +/* RSA 1024bit key index pair structure */ +typedef struct sce_rsa1024_key_pair_index +{ + sce_rsa1024_private_key_index_t priv_key; + sce_rsa1024_public_key_index_t pub_key; +} sce_rsa1024_key_pair_index_t; + +/* RSA 2048bit key index pair structure */ +typedef struct sce_rsa2048_key_pair_index +{ + sce_rsa2048_private_key_index_t priv_key; + sce_rsa2048_public_key_index_t pub_key; +} sce_rsa2048_key_pair_index_t; + +/* RSA 3072bit key index pair structure */ +typedef struct sce_rsa3072_key_pair_index +{ + sce_rsa3072_private_key_index_t priv_key; + sce_rsa3072_public_key_index_t pub_key; +} sce_rsa3072_key_pair_index_t; + +/* RSA 4096bit key index pair structure */ +typedef struct sce_rsa4096_key_pair_index +{ + sce_rsa4096_private_key_index_t priv_key; + sce_rsa4096_public_key_index_t pub_key; +} sce_rsa4096_key_pair_index_t; + +/* ECC P-192/224/256 public key index data structure */ +typedef struct sce_ecc_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_q[HW_SCE_ECC_P192_P224_P256_PUBLIC_KEY_BYTE_SIZE]; + uint32_t key_management_info2[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; + struct + { + uint8_t key[HW_SCE_ECC_P192_P224_P256_PUBLIC_KEY_BYTE_SIZE]; + } plain_value; +} sce_ecc_public_key_index_t; + +/* ECC P-384 public key index data structure */ +typedef struct sce_ecc384_public_key_index +{ + uint32_t type; + struct + { + uint32_t key_management_info1[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO1_WORD_SIZE]; + uint8_t key_q[HW_SCE_ECC_P384_PUBLIC_KEY_BYTE_SIZE]; + uint32_t key_management_info2[HW_SCE_ECC_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; + } value; + struct + { + uint8_t key[HW_SCE_ECC_P384_PUBLIC_KEY_BYTE_SIZE]; + } plain_value; +} sce_ecc384_public_key_index_t; + +/* ECC P-192/224/256 private key index data structure */ +typedef struct sce_ecc_private_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_ECC_PRIVATE_KEY_MANAGEMENT_INFO_WORD_SIZE]; +} sce_ecc_private_key_index_t; + +/* ECC P-192/224/256 key index pair structure */ +typedef struct sce_ecc_key_pair_index +{ + sce_ecc_private_key_index_t priv_key; + sce_ecc_public_key_index_t pub_key; +} sce_ecc_key_pair_index_t; + +/* ECDH key index data structure */ +typedef struct sce_ecdh_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_SHARED_SECRET_KEY_INDEX_WORD_SIZE]; +} sce_ecdh_key_index_t; + +/* TLS CA certification public key index data structure */ +typedef struct sce_tls_ca_certification_public_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_TLS_ROOT_PUBLIC_KEY_WORD_SIZE]; +} sce_tls_ca_certification_public_key_index_t; + +/* TLS P-256 ECC key index data structure */ +typedef struct sce_tls_p256_ecc_key_index +{ + uint32_t type; + uint32_t value[HW_SCE_TLS_P256_ECC_KEY_WORD_SIZE]; +} sce_tls_p256_ecc_key_index_t; + +/* Update key ring index data structure */ +typedef struct sce_update_key_ring +{ + uint32_t type; + uint32_t value[HW_SCE_UPDATE_KEY_RING_INDEX_WORD_SIZE]; +} sce_update_key_ring_t; + +/* The work area for AES */ +typedef struct sce_aes_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint32_t current_input_data_size; + uint8_t last_1_block_as_fraction[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint8_t last_2_block_as_fraction[HW_SCE_AES_BLOCK_BYTE_SIZE * 2]; + uint8_t current_ivec[HW_SCE_AES_CBC_IV_BYTE_SIZE]; + uint8_t current_icounter[HW_SCE_AES_CTR_ICOUNTER_BYTE_SIZE]; + uint8_t flag_call_init; +} sce_aes_handle_t; + +/* The work area for TDES */ +typedef struct sce_tdes_handle +{ + uint32_t id; + sce_tdes_key_index_t key_index; + uint32_t current_input_data_size; + uint8_t last_1_block_as_fraction[HW_SCE_TDES_BLOCK_BYTE_SIZE]; + uint8_t current_ivec[HW_SCE_TDES_CBC_IV_BYTE_SIZE * 2]; + uint8_t flag_call_init; +} sce_tdes_handle_t; + +/* The work area for MD5 */ +typedef struct sce_sha_md5_handle +{ + uint32_t id; + uint8_t sha_buffer[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE * 4]; + uint32_t all_received_length; + uint32_t buffering_length; + + /* SHA1(20byte), SHA256(32byte), MD5(16byte) are supported */ + uint8_t current_hash[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE]; + uint8_t flag_call_init; +} sce_sha_md5_handle_t; + +/* The work area for HMAC-SHA */ +typedef struct sce_hmac_sha_handle +{ + uint32_t id; + sce_hmac_sha_key_index_t key_index; + uint8_t hmac_buffer[HW_SCE_SHA256_HASH_LENGTH_BYTE_SIZE * 4]; + uint32_t all_received_length; + uint32_t buffering_length; + uint8_t flag_call_init; +} sce_hmac_sha_handle_t; + +/* The work area for CMAC */ +typedef struct sce_cmac_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint8_t cmac_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint32_t all_received_length; + uint32_t buffering_length; + uint8_t flag_call_init; +} sce_cmac_handle_t; + +/* The work area for GCM */ +typedef struct sce_gcm_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint8_t gcm_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint8_t gcm_aad_buffer[HW_SCE_AES_GCM_AAD_BLOCK_BYTE_SIZE]; + uint32_t all_received_length; + uint32_t all_received_aad_length; + uint32_t buffering_length; + uint32_t buffering_aad_length; + uint8_t flag_call_init; + uint8_t flag_update_input_data; +} sce_gcm_handle_t; + +/* The work area for CCM */ +typedef struct sce_ccm_handle +{ + uint32_t id; + sce_aes_key_index_t key_index; + uint8_t formatted_data[HW_SCE_AES_CCM_B_FORMAT_BYTE_SIZE]; + uint8_t counter[HW_SCE_AES_CCM_COUNTER_BYTE_SIZE]; + uint8_t ccm_buffer[HW_SCE_AES_BLOCK_BYTE_SIZE]; + uint32_t all_received_length; + uint32_t buffering_length; + uint8_t flag_call_init; +} sce_ccm_handle_t; + +/* The work area for ECDH */ +typedef struct sce_ecdh_handle +{ + uint32_t id; + uint32_t flag_use_key_id; + uint32_t key_id; + uint32_t key_type; + uint8_t flag_call_init; + uint8_t flag_call_make_public; + uint8_t flag_call_read_public; + uint8_t flag_call_shared_secret; +} sce_ecdh_handle_t; + +/* The work area for firmware update */ +typedef struct sce_firmware_generate_mac_resume_handle +{ + uint32_t iLoop; + uint32_t counter; + uint32_t previous_counter; + bool use_resume_flag; +} sce_firmware_generate_mac_resume_handle_t; + +/* The callback function pointer type for HW_SCE_GenerateFirmwareMAC */ +typedef void (* SCE_GEN_MAC_CB_FUNC_T)(SCE_FW_CB_REQ_TYPE req_type, uint32_t iLoop, uint32_t * counter, + uint32_t * InData_UpProgram, uint32_t * OutData_Program, uint32_t MAX_CNT); + +/********************************************************************************************************************** + * External global variables + *********************************************************************************************************************/ + +/********************************************************************************************************************** + * Exported global functions + *********************************************************************************************************************/ +fsp_err_t HW_SCE_Open(lifecycle_t lifecycle, + sce_tls_ca_certification_public_key_index_t * key_index_1, + sce_update_key_ring_t * key_index_2); +fsp_err_t HW_SCE_Close(void); +void HW_SCE_SoftwareReset(void); +fsp_err_t HW_SCE_SelfCheck2(void); +fsp_err_t HW_SCE_SelfCheck3(void); + +// added for RA6M4 start +fsp_err_t HW_SCE_FwIntegrityCheck(void); +fsp_err_t HW_SCE_UpdateOemKeyIndex(lifecycle_t lifecycle, + sce_oem_cmd_t key_type, + uint8_t * iv, + uint8_t * encrypted_oem_key, + uint32_t * key_index); + +// added for RA6M4 end + +fsp_err_t HW_SCE_GenerateAes128KeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes192KeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes256KeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateTdesKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_tdes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa1024PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa1024_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa1024PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa1024_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa2048PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa2048_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa2048PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa2048_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa3072PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa3072_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa3072PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa3072_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa4096PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa4096_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa4096PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa4096_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateTlsRsaPublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_tls_ca_certification_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP192PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP224PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP256PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP384PublicKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP192PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP224PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP256PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP384PrivateKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateSha1HmacKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_hmac_sha_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateSha256HmacKeyIndex(uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_hmac_sha_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateTlsP256EccKeyIndex(sce_tls_p256_ecc_key_index_t * tls_p256_ecc_key_index, + uint8_t * ephemeral_ecdh_public_key); +fsp_err_t HW_SCE_GenerateAes128RandomKeyIndex(sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes192RandomKeyIndex(sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes256RandomKeyIndex(sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes128XtsRandomKeyIndex(sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes256XtsRandomKeyIndex(sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa1024RandomKeyIndex(sce_rsa1024_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateRsa2048RandomKeyIndex(sce_rsa2048_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateRsa3072RandomKeyIndex(sce_rsa3072_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateRsa4096RandomKeyIndex(sce_rsa4096_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateTdesRandomKeyIndex(sce_tdes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP192RandomKeyIndex(uint32_t * indata_curvetype, sce_ecc_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateEccP224RandomKeyIndex(uint32_t * indata_curvetype, sce_ecc_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateEccP256RandomKeyIndex(uint32_t * indata_curvetype, sce_ecc_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndex(uint32_t * indata_curvetype, sce_ecc_key_pair_index_t * key_pair_index); +fsp_err_t HW_SCE_GenerateRandomNumber(uint32_t * random); +fsp_err_t HW_SCE_GenerateUpdateKeyRingKeyIndex(lifecycle_t lifecycle, + uint8_t * encrypted_provisioning_key, + uint8_t * iv, + uint8_t * encrypted_key, + sce_update_key_ring_t * key_index); +uint32_t HW_SCE_GetVersion(void); + +fsp_err_t HW_SCE_GenerateAes128PlainKeyIndex(uint8_t * plain_key, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes192PlainKeyIndex(uint8_t * plain_key, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes256PlainKeyIndex(uint8_t * plain_key, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes128XtsPlainKeyIndex(uint8_t * plain_key, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateAes256XtsPlainKeyIndex(uint8_t * plain_key, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa2048PublicPlainKeyIndex(uint8_t * plain_key, sce_rsa2048_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa2048PrivatePlainKeyIndex(uint8_t * plain_key, sce_rsa2048_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa3072PublicPlainKeyIndex(uint8_t * plain_key, sce_rsa3072_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa3072PrivatePlainKeyIndex(uint8_t * plain_key, sce_rsa3072_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa4096PublicPlainKeyIndex(uint8_t * plain_key, sce_rsa4096_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateRsa4096PrivatePlainKeyIndex(uint8_t * plain_key, sce_rsa4096_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP224PublicPlainKeyIndex(uint8_t * plain_key, sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP256PublicPlainKeyIndex(uint8_t * plain_key, sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP384PublicPlainKeyIndex(uint8_t * plain_key, sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP224PrivatePlainKeyIndex(uint8_t * plain_key, sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP256PrivatePlainKeyIndex(uint8_t * plain_key, sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP384PrivatePlainKeyIndex(uint8_t * plain_key, sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateSha256HmacPlainKeyIndex(uint8_t * plain_key, sce_hmac_sha_key_index_t * key_index); + +fsp_err_t HW_SCE_GenerateEccP256r1PublicPlainKeyIndex(uint8_t * plain_key, sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP384r1PublicPlainKeyIndex(uint8_t * plain_key, sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP256r1PrivatePlainKeyIndex(uint8_t * plain_key, sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccP384r1PrivatePlainKeyIndex(uint8_t * plain_key, sce_ecc_private_key_index_t * key_index); + +fsp_err_t HW_SCE_GenerateEccSecp256k1PublicPlainKeyIndex(uint8_t * plain_key, sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_GenerateEccSecp256k1PrivatePlainKeyIndex(uint8_t * plain_key, sce_ecc_private_key_index_t * key_index); + +fsp_err_t HW_SCE_UpdateAes128KeyIndex(lifecycle_t lifecycle, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateAes192KeyIndex(lifecycle_t lifecycle, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateAes256KeyIndex(lifecycle_t lifecycle, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateAes128XtsKeyIndex(lifecycle_t lifecycle, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateAes256XtsKeyIndex(lifecycle_t lifecycle, + uint8_t * iv, + uint8_t * encrypted_key, + sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateTdesKeyIndex(uint8_t * iv, uint8_t * encrypted_key, sce_tdes_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa1024PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa1024_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa1024PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa1024_private_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa2048PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa2048_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa2048PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa2048_private_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa3072PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa3072_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa3072PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa3072_private_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa4096PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa4096_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateRsa4096PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_rsa4096_private_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateTlsRsaPublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_tls_ca_certification_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP192PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP224PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP256PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP384PublicKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP192PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP224PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP256PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateEccP384PrivateKeyIndex(uint8_t * iv, + uint8_t * encrypted_key, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_Ecc256ScalarMultiplication(uint32_t * InData_CurveType, + uint32_t * InData_Cmd, + uint32_t * InData_KeyIndex, + uint32_t * InData_PubKey, + uint32_t * OutData_R); +fsp_err_t HW_SCE_Ecc384ScalarMultiplication(uint32_t * InData_CurveType, + uint32_t * InData_KeyIndex, + uint32_t * InData_PubKey, + uint32_t * OutData_R); +fsp_err_t HW_SCE_UpdateSha1HmacKeyIndex(uint8_t * iv, uint8_t * encrypted_key, sce_hmac_sha_key_index_t * key_index); +fsp_err_t HW_SCE_UpdateSha256HmacKeyIndex(uint8_t * iv, uint8_t * encrypted_key, sce_hmac_sha_key_index_t * key_index); + +fsp_err_t HW_SCE_StartUpdateFirmware(void); +fsp_err_t HW_SCE_GenerateFirmwareMAC(uint32_t * InData_KeyIndex, + uint32_t * InData_SessionKey, + uint32_t * InData_UpProgram, + uint32_t * InData_IV, + uint32_t * OutData_Program, + uint32_t MAX_CNT, + SCE_GEN_MAC_CB_FUNC_T p_callback, + sce_firmware_generate_mac_resume_handle_t * sce_firmware_generate_mac_resume_handle); +fsp_err_t HW_SCE_VerifyFirmwareMAC(uint32_t * InData_Program, uint32_t MAX_CNT, uint32_t * InData_MAC); + +fsp_err_t HW_SCE_Aes128EcbEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes128EcbEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes128EcbEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes128EcbDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes128EcbDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes128EcbDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); +fsp_err_t HW_SCE_Aes128CbcEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes128CbcEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes128CbcEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes128CbcDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes128CbcDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes128CbcDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t HW_SCE_Aes192EcbEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes192EcbEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes192EcbEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes192EcbDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes192EcbDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes192EcbDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); +fsp_err_t HW_SCE_Aes192CbcEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes192CbcEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes192CbcEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes192CbcDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes192CbcDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes192CbcDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t HW_SCE_Aes256EcbEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes256EcbEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes256EcbEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes256EcbDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes256EcbDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes256EcbDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); +fsp_err_t HW_SCE_Aes256CbcEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes256CbcEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes256CbcEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes256CbcDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes256CbcDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes256CbcDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t HW_SCE_Aes128CtrEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * icounter); +fsp_err_t HW_SCE_Aes128CtrEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes128CtrEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes128CtrDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * icounter); +fsp_err_t HW_SCE_Aes128CtrDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes128CtrDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t HW_SCE_Aes192CtrEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * icounter); +fsp_err_t HW_SCE_Aes192CtrEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes192CtrEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes192CtrDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * icounter); +fsp_err_t HW_SCE_Aes192CtrDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes192CtrDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t HW_SCE_Aes256CtrEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * icounter); +fsp_err_t HW_SCE_Aes256CtrEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes256CtrEncryptFinal(sce_aes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_Aes256CtrDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * icounter); +fsp_err_t HW_SCE_Aes256CtrDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes256CtrDecryptFinal(sce_aes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t HW_SCE_Aes128XtsEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes128XtsEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes128XtsEncryptFinal(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes128XtsDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes128XtsDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes128XtsDecryptFinal(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes256XtsEncryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes256XtsEncryptUpdate(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes256XtsEncryptFinal(sce_aes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes256XtsDecryptInit(sce_aes_handle_t * handle, sce_aes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_Aes256XtsDecryptUpdate(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t text_bitlen); +fsp_err_t HW_SCE_Aes256XtsDecryptFinal(sce_aes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t text_bitlen); + +fsp_err_t HW_SCE_Aes128GcmEncryptInit(sce_gcm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes128GcmEncryptUpdate(sce_gcm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_data_len, + uint8_t * aad, + uint32_t aad_len); +fsp_err_t HW_SCE_Aes128GcmEncryptFinal(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_data_len, + uint8_t * atag); +fsp_err_t HW_SCE_Aes128GcmDecryptInit(sce_gcm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes128GcmDecryptUpdate(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_data_len, + uint8_t * aad, + uint32_t aad_len); +fsp_err_t HW_SCE_Aes128GcmDecryptFinal(sce_gcm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_data_len, + uint8_t * atag, + uint32_t atag_len); + +fsp_err_t HW_SCE_Aes192GcmEncryptInit(sce_gcm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes192GcmEncryptUpdate(sce_gcm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_data_len, + uint8_t * aad, + uint32_t aad_len); +fsp_err_t HW_SCE_Aes192GcmEncryptFinal(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_data_len, + uint8_t * atag); +fsp_err_t HW_SCE_Aes192GcmDecryptInit(sce_gcm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes192GcmDecryptUpdate(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_data_len, + uint8_t * aad, + uint32_t aad_len); +fsp_err_t HW_SCE_Aes192GcmDecryptFinal(sce_gcm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_data_len, + uint8_t * atag, + uint32_t atag_len); + +fsp_err_t HW_SCE_Aes256GcmEncryptInit(sce_gcm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes256GcmEncryptUpdate(sce_gcm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_data_len, + uint8_t * aad, + uint32_t aad_len); +fsp_err_t HW_SCE_Aes256GcmEncryptFinal(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_data_len, + uint8_t * atag); +fsp_err_t HW_SCE_Aes256GcmDecryptInit(sce_gcm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * ivec, + uint32_t ivec_len); +fsp_err_t HW_SCE_Aes256GcmDecryptUpdate(sce_gcm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_data_len, + uint8_t * aad, + uint32_t aad_len); +fsp_err_t HW_SCE_Aes256GcmDecryptFinal(sce_gcm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_data_len, + uint8_t * atag, + uint32_t atag_len); + +fsp_err_t HW_SCE_Aes128CcmEncryptInit(sce_ccm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * nonce, + uint32_t nonce_len, + uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len); +fsp_err_t HW_SCE_Aes128CcmEncryptUpdate(sce_ccm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes128CcmEncryptFinal(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_length, + uint8_t * mac, + uint32_t mac_length); +fsp_err_t HW_SCE_Aes128CcmDecryptInit(sce_ccm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * nonce, + uint32_t nonce_len, + uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len); +fsp_err_t HW_SCE_Aes128CcmDecryptUpdate(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes128CcmDecryptFinal(sce_ccm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_length, + uint8_t * mac, + uint32_t mac_length); + +fsp_err_t HW_SCE_Aes192CcmEncryptInit(sce_ccm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * nonce, + uint32_t nonce_len, + uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len); +fsp_err_t HW_SCE_Aes192CcmEncryptUpdate(sce_ccm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes192CcmEncryptFinal(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_length, + uint8_t * mac, + uint32_t mac_length); +fsp_err_t HW_SCE_Aes192CcmDecryptInit(sce_ccm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * nonce, + uint32_t nonce_len, + uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len); +fsp_err_t HW_SCE_Aes192CcmDecryptUpdate(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes192CcmDecryptFinal(sce_ccm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_length, + uint8_t * mac, + uint32_t mac_length); + +fsp_err_t HW_SCE_Aes256CcmEncryptInit(sce_ccm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * nonce, + uint32_t nonce_len, + uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len); +fsp_err_t HW_SCE_Aes256CcmEncryptUpdate(sce_ccm_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_Aes256CcmEncryptFinal(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint32_t * cipher_length, + uint8_t * mac, + uint32_t mac_length); +fsp_err_t HW_SCE_Aes256CcmDecryptInit(sce_ccm_handle_t * handle, + sce_aes_key_index_t * key_index, + uint8_t * nonce, + uint32_t nonce_len, + uint8_t * adata, + uint8_t a_len, + uint32_t payload_len, + uint32_t mac_len); +fsp_err_t HW_SCE_Aes256CcmDecryptUpdate(sce_ccm_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_Aes256CcmDecryptFinal(sce_ccm_handle_t * handle, + uint8_t * plain, + uint32_t * plain_length, + uint8_t * mac, + uint32_t mac_length); + +fsp_err_t HW_SCE_Aes128CmacGenerateInit(sce_cmac_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes128CmacGenerateUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Aes128CmacGenerateFinal(sce_cmac_handle_t * handle, uint8_t * mac); +fsp_err_t HW_SCE_Aes128CmacVerifyInit(sce_cmac_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes128CmacVerifyUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Aes128CmacVerifyFinal(sce_cmac_handle_t * handle, uint8_t * mac, uint32_t mac_length); +fsp_err_t HW_SCE_Aes256CmacGenerateInit(sce_cmac_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes256CmacGenerateUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Aes256CmacGenerateFinal(sce_cmac_handle_t * handle, uint8_t * mac); +fsp_err_t HW_SCE_Aes256CmacVerifyInit(sce_cmac_handle_t * handle, sce_aes_key_index_t * key_index); +fsp_err_t HW_SCE_Aes256CmacVerifyUpdate(sce_cmac_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Aes256CmacVerifyFinal(sce_cmac_handle_t * handle, uint8_t * mac, uint32_t mac_length); + +fsp_err_t HW_SCE_TdesEcbEncryptInit(sce_tdes_handle_t * handle, sce_tdes_key_index_t * key_index); +fsp_err_t HW_SCE_TdesEcbEncryptUpdate(sce_tdes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_TdesEcbEncryptFinal(sce_tdes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_TdesEcbDecryptInit(sce_tdes_handle_t * handle, sce_tdes_key_index_t * key_index); +fsp_err_t HW_SCE_TdesEcbDecryptUpdate(sce_tdes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_TdesEcbDecryptFinal(sce_tdes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); +fsp_err_t HW_SCE_TdesCbcEncryptInit(sce_tdes_handle_t * handle, sce_tdes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_TdesCbcEncryptUpdate(sce_tdes_handle_t * handle, + uint8_t * plain, + uint8_t * cipher, + uint32_t plain_length); +fsp_err_t HW_SCE_TdesCbcEncryptFinal(sce_tdes_handle_t * handle, uint8_t * cipher, uint32_t * cipher_length); +fsp_err_t HW_SCE_TdesCbcDecryptInit(sce_tdes_handle_t * handle, sce_tdes_key_index_t * key_index, uint8_t * ivec); +fsp_err_t HW_SCE_TdesCbcDecryptUpdate(sce_tdes_handle_t * handle, + uint8_t * cipher, + uint8_t * plain, + uint32_t cipher_length); +fsp_err_t HW_SCE_TdesCbcDecryptFinal(sce_tdes_handle_t * handle, uint8_t * plain, uint32_t * plain_length); + +fsp_err_t HW_SCE_Md5Init(sce_sha_md5_handle_t * handle); +fsp_err_t HW_SCE_Md5Update(sce_sha_md5_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Md5Final(sce_sha_md5_handle_t * handle, uint8_t * digest, uint32_t * digest_length); + +fsp_err_t HW_SCE_Sha1Init(sce_sha_md5_handle_t * handle); +fsp_err_t HW_SCE_Sha1Update(sce_sha_md5_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Sha1Final(sce_sha_md5_handle_t * handle, uint8_t * digest, uint32_t * digest_length); +fsp_err_t HW_SCE_Sha256Init(sce_sha_md5_handle_t * handle); +fsp_err_t HW_SCE_Sha256Update(sce_sha_md5_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Sha256Final(sce_sha_md5_handle_t * handle, uint8_t * digest, uint32_t * digest_length); + +fsp_err_t HW_SCE_Sha1HmacGenerateInit(sce_hmac_sha_handle_t * handle, sce_hmac_sha_key_index_t * key_index); +fsp_err_t HW_SCE_Sha1HmacGenerateUpdate(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Sha1HmacGenerateFinal(sce_hmac_sha_handle_t * handle, uint8_t * mac); +fsp_err_t HW_SCE_Sha256HmacGenerateInit(sce_hmac_sha_handle_t * handle, sce_hmac_sha_key_index_t * key_index); +fsp_err_t HW_SCE_Sha256HmacGenerateUpdate(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Sha256HmacGenerateFinal(sce_hmac_sha_handle_t * handle, uint8_t * mac); +fsp_err_t HW_SCE_Sha1HmacVerifyInit(sce_hmac_sha_handle_t * handle, sce_hmac_sha_key_index_t * key_index); +fsp_err_t HW_SCE_Sha1HmacVerifyUpdate(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Sha1HmacVerifyFinal(sce_hmac_sha_handle_t * handle, uint8_t * mac, uint32_t mac_length); +fsp_err_t HW_SCE_Sha256HmacVerifyInit(sce_hmac_sha_handle_t * handle, sce_hmac_sha_key_index_t * key_index); +fsp_err_t HW_SCE_Sha256HmacVerifyUpdate(sce_hmac_sha_handle_t * handle, uint8_t * message, uint32_t message_length); +fsp_err_t HW_SCE_Sha256HmacVerifyFinal(sce_hmac_sha_handle_t * handle, uint8_t * mac, uint32_t mac_length); + +fsp_err_t HW_SCE_RsassaPkcs1024SignatureGenerate(sce_rsa_byte_data_t * message_hash, + sce_rsa_byte_data_t * signature, + sce_rsa1024_private_key_index_t * key_index, + uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs1024SignatureVerification(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa1024_public_key_index_t * key_index, + uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs2048SignatureGenerate(sce_rsa_byte_data_t * message_hash, + sce_rsa_byte_data_t * signature, + sce_rsa2048_private_key_index_t * key_index, + uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs2048SignatureVerification(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa2048_public_key_index_t * key_index, + uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs3072SignatureGenerate(sce_rsa_byte_data_t * message_hash, + sce_rsa_byte_data_t * signature, + sce_rsa3072_private_key_index_t * key_index, + uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs3072SignatureVerification(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa3072_public_key_index_t * key_index, + uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs4096SignatureGenerate(sce_rsa_byte_data_t * message_hash, + sce_rsa_byte_data_t * signature, + sce_rsa4096_private_key_index_t * key_index, + uint8_t hash_type); +fsp_err_t HW_SCE_RsassaPkcs4096SignatureVerification(sce_rsa_byte_data_t * signature, + sce_rsa_byte_data_t * message_hash, + sce_rsa4096_public_key_index_t * key_index, + uint8_t hash_type); + +fsp_err_t HW_SCE_RsaesPkcs1024Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa1024_public_key_index_t * key_index); +fsp_err_t HW_SCE_RsaesPkcs1024Decrypt(sce_rsa_byte_data_t * cipher, + sce_rsa_byte_data_t * plain, + sce_rsa1024_private_key_index_t * key_index); +fsp_err_t HW_SCE_RsaesPkcs2048Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa2048_public_key_index_t * key_index); +fsp_err_t HW_SCE_RsaesPkcs2048Decrypt(sce_rsa_byte_data_t * cipher, + sce_rsa_byte_data_t * plain, + sce_rsa2048_private_key_index_t * key_index); +fsp_err_t HW_SCE_RsaesPkcs3072Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa3072_public_key_index_t * key_index); +fsp_err_t HW_SCE_RsaesPkcs3072Decrypt(sce_rsa_byte_data_t * cipher, + sce_rsa_byte_data_t * plain, + sce_rsa3072_private_key_index_t * key_index); +fsp_err_t HW_SCE_RsaesPkcs4096Encrypt(sce_rsa_byte_data_t * plain, + sce_rsa_byte_data_t * cipher, + sce_rsa4096_public_key_index_t * key_index); +fsp_err_t HW_SCE_RsaesPkcs4096Decrypt(sce_rsa_byte_data_t * cipher, + sce_rsa_byte_data_t * plain, + sce_rsa4096_private_key_index_t * key_index); + +fsp_err_t HW_SCE_TlsRootCertificateVerification(uint32_t public_key_type, + uint8_t * certificate, + uint32_t certificate_length, + uint32_t public_key_n_start_position, + uint32_t public_key_n_end_position, + uint32_t public_key_e_start_position, + uint32_t public_key_e_end_position, + uint8_t * signature, + uint32_t * encrypted_root_public_key); +fsp_err_t HW_SCE_TlsCertificateVerification(uint32_t public_key_type, + uint32_t * encrypted_input_public_key, + uint8_t * certificate, + uint32_t certificate_length, + uint8_t * signature, + uint32_t public_key_n_start_position, + uint32_t public_key_n_end_position, + uint32_t public_key_e_start_position, + uint32_t public_key_e_end_position, + uint32_t * encrypted_output_public_key); +fsp_err_t HW_SCE_TlsGeneratePreMasterSecret(uint32_t * sce_pre_master_secret); +fsp_err_t HW_SCE_TlsGenerateMasterSecret(uint32_t select_cipher_suite, + uint32_t * sce_pre_master_secret, + uint8_t * client_random, + uint8_t * server_random, + uint32_t * sce_master_secret); +fsp_err_t HW_SCE_TlsEncryptPreMasterSecretWithRsa2048PublicKey(uint32_t * encrypted_public_key, + uint32_t * sce_pre_master_secret, + uint8_t * encrypted_pre_master_secret); +fsp_err_t HW_SCE_TlsGenerateSessionKey(uint32_t select_cipher_suite, + uint32_t * sce_master_secret, + uint8_t * client_random, + uint8_t * server_random, + uint8_t * nonce_explicit, + sce_hmac_sha_key_index_t * client_mac_key_index, + sce_hmac_sha_key_index_t * server_mac_key_index, + sce_aes_key_index_t * client_crypto_key_index, + sce_aes_key_index_t * server_crypto_key_index, + uint8_t * client_iv, + uint8_t * server_iv); +fsp_err_t HW_SCE_TlsGenerateVerifyData(uint32_t select_verify_data, + uint32_t * sce_master_secret, + uint8_t * hand_shake_hash, + uint8_t * verify_data); +fsp_err_t HW_SCE_TlsGeneratePreMasterSecretWithEccP256Key(uint32_t * encrypted_public_key, + sce_tls_p256_ecc_key_index_t * tls_p256_ecc_key_index, + uint32_t * sce_pre_master_secret); +fsp_err_t HW_SCE_TlsServersEphemeralEcdhPublicKeyRetrieves(uint32_t public_key_type, + uint8_t * client_random, + uint8_t * server_random, + uint8_t * server_ephemeral_ecdh_public_key, + uint8_t * server_key_exchange_signature, + uint32_t * encrypted_public_key, + uint32_t * encrypted_ephemeral_ecdh_public_key); + +fsp_err_t HW_SCE_EcdsaP192SignatureGenerate(sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_EcdsaP224SignatureGenerate(uint32_t * indata_curvetype, + sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_EcdsaP256SignatureGenerate(uint32_t * indata_curvetype, + sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_EcdsaP384SignatureGenerate(uint32_t * indata_curvetype, + sce_ecdsa_byte_data_t * message_hash, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_EcdsaP192SignatureVerification(sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_EcdsaP224SignatureVerification(uint32_t * indata_curvetype, + sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_EcdsaP256SignatureVerification(uint32_t * indata_curvetype, + sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_EcdsaP384SignatureVerification(uint32_t * indata_curvetype, + sce_ecdsa_byte_data_t * signature, + sce_ecdsa_byte_data_t * message_hash, + sce_ecc_public_key_index_t * key_index); + +fsp_err_t HW_SCE_RSA_IF_HASH(uint8_t * p_mes, uint8_t * p_hash, uint32_t mes_len, uint8_t hash_type); + +fsp_err_t HW_SCE_EcdhInit(sce_ecdh_handle_t * handle, uint32_t key_type, uint32_t use_key_id); +fsp_err_t HW_SCE_EcdhReadPublicKey(sce_ecdh_handle_t * handle, + sce_ecc_public_key_index_t * public_key_index, + uint8_t * public_key_data, + sce_ecdsa_byte_data_t * signature, + sce_ecc_public_key_index_t * key_index); +fsp_err_t HW_SCE_EcdhMakePublicKey(sce_ecdh_handle_t * handle, + sce_ecc_public_key_index_t * public_key_index, + sce_ecc_private_key_index_t * private_key_index, + uint8_t * public_key, + sce_ecdsa_byte_data_t * signature, + sce_ecc_private_key_index_t * key_index); +fsp_err_t HW_SCE_EcdhCalculateSharedSecretIndex(sce_ecdh_handle_t * handle, + sce_ecc_public_key_index_t * public_key_index, + sce_ecc_private_key_index_t * private_key_index, + sce_ecdh_key_index_t * shared_secret_index); +fsp_err_t HW_SCE_EcdhKeyDerivation(sce_ecdh_handle_t * handle, + sce_ecdh_key_index_t * shared_secret_index, + uint32_t algorithm_id, + uint8_t * other_info, + uint32_t other_info_length, + sce_aes_key_index_t * key_index); + +fsp_err_t HW_SCE_Aes128KeyWrap(sce_aes_key_index_t * wrap_key_index, + uint32_t target_key_type, + sce_aes_key_index_t * target_key_index, + uint32_t * wrapped_key); +fsp_err_t HW_SCE_Aes256KeyWrap(sce_aes_key_index_t * wrap_key_index, + uint32_t target_key_type, + sce_aes_key_index_t * target_key_index, + uint32_t * wrapped_key); +fsp_err_t HW_SCE_Aes128KeyUnwrap(sce_aes_key_index_t * wrap_key_index, + uint32_t target_key_type, + uint32_t * wrapped_key, + sce_aes_key_index_t * target_key_index); +fsp_err_t HW_SCE_Aes256KeyUnwrap(sce_aes_key_index_t * wrap_key_index, + uint32_t target_key_type, + uint32_t * wrapped_key, + sce_aes_key_index_t * target_key_index); + +#endif /* R_SCE_IF_HEADER_FILE */ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/hw_sce_ra_private.h index 134de68ad..e28c00976 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/private/inc/hw_sce_ra_private.h @@ -62,6 +62,14 @@ #define SIZE_AES_256BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 8) #define SIZE_AES_256BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 32) + #define SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED (416) + #define SIZE_AES_XTS_128BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 8) + #define SIZE_AES_XTS_128BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 32) + + #define SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED (672) + #define SIZE_AES_XTS_256BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 8) + #define SIZE_AES_XTS_256BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 32) + /********************************************************************************************************************** Global Typedef definitions *********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/public/inc/r_sce_if.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/public/inc/r_sce_if.h index 10fd7d1bd..e054790f5 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/public/inc/r_sce_if.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5/plainkey/public/inc/r_sce_if.h @@ -113,6 +113,10 @@ #define HW_SCE_AES_CCM_COUNTER_BYTE_SIZE (16U) #define HW_SCE_KEYWRAP_AES128 (0U) #define HW_SCE_KEYWRAP_AES256 (2U) +#define HW_SCE_AES128XTS_KEY_BYTE_SIZE (32U) +#define HW_SCE_AES256XTS_KEY_BYTE_SIZE (64U) +#define HW_SCE_AES128XTS_KEY_BIT_SIZE (256U) +#define HW_SCE_AES256XTS_KEY_BIT_SIZE (512U) /* For TDES operation. */ #define HW_SCE_TDES_KEY_INDEX_WORD_SIZE (16U) diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/private/inc/hw_sce_ra_private.h index ee97645e4..1be8d0ea4 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/private/inc/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/private/inc/hw_sce_ra_private.h @@ -62,6 +62,14 @@ #define SIZE_AES_256BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 8) #define SIZE_AES_256BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 32) + #define SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED (416) + #define SIZE_AES_XTS_128BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 8) + #define SIZE_AES_XTS_128BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 32) + + #define SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED (672) + #define SIZE_AES_XTS_256BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 8) + #define SIZE_AES_XTS_256BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 32) + /********************************************************************************************************************** Global Typedef definitions *********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/public/inc/r_sce_if.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/public/inc/r_sce_if.h index 990ee04e8..d3c513ce0 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/public/inc/r_sce_if.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce5b/plainkey/public/inc/r_sce_if.h @@ -64,6 +64,8 @@ #define HW_SCE_AES_CCM_COUNTER_BYTE_SIZE (16U) #define HW_SCE_AES128XTS_KEY_BYTE_SIZE (32U) #define HW_SCE_AES256XTS_KEY_BYTE_SIZE (64U) +#define HW_SCE_AES128XTS_KEY_BIT_SIZE (256U) +#define HW_SCE_AES256XTS_KEY_BIT_SIZE (512U) #define HW_SCE_AES_XTS_IV_BYTE_SIZE (16U) /* For TDES operation. */ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c index 931e65739..df8976d13 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/adaptors/r_sce_adapt.c @@ -175,6 +175,32 @@ fsp_err_t HW_SCE_GenerateOemKeyIndexPrivate (const sce_oem_key_type_t key_type, indata_cmd[0] = 0 ; ret = HW_SCE_GenerateEccPublicKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, &curve_type, indata_cmd, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index); + } + else if (cmd == SCE_OEM_CMD_ECC_SECP256K1_PUBLIC) + { + uint32_t curve_type = SCE_ECC_CURVE_TYPE_KOBLITZ; + indata_cmd[0] = 0 ; + ret = HW_SCE_GenerateEccPublicKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, &curve_type, indata_cmd, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index); + + } + else if (cmd == SCE_OEM_CMD_ECC_P256R1_PUBLIC) + { + uint32_t curve_type = SCE_ECC_CURVE_TYPE_BRAINPOOL; + indata_cmd[0] = 0 ; + ret = HW_SCE_GenerateEccPublicKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, &curve_type, indata_cmd, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index); + + } + else if (cmd == SCE_OEM_CMD_ECC_P384_PUBLIC) + { + uint32_t curve_type = SCE_ECC_CURVE_TYPE_NIST; + ret = HW_SCE_GenerateEccP384PublicKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, &curve_type, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index); + + } + else if (cmd == SCE_OEM_CMD_ECC_P384R1_PUBLIC) + { + uint32_t curve_type = SCE_ECC_CURVE_TYPE_BRAINPOOL; + ret = HW_SCE_GenerateEccP384PublicKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, &curve_type, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index); + } else if (cmd == SCE_OEM_CMD_ECC_P192_PRIVATE) { @@ -196,6 +222,30 @@ fsp_err_t HW_SCE_GenerateOemKeyIndexPrivate (const sce_oem_key_type_t key_type, ret = HW_SCE_GenerateEccPrivateKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, &curve_type, indata_cmd, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index); } + else if (cmd == SCE_OEM_CMD_ECC_SECP256K1_PRIVATE) + { + uint32_t curve_type = SCE_ECC_CURVE_TYPE_KOBLITZ; + indata_cmd[0] = 0 ; + ret = HW_SCE_GenerateEccPrivateKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, &curve_type, indata_cmd, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index); + + } + else if (cmd == SCE_OEM_CMD_ECC_P256R1_PRIVATE) + { + uint32_t curve_type = SCE_ECC_CURVE_TYPE_BRAINPOOL; + indata_cmd[0] = 0 ; + ret = HW_SCE_GenerateEccPrivateKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, &curve_type, indata_cmd, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index); + + } + else if (cmd == SCE_OEM_CMD_ECC_P384_PRIVATE) + { + uint32_t curve_type = SCE_ECC_CURVE_TYPE_NIST; + ret = HW_SCE_GenerateEccP384PrivateKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, &curve_type, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index); + } + else if (cmd == SCE_OEM_CMD_ECC_P384R1_PRIVATE) + { + uint32_t curve_type = SCE_ECC_CURVE_TYPE_BRAINPOOL; + ret = HW_SCE_GenerateEccP384PrivateKeyIndexSub(indata_key_type, install_key_ring_index, (uint32_t *) encrypted_provisioning_key, &curve_type, (uint32_t *) iv, (uint32_t *) encrypted_oem_key, key_index); + } else { ret = FSP_ERR_ASSERTION; diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p2d.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p2d.c new file mode 100644 index 000000000..3aeff3530 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p2d.c @@ -0,0 +1,372 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_UpdateEccP384PrivateKeyIndexSub(uint32_t *InData_CurveType, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B4H & 0x1dU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00002d01U; + SCE->REG_108H = 0x00000000U; + HW_SCE_p_func100(0x5d4891f3U, 0x531f4bbeU, 0x38b88fd7U, 0xbe97c09dU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x200c3b0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[0]; + SCE->REG_100H = S_INST2[1]; + SCE->REG_100H = S_INST2[2]; + SCE->REG_100H = S_INST2[3]; + SCE->REG_C4H = 0x000c0b0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xda0168d1U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x02f8073dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[4]; + SCE->REG_100H = S_INST2[5]; + SCE->REG_100H = S_INST2[6]; + SCE->REG_100H = S_INST2[7]; + HW_SCE_p_func100(0x25dc3737U, 0x1c34b002U, 0xf95a288bU, 0x33752e7dU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00f9073dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[4+4 + 0]; + SCE->REG_100H = S_INST2[4+4 + 1]; + SCE->REG_100H = S_INST2[4+4 + 2]; + SCE->REG_100H = S_INST2[4+4 + 3]; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[4+8 + 0]; + SCE->REG_100H = S_INST2[4+8 + 1]; + SCE->REG_100H = S_INST2[4+8 + 2]; + SCE->REG_100H = S_INST2[4+8 + 3]; + SCE->REG_A4H = 0x00800c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_p_func100(0x239047fcU, 0xb2619d5bU, 0x46507857U, 0xc1d93159U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_p_func103(); + HW_SCE_p_func100(0xac2c99c9U, 0x0a6c3a9cU, 0xa747daffU, 0x3ca052c1U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x200c3b0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + HW_SCE_p_func076(); + SCE->REG_C4H = 0x000c0b0cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00002133U; + SCE->REG_104H = 0x00000b61U; + SCE->REG_B0H = 0x00000200U; + SCE->REG_A4H = 0x00d0c9a7U; + SCE->REG_D0H = 0x00000200U; + SCE->REG_C4H = 0x02e087bfU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[4]; + SCE->REG_100H = InData_InstData[5]; + SCE->REG_100H = InData_InstData[6]; + SCE->REG_100H = InData_InstData[7]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[8]; + SCE->REG_100H = InData_InstData[9]; + SCE->REG_100H = InData_InstData[10]; + SCE->REG_100H = InData_InstData[11]; + SCE->REG_04H = 0x00000232U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[12] = SCE->REG_100H; + OutData_KeyIndex[13] = SCE->REG_100H; + OutData_KeyIndex[14] = SCE->REG_100H; + OutData_KeyIndex[15] = SCE->REG_100H; + HW_SCE_p_func100(0x2ecf8e8eU, 0x635bc59fU, 0xe532e502U, 0xc1cc96f1U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x000009cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[16] = SCE->REG_100H; + OutData_KeyIndex[17] = SCE->REG_100H; + OutData_KeyIndex[18] = SCE->REG_100H; + OutData_KeyIndex[19] = SCE->REG_100H; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000049a5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[12]; + SCE->REG_100H = InData_InstData[13]; + SCE->REG_100H = InData_InstData[14]; + SCE->REG_100H = InData_InstData[15]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_p_func100(0xba23d592U, 0xd9473c42U, 0x694214adU, 0xfba0188eU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x13826b47U, 0xaabcd093U, 0x2f2d3bc7U, 0xb64808ddU); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x44a7aa80U, 0xae8d4fa8U, 0x4d2e7b48U, 0x91681b47U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_p_func102(0x8a3cf028U, 0x611bfaafU, 0x500bf2fbU, 0x55484cfbU); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p2d_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p2e.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p2e.c new file mode 100644 index 000000000..1b6c4f1e8 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p2e.c @@ -0,0 +1,393 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_UpdateEccP384PublicKeyIndexSub(uint32_t *InData_CurveType, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B4H & 0x1dU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00002e01U; + SCE->REG_108H = 0x00000000U; + HW_SCE_p_func100(0x02781096U, 0x816ffc24U, 0x73bc4cb6U, 0x32fadec2U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x200c3b0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[0]; + SCE->REG_100H = S_INST2[1]; + SCE->REG_100H = S_INST2[2]; + SCE->REG_100H = S_INST2[3]; + SCE->REG_C4H = 0x000c0b0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0xda0168d1U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x02f8073dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[4]; + SCE->REG_100H = S_INST2[5]; + SCE->REG_100H = S_INST2[6]; + SCE->REG_100H = S_INST2[7]; + HW_SCE_p_func100(0xd8136aeaU, 0xddb3c9cfU, 0x7005b6d8U, 0xacaedc6dU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00f9073dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[4+4 + 0]; + SCE->REG_100H = S_INST2[4+4 + 1]; + SCE->REG_100H = S_INST2[4+4 + 2]; + SCE->REG_100H = S_INST2[4+4 + 3]; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_INST2[4+8 + 0]; + SCE->REG_100H = S_INST2[4+8 + 1]; + SCE->REG_100H = S_INST2[4+8 + 2]; + SCE->REG_100H = S_INST2[4+8 + 3]; + SCE->REG_A4H = 0x00800c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_p_func100(0x56d8736cU, 0x44a7ea30U, 0xd931da8eU, 0x5c16b46fU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_p_func103(); + HW_SCE_p_func100(0xe819e582U, 0x0af45c96U, 0x1c0b7a1eU, 0x97b59a81U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x200c3b0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + HW_SCE_p_func077(); + SCE->REG_C4H = 0x000c0b0cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00002153U; + SCE->REG_104H = 0x00000031U; + SCE->REG_B0H = 0x00000400U; + SCE->REG_A4H = 0x00d0c9a7U; + SCE->REG_D0H = 0x00000400U; + SCE->REG_C4H = 0x02e0888fU; + SCE->REG_04H = 0x00000252U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + for (iLoop = 4; iLoop < 20 ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[iLoop + 0]; + SCE->REG_100H = InData_InstData[iLoop + 1]; + SCE->REG_100H = InData_InstData[iLoop + 2]; + SCE->REG_100H = InData_InstData[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[iLoop + 0] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 1] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 2] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[iLoop + 0] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 1] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 2] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 3] = SCE->REG_100H; + SCE->REG_104H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_C8H_b.B6) + { + /* waiting */ + } + HW_SCE_p_func100(0x4fa35818U, 0x4cc5d976U, 0x752cacfcU, 0xc969ededU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x0045094cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00002113U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049a5U; + SCE->REG_C4H = 0x00e0088dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[20]; + SCE->REG_100H = InData_InstData[21]; + SCE->REG_100H = InData_InstData[22]; + SCE->REG_100H = InData_InstData[23]; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[24] = SCE->REG_100H; + OutData_KeyIndex[25] = SCE->REG_100H; + OutData_KeyIndex[26] = SCE->REG_100H; + OutData_KeyIndex[27] = SCE->REG_100H; + HW_SCE_p_func100(0x7e6ff7f3U, 0x8e531ef1U, 0x443c7e7eU, 0xe10b7efbU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000cc4U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[28] = SCE->REG_100H; + OutData_KeyIndex[29] = SCE->REG_100H; + OutData_KeyIndex[30] = SCE->REG_100H; + OutData_KeyIndex[31] = SCE->REG_100H; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000049a5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[24]; + SCE->REG_100H = InData_InstData[25]; + SCE->REG_100H = InData_InstData[26]; + SCE->REG_100H = InData_InstData[27]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_p_func100(0x9f39842fU, 0x4a9cc12eU, 0x08f2543fU, 0xc723faceU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x57469e59U, 0x422a15d2U, 0xa33482f8U, 0x581a2627U); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xfbfa23f6U, 0x026bd09bU, 0xac1ee3b8U, 0x2d19bdb6U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_p_func102(0x672fcd04U, 0x38bcad30U, 0x1eceaf0fU, 0x7aa0e0a0U); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p2e_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p9b.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p9b.c new file mode 100644 index 000000000..b0018e65b --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_p9b.c @@ -0,0 +1,612 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_PubKey, uint32_t *OutData_R) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x00009b01U; + SCE->REG_108H = 0x00000000U; + SCE->REG_28H = 0x008b0001U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_C4H = 0x200c3b0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + HW_SCE_p_func076(); + SCE->REG_C4H = 0x000c0b0cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000b62U; + SCE->REG_D0H = 0x00000200U; + SCE->REG_C4H = 0x02f087bfU; + SCE->REG_00H = 0x00003233U; + SCE->REG_2CH = 0x00000011U; + for (iLoop = 0; iLoop < 12; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4+iLoop + 0]; + SCE->REG_100H = InData_KeyIndex[4+iLoop + 1]; + SCE->REG_100H = InData_KeyIndex[4+iLoop + 2]; + SCE->REG_100H = InData_KeyIndex[4+iLoop + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x000007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4+iLoop + 0]; + SCE->REG_100H = InData_KeyIndex[4+iLoop + 1]; + SCE->REG_100H = InData_KeyIndex[4+iLoop + 2]; + SCE->REG_100H = InData_KeyIndex[4+iLoop + 3]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_p_func100(0x25449e4bU, 0xc3480489U, 0x17a0727cU, 0x3dbe0af4U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xf8abff18U, 0x26b39debU, 0xa0d495afU, 0x6df4b6bfU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0x1c95e1d6U, 0xe72ad1b2U, 0x303fdb2bU, 0xb71983e7U); + SCE->REG_ECH = 0x38000f5aU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000002B4U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000003D8U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + HW_SCE_p_func027_r1(OFS_ADR); + HW_SCE_p_func100(0x87833ea9U, 0x0c3f36a3U, 0x605f699cU, 0x4718a0c7U); + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000820U; + SCE->REG_24H = 0x80009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00021028U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004404U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000808U; + SCE->REG_24H = 0x8000f0d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00000b67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[0]; + SCE->REG_100H = InData_PubKey[1]; + SCE->REG_100H = InData_PubKey[2]; + SCE->REG_100H = InData_PubKey[3]; + SCE->REG_100H = InData_PubKey[4]; + SCE->REG_100H = InData_PubKey[5]; + SCE->REG_100H = InData_PubKey[6]; + SCE->REG_100H = InData_PubKey[7]; + SCE->REG_100H = InData_PubKey[8]; + SCE->REG_100H = InData_PubKey[9]; + SCE->REG_100H = InData_PubKey[10]; + SCE->REG_100H = InData_PubKey[11]; + SCE->REG_24H = 0x00000c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00000b67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_PubKey[12]; + SCE->REG_100H = InData_PubKey[13]; + SCE->REG_100H = InData_PubKey[14]; + SCE->REG_100H = InData_PubKey[15]; + SCE->REG_100H = InData_PubKey[16]; + SCE->REG_100H = InData_PubKey[17]; + SCE->REG_100H = InData_PubKey[18]; + SCE->REG_100H = InData_PubKey[19]; + SCE->REG_100H = InData_PubKey[20]; + SCE->REG_100H = InData_PubKey[21]; + SCE->REG_100H = InData_PubKey[22]; + SCE->REG_100H = InData_PubKey[23]; + SCE->REG_24H = 0x00000c2cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x00000bdeU; + SCE->REG_ECH = 0x00000842U; + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x0000b480U; + SCE->REG_ECH = 0x00000180U; + SCE->REG_ECH = 0x0000b7a0U; + SCE->REG_ECH = 0x0000009bU; + SCE->REG_ECH = 0x00000b9cU; + SCE->REG_E0H = 0x81010380U; + SCE->REG_04H = 0x00000607U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + for(iLoop=0;iLoop<384;iLoop=iLoop+1) + { + HW_SCE_p_func101(0xb227021fU, 0xd3041ffcU, 0xc4619161U, 0x2d50ab6dU); + HW_SCE_p_func300(); + if (S_RAM[0] == 0x00000001U) + { + break; + } + HW_SCE_p_func101(0x863220b7U, 0x936c2027U, 0x7903416bU, 0xcfe76d87U); + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + HW_SCE_p_func100(0x77104cb4U, 0xf86fbcf6U, 0x3f9c36e7U, 0xb8b5ccbeU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x85abca97U, 0x4cdc058bU, 0x87e4d2f2U, 0x6797d767U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005004U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008404U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b420U; + SCE->REG_ECH = 0x00000004U; + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000021U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + for(iLoop=0; iLoop<12; iLoop=iLoop+1) + { + SCE->REG_ECH = 0x0000381fU; + for(jLoop=0; jLoop<32; jLoop=jLoop+1) + { + SCE->REG_24H = 0x0000102cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x3800d81fU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + SCE->REG_ECH = 0x00016c00U; + HW_SCE_p_func100(0xb98a5e65U, 0x7f275f73U, 0x9cfc058fU, 0x029d0986U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_24H = 0x0000082cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x100019b1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019a1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func101(0x5c352e63U, 0x01718940U, 0xa21bf0d2U, 0x9b357fa4U); + } + else + { + HW_SCE_p_func101(0x87581703U, 0xdadbeb82U, 0xb54bc2daU, 0x0e18a892U); + } + } + SCE->REG_ECH = 0x000027e1U; + HW_SCE_p_func101(0x42b94e70U, 0x15021ce2U, 0xa4e120a5U, 0xe8ce4451U); + } + SCE->REG_ECH = 0x00008be0U; + SCE->REG_ECH = 0x00000030U; + SCE->REG_ECH = 0x00007c1fU; + SCE->REG_1CH = 0x00602000U; + HW_SCE_p_func301(); + HW_SCE_p_func100(0xd221f12aU, 0x8f809485U, 0xbdd11068U, 0xc2e99e57U); + SCE->REG_2CH = 0x00000022U; + SCE->REG_04H = 0x00000332U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_R[0] = SCE->REG_100H; + OutData_R[1] = SCE->REG_100H; + OutData_R[2] = SCE->REG_100H; + OutData_R[3] = SCE->REG_100H; + OutData_R[4] = SCE->REG_100H; + OutData_R[5] = SCE->REG_100H; + OutData_R[6] = SCE->REG_100H; + OutData_R[7] = SCE->REG_100H; + OutData_R[8] = SCE->REG_100H; + OutData_R[9] = SCE->REG_100H; + OutData_R[10] = SCE->REG_100H; + OutData_R[11] = SCE->REG_100H; + HW_SCE_p_func100(0x737697f2U, 0x294324f6U, 0xcced2a97U, 0x97fef40dU); + SCE->REG_2CH = 0x00000023U; + SCE->REG_04H = 0x00000332U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_R[12] = SCE->REG_100H; + OutData_R[13] = SCE->REG_100H; + OutData_R[14] = SCE->REG_100H; + OutData_R[15] = SCE->REG_100H; + OutData_R[16] = SCE->REG_100H; + OutData_R[17] = SCE->REG_100H; + OutData_R[18] = SCE->REG_100H; + OutData_R[19] = SCE->REG_100H; + OutData_R[20] = SCE->REG_100H; + OutData_R[21] = SCE->REG_100H; + OutData_R[22] = SCE->REG_100H; + OutData_R[23] = SCE->REG_100H; + HW_SCE_p_func102(0xb255ae22U, 0x8346c84fU, 0x1e2c6dfeU, 0x73ce09e5U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_p9b_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pf5.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pf5.c new file mode 100644 index 000000000..30ab09445 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pf5.c @@ -0,0 +1,783 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_EcdsaP384SignatureGenerateSub(uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, uint32_t *OutData_Signature) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000f501U; + SCE->REG_108H = 0x00000000U; + OFS_ADR = 692; + SCE->REG_28H = 0x008b0001U; + HW_SCE_p_func100(0xdcffa28eU, 0x3b124252U, 0x9c56daa6U, 0xa0a325e6U); + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_ECH = 0x38000f5aU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000002B4U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000003D8U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + HW_SCE_p_func100(0xc2379776U, 0xc6886cddU, 0x49548f5bU, 0xef210a72U); + HW_SCE_p_func027_r1(OFS_ADR); + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000030U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x0000002aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_p_func103(); + HW_SCE_p_func100(0x00891242U, 0x098749a7U, 0xb379086bU, 0xcf4cefe6U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + SCE->REG_2CH = 0x00000011U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_p_func103(); + HW_SCE_p_func100(0xa1ba6586U, 0xf49b066dU, 0xc684308fU, 0x4d9b5195U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_p_func103(); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000b208U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + HW_SCE_p_func100(0xba1527c2U, 0x62526b31U, 0x67f6fac7U, 0xadaf0d0aU); + HW_SCE_p_func028_r1(OFS_ADR); + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000024U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000dcd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000f008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00001030U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + HW_SCE_p_func100(0xac49d836U, 0xa6347bb2U, 0xe4fd07e0U, 0xac5c1528U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xd7a56479U, 0xcfe92545U, 0x28bf174cU, 0xda2bbfe6U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x315a0e5bU, 0x787f3611U, 0xcb74434eU, 0xd052c6a5U); + SCE->REG_24H = 0x00009cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800054d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x000000b0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800050d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800074d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00029008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000c0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a8d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000030U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004808U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + HW_SCE_p_func100(0xb0030b73U, 0x59f35448U, 0x8c833b7aU, 0xf292daecU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x201068b6U, 0xcbbff743U, 0x67ec1dc2U, 0x1b5eb020U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x1487243cU, 0x2e285b4eU, 0xf25d4c34U, 0x3bb709c8U); + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800068d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x000000b8U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_ECH = 0x0000b7e0U; + SCE->REG_ECH = 0x00000030U; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x8000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000011U; + SCE->REG_104H = 0x00000b67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MsgDgst[0]; + SCE->REG_100H = InData_MsgDgst[1]; + SCE->REG_100H = InData_MsgDgst[2]; + SCE->REG_100H = InData_MsgDgst[3]; + SCE->REG_100H = InData_MsgDgst[4]; + SCE->REG_100H = InData_MsgDgst[5]; + SCE->REG_100H = InData_MsgDgst[6]; + SCE->REG_100H = InData_MsgDgst[7]; + SCE->REG_100H = InData_MsgDgst[8]; + SCE->REG_100H = InData_MsgDgst[9]; + SCE->REG_100H = InData_MsgDgst[10]; + SCE->REG_100H = InData_MsgDgst[11]; + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x8000aa0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_C4H = 0x200c3b0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + HW_SCE_p_func076(); + SCE->REG_C4H = 0x000c0b0cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000b62U; + SCE->REG_D0H = 0x00000200U; + SCE->REG_C4H = 0x02f087bfU; + SCE->REG_00H = 0x00003233U; + SCE->REG_2CH = 0x00000018U; + for (iLoop = 0; iLoop < 12; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[iLoop+4 + 0]; + SCE->REG_100H = InData_KeyIndex[iLoop+4 + 1]; + SCE->REG_100H = InData_KeyIndex[iLoop+4 + 2]; + SCE->REG_100H = InData_KeyIndex[iLoop+4 + 3]; + } + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_C4H = 0x000007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[16]; + SCE->REG_100H = InData_KeyIndex[17]; + SCE->REG_100H = InData_KeyIndex[18]; + SCE->REG_100H = InData_KeyIndex[19]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_p_func100(0x4e681996U, 0xc2c24190U, 0x024c3916U, 0x51361411U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xce403bb5U, 0x42dc2b57U, 0x82151e0aU, 0xa8eb60a1U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + SCE->REG_24H = 0x000015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x80006c0dU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x80004c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + HW_SCE_p_func100(0xb51f10abU, 0x6f7da746U, 0x0d6660b4U, 0x03ade7e4U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xc5905cc1U, 0x5899e5ebU, 0x4046fe43U, 0x90d357b1U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x5cc53079U, 0x68cbccd3U, 0x3469c512U, 0x244a0a8dU); + SCE->REG_2CH = 0x0000002bU; + SCE->REG_04H = 0x00000332U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Signature[0] = SCE->REG_100H; + OutData_Signature[1] = SCE->REG_100H; + OutData_Signature[2] = SCE->REG_100H; + OutData_Signature[3] = SCE->REG_100H; + OutData_Signature[4] = SCE->REG_100H; + OutData_Signature[5] = SCE->REG_100H; + OutData_Signature[6] = SCE->REG_100H; + OutData_Signature[7] = SCE->REG_100H; + OutData_Signature[8] = SCE->REG_100H; + OutData_Signature[9] = SCE->REG_100H; + OutData_Signature[10] = SCE->REG_100H; + OutData_Signature[11] = SCE->REG_100H; + HW_SCE_p_func100(0x5b24f09bU, 0x63acbd9bU, 0xa0a22b9bU, 0x34a33de4U); + SCE->REG_2CH = 0x0000002aU; + SCE->REG_04H = 0x00000332U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_Signature[12] = SCE->REG_100H; + OutData_Signature[13] = SCE->REG_100H; + OutData_Signature[14] = SCE->REG_100H; + OutData_Signature[15] = SCE->REG_100H; + OutData_Signature[16] = SCE->REG_100H; + OutData_Signature[17] = SCE->REG_100H; + OutData_Signature[18] = SCE->REG_100H; + OutData_Signature[19] = SCE->REG_100H; + OutData_Signature[20] = SCE->REG_100H; + OutData_Signature[21] = SCE->REG_100H; + OutData_Signature[22] = SCE->REG_100H; + OutData_Signature[23] = SCE->REG_100H; + HW_SCE_p_func102(0xda13650fU, 0xb3a825ecU, 0x3587bd1dU, 0x95de94feU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pf5_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pf6.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pf6.c new file mode 100644 index 000000000..ed1ee7042 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pf6.c @@ -0,0 +1,1419 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_EcdsaP384SignatureVerificationSub(uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, const uint32_t *InData_Signature) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B8H & 0x1eU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000f601U; + SCE->REG_108H = 0x00000000U; + HW_SCE_p_func100(0x9151283eU, 0x1730f9d9U, 0x174bb376U, 0x9b046b10U); + SCE->REG_28H = 0x008b0001U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + SCE->REG_ECH = 0x38000f5aU; + SCE->REG_ECH = 0x00030020U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000002B4U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_ECH = 0x0000b400U; + SCE->REG_ECH = 0x000003D8U; + SCE->REG_ECH = 0x00000080U; + SCE->REG_E0H = 0x81010000U; + SCE->REG_04H = 0x00000606U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + S_RAM[0] = change_endian_long(SCE->REG_100H); + OFS_ADR = S_RAM[0]; + HW_SCE_p_func027_r1(OFS_ADR); + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x808c001fU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000024U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000030U; + SCE->REG_E0H = 0x808c000aU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000025U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_E0H = 0x808c000aU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x0000002aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000090U; + SCE->REG_E0H = 0x808c000aU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_2CH = 0x00000015U; + SCE->REG_104H = 0x00000b67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Signature[0]; + SCE->REG_100H = InData_Signature[1]; + SCE->REG_100H = InData_Signature[2]; + SCE->REG_100H = InData_Signature[3]; + SCE->REG_100H = InData_Signature[4]; + SCE->REG_100H = InData_Signature[5]; + SCE->REG_100H = InData_Signature[6]; + SCE->REG_100H = InData_Signature[7]; + SCE->REG_100H = InData_Signature[8]; + SCE->REG_100H = InData_Signature[9]; + SCE->REG_100H = InData_Signature[10]; + SCE->REG_100H = InData_Signature[11]; + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00000b67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_Signature[12]; + SCE->REG_100H = InData_Signature[13]; + SCE->REG_100H = InData_Signature[14]; + SCE->REG_100H = InData_Signature[15]; + SCE->REG_100H = InData_Signature[16]; + SCE->REG_100H = InData_Signature[17]; + SCE->REG_100H = InData_Signature[18]; + SCE->REG_100H = InData_Signature[19]; + SCE->REG_100H = InData_Signature[20]; + SCE->REG_100H = InData_Signature[21]; + SCE->REG_100H = InData_Signature[22]; + SCE->REG_100H = InData_Signature[23]; + SCE->REG_24H = 0x000070d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8002d008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00008cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000d91U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x00000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001191U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + HW_SCE_p_func100(0xd1cc16e3U, 0x511835c0U, 0x7c9aea8eU, 0x070ed57fU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x98678558U, 0xa9476a3cU, 0xfdb96de2U, 0x874b6a7cU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xd94f3b34U, 0xb35da964U, 0x98a410c2U, 0xd2245b63U); + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00000030U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + HW_SCE_p_func100(0xc0627bb2U, 0x747e9b17U, 0xe2ec8cafU, 0x22cda26fU); + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x000000C0U; + SCE->REG_E0H = 0x808c000aU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00004c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_2CH = 0x00000010U; + SCE->REG_104H = 0x00000b67U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_MsgDgst[0]; + SCE->REG_100H = InData_MsgDgst[1]; + SCE->REG_100H = InData_MsgDgst[2]; + SCE->REG_100H = InData_MsgDgst[3]; + SCE->REG_100H = InData_MsgDgst[4]; + SCE->REG_100H = InData_MsgDgst[5]; + SCE->REG_100H = InData_MsgDgst[6]; + SCE->REG_100H = InData_MsgDgst[7]; + SCE->REG_100H = InData_MsgDgst[8]; + SCE->REG_100H = InData_MsgDgst[9]; + SCE->REG_100H = InData_MsgDgst[10]; + SCE->REG_100H = InData_MsgDgst[11]; + SCE->REG_24H = 0x0000ac0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000e0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000030U; + SCE->REG_E0H = 0x818c0008U; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8002d008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000090U; + SCE->REG_E0H = 0x818c0008U; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_p_func028_r1(OFS_ADR); + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x800088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000802U; + SCE->REG_24H = 0x8000acd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000030U; + SCE->REG_E0H = 0x808c000aU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000025U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000f008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00001030U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_ECH = 0x00000a73U; + SCE->REG_ECH = 0x0000b660U; + SCE->REG_ECH = 0x00000030U; + SCE->REG_E0H = 0x818c0013U; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + HW_SCE_p_func100(0xbe023b56U, 0x5df8c8daU, 0x8205d4bbU, 0x748075baU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x4d7b3a82U, 0x40c88903U, 0x04c56751U, 0x714e7c2aU); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x7688362aU, 0x92b36136U, 0x2e1711e6U, 0x28b818f1U); + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000090U; + SCE->REG_E0H = 0x818c0008U; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x0000001bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80004cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00000030U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006c0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00006e0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000015c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000f008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_C4H = 0x200c3b0dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[0]; + SCE->REG_100H = InData_KeyIndex[1]; + SCE->REG_100H = InData_KeyIndex[2]; + SCE->REG_100H = InData_KeyIndex[3]; + HW_SCE_p_func077(); + SCE->REG_C4H = 0x000c0b0cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00001362U; + SCE->REG_D0H = 0x00000400U; + SCE->REG_C4H = 0x02f0888fU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[4]; + SCE->REG_100H = InData_KeyIndex[5]; + SCE->REG_100H = InData_KeyIndex[6]; + SCE->REG_100H = InData_KeyIndex[7]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[8]; + SCE->REG_100H = InData_KeyIndex[9]; + SCE->REG_100H = InData_KeyIndex[10]; + SCE->REG_100H = InData_KeyIndex[11]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[12]; + SCE->REG_100H = InData_KeyIndex[13]; + SCE->REG_100H = InData_KeyIndex[14]; + SCE->REG_100H = InData_KeyIndex[15]; + SCE->REG_00H = 0x00003233U; + SCE->REG_2CH = 0x00000010U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[16]; + SCE->REG_100H = InData_KeyIndex[17]; + SCE->REG_100H = InData_KeyIndex[18]; + SCE->REG_100H = InData_KeyIndex[19]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[20]; + SCE->REG_100H = InData_KeyIndex[21]; + SCE->REG_100H = InData_KeyIndex[22]; + SCE->REG_100H = InData_KeyIndex[23]; + SCE->REG_00H = 0x00003223U; + SCE->REG_2CH = 0x00000019U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x0045094cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x00f0088dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[24]; + SCE->REG_100H = InData_KeyIndex[25]; + SCE->REG_100H = InData_KeyIndex[26]; + SCE->REG_100H = InData_KeyIndex[27]; + SCE->REG_00H = 0x00003213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000362U; + SCE->REG_C4H = 0x00000885U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyIndex[28]; + SCE->REG_100H = InData_KeyIndex[29]; + SCE->REG_100H = InData_KeyIndex[30]; + SCE->REG_100H = InData_KeyIndex[31]; + SCE->REG_C4H = 0x00900c45U; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_p_func100(0x964d6df3U, 0xfdaf9476U, 0xa79978daU, 0x4c3deefaU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xd1230000U, 0x0e915cb1U, 0xe2df9a02U, 0x115d8499U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_KEY_SET_FAIL; + } + else + { + HW_SCE_p_func100(0xf5daca07U, 0xf0c8b223U, 0xd9231b25U, 0xb1303664U); + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800094d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800060c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x800009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x800080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b540U; + SCE->REG_ECH = 0x00000030U; + SCE->REG_E0H = 0x808c000aU; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000022U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x800c0000U; + SCE->REG_00H = 0x00008333U; + SCE->REG_2CH = 0x00000023U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00001030U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + HW_SCE_p_func100(0xb79d6a97U, 0x6785fd50U, 0xfb134760U, 0xd4ddc48aU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x8836183fU, 0xf13ee801U, 0xab482af0U, 0x71f3af41U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + SCE->REG_ECH = 0x0000b660U; + SCE->REG_ECH = 0x00000030U; + SCE->REG_E0H = 0x818c0013U; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x0000001aU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_E0H = 0x810c0000U; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x0000001bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00003000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + HW_SCE_p_func100(0x25191405U, 0xeb9063b6U, 0xf3725753U, 0x68fb593eU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x1d145709U, 0xd9e261e1U, 0x7b3ab3baU, 0x7d900cc1U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x1e2fa550U, 0xef0a35e1U, 0xc33ba0c8U, 0x0a9a0224U); + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000090U; + SCE->REG_E0H = 0x818c0008U; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x0000001bU; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80004cd0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000080c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000591U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_18H = 0x00000004U; + SCE->REG_38H = 0x00000030U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B10) + { + /* waiting */ + } + SCE->REG_18H = 0x00000000U; + SCE->REG_34H = 0x00000002U; + SCE->REG_24H = 0x80000dc0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000a0c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000008U; + SCE->REG_24H = 0x800011c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000040c1U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00004a0cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x0000480cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x00000bffU; + SCE->REG_E0H = 0x818c001fU; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000084d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_34H = 0x00000800U; + SCE->REG_24H = 0x8002d008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x000088d0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b500U; + SCE->REG_ECH = 0x00000060U; + SCE->REG_E0H = 0x818c0008U; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000012U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x0000880cU; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00005008U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_ECH = 0x0000b660U; + SCE->REG_ECH = 0x000000C0U; + SCE->REG_E0H = 0x818c0013U; + SCE->REG_00H = 0x00003833U; + SCE->REG_2CH = 0x00000014U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_24H = 0x000009c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00001991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + SCE->REG_24H = 0x000019c0U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_24H = 0x00000991U; + /* WAIT_LOOP */ + while (0U != SCE->REG_24H_b.B21) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001f00U; + SCE->REG_1CH = 0x00210000U; + HW_SCE_p_func100(0xd3675573U, 0x5335a30dU, 0xb79fcce4U, 0xf345a276U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x07a19aafU, 0x7b236021U, 0x67cfd46aU, 0xdc5a7466U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func102(0xef6ba964U, 0x1eef2861U, 0x1f03fce6U, 0xfc02fe18U); + SCE->REG_1B8H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + } + } + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pf6_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pf8.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pf8.c new file mode 100644 index 000000000..a6ce4251e --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pf8.c @@ -0,0 +1,601 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateEccP384PrivateKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_CurveType, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B4H & 0x1dU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000f801U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800103e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38000fffU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + HW_SCE_p_func100(0x8052bd39U, 0x9b8e4481U, 0xfe79f9c8U, 0xc6d66098U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(InData_SharedKeyIndex[0]); + SCE->REG_ECH = 0x38008c00U; + SCE->REG_ECH = 0xfffffff0U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_p_func100(0x33c6bb43U, 0x5af630c7U, 0x371e2132U, 0x4f3bddaaU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xb5b276a3U, 0x4149f52cU, 0xb558c94aU, 0x9f612396U); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xd535fa74U, 0x59d665e6U, 0xe64c0e1eU, 0xe7f7f75aU); + OFS_ADR = InData_SharedKeyIndex[0]*8; + SCE->REG_C4H = 0x000c3b0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x3b74d08aU); + SCE->REG_C4H = 0x000c0b0cU; + SCE->REG_E0H = 0x81010000U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x02fb073dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH[OFS_ADR + 0]; + SCE->REG_100H = S_FLASH[OFS_ADR + 1]; + SCE->REG_100H = S_FLASH[OFS_ADR + 2]; + SCE->REG_100H = S_FLASH[OFS_ADR + 3]; + HW_SCE_p_func100(0x9c7fab69U, 0x9e7d7723U, 0xa0631460U, 0x56fbae5dU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 0]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 1]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 2]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 3]; + SCE->REG_A4H = 0x00800c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00087a05U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SessionKey[0]; + SCE->REG_100H = InData_SessionKey[1]; + SCE->REG_100H = InData_SessionKey[2]; + SCE->REG_100H = InData_SessionKey[3]; + HW_SCE_p_func100(0x1deb110aU, 0x989ca753U, 0xa037316bU, 0xd744ca5eU); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00097a05U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SessionKey[4]; + SCE->REG_100H = InData_SessionKey[5]; + SCE->REG_100H = InData_SessionKey[6]; + SCE->REG_100H = InData_SessionKey[7]; + HW_SCE_p_func100(0xb7349d8aU, 0x914d1862U, 0x6859e962U, 0x29ab22d0U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x9e40f5dcU, 0xbfda1eb6U, 0x05e3580eU, 0x17b9d59fU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x200c3b0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + HW_SCE_p_func076(); + SCE->REG_C4H = 0x000c0b0cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00002133U; + SCE->REG_104H = 0x00000b61U; + SCE->REG_B0H = 0x00000200U; + SCE->REG_A4H = 0x00d0c9a7U; + SCE->REG_D0H = 0x00000200U; + SCE->REG_C4H = 0x02e087bfU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[4]; + SCE->REG_100H = InData_InstData[5]; + SCE->REG_100H = InData_InstData[6]; + SCE->REG_100H = InData_InstData[7]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[8]; + SCE->REG_100H = InData_InstData[9]; + SCE->REG_100H = InData_InstData[10]; + SCE->REG_100H = InData_InstData[11]; + SCE->REG_04H = 0x00000232U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[12] = SCE->REG_100H; + OutData_KeyIndex[13] = SCE->REG_100H; + OutData_KeyIndex[14] = SCE->REG_100H; + OutData_KeyIndex[15] = SCE->REG_100H; + HW_SCE_p_func100(0xdd08c6b4U, 0xff921d20U, 0x49b917c5U, 0x596c76eeU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x000009cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[16] = SCE->REG_100H; + OutData_KeyIndex[17] = SCE->REG_100H; + OutData_KeyIndex[18] = SCE->REG_100H; + OutData_KeyIndex[19] = SCE->REG_100H; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000049a5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[12]; + SCE->REG_100H = InData_InstData[13]; + SCE->REG_100H = InData_InstData[14]; + SCE->REG_100H = InData_InstData[15]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_p_func100(0x46170f44U, 0xadc7464fU, 0xb2bfce2bU, 0x5d5ee84fU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0xf63ae5cdU, 0x5d44985fU, 0x7ee99dd1U, 0x05241b0eU); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x8e36e2b5U, 0x15e6773aU, 0x50e5276dU, 0x58bca833U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_p_func102(0xbf05242bU, 0x9fd1762dU, 0xf25f4ed9U, 0xd485bcd5U); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + else + { + HW_SCE_p_func100(0x7b140caaU, 0x15251b13U, 0xafc65209U, 0x0483dde0U); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x73554942U, 0xd100328aU, 0x4b1226feU, 0x9f1fe5c3U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x200c3b0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + HW_SCE_p_func076(); + SCE->REG_C4H = 0x000c0b0cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00002133U; + SCE->REG_104H = 0x00000b61U; + SCE->REG_B0H = 0x00000200U; + SCE->REG_A4H = 0x00008887U; + SCE->REG_D0H = 0x00000200U; + SCE->REG_C4H = 0x02e087bfU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[4]; + SCE->REG_100H = InData_InstData[5]; + SCE->REG_100H = InData_InstData[6]; + SCE->REG_100H = InData_InstData[7]; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[8]; + SCE->REG_100H = InData_InstData[9]; + SCE->REG_100H = InData_InstData[10]; + SCE->REG_100H = InData_InstData[11]; + SCE->REG_04H = 0x00000232U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[4] = SCE->REG_100H; + OutData_KeyIndex[5] = SCE->REG_100H; + OutData_KeyIndex[6] = SCE->REG_100H; + OutData_KeyIndex[7] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[8] = SCE->REG_100H; + OutData_KeyIndex[9] = SCE->REG_100H; + OutData_KeyIndex[10] = SCE->REG_100H; + OutData_KeyIndex[11] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[12] = SCE->REG_100H; + OutData_KeyIndex[13] = SCE->REG_100H; + OutData_KeyIndex[14] = SCE->REG_100H; + OutData_KeyIndex[15] = SCE->REG_100H; + HW_SCE_p_func100(0x557db3e4U, 0x4685d111U, 0x0d6655feU, 0xe82d6a28U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_C4H = 0x000009cdU; + SCE->REG_00H = 0x00002213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[16] = SCE->REG_100H; + OutData_KeyIndex[17] = SCE->REG_100H; + OutData_KeyIndex[18] = SCE->REG_100H; + OutData_KeyIndex[19] = SCE->REG_100H; + HW_SCE_p_func100(0xa6d30775U, 0x7a70cda9U, 0xda932db6U, 0xb4a25d38U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_p_func102(0x643baeb2U, 0x2ef10054U, 0xa20e6e2aU, 0x12984445U); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pf8_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pfb.c b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pfb.c new file mode 100644 index 000000000..82012d269 --- /dev/null +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/primitive/hw_sce_p_pfb.c @@ -0,0 +1,643 @@ +/*********************************************************************************************************************** +* DISCLAIMER +* This software is supplied by Renesas Electronics Corporation and is only intended for use with Renesas products. No +* other uses are authorized. This software is owned by Renesas Electronics Corporation and is protected under all +* applicable laws, including copyright laws. +* THIS SOFTWARE IS PROVIDED AND RENESAS MAKES NO WARRANTIES REGARDING +* THIS SOFTWARE, WHETHER EXPRESS, IMPLIED OR STATUTORY, INCLUDING BUT NOT LIMITED TO WARRANTIES OF MERCHANTABILITY, +* FITNESS FOR A PARTICULAR PURPOSE AND NON-INFRINGEMENT. ALL SUCH WARRANTIES ARE EXPRESSLY DISCLAIMED. TO THE MAXIMUM +* EXTENT PERMITTED NOT PROHIBITED BY LAW, NEITHER RENESAS ELECTRONICS CORPORATION NOR ANY OF ITS AFFILIATED COMPANIES +* SHALL BE LIABLE FOR ANY DIRECT, INDIRECT, SPECIAL, INCIDENTAL OR CONSEQUENTIAL DAMAGES FOR ANY REASON RELATED TO THIS +* SOFTWARE, EVEN IF RENESAS OR ITS AFFILIATES HAVE BEEN ADVISED OF THE POSSIBILITY OF SUCH DAMAGES. +* Renesas reserves the right, without notice, to make changes to this software and to discontinue the availability of +* this software. By using this software, you agree to the additional terms and conditions found by accessing the +* following link: +* http://www.renesas.com/disclaimer +* +* Copyright (C) 2020 Renesas Electronics Corporation. All rights reserved. +***********************************************************************************************************************/ +/*********************************************************************************************************************** + * History : DD.MM.YYYY Version Description + * : 05.10.2020 1.00 First Release. + * : 02.12.2020 1.01 Added new functions such as the Brainpool curve. +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Includes , "Project Includes" +***********************************************************************************************************************/ +#include "r_sce_if.h" +#include "hw_sce_ra_private.h" + +/*********************************************************************************************************************** +Macro definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Typedef definitions +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Imported global variables and functions (from other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Exported global variables (to be accessed by other files) +***********************************************************************************************************************/ + +/*********************************************************************************************************************** +Private global variables and functions +***********************************************************************************************************************/ + +fsp_err_t HW_SCE_GenerateEccP384PublicKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_CurveType, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex) +{ + uint32_t iLoop = 0U; + uint32_t iLoop1 = 0U; + uint32_t iLoop2 = 0U; + int32_t jLoop = 0U; + uint32_t kLoop = 0U; + uint32_t oLoop = 0U; + uint32_t oLoop1 = 0U; + uint32_t oLoop2 = 0U; + uint32_t dummy = 0U; + uint32_t KEY_ADR = 0U; + uint32_t OFS_ADR = 0U; + uint32_t MAX_CNT2 = 0U; + (void)iLoop; + (void)iLoop1; + (void)iLoop2; + (void)jLoop; + (void)kLoop; + (void)oLoop; + (void)oLoop1; + (void)oLoop2; + (void)dummy; + (void)KEY_ADR; + (void)OFS_ADR; + (void)MAX_CNT2; + if (0x0U != (SCE->REG_1B4H & 0x1dU)) + { + return FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT; + } + SCE->REG_84H = 0x0000fb01U; + SCE->REG_108H = 0x00000000U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x800103e0U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_KeyType[0]; + SCE->REG_ECH = 0x38000fffU; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00260000U; + HW_SCE_p_func100(0xe9b91863U, 0xde4bcb57U, 0x071d4ab2U, 0xc458cec7U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010000U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(InData_SharedKeyIndex[0]); + SCE->REG_ECH = 0x38008c00U; + SCE->REG_ECH = 0xfffffff0U; + SCE->REG_E0H = 0x00000080U; + SCE->REG_1CH = 0x00A60000U; + HW_SCE_p_func100(0x590bdb24U, 0x6c3cc6a1U, 0x23999b8dU, 0x7933b1f8U); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x514eb0d1U, 0xe858d792U, 0xea0040f7U, 0x517d7b03U); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0x26fabe19U, 0x17e9ea7eU, 0x3b34a8e4U, 0x093aea0cU); + OFS_ADR = InData_SharedKeyIndex[0]*8; + SCE->REG_C4H = 0x000c3b0cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x3b74d08aU); + SCE->REG_C4H = 0x000c0b0cU; + SCE->REG_E0H = 0x81010000U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x02fb073dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH[OFS_ADR + 0]; + SCE->REG_100H = S_FLASH[OFS_ADR + 1]; + SCE->REG_100H = S_FLASH[OFS_ADR + 2]; + SCE->REG_100H = S_FLASH[OFS_ADR + 3]; + HW_SCE_p_func100(0x9e02fcafU, 0x1aa4c357U, 0xb881a811U, 0x12b23ce6U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000007bdU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 0]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 1]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 2]; + SCE->REG_100H = S_FLASH[OFS_ADR+4 + 3]; + SCE->REG_A4H = 0x00800c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00087a05U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SessionKey[0]; + SCE->REG_100H = InData_SessionKey[1]; + SCE->REG_100H = InData_SessionKey[2]; + SCE->REG_100H = InData_SessionKey[3]; + HW_SCE_p_func100(0x9a0bf8d2U, 0xc237d1b5U, 0x80f51df0U, 0x2f6e0538U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00097a05U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_SessionKey[4]; + SCE->REG_100H = InData_SessionKey[5]; + SCE->REG_100H = InData_SessionKey[6]; + SCE->REG_100H = InData_SessionKey[7]; + HW_SCE_p_func100(0x70f98d57U, 0xde61fd45U, 0x9115dbc9U, 0x8cb7fc66U); + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00040805U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_IV[0]; + SCE->REG_100H = InData_IV[1]; + SCE->REG_100H = InData_IV[2]; + SCE->REG_100H = InData_IV[3]; + SCE->REG_104H = 0x00000051U; + SCE->REG_A4H = 0x00050804U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + HW_SCE_p_func103(); + HW_SCE_p_func100(0xcda9b575U, 0x2e962503U, 0x9e2315bcU, 0x0fce4654U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x200c3b0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + HW_SCE_p_func077(); + SCE->REG_C4H = 0x000c0b0cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00002153U; + SCE->REG_104H = 0x00000031U; + SCE->REG_B0H = 0x00000400U; + SCE->REG_A4H = 0x00d0c9a7U; + SCE->REG_D0H = 0x00000400U; + SCE->REG_C4H = 0x02e0888fU; + SCE->REG_04H = 0x00000252U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + for (iLoop = 4; iLoop < 20 ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[iLoop + 0]; + SCE->REG_100H = InData_InstData[iLoop + 1]; + SCE->REG_100H = InData_InstData[iLoop + 2]; + SCE->REG_100H = InData_InstData[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[iLoop + 0] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 1] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 2] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[iLoop + 0] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 1] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 2] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 3] = SCE->REG_100H; + SCE->REG_104H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_C8H_b.B6) + { + /* waiting */ + } + HW_SCE_p_func100(0x3978fe82U, 0x23f45210U, 0x6a5eb6fbU, 0x5c37e13bU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x0045094cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00002113U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00d049a5U; + SCE->REG_C4H = 0x00e0088dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[20]; + SCE->REG_100H = InData_InstData[21]; + SCE->REG_100H = InData_InstData[22]; + SCE->REG_100H = InData_InstData[23]; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[24] = SCE->REG_100H; + OutData_KeyIndex[25] = SCE->REG_100H; + OutData_KeyIndex[26] = SCE->REG_100H; + OutData_KeyIndex[27] = SCE->REG_100H; + HW_SCE_p_func100(0xb186d35dU, 0x87eb91f6U, 0x7ab4d83cU, 0x95b6848dU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000cc4U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[28] = SCE->REG_100H; + OutData_KeyIndex[29] = SCE->REG_100H; + OutData_KeyIndex[30] = SCE->REG_100H; + OutData_KeyIndex[31] = SCE->REG_100H; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x000049a5U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[24]; + SCE->REG_100H = InData_InstData[25]; + SCE->REG_100H = InData_InstData[26]; + SCE->REG_100H = InData_InstData[27]; + SCE->REG_A4H = 0x00900c45U; + SCE->REG_00H = 0x00001113U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + HW_SCE_p_func100(0x035f7777U, 0x6baa9b6fU, 0xf7e39f9cU, 0x1ca8e74bU); + SCE->REG_1CH = 0x00400000U; + SCE->REG_1D0H = 0x00000000U; + if (1U == (SCE->REG_1CH_b.B22)) + { + HW_SCE_p_func102(0x9802c674U, 0xac883a02U, 0x33a331b1U, 0x74b0f19eU); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_ERR_CRYPTO_SCE_FAIL; + } + else + { + HW_SCE_p_func100(0xfdbef610U, 0x415da158U, 0x1ed011e9U, 0x6c78b280U); + SCE->REG_E0H = 0x81040000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_p_func102(0x92c0bc24U, 0xd21ed2abU, 0xe688a0a6U, 0xf9c31ea4U); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } + } + } + else + { + HW_SCE_p_func100(0x62d7d7cbU, 0xffb6ea53U, 0x9248abf9U, 0xa34aeffbU); + HW_SCE_p_func103(); + HW_SCE_p_func100(0x76805b29U, 0xc74e2316U, 0xbd4e8619U, 0x3adc602dU); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x01000c84U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_E0H = 0x80040000U; + SCE->REG_00H = 0x00008213U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_A4H = 0x200c3b0dU; + SCE->REG_E0H = 0x81040000U; + SCE->REG_00H = 0x00001813U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_104H = 0x00000068U; + SCE->REG_E0H = 0x80010340U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_CurveType[0]; + HW_SCE_p_func077(); + SCE->REG_C4H = 0x000c0b0cU; + SCE->REG_E0H = 0x810103c0U; + SCE->REG_00H = 0x00002807U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + SCE->REG_00H = 0x00002153U; + SCE->REG_104H = 0x00000031U; + SCE->REG_B0H = 0x00000400U; + SCE->REG_A4H = 0x00008887U; + SCE->REG_D0H = 0x00000400U; + SCE->REG_C4H = 0x02e0888fU; + SCE->REG_04H = 0x00000252U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[0]; + SCE->REG_100H = InData_InstData[1]; + SCE->REG_100H = InData_InstData[2]; + SCE->REG_100H = InData_InstData[3]; + for (iLoop = 4; iLoop < 20 ; iLoop = iLoop + 4) + { + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[iLoop + 0]; + SCE->REG_100H = InData_InstData[iLoop + 1]; + SCE->REG_100H = InData_InstData[iLoop + 2]; + SCE->REG_100H = InData_InstData[iLoop + 3]; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[iLoop + 0] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 1] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 2] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 3] = SCE->REG_100H; + } + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[iLoop + 0] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 1] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 2] = SCE->REG_100H; + OutData_KeyIndex[iLoop + 3] = SCE->REG_100H; + SCE->REG_104H = 0x00000000U; + /* WAIT_LOOP */ + while (0U != SCE->REG_00H_b.B25) + { + /* waiting */ + } + SCE->REG_1CH = 0x00001800U; + /* WAIT_LOOP */ + while (0U != SCE->REG_C8H_b.B6) + { + /* waiting */ + } + HW_SCE_p_func100(0xe9322bf3U, 0x3e1722e8U, 0xda682408U, 0xe33534f4U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x0045094cU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_00H = 0x00002113U; + SCE->REG_104H = 0x00000361U; + SCE->REG_A4H = 0x00000885U; + SCE->REG_C4H = 0x00e0088dU; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = InData_InstData[20]; + SCE->REG_100H = InData_InstData[21]; + SCE->REG_100H = InData_InstData[22]; + SCE->REG_100H = InData_InstData[23]; + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[24] = SCE->REG_100H; + OutData_KeyIndex[25] = SCE->REG_100H; + OutData_KeyIndex[26] = SCE->REG_100H; + OutData_KeyIndex[27] = SCE->REG_100H; + HW_SCE_p_func100(0xc4e143d0U, 0x6da34913U, 0x3ec2f188U, 0x040f1b63U); + SCE->REG_104H = 0x00000052U; + SCE->REG_C4H = 0x00000cc4U; + /* WAIT_LOOP */ + while (1U != SCE->REG_104H_b.B31) + { + /* waiting */ + } + SCE->REG_100H = change_endian_long(0x00000000U); + SCE->REG_04H = 0x00000212U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[28] = SCE->REG_100H; + OutData_KeyIndex[29] = SCE->REG_100H; + OutData_KeyIndex[30] = SCE->REG_100H; + OutData_KeyIndex[31] = SCE->REG_100H; + HW_SCE_p_func100(0x79d7dcc4U, 0xb946e80aU, 0xb7b9e4b5U, 0x4a049bfcU); + SCE->REG_E0H = 0x81040000U; + SCE->REG_04H = 0x00000612U; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[0] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[1] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[2] = SCE->REG_100H; + /* WAIT_LOOP */ + while (1U != SCE->REG_04H_b.B30) + { + /* waiting */ + } + OutData_KeyIndex[3] = SCE->REG_100H; + HW_SCE_p_func102(0x521dc8e1U, 0x2cfe7212U, 0x45eaef36U, 0xc36d24b3U); + SCE->REG_1B4H = 0x00000040U; + /* WAIT_LOOP */ + while (0U != SCE->REG_18H_b.B12) + { + /* waiting */ + } + return FSP_SUCCESS; + } +} + +/*********************************************************************************************************************** +End of function ./input_dir/HW_SCE/HW_SCEp/HW_SCEp_pfb_r1.prc +***********************************************************************************************************************/ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h index 15e8bfbc9..c3233d55d 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/private/inc/hw_sce_ra_private.h @@ -62,6 +62,14 @@ #define SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED (512) #define SIZE_AES_256BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 8) #define SIZE_AES_256BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 32) + + #define SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED (416) + #define SIZE_AES_XTS_128BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 8) + #define SIZE_AES_XTS_128BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 32) + + #define SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED (672) + #define SIZE_AES_XTS_256BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 8) + #define SIZE_AES_XTS_256BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 32) /** Return RSA wrapped private key size in bytes from the specified RSA modulus size in bits */ #define RSA_WRAPPED_PRIVATE_KEY_SIZE_BYTES(RSA_SIZE_BITS) (800U) @@ -335,8 +343,8 @@ fsp_err_t HW_SCE_Ecc256ScalarMultiplicationSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_PubKey, uint32_t *OutData_R); fsp_err_t HW_SCE_Ecc384ScalarMultiplicationPrivate(uint32_t *InData_CurveType, uint32_t *InData_KeyIndex, uint32_t *InData_PubKey, uint32_t *OutData_R); -//fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSub(const uint32_t *InData_CurveType, -// const uint32_t *InData_KeyIndex, const uint32_t *InData_PubKey, uint32_t *OutData_R); +fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSub(const uint32_t *InData_CurveType, + const uint32_t *InData_KeyIndex, const uint32_t *InData_PubKey, uint32_t *OutData_R); fsp_err_t HW_SCE_TdesEcbEncryptInitPrivate(sce_tdes_key_index_t *key_index); fsp_err_t HW_SCE_TdesEcbEncryptUpdatePrivate(uint32_t *InData_Text, uint32_t *OutData_Text, uint32_t MAX_CNT); @@ -444,10 +452,9 @@ fsp_err_t HW_SCE_GenerateTlsP256EccKeyIndexSub(uint32_t *OutData_KeyIndex, uint3 fsp_err_t HW_SCE_GenerateEccPrivateKeyIndexSub(const uint32_t * const InData_KeyType, const uint32_t * const InData_SharedKeyIndex, const uint32_t * const InData_SessionKey, const uint32_t * const InData_CurveType, const uint32_t * const InData_Cmd, const uint32_t * const InData_IV, const uint32_t * const InData_InstData, uint32_t *const OutData_KeyIndex); -fsp_err_t HW_SCE_GenerateEccP384PrivateKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, - uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateEccP384PrivateKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_CurveType, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); fsp_err_t HW_SCE_GenerateEccPublicKeyIndexSub(const uint32_t * const InData_KeyType, const uint32_t * const InData_SharedKeyIndex, const uint32_t * const InData_SessionKey, const uint32_t * const InData_CurveType, const uint32_t * const InData_Cmd, const uint32_t * const InData_IV, const uint32_t * const InData_InstData, uint32_t * const OutData_KeyIndex); -fsp_err_t HW_SCE_GenerateEccP384PublicKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_GenerateEccP384PublicKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, uint32_t *InData_CurveType, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); fsp_err_t HW_SCE_GenerateEccRandomKeyIndexSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyType, uint32_t *OutData_PubKeyIndex, uint32_t *OutData_PubKey, uint32_t *OutData_PrivKeyIndex, uint32_t *OutData_PrivKey); fsp_err_t HW_SCE_GenerateEccP384RandomKeyIndexSub(const uint32_t *InData_CurveType, const uint32_t *InData_KeyType, uint32_t *OutData_PubKeyIndex, uint32_t *OutData_PubKey, uint32_t *OutData_PrivKeyIndex, uint32_t *OutData_PrivKey); fsp_err_t HW_SCE_GenerateShaHmacKeyIndexSub(uint32_t *InData_KeyType, uint32_t *InData_SharedKeyIndex, uint32_t *InData_SessionKey, @@ -482,10 +489,8 @@ fsp_err_t HW_SCE_UpdateEccPrivateKeyIndexSub(const uint32_t * const InData_Curve const uint32_t * const InData_InstData, uint32_t * const OutData_KeyIndex); fsp_err_t HW_SCE_UpdateEccPublicKeyIndexSub(const uint32_t * const InData_CurveType, const uint32_t * const InData_Cmd, const uint32_t * const InData_IV, const uint32_t * const InData_InstData, uint32_t * const OutData_KeyIndex); -fsp_err_t HW_SCE_UpdateEccP384PrivateKeyIndexSub(uint32_t *InData_IV, - uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); -fsp_err_t HW_SCE_UpdateEccP384PublicKeyIndexSub(uint32_t *InData_IV, - uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateEccP384PrivateKeyIndexSub(uint32_t *InData_CurveType, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); +fsp_err_t HW_SCE_UpdateEccP384PublicKeyIndexSub(uint32_t *InData_CurveType, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); fsp_err_t HW_SCE_UpdateShaHmacKeyIndexSub(uint32_t *InData_Cmd, uint32_t *InData_IV, uint32_t *InData_InstData, uint32_t *OutData_KeyIndex); @@ -674,12 +679,10 @@ fsp_err_t HW_SCE_Rsa4096ModularExponentDecryptSub(uint32_t *InData_KeyIndex, uin fsp_err_t HW_SCE_EcdsaSignatureGenerateSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, uint32_t *OutData_Signature); -// fsp_err_t HW_SCE_EcdsaP384SignatureGenerateSub(const uint32_t *InData_KeyIndex, -// const uint32_t *InData_MsgDgst, uint32_t *OutData_Signature); +fsp_err_t HW_SCE_EcdsaP384SignatureGenerateSub(uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, uint32_t *OutData_Signature); fsp_err_t HW_SCE_EcdsaSignatureVerificationSub(const uint32_t *InData_CurveType, const uint32_t *InData_Cmd, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, const uint32_t *InData_Signature); -// fsp_err_t HW_SCE_EcdsaP384SignatureVerificationSub(const uint32_t *InData_KeyIndex, -// const uint32_t *InData_MsgDgst, const uint32_t *InData_Signature); +fsp_err_t HW_SCE_EcdsaP384SignatureVerificationSub(uint32_t *InData_CurveType, const uint32_t *InData_KeyIndex, const uint32_t *InData_MsgDgst, const uint32_t *InData_Signature); fsp_err_t HW_SCE_DlmsCosemQeuSignatureVerificationSub(uint32_t *InData_Cmd, uint32_t *InData_KeyIndex, uint32_t *InData_data, uint32_t *InData_Signature, uint32_t *OutData_KeyIndex); fsp_err_t HW_SCE_DlmsCosemQevSignatureGenerationSub(uint32_t *InData_Cmd, uint32_t *InData_KeyType, diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/public/inc/r_sce_if.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/public/inc/r_sce_if.h index 55470d8ac..478daf15f 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/public/inc/r_sce_if.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce7/plainkey/public/inc/r_sce_if.h @@ -64,6 +64,8 @@ #define HW_SCE_AES_CCM_COUNTER_BYTE_SIZE (16U) #define HW_SCE_AES128XTS_KEY_BYTE_SIZE (32U) #define HW_SCE_AES256XTS_KEY_BYTE_SIZE (64U) +#define HW_SCE_AES128XTS_KEY_BIT_SIZE (256U) +#define HW_SCE_AES256XTS_KEY_BIT_SIZE (512U) #define HW_SCE_AES_XTS_IV_BYTE_SIZE (16U) /* For TDES operation. */ diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h index e77fc7ddb..f4d6afac8 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/private/inc/hw_sce_ra_private.h @@ -61,6 +61,14 @@ #define SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED (416) #define SIZE_AES_256BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 8) #define SIZE_AES_256BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED) / 32) + + #define SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED (416) + #define SIZE_AES_XTS_128BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 8) + #define SIZE_AES_XTS_128BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED) / 32) + + #define SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED (672) + #define SIZE_AES_XTS_256BIT_KEYLEN_BYTES_WRAPPED ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 8) + #define SIZE_AES_XTS_256BIT_KEYLEN_WORDS_WRAPPED ((SIZE_AES_XTS_256BIT_KEYLEN_BITS_WRAPPED) / 32) /** Return RSA wrapped private key size in bytes from the specified RSA modulus size in bits. * This is the size of sce_rsa2048_private_key_index_t. diff --git a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/public/inc/r_sce_if.h b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/public/inc/r_sce_if.h index 8ae24a5af..d57861ada 100644 --- a/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/public/inc/r_sce_if.h +++ b/ra/fsp/src/r_sce/crypto_procedures/src/sce9/plainkey/public/inc/r_sce_if.h @@ -92,6 +92,8 @@ #define HW_SCE_AES_CCM_COUNTER_BYTE_SIZE (16U) #define HW_SCE_AES128XTS_KEY_BYTE_SIZE (32U) #define HW_SCE_AES256XTS_KEY_BYTE_SIZE (64U) +#define HW_SCE_AES128XTS_KEY_BIT_SIZE (256U) +#define HW_SCE_AES256XTS_KEY_BIT_SIZE (512U) #define HW_SCE_AES_XTS_IV_BYTE_SIZE (16U) /* For TDES operation. */ @@ -179,6 +181,8 @@ #define HW_SCE_RSA_2048_DATA_BYTE_SIZE (256U) #define HW_SCE_RSA_3072_DATA_BYTE_SIZE (96 * 4U) #define HW_SCE_RSA_4096_DATA_BYTE_SIZE (128 * 4U) +#define HW_SCE_RSA2048_RANDOM_PRIVATE_KEY_BYTE_SIZE (64U * 4U) +#define HW_SCE_RSA2048_RANDOM_PUBLIC_KEY_BYTE_SIZE (65U * 4U) /* RSA HASH type. */ #define HW_SCE_RSA_HASH_MD5 (0x01) /* MD5 */ @@ -496,6 +500,12 @@ typedef struct sce_rsa2048_public_key_index uint32_t key_management_info2[HW_SCE_RSA_2048_PUBLIC_KEY_MANAGEMENT_INFO2_WORD_SIZE]; } value; + struct + { + uint8_t key[HW_SCE_RSA2048_RANDOM_PUBLIC_KEY_BYTE_SIZE]; + } + plain_value; + } sce_rsa2048_public_key_index_t; /* RSA 2048bit private key index data structure */ @@ -509,6 +519,11 @@ typedef struct sce_rsa2048_private_key_index uint32_t key_management_info2[HW_SCE_RSA_2048_PRIVATE_KEY_MANAGEMENT_INFO2_WORD_SIZE]; } value; + struct + { + uint8_t key[HW_SCE_RSA2048_RANDOM_PRIVATE_KEY_BYTE_SIZE]; + } + plain_value; } sce_rsa2048_private_key_index_t; /* RSA 3072bit public key index data structure */ diff --git a/ra/fsp/src/r_sce/hw_sce_ecc_private.h b/ra/fsp/src/r_sce/hw_sce_ecc_private.h index a27b097b1..c342a4b7b 100644 --- a/ra/fsp/src/r_sce/hw_sce_ecc_private.h +++ b/ra/fsp/src/r_sce/hw_sce_ecc_private.h @@ -60,7 +60,7 @@ #define HW_SCE_ECC_WRAPPED_KEY_ADJUST(x) ((x) + ((HW_SCE_PRIVATE_KEY_WRAPPING_WORD_SIZE) * 4)) /* Function pointer declarations */ -#if BSP_FEATURE_CRYPTO_HAS_SCE9 +#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7 #define ECC_PUBLIC_KEY_SIZE_BYTES(curve_size) (curve_size * 2 + 20U) typedef fsp_err_t (* hw_sce_ecc_scalarmultiplication_t)(const uint32_t * InData_CurveType, const uint32_t * InData_Cmd, const uint32_t * InData_K, const uint32_t * InData_P, diff --git a/ra/fsp/src/r_sce/hw_sce_private.h b/ra/fsp/src/r_sce/hw_sce_private.h index d628de11a..802016dfc 100644 --- a/ra/fsp/src/r_sce/hw_sce_private.h +++ b/ra/fsp/src/r_sce/hw_sce_private.h @@ -32,7 +32,7 @@ ***********************************************************************************************************************/ #include "bsp_api.h" #include "hw_sce_common.h" -#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 +#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 #include "r_sce_if.h" #include "hw_sce_ra_private.h" #endif diff --git a/ra/fsp/src/r_sce/ra2/adaptors/r_sce_if.h b/ra/fsp/src/r_sce/ra2/adaptors/r_sce_if.h index 4c6ba8a15..e0eedd109 100644 --- a/ra/fsp/src/r_sce/ra2/adaptors/r_sce_if.h +++ b/ra/fsp/src/r_sce/ra2/adaptors/r_sce_if.h @@ -40,6 +40,10 @@ #ifndef R_SCE_IF_HEADER_FILE #define R_SCE_IF_HEADER_FILE + +#define HW_SCE_AES128XTS_KEY_BIT_SIZE (256U) +#define HW_SCE_AES256XTS_KEY_BIT_SIZE (512U) + /* OEM Command */ typedef enum e_sce_oem_cmd { diff --git a/ra/fsp/src/r_sce_key_injection/r_sce_key_injection.c b/ra/fsp/src/r_sce_key_injection/r_sce_key_injection.c index 4d060a0e3..742ead9e6 100644 --- a/ra/fsp/src/r_sce_key_injection/r_sce_key_injection.c +++ b/ra/fsp/src/r_sce_key_injection/r_sce_key_injection.c @@ -84,15 +84,33 @@ const sce_key_injection_api_t g_sce_key_injection_on_sce = .AES128_EncryptedKeyWrap = R_SCE_AES128_EncryptedKeyWrap, .AES256_EncryptedKeyWrap = R_SCE_AES256_EncryptedKeyWrap, #endif +#if ((SCE7) || (SCE9)) + .RSA2048_InitialPublicKeyWrap = R_SCE_RSA2048_InitialPublicKeyWrap, + .RSA2048_InitialPrivateKeyWrap = R_SCE_RSA2048_InitialPrivateKeyWrap, +#endif +#if (SCE9) + .RSA3072_InitialPublicKeyWrap = R_SCE_RSA3072_InitialPublicKeyWrap, + .RSA4096_InitialPublicKeyWrap = R_SCE_RSA4096_InitialPublicKeyWrap, +#endif +#if (SCE7) + .RSA2048_EncryptedPublicKeyWrap = R_SCE_RSA2048_EncryptedPublicKeyWrap, + .RSA2048_EncryptedPrivateKeyWrap = R_SCE_RSA2048_EncryptedPrivateKeyWrap, +#endif +#if ((SCE7) || (SCE9)) + .ECC_secp256r1_InitialPublicKeyWrap = R_SCE_ECC_secp256r1_InitialPublicKeyWrap, + .ECC_secp256r1_InitialPrivateKeyWrap = R_SCE_ECC_secp256r1_InitialPrivateKeyWrap, + .ECC_secp384r1_InitialPublicKeyWrap = R_SCE_ECC_secp384r1_InitialPublicKeyWrap, + .ECC_secp384r1_InitialPrivateKeyWrap = R_SCE_ECC_secp384r1_InitialPrivateKeyWrap, + .ECC_secp256k1_InitialPublicKeyWrap = R_SCE_ECC_secp256k1_InitialPublicKeyWrap, + .ECC_secp256k1_InitialPrivateKeyWrap = R_SCE_ECC_secp256k1_InitialPrivateKeyWrap, +#endif #if (SCE7) - .RSA2048_InitialPublicKeyWrap = R_SCE_RSA2048_InitialPublicKeyWrap, - .RSA2048_InitialPrivateKeyWrap = R_SCE_RSA2048_InitialPrivateKeyWrap, - .RSA2048_EncryptedPublicKeyWrap = R_SCE_RSA2048_EncryptedPublicKeyWrap, - .RSA2048_EncryptedPrivateKeyWrap = R_SCE_RSA2048_EncryptedPrivateKeyWrap, - .ECC_secp256r1_InitialPublicKeyWrap = R_SCE_ECC_secp256r1_InitialPublicKeyWrap, - .ECC_secp256r1_InitialPrivateKeyWrap = R_SCE_ECC_secp256r1_InitialPrivateKeyWrap, .ECC_secp256r1_EncryptedPublicKeyWrap = R_SCE_ECC_secp256r1_EncryptedPublicKeyWrap, .ECC_secp256r1_EncryptedPrivateKeyWrap = R_SCE_ECC_secp256r1_EncryptedPrivateKeyWrap, + .ECC_secp384r1_EncryptedPublicKeyWrap = R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap, + .ECC_secp384r1_EncryptedPrivateKeyWrap = R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap, + .ECC_secp256k1_EncryptedPublicKeyWrap = R_SCE_ECC_secp256k1_EncryptedPublicKeyWrap, + .ECC_secp256k1_EncryptedPrivateKeyWrap = R_SCE_ECC_secp256k1_EncryptedPrivateKeyWrap #endif }; @@ -517,6 +535,30 @@ fsp_err_t R_SCE_RSA2048_InitialPublicKeyWrap (const uint8_t * const (uint32_t *) initial_vector, (uint32_t *) encrypted_key, (uint32_t *) &wrapped_key->value); +#elif (SCE9) + uint32_t indata_keytype = 0; + uint32_t indata_cmd = 0; + uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX; + + indata_cmd = SCE_OEM_CMD_RSA2048_PUBLIC; + indata_keytype = change_endian_long((uint32_t) (*key_type)); + + if (0 == *key_type) + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd]; + } + else + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd] - 4; + } + + error_code = HW_SCE_GenerateOemKeyIndexSub(&indata_keytype, + &indata_cmd, + &install_key_ring_index, + (uint32_t *) wrapped_user_factory_programming_key, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + (uint32_t *) &wrapped_key->value); #else error_code = FSP_ERR_UNSUPPORTED; @@ -539,6 +581,160 @@ fsp_err_t R_SCE_RSA2048_InitialPublicKeyWrap (const uint8_t * const return error_code; } +/*******************************************************************************************************************//** + * This API generates 3072-bit RSA key within the user routine. + * + * @param[in] key_type Selection key type when generating wrapped key + * (0: for encrypted key, 1: for plain key) + * @param[in] wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key_type is 1 as plain key, this is not required and + * any value can be specified. + * @param[in] initial_vector Initialization vector when generating encrypted_key. + * When key_type is 1 as plain key, this is not required and + * any value can be specified. + * @param[in] encrypted_key Encrypted user key and MAC appended + * @param[in,out] wrapped_key 3072-bit RSA wrapped key + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_UNSUPPORTED API not supported. + * @return If an error occurs, the return value will be as follows. + * * FSP_ERR_CRYPTO_SCE_FAIL Internal I/O buffer is not empty. + * * FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSA3072_InitialPublicKeyWrap (const uint8_t * const key_type, + const uint8_t * const wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_rsa3072_public_wrapped_key_t * const wrapped_key) +{ + fsp_err_t error_code = FSP_SUCCESS; + +#if (SCE9) + uint32_t indata_keytype = 0; + uint32_t indata_cmd = 0; + uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX; + + indata_cmd = SCE_OEM_CMD_RSA3072_PUBLIC; + indata_keytype = change_endian_long((uint32_t) (*key_type)); + + if (0 == *key_type) + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd]; + } + else + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd] - 4; + } + + error_code = HW_SCE_GenerateOemKeyIndexSub(&indata_keytype, + &indata_cmd, + &install_key_ring_index, + (uint32_t *) wrapped_user_factory_programming_key, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + (uint32_t *) &wrapped_key->value); +#else + error_code = FSP_ERR_UNSUPPORTED; + + FSP_PARAMETER_NOT_USED(key_type); + FSP_PARAMETER_NOT_USED(wrapped_user_factory_programming_key); + FSP_PARAMETER_NOT_USED(initial_vector); + FSP_PARAMETER_NOT_USED(encrypted_key); + FSP_PARAMETER_NOT_USED(wrapped_key); +#endif + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_RSA3072_PUBLIC; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API generates 4096-bit RSA key within the user routine. + * + * @param[in] key_type Selection key type when generating wrapped key + * (0: for encrypted key, 1: for plain key) + * @param[in] wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key_type is 1 as plain key, this is not required and + * any value can be specified. + * @param[in] initial_vector Initialization vector when generating encrypted_key. + * When key_type is 1 as plain key, this is not required and + * any value can be specified. + * @param[in] encrypted_key Encrypted user key and MAC appended + * @param[in,out] wrapped_key 4096-bit RSA wrapped key + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_UNSUPPORTED API not supported. + * @return If an error occurs, the return value will be as follows. + * * FSP_ERR_CRYPTO_SCE_FAIL Internal I/O buffer is not empty. + * * FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_RSA4096_InitialPublicKeyWrap (const uint8_t * const key_type, + const uint8_t * const wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_rsa4096_public_wrapped_key_t * const wrapped_key) +{ + fsp_err_t error_code = FSP_SUCCESS; + +#if (SCE9) + uint32_t indata_keytype = 0; + uint32_t indata_cmd = 0; + uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX; + + indata_cmd = SCE_OEM_CMD_RSA4096_PUBLIC; + indata_keytype = change_endian_long((uint32_t) (*key_type)); + + if (0 == *key_type) + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd]; + } + else + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd] - 4; + } + + error_code = HW_SCE_GenerateOemKeyIndexSub(&indata_keytype, + &indata_cmd, + &install_key_ring_index, + (uint32_t *) wrapped_user_factory_programming_key, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + (uint32_t *) &wrapped_key->value); +#else + error_code = FSP_ERR_UNSUPPORTED; + + FSP_PARAMETER_NOT_USED(key_type); + FSP_PARAMETER_NOT_USED(wrapped_user_factory_programming_key); + FSP_PARAMETER_NOT_USED(initial_vector); + FSP_PARAMETER_NOT_USED(encrypted_key); + FSP_PARAMETER_NOT_USED(wrapped_key); +#endif + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_RSA4096_PUBLIC; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + /*******************************************************************************************************************//** * This API generates 2048-bit RSA key within the user routine. * @@ -582,6 +778,30 @@ fsp_err_t R_SCE_RSA2048_InitialPrivateKeyWrap (const uint8_t * const (uint32_t *) initial_vector, (uint32_t *) encrypted_key, (uint32_t *) &wrapped_key->value); +#elif (SCE9) + uint32_t indata_keytype = 0; + uint32_t indata_cmd = 0; + uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX; + + indata_cmd = SCE_OEM_CMD_RSA2048_PRIVATE; + indata_keytype = change_endian_long((uint32_t) (*key_type)); + + if (0 == *key_type) + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd]; + } + else + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd] - 4; + } + + error_code = HW_SCE_GenerateOemKeyIndexSub(&indata_keytype, + &indata_cmd, + &install_key_ring_index, + (uint32_t *) wrapped_user_factory_programming_key, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + (uint32_t *) &wrapped_key->value); #else error_code = FSP_ERR_UNSUPPORTED; @@ -742,10 +962,12 @@ fsp_err_t R_SCE_ECC_secp256r1_InitialPublicKeyWrap (const uint8_t * const #if (SCE7) uint32_t indata_keytype = 0; uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX; - uint32_t indata_cmd = change_endian_long(0); /* P-256 */; - uint32_t indata_curve_type = change_endian_long(0); /* NIST */; + uint32_t indata_cmd = 0; + uint32_t indata_curve_type = 0; - indata_keytype = change_endian_long((uint32_t) (*key_type)); + indata_cmd = change_endian_long(0); /* P-256 */; + indata_curve_type = change_endian_long(0); /* NIST */; + indata_keytype = change_endian_long((uint32_t) (*key_type)); error_code = HW_SCE_GenerateEccPublicKeyIndexSub(&indata_keytype, &install_key_ring_index, @@ -755,6 +977,31 @@ fsp_err_t R_SCE_ECC_secp256r1_InitialPublicKeyWrap (const uint8_t * const (uint32_t *) initial_vector, (uint32_t *) encrypted_key, (uint32_t *) &wrapped_key->value); +#elif (SCE9) + uint32_t indata_keytype = 0; + uint32_t indata_cmd = 0; + uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX; + + indata_cmd = SCE_OEM_CMD_ECC_P256_PUBLIC; + + indata_keytype = change_endian_long((uint32_t) (*key_type)); + + if (0 == *key_type) + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd]; + } + else + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd] - 4; + } + + error_code = HW_SCE_GenerateOemKeyIndexSub(&indata_keytype, + &indata_cmd, + &install_key_ring_index, + (uint32_t *) wrapped_user_factory_programming_key, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + (uint32_t *) &wrapped_key->value); #else error_code = FSP_ERR_UNSUPPORTED; @@ -800,30 +1047,57 @@ fsp_err_t R_SCE_ECC_secp256r1_InitialPublicKeyWrap (const uint8_t * const * @note The pre-run state is SCE Enabled State. * After the function runs the state transitions to SCE Enabled State. **********************************************************************************************************************/ -fsp_err_t R_SCE_ECC_secp256r1_InitialPrivateKeyWrap (const uint8_t * const key_type, - const uint8_t * const wrapped_user_factory_programming_key, - const uint8_t * const initial_vector, - const uint8_t * const encrypted_key, - sce_ecc_private_wrapped_key_t * const wrapped_key) +fsp_err_t R_SCE_ECC_secp256k1_InitialPublicKeyWrap (const uint8_t * const key_type, + const uint8_t * const wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_ecc_public_wrapped_key_t * const wrapped_key) { fsp_err_t error_code = FSP_SUCCESS; #if (SCE7) uint32_t indata_keytype = 0; uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX; - uint32_t indata_cmd = change_endian_long(0); /* P-256 */; - uint32_t indata_curve_type = change_endian_long(0); /* NIST */; + uint32_t indata_cmd = 0; + uint32_t indata_curve_type = 0; + + indata_cmd = change_endian_long((uint32_t) SCE_OEM_CMD_ECC_SECP256K1_PUBLIC); + indata_curve_type = change_endian_long((uint32_t) 0x2); /* 2:Koblitz */ + indata_keytype = change_endian_long((uint32_t) (*key_type)); + + error_code = HW_SCE_GenerateEccPublicKeyIndexSub(&indata_keytype, + &install_key_ring_index, + (uint32_t *) wrapped_user_factory_programming_key, + &indata_curve_type, + &indata_cmd, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + (uint32_t *) &wrapped_key->value); +#elif (SCE9) + uint32_t indata_keytype = 0; + uint32_t indata_cmd = 0; + uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX; + + indata_cmd = SCE_OEM_CMD_ECC_SECP256K1_PUBLIC; indata_keytype = change_endian_long((uint32_t) (*key_type)); - error_code = HW_SCE_GenerateEccPrivateKeyIndexSub(&indata_keytype, - &install_key_ring_index, - (uint32_t *) wrapped_user_factory_programming_key, - &indata_curve_type, - &indata_cmd, - (uint32_t *) initial_vector, - (uint32_t *) encrypted_key, - wrapped_key->value); + if (0 == *key_type) + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd]; + } + else + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd] - 4; + } + + error_code = HW_SCE_GenerateOemKeyIndexSub(&indata_keytype, + &indata_cmd, + &install_key_ring_index, + (uint32_t *) wrapped_user_factory_programming_key, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + (uint32_t *) &wrapped_key->value); #else error_code = FSP_ERR_UNSUPPORTED; @@ -836,7 +1110,7 @@ fsp_err_t R_SCE_ECC_secp256r1_InitialPrivateKeyWrap (const uint8_t * const if (FSP_SUCCESS == error_code) { - wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P256_PRIVATE; + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PUBLIC; } else { @@ -847,7 +1121,383 @@ fsp_err_t R_SCE_ECC_secp256r1_InitialPrivateKeyWrap (const uint8_t * const } /*******************************************************************************************************************//** - * This API wraps 256-bit ECC key within the user routine. + * This API generates 384-bit ECC key within the user routine. + * + * @param[in] key_type Selection key type when generating wrapped key + * (0: for encrypted key, 1: for plain key) + * @param[in] wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key_type is 1 as plain key, this is not required and + * any value can be specified. + * @param[in] initial_vector Initialization vector when generating encrypted_key. + * When key_type is 1 as plain key, this is not required and + * any value can be specified. + * @param[in] encrypted_key Encrypted user key and MAC appended + * @param[in,out] wrapped_key 364-bit ECC wrapped key + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_UNSUPPORTED API not supported. + * @return If an error occurs, the return value will be as follows. + * * FSP_ERR_CRYPTO_SCE_FAIL Internal I/O buffer is not empty. + * * FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp384r1_InitialPublicKeyWrap (const uint8_t * const key_type, + const uint8_t * const wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_ecc_public_wrapped_key_t * const wrapped_key) +{ + fsp_err_t error_code = FSP_SUCCESS; + +#if (SCE7) + uint32_t indata_keytype = 0; + uint32_t install_key_ring_index = 0; + uint32_t indata_curve_type = 0; + + install_key_ring_index = change_endian_long((uint32_t) R_SCE_INSTALL_KEY_RING_INDEX); + indata_curve_type = change_endian_long(0); /* NIST */; + indata_keytype = change_endian_long((uint32_t) (*key_type)); + + error_code = HW_SCE_GenerateEccP384PublicKeyIndexSub(&indata_keytype, + &install_key_ring_index, + (uint32_t *) wrapped_user_factory_programming_key, + &indata_curve_type, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + (uint32_t *) &wrapped_key->value); +#elif (SCE9) + uint32_t indata_keytype = 0; + uint32_t indata_cmd = 0; + uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX; + + indata_cmd = SCE_OEM_CMD_ECC_P384_PUBLIC; + + indata_keytype = change_endian_long((uint32_t) (*key_type)); + + if (0 == *key_type) + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd]; + } + else + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd] - 4; + } + + error_code = HW_SCE_GenerateOemKeyIndexSub(&indata_keytype, + &indata_cmd, + &install_key_ring_index, + (uint32_t *) wrapped_user_factory_programming_key, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + (uint32_t *) &wrapped_key->value); +#else + error_code = FSP_ERR_UNSUPPORTED; + + FSP_PARAMETER_NOT_USED(key_type); + FSP_PARAMETER_NOT_USED(wrapped_user_factory_programming_key); + FSP_PARAMETER_NOT_USED(initial_vector); + FSP_PARAMETER_NOT_USED(encrypted_key); + FSP_PARAMETER_NOT_USED(wrapped_key); +#endif + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P384_PUBLIC; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API generates 256-bit ECC key within the user routine. + * + * @param[in] key_type Selection key type when generating wrapped key + * (0: for encrypted key, 1: for plain key) + * @param[in] wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key_type is 1 as plain key, this is not required and + * any value can be specified. + * @param[in] initial_vector Initialization vector when generating encrypted_key. + * When key_type is 1 as plain key, this is not required and + * any value can be specified. + * @param[in] encrypted_key Encrypted user key and MAC appended + * @param[in,out] wrapped_key 256-bit ECC wrapped key + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_UNSUPPORTED API not supported. + * @return If an error occurs, the return value will be as follows. + * * FSP_ERR_CRYPTO_SCE_FAIL Internal I/O buffer is not empty. + * * FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp256r1_InitialPrivateKeyWrap (const uint8_t * const key_type, + const uint8_t * const wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_ecc_private_wrapped_key_t * const wrapped_key) +{ + fsp_err_t error_code = FSP_SUCCESS; + +#if (SCE7) + uint32_t indata_keytype = 0; + uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX; + uint32_t indata_cmd = 0; + uint32_t indata_curve_type = 0; + + indata_cmd = change_endian_long(0); /* P-256 */; + indata_curve_type = change_endian_long(0); /* NIST */; + indata_keytype = change_endian_long((uint32_t) (*key_type)); + + error_code = HW_SCE_GenerateEccPrivateKeyIndexSub(&indata_keytype, + &install_key_ring_index, + (uint32_t *) wrapped_user_factory_programming_key, + &indata_curve_type, + &indata_cmd, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + wrapped_key->value); +#elif (SCE9) + uint32_t indata_keytype = 0; + uint32_t indata_cmd = 0; + uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX; + + indata_cmd = SCE_OEM_CMD_ECC_P256_PRIVATE; + indata_keytype = change_endian_long((uint32_t) (*key_type)); + + if (0 == *key_type) + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd]; + } + else + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd] - 4; + } + + error_code = HW_SCE_GenerateOemKeyIndexSub(&indata_keytype, + &indata_cmd, + &install_key_ring_index, + (uint32_t *) wrapped_user_factory_programming_key, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + (uint32_t *) &wrapped_key->value); +#else + error_code = FSP_ERR_UNSUPPORTED; + + FSP_PARAMETER_NOT_USED(key_type); + FSP_PARAMETER_NOT_USED(wrapped_user_factory_programming_key); + FSP_PARAMETER_NOT_USED(initial_vector); + FSP_PARAMETER_NOT_USED(encrypted_key); + FSP_PARAMETER_NOT_USED(wrapped_key); +#endif + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P256_PRIVATE; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API generates 256-bit ECC key within the user routine. + * + * @param[in] key_type Selection key type when generating wrapped key + * (0: for encrypted key, 1: for plain key) + * @param[in] wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key_type is 1 as plain key, this is not required and + * any value can be specified. + * @param[in] initial_vector Initialization vector when generating encrypted_key. + * When key_type is 1 as plain key, this is not required and + * any value can be specified. + * @param[in] encrypted_key Encrypted user key and MAC appended + * @param[in,out] wrapped_key 256-bit ECC wrapped key + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_UNSUPPORTED API not supported. + * @return If an error occurs, the return value will be as follows. + * * FSP_ERR_CRYPTO_SCE_FAIL Internal I/O buffer is not empty. + * * FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp256k1_InitialPrivateKeyWrap (const uint8_t * const key_type, + const uint8_t * const wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_ecc_private_wrapped_key_t * const wrapped_key) +{ + fsp_err_t error_code = FSP_SUCCESS; + +#if (SCE7) + uint32_t indata_keytype = 0; + uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX; + uint32_t indata_cmd = 0; + uint32_t indata_curve_type = 0; + + indata_cmd = change_endian_long((uint32_t) SCE_OEM_CMD_ECC_SECP256K1_PRIVATE); + indata_curve_type = change_endian_long((uint32_t) 0x2); /* 2:Koblitz */ + indata_keytype = change_endian_long((uint32_t) (*key_type)); + + error_code = HW_SCE_GenerateEccPrivateKeyIndexSub(&indata_keytype, + &install_key_ring_index, + (uint32_t *) wrapped_user_factory_programming_key, + &indata_curve_type, + &indata_cmd, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + wrapped_key->value); +#elif (SCE9) + uint32_t indata_keytype = 0; + uint32_t indata_cmd = 0; + uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX; + + indata_cmd = SCE_OEM_CMD_ECC_SECP256K1_PRIVATE; + indata_keytype = change_endian_long((uint32_t) (*key_type)); + + if (0 == *key_type) + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd]; + } + else + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd] - 4; + } + + error_code = HW_SCE_GenerateOemKeyIndexSub(&indata_keytype, + &indata_cmd, + &install_key_ring_index, + (uint32_t *) wrapped_user_factory_programming_key, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + (uint32_t *) &wrapped_key->value); +#else + error_code = FSP_ERR_UNSUPPORTED; + + FSP_PARAMETER_NOT_USED(key_type); + FSP_PARAMETER_NOT_USED(wrapped_user_factory_programming_key); + FSP_PARAMETER_NOT_USED(initial_vector); + FSP_PARAMETER_NOT_USED(encrypted_key); + FSP_PARAMETER_NOT_USED(wrapped_key); +#endif + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PRIVATE; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API generates 384-bit ECC key within the user routine. + * + * @param[in] key_type Selection key type when generating wrapped key + * (0: for encrypted key, 1: for plain key) + * @param[in] wrapped_user_factory_programming_key Wrapped user factory programming key by the Renesas Key Wrap Service. + * When key_type is 1 as plain key, this is not required and + * any value can be specified. + * @param[in] initial_vector Initialization vector when generating encrypted_key. + * When key_type is 1 as plain key, this is not required and + * any value can be specified. + * @param[in] encrypted_key Encrypted user key and MAC appended + * @param[in,out] wrapped_key 384-bit ECC wrapped key + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_UNSUPPORTED API not supported. + * @return If an error occurs, the return value will be as follows. + * * FSP_ERR_CRYPTO_SCE_FAIL Internal I/O buffer is not empty. + * * FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp384r1_InitialPrivateKeyWrap (const uint8_t * const key_type, + const uint8_t * const wrapped_user_factory_programming_key, + const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + sce_ecc_private_wrapped_key_t * const wrapped_key) +{ + fsp_err_t error_code = FSP_SUCCESS; + +#if (SCE7) + uint32_t indata_keytype = 0; + uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX; + uint32_t indata_curve_type = 0; + + indata_curve_type = change_endian_long(0); /* NIST */; + indata_keytype = change_endian_long((uint32_t) (*key_type)); + + error_code = HW_SCE_GenerateEccP384PrivateKeyIndexSub(&indata_keytype, + &install_key_ring_index, + (uint32_t *) wrapped_user_factory_programming_key, + &indata_curve_type, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + wrapped_key->value); +#elif (SCE9) + uint32_t indata_keytype = 0; + uint32_t indata_cmd = 0; + uint32_t install_key_ring_index = R_SCE_INSTALL_KEY_RING_INDEX; + + indata_cmd = SCE_OEM_CMD_ECC_P384_PRIVATE; + indata_keytype = change_endian_long((uint32_t) (*key_type)); + + if (0 == *key_type) + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd]; + } + else + { + INST_DATA_SIZE = sce_oem_key_size[indata_cmd] - 4; + } + + error_code = HW_SCE_GenerateOemKeyIndexSub(&indata_keytype, + &indata_cmd, + &install_key_ring_index, + (uint32_t *) wrapped_user_factory_programming_key, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + (uint32_t *) &wrapped_key->value); +#else + error_code = FSP_ERR_UNSUPPORTED; + + FSP_PARAMETER_NOT_USED(key_type); + FSP_PARAMETER_NOT_USED(wrapped_user_factory_programming_key); + FSP_PARAMETER_NOT_USED(initial_vector); + FSP_PARAMETER_NOT_USED(encrypted_key); + FSP_PARAMETER_NOT_USED(wrapped_key); +#endif + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P384_PRIVATE; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps 256-bit ECC key within the user routine. * * @param[in] initial_vector Initialization vector when generating encrypted_key * @param[in] encrypted_key User key encryptedand MAC appended @@ -871,8 +1521,11 @@ fsp_err_t R_SCE_ECC_secp256r1_EncryptedPublicKeyWrap (const uint8_t * const fsp_err_t error_code = FSP_SUCCESS; #if (SCE7) - uint32_t indata_cmd = change_endian_long(0); /* P-256 */ - uint32_t inData_curveType = change_endian_long(0); /* NIST */ + uint32_t indata_cmd = 0; + uint32_t inData_curveType = 0; + + indata_cmd = change_endian_long(0); /* P-256 */ + inData_curveType = change_endian_long(0); /* NIST */ memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); @@ -903,6 +1556,119 @@ fsp_err_t R_SCE_ECC_secp256r1_EncryptedPublicKeyWrap (const uint8_t * const return error_code; } +/*******************************************************************************************************************//** + * This API wraps 256-bit ECC key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 256-bit ECC wrapped key + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_UNSUPPORTED API not supported. + * @return If an error occurs, the return value will be as follows. + * * FSP_ERR_CRYPTO_SCE_FAIL Internal I/O buffer is not empty. + * * FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp256k1_EncryptedPublicKeyWrap (const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + const sce_key_update_key_t * const key_update_key, + sce_ecc_public_wrapped_key_t * const wrapped_key) +{ + fsp_err_t error_code = FSP_SUCCESS; + +#if (SCE7) + uint32_t indata_cmd = 0x0; /* P-256 */ + uint32_t indata_curve_type = 0; + + indata_curve_type = change_endian_long((uint32_t) 0x2); /* 2:Koblitz */ + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = + HW_SCE_UpdateEccPublicKeyIndexSub(&indata_curve_type, + &indata_cmd, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + (uint32_t *) &wrapped_key->value); +#else + error_code = FSP_ERR_UNSUPPORTED; + + FSP_PARAMETER_NOT_USED(initial_vector); + FSP_PARAMETER_NOT_USED(encrypted_key); + FSP_PARAMETER_NOT_USED(key_update_key); + FSP_PARAMETER_NOT_USED(wrapped_key); +#endif + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PUBLIC; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps 384-bit ECC key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 384-bit ECC wrapped key + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_UNSUPPORTED API not supported. + * @return If an error occurs, the return value will be as follows. + * * FSP_ERR_CRYPTO_SCE_FAIL Internal I/O buffer is not empty. + * * FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp384r1_EncryptedPublicKeyWrap (const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + const sce_key_update_key_t * const key_update_key, + sce_ecc_public_wrapped_key_t * const wrapped_key) +{ + fsp_err_t error_code = FSP_SUCCESS; + +#if (SCE7) + uint32_t inData_curveType = 0; + inData_curveType = change_endian_long(0); /* NIST */ + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = HW_SCE_UpdateEccP384PublicKeyIndexSub(&inData_curveType, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + (uint32_t *) &wrapped_key->value); +#else + error_code = FSP_ERR_UNSUPPORTED; + + FSP_PARAMETER_NOT_USED(initial_vector); + FSP_PARAMETER_NOT_USED(encrypted_key); + FSP_PARAMETER_NOT_USED(key_update_key); + FSP_PARAMETER_NOT_USED(wrapped_key); +#endif + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P384_PUBLIC; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + /*******************************************************************************************************************//** * This API wraps 256-bit ECC key within the user routine. * @@ -928,8 +1694,11 @@ fsp_err_t R_SCE_ECC_secp256r1_EncryptedPrivateKeyWrap (const uint8_t * const fsp_err_t error_code = FSP_SUCCESS; #if (SCE7) - uint32_t indata_cmd = change_endian_long(0); /* P-256 */ - uint32_t inData_curveType = change_endian_long(0); /* NIST */ + uint32_t indata_cmd = 0; + uint32_t inData_curveType = 0; + + indata_cmd = change_endian_long(0); /* P-256 */ + inData_curveType = change_endian_long(0); /* NIST */ memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); @@ -960,6 +1729,120 @@ fsp_err_t R_SCE_ECC_secp256r1_EncryptedPrivateKeyWrap (const uint8_t * const return error_code; } +/*******************************************************************************************************************//** + * This API wraps 256-bit ECC key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 256-bit ECC wrapped key + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_UNSUPPORTED API not supported. + * @return If an error occurs, the return value will be as follows. + * * FSP_ERR_CRYPTO_SCE_FAIL Internal I/O buffer is not empty. + * * FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp256k1_EncryptedPrivateKeyWrap (const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + const sce_key_update_key_t * const key_update_key, + sce_ecc_private_wrapped_key_t * const wrapped_key) +{ + fsp_err_t error_code = FSP_SUCCESS; + +#if (SCE7) + uint32_t indata_cmd = 0x0; /* P-256 */ + uint32_t indata_curve_type = 0; + + indata_curve_type = change_endian_long((uint32_t) 0x2); /* 2:Koblitz */ + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = + HW_SCE_UpdateEccPrivateKeyIndexSub(&indata_curve_type, + &indata_cmd, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + wrapped_key->value); +#else + error_code = FSP_ERR_UNSUPPORTED; + + FSP_PARAMETER_NOT_USED(initial_vector); + FSP_PARAMETER_NOT_USED(encrypted_key); + FSP_PARAMETER_NOT_USED(key_update_key); + FSP_PARAMETER_NOT_USED(wrapped_key); +#endif + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_SECP256K1_PRIVATE; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + +/*******************************************************************************************************************//** + * This API wraps 384-bit ECC key within the user routine. + * + * @param[in] initial_vector Initialization vector when generating encrypted_key + * @param[in] encrypted_key User key encryptedand MAC appended + * @param[in] key_update_key Key update keyring + * @param[in,out] wrapped_key 384-bit ECC wrapped key + * + * @retval FSP_SUCCESS Normal termination. + * @retval FSP_ERR_UNSUPPORTED API not supported. + * @return If an error occurs, the return value will be as follows. + * * FSP_ERR_CRYPTO_SCE_FAIL Internal I/O buffer is not empty. + * * FSP_ERR_CRYPTO_SCE_RESOURCE_CONFLICT A resource conflict occurred because a hardware resource needed. + * + * @note The pre-run state is SCE Enabled State. + * After the function runs the state transitions to SCE Enabled State. + **********************************************************************************************************************/ +fsp_err_t R_SCE_ECC_secp384r1_EncryptedPrivateKeyWrap (const uint8_t * const initial_vector, + const uint8_t * const encrypted_key, + const sce_key_update_key_t * const key_update_key, + sce_ecc_private_wrapped_key_t * const wrapped_key) +{ + fsp_err_t error_code = FSP_SUCCESS; + +#if (SCE7) + uint32_t inData_curveType = 0; + inData_curveType = change_endian_long(0); /* NIST */ + + memcpy(S_INST2, key_update_key->value, sizeof(S_INST2)); + + error_code = HW_SCE_UpdateEccP384PrivateKeyIndexSub(&inData_curveType, + (uint32_t *) initial_vector, + (uint32_t *) encrypted_key, + wrapped_key->value); +#else + error_code = FSP_ERR_UNSUPPORTED; + + FSP_PARAMETER_NOT_USED(initial_vector); + FSP_PARAMETER_NOT_USED(encrypted_key); + FSP_PARAMETER_NOT_USED(key_update_key); + FSP_PARAMETER_NOT_USED(wrapped_key); +#endif + + if (FSP_SUCCESS == error_code) + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_ECC_P384_PRIVATE; + } + else + { + wrapped_key->type = SCE_KEY_INDEX_TYPE_INVALID; + } + + return error_code; +} + /*******************************************************************************************************************//** * @} (end addtogroup SCE_KEY_INJECTION) **********************************************************************************************************************/ diff --git a/ra/fsp/src/r_usb_basic/r_usb_basic.c b/ra/fsp/src/r_usb_basic/r_usb_basic.c index 3e6021a7a..4ceafeb7f 100644 --- a/ra/fsp/src/r_usb_basic/r_usb_basic.c +++ b/ra/fsp/src/r_usb_basic/r_usb_basic.c @@ -50,7 +50,9 @@ #if defined(USB_CFG_HPRN_USE) #include "../../../microsoft/azure-rtos/usbx/common/usbx_host_classes/inc/ux_host_class_printer.h" #endif /* defined(USB_CFG_HPRN_USE) */ - + #if defined(USB_CFG_HUVC_USE) + #include "../../../microsoft/azure-rtos/usbx/common/usbx_host_classes/inc/ux_host_class_video.h" + #endif /* defined(USB_CFG_HUVC_USE) */ #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) #include "../../../microsoft/azure-rtos/usbx/common/usbx_host_classes/inc/ux_host_class_hub.h" #endif /* ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ @@ -118,13 +120,16 @@ /****************************************************************************** * Macro definitions ******************************************************************************/ -#define USB_VALUE_50 (50) -#define USB_VALUE_100 (100) -#define USB_VALUE_7FH (0x7F) -#define USB_VALUE_80H (0x80) -#define USB_VALUE_FFH (0xFF) +#define USB_VALUE_50 (50) +#define USB_VALUE_100 (100) +#define USB_VALUE_7FH (0x7F) +#define USB_VALUE_80H (0x80) +#define USB_VALUE_FFH (0xFF) + +#define USB_MASK_ALIGN_2_BYTE (0x1U) +#define USB_MASK_ALIGN_4_BYTE (0x3U) -#define USB_OTG_IRQ (0x7) +#define USB_OTG_IRQ (0x7) /****************************************************************************** * Exported global variables (to be accessed by other files) @@ -472,6 +477,7 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c case USB_CLASS_INTERNAL_HVND: case USB_CLASS_INTERNAL_HMSC: case USB_CLASS_INTERNAL_HPRN: + case USB_CLASS_INTERNAL_HUVC: { #if defined(BSP_MCU_GROUP_RA2A1) @@ -752,6 +758,26 @@ fsp_err_t R_USB_Open (usb_ctrl_t * const p_api_ctrl, usb_cfg_t const * const p_c } } #endif /* defined(USB_CFG_HPRN_USE) */ + #if defined(USB_CFG_HUVC_USE) + ux_host_stack_class_register(_ux_system_host_class_video_name, ux_host_class_video_entry); + if (USB_SPEED_HS == p_cfg->usb_speed) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_huvc_hs", usb_host_usbx_initialize, R_USB_HS0_BASE, 0); + } + else + { + if (USB_IP0 == p_cfg->module_number) + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_huvc_fs", usb_host_usbx_initialize, R_USB_FS0_BASE, + 0); + } + else + { + ux_host_stack_hcd_register((UCHAR *) "fsp_usbx_huvc_hs", usb_host_usbx_initialize, R_USB_HS0_BASE, + 0); + } + } + #endif /* defined(USB_CFG_HUVC_USE) */ #endif /* #if (BSP_CFG_RTOS == 0) */ } #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ @@ -1019,6 +1045,9 @@ fsp_err_t R_USB_Close (usb_ctrl_t * const p_api_ctrl) #if defined(USB_CFG_HPRN_USE) ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hprn_hs", R_USB_HS0_BASE, 0); #endif /* #if defined(USB_CFG_HPRN_USE) */ + #if defined(USB_CFG_HUVC_USE) + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_huvc_hs", R_USB_HS0_BASE, 0); + #endif /* #if defined(USB_CFG_HUVC_USE) */ usb_host_usbx_uninitialize(R_USB_HS0_BASE); } else @@ -1035,6 +1064,9 @@ fsp_err_t R_USB_Close (usb_ctrl_t * const p_api_ctrl) #if defined(USB_CFG_HPRN_USE) ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hprn_fs", R_USB_FS0_BASE, 0); #endif /* #if defined(USB_CFG_HPRN_USE) */ + #if defined(USB_CFG_HUVC_USE) + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_huvc_fs", R_USB_FS0_BASE, 0); + #endif /* #if defined(USB_CFG_HUVC_USE) */ usb_host_usbx_uninitialize(R_USB_FS0_BASE); } @@ -1050,6 +1082,9 @@ fsp_err_t R_USB_Close (usb_ctrl_t * const p_api_ctrl) #if defined(USB_CFG_HPRN_USE) ux_host_stack_class_unregister(ux_host_class_printer_entry); #endif /* #if defined(USB_CFG_HPRN_USE) */ + #if defined(USB_CFG_HUVC_USE) + ux_host_stack_class_unregister(ux_host_class_video_entry); + #endif /* #if defined(USB_CFG_HUVC_USE) */ } g_is_usbx_otg_host_class_init[utr.ip] = USB_NO; @@ -1171,6 +1206,12 @@ fsp_err_t R_USB_Close (usb_ctrl_t * const p_api_ctrl) break; } + case USB_CLASS_INTERNAL_HUVC: + { + class_code = (uint8_t) USB_IFCLS_VID; + break; + } + default: { return FSP_ERR_ASSERTION; @@ -1207,6 +1248,14 @@ fsp_err_t R_USB_Close (usb_ctrl_t * const p_api_ctrl) hw_usb_clear_vdcen(); #endif /* (defined(USB_LDO_REGULATOR_MODULE) && (USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE)) */ + #if defined(USB_SUPPORT_HOCO_MODULE) + if (0 == (R_SYSTEM->SCKSCR & R_SYSTEM_SCKSCR_CKSEL_Msk)) + { + /* Use HOCO */ + hw_usb_clear_uckselc(); + } + #endif /* defined(USB_SUPPORT_HOCO_MODULE) */ + ret_code = usb_module_stop(p_ctrl->module_number); if (FSP_SUCCESS == ret_code) @@ -1237,6 +1286,9 @@ fsp_err_t R_USB_Close (usb_ctrl_t * const p_api_ctrl) #if defined(USB_CFG_HHID_USE) ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hhid_hs", R_USB_HS0_BASE, 0); #endif /* #if defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HUVC_USE) + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_huvc_hs", R_USB_HS0_BASE, 0); + #endif /* #if defined(USB_CFG_HUVC_USE) */ usb_host_usbx_uninitialize(R_USB_HS0_BASE); } else @@ -1250,6 +1302,9 @@ fsp_err_t R_USB_Close (usb_ctrl_t * const p_api_ctrl) #if defined(USB_CFG_HHID_USE) ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_hhid_fs", R_USB_FS0_BASE, 0); #endif /* #if defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HUVC_USE) + ux_host_stack_hcd_unregister((UCHAR *) "fsp_usbx_huvc_fs", R_USB_FS0_BASE, 0); + #endif /* #if defined(USB_CFG_HUVC_USE) */ usb_host_usbx_uninitialize(R_USB_FS0_BASE); } @@ -1262,6 +1317,9 @@ fsp_err_t R_USB_Close (usb_ctrl_t * const p_api_ctrl) #if defined(USB_CFG_HHID_USE) ux_host_stack_class_unregister(ux_host_class_hid_entry); #endif /* #if defined(USB_CFG_HHID_USE) */ + #if defined(USB_CFG_HUVC_USE) + ux_host_stack_class_unregister(ux_host_class_video_entry); + #endif /* #if defined(USB_CFG_HHID_USE) */ #if !defined(USB_CFG_OTG_USE) ux_host_stack_class_unregister(ux_host_class_hub_entry); @@ -1382,6 +1440,9 @@ fsp_err_t R_USB_Close (usb_ctrl_t * const p_api_ctrl) * @note (1). When using High-speed and enabling continuous transfer mode, allocate the storage area with a size that is a multiple of 2048. * @note (2). When using High-speed and disabling continuous transfer mode, allocate the storage area with a size that is a multiple of 512. * @note (3). When using Full-speed, allocate the storage area with a size that is a multiple of 64. + * @note 3. Specify the following address to the 2nd argument (p_buf) when using DMA transfer. + * @note (1). When using High-speed module, specify start address of the buffer area aligned on 4-byte boundary. + * @note (2). When using Full-speed module, specify start address of the buffer area aligned on 2-byte boundary. ******************************************************************************/ fsp_err_t R_USB_Read (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t destination) { @@ -1444,6 +1505,22 @@ fsp_err_t R_USB_Read (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t s FSP_ERR_USB_PARAMETER) /* Check USB Open device class */ #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ +#if (USB_CFG_DMA == USB_CFG_ENABLE) + if (USB_IP0 == p_ctrl->module_number) + { + /* Alignment checking if "p_buf" is 2-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_2_BYTE)), FSP_ERR_USB_PARAMETER) + } + + #if defined(USB_HIGH_SPEED_MODULE) + else + { + /* Alignment checking if "p_buf" is 4-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_4_BYTE)), FSP_ERR_USB_PARAMETER) + } + #endif /* defined(USB_HIGH_SPEED_MODULE) */ +#endif /* (USB_CFG_DMA == USB_CFG_ENABLE) */ + (void) R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); if (USB_STATUS_CONFIGURED == info.device_status) { @@ -1486,7 +1563,10 @@ fsp_err_t R_USB_Read (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t s * @note When sending a ZLP, the user sets USB_NULL in the third argument (size) of R_USB_Write function as follow. * @note e.g) * @note R_USB_Write (&g_basic0_ctrl, &g_buf, USB_NULL); - * @note 2. Do not call this API in the following function. + * @note 2. Specify the following address to the 2nd argument (p_buf) when using DMA transfer. + * @note (1). When using High-speed module, specify start address of the buffer area aligned on 4-byte boundary. + * @note (2). When using Full-speed module, specify start address of the buffer area aligned on 2-byte boundary. + * @note 3. Do not call this API in the following function. * @note (1). Interrupt function. * @note (2). Callback function ( for RTOS ). ******************************************************************************/ @@ -1551,6 +1631,22 @@ fsp_err_t R_USB_Write (usb_ctrl_t * const p_api_ctrl, uint8_t const * const p_bu FSP_ERR_USB_PARAMETER) /* Check USB Open device class */ #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ +#if (USB_CFG_DMA == USB_CFG_ENABLE) + if (USB_IP0 == p_ctrl->module_number) + { + /* Alignment checking if "p_buf" is 2-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_2_BYTE)), FSP_ERR_USB_PARAMETER) + } + + #if defined(USB_HIGH_SPEED_MODULE) + else + { + /* Alignment checking if "p_buf" is 4-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_4_BYTE)), FSP_ERR_USB_PARAMETER) + } + #endif /* defined(USB_HIGH_SPEED_MODULE) */ +#endif /* (USB_CFG_DMA == USB_CFG_ENABLE) */ + (void) R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); if (USB_STATUS_CONFIGURED == info.device_status) { @@ -2261,6 +2357,9 @@ fsp_err_t R_USB_InfoGet (usb_ctrl_t * const p_api_ctrl, usb_info_t * p_info, uin * @note (1). When using High-speed and enabling continuous transfer mode, allocate the storage area with a size that is a multiple of 2048. * @note (2). When using High-speed and disabling continuous transfer mode, allocate the storage area with a size that is a multiple of 512. * @note (3). When using Full-speed, allocate the storage area with a size that is a multiple of 64. + * @note 3. Specify the following address to the 2nd argument (p_buf) when using DMA transfer. + * @note (1). When using High-speed module, specify start address of the buffer area aligned on 4-byte boundary. + * @note (2). When using Full-speed module, specify start address of the buffer area aligned on 2-byte boundary. ******************************************************************************/ fsp_err_t R_USB_PipeRead (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number) { @@ -2294,7 +2393,7 @@ fsp_err_t R_USB_PipeRead (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32 #endif /* USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ #if USB_CFG_PARAM_CHECKING_ENABLE - FSP_ERROR_RETURN((((USB_PIPE0 != p_ctrl->pipe)) || (USB_MAXPIPE_NUM < p_ctrl->pipe)), FSP_ERR_USB_PARAMETER) + FSP_ERROR_RETURN(((USB_MIN_PIPE_NO <= p_ctrl->pipe) && (p_ctrl->pipe <= USB_MAX_PIPE_NO)), FSP_ERR_USB_PARAMETER) FSP_ASSERT(!((USB_NULL == p_buf) || (USB_NULL == size))) @@ -2306,6 +2405,22 @@ fsp_err_t R_USB_PipeRead (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32 FSP_ERR_USB_PARAMETER) /* Check USB Open device class */ #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + #if (USB_CFG_DMA == USB_CFG_ENABLE) + if (USB_IP0 == p_ctrl->module_number) + { + /* Alignment checking if "p_buf" is 2-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_2_BYTE)), FSP_ERR_USB_PARAMETER) + } + + #if defined(USB_HIGH_SPEED_MODULE) + else + { + /* Alignment checking if "p_buf" is 4-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_4_BYTE)), FSP_ERR_USB_PARAMETER) + } + #endif /* defined(USB_HIGH_SPEED_MODULE) */ + #endif /* (USB_CFG_DMA == USB_CFG_ENABLE) */ + ret_code = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); if (USB_STATUS_CONFIGURED == info.device_status) { @@ -2314,9 +2429,9 @@ fsp_err_t R_USB_PipeRead (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32 { #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) #if (BSP_CFG_RTOS != 0) - p_tran_data = (usb_utr_t *) &tran_data; + p_tran_data = &tran_data; #else /* (BSP_CFG_RTOS != 0) */ - p_tran_data = (usb_utr_t *) &g_usb_hdata[p_ctrl->module_number][p_ctrl->pipe]; + p_tran_data = &g_usb_hdata[p_ctrl->module_number][p_ctrl->pipe]; #endif /* (BSP_CFG_RTOS != 0) */ p_tran_data->ip = p_ctrl->module_number; @@ -2367,9 +2482,9 @@ fsp_err_t R_USB_PipeRead (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32 { #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) #if (BSP_CFG_RTOS != 0) - p_tran_data = (usb_utr_t *) &tran_data; + p_tran_data = &tran_data; #else /* (BSP_CFG_RTOS != 0) */ - p_tran_data = (usb_utr_t *) &g_usb_pdata[p_ctrl->pipe]; + p_tran_data = &g_usb_pdata[p_ctrl->pipe]; #endif /* (BSP_CFG_RTOS != 0) */ p_tran_data->ip = p_ctrl->module_number; /* USB Module Number */ @@ -2415,8 +2530,12 @@ fsp_err_t R_USB_PipeRead (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32 #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ } } + else + { + ret_code = FSP_ERR_USB_FAILED; + } return ret_code; -#endif /* !defined(USB_CFG_HVND_USE) && !defined(USB_CFG_PVND_USE) */ +#endif /* !defined(USB_CFG_HVND_USE) && !defined(USB_CFG_PVND_USE) */ } /**************************************************************************//** @@ -2436,9 +2555,12 @@ fsp_err_t R_USB_PipeRead (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32 * @note When sending a ZLP, the user sets USB_NULL in the third argument (size) of R_USB_PipeWrite function as follow. * @note e.g) * @note R_USB_PipeWrite (&g_basic0_ctrl, &g_buf, USB_NULL, pipe_number); - * @note 2. Do not call this API in the following function. - * @note (1). Interrupt function. - * @note (2). Callback function ( for RTOS ). + * @note 2. Specify the following address to the 2nd argument (p_buf) when using DMA transfer. + * @note (1). When using High-speed module, specify start address of the buffer area aligned on 4-byte boundary. + * @note (2). When using Full-speed module, specify start address of the buffer area aligned on 2-byte boundary. + * @note 3. Do not call this API in the following function. + * @note (1). Interrupt function. + * @note (2). Callback function ( for RTOS ). ******************************************************************************/ fsp_err_t R_USB_PipeWrite (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint32_t size, uint8_t pipe_number) { @@ -2471,8 +2593,7 @@ fsp_err_t R_USB_PipeWrite (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint3 /* Argument Checking */ FSP_ERROR_RETURN(!((USB_IP0 != p_ctrl->module_number) && (USB_IP1 != p_ctrl->module_number)), FSP_ERR_USB_PARAMETER) - FSP_ERROR_RETURN((((USB_NULL != p_buf) || (USB_PIPE0 != p_ctrl->pipe)) || (USB_MAXPIPE_NUM > p_ctrl->pipe)), - FSP_ERR_USB_PARAMETER) + FSP_ERROR_RETURN(((USB_MIN_PIPE_NO <= p_ctrl->pipe) && (p_ctrl->pipe <= USB_MAX_PIPE_NO)), FSP_ERR_USB_PARAMETER) if (USB_MODE_PERI == g_usb_usbmode[p_ctrl->module_number]) { @@ -2484,10 +2605,26 @@ fsp_err_t R_USB_PipeWrite (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint3 { #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) p_ctrl->device_address = USB_ADDRESS1; - #endif /* USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ /* USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ } FSP_ERROR_RETURN(USB_NULL != (g_usb_open_class[p_ctrl->module_number] & (1 << p_ctrl->type)), FSP_ERR_USB_PARAMETER) /* Check USB Open device class */ - #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ + #endif /* USB_CFG_PARAM_CHECKING_ENABLE */ /* USB_CFG_PARAM_CHECKING_ENABLE */ + + #if (USB_CFG_DMA == USB_CFG_ENABLE) + if (USB_IP0 == p_ctrl->module_number) + { + /* Alignment checking if "p_buf" is 2-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_2_BYTE)), FSP_ERR_USB_PARAMETER) + } + + #if defined(USB_HIGH_SPEED_MODULE) + else + { + /* Alignment checking if "p_buf" is 4-byte boundary */ + FSP_ERROR_RETURN((0 == ((uint32_t) p_buf & USB_MASK_ALIGN_4_BYTE)), FSP_ERR_USB_PARAMETER) + } + #endif /* defined(USB_HIGH_SPEED_MODULE) */ + #endif /* (USB_CFG_DMA == USB_CFG_ENABLE) */ ret_code = R_USB_InfoGet(p_ctrl, &info, p_ctrl->device_address); if (USB_STATUS_CONFIGURED == info.device_status) @@ -2497,13 +2634,13 @@ fsp_err_t R_USB_PipeWrite (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint3 { #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) #if (BSP_CFG_RTOS != 0) - p_tran_data = (usb_utr_t *) &tran_data; + p_tran_data = &tran_data; #else /* (BSP_CFG_RTOS != 0) */ - p_tran_data = (usb_utr_t *) &g_usb_hdata[p_ctrl->module_number][p_ctrl->pipe]; + p_tran_data = &g_usb_hdata[p_ctrl->module_number][p_ctrl->pipe]; #endif /* (BSP_CFG_RTOS != 0) */ p_tran_data->ip = p_ctrl->module_number; - p_tran_data->ipp = usb_hstd_get_usb_ip_adr((uint8_t) p_ctrl->module_number); + p_tran_data->ipp = usb_hstd_get_usb_ip_adr(p_ctrl->module_number); p_tran_data->keyword = p_ctrl->pipe; /* Pipe No */ p_tran_data->p_tranadr = p_buf; /* Data address */ p_tran_data->tranlen = size; /* Data Size */ @@ -2549,9 +2686,9 @@ fsp_err_t R_USB_PipeWrite (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint3 { #if ((USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI) #if (BSP_CFG_RTOS != 0) - p_tran_data = (usb_utr_t *) &tran_data; + p_tran_data = &tran_data; #else /* (BSP_CFG_RTOS != 0) */ - p_tran_data = (usb_utr_t *) &g_usb_pdata[p_ctrl->pipe]; + p_tran_data = &g_usb_pdata[p_ctrl->pipe]; #endif /* (BSP_CFG_RTOS != 0) */ p_tran_data->ip = p_ctrl->module_number; /* USB Module Number */ @@ -2597,8 +2734,12 @@ fsp_err_t R_USB_PipeWrite (usb_ctrl_t * const p_api_ctrl, uint8_t * p_buf, uint3 #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_PERI */ } } + else + { + ret_code = FSP_ERR_USB_FAILED; + } return ret_code; -#endif /* #if !defined(USB_CFG_HVND_USE) && !defined(USB_CFG_PVND_USE) */ +#endif /* #if !defined(USB_CFG_HVND_USE) && !defined(USB_CFG_PVND_USE) */ } /**************************************************************************//** @@ -2624,7 +2765,7 @@ fsp_err_t R_USB_PipeStop (usb_ctrl_t * const p_api_ctrl, uint8_t pipe_number) #else usb_er_t err = FSP_ERR_USB_FAILED; fsp_err_t ret_code = FSP_ERR_USB_FAILED; - usb_info_t info; + usb_info_t info = {USB_NULL, USB_NULL, USB_NULL, USB_NULL}; usb_utr_t utr; #if USB_CFG_PARAM_CHECKING_ENABLE diff --git a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h index ec13c3ccb..2bc709eed 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h +++ b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_basic_define.h @@ -45,6 +45,10 @@ extern "C" { #define USB_HIGH_SPEED_MODULE #endif /* defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) */ + #if defined(BSP_MCU_GROUP_RA2A1) + #define USB_SUPPORT_HOCO_MODULE + #endif /* defined(BSP_MCU_GROUP_RA6M5) || defined(BSP_MCU_GROUP_RA6M3) */ + /* Version Number of API. */ #define USB_VERSION_MAJOR (1) #define USB_VERSION_MINOR (0) @@ -863,11 +867,15 @@ extern "C" { #define USB_REL_BLK(ID, BLK) (usb_cstd_rel_blk((uint8_t) (ID), (usb_utr_t *) (BLK))) /* Descriptor size */ - #define USB_DEVICESIZE (20U) /* Device Descriptor size */ - #define USB_CONFIGSIZE (256U) /* Configuration Descriptor size */ + #define USB_DEVICESIZE (20U) /* Device Descriptor size */ + #ifdef USB_CFG_HUVC_USE + #define USB_CONFIGSIZE (3 * 1024) /* Configuration Descriptor size */ + #else + #define USB_CONFIGSIZE (1 * 1024) /* Configuration Descriptor size */ + #endif /* USB_CFG_HUVC_USE */ /* Number of software retries when a no-response condition occurs during a transfer */ - #define USB_PIPEERROR (1U) + #define USB_PIPEERROR (1U) /** [Output debugging message in a console of IDE.] * not defined(USB_DEBUG_ON) : No output the debugging message diff --git a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_typedef.h b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_typedef.h index 5b855496d..77451f629 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_typedef.h +++ b/ra/fsp/src/r_usb_basic/src/driver/inc/r_usb_typedef.h @@ -253,8 +253,9 @@ typedef enum e_usb_class_internal USB_CLASS_INTERNAL_HMSC, ///< HMSC Class 13 USB_CLASS_INTERNAL_PMSC, ///< PMSC Class 14 USB_CLASS_INTERNAL_HPRN, ///< HPRN Class 15 - USB_CLASS_INTERNAL_REQUEST, ///< USB Class Request 16 - USB_CLASS_INTERNAL_END ///< USB Class 17 + USB_CLASS_INTERNAL_HUVC, ///< HUVC Class 16 + USB_CLASS_INTERNAL_REQUEST, ///< USB Class Request 17 + USB_CLASS_INTERNAL_END ///< USB Class 18 } usb_class_internal_t; /** Common macro for FSP header files. There is also a corresponding FSP_HEADER macro at the top of this file. */ diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c index a12a1595c..e49a54ec9 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c +++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_cdataio.c @@ -80,6 +80,10 @@ #if defined(USB_CFG_PAUD_USE) #include "r_usb_paud_cfg.h" #endif /* defined(USB_CFG_PAUD_USE) */ + #if defined(USB_CFG_HUVC_USE) + #include "r_usb_huvc_cfg.h" + #endif /* defined(USB_CFG_HUVC_USE) */ + #endif /* #if (BSP_CFG_RTOS != 1) */ #if ((USB_CFG_DTC == USB_CFG_ENABLE) || (USB_CFG_DMA == USB_CFG_ENABLE)) @@ -142,6 +146,18 @@ static const uint8_t g_usb_pipe_host[] = USB_NULL, USB_NULL, USB_NULL, USB_NULL, USB_NULL, USB_NULL, + #endif /* defined(USB_CFG_HPRN_USE) */ + + #if defined(USB_CFG_HUVC_USE) + USB_CFG_HUVC_ISO_IN, USB_CFG_HUVC_ISO_OUT, /* HPRN: Address 1 */ + USB_CFG_HUVC_ISO_IN, USB_CFG_HUVC_ISO_OUT, /* HPRN: Address 2 using Hub */ + USB_NULL, USB_NULL, /* HPRN: Address 3 using Hub */ + USB_NULL, USB_NULL, /* HPRN: Address 4 using Hub */ + #else /* defined(USB_CFG_HPRN_USE) */ + USB_NULL, USB_NULL, + USB_NULL, USB_NULL, + USB_NULL, USB_NULL, + USB_NULL, USB_NULL, #endif /* defined(USB_CFG_HPRN_USE) */ }; #endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ @@ -308,7 +324,11 @@ void (* g_usb_callback[])(usb_utr_t *, uint16_t, uint16_t) = #else USB_NULL, USB_NULL, /* USB_HPRN (15) */ #endif -}; /* const void (g_usb_callback[])(usb_utr_t *, uint16_t, uint16_t) */ + + /* HUVC */ + + USB_NULL, USB_NULL, /* USB_HUVC (16) */ +}; /* const void (g_usb_callback[])(usb_utr_t *, uint16_t, uint16_t) */ #if defined(USB_CFG_PCDC_USE) diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hcontrolrw.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hcontrolrw.c index cd639b008..cc557fbc1 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hcontrolrw.c +++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hcontrolrw.c @@ -271,6 +271,13 @@ void usb_hstd_status_start (usb_utr_t * ptr) /* NoData Control */ case USB_SETUPNDC: { + #if defined(USB_CFG_HUVC_USE) + if ((USB_SET_INTERFACE | USB_HOST_TO_DEV | USB_STANDARD | USB_INTERFACE) == hw_usb_read_usbreq(ptr->ip)) + { + usb_cpu_delay_xms((uint16_t) 50); + } + #endif + /* Control Read Status */ usb_hstd_ctrl_read_start(ptr, (uint32_t) 0, (uint8_t *) &buf1); diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c index 0ec285c5a..bed87114f 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c +++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hdriver.c @@ -3089,13 +3089,13 @@ static void usb_hvnd_pipe_info (usb_utr_t * p_utr, uint8_t * table, uint16_t spe if (USB_DT_ENDPOINT == table[ofdsc + 1]) { pipe_no = (uint16_t) (usb_hvnd_make_pipe_reg_info(p_utr, USB_ADDRESS1, speed, &table[ofdsc], &ep_tbl)); - if (USB_NULL == pipe_no) + if (USB_NULL != pipe_no) { - return; + usb_hstd_set_pipe_info(p_utr->ip, pipe_no, &ep_tbl); } else { - usb_hstd_set_pipe_info(p_utr->ip, pipe_no, &ep_tbl); + return; } } diff --git a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c index f5eb345d1..2a38ded99 100644 --- a/ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c +++ b/ra/fsp/src/r_usb_basic/src/driver/r_usb_hlibusbip.c @@ -60,6 +60,10 @@ #include "r_usb_hprn_cfg.h" #endif /* defined(USB_CFG_HPRN_USE) */ +#if defined(USB_CFG_HUVC_USE) + #include "r_usb_huvc_cfg.h" +#endif /* defined(USB_CFG_HPRN_USE) */ + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) #if (USB_CFG_DMA == USB_CFG_ENABLE) @@ -1394,6 +1398,31 @@ uint8_t usb_hstd_make_pipe_reg_info (uint16_t ip_no, break; } + case USB_EP_ISO: + { + /* Set pipe configuration table */ + if (USB_EP_IN == (descriptor[USB_EP_B_ENDPOINTADDRESS] & USB_EP_DIRMASK)) + { + /* IN(receive) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_ISO | USB_CFG_DBLB | USB_SHTNAKFIELD | USB_DIR_H_IN); + pipe_no = usb_hstd_get_pipe_no(ip_no, address, usb_class, USB_EP_ISO, USB_PIPE_DIR_IN); + } + else + { + /* OUT(send) */ + pipe_cfg = (uint16_t) (USB_TYPFIELD_ISO | USB_CFG_DBLB | USB_DIR_H_OUT); + pipe_no = usb_hstd_get_pipe_no(ip_no, address, usb_class, USB_EP_ISO, USB_PIPE_DIR_OUT); + } + + #if defined(USB_HIGH_SPEED_MODULE) + if (USB_IP1 == ip_no) + { + pipe_cfg |= (uint16_t) (USB_CFG_CNTMD); + } + #endif /* defined (USB_HIGH_SPEED_MODULE) */ + break; + } + default: { return USB_NULL; /* Error */ @@ -1786,6 +1815,50 @@ uint8_t usb_hstd_get_pipe_no (uint16_t ip_no, uint16_t address, uint16_t usb_cla break; } + case USB_CLASS_INTERNAL_HUVC: + { + #if defined(USB_CFG_HUVC_USE) + if (USB_EP_ISO == type) + { + if (USB_PIPE_DIR_IN == dir) + { + switch (address) + { + case 1: /* Root port device1 */ + case 2: /* Hub downport device1 */ + { + pipe_no = USB_CFG_HUVC_ISO_IN; + break; + } + + default: + { + break; + } + } + } + else + { + switch (address) + { + case 1: /* Root port device1 */ + case 2: /* Hub downport device1 */ + { + pipe_no = USB_CFG_HUVC_ISO_OUT; + break; + } + + default: + { + break; + } + } + } + } + #endif /* defined(USB_CFG_HUVC_USE) */ + break; + } + case USB_HUB: { pipe_no = USB_HUB_PIPE; @@ -1932,31 +2005,31 @@ uint16_t usb_hstd_get_pipe_buf_value (uint16_t pipe_no) #if defined(USB_CFG_HVND_USE) case USB_PIPE1: { - pipe_buf = (USB_BUF_SIZE(512u) | USB_BUF_NUMB(8u)); + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(8U)); break; } case USB_PIPE2: { - pipe_buf = (USB_BUF_SIZE(512u) | USB_BUF_NUMB(24u)); + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(24U)); break; } case USB_PIPE3: { - pipe_buf = (USB_BUF_SIZE(512u) | USB_BUF_NUMB(40u)); + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(40U)); break; } case USB_PIPE4: { - pipe_buf = (USB_BUF_SIZE(512u) | USB_BUF_NUMB(56u)); + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(56U)); break; } case USB_PIPE5: { - pipe_buf = (USB_BUF_SIZE(512u) | USB_BUF_NUMB(72u)); + pipe_buf = (USB_BUF_SIZE(512U) | USB_BUF_NUMB(72U)); break; } #endif /* defined(USB_CFG_HVND_USE) */ @@ -1999,6 +2072,20 @@ uint16_t usb_hstd_get_pipe_buf_value (uint16_t pipe_no) #endif /* (USB_NULL != USB_CFG_HPRN_BULK_OUT2) */ #endif /* defined(USB_CFG_HPRN_USE) */ + #if defined(USB_CFG_HUVC_USE) + case USB_CFG_HUVC_ISO_IN: + { + pipe_buf = (USB_BUF_SIZE(2048u) | USB_BUF_NUMB(8u)); + break; + } + + case USB_CFG_HUVC_ISO_OUT: + { + pipe_buf = (USB_BUF_SIZE(2048u) | USB_BUF_NUMB(72u)); + break; + } + #endif /* defined(USB_CFG_PAUD_USE) */ + default: { /* Error */ diff --git a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h index 863294d24..5eb253f06 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h +++ b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_bitdefine.h @@ -339,6 +339,8 @@ extern "C" { #define USB_TRCLR (0x0100U) /* b8: Transaction count clear */ #define USB_TRNCNT (0xFFFFU) /* b15-0: Transaction counter */ + #define USB_UCKSELC (0x0001U) /* b0: USB Clock Seielction Bit */ + #define USB_VDCEN (0x0080U) /* b7: Regulator ON/OFF control */ #define USB_UPPHUB (0x7800U) /* b14-11: HUB register */ diff --git a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h index 54dab35ad..4ce2a9c43 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h +++ b/ra/fsp/src/r_usb_basic/src/hw/inc/r_usb_reg_access.h @@ -296,6 +296,15 @@ uint16_t hw_usb_read_usbindx(uint8_t usb_ip); /************/ uint16_t hw_usb_read_usbleng(uint8_t usb_ip); + #else + #if defined(USB_CFG_HUVC_USE) + +/************/ +/* USBREQ */ +/************/ +uint16_t hw_usb_read_usbreq(uint8_t usb_ip); + + #endif #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ /************/ @@ -391,6 +400,8 @@ void hw_usb_clear_suspm(uint8_t usb_ip); void hw_usb_clear_idpsinke(usb_utr_t * ptr); void hw_usb_set_vdcen(void); void hw_usb_clear_vdcen(void); +void hw_usb_set_uckselc(void); +void hw_usb_clear_uckselc(void); #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) void hw_usb_hset_dcpmode(usb_utr_t * ptr); diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c index e6c846c09..c1100da6d 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c +++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_creg_access.c @@ -2578,6 +2578,32 @@ uint16_t hw_usb_read_usbleng (uint8_t usb_ip) /****************************************************************************** * End of function hw_usb_read_usbleng ******************************************************************************/ +#else + #if defined(USB_CFG_HUVC_USE) + +/****************************************************************************** + * Function Name : hw_usb_read_usbreq + * Description : Returns USBREQ register content. + * Arguments : none + * Return value : USBREQ content + ******************************************************************************/ +uint16_t hw_usb_read_usbreq (uint8_t usb_ip) +{ + uint16_t result = 0; + + if (USB_CFG_IP0 == usb_ip) + { + result = USB_M0->USBREQ; + } + else + { + result = USB_M1->USBREQ; + } + + return result; +} + + #endif #endif /* (USB_CFG_MODE & USB_CFG_PERI) == USB_CFG_REPI */ /****************************************************************************** @@ -3878,6 +3904,40 @@ void hw_usb_clear_vdcen (void) #endif /* (defined(USB_LDO_REGULATOR_MODULE) && (USB_CFG_LDO_REGULATOR == USB_CFG_ENABLE)) */ +#if defined(USB_SUPPORT_HOCO_MODULE) + +/****************************************************************************** + * Function Name : hw_usb_set_uckselc + * Description : Set UCKSELC bit in UCKSEL register. + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_set_uckselc (void) +{ + USB_M0->UCKSEL |= USB_UCKSELC; +} + +/****************************************************************************** + * End of function hw_usb_set_uckselc + ******************************************************************************/ + +/****************************************************************************** + * Function Name : hw_usb_clear_uckselc + * Description : Clear UCLKSELC bit in UCKSEL register. + * Arguments : none + * Return value : none + ******************************************************************************/ +void hw_usb_clear_uckselc (void) +{ + USB_M0->UCKSEL = (uint16_t) (USB_M0->UCKSEL & (~USB_UCKSELC)); +} + +/****************************************************************************** + * End of function hw_usb_clear_uckselc + ******************************************************************************/ + +#endif /* defined(USB_SUPPORT_HOCO_MODULE) */ + /****************************************************************************** * End of file ******************************************************************************/ diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_dma.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_dma.c index 707e6a5af..82c97d4eb 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_dma.c +++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_dma.c @@ -840,7 +840,7 @@ uint8_t usb_cstd_dma_ref_ch_no (usb_utr_t * p_utr, uint16_t use_port) ******************************************************************************/ void usb_cstd_dma_send_complete (uint8_t ip_no, uint16_t use_port) { - usb_cfg_t * p_cfg; + usb_cfg_t * p_cfg = USB_NULL; usb_utr_t utr; #if (BSP_CFG_RTOS != 0) #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c index 3204bd7cf..06e0f1263 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c +++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_hreg_access.c @@ -773,6 +773,14 @@ void hw_usb_hmodule_init (uint8_t usb_ip) USB_M0->SYSCFG |= USB_USBE; + #if defined(USB_SUPPORT_HOCO_MODULE) + if (0 == (R_SYSTEM->SCKSCR & R_SYSTEM_SCKSCR_CKSEL_Msk)) + { + /* Use HOCO */ + hw_usb_set_uckselc(); + } + #endif /* defined(USB_SUPPORT_HOCO_MODULE) */ + USB_M0->CFIFOSEL = USB0_CFIFO_MBW; USB_M0->D0FIFOSEL = USB0_D0FIFO_MBW; USB_M0->D1FIFOSEL = USB0_D1FIFO_MBW; @@ -909,6 +917,7 @@ void hw_usb_hmodule_init (uint8_t usb_ip) USB_M1->D0FIFOSEL |= USB_BIGEND; USB_M1->D1FIFOSEL |= USB_BIGEND; #endif + switch (sts) { case USB_FS_JSTS: /* USB device already connected */ diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c index 8e8b45f89..504607b5f 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c +++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_mcu.c @@ -133,6 +133,15 @@ volatile uint8_t g_usb_otg_chattering_counter = 0; volatile uint8_t g_usb_otg_hnp_counter = 0; #endif /* defined(USB_CFG_OTG_USE) */ +#if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) +static uint16_t g_usb_hstd_m0_reg_intenb0; +static uint16_t g_usb_hstd_m0_reg_intenb1; + #if defined(USB_HIGH_SPEED_MODULE) +static uint16_t g_usb_hstd_m1_reg_intenb0; +static uint16_t g_usb_hstd_m1_reg_intenb1; + #endif /* defined(USB_HIGH_SPEED_MODULE) */ +#endif /* (USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST */ + /****************************************************************************** * Renesas Abstracted RSK functions ******************************************************************************/ @@ -480,6 +489,9 @@ void usb_cpu_int_enable (void) if (USB_MODE_HOST == g_p_usb_cfg_ip0->usb_mode) { R_BSP_IrqCfgEnable(g_p_usb_cfg_ip0->irq, g_p_usb_cfg_ip0->ipl, g_p_usb_cfg_ip0); /* USBI enable */ + + USB_M0->INTENB0 = g_usb_hstd_m0_reg_intenb0; + USB_M0->INTENB1 = g_usb_hstd_m0_reg_intenb1; } } @@ -500,9 +512,12 @@ void usb_cpu_int_enable (void) if (USB_MODE_HOST == g_p_usb_cfg_ip1->usb_mode) { R_BSP_IrqCfgEnable(g_p_usb_cfg_ip1->hsirq, g_p_usb_cfg_ip1->hsipl, g_p_usb_cfg_ip1); /* USBIR enable */ + + USB_M1->INTENB0 = g_usb_hstd_m1_reg_intenb0; + USB_M1->INTENB1 = g_usb_hstd_m1_reg_intenb1; } } - #endif /* defined (USB_HIGH_SPEED_MODULE) */ + #endif /* defined (USB_HIGH_SPEED_MODULE) */ } /****************************************************************************** @@ -531,6 +546,11 @@ void usb_cpu_int_disable (void) { if (USB_MODE_HOST == g_p_usb_cfg_ip0->usb_mode) { + g_usb_hstd_m0_reg_intenb0 = USB_M0->INTENB0; + g_usb_hstd_m0_reg_intenb1 = USB_M0->INTENB1; + USB_M0->INTENB0 = 0; + USB_M0->INTENB1 = 0; + R_BSP_IrqDisable(g_p_usb_cfg_ip0->irq); /* USBI enable */ } } @@ -551,6 +571,11 @@ void usb_cpu_int_disable (void) { if (USB_MODE_HOST == g_p_usb_cfg_ip1->usb_mode) { + g_usb_hstd_m1_reg_intenb0 = USB_M1->INTENB0; + g_usb_hstd_m1_reg_intenb1 = USB_M1->INTENB1; + USB_M1->INTENB0 = 0; + USB_M1->INTENB1 = 0; + R_BSP_IrqDisable(g_p_usb_cfg_ip1->hsirq); /* USBIR enable */ } } diff --git a/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c b/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c index a98ad0c71..0a6988a36 100644 --- a/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c +++ b/ra/fsp/src/r_usb_basic/src/hw/r_usb_preg_access.c @@ -236,7 +236,16 @@ void hw_usb_pmodule_init (uint8_t usb_ip) USB_M0->SYSCFG &= (uint16_t) (~USB_DRPD); - USB_M0->SYSCFG |= USB_USBE; + USB_M0->SYSCFG |= USB_USBE; + + #if defined(USB_SUPPORT_HOCO_MODULE) + if (0 == (R_SYSTEM->SCKSCR & R_SYSTEM_SCKSCR_CKSEL_Msk)) + { + /* Use HOCO */ + hw_usb_set_uckselc(); + } + #endif /* defined(USB_SUPPORT_HOCO_MODULE) */ + USB_M0->CFIFOSEL = USB0_CFIFO_MBW; USB_M0->D0FIFOSEL = USB0_D0FIFO_MBW; USB_M0->D1FIFOSEL = USB0_D1FIFO_MBW; @@ -245,6 +254,7 @@ void hw_usb_pmodule_init (uint8_t usb_ip) USB_M0->D0FIFOSEL |= USB_BIGEND; USB_M0->D1FIFOSEL |= USB_BIGEND; #endif /* USB_CFG_ENDIAN == USB_CFG_BIG */ + USB_M0->INTENB0 = (USB_BEMPE | USB_BRDYE | USB_VBSE | USB_DVSE | USB_CTRE); } else diff --git a/ra/fsp/src/r_usb_pmsc/r_usb_pmsc_descriptor.c.template b/ra/fsp/src/r_usb_pmsc/r_usb_pmsc_descriptor.c.template index 3a32e3cf5..19731d21e 100644 --- a/ra/fsp/src/r_usb_pmsc/r_usb_pmsc_descriptor.c.template +++ b/ra/fsp/src/r_usb_pmsc/r_usb_pmsc_descriptor.c.template @@ -41,6 +41,7 @@ #define USB_PMSC_SD4_BLENGTH (0x16U) #define USB_PMSC_SD5_BLENGTH (0x12U) #define USB_PMSC_SD6_BLENGTH (0x1cU) +#define NUM_STRING_DESCRIPTOR (6U) /* Sub_class code */ #define USB_ATAPI ((uint8_t) 0x05U) @@ -323,6 +324,17 @@ uint8_t * g_apl_string_table[] = g_usb_pmsc_string_descriptor6 }; +const usb_descriptor_t g_usb_descriptor = +{ + g_apl_device, + g_apl_configuration, + g_apl_hs_configuration, /* Pointer to the configuration descriptor for Hi-speed */ + g_apl_qualifier_descriptor, /* Pointer to the qualifier descriptor */ + g_apl_string_table, + NUM_STRING_DESCRIPTOR +}; + + /****************************************************************************** * Renesas Abstracted Peripheral Mass Storage Class Driver API functions ******************************************************************************/ diff --git a/ra/fsp/src/rm_aws_sockets_wrapper_wifi_da16200/sockets_wrapper.c b/ra/fsp/src/rm_aws_sockets_wrapper_wifi_da16200/sockets_wrapper.c new file mode 100644 index 000000000..091326daa --- /dev/null +++ b/ra/fsp/src/rm_aws_sockets_wrapper_wifi_da16200/sockets_wrapper.c @@ -0,0 +1,406 @@ +/* + * FreeRTOS V202112.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#include "bsp_api.h" + +#if (BSP_CFG_RTOS == 2) + +/* Standard includes. */ + #include + #include + #include + +/* FreeRTOS includes. */ + #include "FreeRTOS.h" + #include "event_groups.h" + +/* Sockets wrapper includes. */ + #include "sockets_wrapper.h" + +/* WiFi includes. */ + #include "rm_wifi_onchip_da16200.h" + +/* Configure logs for the functions in this file. */ + #include "logging_levels.h" + #ifndef LIBRARY_LOG_NAME + #define LIBRARY_LOG_NAME "WIFI_SOCKETS" + #endif + #ifndef LIBRARY_LOG_LEVEL + #define LIBRARY_LOG_LEVEL LOG_INFO + #endif + #include "logging_stack.h" + + #define SOCKETS_SOCK_STREAM (1) + +/* Ticks MS conversion macros. */ + #define TICKS_TO_MS(xTicks) (((xTicks) * 1000U) / ((uint32_t) configTICK_RATE_HZ)) + #define UINT32_MAX_DELAY_MS (0xFFFFFFFFUL) + #define UINT32_MAX_MS_TICKS (UINT32_MAX_DELAY_MS / (TICKS_TO_MS(1U))) + +/* Logging macros definition. */ + #define IotLogError(...) LogError((__VA_ARGS__)) + #define IotLogWarn(...) LogWarn((__VA_ARGS__)) + #define IotLogInfo(...) LogInfo((__VA_ARGS__)) + #define IotLogDebug(...) LogDebug((__VA_ARGS__)) + +typedef struct xSOCKET +{ + uint32_t socketId; + TickType_t receiveTimeout; + TickType_t sendTimeout; +} wifiSocketWrapper_t; + +static uint32_t g_sockets_num_allocated = 0; + +/** + * @brief Setup socket receive timeout. + * + * @param[in] pWiFiSocketContext Cellular socket wrapper context for socket operations. + * @param[out] receiveTimeout Socket receive timeout in TickType_t. + * + * @return On success, SOCKETS_ERROR_NONE is returned. If an error occurred, error code defined + * in sockets_wrapper.h is returned. + */ +static BaseType_t prvSetupSocketRecvTimeout(wifiSocketWrapper_t * pWiFiSocketContext, TickType_t receiveTimeout); + +/** + * @brief Setup socket send timeout. + * + * @param[in] pWiFiSocketContext Cellular socket wrapper context for socket operations. + * @param[out] sendTimeout Socket send timeout in TickType_t. + * + * @note Send timeout unit is TickType_t. The underlying cellular API uses miliseconds for timeout. + * Any send timeout greater than UINT32_MAX_MS_TICKS( UINT32_MAX_DELAY_MS/MS_PER_TICKS ) or + * portMAX_DELAY is regarded as UINT32_MAX_DELAY_MS for cellular API. + * + * @return On success, SOCKETS_ERROR_NONE is returned. If an error occurred, error code defined + * in sockets_wrapper.h is returned. + */ +static BaseType_t prvSetupSocketSendTimeout(wifiSocketWrapper_t * pWiFiSocketContext, TickType_t sendTimeout); + +/*-----------------------------------------------------------*/ + +static BaseType_t prvSetupSocketRecvTimeout (wifiSocketWrapper_t * pWiFiSocketContext, TickType_t receiveTimeout) +{ + BaseType_t retSetSockOpt = SOCKETS_ERROR_NONE; + + if (pWiFiSocketContext == NULL) + { + retSetSockOpt = SOCKETS_EINVAL; + } + else + { + if (receiveTimeout >= UINT32_MAX_MS_TICKS) + { + /* Check if the ticks cause overflow. */ + pWiFiSocketContext->receiveTimeout = UINT32_MAX_DELAY_MS; + } + else if (receiveTimeout >= portMAX_DELAY) + { + IotLogWarn("Receievetimeout %d longer than portMAX_DELAY, %d ms is used instead", + receiveTimeout, + UINT32_MAX_DELAY_MS); + pWiFiSocketContext->receiveTimeout = UINT32_MAX_DELAY_MS; + } + else + { + pWiFiSocketContext->receiveTimeout = TICKS_TO_MS(receiveTimeout); + } + } + + return retSetSockOpt; +} + +/*-----------------------------------------------------------*/ + +static BaseType_t prvSetupSocketSendTimeout (wifiSocketWrapper_t * pWiFiSocketContext, TickType_t sendTimeout) +{ + BaseType_t retSetSockOpt = SOCKETS_ERROR_NONE; + + if (pWiFiSocketContext == NULL) + { + retSetSockOpt = SOCKETS_EINVAL; + } + else + { + if (sendTimeout >= UINT32_MAX_MS_TICKS) + { + /* Check if the ticks cause overflow. */ + pWiFiSocketContext->sendTimeout = UINT32_MAX_DELAY_MS; + } + else if (sendTimeout >= portMAX_DELAY) + { + IotLogWarn("Sendtimeout %d longer than portMAX_DELAY, %d ms is used instead", + sendTimeout, + UINT32_MAX_DELAY_MS); + pWiFiSocketContext->sendTimeout = UINT32_MAX_DELAY_MS; + } + else + { + pWiFiSocketContext->sendTimeout = TICKS_TO_MS(sendTimeout); + } + } + + return retSetSockOpt; +} + +/*-----------------------------------------------------------*/ + +BaseType_t Sockets_Connect (Socket_t * pTcpSocket, + const char * pHostName, + uint16_t port, + uint32_t receiveTimeoutMs, + uint32_t sendTimeoutMs) +{ + wifiSocketWrapper_t * pWiFiSocketContext = NULL; + uint32_t socketId = 0; + fsp_err_t err; + uint8_t ipAddressArray[4]; // NOLINT + uint32_t ipAddress; + BaseType_t retConnect = SOCKETS_ERROR_NONE; + + /* Allocate socket context. */ + if (retConnect == SOCKETS_ERROR_NONE) + { + pWiFiSocketContext = pvPortMalloc(sizeof(wifiSocketWrapper_t)); + + if (pWiFiSocketContext == NULL) + { + IotLogError("Failed to allocate new socket context."); + retConnect = SOCKETS_ENOMEM; + } + else + { + IotLogDebug("Created WIFI Socket %p.", pWiFiSocketContext); + memset(pWiFiSocketContext, 0, sizeof(wifiSocketWrapper_t)); + pWiFiSocketContext->socketId = UINT32_MAX; + } + } + + rm_wifi_onchip_da16200_avail_socket_get(&socketId); + + if ((g_sockets_num_allocated > WIFI_ONCHIP_DA16200_CFG_NUM_CREATEABLE_SOCKETS) || (socketId == UINT8_MAX)) + { + retConnect = SOCKETS_ENOSOCKETS; + } + + if (SOCKETS_ERROR_NONE == retConnect) + { + /* Create the wrapped socket. */ + err = + rm_wifi_onchip_da16200_socket_create(socketId, (uint32_t) SOCKETS_SOCK_STREAM, SOCKETS_IPPROTO_V4_DA16200); + if (FSP_SUCCESS != err) + { + IotLogError("Failed to create WiFi sockets. %d", err); + retConnect = SOCKETS_SOCKET_ERROR; + } + } + + if (SOCKETS_ERROR_NONE == retConnect) + { + if (g_sockets_num_allocated < WIFI_ONCHIP_DA16200_CFG_NUM_CREATEABLE_SOCKETS) + { + g_sockets_num_allocated++; + } + + pWiFiSocketContext->socketId = socketId; + } + + /* Setup cellular socket send/recv timeout. */ + if (retConnect == SOCKETS_ERROR_NONE) + { + retConnect = prvSetupSocketSendTimeout(pWiFiSocketContext, pdMS_TO_TICKS(sendTimeoutMs)); + } + + if (retConnect == SOCKETS_ERROR_NONE) + { + retConnect = prvSetupSocketRecvTimeout(pWiFiSocketContext, pdMS_TO_TICKS(receiveTimeoutMs)); + } + + /* Perform a DNS lookup */ + if (retConnect == SOCKETS_ERROR_NONE) + { + err = rm_wifi_onchip_da16200_dns_query(pHostName, ipAddressArray); + + if (FSP_SUCCESS != err) + { + retConnect = SOCKETS_EDNS; + } + } + + /* Cellular socket connect. */ + if (retConnect == SOCKETS_ERROR_NONE) + { + /* Convert IP address to binary representation */ + ipAddress = ((uint32_t) (ipAddressArray[0]) << 24) + ((uint32_t) (ipAddressArray[1]) << 16) + + ((uint32_t) (ipAddressArray[2]) << 8) + (uint32_t) (ipAddressArray[3]); + + err = rm_wifi_onchip_da16200_tcp_connect(socketId, ipAddress, port); + + if (FSP_SUCCESS != err) + { + IotLogError("Failed to establish new connection. Connect return %d.", err); + retConnect = SOCKETS_SOCKET_ERROR; + } + } + + /* Cleanup the socket if any error. */ + if (retConnect != SOCKETS_ERROR_NONE) + { + if (pWiFiSocketContext != NULL) + { + vPortFree(pWiFiSocketContext); + pWiFiSocketContext = NULL; + } + } + + *pTcpSocket = pWiFiSocketContext; + + return retConnect; +} + +/*-----------------------------------------------------------*/ + +void Sockets_Disconnect (Socket_t xSocket) +{ + int32_t retClose = SOCKETS_ERROR_NONE; + wifiSocketWrapper_t * pWiFiSocketContext = (wifiSocketWrapper_t *) xSocket; + int32_t recvLength = 0; + uint8_t buf[128] = {0}; // NOLINT + + /* xSocket need to be check against SOCKET_INVALID_SOCKET. */ + /* coverity[misra_c_2012_rule_11_4_violation] */ + if ((pWiFiSocketContext == NULL) || (xSocket == SOCKETS_INVALID_SOCKET)) + { + IotLogError("Invalid xSocket %p", pWiFiSocketContext); + retClose = SOCKETS_EINVAL; + } + + if (retClose == SOCKETS_ERROR_NONE) + { + if (UINT32_MAX != pWiFiSocketContext->socketId) + { + /* Receive all the data before socket close. */ + do + { + recvLength = rm_wifi_onchip_da16200_recv(pWiFiSocketContext->socketId, + buf, + 128, // NOLINT + pWiFiSocketContext->socketId); + IotLogDebug("%u bytes received in close", recvLength); + } while (recvLength > 0); + + /* Close sockets. */ + if (FSP_SUCCESS != rm_wifi_onchip_da16200_socket_disconnect(pWiFiSocketContext->socketId)) + { + IotLogWarn("Failed to destroy connection."); + retClose = SOCKETS_SOCKET_ERROR; + } + } + + vPortFree(pWiFiSocketContext); + + g_sockets_num_allocated--; + } + + (void) retClose; + IotLogDebug("Sockets close exit with code %d", retClose); +} + +/*-----------------------------------------------------------*/ + +int32_t Sockets_Recv (Socket_t xSocket, void * pvBuffer, size_t xBufferLength) +{ + wifiSocketWrapper_t * pWiFiSocketContext = (wifiSocketWrapper_t *) xSocket; + uint8_t * buf = (uint8_t *) pvBuffer; + int32_t retRecvLength = 0; + + if ((pWiFiSocketContext == NULL) || (UINT32_MAX == pWiFiSocketContext->socketId)) + { + IotLogError("prvNetworkRecv Invalid xSocket %p", pWiFiSocketContext); + retRecvLength = SOCKETS_EINVAL; + } + else + { + int32_t recvLength = 0; + + recvLength = + rm_wifi_onchip_da16200_recv(pWiFiSocketContext->socketId, + buf, + xBufferLength, + pWiFiSocketContext->receiveTimeout); + + if (recvLength >= 0) + { + retRecvLength = recvLength; + } + else + { + retRecvLength = SOCKETS_SOCKET_ERROR; + } + + IotLogDebug("prvNetworkRecv expect %d read %d", xBufferLength, recvLength); + } + + return retRecvLength; +} + +/*-----------------------------------------------------------*/ + +/* This function sends the data until timeout or data is completely sent to server. + * Send timeout unit is TickType_t. Any timeout value greater than UINT32_MAX_MS_TICKS + * or portMAX_DELAY will be regarded as MAX delay. In this case, this function + * will not return until all bytes of data are sent successfully or until an error occurs. */ +int32_t Sockets_Send (Socket_t xSocket, const void * pvBuffer, size_t xDataLength) +{ + uint8_t * buf = (uint8_t *) pvBuffer; + int32_t sentLength = 0; + wifiSocketWrapper_t * pWiFiSocketContext = (wifiSocketWrapper_t *) xSocket; + + if ((pWiFiSocketContext == NULL) || (UINT32_MAX == pWiFiSocketContext->socketId)) + { + IotLogError("prvNetworkSend Invalid xSocket %p", pWiFiSocketContext); + sentLength = SOCKETS_EINVAL; + } + else + { + sentLength = + rm_wifi_onchip_da16200_send(pWiFiSocketContext->socketId, buf, xDataLength, + pWiFiSocketContext->sendTimeout); + + if (sentLength < 0) + { + IotLogError("prvNetworkSend failed %d"); + sentLength = SOCKETS_SOCKET_ERROR; + } + } + + return sentLength; +} + +/*-----------------------------------------------------------*/ + +#endif diff --git a/ra/fsp/src/rm_aws_sockets_wrapper_wifi_da16200/sockets_wrapper.h b/ra/fsp/src/rm_aws_sockets_wrapper_wifi_da16200/sockets_wrapper.h new file mode 100644 index 000000000..03382745d --- /dev/null +++ b/ra/fsp/src/rm_aws_sockets_wrapper_wifi_da16200/sockets_wrapper.h @@ -0,0 +1,128 @@ +/* + * FreeRTOS V202112.00 + * Copyright (C) 2020 Amazon.com, Inc. or its affiliates. All Rights Reserved. + * + * Permission is hereby granted, free of charge, to any person obtaining a copy of + * this software and associated documentation files (the "Software"), to deal in + * the Software without restriction, including without limitation the rights to + * use, copy, modify, merge, publish, distribute, sublicense, and/or sell copies of + * the Software, and to permit persons to whom the Software is furnished to do so, + * subject to the following conditions: + * + * The above copyright notice and this permission notice shall be included in all + * copies or substantial portions of the Software. + * + * THE SOFTWARE IS PROVIDED "AS IS", WITHOUT WARRANTY OF ANY KIND, EXPRESS OR + * IMPLIED, INCLUDING BUT NOT LIMITED TO THE WARRANTIES OF MERCHANTABILITY, FITNESS + * FOR A PARTICULAR PURPOSE AND NONINFRINGEMENT. IN NO EVENT SHALL THE AUTHORS OR + * COPYRIGHT HOLDERS BE LIABLE FOR ANY CLAIM, DAMAGES OR OTHER LIABILITY, WHETHER + * IN AN ACTION OF CONTRACT, TORT OR OTHERWISE, ARISING FROM, OUT OF OR IN + * CONNECTION WITH THE SOFTWARE OR THE USE OR OTHER DEALINGS IN THE SOFTWARE. + * + * https://www.FreeRTOS.org + * https://github.com/FreeRTOS + * + */ + +#ifndef SOCKETS_WRAPPER_H +#define SOCKETS_WRAPPER_H + +/**************************************************/ +/******* DO NOT CHANGE the following order ********/ +/**************************************************/ + +/* Logging related header files are required to be included in the following order: + * 1. Include the header file "logging_levels.h". + * 2. Define LIBRARY_LOG_NAME and LIBRARY_LOG_LEVEL. + * 3. Include the header file "logging_stack.h". + */ + +/* Include header that defines log levels. */ +#include "logging_levels.h" + +/* Logging configuration for the Sockets. */ +#ifndef LIBRARY_LOG_NAME + #define LIBRARY_LOG_NAME "Sockets" +#endif +#ifndef LIBRARY_LOG_LEVEL + #define LIBRARY_LOG_LEVEL LOG_INFO +#endif + +extern void vLoggingPrintf(const char * pcFormatString, ...); + +#include "logging_stack.h" + +/************ End of logging configuration ****************/ + +#define SOCKETS_ERROR_NONE (0) /*!< No error. */ +#define SOCKETS_SOCKET_ERROR (-1) /*!< Catch-all sockets error code. */ +#define SOCKETS_ENOMEM (-12) /*!< Memory allocation failed. */ +#define SOCKETS_ENOSOCKETS (-13) /*!< Max number of sockets has been used. */ +#define SOCKETS_EINVAL (-22) /*!< Invalid argument. */ +#define SOCKETS_EDNS (-200) /*!< DNS lookup failed. */ + +#define SOCKETS_INVALID_SOCKET ((Socket_t) ~0U) + +struct xSOCKET; +typedef struct xSOCKET * Socket_t; /**< @brief Socket handle data type. */ + +/** + * @brief Establish a connection to server. + * + * @param[out] pTcpSocket The output parameter to return the created socket descriptor. + * @param[in] pHostName Server hostname to connect to. + * @param[in] port Server port to connect to. + * @param[in] receiveTimeoutMs Timeout (in milliseconds) for transport receive. + * @param[in] sendTimeoutMs Timeout (in milliseconds) for transport send. + * + * @note A timeout of 0 means infinite timeout. + * + * @return Non-zero value on error, 0 on success. + */ +BaseType_t Sockets_Connect(Socket_t * pTcpSocket, + const char * pHostName, + uint16_t port, + uint32_t receiveTimeoutMs, + uint32_t sendTimeoutMs); + +/** + * @brief End connection to server. + * + * @param[in] xSocket The socket descriptor. + */ +void Sockets_Disconnect(Socket_t xSocket); + +/** + * @brief Transmit data to the remote socket. + * + * The socket must have already been created using a call to Sockets_Connect(). + * + * @param[in] xSocket The handle of the sending socket. + * @param[in] pvBuffer The buffer containing the data to be sent. + * @param[in] xDataLength The length of the data to be sent. + * + * @return + * * On success, the number of bytes actually sent is returned. + * * If an error occurred, a negative value is returned. + */ +int32_t Sockets_Send(Socket_t xSocket, const void * pvBuffer, size_t xDataLength); + +/** + * @brief Receive data from a TCP socket. + * + * The socket must have already been created using a call to Sockets_Connect(). + * + * @param[in] xSocket The handle of the socket from which data is being received. + * @param[out] pvBuffer The buffer into which the received data will be placed. + * @param[in] xBufferLength The maximum number of bytes which can be received. + * pvBuffer must be at least xBufferLength bytes long. + * + * @return + * * If the receive was successful then the number of bytes received (placed in the + * buffer pointed to by pvBuffer) is returned. + * * If a timeout occurred before data could be received then 0 is returned. + * * If an error occurred, a negative value is returned. + */ +int32_t Sockets_Recv(Socket_t xSocket, void * pvBuffer, size_t xBufferLength); + +#endif /* ifndef SOCKETS_WRAPPER_H */ diff --git a/ra/fsp/src/rm_aws_sockets_wrapper_wifi_silex/sockets_wrapper.c b/ra/fsp/src/rm_aws_sockets_wrapper_wifi_silex/sockets_wrapper.c index d8d3bb71a..01233a0e7 100644 --- a/ra/fsp/src/rm_aws_sockets_wrapper_wifi_silex/sockets_wrapper.c +++ b/ra/fsp/src/rm_aws_sockets_wrapper_wifi_silex/sockets_wrapper.c @@ -357,7 +357,7 @@ int32_t Sockets_Recv (Socket_t xSocket, void * pvBuffer, size_t xBufferLength) } else { - IotLogError("prvNetworkRecv failed %d", socketStatus); + IotLogError("prvNetworkRecv failed"); retRecvLength = SOCKETS_SOCKET_ERROR; } @@ -391,7 +391,7 @@ int32_t Sockets_Send (Socket_t xSocket, const void * pvBuffer, size_t xDataLengt if (sentLength < 0) { - IotLogError("prvNetworkSend failed %d", socketStatus); + IotLogError("prvNetworkSend failed %d"); sentLength = SOCKETS_SOCKET_ERROR; } } diff --git a/ra/fsp/src/rm_aws_sockets_wrapper_wifi_silex/sockets_wrapper.h b/ra/fsp/src/rm_aws_sockets_wrapper_wifi_silex/sockets_wrapper.h index 4d4d8d353..03382745d 100644 --- a/ra/fsp/src/rm_aws_sockets_wrapper_wifi_silex/sockets_wrapper.h +++ b/ra/fsp/src/rm_aws_sockets_wrapper_wifi_silex/sockets_wrapper.h @@ -24,11 +24,6 @@ * */ -/** - * @file sockets_wrapper.h - * @brief FreeRTOS Sockets connect and disconnect function wrapper. - */ - #ifndef SOCKETS_WRAPPER_H #define SOCKETS_WRAPPER_H diff --git a/ra/fsp/src/rm_ble_abs/rm_ble_abs.c b/ra/fsp/src/rm_ble_abs/rm_ble_abs.c index 0a5dff492..36acf5955 100644 --- a/ra/fsp/src/rm_ble_abs/rm_ble_abs.c +++ b/ra/fsp/src/rm_ble_abs/rm_ble_abs.c @@ -4050,10 +4050,12 @@ static fsp_err_t ble_abs_secure_data_read_bond_info (flash_instance_t const * p_ p_bonds = *pp_sec_data; FSP_ERROR_RETURN(NULL != p_bonds, FSP_ERR_BLE_ABS_NOT_FOUND); - ble_abs_secure_data_flash_read(p_instance, - (uint32_t) BLE_ABS_SECURE_DATA_BASE_ADDR, - p_bonds, - BLE_ABS_SECURE_DATA_MAX_SIZE); + retval = ble_abs_secure_data_flash_read(p_instance, + (uint32_t) BLE_ABS_SECURE_DATA_BASE_ADDR, + p_bonds, + BLE_ABS_SECURE_DATA_MAX_SIZE); + + FSP_ERROR_RETURN(FSP_SUCCESS == retval, retval); /** check magic number and bond number */ *p_out_bond_num = 0; diff --git a/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c b/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c index 262824071..a44d80db5 100644 --- a/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c +++ b/ra/fsp/src/rm_freertos_plus_tcp/NetworkInterface.c @@ -119,10 +119,7 @@ BaseType_t xNetworkInterfaceInitialise (void) return pdFAIL; } - do - { - err = gp_freertos_ether->p_api->linkProcess(gp_freertos_ether->p_ctrl); - } while (FSP_SUCCESS != err); + gp_freertos_ether->p_api->linkProcess(gp_freertos_ether->p_ctrl); xReturn = xTaskCreate(prvRXHandlerTask, "RXHandlerTask", @@ -358,20 +355,3 @@ BSP_WEAK_REFERENCE uint32_t ulApplicationGetNextSequenceNumber (uint32_t ulSourc return ulResult; } - -#if defined(__ARMCC_VERSION) - -/*******************************************************************************************************************//** - * Default implementation of IotClock_GetTimestring for AC6. - **********************************************************************************************************************/ -__attribute__((weak)) -bool IotClock_GetTimestring (char * pBuffer, size_t bufferSize, size_t * pTimestringLength) -{ - FSP_PARAMETER_NOT_USED(pBuffer); - FSP_PARAMETER_NOT_USED(bufferSize); - FSP_PARAMETER_NOT_USED(pTimestringLength); - - return true; -} - -#endif diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_aes_alt.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_aes_alt.c index ff770db05..efa50c7b7 100644 --- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_aes_alt.c +++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_aes_alt.c @@ -2610,7 +2610,7 @@ UINT status; message_len = input_length_in_byte - icv_len; #if (1U == NETX_SECURE_CRYPTO_NX_CRYPTO_METHODS_AES_ALT) && ((1U == BSP_FEATURE_CRYPTO_HAS_SCE9) || \ - (1U == BSP_FEATURE_CRYPTO_HAS_SCE5B)) + (1U == BSP_FEATURE_CRYPTO_HAS_SCE5B) || (1U == BSP_FEATURE_CRYPTO_HAS_SCE7)) /* SCE9 APIs are different for Encryption and Decryption. * Since _nx_crypto_gcm_decrypt_init is mapped to _nx_crypto_gcm_encrypt_init this * new function is created for supporting decryption specific HW acceleration: GHASH and block cipher. @@ -2703,7 +2703,7 @@ UINT status; } #if (1U == NETX_SECURE_CRYPTO_NX_CRYPTO_METHODS_AES_ALT) && ((1U == BSP_FEATURE_CRYPTO_HAS_SCE9) || \ - (1U == BSP_FEATURE_CRYPTO_HAS_SCE5B)) + (1U == BSP_FEATURE_CRYPTO_HAS_SCE5B) || (1U == BSP_FEATURE_CRYPTO_HAS_SCE7)) /* SCE9 APIs are different for Encryption and Decryption. * Since _nx_crypto_gcm_decrypt_init is mapped to _nx_crypto_gcm_encrypt_init this * new function is created for supporting decryption specific HW acceleration: GHASH and block cipher. diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_aes_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_aes_alt_process.c index 2531a7b3f..1dc474aa6 100644 --- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_aes_alt_process.c +++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_aes_alt_process.c @@ -99,7 +99,7 @@ UINT sce_nx_crypto_aes_encrypt (NX_CRYPTO_AES * aes_ptr, UCHAR * input, UCHAR * break; } - #if (1U == BSP_FEATURE_CRYPTO_HAS_SCE9) + #if (1U == BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7) case 12: { ret = HW_SCE_Aes192EncryptDecryptInitSub(&indata_cmd, (uint32_t *) w, dummy_iv); @@ -206,7 +206,7 @@ UINT sce_nx_crypto_aes_decrypt (NX_CRYPTO_AES * aes_ptr, UCHAR * input, UCHAR * break; } - #if (1U == BSP_FEATURE_CRYPTO_HAS_SCE9) + #if (1U == BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7) case 12: { ret = HW_SCE_Aes192EncryptDecryptInitSub(&indata_cmd, (uint32_t *) w, dummy_iv); diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_cbc_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_cbc_alt_process.c index caf127051..27266731f 100644 --- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_cbc_alt_process.c +++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_cbc_alt_process.c @@ -113,7 +113,7 @@ UINT sce_nx_crypto_cbc_encrypt (VOID * crypto_metadata, break; } - #if (1U == BSP_FEATURE_CRYPTO_HAS_SCE9) + #if (1U == BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7) case 12: { ret = HW_SCE_Aes192EncryptDecryptInitSub(&indata_cmd, @@ -250,7 +250,7 @@ UINT sce_nx_crypto_cbc_decrypt (VOID * crypto_metadata, break; } - #if (1U == BSP_FEATURE_CRYPTO_HAS_SCE9) + #if (1U == BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7) case 12: { ret = HW_SCE_Aes192EncryptDecryptInitSub(&indata_cmd, diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ctr_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ctr_alt_process.c index 20c84daab..71ba81bc8 100644 --- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ctr_alt_process.c +++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ctr_alt_process.c @@ -115,7 +115,7 @@ UINT sce_nx_crypto_ctr_encrypt (VOID * crypto_metadata, break; } - #if (1U == BSP_FEATURE_CRYPTO_HAS_SCE9) + #if (1U == BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7) case AES_CTR_KEY_SIZE_192_ROUNDS: { status = HW_SCE_Aes192EncryptDecryptInitSub(&indata_cmd, diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdh_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdh_alt_process.c index fa14fbd0f..d1a289e8e 100644 --- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdh_alt_process.c +++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdh_alt_process.c @@ -258,12 +258,10 @@ UINT sce_nx_crypto_ecdh_compute_secret (NX_CRYPTO_ECDH * ecdh_ptr, /* Generate ECC key pair based on the curve type & size */ if (curve->nx_crypto_ec_id == NX_CRYPTO_EC_SECP384R1) { - #if 0 err = HW_SCE_Ecc384ScalarMultiplicationSub(&curve_type, (uint32_t *) ecdh_ptr->nx_crypto_ecdh_private_key_buffer, pub_key, (uint32_t *) share_secret_key_ptr); - #endif } else if (curve->nx_crypto_ec_id == NX_CRYPTO_EC_SECP256R1) { diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdsa_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdsa_alt_process.c index f468cc9b5..cd7d4ecd5 100644 --- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdsa_alt_process.c +++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_ecdsa_alt_process.c @@ -183,16 +183,15 @@ UINT sce_nx_crypto_ecdsa_sign (NX_CRYPTO_EC * curve, switch (curve->nx_crypto_ec_id) { - #if 0 + case NX_CRYPTO_EC_SECP384R1: { /* digest - No 0 padding, skip the first 2 '0' words */ err = - HW_SCE_EcdsaP384SignatureGenerateSub(wrapped_private_key, (uint32_t *) &work_buffer[digest_offset], + HW_SCE_EcdsaP384SignatureGenerateSub(&curve_type, wrapped_private_key, (uint32_t *) &work_buffer[digest_offset], sign); break; } - #endif /* digest - 1 word 0 padding, skip the first '0' word */ case NX_CRYPTO_EC_SECP224R1: @@ -352,16 +351,14 @@ UINT sce_nx_crypto_ecdsa_verify (NX_CRYPTO_EC * curve, /* Verify procedure selection based on ECC curve (type & size) */ switch (curve->nx_crypto_ec_id) { - #if 0 case NX_CRYPTO_EC_SECP384R1: { /* digest - No 0 padding, skip the first 2 '0' words */ err = - HW_SCE_EcdsaP384SignatureVerificationSub(formatted_public_key, (uint32_t *) &digest[digest_offset], + HW_SCE_EcdsaP384SignatureVerificationSub(&curve_type, formatted_public_key, (uint32_t *) &digest[digest_offset], sign); break; } - #endif /* digest - 1 word 0 padding, skip the first '0' word */ case NX_CRYPTO_EC_SECP224R1: diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_gcm_alt.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_gcm_alt.c index d47339ec3..22f663ead 100644 --- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_gcm_alt.c +++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_gcm_alt.c @@ -158,7 +158,7 @@ USHORT result; counter_block[12] = (UCHAR)(result & 0xFF); } #if (0U == NETX_SECURE_CRYPTO_NX_CRYPTO_METHODS_AES_ALT) || ((0U == BSP_FEATURE_CRYPTO_HAS_SCE9) && \ - (0U == BSP_FEATURE_CRYPTO_HAS_SCE5B)) + (0U == BSP_FEATURE_CRYPTO_HAS_SCE5B) && (0U == BSP_FEATURE_CRYPTO_HAS_SCE7)) /**************************************************************************/ /* */ /* FUNCTION RELEASE */ @@ -296,7 +296,7 @@ UCHAR mask; NX_CRYPTO_KEEP static VOID _nx_crypto_gcm_ghash_update(UCHAR *hkey, UCHAR *input, UINT input_length, UCHAR *output) { #if (1U == NETX_SECURE_CRYPTO_NX_CRYPTO_METHODS_AES_ALT) && ((1U == BSP_FEATURE_CRYPTO_HAS_SCE9) || \ - (1U == BSP_FEATURE_CRYPTO_HAS_SCE5B)) + (1U == BSP_FEATURE_CRYPTO_HAS_SCE5B) || (1U == BSP_FEATURE_CRYPTO_HAS_SCE7)) sce_nx_crypto_gcm_ghash_update(hkey, input, input_length, output); #else UCHAR tmp_block[NX_CRYPTO_GCM_BLOCK_SIZE]; @@ -512,7 +512,7 @@ UCHAR iv_len; _nx_crypto_gcm_ghash_update(hkey, tmp_block, NX_CRYPTO_GCM_BLOCK_SIZE, j0); } #if (1U == NETX_SECURE_CRYPTO_NX_CRYPTO_METHODS_AES_ALT) && ((1U == BSP_FEATURE_CRYPTO_HAS_SCE9) || \ - (1U == BSP_FEATURE_CRYPTO_HAS_SCE5B)) + (1U == BSP_FEATURE_CRYPTO_HAS_SCE5B) || (1U == BSP_FEATURE_CRYPTO_HAS_SCE7)) NX_CRYPTO_PARAMETER_NOT_USED(counter); UINT ret = sce_nx_crypto_gcm_encrypt_init ((NX_CRYPTO_AES *)crypto_metadata, j0, additional_data, additional_len); if (NX_CRYPTO_SUCCESS != ret) @@ -601,7 +601,7 @@ UCHAR *counter = gcm_metadata -> nx_crypto_gcm_counter; return(NX_CRYPTO_PTR_ERROR); } #if (1U == NETX_SECURE_CRYPTO_NX_CRYPTO_METHODS_AES_ALT) && ((1U == BSP_FEATURE_CRYPTO_HAS_SCE9) || \ - (1U == BSP_FEATURE_CRYPTO_HAS_SCE5B)) + (1U == BSP_FEATURE_CRYPTO_HAS_SCE5B) || (1U == BSP_FEATURE_CRYPTO_HAS_SCE7)) NX_CRYPTO_PARAMETER_NOT_USED(hkey); NX_CRYPTO_PARAMETER_NOT_USED(s); NX_CRYPTO_PARAMETER_NOT_USED(counter); @@ -705,7 +705,7 @@ UINT length; tmp_block[14] = (UCHAR)(((length << 3) & 0x0000FF00) >> 8); tmp_block[15] = (UCHAR)((length << 3) & 0x000000FF); #if (1U == NETX_SECURE_CRYPTO_NX_CRYPTO_METHODS_AES_ALT) && ((1U == BSP_FEATURE_CRYPTO_HAS_SCE9) || \ - (1U == BSP_FEATURE_CRYPTO_HAS_SCE5B)) + (1U == BSP_FEATURE_CRYPTO_HAS_SCE5B) || (1U == BSP_FEATURE_CRYPTO_HAS_SCE7)) NX_CRYPTO_PARAMETER_NOT_USED(hkey); NX_CRYPTO_PARAMETER_NOT_USED(s); NX_CRYPTO_PARAMETER_NOT_USED(j0); @@ -912,7 +912,7 @@ UINT i; } #if (1U == NETX_SECURE_CRYPTO_NX_CRYPTO_METHODS_AES_ALT) && ((1U == BSP_FEATURE_CRYPTO_HAS_SCE9) || \ - (1U == BSP_FEATURE_CRYPTO_HAS_SCE5B)) + (1U == BSP_FEATURE_CRYPTO_HAS_SCE5B) || (1U == BSP_FEATURE_CRYPTO_HAS_SCE7)) /*********************************************************************************************************************** * GCM Decrypt Init and AAD setup. This includes preparing the IV. * diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_gcm_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_gcm_alt_process.c index dac865e9f..7d861036c 100644 --- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_gcm_alt_process.c +++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_gcm_alt_process.c @@ -29,7 +29,7 @@ #include "rm_netx_secure_crypto_cfg.h" #include "rm_netx_secure_crypto.h" -#if (1U == NETX_SECURE_CRYPTO_NX_CRYPTO_METHODS_AES_ALT) && ((BSP_FEATURE_CRYPTO_HAS_SCE9 == 1) || \ +#if (1U == NETX_SECURE_CRYPTO_NX_CRYPTO_METHODS_AES_ALT) && (((BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7) == 1) || \ (BSP_FEATURE_CRYPTO_HAS_SCE5B == 1)) #include "nx_crypto_aes.h" #include "hw_sce_private.h" @@ -141,7 +141,7 @@ UINT sce_nx_crypto_gcm_encrypt_init (NX_CRYPTO_AES * aes_ctx, } } - #if (BSP_FEATURE_CRYPTO_HAS_SCE9 == 1) + #if ((BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7) == 1) else if (SCE_NX_CRYPTO_AES_KEY_SIZE_192_WRAPPED_WORDS == aes_ctx->nx_crypto_aes_key_size) { err = HW_SCE_Aes192GcmEncryptInitSub((uint32_t *) (aes_ctx->nx_crypto_aes_key_schedule), @@ -215,7 +215,7 @@ UINT sce_nx_crypto_gcm_encrypt_update (NX_CRYPTO_AES * aes_ctx, UCHAR * input, U RM_NETX_SECURE_CRYPTO_BYTES_TO_WORDS(input_length)); } - #if (BSP_FEATURE_CRYPTO_HAS_SCE9 == 1) + #if ((BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7) == 1) else if (SCE_NX_CRYPTO_AES_KEY_SIZE_192_WRAPPED_WORDS == aes_ctx->nx_crypto_aes_key_size) { HW_SCE_Aes192GcmEncryptUpdateSub((uint32_t *) input, @@ -335,7 +335,7 @@ static UINT sce_nx_crypto_gcm_encrypt_final (NX_CRYPTO_AES * aes_ctx, err = HW_SCE_Aes128GcmEncryptFinalSub(input, aad_bit_size, data_bit_size, output, tag); } - #if (BSP_FEATURE_CRYPTO_HAS_SCE9 == 1) + #if ((BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7) == 1) else if (SCE_NX_CRYPTO_AES_KEY_SIZE_192_WRAPPED_WORDS == aes_ctx->nx_crypto_aes_key_size) { err = HW_SCE_Aes192GcmEncryptFinalSub(input, aad_bit_size, data_bit_size, output, tag); diff --git a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_rsa_alt_process.c b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_rsa_alt_process.c index 07352661c..65851789a 100644 --- a/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_rsa_alt_process.c +++ b/ra/fsp/src/rm_netx_secure_crypto/nx_crypto_rsa_alt_process.c @@ -123,12 +123,10 @@ UINT sce_nx_crypto_rsa_operation (const UCHAR * exponent, if (FSP_SUCCESS == err) { - #if 0 err = HW_SCE_Rsa4096ModularExponentEncryptSub((uint32_t *) &formatted_rsa_public_key_output.value, (uint32_t *) aligned_work_buffer, (uint32_t *) aligned_work_buffer); - #endif } NX_CRYPTO_MEMCPY(output, aligned_work_buffer, sizeof(aligned_work_buffer)); #endif @@ -161,12 +159,10 @@ UINT sce_nx_crypto_rsa_operation (const UCHAR * exponent, if (FSP_SUCCESS == err) { - #if 0 err = HW_SCE_Rsa3072ModularExponentEncryptSub((uint32_t *) &formatted_rsa_public_key_output.value, (uint32_t *) aligned_work_buffer, (uint32_t *) aligned_work_buffer); - #endif } NX_CRYPTO_MEMCPY(output, aligned_work_buffer, sizeof(aligned_work_buffer)); #endif diff --git a/ra/fsp/src/rm_netxduo_wifi/rm_netxduo_wifi.c b/ra/fsp/src/rm_netxduo_wifi/rm_netxduo_wifi.c index 4995bd27b..ceb487c06 100644 --- a/ra/fsp/src/rm_netxduo_wifi/rm_netxduo_wifi.c +++ b/ra/fsp/src/rm_netxduo_wifi/rm_netxduo_wifi.c @@ -71,7 +71,10 @@ #define NX_DRIVER_STATE_LINK_ENABLED 4 #define NX_DRIVER_ERROR 90 -/* Define basic netword driver information typedef. */ +/* Driver Thread Events */ +#define RM_NETXDUO_DRIVER_THREAD_EVENT_DEINITIALIZE (0x1) + +/* Define basic network driver information typedef. */ typedef struct NX_DRIVER_INFORMATION_STRUCT { @@ -105,6 +108,7 @@ static NX_DRIVER_INFORMATION nx_driver_information; static NX_DRIVER_SOCKET nx_driver_sockets[RM_NETXDUO_WIFI_SOCKETS_MAXIMUM]; static TX_THREAD nx_driver_thread; static UCHAR nx_driver_thread_stack[RM_NETXDUO_WIFI_DRIVER_THREAD_STACK_SIZE]; +static TX_EVENT_FLAGS_GROUP nx_driver_thread_events; /* Define the routines for processing each driver entry request. The contents of these routines will change with * each driver. However, the main driver entry function will not change, except for the entry function name. */ @@ -194,6 +198,28 @@ VOID rm_netxduo_wifi (NX_IP_DRIVER * driver_req_ptr) break; } + case NX_LINK_UNINITIALIZE: + { + UINT thread_state = TX_READY; + + /* Send signal for driver thread to exit */ + tx_event_flags_set(&nx_driver_thread_events, RM_NETXDUO_DRIVER_THREAD_EVENT_DEINITIALIZE, TX_OR); + + /* Wait for driver thread to exit */ + while (TX_TERMINATED != thread_state) + { + tx_thread_info_get(&nx_driver_thread, NULL, &thread_state, NULL, NULL, NULL, NULL, NULL, NULL); + tx_thread_sleep(1); + } + + /* Delete thread */ + tx_thread_delete(&nx_driver_thread); + + tx_event_flags_delete(&nx_driver_thread_events); + + break; + } + case NX_LINK_ENABLE: { /* Process link enable requests. */ @@ -751,6 +777,24 @@ static VOID _nx_driver_thread_entry (ULONG thread_input) for ( ; ; ) { + ULONG actual_events = 0; + + if (TX_SUCCESS == + tx_event_flags_get(&nx_driver_thread_events, RM_NETXDUO_DRIVER_THREAD_EVENT_DEINITIALIZE, TX_AND_CLEAR, + &actual_events, TX_NO_WAIT)) + { + /* Check for driver close */ + if (actual_events & RM_NETXDUO_DRIVER_THREAD_EVENT_DEINITIALIZE) + { + /* Attempt to release packets */ + nx_packet_release(current_packet_ptr); + nx_packet_release(next_packet_ptr); + + /* Terminate thread */ + tx_thread_terminate(&nx_driver_thread); + } + } + /* Obtain the IP internal mutex before processing the IP event. */ tx_mutex_get(&(ip_ptr->nx_ip_protection), TX_WAIT_FOREVER); @@ -1246,21 +1290,34 @@ static UINT _nx_driver_hardware_initialize (NX_IP_DRIVER * driver_req_ptr) UINT status; UINT priority = 0; - /* Get priority of IP thread. */ - tx_thread_info_get(tx_thread_identify(), NX_NULL, NX_NULL, NX_NULL, &priority, NX_NULL, NX_NULL, NX_NULL, NX_NULL); - - /* Create the driver thread. */ - /* The priority of network thread is lower than IP thread. */ - status = tx_thread_create(&nx_driver_thread, - "Driver Thread", - _nx_driver_thread_entry, - 0, - nx_driver_thread_stack, - RM_NETXDUO_WIFI_DRIVER_THREAD_STACK_SIZE, - priority + 1, - priority + 1, - TX_NO_TIME_SLICE, - TX_DONT_START); + status = tx_event_flags_create(&nx_driver_thread_events, "nx_driver_thread_events"); + + if (TX_SUCCESS == status) + { + /* Get priority of IP thread. */ + tx_thread_info_get(tx_thread_identify(), + NX_NULL, + NX_NULL, + NX_NULL, + &priority, + NX_NULL, + NX_NULL, + NX_NULL, + NX_NULL); + + /* Create the driver thread. */ + /* The priority of network thread is lower than IP thread. */ + status = tx_thread_create(&nx_driver_thread, + "Driver Thread", + _nx_driver_thread_entry, + 0, + nx_driver_thread_stack, + RM_NETXDUO_WIFI_DRIVER_THREAD_STACK_SIZE, + priority + 1, + priority + 1, + TX_NO_TIME_SLICE, + TX_DONT_START); + } /* Return success! */ return status; diff --git a/ra/fsp/src/rm_psa_crypto/aes_alt.c b/ra/fsp/src/rm_psa_crypto/aes_alt.c index a2666c4fa..c42cdea4b 100644 --- a/ra/fsp/src/rm_psa_crypto/aes_alt.c +++ b/ra/fsp/src/rm_psa_crypto/aes_alt.c @@ -1131,6 +1131,13 @@ int mbedtls_aes_crypt_xts( mbedtls_aes_xts_context *ctx, if( length > ( 1 << 20 ) * 16 ) return MBEDTLS_ERR_AES_INVALID_INPUT_LENGTH; +#if BSP_FEATURE_CRYPTO_HAS_SCE9 + if( mode == MBEDTLS_AES_ENCRYPT ) + return( mbedtls_internal_aes_encrypt_xts( &ctx->tweak, length, data_unit, input, output ) ); + else + return( mbedtls_internal_aes_decrypt_xts( &ctx->tweak, length, data_unit, input, output ) ); +#endif + /* Compute the tweak. */ ret = mbedtls_aes_crypt_ecb( &ctx->tweak, MBEDTLS_AES_ENCRYPT, data_unit, tweak ); diff --git a/ra/fsp/src/rm_psa_crypto/aes_alt_process.c b/ra/fsp/src/rm_psa_crypto/aes_alt_process.c index 788fd5289..db35a8fb3 100644 --- a/ra/fsp/src/rm_psa_crypto/aes_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/aes_alt_process.c @@ -22,60 +22,126 @@ #if defined(MBEDTLS_AES_C) - #include - - #include "mbedtls/aes.h" - #include "mbedtls/platform.h" - #include "mbedtls/platform_util.h" - #include "mbedtls/error.h" - #if defined(MBEDTLS_PADLOCK_C) - #include "mbedtls/padlock.h" - #endif - #if defined(MBEDTLS_AESNI_C) - #include "mbedtls/aesni.h" - #endif - #include "hw_sce_aes_private.h" - #include "hw_sce_private.h" - #include "hw_sce_ra_private.h" + #if defined(MBEDTLS_AES_ALT) + + #include + + #include "mbedtls/aes.h" + #include "mbedtls/platform.h" + #include "mbedtls/platform_util.h" + #include "mbedtls/error.h" + #if defined(MBEDTLS_PADLOCK_C) + #include "mbedtls/padlock.h" + #endif + #if defined(MBEDTLS_AESNI_C) + #include "mbedtls/aesni.h" + #endif + #include "hw_sce_aes_private.h" + #include "hw_sce_private.h" + #include "hw_sce_ra_private.h" /* * 32-bit integer manipulation macros (little endian) */ - #ifndef GET_UINT32_LE - #define GET_UINT32_LE(n, b, i) \ + #ifndef GET_UINT32_LE + #define GET_UINT32_LE(n, b, i) \ { \ (n) = ((uint32_t) (b)[(i)]) \ | ((uint32_t) (b)[(i) + 1] << 8) \ | ((uint32_t) (b)[(i) + 2] << 16) \ | ((uint32_t) (b)[(i) + 3] << 24); \ } - #endif + #endif - #ifndef PUT_UINT32_LE - #define PUT_UINT32_LE(n, b, i) \ + #ifndef PUT_UINT32_LE + #define PUT_UINT32_LE(n, b, i) \ { \ (b)[(i)] = (unsigned char) (((n)) & 0xFF); \ (b)[(i) + 1] = (unsigned char) (((n) >> 8) & 0xFF); \ (b)[(i) + 2] = (unsigned char) (((n) >> 16) & 0xFF); \ (b)[(i) + 3] = (unsigned char) (((n) >> 24) & 0xFF); \ } - #endif + #endif -/** - * \brief This function sets the decryption/decryption key. - * - * \param ctx The AES context to which the key should be bound. - * It must be initialized. - * \param key The decryption key. - * This must be a readable buffer of size \p keybits bits. - * \param keybits The size of data passed. Valid options are: - *
  • 128 bits
    • - *
  • 256 bits
- * - * \return \c 0 on success. - * \return #MBEDTLS_ERR_AES_INVALID_KEY_LENGTH on failure. - */ - #if defined(MBEDTLS_AES_SETKEY_ENC_ALT) || defined(MBEDTLS_AES_SETKEY_DEC_ALT) + #if defined(MBEDTLS_CIPHER_MODE_XTS) + #if BSP_FEATURE_CRYPTO_HAS_SCE9 +int aes_xts_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, unsigned int keybits) +{ + FSP_ASSERT(ctx); + FSP_ASSERT(key); + int ret = 0; + unsigned int local_keybits = 0; + const unsigned char * p_internal_key = key; + + /* Create storage to hold the generated OEM key index. Size = Largest key size possible. */ + uint8_t encrypted_aes_key[SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED] = {0}; + + switch (keybits) + { + case HW_SCE_AES128XTS_KEY_BIT_SIZE: + { + local_keybits = SIZE_AES_XTS_128BIT_KEYLEN_BITS_WRAPPED; + ctx->nr = 10; + if (false == (bool) ctx->vendor_ctx) + { + p_internal_key = encrypted_aes_key; + ret = (int) HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, + SCE_OEM_CMD_AES128_XTS, + NULL, + NULL, + key, + (uint32_t *) p_internal_key); + ctx->vendor_ctx = (bool *) true; + } + + break; + } + + case HW_SCE_AES256XTS_KEY_BIT_SIZE: + { + local_keybits = SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED; + ctx->nr = 14; + if (false == (bool) ctx->vendor_ctx) + { + p_internal_key = encrypted_aes_key; + ret = (int) HW_SCE_GenerateOemKeyIndexPrivate(SCE_OEM_KEY_TYPE_PLAIN, + SCE_OEM_CMD_AES256_XTS, + NULL, + NULL, + key, + (uint32_t *) p_internal_key); + ctx->vendor_ctx = (bool *) true; + } + + break; + } + + default: + + ret = MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + if (0 == ret) + { + ctx->state = SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT; + + /* Store the encrypted key into the buffer */ + for (uint32_t i = 0; i < (local_keybits >> 5); i++) + { + /* buf is large enough to hold AES 192 bit wrapped key + * (largest key due to 32 bit padding for differentiating it from 256 wrapped key) + * */ + GET_UINT32_LE(ctx->buf[i], p_internal_key, i << 2); + } + } + + return ret; +} + + #endif + #endif // defined(MBEDTLS_AES_SETKEY_ENC_ALT) || defined(MBEDTLS_AES_SETKEY_DEC_ALT) + + #if defined(MBEDTLS_AES_SETKEY_ENC_ALT) || defined(MBEDTLS_AES_SETKEY_DEC_ALT) int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, unsigned int keybits) { FSP_ASSERT(ctx); @@ -83,16 +149,18 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un int ret = 0; unsigned int local_keybits = 0; const unsigned char * p_internal_key = key; - #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 + #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || \ + BSP_FEATURE_CRYPTO_HAS_SCE7 /* Create storage to hold the generated OEM key index. Size = Largest key size possible. */ uint8_t encrypted_aes_key[SIZE_AES_192BIT_KEYLEN_BYTES_WRAPPED] = {0}; - #endif + #endif switch (keybits) { case SIZE_AES_128BIT_KEYLEN_BITS: { - #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 + #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || \ + BSP_FEATURE_CRYPTO_HAS_SCE7 local_keybits = SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED; ctx->nr = 10; if (false == (bool) ctx->vendor_ctx) @@ -107,7 +175,7 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un ctx->vendor_ctx = (bool *) true; } - #else + #else if (true == (bool) ctx->vendor_ctx) { local_keybits = SIZE_AES_128BIT_KEYLEN_BITS_WRAPPED; @@ -117,13 +185,14 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un local_keybits = keybits; } ctx->nr = 10; - #endif + #endif break; } case SIZE_AES_192BIT_KEYLEN_BITS: { - #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 + #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || \ + BSP_FEATURE_CRYPTO_HAS_SCE7 local_keybits = SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED; ctx->nr = 12; if (false == (bool) ctx->vendor_ctx) @@ -138,7 +207,7 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un ctx->vendor_ctx = (bool *) true; } - #else + #else if (true == (bool) ctx->vendor_ctx) { local_keybits = SIZE_AES_192BIT_KEYLEN_BITS_WRAPPED; @@ -148,13 +217,14 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un local_keybits = keybits; } ctx->nr = 12; - #endif + #endif break; } case SIZE_AES_256BIT_KEYLEN_BITS: { - #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 + #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || \ + BSP_FEATURE_CRYPTO_HAS_SCE7 local_keybits = SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED; ctx->nr = 14; if (false == (bool) ctx->vendor_ctx) @@ -169,7 +239,7 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un ctx->vendor_ctx = (bool *) true; } - #else + #else if (true == (bool) ctx->vendor_ctx) { local_keybits = SIZE_AES_256BIT_KEYLEN_BITS_WRAPPED; @@ -179,7 +249,7 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un local_keybits = keybits; } ctx->nr = 14; - #endif + #endif break; } @@ -206,31 +276,153 @@ int aes_setkey_generic (mbedtls_aes_context * ctx, const unsigned char * key, un return ret; } - #endif // defined(MBEDTLS_AES_SETKEY_ENC_ALT) || defined(MBEDTLS_AES_SETKEY_DEC_ALT) + #endif /* * AES key schedule (encryption) */ - #if defined(MBEDTLS_AES_SETKEY_ENC_ALT) + #if defined(MBEDTLS_AES_SETKEY_ENC_ALT) int mbedtls_aes_setkey_enc (mbedtls_aes_context * ctx, const unsigned char * key, unsigned int keybits) { return aes_setkey_generic(ctx, key, keybits); } - #endif /* !MBEDTLS_AES_SETKEY_ENC_ALT */ + #endif /* !MBEDTLS_AES_SETKEY_ENC_ALT */ /* * AES key schedule (decryption) */ - #if defined(MBEDTLS_AES_SETKEY_DEC_ALT) + #if defined(MBEDTLS_AES_SETKEY_DEC_ALT) int mbedtls_aes_setkey_dec (mbedtls_aes_context * ctx, const unsigned char * key, unsigned int keybits) { return aes_setkey_generic(ctx, key, keybits); } - #endif /* !MBEDTLS_AES_SETKEY_DEC_ALT */ + #endif /* !MBEDTLS_AES_SETKEY_DEC_ALT */ + + #if defined(MBEDTLS_CIPHER_MODE_XTS) + + #if !(BSP_FEATURE_CRYPTO_HAS_SCE9) +static int mbedtls_aes_xts_decode_keys (const unsigned char * key, + unsigned int keybits, + const unsigned char ** key1, + unsigned int * key1bits, + const unsigned char ** key2, + unsigned int * key2bits) +{ + const unsigned int half_keybits = keybits / 2; + const unsigned int half_keybytes = half_keybits / 8; + + switch (keybits) + { + case HW_SCE_AES128XTS_KEY_BIT_SIZE: + {} + break; + + case HW_SCE_AES256XTS_KEY_BIT_SIZE: + {} + break; + + default: + + return MBEDTLS_ERR_AES_INVALID_KEY_LENGTH; + } + + *key1bits = half_keybits; + *key2bits = half_keybits; + *key1 = &key[0]; + *key2 = &key[half_keybytes]; + + return 0; +} + + #endif + +int mbedtls_aes_xts_setkey_enc (mbedtls_aes_xts_context * ctx, const unsigned char * key, unsigned int keybits) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + (void) ctx; + (void) key; + (void) keybits; + + #if BSP_FEATURE_CRYPTO_HAS_SCE9 + ret = aes_xts_setkey_generic(&ctx->tweak, key, keybits); + if (ret != 0) + { + return ret; + } + #endif + + #if !(BSP_FEATURE_CRYPTO_HAS_SCE9) + const unsigned char * key1; + const unsigned char * key2; + unsigned int key1bits; + unsigned int key2bits; + + ret = mbedtls_aes_xts_decode_keys(key, keybits, &key1, &key1bits, &key2, &key2bits); + if (ret != 0) + { + return ret; + } + + /* Set the tweak key. Always set tweak key for the encryption mode. */ + ret = mbedtls_aes_setkey_enc(&ctx->tweak, key2, key2bits); + if (ret != 0) + { + return ret; + } + + /* Set crypt key for encryption. */ + ret = mbedtls_aes_setkey_enc(&ctx->crypt, key1, key1bits); + #endif + + return ret; +} + +int mbedtls_aes_xts_setkey_dec (mbedtls_aes_xts_context * ctx, const unsigned char * key, unsigned int keybits) +{ + int ret = MBEDTLS_ERR_ERROR_CORRUPTION_DETECTED; + (void) ctx; + (void) key; + (void) keybits; + + #if BSP_FEATURE_CRYPTO_HAS_SCE9 + ret = aes_xts_setkey_generic(&ctx->tweak, key, keybits); + if (ret != 0) + { + return ret; + } + #endif + + #if !(BSP_FEATURE_CRYPTO_HAS_SCE9) + const unsigned char * key1; + const unsigned char * key2; + unsigned int key1bits; + unsigned int key2bits; + + ret = mbedtls_aes_xts_decode_keys(key, keybits, &key1, &key1bits, &key2, &key2bits); + if (ret != 0) + { + return ret; + } + + /* Set the tweak key. Always set tweak key for encryption. */ + ret = mbedtls_aes_setkey_enc(&ctx->tweak, key2, key2bits); + if (ret != 0) + { + return ret; + } + + /* Set crypt key for decryption. */ + ret = mbedtls_aes_setkey_dec(&ctx->crypt, key1, key1bits); + #endif + + return ret; +} + + #endif /* MBEDTLS_CIPHER_MODE_XTS */ - #if defined(MBEDTLS_AES_ENCRYPT_ALT) + #if defined(MBEDTLS_AES_ENCRYPT_ALT) /* * AES-ECB block encryption @@ -263,7 +455,7 @@ int mbedtls_internal_aes_encrypt (mbedtls_aes_context * ctx, const unsigned char err = HW_SCE_Aes128EncryptDecryptFinalSub(); } - #if BSP_FEATURE_CRYPTO_HAS_SCE9 + #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7 else if (ctx->nr == 12) { err = HW_SCE_Aes192EncryptDecryptInitSub(&indata_cmd, ctx->buf, dummy_iv); @@ -274,7 +466,7 @@ int mbedtls_internal_aes_encrypt (mbedtls_aes_context * ctx, const unsigned char err = HW_SCE_Aes192EncryptDecryptFinalSub(); } - #endif + #endif else if (ctx->nr == 14) { err = HW_SCE_Aes256EncryptDecryptInitSub(&indata_key_type, &indata_cmd, ctx->buf, dummy_iv); @@ -368,14 +560,126 @@ int mbedtls_internal_aes_encrypt_cbc (mbedtls_aes_context * ctx, return ret; } - #endif /* !MBEDTLS_AES_ENCRYPT_ALT */ + #if BSP_FEATURE_CRYPTO_HAS_SCE9 +int mbedtls_internal_aes_encrypt_xts (mbedtls_aes_context * ctx, + unsigned int length, + const unsigned char * iv, + const unsigned char * input, + unsigned char * output) +{ + (void) length; + (void) input; + (void) output; + fsp_err_t err = FSP_SUCCESS; + int ret = 0; + + uint32_t bitlen = 0; + uint32_t text_bitlen = length * 8; + uint32_t input_data_size = 0; + uint32_t copy_size = 0; + uint8_t local_input[HW_SCE_AES_BLOCK_BYTE_SIZE * 2]; + uint8_t local_output[HW_SCE_AES_BLOCK_BYTE_SIZE * 2]; + + if (ctx->nr == 10) + { + if (SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT == ctx->state) + { + err = HW_SCE_Aes128XtsEncryptInitSub(ctx->buf, (uint32_t *) &iv[0]); + if (FSP_SUCCESS != err) + { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + ctx->state = SCE_MBEDTLS_CIPHER_OPERATION_STATE_UPDATE; + } + + if ((text_bitlen % HW_SCE_AES_BLOCK_BIT_SIZE) == 0) + { + HW_SCE_Aes128XtsEncryptUpdateSub((uint32_t *) input, (uint32_t *) output, length >> 2); + + bitlen = change_endian_long(0U); + + err = HW_SCE_Aes128XtsEncryptFinalSub(&bitlen, (uint32_t *) input, (uint32_t *) output); + if (err == 0U) + { + /* Once final is successful, change operation state back to SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT to allow same AES key to + * be used for subsequent operations */ + ctx->state = SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT; + } + else + { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + } + else + { + if (text_bitlen < HW_SCE_AES_BLOCK_BIT_SIZE) + { + input_data_size = 0; + memcpy(local_input, input, length); + bitlen = change_endian_long(HW_SCE_AES_BLOCK_BIT_SIZE); + } + else if (text_bitlen > (HW_SCE_AES_BLOCK_BIT_SIZE * 2)) + { + copy_size = length % HW_SCE_AES_BLOCK_BYTE_SIZE; + if (copy_size == 0) + { + copy_size = HW_SCE_AES_BLOCK_BYTE_SIZE; + } + + memcpy(local_input, + input + ((text_bitlen / HW_SCE_AES_BLOCK_BIT_SIZE - 1) * HW_SCE_AES_BLOCK_BYTE_SIZE), + copy_size + HW_SCE_AES_BLOCK_BYTE_SIZE); + + input_data_size = text_bitlen / HW_SCE_AES_BLOCK_BIT_SIZE - 1; + + HW_SCE_Aes128XtsEncryptUpdateSub((uint32_t *) input, (uint32_t *) output, input_data_size << 2); + + bitlen = change_endian_long(text_bitlen - (input_data_size * HW_SCE_AES_BLOCK_BIT_SIZE)); + } + else + { + input_data_size = 0; + memcpy(local_input, input, length); + bitlen = change_endian_long(text_bitlen); + } + + err = HW_SCE_Aes128XtsEncryptFinalSub(&bitlen, (uint32_t *) local_input, (uint32_t *) local_output); + if (err == 0U) + { + /* Once final is successful, change operation state back to SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT to allow same AES key to + * be used for subsequent operations */ + ctx->state = SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT; + memcpy((output + (input_data_size * HW_SCE_AES_BLOCK_BYTE_SIZE)), local_output, length); + } + else + { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + } + } + else + { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + if (FSP_SUCCESS != err) + { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + return ret; +} + + #endif + #endif /* !MBEDTLS_AES_ENCRYPT_ALT */ /* * AES-ECB block decryption * NOTE: The return code from this function is not checked by the mbedCrypto implementation, * so a failure here wont show up in the calling layer. */ - #if defined(MBEDTLS_AES_DECRYPT_ALT) + #if defined(MBEDTLS_AES_DECRYPT_ALT) int mbedtls_internal_aes_decrypt (mbedtls_aes_context * ctx, const unsigned char input[16], unsigned char output[16]) { @@ -402,7 +706,7 @@ int mbedtls_internal_aes_decrypt (mbedtls_aes_context * ctx, const unsigned char err = HW_SCE_Aes128EncryptDecryptFinalSub(); } - #if BSP_FEATURE_CRYPTO_HAS_SCE9 + #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7 else if (ctx->nr == 12) { err = HW_SCE_Aes192EncryptDecryptInitSub(&indata_cmd, ctx->buf, dummy_iv); @@ -413,7 +717,7 @@ int mbedtls_internal_aes_decrypt (mbedtls_aes_context * ctx, const unsigned char err = HW_SCE_Aes192EncryptDecryptFinalSub(); } - #endif + #endif else if (ctx->nr == 14) { err = HW_SCE_Aes256EncryptDecryptInitSub(&indata_key_type, &indata_cmd, ctx->buf, dummy_iv); @@ -506,9 +810,117 @@ int mbedtls_internal_aes_decrypt_cbc (mbedtls_aes_context * ctx, return ret; } - #endif /* !MBEDTLS_AES_DECRYPT_ALT */ + #if BSP_FEATURE_CRYPTO_HAS_SCE9 +int mbedtls_internal_aes_decrypt_xts (mbedtls_aes_context * ctx, + unsigned int length, + const unsigned char * iv, + const unsigned char * input, + unsigned char * output) +{ + fsp_err_t err = FSP_SUCCESS; + int ret = 0; + + uint32_t bitlen = 0; + uint32_t text_bitlen = length * 8; + uint32_t input_data_size = 0; + uint32_t copy_size = 0; + uint8_t local_input[HW_SCE_AES_BLOCK_BYTE_SIZE * 2]; + uint8_t local_output[HW_SCE_AES_BLOCK_BYTE_SIZE * 2]; + + if (ctx->nr == 10) + { + if (SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT == ctx->state) + { + err = HW_SCE_Aes128XtsDecryptInitSub(ctx->buf, (uint32_t *) &iv[0]); + if (FSP_SUCCESS != err) + { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + ctx->state = SCE_MBEDTLS_CIPHER_OPERATION_STATE_UPDATE; + } + + if ((text_bitlen % HW_SCE_AES_BLOCK_BIT_SIZE) == 0) + { + HW_SCE_Aes128XtsDecryptUpdateSub((uint32_t *) input, (uint32_t *) output, length >> 2); + + bitlen = change_endian_long(0); + err = HW_SCE_Aes128XtsDecryptFinalSub(&bitlen, (uint32_t *) input, (uint32_t *) output); + if (err == 0U) + { + /* Once final is successful, change operation state back to SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT to allow same AES key to + * be used for subsequent operations */ + ctx->state = SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT; + } + else + { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + } + else + { + if (text_bitlen < HW_SCE_AES_BLOCK_BIT_SIZE) + { + input_data_size = 0; + memcpy(local_input, input, HW_SCE_AES_BLOCK_BYTE_SIZE); + bitlen = change_endian_long(HW_SCE_AES_BLOCK_BIT_SIZE); + } + else if (text_bitlen > (HW_SCE_AES_BLOCK_BIT_SIZE * 2)) + { + copy_size = length % HW_SCE_AES_BLOCK_BYTE_SIZE; + if (copy_size == 0) + { + copy_size = HW_SCE_AES_BLOCK_BYTE_SIZE; + } - #if defined(MBEDTLS_AES_DECRYPT_ALT) || defined(MBEDTLS_AES_ENCRYPT_ALT) + memcpy(local_input, + input + ((text_bitlen / HW_SCE_AES_BLOCK_BIT_SIZE - 1) * HW_SCE_AES_BLOCK_BYTE_SIZE), + copy_size + HW_SCE_AES_BLOCK_BYTE_SIZE); + + input_data_size = text_bitlen / HW_SCE_AES_BLOCK_BIT_SIZE - 1; + + HW_SCE_Aes128XtsDecryptUpdateSub((uint32_t *) input, (uint32_t *) output, input_data_size << 2); + + bitlen = change_endian_long(text_bitlen - (input_data_size * HW_SCE_AES_BLOCK_BIT_SIZE)); + } + else + { + input_data_size = 0; + memcpy(local_input, input, HW_SCE_AES_BLOCK_BYTE_SIZE * 2); + bitlen = change_endian_long(text_bitlen); + } + + err = HW_SCE_Aes128XtsDecryptFinalSub(&bitlen, (uint32_t *) local_input, (uint32_t *) local_output); + if (err == 0U) + { + /* Once final is successful, change operation state back to SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT to allow same AES key to + * be used for subsequent operations */ + ctx->state = SCE_MBEDTLS_CIPHER_OPERATION_STATE_INIT; + memcpy((output + (input_data_size * HW_SCE_AES_BLOCK_BYTE_SIZE)), local_output, length); + } + else + { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + } + } + else + { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } + + if (FSP_SUCCESS != err) + { + return MBEDTLS_ERR_PLATFORM_HW_ACCEL_FAILED; + } + + return ret; +} + + #endif + #endif /* !MBEDTLS_AES_DECRYPT_ALT */ + + #if defined(MBEDTLS_AES_DECRYPT_ALT) || defined(MBEDTLS_AES_ENCRYPT_ALT) int mbedtls_internal_aes_encrypt_decrypt_ctr (mbedtls_aes_context * ctx, unsigned int length, @@ -613,6 +1025,6 @@ int mbedtls_internal_aes_crypt_ctr_finish (mbedtls_aes_context * ctx) return 0; } - #endif /* !MBEDTLS_AES_DECRYPT_ALT */ - + #endif /* !MBEDTLS_AES_DECRYPT_ALT */ + #endif /* MBEDTLS_AES_ALT */ #endif /* MBEDTLS_AES_C */ diff --git a/ra/fsp/src/rm_psa_crypto/aes_vendor.c b/ra/fsp/src/rm_psa_crypto/aes_vendor.c index f67f32e3c..d73490fd6 100644 --- a/ra/fsp/src/rm_psa_crypto/aes_vendor.c +++ b/ra/fsp/src/rm_psa_crypto/aes_vendor.c @@ -148,7 +148,7 @@ psa_status_t psa_generate_symmetric_vendor (psa_key_type_t type, size_t bits, ui break; } - #if BSP_FEATURE_CRYPTO_HAS_SCE9 + #if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE7 case SIZE_AES_192BIT_KEYLEN_BITS: { if (output_size != SIZE_AES_192BIT_KEYLEN_BYTES_WRAPPED) diff --git a/ra/fsp/src/rm_psa_crypto/cipher_alt.c b/ra/fsp/src/rm_psa_crypto/cipher_alt.c index c8112a0f8..d3bf01a68 100644 --- a/ra/fsp/src/rm_psa_crypto/cipher_alt.c +++ b/ra/fsp/src/rm_psa_crypto/cipher_alt.c @@ -79,7 +79,7 @@ #define CIPHER_VALIDATE( cond ) \ MBEDTLS_INTERNAL_VALIDATE( cond ) -#if (BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5) && defined(MBEDTLS_AES_C) && defined(MBEDTLS_AES_ALT) +#if (BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7) && defined(MBEDTLS_AES_C) && defined(MBEDTLS_AES_ALT) static int sce_aes_cipher_final( mbedtls_cipher_context_t *ctx ) { int ret = 0; @@ -112,7 +112,7 @@ static int sce_aes_cipher_final( mbedtls_cipher_context_t *ctx ) return( 0 ); } -#endif /* (BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5) && MBEDTLS_AES_C && MBEDTLS_AES_ALT */ +#endif /* (BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7) && MBEDTLS_AES_C && MBEDTLS_AES_ALT */ static int supported_init = 0; @@ -1103,7 +1103,7 @@ int mbedtls_cipher_finish( mbedtls_cipher_context_t *ctx, if( 0 != ctx->unprocessed_len ) return( MBEDTLS_ERR_CIPHER_FULL_BLOCK_EXPECTED ); -#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 +#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 return sce_aes_cipher_final( ctx ); #else return( 0 ); @@ -1123,7 +1123,7 @@ int mbedtls_cipher_finish( mbedtls_cipher_context_t *ctx, if( NULL == ctx->add_padding && 0 == ctx->unprocessed_len ) { -#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 +#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 return sce_aes_cipher_final( ctx ); #else return( 0 ); @@ -1144,7 +1144,7 @@ int mbedtls_cipher_finish( mbedtls_cipher_context_t *ctx, /* Set output size for decryption */ if( MBEDTLS_DECRYPT == ctx->operation ) { -#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 +#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 if( 0 != ( ret = sce_aes_cipher_final( ctx ))) { return( ret ); @@ -1157,7 +1157,7 @@ int mbedtls_cipher_finish( mbedtls_cipher_context_t *ctx, /* Set output size for encryption */ *olen = mbedtls_cipher_get_block_size( ctx ); -#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 +#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 return sce_aes_cipher_final( ctx ); #else return( 0 ); @@ -1190,7 +1190,7 @@ int mbedtls_cipher_finish( mbedtls_cipher_context_t *ctx, *olen = ctx->unprocessed_len; } -#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 +#if BSP_FEATURE_CRYPTO_HAS_SCE9 || BSP_FEATURE_CRYPTO_HAS_SCE5B || BSP_FEATURE_CRYPTO_HAS_SCE5 || BSP_FEATURE_CRYPTO_HAS_SCE7 return sce_aes_cipher_final( ctx ); #else return( 0 ); diff --git a/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c b/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c index 4b4ab38b6..baf9d69af 100644 --- a/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/ecdsa_alt_process.c @@ -24,45 +24,6 @@ #if (defined(MBEDTLS_ECDSA_SIGN_ALT) || defined(MBEDTLS_ECDSA_VERIFY_ALT) || defined(MBEDTLS_ECP_ALT)) - #if BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS -fsp_err_t HW_SCE_EcdsaP384SignatureGenerateSub(const uint32_t * InData_CurveType, - const uint32_t * InData_KeyIndex, - const uint32_t * InData_MsgDgst, - uint32_t * OutData_Signature); - -fsp_err_t HW_SCE_EcdsaP384SignatureGenerateSub (const uint32_t * InData_CurveType, - const uint32_t * InData_KeyIndex, - const uint32_t * InData_MsgDgst, - uint32_t * OutData_Signature) -{ - FSP_PARAMETER_NOT_USED(InData_CurveType); - FSP_PARAMETER_NOT_USED(InData_KeyIndex); - FSP_PARAMETER_NOT_USED(InData_MsgDgst); - FSP_PARAMETER_NOT_USED(OutData_Signature); - - return FSP_ERR_UNSUPPORTED; -} - -fsp_err_t HW_SCE_EcdsaP384SignatureVerificationSub(const uint32_t * InData_CurveType, - const uint32_t * InData_KeyIndex, - const uint32_t * InData_MsgDgst, - const uint32_t * InData_Signature); - -fsp_err_t HW_SCE_EcdsaP384SignatureVerificationSub (const uint32_t * InData_CurveType, - const uint32_t * InData_KeyIndex, - const uint32_t * InData_MsgDgst, - const uint32_t * InData_Signature) -{ - FSP_PARAMETER_NOT_USED(InData_CurveType); - FSP_PARAMETER_NOT_USED(InData_KeyIndex); - FSP_PARAMETER_NOT_USED(InData_MsgDgst); - FSP_PARAMETER_NOT_USED(InData_Signature); - - return FSP_ERR_UNSUPPORTED; -} - - #endif - fsp_err_t HW_SCE_ECC_256GenerateSign (const uint32_t * InData_DomainParam, const uint32_t * InData_G, const uint32_t * InData_PrivKey, @@ -175,7 +136,7 @@ fsp_err_t HW_SCE_ECC_384GenerateSign (const uint32_t * InData_DomainParam, if (FSP_SUCCESS == err) { err = - HW_SCE_EcdsaP384SignatureGenerateSub(InData_DomainParam, wrapped_private_key, InData_MsgDgst, signature); + HW_SCE_EcdsaP384SignatureGenerateSub((uint32_t *)InData_DomainParam, wrapped_private_key, InData_MsgDgst, signature); } if (FSP_SUCCESS == err) @@ -198,7 +159,7 @@ fsp_err_t HW_SCE_ECC_384HrkGenerateSign (const uint32_t * InData_DomainParam, FSP_PARAMETER_NOT_USED(InData_G); uint32_t signature[HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 4U] = {0}; fsp_err_t err = - HW_SCE_EcdsaP384SignatureGenerateSub(InData_DomainParam, InData_KeyIndex, InData_MsgDgst, signature); + HW_SCE_EcdsaP384SignatureGenerateSub((uint32_t *)InData_DomainParam, InData_KeyIndex, InData_MsgDgst, signature); if (FSP_SUCCESS == err) { memcpy(OutData_R, signature, (HW_SCE_ECDSA_P384_DATA_BYTE_SIZE / 2U)); @@ -298,7 +259,7 @@ fsp_err_t HW_SCE_ECC_384VerifySign (const uint32_t * InData_DomainParam, formatted_public_key); if (FSP_SUCCESS == err) { - err = HW_SCE_EcdsaP384SignatureVerificationSub(InData_DomainParam, + err = HW_SCE_EcdsaP384SignatureVerificationSub((uint32_t *)InData_DomainParam, formatted_public_key, InData_MsgDgst, signature); diff --git a/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c b/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c index 8334a1cff..2cf039237 100644 --- a/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/ecp_alt_process.c @@ -90,26 +90,6 @@ fsp_err_t HW_SCE_ECC_256WrappedScalarMultiplication (const uint32_t * InData_Cur return HW_SCE_Ecc256ScalarMultiplicationSub(InData_CurveType, InData_Cmd, InData_KeyIndex, InData_P, OutData_R); } - #if BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS -fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSub(const uint32_t * InData_CurveType, - const uint32_t * InData_KeyIndex, - const uint32_t * InData_PubKey, - uint32_t * OutData_R); - -fsp_err_t HW_SCE_Ecc384ScalarMultiplicationSub (const uint32_t * InData_CurveType, - const uint32_t * InData_KeyIndex, - const uint32_t * InData_PubKey, - uint32_t * OutData_R) -{ - FSP_PARAMETER_NOT_USED(InData_CurveType); - FSP_PARAMETER_NOT_USED(InData_KeyIndex); - FSP_PARAMETER_NOT_USED(InData_PubKey); - FSP_PARAMETER_NOT_USED(OutData_R); - - return FSP_ERR_UNSUPPORTED; -} - - #endif fsp_err_t HW_SCE_ECC_384WrappedScalarMultiplication (const uint32_t * InData_CurveType, const uint32_t * InData_Cmd, const uint32_t * InData_KeyIndex, diff --git a/ra/fsp/src/rm_psa_crypto/inc/aes_alt.h b/ra/fsp/src/rm_psa_crypto/inc/aes_alt.h index b86b97747..8faeca00c 100644 --- a/ra/fsp/src/rm_psa_crypto/inc/aes_alt.h +++ b/ra/fsp/src/rm_psa_crypto/inc/aes_alt.h @@ -65,6 +65,8 @@ typedef struct mbedtls_aes_xts_context #endif /* MBEDTLS_CIPHER_MODE_XTS */ int aes_setkey_generic(mbedtls_aes_context * ctx, const unsigned char * key, unsigned int keybits); +int aes_xts_setkey_generic(mbedtls_aes_context * ctx, const unsigned char * key, unsigned int keybits); + int mbedtls_internal_aes_encrypt_cbc(mbedtls_aes_context * ctx, unsigned int length, unsigned char * iv, @@ -75,6 +77,16 @@ int mbedtls_internal_aes_decrypt_cbc(mbedtls_aes_context * ctx, unsigned char * iv, const unsigned char * input, unsigned char * output); +int mbedtls_internal_aes_encrypt_xts(mbedtls_aes_context * ctx, + unsigned int length, + const unsigned char * iv, + const unsigned char * input, + unsigned char * output); +int mbedtls_internal_aes_decrypt_xts(mbedtls_aes_context * ctx, + unsigned int length, + const unsigned char * iv, + const unsigned char * input, + unsigned char * output); int mbedtls_internal_aes_encrypt_decrypt_ctr(mbedtls_aes_context * ctx, unsigned int length, unsigned char * iv, diff --git a/ra/fsp/src/rm_psa_crypto/rsa_alt.c b/ra/fsp/src/rm_psa_crypto/rsa_alt.c index e0ac0aee4..85d344522 100644 --- a/ra/fsp/src/rm_psa_crypto/rsa_alt.c +++ b/ra/fsp/src/rm_psa_crypto/rsa_alt.c @@ -451,41 +451,28 @@ int mbedtls_rsa_export_crt( const mbedtls_rsa_context *ctx, #else /* CRT deduction is not applicable to MCU generated wrapped keys so we will add in some dummy values to get past the non-zero check in the import code */ - #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_RSA_FORMAT) - if (true == (bool) ctx->vendor_ctx) + + uint8_t dummy_val[4] ={0xFF, 0xFF, 0xFF, 0xFF}; + if (DP != NULL) { - uint8_t dummy_val[4] ={0xFF, 0xFF, 0xFF, 0xFF}; - if (DP != NULL) - { - ret = mbedtls_mpi_read_binary(DP, dummy_val, sizeof(dummy_val)); - } - else if (DQ != NULL) - { - ret = mbedtls_mpi_read_binary(DQ, dummy_val, sizeof(dummy_val)); - } - else if (QP != NULL) - { - ret = mbedtls_mpi_read_binary(QP, dummy_val, sizeof(dummy_val)); - } - else - { - ret = 0; - } - return ret; + ret = mbedtls_mpi_read_binary(DP, dummy_val, sizeof(dummy_val)); } - else - #endif // #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_RSA_FORMAT) + else if (DQ != NULL) { - ret = mbedtls_rsa_deduce_crt(&ctx->P, &ctx->Q, &ctx->D, DP, DQ, QP); - if (ret) - { - return( MBEDTLS_ERROR_ADD( MBEDTLS_ERR_RSA_BAD_INPUT_DATA, ret ) ); - } + ret = mbedtls_mpi_read_binary(DQ, dummy_val, sizeof(dummy_val)); + } + else if (QP != NULL) + { + ret = mbedtls_mpi_read_binary(QP, dummy_val, sizeof(dummy_val)); } + else + { + ret = 0; + } + return ret; #endif - return( 0 ); } /* diff --git a/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c b/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c index ee99e6cf1..5abb0bfd8 100644 --- a/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c +++ b/ra/fsp/src/rm_psa_crypto/rsa_alt_process.c @@ -55,7 +55,7 @@ #define RM_PSA_CRYPTO_RSA_KEY_WRAPPED (1U) #define RM_PSA_CRYPTO_DUMMY_KEY_BYTES (20U) - #if BSP_FEATURE_CRYPTO_HAS_SCE7_MISSING_PROCS + #if BSP_FEATURE_CRYPTO_HAS_SCE7 fsp_err_t HW_SCE_Rsa3072ModularExponentEncryptSub (const uint32_t * InData_KeyIndex, const uint32_t * InData_Text, uint32_t * OutData_Text) @@ -166,6 +166,54 @@ fsp_err_t HW_SCE_HRK_RSA_2048PrivateKeyDecrypt (const uint32_t * InData_Text, return err; } +fsp_err_t HW_SCE_RSA_2048KeyGenerate (uint32_t num_tries, + uint32_t * OutData_PrivateKey, + uint32_t * OutData_N, + uint32_t * OutData_DomainParam) + +{ + sce_rsa2048_key_pair_index_t key_pair_index = {0}; + fsp_err_t err = FSP_SUCCESS; + uint32_t local_dummy[RM_PSA_CRYPTO_DUMMY_KEY_BYTES / 4U]; + uint32_t indata_key_type = SCE_OEM_KEY_TYPE_PLAIN; + + /* P.Q are the prime 1 and 2 fields that are in some cases generated when the private key is generated. + * This was the case with W1D; but this information is not provided on the RA6M4. + * There is no functional issue since the procedures do not require it for operation, + * however mbedCrypto requires these fields to be non-zero in order for the private key_export to work. + * These dummy values are placed into those fields to get past the non-zero check. */ + uint8_t dummy_P_Q[24] = {5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5, 5}; + + err = + HW_SCE_GenerateRsa2048RandomKeyIndexSub(num_tries, + &indata_key_type, + local_dummy, + (uint32_t *) &key_pair_index.pub_key.plain_value, + local_dummy, + (uint32_t *) &key_pair_index.priv_key.plain_value); + + if (FSP_SUCCESS == err) + { + memcpy(OutData_PrivateKey, &key_pair_index.priv_key.plain_value, sizeof(key_pair_index.priv_key.plain_value)); + memcpy(OutData_N, &key_pair_index.pub_key.plain_value, sizeof(key_pair_index.pub_key.value.key_n)); + memcpy((uint8_t *) OutData_DomainParam, dummy_P_Q, sizeof(dummy_P_Q)); + } + + return err; +} + +static const hw_sce_rsa_generatekey_t g_rsa_keygen_lookup[2] = +{ + #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_RSA_FORMAT) + [RM_PSA_CRYPTO_RSA_KEY_PLAINTEXT] = + HW_SCE_RSA_2048KeyGenerate, + #endif + #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_RSA_FORMAT) + [RM_PSA_CRYPTO_RSA_KEY_WRAPPED] = + HW_SCE_HRK_RSA_2048KeyGenerate, + #endif +}; + static const hw_sce_rsa_private_decrypt_t g_rsa_private_decrypt_lookup[2] = { #if PSA_CRYPTO_IS_PLAINTEXT_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_RSA_FORMAT) @@ -234,14 +282,15 @@ int mbedtls_rsa_gen_key (mbedtls_rsa_context * ctx, uint32_t * p_rsa_public_modulus = NULL; uint32_t * p_additional_key_info = NULL; - fsp_err_t err = FSP_SUCCESS; - uint8_t rsa_public_exponent[4] = {0x00, 0x01, 0x00, 0x01}; + hw_sce_rsa_generatekey_t p_hw_sce_rsa_generatekey = NULL; + uint8_t rsa_public_exponent[4] = {0x00, 0x01, 0x00, 0x01}; - #if !PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_RSA_FORMAT) - FSP_PARAMETER_NOT_USED(private_key_size_bytes); + p_hw_sce_rsa_generatekey = g_rsa_keygen_lookup[(uint32_t) ctx->vendor_ctx]; + if (NULL == p_hw_sce_rsa_generatekey) + { + return MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; + } - ret = MBEDTLS_ERR_PLATFORM_FEATURE_UNSUPPORTED; - #endif if (ret == 0) { /* Obtain a 32-bit aligned block of memory. It will be used for all the following items in this order: @@ -265,13 +314,9 @@ int mbedtls_rsa_gen_key (mbedtls_rsa_context * ctx, p_additional_key_info = p_rsa_public_modulus + (public_key_size_bytes / 4); p_additional_key_info_8 = (uint8_t *) p_additional_key_info; - #if PSA_CRYPTO_IS_WRAPPED_SUPPORT_REQUIRED(PSA_CRYPTO_CFG_RSA_FORMAT) - err = HW_SCE_HRK_RSA_2048KeyGenerate(SCE_RSA_NUM_TRIES_20480, - p_rsa_private_exponent, - p_rsa_public_modulus, - p_additional_key_info); - #endif - if (FSP_SUCCESS != err) + if (FSP_SUCCESS != + p_hw_sce_rsa_generatekey(SCE_RSA_NUM_TRIES_20480, p_rsa_private_exponent, p_rsa_public_modulus, + p_additional_key_info)) { ret = MBEDTLS_ERR_RSA_KEY_GEN_FAILED; } diff --git a/ra/fsp/src/rm_threadx_port/tx_port.h b/ra/fsp/src/rm_threadx_port/tx_port.h index 51e2d41da..0ad9b9529 100644 --- a/ra/fsp/src/rm_threadx_port/tx_port.h +++ b/ra/fsp/src/rm_threadx_port/tx_port.h @@ -185,7 +185,7 @@ UINT _tx_thread_secure_stack_free(struct TX_THREAD_STRUCT *thread_ptr); #ifndef TX_MISRA_ENABLE #ifndef TX_TRACE_TIME_SOURCE -#if defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) +#if defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__) /* CM4 and CM33 do have DWT. */ #define TX_TRACE_TIME_SOURCE *((ULONG *) 0xE0001004) #else @@ -556,7 +556,7 @@ extern void _tx_thread_secure_stack_initialize(void); /* Cortex-M4 and Cortex-M33 have BASEPRI, so BASEPRI can be used to allow high priority interrupts * to preempt the scheduler. */ -#if (defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__)) && TX_PORT_MAX_IPL != 0 +#if (defined(__ARM_ARCH_7EM__) || defined(__ARM_ARCH_8M_MAIN__) || defined(__ARM_ARCH_8_1M_MAIN__)) && TX_PORT_MAX_IPL != 0 #define TX_PORT_USE_BASEPRI #endif diff --git a/ra/fsp/src/rm_threadx_port/tx_port_wait_thread_ready.c b/ra/fsp/src/rm_threadx_port/tx_port_wait_thread_ready.c index 6859b845d..7e2c87847 100644 --- a/ra/fsp/src/rm_threadx_port/tx_port_wait_thread_ready.c +++ b/ra/fsp/src/rm_threadx_port/tx_port_wait_thread_ready.c @@ -81,8 +81,8 @@ extern TX_THREAD * volatile _tx_thread_execute_ptr; /* These variables are global because this function is called from PendSV_Handler, which is a stackless * function. */ -static volatile uint16_t g_sbycr = 0U; -static volatile uint32_t g_prcr = 0U; +static volatile uint16_t g_saved_lpm_state = 0U; +static volatile uint32_t g_prcr = 0U; void * _tx_port_wait_thread_ready (void) { /* The following compile time assertions validate offsets used in the assembly code @@ -138,13 +138,31 @@ void * _tx_port_wait_thread_ready (void) } /* Save LPM Mode */ - g_sbycr = R_SYSTEM->SBYCR; +#if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + g_saved_lpm_state = R_SYSTEM->SBYCR; +#elif BSP_FEATURE_LPM_HAS_LPSCR + g_saved_lpm_state = R_SYSTEM->LPSCR; +#endif + +#if BSP_FEATURE_LPM_HAS_SBYCR_SSBY /* Check if the LPM peripheral is set to go to Software Standby mode with WFI instruction. * If yes, change the LPM peripheral to go to Sleep mode. Otherwise skip following procedures * to avoid the LPM register access which is high latency and impacts kernel performance. */ - if (g_sbycr & R_SYSTEM_SBYCR_SSBY_Msk) + if (g_saved_lpm_state & R_SYSTEM_SBYCR_SSBY_Msk) + { + /* Save register protect value */ + g_prcr = R_SYSTEM->PRCR; + + /* Unlock LPM peripheral registers */ + R_SYSTEM->PRCR = RM_THREADX_PORT_PRCR_UNLOCK_LPM_REGISTER_ACCESS; + + /* Clear to set to sleep low power mode (not standby or deep standby) */ + R_SYSTEM->SBYCR = g_saved_lpm_state & (uint16_t) ~R_SYSTEM_SBYCR_SSBY_Msk; + } +#elif BSP_FEATURE_LPM_HAS_LPSCR + if (R_SYSTEM_LPSCR_LPMD_Msk & g_saved_lpm_state) { /* Save register protect value */ g_prcr = R_SYSTEM->PRCR; @@ -153,8 +171,9 @@ void * _tx_port_wait_thread_ready (void) R_SYSTEM->PRCR = RM_THREADX_PORT_PRCR_UNLOCK_LPM_REGISTER_ACCESS; /* Clear to set to sleep low power mode (not standby or deep standby) */ - R_SYSTEM->SBYCR = g_sbycr & (uint16_t) ~R_SYSTEM_SBYCR_SSBY_Msk; + R_SYSTEM->LPSCR = 0U; } +#endif /** * DSB should be last instruction executed before WFI @@ -170,18 +189,30 @@ void * _tx_port_wait_thread_ready (void) /* Instruction Synchronization Barrier. */ __ISB(); +#if BSP_FEATURE_LPM_HAS_SBYCR_SSBY + /* Check if the LPM peripheral was supposed to go to Software Standby mode with WFI instruction. * If yes, restore the LPM peripheral setting. Otherwise skip following procedures to avoid the * LPM register access which is high latency and impacts kernel performance. */ - if (g_sbycr & R_SYSTEM_SBYCR_SSBY_Msk) + if (g_saved_lpm_state & R_SYSTEM_SBYCR_SSBY_Msk) + { + /* Restore LPM Mode */ + R_SYSTEM->SBYCR = g_saved_lpm_state; + + /* Restore register lock */ + R_SYSTEM->PRCR = (uint16_t) (RM_THREADX_PORT_PRCR_LOCK_LPM_REGISTER_ACCESS | g_prcr); + } +#elif BSP_FEATURE_LPM_HAS_LPSCR + if (R_SYSTEM_LPSCR_LPMD_Msk & g_saved_lpm_state) { /* Restore LPM Mode */ - R_SYSTEM->SBYCR = g_sbycr; + R_SYSTEM->LPSCR = (uint8_t) g_saved_lpm_state; /* Restore register lock */ R_SYSTEM->PRCR = (uint16_t) (RM_THREADX_PORT_PRCR_LOCK_LPM_REGISTER_ACCESS | g_prcr); } +#endif /* Re-enable interrupts. */ __enable_irq(); diff --git a/ra/fsp/src/rm_touch/rm_touch.c b/ra/fsp/src/rm_touch/rm_touch.c index bc4e8d01e..0adf93768 100644 --- a/ra/fsp/src/rm_touch/rm_touch.c +++ b/ra/fsp/src/rm_touch/rm_touch.c @@ -1682,10 +1682,20 @@ void touch_button_self_decode (touch_button_info_t * p_binfo, uint16_t value, ui { touch_button_off(p_binfo, button_id); } + + #if (0 == TOUCH_CFG_CHATTERING_SUPPRESSION_TYPE) else { /* Do nothing during hysteresis */ } + #else + else + { + /* touch count reset during hysteresis */ + (*(p_binfo->p_on_count + button_id)) = 0; + (*(p_binfo->p_off_count + button_id)) = 0; + } + #endif } #endif @@ -1733,10 +1743,20 @@ void touch_button_mutual_decode (touch_button_info_t * p_binfo, int16_t value, u { touch_button_off(p_binfo, button_id); } + + #if (0 == TOUCH_CFG_CHATTERING_SUPPRESSION_TYPE) else { /* Do nothing during hysteresis */ } + #else + else + { + /* touch count reset during hysteresis */ + (*(p_binfo->p_on_count + button_id)) = 0; + (*(p_binfo->p_off_count + button_id)) = 0; + } + #endif } /* End of function touch_button_decode() */ #endif @@ -3724,7 +3744,10 @@ void touch_tuning_qe_get_cfg (touch_instance_ctrl_t * const p_instance_ctrl) } else if (TOUCH_TUNING_MODE_MEASURE_PHASE2 == g_touch_tuning_mode) { - *(p_ctsu_instance_ctrl->p_tuning_count + i) = 0; + *(p_ctsu_instance_ctrl->p_element_complete_flag + i) = 0; + #if (BSP_FEATURE_CTSU_VERSION == 2) + *(p_ctsu_instance_ctrl->p_frequency_complete_flag + i) = 0; + #endif #if (BSP_FEATURE_CTSU_VERSION == 1) *(p_ctsu_instance_ctrl->p_tuning_diff + i) = 0; #endif @@ -4105,9 +4128,14 @@ void touch_tuning_open (touch_instance_ctrl_t * const p_instance_ctrl) ((p_ctsu_instance_ctrl->mutual_elem_index - p_ctsu_instance_ctrl->num_elements))); } #endif - p_ctsu_instance_ctrl->p_tuning_count = - (p_ctsu_instance_ctrl->p_tuning_count - + p_ctsu_instance_ctrl->p_element_complete_flag = + (p_ctsu_instance_ctrl->p_element_complete_flag - + (p_ctsu_instance_ctrl->ctsu_elem_index - p_ctsu_instance_ctrl->num_elements)); + #if (BSP_FEATURE_CTSU_VERSION == 2) + p_ctsu_instance_ctrl->p_frequency_complete_flag = + (p_ctsu_instance_ctrl->p_frequency_complete_flag - (p_ctsu_instance_ctrl->ctsu_elem_index - p_ctsu_instance_ctrl->num_elements)); + #endif p_ctsu_instance_ctrl->p_tuning_diff = (p_ctsu_instance_ctrl->p_tuning_diff - (p_ctsu_instance_ctrl->ctsu_elem_index - p_ctsu_instance_ctrl->num_elements)); @@ -4165,11 +4193,6 @@ void touch_tuning_dataget (touch_instance_ctrl_t * const p_instance_ctrl) { if (p_ctsu_instance_ctrl->tuning == CTSU_TUNING_INCOMPLETE) { - for (i = 0; i < p_ctsu_instance_ctrl->num_elements; i++) - { - *(p_ctsu_instance_ctrl->p_tuning_count + i) = 0; - } - g_touch_tuning_state = TOUCH_TUNING_STATE_SCAN; } } diff --git a/ra/fsp/src/rm_usbx_port/rm_usbx_port.c b/ra/fsp/src/rm_usbx_port/rm_usbx_port.c index 4a467c3a2..a3fce9b56 100644 --- a/ra/fsp/src/rm_usbx_port/rm_usbx_port.c +++ b/ra/fsp/src/rm_usbx_port/rm_usbx_port.c @@ -75,6 +75,11 @@ #define USB_MAX_CONNECT_DEVICE_NUM 2 #endif /* defined(USB_CFG_HPRN_USE) */ + #if defined(USB_CFG_HUVC_USE) + #include "ux_host_class_video.h" + #define USB_MAX_CONNECT_DEVICE_NUM 1 + #endif /* defined(USB_CFG_HPRN_USE) */ + #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) #include "ux_host_stack.h" #endif /* #if ((USB_CFG_MODE & USB_CFG_HOST) == USB_CFG_HOST) */ @@ -85,6 +90,8 @@ #define VALUE_1000UL (1000UL) #if defined(USB_CFG_HHID_USE) #define UX_FSP_HC_AVAILABLE_BANDWIDTH (2322UL) + #elif defined(USB_CFG_HUVC_USE) + #define UX_FSP_HC_AVAILABLE_BANDWIDTH (6000UL) #else #define UX_FSP_HC_AVAILABLE_BANDWIDTH (2304UL) #endif /* defined(USB_CFG_HHID_USE) */ @@ -1478,6 +1485,10 @@ void usb_host_usbx_registration (usb_utr_t * p_utr) driver.ifclass = (uint16_t) USB_IFCLS_PRN; /* Interface class : Printer */ #endif /* defined(USB_CFG_HPRN_USE) */ + #if defined(USB_CFG_HUVC_USE) + driver.ifclass = (uint16_t) USB_IFCLS_VID; /* Interface class : Video */ + #endif /* defined(USB_CFG_HUVC_USE) */ + #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE driver.p_tpl = (uint16_t *) USB_CFG_TPL_TABLE; #else /* #if USB_CFG_COMPLIANCE == USB_CFG_ENABLE */ @@ -1530,7 +1541,8 @@ void usb_host_usbx_registration (usb_utr_t * p_utr) ******************************************************************************/ void usb_host_usbx_class_check (usb_utr_t * p_utr, uint16_t ** table) { - #if defined(USB_CFG_HCDC_USE) || defined(USB_CFG_HHID_USE) || defined(USB_CFG_HMSC_USE) || defined(USB_CFG_HPRN_USE) + #if defined(USB_CFG_HCDC_USE) || defined(USB_CFG_HHID_USE) || defined(USB_CFG_HMSC_USE) || \ + defined(USB_CFG_HPRN_USE) || defined(USB_CFG_HUVC_USE) uint16_t speed; uint16_t length; uint16_t offset; @@ -1578,6 +1590,10 @@ void usb_host_usbx_class_check (usb_utr_t * p_utr, uint16_t ** table) usb_class = USB_CLASS_INTERNAL_HPRN; #endif + #if defined(USB_CFG_HUVC_USE) + usb_class = USB_CLASS_INTERNAL_HUVC; + #endif + offset = 0; while (offset < length) { @@ -1587,6 +1603,13 @@ void usb_host_usbx_class_check (usb_utr_t * p_utr, uint16_t ** table) { usb_class = USB_HUB; } + else + { + if (USB_IFCLS_VID == *(p_config + offset + 5)) + { + break; + } + } } if (USB_DT_ENDPOINT == *(p_config + offset + USB_EP_B_DESCRIPTORTYPE)) @@ -1779,7 +1802,12 @@ static void usb_host_usbx_set_configuration_cb (usb_utr_t * p_utr, uint16_t data g_usb_hstd_mgr_mode[p_utr->ip] = USB_CONFIGURED; tx_semaphore_put(&g_usb_host_usbx_sem[p_utr->ip][pipe]); + #if defined(USB_CFG_HUVC_USE) + + /* Pipe registration will be done at completion of SET_INTERFACE */ + #else usb_host_usbx_set_pipe_registration(p_utr, g_usb_hstd_device_addr[p_utr->ip]); /* Host Pipe registration */ + #endif usb_hstd_mgr_snd_mbx(p_utr, (uint16_t) USB_MSG_MGR_SUBMITRESULT, p_utr->keyword, p_utr->status); } /* End of function usb_pstd_transfer_complete_cb() */ @@ -1801,12 +1829,25 @@ static void usb_host_usbx_class_request_cb (usb_utr_t * p_utr, uint16_t data1, u uint32_t i; + #if defined(USB_CFG_HUVC_USE) + uint32_t alternate_number; + uint32_t interface_number; + uint16_t is_interface_discoverd = 0; + uint16_t length; + uint16_t offset; + uint16_t usb_class; + uint8_t * p_config; + uint16_t dev_addr; + uint8_t pipe_no; + usb_pipe_table_reg_t ep_tbl; + #endif /* defined(USB_CFG_HUVC_USE) */ + pipe = (uint8_t) p_utr->keyword; #if (defined(USB_CFG_HHID_USE) | defined(USB_CFG_OTG_USE) | defined(USB_CFG_HPRN_USE) | defined(USB_CFG_HCDC_USE) | \ - defined(USB_CFG_HMSC_USE)) + defined(USB_CFG_HMSC_USE) | defined(USB_CFG_HUVC_USE)) *g_p_usb_host_actural_length[p_utr->ip][0] = p_utr->read_req_len - p_utr->tranlen; - #endif /* #if defined(USB_CFG_HHID_USE) | defined(USB_CFG_OTG_USE) | defined(USB_CFG_HPRN_USE) | defined(USB_CFG_HCDC_USE) */ + #endif /* #if defined(USB_CFG_HHID_USE) | defined(USB_CFG_OTG_USE) | defined(USB_CFG_HPRN_USE) | defined(USB_CFG_HCDC_USE) | defined(USB_CFG_HUVC_USE) */ /* Completion of Hub Port Reset (SET_FEATURE : Set Port Feature) */ if (p_utr->p_setup[0] == (USB_SET_FEATURE | USB_HOST_TO_DEV | USB_CLASS | USB_OTHER)) @@ -2014,8 +2055,71 @@ static void usb_host_usbx_class_request_cb (usb_utr_t * p_utr, uint16_t data1, u g_usbx_hub_passed_count++; } + #if defined(USB_CFG_HUVC_USE) + + /* Completion of SET_INTERFACE */ + if (p_utr->p_setup[0] == (USB_SET_INTERFACE | USB_HOST_TO_DEV | USB_STANDARD | USB_INTERFACE)) + { + alternate_number = p_utr->p_setup[1]; /* Requested alternate number at SET_INTERFACE */ + interface_number = p_utr->p_setup[2]; /* Requested interface number at SET_INTERFACE */ + + if ((0 != alternate_number) && (0 != interface_number)) + { + dev_addr = p_utr->p_setup[4]; + usb_class = USB_CLASS_INTERNAL_HUVC; + + p_config = (uint8_t *) g_usb_hstd_config_descriptor[p_utr->ip]; + length = (uint16_t) (*(p_config + 3) << 8); + length = (uint16_t) (length + *(p_config + 2)); + offset = 0; + + while (offset < length) + { + if (USB_DT_INTERFACE == *(p_config + offset + 1)) + { + if (interface_number == *(p_config + offset + 2)) + { + if ((UX_HOST_CLASS_VIDEO_SUBCLASS_STREAMING == *(p_config + offset + 6)) && + (alternate_number == *(p_config + offset + 3))) + { + is_interface_discoverd = 1; + } + } + } + + if (1 == is_interface_discoverd) + { + if (USB_DT_ENDPOINT == *(p_config + offset + USB_EP_B_DESCRIPTORTYPE)) + { + if (USB_EP_IN == (*(p_config + offset + USB_EP_B_ENDPOINTADDRESS) & USB_EP_DIRMASK)) + { + pipe_no = + usb_hstd_make_pipe_reg_info(p_utr->ip, + dev_addr, + usb_class, + 0, + (p_config + offset), + &ep_tbl); + if (USB_NULL != pipe_no) + { + usb_hstd_set_pipe_info(p_utr->ip, pipe_no, &ep_tbl); + } + + break; + } + } + } + + offset = (uint16_t) (offset + (*(p_config + offset))); + } + + usb_host_usbx_set_pipe_registration(p_utr, g_usb_hstd_device_addr[p_utr->ip]); /* Host Pipe registration */ + } + } + #endif /* defined(USB_CFG_HUVC_USE) */ + tx_semaphore_put(&g_usb_host_usbx_sem[p_utr->ip][pipe]); -} /* End of function usb_pstd_transfer_complete_cb() */ +} /* End of function usb_pstd_transfer_complete_cb() */ /****************************************************************************** * Function Name : usb_hstd_transfer_complete_cb @@ -2184,6 +2288,23 @@ static void usb_host_usbx_transfer_complete_cb (usb_utr_t * p_utr, uint16_t data } #endif /* defined(USB_CFG_HCDC_USE) */ + #if defined(USB_CFG_HUVC_USE) + if ((USB_DATA_OK == g_p_usb_hstd_pipe[p_utr->ip][pipe]->status) || + (USB_DATA_SHT == g_p_usb_hstd_pipe[p_utr->ip][pipe]->status)) + { + transfer_request->ux_transfer_request_completion_code = UX_SUCCESS; + } + else + { + transfer_request->ux_transfer_request_completion_code = UX_TRANSFER_ERROR; + } + + if (UX_NULL != transfer_request->ux_transfer_request_completion_function) + { + transfer_request->ux_transfer_request_completion_function(transfer_request); + } + #endif /* defined(USB_CFG_HUVC_USE) */ + #if defined(USB_CFG_OTG_USE) status = tx_semaphore_info_get(&transfer_request->ux_transfer_request_semaphore, &p_sem_name, @@ -2521,6 +2642,54 @@ static UINT usb_host_usbx_to_basic (UX_HCD * hcd, UINT function, VOID * paramete } case (uint32_t) UX_FSP_ISOCHRONOUS_ENDPOINT: + { + #if defined(USB_CFG_HUVC_USE) + usb_class = USB_CLASS_INTERNAL_HUVC; + pipe_number = usb_hstd_get_pipe_no(module_number, + (uint16_t) endpoint->ux_endpoint_device->ux_device_address, + usb_class, + (endpoint->ux_endpoint_descriptor.bmAttributes) & (uint32_t) UX_FSP_MASK_ENDPOINT_TYPE, + (uint8_t) ((((endpoint->ux_endpoint_descriptor.bEndpointAddress & + USB_ENDPOINT_DIRECTION) >> 7) ? + USB_PIPE_DIR_IN : USB_PIPE_DIR_OUT))); + + size = transfer_request->ux_transfer_request_requested_length; + + g_usb_host_usbx_req_nml_msg[module_number][pipe_number].read_req_len = size; /* Request Data Size */ + g_usb_host_usbx_req_nml_msg[module_number][pipe_number].keyword = pipe_number; /* Pipe Number */ + g_usb_host_usbx_req_nml_msg[module_number][pipe_number].p_tranadr = + transfer_request->ux_transfer_request_data_pointer; /* Data address */ + + g_usb_host_usbx_req_nml_msg[module_number][pipe_number].tranlen = size; /* Request Data Size */ + g_usb_host_usbx_req_nml_msg[module_number][pipe_number].complete = + usb_host_usbx_transfer_complete_cb; + + /* Callback function */ + g_usb_host_usbx_req_nml_msg[module_number][pipe_number].segment = USB_TRAN_END; + g_usb_host_usbx_req_nml_msg[module_number][pipe_number].ip = module_number; + g_usb_host_usbx_req_nml_msg[module_number][pipe_number].ipp = usb_hstd_get_usb_ip_adr( + module_number); + #if (USB_CFG_DMA == USB_CFG_ENABLE) + g_usb_host_usbx_req_nml_msg[module_number][pipe_number].p_transfer_tx = g_p_usbx_transfer_tx; + g_usb_host_usbx_req_nml_msg[module_number][pipe_number].p_transfer_rx = g_p_usbx_transfer_rx; + #endif /* #if (USB_CFG_DMA == USB_CFG_ENABLE) */ + g_p_usb_host_actural_length[module_number][pipe_number] = + (uint32_t *) &(transfer_request->ux_transfer_request_actual_length); + + g_p_usb_host_usbx_transfer_request[module_number][pipe_number] = transfer_request; + err = usb_hstd_transfer_start(&g_usb_host_usbx_req_nml_msg[module_number][pipe_number]); + + if (USB_OK == err) + { + status = (uint32_t) UX_SUCCESS; + } + else + { + status = (uint32_t) UX_TRANSFER_ERROR; + } + #endif /* defined(USB_CFG_HUVC_USE) */ + } + default: { break; @@ -2532,6 +2701,26 @@ static UINT usb_host_usbx_to_basic (UX_HCD * hcd, UINT function, VOID * paramete case (uint32_t) UX_HCD_TRANSFER_ABORT: { + #if defined(USB_CFG_HUVC_USE) + usb_utr_t utr; + + transfer_request = (UX_TRANSFER *) parameter; + endpoint = (UX_ENDPOINT *) transfer_request->ux_transfer_request_endpoint; + + usb_class = USB_CLASS_INTERNAL_HUVC; + pipe_number = usb_hstd_get_pipe_no(module_number, + (uint16_t) endpoint->ux_endpoint_device->ux_device_address, + usb_class, + (endpoint->ux_endpoint_descriptor.bmAttributes) & (uint32_t) UX_FSP_MASK_ENDPOINT_TYPE, + (uint8_t) ((((endpoint->ux_endpoint_descriptor.bEndpointAddress & + USB_ENDPOINT_DIRECTION) >> 7) ? + USB_PIPE_DIR_IN : USB_PIPE_DIR_OUT))); + + utr.ip = module_number; + utr.ipp = usb_hstd_get_usb_ip_adr(module_number); + + usb_hstd_hcd_snd_mbx(&utr, USB_MSG_HCD_TRANSEND1, pipe_number, (uint16_t *) 0, 0); + #endif break; } diff --git a/ra/fsp/src/rm_wifi_onchip_da16200/rm_wifi_api_da16200.c b/ra/fsp/src/rm_wifi_onchip_da16200/rm_wifi_api_da16200.c new file mode 100644 index 000000000..573d051c9 --- /dev/null +++ b/ra/fsp/src/rm_wifi_onchip_da16200/rm_wifi_api_da16200.c @@ -0,0 +1,411 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include +#include + +#include "rm_wifi_onchip_da16200.h" + +#if (BSP_CFG_RTOS == 2) + +/* FreeRTOS includes. */ + #include "FreeRTOS.h" + +/* Socket and WiFi interface includes. */ + #include "rm_wifi_config.h" + +/* WiFi configuration includes. */ + #include "rm_wifi_api.h" + +/** + * Turns on Wi-Fi. + * + * This function turns on Wi-Fi module,initializes the drivers and must be called + * before calling any other Wi-Fi API + * + * @return eWiFiSuccess if Wi-Fi module was successfully turned on, failure code otherwise. + */ +WIFIReturnCode_t WIFI_On (void) +{ + WIFIReturnCode_t xRetVal = eWiFiFailure; + fsp_err_t ret = FSP_ERR_WIFI_FAILED; + + ret = rm_wifi_onchip_da16200_open(&g_wifi_onchip_da16200_cfg); + if (!ret) + { + xRetVal = eWiFiSuccess; + } + + return xRetVal; +} + +/** + * Turns off Wi-Fi. + * + * This function turns off the Wi-Fi module. The Wi-Fi peripheral should be put in a + * low power or off state in this routine. + * + * @return eWiFiSuccess if Wi-Fi module was successfully turned off, failure code otherwise. + */ +WIFIReturnCode_t WIFI_Off (void) +{ + WIFIReturnCode_t xRetVal = eWiFiFailure; + int32_t ret = FSP_ERR_WIFI_FAILED; + + ret = (int32_t) rm_wifi_onchip_da16200_close(); + if (!ret) + { + xRetVal = eWiFiSuccess; + } + + return xRetVal; +} + +/** + * Connects to the Wi-Fi Access Point (AP) specified in the input. + * + * The Wi-Fi should stay connected when the same Access Point it is currently connected to + * is specified. Otherwise, the Wi-Fi should disconnect and connect to the new Access Point + * specified. If the new Access Point specifed has invalid parameters, then the Wi-Fi should be + * disconnected. + * + * @param[in] pxNetworkParams Configuration to join AP. + * + * @return eWiFiSuccess if connection is successful, failure code otherwise. + * + * @code + * WIFINetworkParams_t xNetworkParams; + * WIFIReturnCode_t xWifiStatus; + * xNetworkParams.pcSSID = "SSID String"; + * xNetworkParams.ucSSIDLength = SSIDLen; + * xNetworkParams.pcPassword = "Password String"; + * xNetworkParams.ucPasswordLength = PassLength; + * xNetworkParams.xSecurity = eWiFiSecurityWPA2; + * xWifiStatus = WIFI_ConnectAP( &( xNetworkParams ) ); + * if(xWifiStatus == eWiFiSuccess) + * { + * //Connected to AP. + * } + * @endcode + * + * @see WIFINetworkParams_t + */ + +WIFIReturnCode_t WIFI_ConnectAP (const WIFINetworkParams_t * const pxNetworkParams) +{ + WIFIReturnCode_t xRetVal = eWiFiFailure; + int32_t ret = -1; + + if ((NULL == pxNetworkParams) || (0 == pxNetworkParams->ucSSIDLength) || + (0 == pxNetworkParams->xPassword.xWPA.ucLength)) + { + return eWiFiFailure; + } + + if (pxNetworkParams->xSecurity >= eWiFiSecurityNotSupported) + { + return eWiFiFailure; + } + + if ((0 == pxNetworkParams->xPassword.xWPA.ucLength) && + (eWiFiSecurityOpen != pxNetworkParams->xSecurity)) + { + return eWiFiFailure; + } + + if (pxNetworkParams->ucSSIDLength > wificonfigMAX_SSID_LEN) + { + return eWiFiFailure; + } + + if (pxNetworkParams->xPassword.xWPA.ucLength > wificonfigMAX_PASSPHRASE_LEN) + { + return eWiFiFailure; + } + + ret = (int32_t) rm_wifi_onchip_da16200_connect((char *) pxNetworkParams->ucSSID, + pxNetworkParams->xSecurity, + pxNetworkParams->xPassword.xWPA.cPassphrase, + WIFI_ONCHIP_DA16200_TKIP_AES_ENC_TYPE); + if (!ret) + { + xRetVal = eWiFiSuccess; + } + + return xRetVal; +} + +/** + * Disconnects from the currently connected Access Point. + * + * @return eWiFiSuccess if disconnection was successful or if the device is already + * disconnected, failure code otherwise. + */ +WIFIReturnCode_t WIFI_Disconnect (void) { + WIFIReturnCode_t xRetVal = eWiFiFailure; + int32_t ret = -1; + + ret = (int32_t) rm_wifi_onchip_da16200_disconnect(); + if (!ret) + { + xRetVal = eWiFiSuccess; + } + + return xRetVal; +} + +/** + * Resets the Wi-Fi Module. + * + * @return eWiFiSuccess if Wi-Fi module was successfully reset, failure code otherwise. + */ +WIFIReturnCode_t WIFI_Reset (void) +{ + WIFIReturnCode_t ret; + + ret = WIFI_Off(); + if (ret) + { + return eWiFiFailure; + } + + ret = WIFI_On(); + if (ret) + { + return eWiFiFailure; + } + + return eWiFiSuccess; +} + +/** + * Perform a Wi-Fi network Scan. + * + * @param[in] pxBuffer - Buffer for scan results. + * @param[in] ucNumNetworks - Number of networks to retrieve in scan result. + * + * @return eWiFiSuccess if the Wi-Fi network scan was successful, failure code otherwise. + * + * @note The input buffer will have the results of the scan. + * + * @code + * const uint8_t ucNumNetworks = 10; //Get 10 scan results + * WIFIScanResult_t xScanResults[ ucNumNetworks ]; + * WIFI_Scan( xScanResults, ucNumNetworks ); + * @endcode + */ +WIFIReturnCode_t WIFI_Scan (WIFIScanResult_t * pxBuffer, uint8_t ucNumNetworks) +{ + fsp_err_t err = FSP_SUCCESS; + + err = rm_wifi_onchip_da16200_scan(pxBuffer, ucNumNetworks); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, eWiFiFailure); + + return eWiFiSuccess; +} + +WIFIReturnCode_t WIFI_SetMode (WIFIDeviceMode_t xDeviceMode) +{ + FSP_PARAMETER_NOT_USED(xDeviceMode); + + return eWiFiNotSupported; +} + +WIFIReturnCode_t WIFI_GetMode (WIFIDeviceMode_t * pxDeviceMode) +{ + FSP_PARAMETER_NOT_USED(pxDeviceMode); + + return eWiFiNotSupported; +} + +/** + * Ping an IP address in the network. + * + * @param[in] pucIPAddr IP Address array to ping. + * @param[in] usCount Number of times to ping + * @param[in] ulIntervalMS Interval in milliseconds for ping operation + * + * @return eWiFiSuccess if ping was successful, other failure code otherwise. + */ +WIFIReturnCode_t WIFI_Ping (uint8_t * pucIPAddr, uint16_t usCount, uint32_t ulIntervalMS) +{ + int32_t ret = -1; + + ret = (int32_t) rm_wifi_onchip_da16200_ping(pucIPAddr, usCount, ulIntervalMS); + FSP_ERROR_RETURN(FSP_SUCCESS == ret, eWiFiFailure); + + return eWiFiSuccess; +} + +/** + * @brief Get IP configuration (IP address, NetworkMask, Gateway and + * DNS server addresses). + * + * @param[out] pxIPInfo - Current IP configuration. + * + * @return eWiFiSuccess if successful and IP Address buffer has the interface's IP address, + * failure code otherwise. + * + * **Example** + * @code + * WIFIIPConfiguration_t xIPInfo; + * WIFI_GetIPInfo( &xIPInfo ); + * @endcode + */ +WIFIReturnCode_t WIFI_GetIPInfo (WIFIIPConfiguration_t * pxIPInfo) { + int32_t ret = -1; + + ret = (int32_t) rm_wifi_onchip_da16200_ipaddr_get(pxIPInfo->xIPAddress.ulAddress); + FSP_ERROR_RETURN(FSP_SUCCESS == ret, eWiFiFailure); + + return eWiFiSuccess; +} + +/** + * Retrieves the Wi-Fi interface's MAC address. + * + * @param[out] pucMac MAC Address buffer sized 6 bytes. + * + * @code + * uint8_t ucMacAddressVal[ wificonfigMAX_BSSID_LEN ]; + * WIFI_GetMAC( &ucMacAddressVal[0] ); + * @endcode + * + * @return eWiFiSuccess if the MAC address was successfully retrieved, failure code + * otherwise. The returned MAC address must be 6 consecutive bytes with no delimitters. + */ +WIFIReturnCode_t WIFI_GetMAC (uint8_t * pucMac) { + int32_t ret = -1; + + ret = (int32_t) rm_wifi_onchip_da16200_mac_addr_get(pucMac); + FSP_ERROR_RETURN(FSP_SUCCESS == ret, eWiFiFailure); + + return eWiFiSuccess; +} + +/** + * Retrieves the host IP address from a host name using DNS. + * + * @param[in] pcHost - Host (node) name. + * @param[in] pucIPAddr - IP Address buffer. + * + * @return eWiFiSuccess if the host IP address was successfully retrieved, failure code + * otherwise. + * + * @code + * uint8_t ucIPAddr[ 4 ]; + * WIFI_GetHostIP( "amazon.com", &ucIPAddr[0] ); + * @endcode + */ +WIFIReturnCode_t WIFI_GetHostIP (char * pcHost, uint8_t * pucIPAddr) { + int32_t ret = -1; + + if ((NULL == pcHost) || (NULL == pucIPAddr)) + { + return eWiFiFailure; + } + + ret = (int32_t) rm_wifi_onchip_da16200_dns_query(pcHost, pucIPAddr); + FSP_ERROR_RETURN(FSP_SUCCESS == ret, eWiFiFailure); + + return eWiFiSuccess; +} + +/** + * + * @brief Check if the Wi-Fi is connected and the AP configuration matches the query. + * + * param[in] pxNetworkParams - Network parameters to query, if NULL then just check the + * Wi-Fi link status. + */ +BaseType_t WIFI_IsConnected (const WIFINetworkParams_t * pxNetworkParams) { + BaseType_t xIsConnected = pdFALSE; + fsp_err_t status = FSP_SUCCESS; + + FSP_PARAMETER_NOT_USED(pxNetworkParams); + + rm_wifi_onchip_da16200_connected(&status); + if (0 == status) + { + xIsConnected = pdTRUE; + } + + return xIsConnected; +} + +WIFIReturnCode_t WIFI_SetPMMode (WIFIPMMode_t xPMModeType, const void * pvOptionValue) { + /* FIX ME. */ + FSP_PARAMETER_NOT_USED(xPMModeType); + FSP_PARAMETER_NOT_USED(pvOptionValue); + + return eWiFiNotSupported; +} + +WIFIReturnCode_t WIFI_GetPMMode (WIFIPMMode_t * pxPMModeType, void * pvOptionValue) { + /* FIX ME. */ + FSP_PARAMETER_NOT_USED(pxPMModeType); + FSP_PARAMETER_NOT_USED(pvOptionValue); + + return eWiFiNotSupported; +} + +WIFIReturnCode_t WIFI_NetworkAdd (const WIFINetworkProfile_t * const pxNetworkProfile, uint16_t * pusIndex) +{ + FSP_PARAMETER_NOT_USED(pxNetworkProfile); + FSP_PARAMETER_NOT_USED(pusIndex); + + return eWiFiNotSupported; +} + +WIFIReturnCode_t WIFI_NetworkGet (WIFINetworkProfile_t * pxNetworkProfile, uint16_t usIndex) +{ + FSP_PARAMETER_NOT_USED(pxNetworkProfile); + FSP_PARAMETER_NOT_USED(usIndex); + + return eWiFiNotSupported; +} + +WIFIReturnCode_t WIFI_NetworkDelete (uint16_t usIndex) +{ + FSP_PARAMETER_NOT_USED(usIndex); + + return eWiFiNotSupported; +} + +WIFIReturnCode_t WIFI_StartAP (void) { + return eWiFiNotSupported; +} + +WIFIReturnCode_t WIFI_StopAP (void) { + return eWiFiNotSupported; +} + +WIFIReturnCode_t WIFI_ConfigureAP (const WIFINetworkParams_t * const pxNetworkParams) { + /* FIX ME. */ + FSP_PARAMETER_NOT_USED(pxNetworkParams); + + return eWiFiNotSupported; +} + +#endif diff --git a/ra/fsp/src/rm_wifi_onchip_da16200/rm_wifi_onchip_da16200.c b/ra/fsp/src/rm_wifi_onchip_da16200/rm_wifi_onchip_da16200.c new file mode 100644 index 000000000..c81036906 --- /dev/null +++ b/ra/fsp/src/rm_wifi_onchip_da16200/rm_wifi_onchip_da16200.c @@ -0,0 +1,3076 @@ +/*********************************************************************************************************************** + * Copyright [2020-2022] Renesas Electronics Corporation and/or its affiliates. All Rights Reserved. + * + * This software and documentation are supplied by Renesas Electronics America Inc. and may only be used with products + * of Renesas Electronics Corp. and its affiliates ("Renesas"). No other uses are authorized. Renesas products are + * sold pursuant to Renesas terms and conditions of sale. Purchasers are solely responsible for the selection and use + * of Renesas products and Renesas assumes no liability. No license, express or implied, to any intellectual property + * right is granted by Renesas. This software is protected under all applicable laws, including copyright laws. Renesas + * reserves the right to change or discontinue this software and/or this documentation. THE SOFTWARE AND DOCUMENTATION + * IS DELIVERED TO YOU "AS IS," AND RENESAS MAKES NO REPRESENTATIONS OR WARRANTIES, AND TO THE FULLEST EXTENT + * PERMISSIBLE UNDER APPLICABLE LAW, DISCLAIMS ALL WARRANTIES, WHETHER EXPLICITLY OR IMPLICITLY, INCLUDING WARRANTIES + * OF MERCHANTABILITY, FITNESS FOR A PARTICULAR PURPOSE, AND NONINFRINGEMENT, WITH RESPECT TO THE SOFTWARE OR + * DOCUMENTATION. RENESAS SHALL HAVE NO LIABILITY ARISING OUT OF ANY SECURITY VULNERABILITY OR BREACH. TO THE MAXIMUM + * EXTENT PERMITTED BY LAW, IN NO EVENT WILL RENESAS BE LIABLE TO YOU IN CONNECTION WITH THE SOFTWARE OR DOCUMENTATION + * (OR ANY PERSON OR ENTITY CLAIMING RIGHTS DERIVED FROM YOU) FOR ANY LOSS, DAMAGES, OR CLAIMS WHATSOEVER, INCLUDING, + * WITHOUT LIMITATION, ANY DIRECT, CONSEQUENTIAL, SPECIAL, INDIRECT, PUNITIVE, OR INCIDENTAL DAMAGES; ANY LOST PROFITS, + * OTHER ECONOMIC DAMAGE, PROPERTY DAMAGE, OR PERSONAL INJURY; AND EVEN IF RENESAS HAS BEEN ADVISED OF THE POSSIBILITY + * OF SUCH LOSS, DAMAGES, CLAIMS OR COSTS. + **********************************************************************************************************************/ + +/*********************************************************************************************************************** + * Includes + **********************************************************************************************************************/ +#include "rm_wifi_onchip_da16200.h" + +#if (BSP_FEATURE_SCI_VERSION == 2U) + #include "r_sci_b_uart.h" +typedef sci_b_uart_instance_ctrl_t rm_wifi_onchip_da16200_uart_instance_ctrl_t; +typedef sci_b_uart_extended_cfg_t rm_wifi_onchip_da16200_uart_extended_cfg_t; +typedef sci_b_baud_setting_t rm_wifi_onchip_da16200_baud_setting_t; + #define RM_WIFI_ONCHIP_DA16200_SCI_UART_FLOW_CONTROL_RTS SCI_B_UART_FLOW_CONTROL_RTS + #define RM_WIFI_ONCHIP_DA16200_SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS SCI_B_UART_FLOW_CONTROL_HARDWARE_CTSRTS +static fsp_err_t (* p_sci_uart_baud_calculate)(uint32_t, bool, uint32_t, + struct st_sci_b_baud_setting_t * const) = &R_SCI_B_UART_BaudCalculate; +#else + #include "r_sci_uart.h" +typedef sci_uart_instance_ctrl_t rm_wifi_onchip_da16200_uart_instance_ctrl_t; +typedef sci_uart_extended_cfg_t rm_wifi_onchip_da16200_uart_extended_cfg_t; +typedef baud_setting_t rm_wifi_onchip_da16200_baud_setting_t; + #define RM_WIFI_ONCHIP_DA16200_SCI_UART_FLOW_CONTROL_RTS SCI_UART_FLOW_CONTROL_RTS + #define RM_WIFI_ONCHIP_DA16200_SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS SCI_UART_FLOW_CONTROL_HARDWARE_CTSRTS +static fsp_err_t (* p_sci_uart_baud_calculate)(uint32_t, bool, uint32_t, + baud_setting_t * const) = &R_SCI_UART_BaudCalculate; +#endif + +/*! \cond PRIVATE */ + +/*********************************************************************************************************************** + * Defines + **********************************************************************************************************************/ +#define WIFI_ONCHIP_DA16200_TEMP_BUFFER_SIZE (256) + +/* Text full versions of AT command returns */ +#define WIFI_ONCHIP_DA16200_RETURN_TEXT_OK "OK" +#define WIFI_ONCHIP_DA16200_RETURN_CONN_TEXT "+WFJAP:1" + +/* DA16200 UART port defines */ +#define WIFI_ONCHIP_DA16200_UART_INITIAL_PORT (0) +#define WIFI_ONCHIP_DA16200_UART_SECOND_PORT (1) + +/* Initial DA16200 Wifi module UART settings */ +#define WIFI_ONCHIP_DA16200_DEFAULT_BAUDRATE (115200) +#define WIFI_ONCHIP_DA16200_DEFAULT_MODULATION false +#define WIFI_ONCHIP_DA16200_DEFAULT_ERROR (9000) + +/* Pin or port invalid definition */ +#define WIFI_ONCHIP_DA16200_BSP_PIN_PORT_INVALID (UINT16_MAX) + +#define WIFI_ONCHIP_DA16200_TEMP_BUFF_SIZE (30) + +/* Mutex give/take defines */ +#define WIFI_ONCHIP_DA16200_MUTEX_TX (1 << 0) +#define WIFI_ONCHIP_DA16200_MUTEX_RX (1 << 1) + +/* Predefined timeout values */ +#define WIFI_ONCHIP_DA16200_TIMEOUT_1MS (1) +#define WIFI_ONCHIP_DA16200_TIMEOUT_3MS (3) +#define WIFI_ONCHIP_DA16200_TIMEOUT_5MS (5) +#define WIFI_ONCHIP_DA16200_TIMEOUT_10MS (10) +#define WIFI_ONCHIP_DA16200_TIMEOUT_20MS (20) +#define WIFI_ONCHIP_DA16200_TIMEOUT_30MS (30) +#define WIFI_ONCHIP_DA16200_TIMEOUT_100MS (100) +#define WIFI_ONCHIP_DA16200_TIMEOUT_200MS (200) +#define WIFI_ONCHIP_DA16200_TIMEOUT_300MS (300) +#define WIFI_ONCHIP_DA16200_TIMEOUT_400MS (400) +#define WIFI_ONCHIP_DA16200_TIMEOUT_500MS (500) +#define WIFI_ONCHIP_DA16200_TIMEOUT_1SEC (1000) +#define WIFI_ONCHIP_DA16200_TIMEOUT_2SEC (2000) +#define WIFI_ONCHIP_DA16200_TIMEOUT_3SEC (3000) +#define WIFI_ONCHIP_DA16200_TIMEOUT_4SEC (4000) +#define WIFI_ONCHIP_DA16200_TIMEOUT_5SEC (5000) +#define WIFI_ONCHIP_DA16200_TIMEOUT_8SEC (8000) +#define WIFI_ONCHIP_DA16200_TIMEOUT_15SEC (15000) +#define WIFI_ONCHIP_DA16200_TIMEOUT_20SEC (20000) + +/* DA16200 AT command retry delay in milliseconds */ +#define WIFI_ONCHIP_DA16200_DELAY_20MS (20) +#define WIFI_ONCHIP_DA16200_DELAY_50MS (50) +#define WIFI_ONCHIP_DA16200_DELAY_100MS (100) +#define WIFI_ONCHIP_DA16200_DELAY_200MS (200) +#define WIFI_ONCHIP_DA16200_DELAY_300MS (300) +#define WIFI_ONCHIP_DA16200_DELAY_500MS (500) +#define WIFI_ONCHIP_DA16200_DELAY_1000MS (1000) +#define WIFI_ONCHIP_DA16200_DELAY_2000MS (2000) +#define WIFI_ONCHIP_DA16200_DELAY_5000MS (5000) +#define WIFI_ONCHIP_DA16200_DELAY_8000MS (8000) +#define WIFI_ONCHIP_DA16200_DELAY_15SEC (15000) + +/* Minimum string size for getting local time string */ +#define WIFI_ONCHIP_DA16200_LOCAL_TIME_STR_SIZE (25) + +#define HOURS_IN_SECONDS (3600) + +/* Socket Types supported */ +#define WIFI_ONCHIP_DA16200_SOCKET_TYPE_TCP_SERVER (0) +#define WIFI_ONCHIP_DA16200_SOCKET_TYPE_TCP_CLIENT (1) +#define WIFI_ONCHIP_DA16200_SOCKET_TYPE_UDP (2) +#define WIFI_ONCHIP_DA16200_SOCKET_TYPE_MAX (3) + +/* Error Response Codes */ +#define WIFI_ONCHIP_DA16200_ERR_UNKNOWN_CMD (-1) +#define WIFI_ONCHIP_DA16200_ERR_INSUF_PARAMS (-2) +#define WIFI_ONCHIP_DA16200_ERR_TOO_MANY_PARAMS (-3) +#define WIFI_ONCHIP_DA16200_ERR_INVALID_PARAM (-4) +#define WIFI_ONCHIP_DA16200_ERR_UNSUPPORTED_FUN (-5) +#define WIFI_ONCHIP_DA16200_ERR_NOT_CONNECTED_AP (-6) +#define WIFI_ONCHIP_DA16200_ERR_NO_RESULT (-7) +#define WIFI_ONCHIP_DA16200_ERR_RESP_BUF_OVERFLOW (-8) +#define WIFI_ONCHIP_DA16200_ERR_FUNC_NOT_CONFIG (-9) +#define WIFI_ONCHIP_DA16200_ERR_CMD_TIMEOUT (-10) +#define WIFI_ONCHIP_DA16200_ERR_NVRAM_WR_FAIL (-11) +#define WIFI_ONCHIP_DA16200_ERR_RETEN_MEM_WR_FAIL (-12) +#define WIFI_ONCHIP_DA16200_ERR_UNKNOWN (-99) + +#define sbFLAGS_IS_MESSAGE_BUFFER ((uint8_t) 1) /* Set if the stream buffer was created as a message buffer, in which case it holds discrete messages rather than a stream. */ +#define sbBYTES_TO_STORE_MESSAGE_LENGTH (sizeof(configMESSAGE_BUFFER_LENGTH_TYPE)) + +/* Unique number for WIFI Open status */ +#define WIFI_OPEN (0x57495749ULL) // Is "WIFI" in ASCII + +/* Unique number for SCI Open Status */ +#if (BSP_FEATURE_SCI_VERSION == 2U) + #define SCIU_OPEN (0x53434942U) // Is "SCIB" in ASCII +#else + #define SCIU_OPEN (0x53434955U) // Is "SCIU" in ASCII +#endif + +#define UART_BAUD_MAX_CNT (4) + +/* UART Baud rates */ +#define UART_BAUD_115200 (115200) +#define UART_BAUD_230400 (230400) +#define UART_BAUD_460800 (460800) +#define UART_BAUD_921600 (921600) + +/*********************************************************************************************************************** + * Extern variables + **********************************************************************************************************************/ +extern const ioport_instance_t g_ioport; + +/*********************************************************************************************************************** + * Enumerations + **********************************************************************************************************************/ + +/* Numeric return types for AT basic function commands */ +typedef enum +{ + WIFI_ONCHIP_DA16200_RETURN_OK = 0, ///< WIFI_ONCHIP_DA16200_RETURN_OK + WIFI_ONCHIP_DA16200_RETURN_INIT_OK, ///< WIFI_ONCHIP_DA16200_RETURN_INIT_OK + WIFI_ONCHIP_DA16200_RETURN_CONNECT, ///< WIFI_ONCHIP_DA16200_RETURN_CONNECT + WIFI_ONCHIP_DA16200_RETURN_CONNECT_FAIL, ///< WIFI_ONCHIP_DA16200_RETURN_CONNECT_FAIL + WIFI_ONCHIP_DA16200_RETURN_ERROR_CODES, + WIFI_ONCHIP_DA16200_RETURN_PROVISION_IDLE, + WIFI_ONCHIP_DA16200_RETURN_PROVISION_START +} da16200_return_code_t; + +/*********************************************************************************************************************** + * Static Globals + **********************************************************************************************************************/ +static rm_wifi_onchip_da16200_baud_setting_t g_baud_setting = +{ +#if (2U == BSP_FEATURE_SCI_VERSION) + .baudrate_bits_b.brme = 0, + .baudrate_bits_b.abcse = 0, + .baudrate_bits_b.abcs = 0, + .baudrate_bits_b.bgdm = 0, + .baudrate_bits_b.brr = 0, + .baudrate_bits_b.mddr = 0, +#else + .semr_baudrate_bits_b.brme = 0, + .semr_baudrate_bits_b.abcse = 0, + .semr_baudrate_bits_b.abcs = 0, + .semr_baudrate_bits_b.bgdm = 0, + .brr = 0, + .mddr = 0, +#endif +}; + +/* Control instance for the da16200 wifi module */ +static wifi_onchip_da16200_instance_ctrl_t g_rm_wifi_onchip_da16200_instance; + +/* Transmit and receive mutexes for UARTs */ +static StaticSemaphore_t g_socket_mutexes[2]; +static StaticSemaphore_t g_uart_tei_mutex[2]; + +/** + * Maximum time in ticks to wait for obtaining a semaphore. + */ +static const TickType_t wifi_sx_wifi_onchip_da16200_sem_block_timeout = pdMS_TO_TICKS( + WIFI_ONCHIP_DA16200_CFG_SEM_MAX_TIMEOUT); + +static uint8_t rx_buffer[WIFI_ONCHIP_DA16200_TEMP_BUFFER_SIZE] = {0}; +static uint8_t rx_data_index = 0; + +/* Structure that hold state information on the buffer. */ +typedef struct StreamBufferDef_t /*lint !e9058 Style convention uses tag. */ +{ + volatile size_t xTail; /* Index to the next item to read within the buffer. */ + volatile size_t xHead; /* Index to the next item to write within the buffer. */ + size_t xLength; /* The length of the buffer pointed to by pucBuffer. */ + size_t xTriggerLevelBytes; /* The number of bytes that must be in the stream buffer before a task that is waiting for data is unblocked. */ + volatile TaskHandle_t xTaskWaitingToReceive; /* Holds the handle of a task waiting for data, or NULL if no tasks are waiting. */ + volatile TaskHandle_t xTaskWaitingToSend; /* Holds the handle of a task waiting to send data to a message buffer that is full. */ + uint8_t * pucBuffer; /* Points to the buffer itself - that is - the RAM that stores the data passed through the buffer. */ + uint8_t ucFlags; +#if (configUSE_TRACE_FACILITY == 1) + UBaseType_t uxStreamBufferNumber; /* Used for tracing purposes. */ +#endif +} StreamBuffer_t; + +#ifndef sbRECEIVE_COMPLETED + #define sbRECEIVE_COMPLETED(pxStreamBuffer) \ + vTaskSuspendAll(); \ + { \ + if ((pxStreamBuffer)->xTaskWaitingToSend != NULL) \ + { \ + (void) xTaskNotify((pxStreamBuffer)->xTaskWaitingToSend, (uint32_t) 0, eNoAction); \ + (pxStreamBuffer)->xTaskWaitingToSend = NULL; \ + } \ + } \ + (void) xTaskResumeAll(); +#endif /* sbRECEIVE_COMPLETED */ + +/*********************************************************************************************************************** + * Local function prototypes + **********************************************************************************************************************/ +static void rm_wifi_onchip_da16200_cleanup_open(wifi_onchip_da16200_instance_ctrl_t * const p_instance_ctrl); +static void rm_wifi_onchip_da16200_wifi_module_reset(wifi_onchip_da16200_instance_ctrl_t * const p_instance_ctrl); +static fsp_err_t rm_wifi_onchip_da16200_error_lookup(char * resp); +static fsp_err_t rm_wifi_onchip_da16200_send_basic(wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl, + uint32_t serial_ch_id, + const char * p_textstring, + uint32_t length, + uint32_t timeout_ms, + uint32_t retry_delay, + const char * p_expect_code); + +static BaseType_t rm_wifi_onchip_da16200_send_basic_take_mutex(wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl, + uint32_t mutex_flag); +static BaseType_t rm_wifi_onchip_da16200_send_basic_give_mutex(wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl, + uint32_t mutex_flag); + +static void rm_wifi_da16200_handle_incoming_socket_data(da16200_socket_t * pSocket, uint8_t data_byte); + +static size_t xStreamBufferReceiveAlt(StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait); + +#if (1 == WIFI_ONCHIP_DA16200_CFG_SNTP_ENABLE) +static fsp_err_t rm_wifi_onchip_da16200_sntp_service_init(wifi_onchip_da16200_instance_ctrl_t * const p_instance_ctrl); + +#endif + +/*********************************************************************************************************************** + * Public Functions Implementation + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Opens and configures the WIFI_ONCHIP_DA16200 Middleware module. + * + * @param[in] p_cfg Pointer to pin configuration structure. + * + * @retval FSP_SUCCESS WIFI_ONCHIP_DA16200 successfully configured. + * @retval FSP_ERR_ASSERTION The parameter p_cfg or p_instance_ctrl is NULL. + * @retval FSP_ERR_OUT_OF_MEMORY There is no more heap memory available. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_ALREADY_OPEN Module is already open. This module can only be opened once. + * @retval FSP_ERR_WIFI_INIT_FAILED WiFi module initialization failed. + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_open (wifi_onchip_da16200_cfg_t const * const p_cfg) +{ + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + fsp_err_t err = FSP_SUCCESS; + uart_instance_t * p_uart = NULL; + rm_wifi_onchip_da16200_uart_extended_cfg_t uart0_cfg_extended; + uart_cfg_t uart0_cfg; + uint8_t temp_buff[WIFI_ONCHIP_DA16200_TEMP_BUFF_SIZE] = {0}; + uint8_t * p_temp_buff = temp_buff; + uint32_t uart_baud_rates[UART_BAUD_MAX_CNT] = + { + UART_BAUD_115200, UART_BAUD_230400, UART_BAUD_460800, UART_BAUD_921600 + }; + uint32_t curr_uart_baud = 0; + int index = 0; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_cfg); + FSP_ERROR_RETURN(WIFI_OPEN != p_instance_ctrl->open, FSP_ERR_ALREADY_OPEN); +#endif + + /* Clear the control structure */ + memset(p_instance_ctrl, 0, sizeof(wifi_onchip_da16200_instance_ctrl_t)); + + /* Update control structure from configuration values */ + p_instance_ctrl->p_wifi_onchip_da16200_cfg = p_cfg; + p_instance_ctrl->num_uarts = p_cfg->num_uarts; + + for (uint32_t i = 0; i < p_instance_ctrl->num_uarts; i++) + { + p_instance_ctrl->uart_instance_objects[i] = (uart_instance_t *) p_cfg->uart_instances[i]; + + p_instance_ctrl->uart_tei_sem[i] = xSemaphoreCreateBinaryStatic(&g_uart_tei_mutex[i]); + if (NULL == p_instance_ctrl->uart_tei_sem[i]) + { + rm_wifi_onchip_da16200_cleanup_open(p_instance_ctrl); + } + + FSP_ERROR_RETURN(NULL != p_instance_ctrl->uart_tei_sem[i], FSP_ERR_OUT_OF_MEMORY); + + xSemaphoreTake(p_instance_ctrl->uart_tei_sem[i], 0); + } + + p_instance_ctrl->reset_pin = p_cfg->reset_pin; + p_instance_ctrl->num_creatable_sockets = p_cfg->num_sockets; + p_instance_ctrl->curr_cmd_port = WIFI_ONCHIP_DA16200_UART_INITIAL_PORT; + + /* Reset the wi-fi module to a known state */ + rm_wifi_onchip_da16200_wifi_module_reset(p_instance_ctrl); + + /* Create the Tx/Rx mutexes */ + if (p_instance_ctrl->tx_sem != NULL) + { + vSemaphoreDelete(p_instance_ctrl->tx_sem); + } + + p_instance_ctrl->tx_sem = xSemaphoreCreateMutexStatic(&g_socket_mutexes[0]); + if (NULL == p_instance_ctrl->tx_sem) + { + rm_wifi_onchip_da16200_cleanup_open(p_instance_ctrl); + } + + FSP_ERROR_RETURN(NULL != p_instance_ctrl->tx_sem, FSP_ERR_OUT_OF_MEMORY); + + if (p_instance_ctrl->rx_sem != NULL) + { + vSemaphoreDelete(p_instance_ctrl->rx_sem); + } + + p_instance_ctrl->rx_sem = xSemaphoreCreateMutexStatic(&g_socket_mutexes[1]); + if (NULL == p_instance_ctrl->rx_sem) + { + rm_wifi_onchip_da16200_cleanup_open(p_instance_ctrl); + } + + FSP_ERROR_RETURN(NULL != p_instance_ctrl->rx_sem, FSP_ERR_OUT_OF_MEMORY); + + /* Create the stream buffer used to transfer UART data from ISR */ + p_instance_ctrl->socket_byteq_hdl = xStreamBufferCreateStatic(sizeof(p_instance_ctrl->cmd_rx_queue_buf), + 1, + p_instance_ctrl->cmd_rx_queue_buf, + &p_instance_ctrl->socket_byteq_struct); + if (NULL == p_instance_ctrl->socket_byteq_hdl) + { + rm_wifi_onchip_da16200_cleanup_open(p_instance_ctrl); + } + + FSP_ERROR_RETURN(NULL != p_instance_ctrl->socket_byteq_hdl, FSP_ERR_OUT_OF_MEMORY); + + /* Create memory copy of uart extended configuration and then copy new configuration values in. */ + memcpy((void *) &uart0_cfg_extended, (void *) p_instance_ctrl->uart_instance_objects[0]->p_cfg->p_extend, + sizeof(rm_wifi_onchip_da16200_uart_extended_cfg_t)); + + /* Create memory copy of uart configuration and update with new extended configuration structure. */ + memcpy((void *) &uart0_cfg, p_instance_ctrl->uart_instance_objects[0]->p_cfg, sizeof(uart_cfg_t)); + + for (index = 0; index < UART_BAUD_MAX_CNT; index++) + { + curr_uart_baud = uart_baud_rates[index]; + + (*p_sci_uart_baud_calculate)(curr_uart_baud, WIFI_ONCHIP_DA16200_DEFAULT_MODULATION, + WIFI_ONCHIP_DA16200_DEFAULT_ERROR, &g_baud_setting); + + uart0_cfg_extended.p_baud_setting = &g_baud_setting; + uart0_cfg_extended.flow_control = RM_WIFI_ONCHIP_DA16200_SCI_UART_FLOW_CONTROL_RTS; + uart0_cfg_extended.flow_control_pin = (bsp_io_port_pin_t) WIFI_ONCHIP_DA16200_BSP_PIN_PORT_INVALID; + + uart0_cfg.p_extend = (void *) &uart0_cfg_extended; + uart0_cfg.p_callback = rm_wifi_onchip_da16200_uart_callback; + + /* Open UART */ + p_uart = p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_DA16200_UART_INITIAL_PORT]; + err = p_uart->p_api->open(p_uart->p_ctrl, &uart0_cfg); + + if (FSP_SUCCESS != err) + { + rm_wifi_onchip_da16200_cleanup_open(p_instance_ctrl); + } + + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_INIT_FAILED); + + /* Delay after open */ + vTaskDelay(pdMS_TO_TICKS(WIFI_ONCHIP_DA16200_TIMEOUT_10MS)); + + /* Test basic communications with an AT command. */ + err = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + "ATZ\r", + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_20MS, + WIFI_ONCHIP_DA16200_DELAY_20MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + if (FSP_SUCCESS != err) + { + vTaskDelay(pdMS_TO_TICKS(WIFI_ONCHIP_DA16200_TIMEOUT_10MS)); + + /* Test basic communications with an AT command. */ + err = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + "ATZ\r", + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_20MS, + WIFI_ONCHIP_DA16200_DELAY_20MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + if (FSP_SUCCESS != err) + { + /* Close the UART port */ + err = p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_DA16200_UART_INITIAL_PORT]->p_api->close( + p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_DA16200_UART_INITIAL_PORT]->p_ctrl); + + if (FSP_SUCCESS != err) + { + rm_wifi_onchip_da16200_cleanup_open(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_INIT_FAILED); + } + + /* Delay after close */ + vTaskDelay(pdMS_TO_TICKS(WIFI_ONCHIP_DA16200_TIMEOUT_10MS)); + } + else + { + break; + } + } + else + { + break; + } + } + + FSP_ERROR_RETURN(UART_BAUD_MAX_CNT != (index), FSP_ERR_WIFI_FAILED); + + /* Update the module baud rate in case if it doesn't match with user configured baud rate */ + if (curr_uart_baud != (uint32_t) strtol((char *) g_wifi_onchip_da16200_uart_cmd_baud, NULL, 10)) + { + strncpy((char *) p_temp_buff, "ATB=", 5); + strncat((char *) p_temp_buff, g_wifi_onchip_da16200_uart_cmd_baud, 10); + strncat((char *) p_temp_buff, "\r", 3); + + /* Send UART Baud rate reconfiguration AT command to wifi module */ + err = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + (char *) p_temp_buff, + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_20MS, + WIFI_ONCHIP_DA16200_DELAY_20MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + if (FSP_SUCCESS != err) + { + rm_wifi_onchip_da16200_cleanup_open(p_instance_ctrl); + } + + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_INIT_FAILED); + } + + /* Close the UART port */ + err = p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_DA16200_UART_INITIAL_PORT]->p_api->close( + p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_DA16200_UART_INITIAL_PORT]->p_ctrl); + + if (FSP_SUCCESS != err) + { + rm_wifi_onchip_da16200_cleanup_open(p_instance_ctrl); + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_INIT_FAILED); + } + + /* Delay after close */ + vTaskDelay(pdMS_TO_TICKS(WIFI_ONCHIP_DA16200_TIMEOUT_10MS)); + + /* Open uart port with config values from the configurator */ + p_uart = p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_DA16200_UART_INITIAL_PORT]; + err = p_uart->p_api->open(p_uart->p_ctrl, p_uart->p_cfg); + if (FSP_SUCCESS != err) + { + rm_wifi_onchip_da16200_cleanup_open(p_instance_ctrl); + } + + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_INIT_FAILED); + + /* Delay after open */ + vTaskDelay(pdMS_TO_TICKS(WIFI_ONCHIP_DA16200_TIMEOUT_100MS)); + + /* Set AP mode */ + err = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + "AT+WFMODE=0\r", + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_500MS, + WIFI_ONCHIP_DA16200_DELAY_20MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_INIT_FAILED); + + /* Set Country Code */ + snprintf((char *) p_instance_ctrl->cmd_tx_buff, + sizeof(p_instance_ctrl->cmd_tx_buff), + "AT+WFCC=%s\r", + p_cfg->country_code); + + err = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + (char *) p_instance_ctrl->cmd_tx_buff, + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_500MS, + WIFI_ONCHIP_DA16200_DELAY_20MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_INIT_FAILED); + +#if (1 == WIFI_ONCHIP_DA16200_CFG_SNTP_ENABLE) + p_instance_ctrl->open = WIFI_OPEN; // Allows interface calls to complete for SNTP init. + err = rm_wifi_onchip_da16200_sntp_service_init(p_instance_ctrl); + p_instance_ctrl->open = 0; + if (FSP_SUCCESS != err) + { + rm_wifi_onchip_da16200_cleanup_open(p_instance_ctrl); + } + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_INIT_FAILED); +#endif + + p_instance_ctrl->curr_socket_index = 0; + p_instance_ctrl->open = WIFI_OPEN; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Disables WIFI_ONCHIP_DA16200. + * + * @retval FSP_SUCCESS WIFI_ONCHIP_DA16200 closed successfully. + * @retval FSP_ERR_ASSERTION The parameter p_instance_ctrl is NULL. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_close (void) +{ + uint32_t mutex_flag; + fsp_err_t err = FSP_SUCCESS; + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Take mutexes */ + mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_TX | WIFI_ONCHIP_DA16200_MUTEX_RX); + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + /* Tell wifi module to disconnect from the current AP */ + err = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + "AT+WFQAP\r", + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_20MS, + WIFI_ONCHIP_DA16200_DELAY_50MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + p_instance_ctrl->open = 0; + + rm_wifi_onchip_da16200_cleanup_open(p_instance_ctrl); + + return err; +} + +/*******************************************************************************************************************//** + * Disconnects from connected AP. + * + * @retval FSP_SUCCESS WIFI_ONCHIP_DA16200 disconnected successfully. + * @retval FSP_ERR_ASSERTION The parameter p_instance_ctrl is NULL. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_disconnect (void) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t mutex_flag; + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Take mutexes */ + mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_TX | WIFI_ONCHIP_DA16200_MUTEX_RX); + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + /* Tell wifi module to disconnect from the current AP */ + err = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + "AT+WFQAP\r", + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_3SEC, + WIFI_ONCHIP_DA16200_DELAY_500MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + if (FSP_SUCCESS == err) + { + memset(p_instance_ctrl->curr_ipaddr, 0, 4); + memset(p_instance_ctrl->curr_subnetmask, 0, 4); + memset(p_instance_ctrl->curr_gateway, 0, 4); + } + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return err; +} + +/*******************************************************************************************************************//** + * Check if DA16200 module is connected to an Access point. + * + * @param[out] p_status Pointer to integer holding the socket connection status. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_WIFI_AP_NOT_CONNECTED WiFi module is not connected to access point. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_connected (fsp_err_t * p_status) +{ + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_status); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + uint32_t value = *((uint32_t *) &p_instance_ctrl->curr_ipaddr[0]); + if (value != 0) + { + *p_status = FSP_SUCCESS; + } + else + { + *p_status = FSP_ERR_WIFI_AP_NOT_CONNECTED; + } + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Return the network information for the connection to the access point. + * + * @param[out] p_ip_addr Pointer to integer holding the IP address. + * @param[out] p_subnet_mask Pointer to integer holding the subnet mask. + * @param[out] p_gateway Pointer to integer holding the gateway. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_ASSERTION A parameter pointer is NULL. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_WIFI_AP_NOT_CONNECTED No connection to access point has happened. + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_network_info_get (uint32_t * p_ip_addr, uint32_t * p_subnet_mask, uint32_t * p_gateway) +{ + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_ip_addr); + FSP_ASSERT(NULL != p_subnet_mask); + FSP_ASSERT(NULL != p_gateway); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Make sure IP address has been assigned */ + uint32_t ip = *((uint32_t *) p_instance_ctrl->curr_ipaddr); + if (!ip) + { + return FSP_ERR_WIFI_AP_NOT_CONNECTED; + } + + *p_ip_addr = ip; + *p_subnet_mask = *((uint32_t *) p_instance_ctrl->curr_subnetmask); + *p_gateway = *((uint32_t *) p_instance_ctrl->curr_gateway); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Connects to the specified Wifi Access Point. + * + * @param[in] p_ssid Pointer to SSID of Wifi Access Point. + * @param[in] security Security type to use for connection. + * @param[in] p_passphrase Pointer to the passphrase to use for connection. + * @param[in] enc_type Encryption type to use for connection. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_ASSERTION The parameter pSSID or p_passphrase is NULL. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_INVALID_ARGUMENT No commas are accepted in the SSID or Passphrase. + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_connect (const char * p_ssid, + WIFISecurity_t security, + const char * p_passphrase, + uint8_t enc_type) +{ + fsp_err_t ret; + uint32_t mutex_flag; + fsp_err_t status = FSP_SUCCESS; + int32_t scanf_ret; + int ipaddr[4] = {0, 0, 0, 0}; + int subnetmask[4] = {0, 0, 0, 0}; + int gateway[4] = {0, 0, 0, 0}; + + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + char * ptr = (char *) (p_instance_ctrl->cmd_rx_buff); + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_ssid); + FSP_ASSERT(NULL != p_passphrase); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Commas are not accepted by the WiFi module in the SSID or Passphrase */ + FSP_ERROR_RETURN((NULL == strchr(p_ssid, ',') && NULL == strchr(p_passphrase, ',')), FSP_ERR_INVALID_ARGUMENT); + + mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_TX | WIFI_ONCHIP_DA16200_MUTEX_RX); + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + rm_wifi_onchip_da16200_connected(&status); + + if (FSP_SUCCESS == status) + { + /* If Wifi is already connected, do nothing and return fail. */ + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return FSP_ERR_WIFI_FAILED; + } + + memset(p_instance_ctrl->cmd_tx_buff, 0, sizeof(p_instance_ctrl->cmd_tx_buff)); + + /* Connect to an OPEN security AP */ + if (eWiFiSecurityOpen == security) + { + strncpy((char *) p_instance_ctrl->cmd_tx_buff, "AT+WFJAP=", 10); + strncat((char *) p_instance_ctrl->cmd_tx_buff, p_ssid, wificonfigMAX_SSID_LEN); + strncat((char *) p_instance_ctrl->cmd_tx_buff, ",", 2); + strncat((char *) p_instance_ctrl->cmd_tx_buff, "0", 2); + strncat((char *) p_instance_ctrl->cmd_tx_buff, ",", 2); + } + else if ((eWiFiSecurityWPA == security) || (eWiFiSecurityWPA2 == security)) + { + strncpy((char *) p_instance_ctrl->cmd_tx_buff, "AT+WFJAP=", 10); + strncat((char *) p_instance_ctrl->cmd_tx_buff, p_ssid, wificonfigMAX_SSID_LEN); + strncat((char *) p_instance_ctrl->cmd_tx_buff, ",", 2); + if (eWiFiSecurityWPA == security) + { + strncat((char *) p_instance_ctrl->cmd_tx_buff, "2,", 3); + } + else + { + strncat((char *) p_instance_ctrl->cmd_tx_buff, "3,", 3); + } + + switch (enc_type) + { + case WIFI_ONCHIP_DA16200_TKIP_ENC_TYPE: + { + strncat((char *) p_instance_ctrl->cmd_tx_buff, "0,", 3); + break; + } + + case WIFI_ONCHIP_DA16200_AES_ENC_TYPE: + { + strncat((char *) p_instance_ctrl->cmd_tx_buff, "1,", 3); + break; + } + + case WIFI_ONCHIP_DA16200_TKIP_AES_ENC_TYPE: + { + strncat((char *) p_instance_ctrl->cmd_tx_buff, "2,", 3); + break; + } + } + } + else if (eWiFiSecurityWPA3 == security) + { + strncpy((char *) p_instance_ctrl->cmd_tx_buff, "AT+WFJAPA=", 11); + strncat((char *) p_instance_ctrl->cmd_tx_buff, p_ssid, wificonfigMAX_SSID_LEN); + strncat((char *) p_instance_ctrl->cmd_tx_buff, ",", 2); + } + else + { + /* Return with error for unsupported secuirty types */ + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return FSP_ERR_WIFI_FAILED; + } + + strncat((char *) p_instance_ctrl->cmd_tx_buff, p_passphrase, wificonfigMAX_PASSPHRASE_LEN); + strncat((char *) p_instance_ctrl->cmd_tx_buff, "\r", 2); + + ret = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + (char *) p_instance_ctrl->cmd_tx_buff, + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_5SEC, + WIFI_ONCHIP_DA16200_DELAY_500MS, + WIFI_ONCHIP_DA16200_RETURN_CONN_TEXT); + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + if (FSP_SUCCESS == ret) + { + /* Parse the response */ + ptr = strstr(ptr, "ERROR:"); + if (NULL != ptr) + { + ret = rm_wifi_onchip_da16200_error_lookup(ptr); + } + else + { + /* Parsing the response */ + rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag); + + /* Enable DHCP */ + ret = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + "AT+NWDHC=1\r", + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_200MS, + WIFI_ONCHIP_DA16200_DELAY_500MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + FSP_ERROR_RETURN(FSP_SUCCESS == ret, FSP_ERR_WIFI_FAILED); + + ptr = (char *) (p_instance_ctrl->cmd_rx_buff); + + R_BSP_SoftwareDelay(WIFI_ONCHIP_DA16200_TIMEOUT_3SEC, BSP_DELAY_UNITS_MILLISECONDS); + + /* Call to get IP address does not always work the first time */ + for (int index = 0; index < WIFI_ONCHIP_DA16200_CFG_MAX_RETRIES_UART_COMMS; index++) + { + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + /* Query the IP address from the current AP */ + ret = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + "AT+NWIP=?\r", + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_5SEC, + WIFI_ONCHIP_DA16200_DELAY_200MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + FSP_ERROR_RETURN(FSP_SUCCESS == ret, FSP_ERR_WIFI_FAILED); + + /* Parsing the response */ + ptr = strstr(ptr, "+NWIP:"); + if (ptr == NULL) + { + R_BSP_SoftwareDelay(WIFI_ONCHIP_DA16200_TIMEOUT_3SEC, BSP_DELAY_UNITS_MILLISECONDS); + } + else + { + ptr = ptr + strlen("+NWIP: ,"); + + // NOLINTNEXTLINE(cert-err34-c) Disable warning about the use of sscanf + scanf_ret = sscanf((const char *) ptr, + "%d.%d.%d.%d,%d.%d.%d.%d,%d.%d.%d.%d", + &ipaddr[0], + &ipaddr[1], + &ipaddr[2], + &ipaddr[3], + &subnetmask[0], + &subnetmask[1], + &subnetmask[2], + &subnetmask[3], + &gateway[0], + &gateway[1], + &gateway[2], + &gateway[3]); + + FSP_ERROR_RETURN(12 == scanf_ret, FSP_ERR_WIFI_FAILED); + FSP_ERROR_RETURN(0 != (ipaddr[0] | ipaddr[1] | ipaddr[2] | ipaddr[3]), FSP_ERR_WIFI_FAILED); + + for (int i = 0; i < 4; i++) + { + p_instance_ctrl->curr_ipaddr[i] = (uint8_t) ipaddr[i]; + p_instance_ctrl->curr_subnetmask[i] = (uint8_t) subnetmask[i]; + p_instance_ctrl->curr_gateway[i] = (uint8_t) gateway[i]; + } + + break; + } + } + } + } + + return ret; +} + +/*******************************************************************************************************************//** + * Get MAC address. + * + * @param[out] p_macaddr Pointer array to hold mac address. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_ASSERTION The parameter p_macaddr is NULL. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_mac_addr_get (uint8_t * p_macaddr) +{ + fsp_err_t ret; + int32_t err; + unsigned int macaddr[6]; + uint32_t mutex_flag; + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + char * ptr = (char *) (p_instance_ctrl->cmd_rx_buff); + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_macaddr); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + memset((char *) p_instance_ctrl->cmd_rx_buff, 0, sizeof(p_instance_ctrl->cmd_rx_buff)); + + mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_TX | WIFI_ONCHIP_DA16200_MUTEX_RX); + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + ret = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + "AT+WFMAC=?\r", + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_400MS, + WIFI_ONCHIP_DA16200_DELAY_200MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + FSP_ERROR_RETURN(FSP_SUCCESS == ret, FSP_ERR_WIFI_FAILED); + + if (FSP_SUCCESS == ret) + { + /* Parsing the response */ + ptr = strstr(ptr, "+WFMAC:"); + FSP_ERROR_RETURN(NULL != ptr, FSP_ERR_INVALID_DATA); + + ptr = ptr + strlen("+WFMAC:"); + + // NOLINTNEXTLINE(cert-err34-c) Disable warning about the use of sscanf + err = sscanf((const char *) ptr, + "%2x:%2x:%2x:%2x:%2x:%2x", + &macaddr[0], + &macaddr[1], + &macaddr[2], + &macaddr[3], + &macaddr[4], + &macaddr[5]); + if (6 == err) + { + for (int i = 0; i < 6; i++) + { + p_macaddr[i] = (uint8_t) macaddr[i]; + } + } + else + { + ret = FSP_ERR_WIFI_FAILED; + } + } + + return ret; +} + +/*******************************************************************************************************************//** + * Get the information about local Wifi Access Points. + * + * @param[out] p_results Pointer to a structure array holding scanned Access Points. + * @param[in] maxNetworks Size of the structure array for holding APs. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_ASSERTION The parameter p_results or p_instance_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_WIFI_SCAN_COMPLETE Wifi scan has completed. + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_scan (WIFIScanResult_t * p_results, uint32_t maxNetworks) +{ + fsp_err_t ret = FSP_ERR_INTERNAL; + int32_t err; + uint32_t idx = 0; + uint8_t * bssid; + uint32_t mutex_flag; + + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_results); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + char * ptr = (char *) (p_instance_ctrl->cmd_rx_buff); + + FSP_ERROR_RETURN((NULL != p_results) && (0 != maxNetworks), FSP_ERR_INVALID_ARGUMENT); + + memset((char *) p_instance_ctrl->cmd_rx_buff, 0, sizeof(p_instance_ctrl->cmd_rx_buff)); + + mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_TX | WIFI_ONCHIP_DA16200_MUTEX_RX); + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + ret = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + "AT+WFSCAN\r", + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_8SEC, + WIFI_ONCHIP_DA16200_DELAY_1000MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + FSP_ERROR_RETURN(FSP_SUCCESS == ret, FSP_ERR_WIFI_FAILED); + + /* Parsing the response */ + ptr = strstr(ptr, "+WFSCAN:"); + FSP_ERROR_RETURN(NULL != ptr, FSP_ERR_INVALID_DATA); + ptr = ptr + strlen("+WFSCAN:"); + + do + { + if (((*ptr == 'O') && (*++ptr == 'K')) || (idx >= 10)) + { + break; + } + + /* BSSID */ + bssid = &p_results[idx].ucBSSID[0]; + unsigned int bssid2[6]; + memset(bssid2, 0, sizeof(bssid2)); + + // NOLINTNEXTLINE(cert-err34-c) Disable warning about the use of sscanf + err = sscanf(ptr, "%x:%x:%x:%x:%x:%x", &bssid2[0], &bssid2[1], &bssid2[2], &bssid2[3], &bssid2[4], &bssid2[5]); + + FSP_ERROR_RETURN(6 == err, FSP_ERR_WIFI_FAILED); + + if (6 != err) + { + ret = FSP_ERR_WIFI_FAILED; + break; + } + + /* Copy the bssid data into result */ + for (int i = 0; i < wificonfigMAX_BSSID_LEN; i++) + { + bssid[i] = (uint8_t) bssid2[i]; + } + + /* Advance string pointer to next section of scan info */ + ptr = strchr(ptr, '\t'); + if (NULL != ptr) + { + ptr++; + } + else + { + ret = FSP_ERR_WIFI_FAILED; + break; + } + + /* Ignore the frequency */ + ptr = strchr(ptr, '\t'); + if (NULL != ptr) + { + ptr++; + } + else + { + ret = FSP_ERR_WIFI_FAILED; + break; + } + + /* Copy signal strength from scan info buffer */ + uint32_t temp_val; + + // NOLINTNEXTLINE(cert-err34-c) Disable warning about the use of sscanf + err = sscanf(ptr, "%d", (int *) &temp_val); + if (1 != err) + { + ret = FSP_ERR_WIFI_FAILED; + break; + } + + p_results[idx].cRSSI = (int8_t) temp_val;; + + /* Advance string pointer to next section of scan info */ + ptr = strchr(ptr, '\t'); + if (NULL != ptr) + { + ptr++; + } + else + { + ret = FSP_ERR_WIFI_FAILED; + break; + } + + if ('\t' != *(ptr)) + { + if (0 == strncmp(ptr, "[WPA2-PSK", 9)) + { + p_results[idx].xSecurity = eWiFiSecurityWPA2; + } + else if (0 == strncmp(ptr, "[WPA-PSK", 8)) + { + p_results[idx].xSecurity = eWiFiSecurityWPA; + } + else if (0 == strncmp(ptr, "[OPEN]", 6)) + { + p_results[idx].xSecurity = eWiFiSecurityOpen; + } + else if (0 == strncmp(ptr, "[WPS]", 5)) + { + p_results[idx].xSecurity = eWiFiSecurityNotSupported; + } + else + { + /* Do Nothing */ + } + } + + /* Advance string pointer to next section of scan info */ + ptr = strchr(ptr, '\t'); + if (NULL != ptr) + { + ptr++; + } + else + { + ret = FSP_ERR_WIFI_FAILED; + break; + } + + /* Copy SSID from scan info buffer */ + int idx_ssid = 0; + while ((*ptr != '\n') && (idx_ssid < (wificonfigMAX_SSID_LEN - 1))) + { + p_results[idx].ucSSID[idx_ssid++] = (uint8_t) *ptr; + ptr++; + } + + /* Advance string pointer to next section of scan info */ + ptr++; + } while (++idx < maxNetworks); + + return ret; +} + +/*******************************************************************************************************************//** + * Ping an IP address on the network. + * + * @param[in] p_ip_addr Pointer to IP address array. + * @param[in] count Number of pings to attempt. + * @param[in] interval_ms Interval between ping attempts. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_ASSERTION The parameter p_ip_addr is NULL. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_ping (uint8_t * p_ip_addr, int count, uint32_t interval_ms) +{ + FSP_PARAMETER_NOT_USED(interval_ms); + fsp_err_t func_ret = FSP_ERR_WIFI_FAILED; + uint32_t mutex_flag; + int sent_cnt = 0; + int recv_cnt = 0; + + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_ip_addr); + FSP_ERROR_RETURN(0 != count, FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + memset((char *) p_instance_ctrl->cmd_rx_buff, 0, sizeof(p_instance_ctrl->cmd_rx_buff)); + char * ptr = (char *) (p_instance_ctrl->cmd_rx_buff); + + mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_TX | WIFI_ONCHIP_DA16200_MUTEX_RX); + FSP_ERROR_RETURN((pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag)), + FSP_ERR_WIFI_FAILED); + + snprintf((char *) p_instance_ctrl->cmd_tx_buff, + sizeof(p_instance_ctrl->cmd_tx_buff), + "AT+NWPING=0,%d.%d.%d.%d,%d\r", + p_ip_addr[0], + p_ip_addr[1], + p_ip_addr[2], + p_ip_addr[3], + count); + + func_ret = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + (char *) p_instance_ctrl->cmd_tx_buff, + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_2SEC, + WIFI_ONCHIP_DA16200_DELAY_500MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + /* Parsing the response */ + ptr = strstr(ptr, "+NWPING:"); + if (ptr != NULL) + { + ptr = ptr + strlen("+NWPING:"); + + sent_cnt = strtol(ptr, NULL, 10); + + /* Advance string pointer to next section */ + ptr = strchr(ptr, ','); + if (NULL != ptr) + { + ptr++; + } + + recv_cnt = strtol(ptr, NULL, 10); + + if (sent_cnt != recv_cnt) + { + func_ret = FSP_ERR_WIFI_FAILED; + } + } + else + { + func_ret = FSP_ERR_WIFI_FAILED; + } + + return func_ret; +} + +/*******************************************************************************************************************//** + * Get the IP address from the module. + * + * @param[in] p_ip_addr Pointer to the IP address string. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_ASSERTION Assertion error occurred. + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_ipaddr_get (uint32_t * p_ip_addr) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t mutex_flag; + int32_t scanf_ret; + int index = 0; + int ipaddr[4] = {0, 0, 0, 0}; + int subnetmask[4] = {0, 0, 0, 0}; + int gateway[4] = {0, 0, 0, 0}; + + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + char * ptr = (char *) (p_instance_ctrl->cmd_rx_buff); + memset((char *) p_instance_ctrl->cmd_rx_buff, 0, sizeof(p_instance_ctrl->cmd_rx_buff)); + + /* Take mutexes */ + mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_TX | WIFI_ONCHIP_DA16200_MUTEX_RX); + + /* Call to get IP address does not always work the first time */ + for (index = 0; index < WIFI_ONCHIP_DA16200_CFG_MAX_RETRIES_UART_COMMS; index++) + { + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + /* Query the IP address from the current AP */ + err = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + "AT+NWIP=?\r", + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_5SEC, + WIFI_ONCHIP_DA16200_DELAY_200MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_FAILED); + + /* Parsing the response */ + ptr = strstr(ptr, "+NWIP:"); + if (ptr == NULL) + { + R_BSP_SoftwareDelay(WIFI_ONCHIP_DA16200_TIMEOUT_3SEC, BSP_DELAY_UNITS_MILLISECONDS); + } + else + { + ptr = ptr + strlen("+NWIP: ,"); + + // NOLINTNEXTLINE(cert-err34-c) Disable warning about the use of sscanf + scanf_ret = sscanf((const char *) ptr, + "%d.%d.%d.%d,%d.%d.%d.%d,%d.%d.%d.%d", + &ipaddr[0], + &ipaddr[1], + &ipaddr[2], + &ipaddr[3], + &subnetmask[0], + &subnetmask[1], + &subnetmask[2], + &subnetmask[3], + &gateway[0], + &gateway[1], + &gateway[2], + &gateway[3]); + + FSP_ERROR_RETURN(12 == scanf_ret, FSP_ERR_WIFI_FAILED); + FSP_ERROR_RETURN(0 != (ipaddr[0] | ipaddr[1] | ipaddr[2] | ipaddr[3]), FSP_ERR_WIFI_FAILED); + + for (int i = 0; i < 4; i++) + { + p_instance_ctrl->curr_ipaddr[i] = (uint8_t) ipaddr[i]; + p_ip_addr[i] = (uint8_t) ipaddr[i]; + p_instance_ctrl->curr_subnetmask[i] = (uint8_t) subnetmask[i]; + p_instance_ctrl->curr_gateway[i] = (uint8_t) gateway[i]; + } + + break; + } + } + + FSP_ERROR_RETURN(WIFI_ONCHIP_DA16200_CFG_MAX_RETRIES_UART_COMMS != (index), FSP_ERR_WIFI_FAILED); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Initiate a DNS lookup for a given URL. + * + * @param[in] p_textstring Pointer to array holding URL to query from DNS. + * @param[out] p_ip_addr Pointer to IP address returned from look up. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_ASSERTION The p_instance_ctrl, p_textstring, p_ip_addr is NULL. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_INVALID_ARGUMENT The URL passed in is to long. + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_dns_query (const char * p_textstring, uint8_t * p_ip_addr) +{ + fsp_err_t func_ret; + int32_t scanf_ret; + int temp_addr[4] = {0, 0, 0, 0}; + int32_t i = 0; + uint32_t mutex_flag; + + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + char * buff = (char *) p_instance_ctrl->cmd_rx_buff; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_textstring); + FSP_ASSERT(NULL != p_ip_addr); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN((sizeof(p_instance_ctrl->cmd_tx_buff) - 16) > strlen(p_textstring), FSP_ERR_INVALID_ARGUMENT) +#endif + + memset((char *) p_instance_ctrl->cmd_rx_buff, 0, sizeof(p_instance_ctrl->cmd_rx_buff)); + + mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_TX | WIFI_ONCHIP_DA16200_MUTEX_RX); + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + strncpy((char *) p_instance_ctrl->cmd_tx_buff, "AT+NWHOST=", sizeof(p_instance_ctrl->cmd_tx_buff)); + snprintf((char *) p_instance_ctrl->cmd_tx_buff + strlen((char *) p_instance_ctrl->cmd_tx_buff), + sizeof(p_instance_ctrl->cmd_tx_buff), "%s\r\n", p_textstring); + + func_ret = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + (char *) p_instance_ctrl->cmd_tx_buff, + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_8SEC, + WIFI_ONCHIP_DA16200_DELAY_1000MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + if (FSP_SUCCESS == func_ret) + { + /* Parsing the response */ + buff = strstr(buff, "+NWHOST:"); + FSP_ERROR_RETURN(NULL != buff, FSP_ERR_INVALID_DATA); + + buff = buff + strlen("+NWHOST:"); + + // NOLINTNEXTLINE(cert-err34-c) Disable warning about the use of sscanf + scanf_ret = sscanf((const char *) buff, + "%d.%d.%d.%d", + &temp_addr[0], + &temp_addr[1], + &temp_addr[2], + &temp_addr[3]); + + FSP_ERROR_RETURN(4 == scanf_ret, FSP_ERR_WIFI_FAILED); + + for (i = 0; i < 4; i++) + { + if (temp_addr[i] <= UINT8_MAX) + { + p_ip_addr[i] = (uint8_t) temp_addr[i]; + } + else + { + func_ret = FSP_ERR_WIFI_FAILED; + break; + } + } + } + + return func_ret; +} + +/*******************************************************************************************************************//** + * Get the next available socket ID. + * + * @param[out] p_socket_id Pointer to an integer to hold the socket ID. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_ASSERTION The parameter p_socket_id is NULL. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_WIFI_FAILED Error occured in the execution of this function + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_avail_socket_get (uint32_t * p_socket_id) +{ + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_socket_id); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + for (uint32_t i = 0; i < p_instance_ctrl->num_creatable_sockets; i++) + { + if (0 == p_instance_ctrl->sockets[i].socket_create_flag) + { + *p_socket_id = (uint8_t) i; + + return FSP_SUCCESS; + } + } + + *p_socket_id = UINT8_MAX; + + return FSP_ERR_WIFI_FAILED; +} + +/*******************************************************************************************************************//** + * Get the socket status. + * + * @param[in] socket_no Socket ID number. + * @param[out] p_socket_status Pointer to an integer to hold the socket status + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_ASSERTION The parameter p_instance_ctrl or p_socket_status is NULL. The value of socket_no + * is greater than/equal num_creatable_sockets. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_socket_status_get (uint32_t socket_no, uint32_t * p_socket_status) +{ + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_socket_status); + FSP_ASSERT(socket_no < p_instance_ctrl->num_creatable_sockets); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + *p_socket_status = p_instance_ctrl->sockets[socket_no].socket_status; + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Create a new socket instance. + * + * @param[in] socket_no Socket ID number. + * @param[in] type Socket type. + * @param[in] ipversion Socket IP type. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_ASSERTION The p_instance_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_UNSUPPORTED Selected mode not supported by this API + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_socket_create (uint32_t socket_no, uint32_t type, uint32_t ipversion) +{ + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ASSERT(type <= WIFI_ONCHIP_DA16200_SOCKET_TYPE_MAX); +#endif + + if ((1 == p_instance_ctrl->sockets[socket_no].socket_create_flag) || (1 < p_instance_ctrl->num_creatable_sockets)) + { + return FSP_ERR_WIFI_FAILED; + } + + if (WIFI_ONCHIP_DA16200_SOCKET_TYPE_TCP_CLIENT == type) + { + p_instance_ctrl->sockets[socket_no].socket_type = WIFI_ONCHIP_DA16200_SOCKET_TYPE_TCP_CLIENT; + } + else + { + return FSP_ERR_UNSUPPORTED; + } + + for (uint32_t i = 0; i < p_instance_ctrl->num_creatable_sockets; i++) + { + if (NULL == p_instance_ctrl->sockets[i].socket_byteq_hdl) + { + p_instance_ctrl->sockets[i].socket_byteq_hdl = + xStreamBufferCreateStatic(sizeof(p_instance_ctrl->sockets[i].socket_recv_buff), + 1, + p_instance_ctrl->sockets[i].socket_recv_buff, + &p_instance_ctrl->sockets[i].socket_byteq_struct); + } + + FSP_ERROR_RETURN(NULL != p_instance_ctrl->sockets[i].socket_byteq_hdl, FSP_ERR_WIFI_FAILED); + } + + p_instance_ctrl->curr_socket_index = socket_no; + memset(rx_buffer, 0, sizeof(rx_buffer)); + + BaseType_t rst_status = xStreamBufferReset(p_instance_ctrl->sockets[socket_no].socket_byteq_hdl); + if (pdPASS != rst_status) + { + return FSP_ERR_WIFI_FAILED; + } + + FSP_PARAMETER_NOT_USED(ipversion); + + return FSP_SUCCESS; +} + +/*******************************************************************************************************************//** + * Connect to a specific IP and Port using socket. + * + * @param[in] socket_no Socket ID number. + * @param[in] ipaddr IP address for socket connection. + * @param[in] port Port number for socket connection. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_ASSERTION The p_instance_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_tcp_connect (uint32_t socket_no, uint32_t ipaddr, uint32_t port) +{ + fsp_err_t ret = FSP_SUCCESS; + uint32_t mutex_flag; + + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_TX | WIFI_ONCHIP_DA16200_MUTEX_RX); + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + memset(p_instance_ctrl->cmd_tx_buff, 0, sizeof(p_instance_ctrl->cmd_tx_buff)); + memset(p_instance_ctrl->cmd_rx_buff, 0, sizeof(p_instance_ctrl->cmd_rx_buff)); + + // NOLINTNEXTLINE(clang-analyzer-security.insecureAPI.strcpy) Disable warning about use of strcpy + strncpy((char *) p_instance_ctrl->cmd_tx_buff, "AT+TRTC=", sizeof(p_instance_ctrl->cmd_tx_buff)); + snprintf((char *) p_instance_ctrl->cmd_tx_buff + strlen((char *) p_instance_ctrl->cmd_tx_buff), + sizeof(p_instance_ctrl->cmd_tx_buff), "%d.%d.%d.%d,%d\r\n", (uint8_t) (ipaddr >> 24), + (uint8_t) (ipaddr >> 16), + (uint8_t) (ipaddr >> 8), (uint8_t) (ipaddr), (int) port); + + ret = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + (char *) p_instance_ctrl->cmd_tx_buff, + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_5SEC, + WIFI_ONCHIP_DA16200_DELAY_500MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + FSP_ERROR_RETURN(FSP_SUCCESS == ret, FSP_ERR_WIFI_FAILED); + + p_instance_ctrl->sockets[socket_no].remote_ipaddr[0] = (uint8_t) (ipaddr >> 24); + p_instance_ctrl->sockets[socket_no].remote_ipaddr[1] = (uint8_t) (ipaddr >> 16); + p_instance_ctrl->sockets[socket_no].remote_ipaddr[2] = (uint8_t) (ipaddr >> 8); + p_instance_ctrl->sockets[socket_no].remote_ipaddr[3] = (uint8_t) (ipaddr); + p_instance_ctrl->sockets[socket_no].remote_port = (int) port; + p_instance_ctrl->sockets[socket_no].socket_status = WIFI_ONCHIP_DA16200_SOCKET_STATUS_CONNECTED; + p_instance_ctrl->sockets[socket_no].socket_read_write_flag = WIFI_ONCHIP_DA16200_SOCKET_READ | + WIFI_ONCHIP_DA16200_SOCKET_WRITE; + p_instance_ctrl->sockets[socket_no].socket_recv_state = WIFI_ONCHIP_DA16200_RECV_PREFIX; + p_instance_ctrl->sockets[socket_no].socket_create_flag = 1; + + return ret; +} + +/*********************************************************************************************************************** + * Send data over TCP to a server. + * + * @param[in] socket_no Socket ID number. + * @param[in] p_data Pointer to data to send. + * @param[in] length Length of data to send. + * @param[in] timeout_ms Timeout to wait for transmit end event + * + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_ASSERTION The p_instance_ctrl or parameter p_data is NULL. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + **********************************************************************************************************************/ +int32_t rm_wifi_onchip_da16200_send (uint32_t socket_no, const uint8_t * p_data, uint32_t length, uint32_t timeout_ms) +{ + uint32_t sent_count = 0; + uint32_t tx_length; + fsp_err_t ret; + uint32_t mutex_flag; + int header_len; + + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_data); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(WIFI_ONCHIP_DA16200_CFG_CMD_TX_BUF_SIZE > length, FSP_ERR_INVALID_ARGUMENT); +#endif + + /* If socket write has been disabled by shutdown call then return 0 bytes sent */ + if (!(p_instance_ctrl->sockets[socket_no].socket_read_write_flag & WIFI_ONCHIP_DA16200_SOCKET_WRITE)) + { + return 0; + } + + if ((0 == p_instance_ctrl->sockets[socket_no].socket_create_flag) || + (WIFI_ONCHIP_DA16200_SOCKET_STATUS_CONNECTED != p_instance_ctrl->sockets[socket_no].socket_status)) + { + return FSP_ERR_WIFI_FAILED; + } + + mutex_flag = WIFI_ONCHIP_DA16200_MUTEX_TX; + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + if (socket_no != p_instance_ctrl->curr_socket_index) + { + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return FSP_ERR_WIFI_FAILED; + } + + memset(p_instance_ctrl->cmd_rx_buff, 0, sizeof(p_instance_ctrl->cmd_rx_buff)); + +#define DATA_IP_MODE "\x1B" + + while (sent_count < length) + { + /* Put the DA16200 module into data input mode */ + header_len = snprintf((char *) p_instance_ctrl->cmd_tx_buff, + sizeof(p_instance_ctrl->cmd_tx_buff), + "%s%s%d%d,%d.%d.%d.%d,%d,%s,", + DATA_IP_MODE, + "S", + p_instance_ctrl->sockets[socket_no].socket_type, + (int) length, + p_instance_ctrl->sockets[socket_no].remote_ipaddr[0], + p_instance_ctrl->sockets[socket_no].remote_ipaddr[1], + p_instance_ctrl->sockets[socket_no].remote_ipaddr[2], + p_instance_ctrl->sockets[socket_no].remote_ipaddr[3], + p_instance_ctrl->sockets[socket_no].remote_port, + "r"); + + if (length - sent_count > (uint32_t) (WIFI_ONCHIP_DA16200_CFG_CMD_TX_BUF_SIZE - header_len)) + { + tx_length = (uint32_t) (WIFI_ONCHIP_DA16200_CFG_CMD_TX_BUF_SIZE - header_len); + } + else + { + tx_length = length - sent_count; + } + + /* Send data through a socket */ + memcpy((char *) p_instance_ctrl->cmd_tx_buff + strlen((char *) p_instance_ctrl->cmd_tx_buff), + (char *) p_data, + tx_length); + + ret = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + (char *) p_instance_ctrl->cmd_tx_buff, + tx_length + (uint32_t) header_len, + timeout_ms, + WIFI_ONCHIP_DA16200_DELAY_500MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + if (FSP_SUCCESS != ret) + { + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + } + + FSP_ERROR_RETURN(FSP_SUCCESS == ret, FSP_ERR_WIFI_FAILED); + + sent_count += tx_length; + p_data = p_data + sent_count; + } + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return (int32_t) sent_count; +} + +/*******************************************************************************************************************//** + * Receive data over TCP from a server. + * + * @param[in] socket_no Socket ID number. + * @param[out] p_data Pointer to data received from socket. + * @param[in] length Length of data array used for receive. + * @param[in] timeout_ms Timeout to wait for data to be received from socket. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_ASSERTION The p_instance_ctrl or parameter p_data is NULL. + **********************************************************************************************************************/ +int32_t rm_wifi_onchip_da16200_recv (uint32_t socket_no, uint8_t * p_data, uint32_t length, uint32_t timeout_ms) +{ + uint32_t mutex_flag; + uint32_t recvcnt = 0; + int32_t ret = 0; + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_data); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(0 != length, FSP_ERR_INVALID_ARGUMENT); +#endif + + /* if socket read has been disabled by shutdown call then return 0 bytes received. */ + if (!(p_instance_ctrl->sockets[socket_no].socket_read_write_flag & WIFI_ONCHIP_DA16200_SOCKET_READ)) + { + return 0; + } + + /* Take the receive mutex */ + mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_RX); + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + if (0 == p_instance_ctrl->sockets[socket_no].socket_create_flag) + { + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return FSP_ERR_WIFI_FAILED; + } + + if (socket_no != p_instance_ctrl->curr_socket_index) + { + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return WIFI_ONCHIP_DA16200_ERR_UNKNOWN; + } + + volatile size_t xReceivedBytes = + xStreamBufferReceiveAlt(p_instance_ctrl->sockets[socket_no].socket_byteq_hdl, + (p_data + recvcnt), + 1, + pdMS_TO_TICKS(timeout_ms)); + if (xReceivedBytes == 1) + { + recvcnt++; + + /* Get the rest of the transmitted data from the stream buffer */ + for (uint32_t i = 0; i < length; i++) + { + uint32_t num_bytes_left = length - recvcnt; + + if (0 == num_bytes_left) + { + ret = (int32_t) recvcnt; + break; + } + + xStreamBufferSetTriggerLevel(p_instance_ctrl->sockets[socket_no].socket_byteq_hdl, num_bytes_left); + xReceivedBytes = + xStreamBufferReceiveAlt(p_instance_ctrl->sockets[socket_no].socket_byteq_hdl, + (p_data + recvcnt), + num_bytes_left, + pdMS_TO_TICKS(WIFI_ONCHIP_DA16200_TIMEOUT_500MS)); + if (xReceivedBytes > 0) + { + recvcnt += xReceivedBytes; + } + else + { + ret = (int32_t) recvcnt; + break; + } + } /* For */ + } + else + { + ret = 0; // Timeout occurred + } + + /* Reset the trigger level for socket stream buffer */ + xStreamBufferSetTriggerLevel(p_instance_ctrl->sockets[socket_no].socket_byteq_hdl, 1); + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return ret; +} + +/*******************************************************************************************************************//** + * Disconnect a specific socket connection. + * + * @param[in] socket_no Socket ID to disconnect + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_ASSERTION The p_instance_ctrl is NULL. + * @retval FSP_ERR_NOT_OPEN The instance has not been opened. + * @retval FSP_ERR_INVALID_ARGUMENT Bad parameter value was passed into function. + **********************************************************************************************************************/ +fsp_err_t rm_wifi_onchip_da16200_socket_disconnect (uint32_t socket_no) +{ + fsp_err_t ret = FSP_ERR_WIFI_FAILED; + uint32_t mutex_flag; + + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + /* Test if socket has been created for socket index passed in to function */ + if (1 == p_instance_ctrl->sockets[socket_no].socket_create_flag) + { + mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_TX | WIFI_ONCHIP_DA16200_MUTEX_RX); + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + // NOLINT(clang-analyzer-security.insecureAPI.strchr) Disable warning about use of strcpy + strncpy((char *) p_instance_ctrl->cmd_tx_buff, "AT+TRTRM=", sizeof(p_instance_ctrl->cmd_tx_buff)); + snprintf((char *) p_instance_ctrl->cmd_tx_buff + strlen((char *) p_instance_ctrl->cmd_tx_buff), + sizeof(p_instance_ctrl->cmd_tx_buff), "%d\r", p_instance_ctrl->sockets[socket_no].socket_type); + + ret = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + (char *) p_instance_ctrl->cmd_tx_buff, + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_2SEC, + WIFI_ONCHIP_DA16200_DELAY_500MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + FSP_ERROR_RETURN(FSP_SUCCESS == ret, FSP_ERR_WIFI_FAILED); + + /* Clear the create flag, set status to closed, and flush the stream buffer */ + if (FSP_SUCCESS == ret) + { + p_instance_ctrl->sockets[socket_no].socket_create_flag = 0; + p_instance_ctrl->sockets[socket_no].socket_status = WIFI_ONCHIP_DA16200_SOCKET_STATUS_CLOSED; + p_instance_ctrl->sockets[socket_no].socket_read_write_flag = 0; + + BaseType_t rst_status = xStreamBufferReset(p_instance_ctrl->sockets[socket_no].socket_byteq_hdl); + if (pdPASS != rst_status) + { + return FSP_ERR_WIFI_FAILED; + } + } + } + + return ret; +} + +#if (1 == WIFI_ONCHIP_DA16200_CFG_SNTP_ENABLE) + +/*******************************************************************************************************************//** + * Initialize DA16200 module SNTP client service. + * + * @param[in] p_instance_ctrl Pointer to array holding URL to query from DNS. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_INVALID_ARGUMENT Parameter passed into function was invalid. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +static fsp_err_t rm_wifi_onchip_da16200_sntp_service_init (wifi_onchip_da16200_instance_ctrl_t * const p_instance_ctrl) +{ + fsp_err_t err = FSP_ERR_INTERNAL; + uint8_t ip_address_sntp_server[4] = {0, 0, 0, 0}; + int32_t err_scan; + + /* Set the SNTP server IP address */ + err_scan = + + // NOLINTNEXTLINE(cert-err34-c) Disable warning about the use of sscanf + sscanf((const char *) p_instance_ctrl->p_wifi_onchip_da16200_cfg->sntp_server_ip, + "%u.%u.%u.%u,", + (unsigned int *) &ip_address_sntp_server[0], + (unsigned int *) &ip_address_sntp_server[1], + (unsigned int *) &ip_address_sntp_server[2], + (unsigned int *) &ip_address_sntp_server[3]); + if (4 == err_scan) + { + /* Configure the SNTP Server Address */ + err = RM_WIFI_ONCHIP_DA16200_SntpServerIpAddressSet((uint8_t *) ip_address_sntp_server); + } + + if (FSP_SUCCESS == err) + { + /* Enable/disable the SNTP clinet */ + err = RM_WIFI_ONCHIP_DA16200_SntpEnableSet(WIFI_ONCHIP_DA16200_SNTP_ENABLE); + } + + /* Set the SNTP Timezone configuration string */ + if (FSP_SUCCESS == err) + { + err = RM_WIFI_ONCHIP_DA16200_SntpTimeZoneSet( + p_instance_ctrl->p_wifi_onchip_da16200_cfg->sntp_utc_offset_in_hours, + 0, + WIFI_ONCHIP_DA16200_SNTP_DAYLIGHT_SAVINGS_DISABLE); + } + + return err; +} + +#endif + +/*! \endcond */ + +/*******************************************************************************************************************//** + * @addtogroup WIFI_ONCHIP_DA16200 WIFI_ONCHIP_DA16200 + * @{ + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Set the SNTP Client Server IP Address + * + * @param[in] p_server_ip_addr Pointer to IP address of SNTP server in byte array format. + * + * @retval FSP_SUCCESS Successfully set the value. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_ASSERTION The parameter p_server_ip_addr is NULL. + **********************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_DA16200_SntpServerIpAddressSet (uint8_t * p_server_ip_addr) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t mutex_flag; + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_server_ip_addr); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_TX | WIFI_ONCHIP_DA16200_MUTEX_RX); + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + // NOLINT(clang-analyzer-security.insecureAPI.strchr) Disable warning about use of strcpy + strncpy((char *) p_instance_ctrl->cmd_tx_buff, "AT+NWSNS=", sizeof(p_instance_ctrl->cmd_tx_buff)); + + snprintf((char *) p_instance_ctrl->cmd_tx_buff + strlen((char *) p_instance_ctrl->cmd_tx_buff), + sizeof(p_instance_ctrl->cmd_tx_buff), "%u.%u.%u.%u\r\n", p_server_ip_addr[0], p_server_ip_addr[1], + p_server_ip_addr[2], p_server_ip_addr[3]); + + err = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + (char *) p_instance_ctrl->cmd_tx_buff, + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_400MS, + WIFI_ONCHIP_DA16200_DELAY_500MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return err; +} + +/*******************************************************************************************************************//** + * Set the SNTP Client to Enable or Disable + * + * @param[in] enable Flag to indicate enable/disable for SNTP support. + * + * @retval FSP_SUCCESS Successfully set the value. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_NOT_OPEN Module is not open. + **********************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_DA16200_SntpEnableSet (wifi_onchip_da16200_sntp_enable_t enable) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t mutex_flag; + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); +#endif + + mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_TX | WIFI_ONCHIP_DA16200_MUTEX_RX); + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + if (WIFI_ONCHIP_DA16200_SNTP_ENABLE == enable) + { + // NOLINT(clang-analyzer-security.insecureAPI.strchr) Disable warning about use of strcpy + strncpy((char *) p_instance_ctrl->cmd_tx_buff, "AT+NWSNTP=1\r\n", sizeof(p_instance_ctrl->cmd_tx_buff)); + + err = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + (char *) p_instance_ctrl->cmd_tx_buff, + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_400MS, + WIFI_ONCHIP_DA16200_DELAY_500MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + p_instance_ctrl->is_sntp_enabled = true; + } + else + { + // NOLINT(clang-analyzer-security.insecureAPI.strchr) Disable warning about use of strcpy + strncpy((char *) p_instance_ctrl->cmd_tx_buff, "AT+NWSNTP=0\r\n", sizeof(p_instance_ctrl->cmd_tx_buff)); + err = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + (char *) p_instance_ctrl->cmd_tx_buff, + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_400MS, + WIFI_ONCHIP_DA16200_DELAY_500MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + p_instance_ctrl->is_sntp_enabled = false; + } + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return err; +} + +/*******************************************************************************************************************//** + * Set the SNTP Client Timezone + * + * @param[in] utc_offset_in_hours Timezone in UTC offset in hours + * @param[in] minutes Number of minutes used for timezone offset from GMT. + * @param[in] daylightSavingsEnable Enable/Disable daylight saving in the timezone calculation. + * + * @retval FSP_SUCCESS Successfully set the value. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_ARGUMENT Parameter passed into function was invalid. + **********************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_DA16200_SntpTimeZoneSet ( + int utc_offset_in_hours, + uint32_t minutes, + wifi_onchip_da16200_sntp_daylight_savings_enable_t daylightSavingsEnable) +{ + fsp_err_t err = FSP_SUCCESS; + uint32_t mutex_flag; + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(((utc_offset_in_hours >= -12) && (utc_offset_in_hours <= 12)), FSP_ERR_INVALID_ARGUMENT); + FSP_ERROR_RETURN((0 == minutes) && (0 == daylightSavingsEnable), FSP_ERR_INVALID_ARGUMENT); +#endif + + mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_TX | WIFI_ONCHIP_DA16200_MUTEX_RX); + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + int utc_offset_in_secs = (utc_offset_in_hours * HOURS_IN_SECONDS); + snprintf((char *) p_instance_ctrl->cmd_tx_buff, + sizeof(p_instance_ctrl->cmd_tx_buff), + "AT+TZONE=%d\r", + utc_offset_in_secs); + + err = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + (char *) p_instance_ctrl->cmd_tx_buff, + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_400MS, + WIFI_ONCHIP_DA16200_DELAY_200MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + FSP_PARAMETER_NOT_USED(minutes); + FSP_PARAMETER_NOT_USED(daylightSavingsEnable); + + return err; +} + +/*******************************************************************************************************************//** + * Get the current local time based on current timezone in a string . Exp: YYYY-MM-DD,HOUR:MIN:SECS + * + * @param[out] p_local_time Returns local time in string format. + * @param[in] size_string Size of p_local_time string buffer.The size of this string needs to be at least 25 bytes + * + * @retval FSP_SUCCESS Successfully returned the local time string. + * @retval FSP_ERR_ASSERTION The parameter local_time or p_instance_ctrl is NULL. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_NOT_OPEN Module is not open. + * @retval FSP_ERR_INVALID_SIZE String size value passed in exceeds maximum. + **********************************************************************************************************************/ +fsp_err_t RM_WIFI_ONCHIP_DA16200_LocalTimeGet (uint8_t * p_local_time, uint32_t size_string) +{ + uint32_t mutex_flag; + fsp_err_t ret; + + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + char * p_str = (char *) p_instance_ctrl->cmd_rx_buff; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_local_time); + FSP_ERROR_RETURN(WIFI_OPEN == p_instance_ctrl->open, FSP_ERR_NOT_OPEN); + FSP_ERROR_RETURN(WIFI_ONCHIP_DA16200_LOCAL_TIME_STR_SIZE <= size_string, FSP_ERR_INVALID_SIZE); + FSP_ERROR_RETURN(p_instance_ctrl->is_sntp_enabled == true, FSP_ERR_WIFI_FAILED); +#endif + + /* Take mutexes */ + mutex_flag = (WIFI_ONCHIP_DA16200_MUTEX_TX | WIFI_ONCHIP_DA16200_MUTEX_RX); + FSP_ERROR_RETURN(pdTRUE == rm_wifi_onchip_da16200_send_basic_take_mutex(p_instance_ctrl, mutex_flag), + FSP_ERR_WIFI_FAILED); + + memset(p_local_time, 0, size_string); + memset((char *) p_instance_ctrl->cmd_rx_buff, 0, sizeof(p_instance_ctrl->cmd_rx_buff)); + + ret = rm_wifi_onchip_da16200_send_basic(p_instance_ctrl, + p_instance_ctrl->curr_cmd_port, + "AT+TIME=?\r", + 0, + WIFI_ONCHIP_DA16200_TIMEOUT_2SEC, + WIFI_ONCHIP_DA16200_DELAY_1000MS, + WIFI_ONCHIP_DA16200_RETURN_TEXT_OK); + if (FSP_SUCCESS == ret) + { + /* Parse the response */ + p_str = strstr(p_str, "+TIME:"); + FSP_ERROR_RETURN(NULL != p_str, FSP_ERR_WIFI_FAILED); + + p_str = p_str + strlen("+TIME:"); + + /* Copy SSID from scan info buffer */ + uint32_t idx = 0; + while ((*p_str != '\r') && (idx < (size_string - 1))) + { + p_local_time[idx++] = (uint8_t) *p_str; + p_str++; + } + } + + rm_wifi_onchip_da16200_send_basic_give_mutex(p_instance_ctrl, mutex_flag); + + return ret; +} + +/*******************************************************************************************************************//** + * @} (end addtogroup WIFI_ONCHIP_DA16200) + **********************************************************************************************************************/ + +/*! \cond PRIVATE */ + +/*********************************************************************************************************************** + * Local Functions definitions + **********************************************************************************************************************/ + +/*******************************************************************************************************************//** + * Handles incoming socket data. + * + * @param[in] pSocket Pointer to socket instance structure. + * @param[in] data_byte Incoming data in byte + * + **********************************************************************************************************************/ +static void rm_wifi_da16200_handle_incoming_socket_data (da16200_socket_t * pSocket, uint8_t data_byte) +{ + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + da16200_socket_t * p_socket = pSocket; + BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialized to pdFALSE. + + switch (p_socket->socket_recv_state) + { + case WIFI_ONCHIP_DA16200_RECV_PREFIX: + { + if ('+' == data_byte) + { + p_socket->socket_recv_state = WIFI_ONCHIP_DA16200_RECV_CMD; + rx_data_index = 0; + } + else + { + xStreamBufferSendFromISR(p_instance_ctrl->socket_byteq_hdl, &data_byte, 1, &xHigherPriorityTaskWoken); + } + + break; + } + + case WIFI_ONCHIP_DA16200_RECV_CMD: + { + rx_buffer[rx_data_index++] = data_byte; + rx_data_index = (rx_data_index) % WIFI_ONCHIP_DA16200_TEMP_BUFFER_SIZE; + + if (5 == rx_data_index) + { + /* Check for incoming data through socket */ + if (0 == strncmp("TRDTC", (char *) rx_buffer, strlen("TRDTC"))) + { + p_socket->socket_recv_state = WIFI_ONCHIP_DA16200_RECV_SUFFIX; + } + /* Check for TCP socket disconnect notification */ + else if (0 == strncmp("TRXTC", (char *) rx_buffer, strlen("TRXTC"))) + { + p_socket->socket_recv_state = WIFI_ONCHIP_DA16200_RECV_PREFIX; + + /* Socket disconnect event received */ + p_instance_ctrl->sockets[p_instance_ctrl->curr_socket_index].socket_create_flag = 0; + p_instance_ctrl->sockets[p_instance_ctrl->curr_socket_index].socket_status = + WIFI_ONCHIP_DA16200_SOCKET_STATUS_CLOSED; + p_instance_ctrl->sockets[p_instance_ctrl->curr_socket_index].socket_read_write_flag = 0; + } + else + { + p_socket->socket_recv_state = WIFI_ONCHIP_DA16200_RECV_PREFIX; + } + } + + break; + } + + case WIFI_ONCHIP_DA16200_RECV_SUFFIX: + { + if (':' == data_byte) + { + p_socket->socket_recv_state = WIFI_ONCHIP_DA16200_RECV_PARAM_CID; + } + + break; + } + + case WIFI_ONCHIP_DA16200_RECV_PARAM_CID: + { + if (',' == data_byte) + { + p_socket->socket_recv_state = WIFI_ONCHIP_DA16200_RECV_PARAM_IP; + rx_data_index = 0; + } + + break; + } + + case WIFI_ONCHIP_DA16200_RECV_PARAM_IP: + { + if (',' == data_byte) + { + p_socket->socket_recv_state = WIFI_ONCHIP_DA16200_RECV_PARAM_PORT; + rx_data_index = 0; + } + + break; + } + + case WIFI_ONCHIP_DA16200_RECV_PARAM_PORT: + { + if (',' == data_byte) + { + p_socket->socket_recv_state = WIFI_ONCHIP_DA16200_RECV_PARAM_LEN; + rx_data_index = 0; + } + + break; + } + + case WIFI_ONCHIP_DA16200_RECV_PARAM_LEN: + { + if (',' == data_byte) + { + p_socket->socket_recv_data_len = strtol((char *) rx_buffer, NULL, 10); + p_socket->socket_recv_state = WIFI_ONCHIP_DA16200_RECV_DATA; + rx_data_index = 0; + } + else + { + rx_buffer[rx_data_index++] = data_byte; + rx_data_index = (rx_data_index) % WIFI_ONCHIP_DA16200_TEMP_BUFFER_SIZE; + } + + break; + } + + case WIFI_ONCHIP_DA16200_RECV_DATA: + { + if (0 < p_socket->socket_recv_data_len--) + { + xStreamBufferSendFromISR(p_instance_ctrl->sockets[p_instance_ctrl->curr_socket_index].socket_byteq_hdl, + &data_byte, + 1, + &xHigherPriorityTaskWoken); + } + + if (0 >= p_socket->socket_recv_data_len) + { + p_socket->socket_recv_state = WIFI_ONCHIP_DA16200_RECV_PREFIX; + } + + break; + } + } +} + +/*******************************************************************************************************************//** + * UART Callback routine. + * + * @param[in] p_args Pointer to uart callback structure. + * + **********************************************************************************************************************/ +void rm_wifi_onchip_da16200_uart_callback (uart_callback_args_t * p_args) +{ + BaseType_t xHigherPriorityTaskWoken = pdFALSE; // Initialized to pdFALSE. + + wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl = &g_rm_wifi_onchip_da16200_instance; + volatile uint32_t uart_context_index = 0; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + if (NULL == p_args) + { + return; + } +#endif + + if ((NULL != p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_DA16200_UART_SECOND_PORT]) && + (p_args->channel == + p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_DA16200_UART_SECOND_PORT]->p_cfg->channel)) + { + uart_context_index = 1; + } + + switch (p_args->event) + { + case UART_EVENT_RX_CHAR: + { + uint8_t data_byte = (uint8_t) p_args->data; + + if (uart_context_index == WIFI_ONCHIP_DA16200_UART_INITIAL_PORT) + { + if (0 == p_instance_ctrl->sockets[p_instance_ctrl->curr_socket_index].socket_create_flag) + { + xStreamBufferSendFromISR(p_instance_ctrl->socket_byteq_hdl, &data_byte, 1, + &xHigherPriorityTaskWoken); + } + else // socket data mode + { + rm_wifi_da16200_handle_incoming_socket_data(&p_instance_ctrl->sockets[p_instance_ctrl-> + curr_socket_index], + data_byte); + } + } + else if (uart_context_index == WIFI_ONCHIP_DA16200_UART_SECOND_PORT) + { + xStreamBufferSendFromISR(p_instance_ctrl->socket_byteq_hdl, &data_byte, 1, &xHigherPriorityTaskWoken); + } + else + { + /* Do Nothing */ + } + + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + break; + } + + case UART_EVENT_TX_DATA_EMPTY: + { + if ((0 == uxQueueMessagesWaitingFromISR((QueueHandle_t) p_instance_ctrl->uart_tei_sem[uart_context_index]))) + { + xSemaphoreGiveFromISR(p_instance_ctrl->uart_tei_sem[uart_context_index], &xHigherPriorityTaskWoken); + } + + portYIELD_FROM_ISR(xHigherPriorityTaskWoken); + break; + } + + default: + { + /* Do Nothing */ + } + } +} + +/*******************************************************************************************************************//** + * Clean up the DA16200 instance. + * + * @param[in] p_instance_ctrl Pointer to DA16200 instance structure. + * + **********************************************************************************************************************/ +static void rm_wifi_onchip_da16200_cleanup_open (wifi_onchip_da16200_instance_ctrl_t * const p_instance_ctrl) +{ + /* Delete the semaphores */ + if (NULL != p_instance_ctrl->tx_sem) + { + vSemaphoreDelete(p_instance_ctrl->tx_sem); + p_instance_ctrl->tx_sem = NULL; + } + + if (NULL != p_instance_ctrl->rx_sem) + { + vSemaphoreDelete(p_instance_ctrl->rx_sem); + p_instance_ctrl->rx_sem = NULL; + } + + /* Delete the command channel stream buffer */ + if (NULL != p_instance_ctrl->socket_byteq_hdl) + { + vStreamBufferDelete(p_instance_ctrl->socket_byteq_hdl); + p_instance_ctrl->socket_byteq_hdl = NULL; + } + + if (NULL != p_instance_ctrl->uart_tei_sem[WIFI_ONCHIP_DA16200_UART_INITIAL_PORT]) + { + vSemaphoreDelete(p_instance_ctrl->uart_tei_sem[WIFI_ONCHIP_DA16200_UART_INITIAL_PORT]); + p_instance_ctrl->uart_tei_sem[WIFI_ONCHIP_DA16200_UART_INITIAL_PORT] = NULL; + } + + if (p_instance_ctrl->num_uarts > 1) + { + if (NULL != p_instance_ctrl->uart_tei_sem[WIFI_ONCHIP_DA16200_UART_SECOND_PORT]) + { + vSemaphoreDelete(p_instance_ctrl->uart_tei_sem[WIFI_ONCHIP_DA16200_UART_SECOND_PORT]); + p_instance_ctrl->uart_tei_sem[WIFI_ONCHIP_DA16200_UART_SECOND_PORT] = NULL; + } + } + + uart_instance_t * p_uart = p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_DA16200_UART_INITIAL_PORT]; + if (SCIU_OPEN == ((rm_wifi_onchip_da16200_uart_instance_ctrl_t *) p_uart->p_ctrl)->open) + { + p_uart->p_api->close(p_uart->p_ctrl); + } + + p_uart = p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_DA16200_UART_SECOND_PORT]; + if (SCIU_OPEN == ((rm_wifi_onchip_da16200_uart_instance_ctrl_t *) p_uart->p_ctrl)->open) + { + p_uart->p_api->close(p_uart->p_ctrl); + } +} + +/*******************************************************************************************************************//** + * Resets the DA16200 module. + * + * @param[in] p_instance_ctrl Pointer to DA16200 instance structure. + * + **********************************************************************************************************************/ +static void rm_wifi_onchip_da16200_wifi_module_reset (wifi_onchip_da16200_instance_ctrl_t * const p_instance_ctrl) +{ + /* Reset the wifi module */ + g_ioport.p_api->pinWrite(g_ioport.p_ctrl, p_instance_ctrl->reset_pin, BSP_IO_LEVEL_LOW); + + vTaskDelay(pdMS_TO_TICKS(WIFI_ONCHIP_DA16200_TIMEOUT_20MS)); + + g_ioport.p_api->pinWrite(g_ioport.p_ctrl, p_instance_ctrl->reset_pin, BSP_IO_LEVEL_HIGH); + + vTaskDelay(pdMS_TO_TICKS(WIFI_ONCHIP_DA16200_TIMEOUT_1MS)); +} + +/*******************************************************************************************************************//** + * Give the mutex for the send basic call. + * + * @param[in] p_instance_ctrl Pointer to control instance. + * @param[in] mutex_flag Flags for the mutex. + * + * @retval pdTrue Function completed successfully. + **********************************************************************************************************************/ +static BaseType_t rm_wifi_onchip_da16200_send_basic_give_mutex (wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl, + uint32_t mutex_flag) +{ + BaseType_t volatile xSemRet = pdFALSE; + + if (0 != (mutex_flag & WIFI_ONCHIP_DA16200_MUTEX_RX)) + { + xSemRet = xSemaphoreGive(p_instance_ctrl->rx_sem); + if (xSemRet != pdTRUE) + { + return pdFALSE; + } + } + + if (0 != (mutex_flag & WIFI_ONCHIP_DA16200_MUTEX_TX)) + { + xSemRet = xSemaphoreGive(p_instance_ctrl->tx_sem); + if (xSemRet != pdTRUE) + { + return pdFALSE; + } + } + + return xSemRet; +} + +/*******************************************************************************************************************//** + * Take the mutex for the send basic call. + * + * @param[in] p_instance_ctrl Pointer to control instance. + * @param[in] mutex_flag Flags for the mutex. + * + * @retval pdTrue Function completed successfully. + **********************************************************************************************************************/ +static BaseType_t rm_wifi_onchip_da16200_send_basic_take_mutex (wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl, + uint32_t mutex_flag) +{ + BaseType_t volatile xSemRet = pdFALSE; + + if (0 != (mutex_flag & WIFI_ONCHIP_DA16200_MUTEX_TX)) + { + if (NULL != p_instance_ctrl->tx_sem) + { + xSemRet = + xSemaphoreTake(p_instance_ctrl->tx_sem, + (wifi_sx_wifi_onchip_da16200_sem_block_timeout / portTICK_PERIOD_MS)); + if (xSemRet != pdTRUE) + { + return pdFALSE; + } + } + } + + if (0 != (mutex_flag & WIFI_ONCHIP_DA16200_MUTEX_RX)) + { + if (NULL != p_instance_ctrl->rx_sem) + { + xSemRet = + xSemaphoreTake(p_instance_ctrl->rx_sem, + (wifi_sx_wifi_onchip_da16200_sem_block_timeout / portTICK_PERIOD_MS)); + if (xSemRet != pdTRUE) + { + if (0 != (mutex_flag & WIFI_ONCHIP_DA16200_MUTEX_TX)) + { + xSemaphoreGive(p_instance_ctrl->tx_sem); + } + + return pdFALSE; + } + } + } + + return xSemRet; +} + +/*******************************************************************************************************************//** + * Send and receive an AT command with testing for return. + * + * @param[in] p_instance_ctrl Pointer to array holding URL to query from DNS. + * @param[in] serial_ch_id Pointer to IP address returned from look up. + * @param[in] p_textstring Pointer to IP address returned from look up. + * @param[in] length length of data to be send. + * @param[in] timeout_ms Pointer to IP address returned from look up. + * @param[in] retry_delay retry delay in milliseconds + * @param[in] p_expect_code Pointer containing AT command response. + * + * @retval FSP_SUCCESS Function completed successfully. + * @retval FSP_ERR_WIFI_FAILED Error occurred with command to Wifi module. + * @retval FSP_ERR_ASSERTION Assertion error occurred. + * @retval FSP_ERR_INVALID_DATA Accuracy of data is not guaranteed + **********************************************************************************************************************/ +static fsp_err_t rm_wifi_onchip_da16200_send_basic (wifi_onchip_da16200_instance_ctrl_t * p_instance_ctrl, + uint32_t serial_ch_id, + const char * p_textstring, + uint32_t length, + uint32_t timeout_ms, + uint32_t retry_delay, + const char * p_expect_code) +{ + fsp_err_t err = FSP_SUCCESS; + volatile uint8_t retry_count = 0U; + uint32_t recvcnt = 0; + char * ret = NULL; + +#if (WIFI_ONCHIP_DA16200_CFG_PARAM_CHECKING_ENABLED == 1) + FSP_ASSERT(NULL != p_textstring); +#endif + + memset(p_instance_ctrl->cmd_rx_buff, 0, sizeof(p_instance_ctrl->cmd_rx_buff)); + + if (p_textstring != NULL) + { + recvcnt = 0; + + if (uxQueueMessagesWaiting((QueueHandle_t) p_instance_ctrl->uart_tei_sem[serial_ch_id]) != 0) + { + return FSP_ERR_WIFI_FAILED; + } + + if (0 == length) + { + err = + p_instance_ctrl->uart_instance_objects[serial_ch_id]->p_api->write(p_instance_ctrl->uart_instance_objects[ + serial_ch_id]->p_ctrl, + (uint8_t *) p_textstring, + strlen( + p_textstring)); + } + else + { + err = + p_instance_ctrl->uart_instance_objects[serial_ch_id]->p_api->write(p_instance_ctrl->uart_instance_objects[ + serial_ch_id]->p_ctrl, + (uint8_t *) p_textstring, + length); + } + + FSP_ERROR_RETURN(FSP_SUCCESS == err, FSP_ERR_WIFI_FAILED); + + FSP_ERROR_RETURN(pdTRUE == + xSemaphoreTake(p_instance_ctrl->uart_tei_sem[serial_ch_id], (timeout_ms / portTICK_PERIOD_MS)), + FSP_ERR_WIFI_FAILED); + } + + for (retry_count = 0; retry_count < WIFI_ONCHIP_DA16200_CFG_MAX_RETRIES_UART_COMMS; retry_count++) + { + if (NULL != p_expect_code) + { + /* Get the transmitted message from the stream buffer */ + xStreamBufferSetTriggerLevel(p_instance_ctrl->socket_byteq_hdl, sizeof(p_instance_ctrl->cmd_rx_buff)); + + size_t xReceivedBytes = xStreamBufferReceiveAlt(p_instance_ctrl->socket_byteq_hdl, + &p_instance_ctrl->cmd_rx_buff[recvcnt], + (int) sizeof(p_instance_ctrl->cmd_rx_buff), + pdMS_TO_TICKS(timeout_ms)); + + /* Response data check */ + if (xReceivedBytes > 0) + { + ret = strstr((char *) &p_instance_ctrl->cmd_rx_buff[0], p_expect_code); + if (ret == NULL) + { + R_BSP_SoftwareDelay(retry_delay, BSP_DELAY_UNITS_MILLISECONDS); + } + else + { + break; + } + } + else + { + R_BSP_SoftwareDelay(retry_delay, BSP_DELAY_UNITS_MILLISECONDS); + } + } + else + { + break; + } + } + + FSP_ERROR_RETURN(WIFI_ONCHIP_DA16200_CFG_MAX_RETRIES_UART_COMMS != (retry_count), FSP_ERR_WIFI_FAILED); + if (ret == NULL) + { + if (p_instance_ctrl->cmd_rx_buff[0] != 0) + { + err = rm_wifi_onchip_da16200_error_lookup((char *) p_instance_ctrl->cmd_rx_buff); + } + } + + return err; +} + +/*******************************************************************************************************************//** + * Parse the incoming DA16200 error code and translates into FSP error. + * + * @param[in] p_resp Pointer to response string. + * + * @retval FSP_ERR_WIFI_UNKNOWN_AT_CMD DA16200 Unknown AT command Error. + * @retval FSP_ERR_WIFI_INSUF_PARAM DA16200 Insufficient parameter. + * @retval FSP_ERR_WIFI_TOO_MANY_PARAMS DA16200 Too many parameters. + * @retval FSP_ERR_WIFI_INV_PARAM_VAL DA16200 Wrong parameter value. + * @retval FSP_ERR_UNSUPPORTED Selected mode not supported by this API. + * @retval FSP_ERR_WIFI_AP_NOT_CONNECTED DA16200 Not connected to an AP or Communication peer. + * @retval FSP_ERR_WIFI_NO_RESULT DA16200 No result. + * @retval FSP_ERR_WIFI_RSP_BUF_OVFLW DA16200 Response buffer overflow. + * @retval FSP_ERR_WIFI_FUNC_NOT_CONFIG DA16200 Function is not configured. + * @retval FSP_ERR_TIMEOUT Timeout error + * @retval FSP_ERR_WIFI_NVRAM_WR_FAIL DA16200 NVRAM write failure + * @retval FSP_ERR_WIFI_RET_MEM_WR_FAIL DA16200 Retention memory write failure + * @retval FSP_ERR_WIFI_UNKNOWN_ERR DA16200 unknown error + * @retval FSP_ERR_INVALID_DATA Accuracy of data is not guaranteed + * @retval FSP_ERR_INTERNAL Internal error + **********************************************************************************************************************/ +static fsp_err_t rm_wifi_onchip_da16200_error_lookup (char * p_resp) +{ + int8_t err_code; + int32_t scanf_ret; + fsp_err_t err = FSP_ERR_INTERNAL; + + // NOLINTNEXTLINE(cert-err34-c) Disable warning about the use of sscanf + scanf_ret = sscanf(p_resp, "\r\nERROR:%d\r\n", (int *) &err_code); + if (1 != scanf_ret) + { + return FSP_ERR_INVALID_DATA; + } + + switch (err_code) + { + case WIFI_ONCHIP_DA16200_ERR_UNKNOWN_CMD: + { + err = FSP_ERR_WIFI_UNKNOWN_AT_CMD; + break; + } + + case WIFI_ONCHIP_DA16200_ERR_INSUF_PARAMS: + { + err = FSP_ERR_WIFI_INSUF_PARAM; + break; + } + + case WIFI_ONCHIP_DA16200_ERR_TOO_MANY_PARAMS: + { + err = FSP_ERR_WIFI_TOO_MANY_PARAMS; + break; + } + + case WIFI_ONCHIP_DA16200_ERR_INVALID_PARAM: + { + err = FSP_ERR_WIFI_INV_PARAM_VAL; + break; + } + + case WIFI_ONCHIP_DA16200_ERR_UNSUPPORTED_FUN: + { + err = FSP_ERR_UNSUPPORTED; + break; + } + + case WIFI_ONCHIP_DA16200_ERR_NOT_CONNECTED_AP: + { + err = FSP_ERR_WIFI_AP_NOT_CONNECTED; + break; + } + + case WIFI_ONCHIP_DA16200_ERR_NO_RESULT: + { + err = FSP_ERR_WIFI_NO_RESULT; + break; + } + + case WIFI_ONCHIP_DA16200_ERR_RESP_BUF_OVERFLOW: + { + err = FSP_ERR_WIFI_RSP_BUF_OVFLW; + break; + } + + case WIFI_ONCHIP_DA16200_ERR_FUNC_NOT_CONFIG: + { + err = FSP_ERR_WIFI_FUNC_NOT_CONFIG; + break; + } + + case WIFI_ONCHIP_DA16200_ERR_CMD_TIMEOUT: + { + err = FSP_ERR_TIMEOUT; + break; + } + + case WIFI_ONCHIP_DA16200_ERR_NVRAM_WR_FAIL: + { + err = FSP_ERR_WIFI_NVRAM_WR_FAIL; + break; + } + + case WIFI_ONCHIP_DA16200_ERR_RETEN_MEM_WR_FAIL: + { + err = FSP_ERR_WIFI_RET_MEM_WR_FAIL; + break; + } + + case WIFI_ONCHIP_DA16200_ERR_UNKNOWN: + { + err = FSP_ERR_WIFI_UNKNOWN_ERR; + break; + } + } + + return err; +} + +/////////////////////////////////////////////////////////////////////////////// + +/* + * Alternate function for the StreamBufferReceive call. Allows for the byte + * triggering mechanism to work correctly. The alternate function does perform + * thread blocking when the trigger level has not been reached. + */ + +/////////////////////////////////////////////////////////////////////////////// +static size_t prvBytesInBuffer (const StreamBuffer_t * const pxStreamBuffer) +{ +/* Returns the distance between xTail and xHead. */ + size_t xCount; + + xCount = pxStreamBuffer->xLength + pxStreamBuffer->xHead; + xCount -= pxStreamBuffer->xTail; + if (xCount >= pxStreamBuffer->xLength) + { + xCount -= pxStreamBuffer->xLength; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xCount; +} + +static size_t prvReadBytesFromBuffer (StreamBuffer_t * pxStreamBuffer, + uint8_t * pucData, + size_t xMaxCount, + size_t xBytesAvailable) +{ + size_t xCount; + size_t xFirstLength; + size_t xNextTail; + + /* Use the minimum of the wanted bytes and the available bytes. */ + xCount = configMIN(xBytesAvailable, xMaxCount); + + if (xCount > (size_t) 0) + { + xNextTail = pxStreamBuffer->xTail; + + /* Calculate the number of bytes that can be read - which may be + * less than the number wanted if the data wraps around to the start of + * the buffer. */ + xFirstLength = configMIN(pxStreamBuffer->xLength - xNextTail, xCount); + + /* Obtain the number of bytes it is possible to obtain in the first + * read. Asserts check bounds of read and write. */ + configASSERT(xFirstLength <= xMaxCount); + configASSERT((xNextTail + xFirstLength) <= pxStreamBuffer->xLength); + (void) memcpy((void *) pucData, (const void *) &(pxStreamBuffer->pucBuffer[xNextTail]), xFirstLength); /*lint !e9087 memcpy() requires void *. */ + + /* If the total number of wanted bytes is greater than the number + * that could be read in the first read... */ + if (xCount > xFirstLength) + { + /*...then read the remaining bytes from the start of the buffer. */ + configASSERT(xCount <= xMaxCount); + (void) memcpy((void *) &(pucData[xFirstLength]), (void *) (pxStreamBuffer->pucBuffer), + xCount - xFirstLength); /*lint !e9087 memcpy() requires void *. */ + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + /* Move the tail pointer to effectively remove the data read from + * the buffer. */ + xNextTail += xCount; + + if (xNextTail >= pxStreamBuffer->xLength) + { + xNextTail -= pxStreamBuffer->xLength; + } + + pxStreamBuffer->xTail = xNextTail; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + + return xCount; +} + +static size_t prvReadMessageFromBuffer (StreamBuffer_t * pxStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + size_t xBytesAvailable, + size_t xBytesToStoreMessageLength) +{ + size_t xOriginalTail; + size_t xReceivedLength; + size_t xNextMessageLength; + configMESSAGE_BUFFER_LENGTH_TYPE xTempNextMessageLength; + + if (xBytesToStoreMessageLength != (size_t) 0) + { + /* A discrete message is being received. First receive the length + * of the message. A copy of the tail is stored so the buffer can be + * returned to its prior state if the length of the message is too + * large for the provided buffer. */ + xOriginalTail = pxStreamBuffer->xTail; + (void) prvReadBytesFromBuffer(pxStreamBuffer, + (uint8_t *) &xTempNextMessageLength, + xBytesToStoreMessageLength, + xBytesAvailable); + xNextMessageLength = xTempNextMessageLength; + + /* Reduce the number of bytes available by the number of bytes just + * read out. */ + xBytesAvailable -= xBytesToStoreMessageLength; + + /* Check there is enough space in the buffer provided by the + * user. */ + if (xNextMessageLength > xBufferLengthBytes) + { + /* The user has provided insufficient space to read the message + * so return the buffer to its previous state (so the length of + * the message is in the buffer again). */ + pxStreamBuffer->xTail = xOriginalTail; + xNextMessageLength = 0; + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + /* A stream of bytes is being received (as opposed to a discrete + * message), so read as many bytes as possible. */ + xNextMessageLength = xBufferLengthBytes; + } + + /* Read the actual data. */ + xReceivedLength = prvReadBytesFromBuffer(pxStreamBuffer, (uint8_t *) pvRxData, xNextMessageLength, xBytesAvailable); /*lint !e9079 Data storage area is implemented as uint8_t array for ease of sizing, indexing and alignment. */ + + return xReceivedLength; +} + +static size_t xStreamBufferReceiveAlt (StreamBufferHandle_t xStreamBuffer, + void * pvRxData, + size_t xBufferLengthBytes, + TickType_t xTicksToWait) +{ + StreamBuffer_t * const pxStreamBuffer = xStreamBuffer; + size_t xReceivedLength = 0; + size_t xBytesAvailable; + size_t xBytesToStoreMessageLength; + + configASSERT(pvRxData); + configASSERT(pxStreamBuffer); + + /* This receive function is used by both message buffers, which store + * discrete messages, and stream buffers, which store a continuous stream of + * bytes. Discrete messages include an additional + * sbBYTES_TO_STORE_MESSAGE_LENGTH bytes that hold the length of the + * message. */ + if ((pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER) != (uint8_t) 0) + { + xBytesToStoreMessageLength = sbBYTES_TO_STORE_MESSAGE_LENGTH; + } + else + { + /* if this is a stream buffer then set wait count to the trigger level */ + xBytesToStoreMessageLength = pxStreamBuffer->xTriggerLevelBytes; + } + + if (xTicksToWait != (TickType_t) 0) + { + /* Checking if there is data and clearing the notification state must be + * performed atomically. */ + taskENTER_CRITICAL(); + { + xBytesAvailable = prvBytesInBuffer(pxStreamBuffer); + + /* If this function was invoked by a message buffer read then + * xBytesToStoreMessageLength holds the number of bytes used to hold + * the length of the next discrete message. If this function was + * invoked by a stream buffer read then xBytesToStoreMessageLength will + * be 0. */ + if (xBytesAvailable <= xBytesToStoreMessageLength) + { + /* Clear notification state as going to wait for data. */ + (void) xTaskNotifyStateClear(NULL); + + /* Should only be one reader. */ + configASSERT(pxStreamBuffer->xTaskWaitingToReceive == NULL); + pxStreamBuffer->xTaskWaitingToReceive = xTaskGetCurrentTaskHandle(); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + taskEXIT_CRITICAL(); + + if (xBytesAvailable <= xBytesToStoreMessageLength) + { + /* Wait for data to be available. */ + traceBLOCKING_ON_STREAM_BUFFER_RECEIVE(xStreamBuffer); + (void) xTaskNotifyWait((uint32_t) 0, (uint32_t) 0, NULL, xTicksToWait); + pxStreamBuffer->xTaskWaitingToReceive = NULL; + + /* Recheck the data available after blocking. */ + xBytesAvailable = prvBytesInBuffer(pxStreamBuffer); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + xBytesAvailable = prvBytesInBuffer(pxStreamBuffer); + } + + /* Set bytes to store message to length to 0 if this is a stream buffer */ + /* since stream buffers have no byte count header. */ + if ((pxStreamBuffer->ucFlags & sbFLAGS_IS_MESSAGE_BUFFER) == (uint8_t) 0) + { + xBytesToStoreMessageLength = 0; + } + + /* Whether receiving a discrete message (where xBytesToStoreMessageLength + * holds the number of bytes used to store the message length) or a stream of + * bytes (where xBytesToStoreMessageLength is zero), the number of bytes + * available must be greater than xBytesToStoreMessageLength to be able to + * read bytes from the buffer. */ + if (xBytesAvailable > xBytesToStoreMessageLength) + { + xReceivedLength = prvReadMessageFromBuffer(pxStreamBuffer, + pvRxData, + xBufferLengthBytes, + xBytesAvailable, + xBytesToStoreMessageLength); + + /* Was a task waiting for space in the buffer? */ + if (xReceivedLength != (size_t) 0) + { + traceSTREAM_BUFFER_RECEIVE(xStreamBuffer, xReceivedLength); + sbRECEIVE_COMPLETED(pxStreamBuffer); + } + else + { + mtCOVERAGE_TEST_MARKER(); + } + } + else + { + traceSTREAM_BUFFER_RECEIVE_FAILED(xStreamBuffer); + mtCOVERAGE_TEST_MARKER(); + } + + return xReceivedLength; +} + +/*! \endcond */ diff --git a/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c b/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c index 492350dc0..ea93b288f 100644 --- a/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c +++ b/ra/fsp/src/rm_wifi_onchip_silex/rm_wifi_onchip_silex.c @@ -38,7 +38,7 @@ #endif #if (BSP_FEATURE_SCI_VERSION == 2U) #include "r_sci_b_uart.h" -typedef sci_b_uart_instance_ctrl_t rm_wifi_onchip_silex_uart_instance_t; +typedef sci_b_uart_instance_ctrl_t rm_wifi_onchip_silex_uart_instance_ctrl_t; typedef sci_b_uart_extended_cfg_t rm_wifi_onchip_silex_uart_extended_cfg_t; typedef sci_b_baud_setting_t rm_wifi_onchip_silex_baud_setting_t; #define RM_WIFI_ONCHIP_SILEX_SCI_UART_FLOW_CONTROL_RTS SCI_B_UART_FLOW_CONTROL_RTS @@ -47,7 +47,7 @@ static fsp_err_t (* p_sci_uart_baud_calculate)(uint32_t, bool, uint32_t, struct st_sci_b_baud_setting_t * const) = &R_SCI_B_UART_BaudCalculate; #else #include "r_sci_uart.h" -typedef sci_uart_instance_ctrl_t rm_wifi_onchip_silex_uart_instance_t; +typedef sci_uart_instance_ctrl_t rm_wifi_onchip_silex_uart_instance_ctrl_t; typedef sci_uart_extended_cfg_t rm_wifi_onchip_silex_uart_extended_cfg_t; typedef baud_setting_t rm_wifi_onchip_silex_baud_setting_t; #define RM_WIFI_ONCHIP_SILEX_SCI_UART_FLOW_CONTROL_RTS SCI_UART_FLOW_CONTROL_RTS @@ -209,7 +209,11 @@ typedef enum #define WIFI_OPEN (0x57495749ULL) // Is "WIFI" in ASCII /* Unique number for SCI Open Status */ -#define SCIU_OPEN (0x53434955U) // Is "SCIU" in ASCII +#if (BSP_FEATURE_SCI_VERSION == 2U) + #define SCIU_OPEN (0x53434942U) // Is "SCIB" in ASCII +#else + #define SCIU_OPEN (0x53434955U) // Is "SCIU" in ASCII +#endif /*********************************************************************************************************************** * Constants @@ -304,12 +308,21 @@ static wifi_onchip_silex_instance_ctrl_t g_rm_wifi_onchip_silex_instance; static rm_wifi_onchip_silex_baud_setting_t g_baud_setting_115200 = { +#if (2U == BSP_FEATURE_SCI_VERSION) + .baudrate_bits_b.brme = 0, + .baudrate_bits_b.abcse = 0, + .baudrate_bits_b.abcs = 0, + .baudrate_bits_b.bgdm = 0, + .baudrate_bits_b.brr = 0, + .baudrate_bits_b.mddr = 0, +#else .semr_baudrate_bits_b.brme = 0, .semr_baudrate_bits_b.abcse = 0, .semr_baudrate_bits_b.abcs = 0, .semr_baudrate_bits_b.bgdm = 0, .brr = 0, .mddr = 0, +#endif }; /*********************************************************************************************************************** @@ -2799,13 +2812,13 @@ static void rm_wifi_onchip_silex_cleanup_open (wifi_onchip_silex_instance_ctrl_t #endif uart_instance_t * p_uart = p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_SILEX_UART_INITIAL_PORT]; - if (SCIU_OPEN == ((rm_wifi_onchip_silex_uart_instance_t *) p_uart->p_ctrl)->open) + if (SCIU_OPEN == ((rm_wifi_onchip_silex_uart_instance_ctrl_t *) p_uart->p_ctrl)->open) { p_uart->p_api->close(p_uart->p_ctrl); } p_uart = p_instance_ctrl->uart_instance_objects[WIFI_ONCHIP_SILEX_UART_SECOND_PORT]; - if (SCIU_OPEN == ((rm_wifi_onchip_silex_uart_instance_t *) p_uart->p_ctrl)->open) + if (SCIU_OPEN == ((rm_wifi_onchip_silex_uart_instance_ctrl_t *) p_uart->p_ctrl)->open) { p_uart->p_api->close(p_uart->p_ctrl); } @@ -3460,9 +3473,9 @@ static fsp_err_t rm_wifi_onchip_silex_change_socket_index (wifi_onchip_silex_ins if (socket_no != p_instance_ctrl->curr_socket_index) // Only attempt change if socket number is different than current. { #if (BSP_CFG_RTOS == 1) - rm_wifi_onchip_silex_uart_instance_t * p_data_port_uart_ctrl = - (rm_wifi_onchip_silex_uart_instance_t *) p_instance_ctrl->uart_instance_objects[p_instance_ctrl-> - curr_data_port]-> + rm_wifi_onchip_silex_uart_instance_ctrl_t * p_data_port_uart_ctrl = + (rm_wifi_onchip_silex_uart_instance_ctrl_t *) p_instance_ctrl->uart_instance_objects[p_instance_ctrl-> + curr_data_port]-> p_ctrl; /* Set flow control in order to pause data over data port. */ @@ -4377,23 +4390,6 @@ size_t xStreamBufferReceiveAlternate (StreamBufferHandle_t xStreamBuffer, return xReceivedLength; } - #if defined(__ARMCC_VERSION) - -/*******************************************************************************************************************//** - * Default implementation of IotClock_GetTimestring for AC6. - **********************************************************************************************************************/ -__attribute__((weak)) -bool IotClock_GetTimestring (char * pBuffer, size_t bufferSize, size_t * pTimestringLength) -{ - FSP_PARAMETER_NOT_USED(pBuffer); - FSP_PARAMETER_NOT_USED(bufferSize); - FSP_PARAMETER_NOT_USED(pTimestringLength); - - return true; -} - - #endif - /*! \endcond */ #endif // FREERTOS diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/iaq_2nd_gen.h b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/iaq_2nd_gen.h index 58fc54488..688d105c7 100644 --- a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/iaq_2nd_gen.h +++ b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/iaq_2nd_gen.h @@ -39,21 +39,12 @@ extern "C" { #include #include - #if 0 // For multiple operations - #include "zmod4xxx_types.h" -/** - * @brief Variables that describe the library version - */ -typedef struct -{ - uint8_t major; - uint8_t minor; - uint8_t patch; -} algorithm_version; - #else - #include "../zmod4xxx_types.h" - #endif +#if TEST_RM_ZMOD4XXX // For RA FSP test + #include "../../../../../fsp/src/rm_zmod4xxx/zmod4xxx_types.h" +#else + #include "../zmod4xxx_types.h" +#endif /** \addtogroup RetCodes Return codes of the algorithm functions. * @{ diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/zmod4410_config_iaq2.h b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/zmod4410_config_iaq2.h index 72bbe7a74..da991aa3b 100644 --- a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/zmod4410_config_iaq2.h +++ b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen/zmod4410_config_iaq2.h @@ -29,8 +29,9 @@ #define _ZMOD4410_CONFIG_IAQ_2ND_GEN_H #include -#if 0 // For multiple operations - #include "zmod4xxx_types.h" + +#if TEST_RM_ZMOD4XXX // For RA FSP test + #include "../../../../../fsp/src/rm_zmod4xxx/zmod4xxx_types.h" #else #include "../zmod4xxx_types.h" #endif diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/iaq_2nd_gen_ulp.h b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/iaq_2nd_gen_ulp.h index 51acac5f7..2da48f9c0 100644 --- a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/iaq_2nd_gen_ulp.h +++ b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/iaq_2nd_gen_ulp.h @@ -39,21 +39,12 @@ extern "C" { #include #include - #if 0 // For multiple operations - #include "zmod4xxx_types.h" - -/** - * @brief Variables that describe the library version - */ -typedef struct -{ - uint8_t major; - uint8_t minor; - uint8_t patch; -} algorithm_version; - #else - #include "../zmod4xxx_types.h" - #endif + +#if TEST_RM_ZMOD4XXX // For RA FSP test + #include "../../../../../fsp/src/rm_zmod4xxx/zmod4xxx_types.h" +#else + #include "../zmod4xxx_types.h" +#endif /** \addtogroup RetCodes Return codes of the algorithm functions. * @{ diff --git a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/zmod4410_config_iaq2_ulp.h b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/zmod4410_config_iaq2_ulp.h index 608b775d0..308a455a1 100644 --- a/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/zmod4410_config_iaq2_ulp.h +++ b/ra/fsp/src/rm_zmod4xxx/iaq_2nd_gen_ulp/zmod4410_config_iaq2_ulp.h @@ -29,8 +29,9 @@ #define _ZMOD4410_CONFIG_IAQ_2ND_GEN_ULP_H #include -#if 0 // For multiple operations - #include "zmod4xxx_types.h" + +#if TEST_RM_ZMOD4XXX // For RA FSP test + #include "../../../../../fsp/src/rm_zmod4xxx/zmod4xxx_types.h" #else #include "../zmod4xxx_types.h" #endif diff --git a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/oaq_2nd_gen.h b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/oaq_2nd_gen.h index ae306c387..705076c71 100644 --- a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/oaq_2nd_gen.h +++ b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/oaq_2nd_gen.h @@ -38,21 +38,12 @@ extern "C" { #include #include - #if 0 // For multiple operations - #include "zmod4xxx_types.h" -/** - * @brief Variables that describe the library version - */ -typedef struct -{ - uint8_t major; - uint8_t minor; - uint8_t patch; -} algorithm_version; - #else - #include "../zmod4xxx_types.h" - #endif +#if TEST_RM_ZMOD4XXX // For RA FSP test + #include "../../../../../fsp/src/rm_zmod4xxx/zmod4xxx_types.h" +#else + #include "../zmod4xxx_types.h" +#endif /** \addtogroup RetCodes Return codes of the algorithm functions. * @{ diff --git a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_oaq2.h b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_oaq2.h index 4476fe7ba..4e6d5af5a 100644 --- a/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_oaq2.h +++ b/ra/fsp/src/rm_zmod4xxx/oaq_2nd_gen/zmod4510_config_oaq2.h @@ -29,8 +29,9 @@ #define _ZMOD4510_CONFIG_OAQ_2ND_GEN_H_ #include -#if 0 // For multiple operations - #include "zmod4xxx_types.h" + +#if TEST_RM_ZMOD4XXX // For RA FSP test + #include "../../../../../fsp/src/rm_zmod4xxx/zmod4xxx_types.h" #else #include "../zmod4xxx_types.h" #endif diff --git a/ra/fsp/src/rm_zmod4xxx/sulfur_odor/sulfur_odor.h b/ra/fsp/src/rm_zmod4xxx/sulfur_odor/sulfur_odor.h index c8b051acf..b6598dab6 100644 --- a/ra/fsp/src/rm_zmod4xxx/sulfur_odor/sulfur_odor.h +++ b/ra/fsp/src/rm_zmod4xxx/sulfur_odor/sulfur_odor.h @@ -39,21 +39,12 @@ extern "C" { #include #include - #if 0 // For multiple operations - #include "zmod4xxx_types.h" -/** - * @brief Variables that describe the library version - */ -typedef struct -{ - uint8_t major; - uint8_t minor; - uint8_t patch; -} algorithm_version; - #else - #include "../zmod4xxx_types.h" - #endif +#if TEST_RM_ZMOD4XXX // For RA FSP test + #include "../../../../../fsp/src/rm_zmod4xxx/zmod4xxx_types.h" +#else + #include "../zmod4xxx_types.h" +#endif /** * \defgroup sulfur_odor_ret Return codes of the sulfur odor algorithm functions diff --git a/ra/fsp/src/rm_zmod4xxx/sulfur_odor/zmod4410_config_sulfur_odor.h b/ra/fsp/src/rm_zmod4xxx/sulfur_odor/zmod4410_config_sulfur_odor.h index 92e3ac57a..4776e3e9c 100644 --- a/ra/fsp/src/rm_zmod4xxx/sulfur_odor/zmod4410_config_sulfur_odor.h +++ b/ra/fsp/src/rm_zmod4xxx/sulfur_odor/zmod4410_config_sulfur_odor.h @@ -29,8 +29,9 @@ #define _ZMOD4410_CONFIG_SULFUR_ODOR_H #include -#if 0 // For multiple operations - #include "zmod4xxx_types.h" + +#if TEST_RM_ZMOD4XXX // For RA FSP test + #include "../../../../../fsp/src/rm_zmod4xxx/zmod4xxx_types.h" #else #include "../zmod4xxx_types.h" #endif