diff --git a/tests/gtest/register_mode.json b/tests/gtest/register_mode.json new file mode 100644 index 000000000..8c1a4b6cd --- /dev/null +++ b/tests/gtest/register_mode.json @@ -0,0 +1,444 @@ +{"top":"global.RegisterMode", +"namespaces":{ + "global":{ + "modules":{ + "Mux2xOutBit":{ + "type":["Record",[ + ["I0","BitIn"], + ["I1","BitIn"], + ["S","BitIn"], + ["O","Bit"] + ]], + "instances":{ + "coreir_commonlib_mux2x1_inst0":{ + "genref":"commonlib.muxn", + "genargs":{"N":["Int",2], "width":["Int",1]} + } + }, + "connections":[ + ["self.I0","coreir_commonlib_mux2x1_inst0.in.data.0.0"], + ["self.I1","coreir_commonlib_mux2x1_inst0.in.data.1.0"], + ["self.S","coreir_commonlib_mux2x1_inst0.in.sel.0"], + ["self.O","coreir_commonlib_mux2x1_inst0.out.0"] + ] + }, + "Mux2xOutBits4":{ + "type":["Record",[ + ["I0",["Array",4,"BitIn"]], + ["I1",["Array",4,"BitIn"]], + ["S","BitIn"], + ["O",["Array",4,"Bit"]] + ]], + "instances":{ + "coreir_commonlib_mux2x4_inst0":{ + "genref":"commonlib.muxn", + "genargs":{"N":["Int",2], "width":["Int",4]} + } + }, + "connections":[ + ["self.I0","coreir_commonlib_mux2x4_inst0.in.data.0"], + ["self.I1","coreir_commonlib_mux2x4_inst0.in.data.1"], + ["self.S","coreir_commonlib_mux2x4_inst0.in.sel.0"], + ["self.O","coreir_commonlib_mux2x4_inst0.out"] + ] + }, + "Register":{ + "type":["Record",[ + ["value",["Array",4,"BitIn"]], + ["en","BitIn"], + ["CLK",["Named","coreir.clkIn"]], + ["O",["Array",4,"Bit"]] + ]], + "instances":{ + "Register_comb_inst0":{ + "modref":"global.Register_comb" + }, + "reg_P_inst0":{ + "genref":"coreir.reg", + "genargs":{"width":["Int",4]}, + "modargs":{"clk_posedge":["Bool",true], "init":[["BitVector",4],"4'h0"]} + } + }, + "connections":[ + ["reg_P_inst0.in","Register_comb_inst0.O0"], + ["self.O","Register_comb_inst0.O1"], + ["self.en","Register_comb_inst0.en"], + ["reg_P_inst0.out","Register_comb_inst0.self_value_O"], + ["self.value","Register_comb_inst0.value"], + ["self.CLK","reg_P_inst0.clk"] + ] + }, + "RegisterMode":{ + "type":["Record",[ + ["mode",["Array",2,"BitIn"]], + ["const_",["Array",4,"BitIn"]], + ["value",["Array",4,"BitIn"]], + ["clk_en","BitIn"], + ["config_we","BitIn"], + ["config_data",["Array",4,"BitIn"]], + ["CLK",["Named","coreir.clkIn"]], + ["O0",["Array",4,"Bit"]], + ["O1",["Array",4,"Bit"]] + ]], + "instances":{ + "RegisterMode_comb_inst0":{ + "modref":"global.RegisterMode_comb" + }, + "Register_inst0":{ + "modref":"global.Register" + } + }, + "connections":[ + ["Register_inst0.value","RegisterMode_comb_inst0.O0"], + ["Register_inst0.en","RegisterMode_comb_inst0.O1"], + ["self.O0","RegisterMode_comb_inst0.O2"], + ["self.O1","RegisterMode_comb_inst0.O3"], + ["self.clk_en","RegisterMode_comb_inst0.clk_en"], + ["self.config_data","RegisterMode_comb_inst0.config_data"], + ["self.config_we","RegisterMode_comb_inst0.config_we"], + ["self.const_","RegisterMode_comb_inst0.const_"], + ["self.mode","RegisterMode_comb_inst0.mode"], + ["Register_inst0.O","RegisterMode_comb_inst0.self_register_O"], + ["self.value","RegisterMode_comb_inst0.value"], + ["self.CLK","Register_inst0.CLK"] + ] + }, + "RegisterMode_comb":{ + "type":["Record",[ + ["mode",["Array",2,"BitIn"]], + ["const_",["Array",4,"BitIn"]], + ["value",["Array",4,"BitIn"]], + ["clk_en","BitIn"], + ["config_we","BitIn"], + ["config_data",["Array",4,"BitIn"]], + ["self_register_O",["Array",4,"BitIn"]], + ["O0",["Array",4,"Bit"]], + ["O1","Bit"], + ["O2",["Array",4,"Bit"]], + ["O3",["Array",4,"Bit"]] + ]], + "instances":{ + "Mux2xOutBit_inst0":{ + "modref":"global.Mux2xOutBit" + }, + "Mux2xOutBit_inst1":{ + "modref":"global.Mux2xOutBit" + }, + "Mux2xOutBit_inst2":{ + "modref":"global.Mux2xOutBit" + }, + "Mux2xOutBit_inst3":{ + "modref":"global.Mux2xOutBit" + }, + "Mux2xOutBit_inst4":{ + "modref":"global.Mux2xOutBit" + }, + "Mux2xOutBit_inst5":{ + "modref":"global.Mux2xOutBit" + }, + "Mux2xOutBits4_inst0":{ + "modref":"global.Mux2xOutBits4" + }, + "Mux2xOutBits4_inst1":{ + "modref":"global.Mux2xOutBits4" + }, + "Mux2xOutBits4_inst10":{ + "modref":"global.Mux2xOutBits4" + }, + "Mux2xOutBits4_inst11":{ + "modref":"global.Mux2xOutBits4" + }, + "Mux2xOutBits4_inst12":{ + "modref":"global.Mux2xOutBits4" + }, + "Mux2xOutBits4_inst13":{ + "modref":"global.Mux2xOutBits4" + }, + "Mux2xOutBits4_inst14":{ + "modref":"global.Mux2xOutBits4" + }, + "Mux2xOutBits4_inst2":{ + "modref":"global.Mux2xOutBits4" + }, + "Mux2xOutBits4_inst3":{ + "modref":"global.Mux2xOutBits4" + }, + "Mux2xOutBits4_inst4":{ + "modref":"global.Mux2xOutBits4" + }, + "Mux2xOutBits4_inst5":{ + "modref":"global.Mux2xOutBits4" + }, + "Mux2xOutBits4_inst6":{ + "modref":"global.Mux2xOutBits4" + }, + "Mux2xOutBits4_inst7":{ + "modref":"global.Mux2xOutBits4" + }, + "Mux2xOutBits4_inst8":{ + "modref":"global.Mux2xOutBits4" + }, + "Mux2xOutBits4_inst9":{ + "modref":"global.Mux2xOutBits4" + }, + "bit_const_0_None":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",false]} + }, + "bit_const_1_None":{ + "modref":"corebit.const", + "modargs":{"value":["Bool",true]} + }, + "const_0_2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",2]}, + "modargs":{"value":[["BitVector",2],"2'h0"]} + }, + "const_1_2":{ + "genref":"coreir.const", + "genargs":{"width":["Int",2]}, + "modargs":{"value":[["BitVector",2],"2'h1"]} + }, + "magma_Bit_not_inst0":{ + "modref":"corebit.not" + }, + "magma_Bit_not_inst1":{ + "modref":"corebit.not" + }, + "magma_Bit_not_inst2":{ + "modref":"corebit.not" + }, + "magma_Bit_not_inst3":{ + "modref":"corebit.not" + }, + "magma_Bit_not_inst4":{ + "modref":"corebit.not" + }, + "magma_Bit_not_inst5":{ + "modref":"corebit.not" + }, + "magma_Bit_not_inst6":{ + "modref":"corebit.not" + }, + "magma_Bit_xor_inst0":{ + "modref":"corebit.xor" + }, + "magma_Bit_xor_inst1":{ + "modref":"corebit.xor" + }, + "magma_Bit_xor_inst2":{ + "modref":"corebit.xor" + }, + "magma_Bit_xor_inst3":{ + "modref":"corebit.xor" + }, + "magma_Bit_xor_inst4":{ + "modref":"corebit.xor" + }, + "magma_Bit_xor_inst5":{ + "modref":"corebit.xor" + }, + "magma_Bit_xor_inst6":{ + "modref":"corebit.xor" + }, + "magma_Bits_2_eq_inst0":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",2]} + }, + "magma_Bits_2_eq_inst1":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",2]} + }, + "magma_Bits_2_eq_inst10":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",2]} + }, + "magma_Bits_2_eq_inst11":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",2]} + }, + "magma_Bits_2_eq_inst12":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",2]} + }, + "magma_Bits_2_eq_inst13":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",2]} + }, + "magma_Bits_2_eq_inst2":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",2]} + }, + "magma_Bits_2_eq_inst3":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",2]} + }, + "magma_Bits_2_eq_inst4":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",2]} + }, + "magma_Bits_2_eq_inst5":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",2]} + }, + "magma_Bits_2_eq_inst6":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",2]} + }, + "magma_Bits_2_eq_inst7":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",2]} + }, + "magma_Bits_2_eq_inst8":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",2]} + }, + "magma_Bits_2_eq_inst9":{ + "genref":"coreir.eq", + "genargs":{"width":["Int",2]} + } + }, + "connections":[ + ["self.clk_en","Mux2xOutBit_inst0.I0"], + ["bit_const_0_None.out","Mux2xOutBit_inst0.I1"], + ["Mux2xOutBit_inst1.I0","Mux2xOutBit_inst0.O"], + ["magma_Bits_2_eq_inst1.out","Mux2xOutBit_inst0.S"], + ["bit_const_0_None.out","Mux2xOutBit_inst1.I1"], + ["Mux2xOutBit_inst2.I0","Mux2xOutBit_inst1.O"], + ["magma_Bits_2_eq_inst4.out","Mux2xOutBit_inst1.S"], + ["bit_const_1_None.out","Mux2xOutBit_inst2.I1"], + ["magma_Bit_not_inst1.out","Mux2xOutBit_inst2.S"], + ["self.clk_en","Mux2xOutBit_inst3.I0"], + ["bit_const_0_None.out","Mux2xOutBit_inst3.I1"], + ["Mux2xOutBit_inst4.I0","Mux2xOutBit_inst3.O"], + ["magma_Bits_2_eq_inst7.out","Mux2xOutBit_inst3.S"], + ["bit_const_0_None.out","Mux2xOutBit_inst4.I1"], + ["Mux2xOutBit_inst5.I0","Mux2xOutBit_inst4.O"], + ["magma_Bits_2_eq_inst11.out","Mux2xOutBit_inst4.S"], + ["bit_const_1_None.out","Mux2xOutBit_inst5.I1"], + ["self.O1","Mux2xOutBit_inst5.O"], + ["magma_Bit_not_inst4.out","Mux2xOutBit_inst5.S"], + ["self.value","Mux2xOutBits4_inst0.I0"], + ["self.value","Mux2xOutBits4_inst0.I1"], + ["Mux2xOutBits4_inst2.I0","Mux2xOutBits4_inst0.O"], + ["magma_Bits_2_eq_inst0.out","Mux2xOutBits4_inst0.S"], + ["self.self_register_O","Mux2xOutBits4_inst1.I0"], + ["self.self_register_O","Mux2xOutBits4_inst1.I1"], + ["Mux2xOutBits4_inst3.I0","Mux2xOutBits4_inst1.O"], + ["magma_Bits_2_eq_inst2.out","Mux2xOutBits4_inst1.S"], + ["Mux2xOutBits4_inst7.O","Mux2xOutBits4_inst10.I0"], + ["self.const_","Mux2xOutBits4_inst10.I1"], + ["Mux2xOutBits4_inst13.I0","Mux2xOutBits4_inst10.O"], + ["magma_Bits_2_eq_inst12.out","Mux2xOutBits4_inst10.S"], + ["Mux2xOutBits4_inst8.O","Mux2xOutBits4_inst11.I0"], + ["self.self_register_O","Mux2xOutBits4_inst11.I1"], + ["Mux2xOutBits4_inst14.I0","Mux2xOutBits4_inst11.O"], + ["magma_Bits_2_eq_inst13.out","Mux2xOutBits4_inst11.S"], + ["Mux2xOutBits4_inst9.O","Mux2xOutBits4_inst12.I0"], + ["self.config_data","Mux2xOutBits4_inst12.I1"], + ["self.O0","Mux2xOutBits4_inst12.O"], + ["magma_Bit_not_inst3.out","Mux2xOutBits4_inst12.S"], + ["self.self_register_O","Mux2xOutBits4_inst13.I1"], + ["self.O2","Mux2xOutBits4_inst13.O"], + ["magma_Bit_not_inst5.out","Mux2xOutBits4_inst13.S"], + ["self.self_register_O","Mux2xOutBits4_inst14.I1"], + ["self.O3","Mux2xOutBits4_inst14.O"], + ["magma_Bit_not_inst6.out","Mux2xOutBits4_inst14.S"], + ["self.value","Mux2xOutBits4_inst2.I1"], + ["Mux2xOutBits4_inst4.I0","Mux2xOutBits4_inst2.O"], + ["magma_Bits_2_eq_inst3.out","Mux2xOutBits4_inst2.S"], + ["self.self_register_O","Mux2xOutBits4_inst3.I1"], + ["Mux2xOutBits4_inst5.I0","Mux2xOutBits4_inst3.O"], + ["magma_Bits_2_eq_inst5.out","Mux2xOutBits4_inst3.S"], + ["self.config_data","Mux2xOutBits4_inst4.I1"], + ["magma_Bit_not_inst0.out","Mux2xOutBits4_inst4.S"], + ["self.self_register_O","Mux2xOutBits4_inst5.I1"], + ["magma_Bit_not_inst2.out","Mux2xOutBits4_inst5.S"], + ["self.value","Mux2xOutBits4_inst6.I0"], + ["self.value","Mux2xOutBits4_inst6.I1"], + ["Mux2xOutBits4_inst9.I0","Mux2xOutBits4_inst6.O"], + ["magma_Bits_2_eq_inst6.out","Mux2xOutBits4_inst6.S"], + ["self.self_register_O","Mux2xOutBits4_inst7.I0"], + ["self.value","Mux2xOutBits4_inst7.I1"], + ["magma_Bits_2_eq_inst8.out","Mux2xOutBits4_inst7.S"], + ["self.self_register_O","Mux2xOutBits4_inst8.I0"], + ["self.self_register_O","Mux2xOutBits4_inst8.I1"], + ["magma_Bits_2_eq_inst9.out","Mux2xOutBits4_inst8.S"], + ["self.value","Mux2xOutBits4_inst9.I1"], + ["magma_Bits_2_eq_inst10.out","Mux2xOutBits4_inst9.S"], + ["magma_Bit_xor_inst0.in1","bit_const_1_None.out"], + ["magma_Bit_xor_inst1.in1","bit_const_1_None.out"], + ["magma_Bit_xor_inst2.in1","bit_const_1_None.out"], + ["magma_Bit_xor_inst3.in1","bit_const_1_None.out"], + ["magma_Bit_xor_inst4.in1","bit_const_1_None.out"], + ["magma_Bit_xor_inst5.in1","bit_const_1_None.out"], + ["magma_Bit_xor_inst6.in1","bit_const_1_None.out"], + ["magma_Bits_2_eq_inst10.in1","const_0_2.out"], + ["magma_Bits_2_eq_inst11.in1","const_0_2.out"], + ["magma_Bits_2_eq_inst12.in1","const_0_2.out"], + ["magma_Bits_2_eq_inst13.in1","const_0_2.out"], + ["magma_Bits_2_eq_inst3.in1","const_0_2.out"], + ["magma_Bits_2_eq_inst4.in1","const_0_2.out"], + ["magma_Bits_2_eq_inst5.in1","const_0_2.out"], + ["magma_Bits_2_eq_inst0.in1","const_1_2.out"], + ["magma_Bits_2_eq_inst1.in1","const_1_2.out"], + ["magma_Bits_2_eq_inst2.in1","const_1_2.out"], + ["magma_Bits_2_eq_inst6.in1","const_1_2.out"], + ["magma_Bits_2_eq_inst7.in1","const_1_2.out"], + ["magma_Bits_2_eq_inst8.in1","const_1_2.out"], + ["magma_Bits_2_eq_inst9.in1","const_1_2.out"], + ["magma_Bit_xor_inst0.out","magma_Bit_not_inst0.in"], + ["magma_Bit_xor_inst1.out","magma_Bit_not_inst1.in"], + ["magma_Bit_xor_inst2.out","magma_Bit_not_inst2.in"], + ["magma_Bit_xor_inst3.out","magma_Bit_not_inst3.in"], + ["magma_Bit_xor_inst4.out","magma_Bit_not_inst4.in"], + ["magma_Bit_xor_inst5.out","magma_Bit_not_inst5.in"], + ["magma_Bit_xor_inst6.out","magma_Bit_not_inst6.in"], + ["self.config_we","magma_Bit_xor_inst0.in0"], + ["self.config_we","magma_Bit_xor_inst1.in0"], + ["self.config_we","magma_Bit_xor_inst2.in0"], + ["self.config_we","magma_Bit_xor_inst3.in0"], + ["self.config_we","magma_Bit_xor_inst4.in0"], + ["self.config_we","magma_Bit_xor_inst5.in0"], + ["self.config_we","magma_Bit_xor_inst6.in0"], + ["self.mode","magma_Bits_2_eq_inst0.in0"], + ["self.mode","magma_Bits_2_eq_inst1.in0"], + ["self.mode","magma_Bits_2_eq_inst10.in0"], + ["self.mode","magma_Bits_2_eq_inst11.in0"], + ["self.mode","magma_Bits_2_eq_inst12.in0"], + ["self.mode","magma_Bits_2_eq_inst13.in0"], + ["self.mode","magma_Bits_2_eq_inst2.in0"], + ["self.mode","magma_Bits_2_eq_inst3.in0"], + ["self.mode","magma_Bits_2_eq_inst4.in0"], + ["self.mode","magma_Bits_2_eq_inst5.in0"], + ["self.mode","magma_Bits_2_eq_inst6.in0"], + ["self.mode","magma_Bits_2_eq_inst7.in0"], + ["self.mode","magma_Bits_2_eq_inst8.in0"], + ["self.mode","magma_Bits_2_eq_inst9.in0"] + ] + }, + "Register_comb":{ + "type":["Record",[ + ["value",["Array",4,"BitIn"]], + ["en","BitIn"], + ["self_value_O",["Array",4,"BitIn"]], + ["O0",["Array",4,"Bit"]], + ["O1",["Array",4,"Bit"]] + ]], + "instances":{ + "Mux2xOutBits4_inst0":{ + "modref":"global.Mux2xOutBits4" + } + }, + "connections":[ + ["self.self_value_O","Mux2xOutBits4_inst0.I0"], + ["self.value","Mux2xOutBits4_inst0.I1"], + ["self.O0","Mux2xOutBits4_inst0.O"], + ["self.en","Mux2xOutBits4_inst0.S"], + ["self.self_value_O","self.O1"] + ] + } + } + } +} +} diff --git a/tests/gtest/register_mode_golden.v b/tests/gtest/register_mode_golden.v new file mode 100644 index 000000000..07aebeefe --- /dev/null +++ b/tests/gtest/register_mode_golden.v @@ -0,0 +1,89 @@ +module coreir_reg #(parameter width = 1, parameter clk_posedge = 1, parameter init = 1) (input clk, input [width-1:0] in, output [width-1:0] out); + reg [width-1:0] outReg=init; + wire real_clk; + assign real_clk = clk_posedge ? clk : ~clk; + always @(posedge real_clk) begin + outReg <= in; + end + assign out = outReg; +endmodule + +module commonlib_muxn__N2__width4 (input [3:0] in_data_0, input [3:0] in_data_1, input [0:0] in_sel, output [3:0] out); +assign out = in_sel[0] ? in_data_1 : in_data_0; +endmodule + +module commonlib_muxn__N2__width1 (input [0:0] in_data_0, input [0:0] in_data_1, input [0:0] in_sel, output [0:0] out); +assign out = in_sel[0] ? in_data_1 : in_data_0; +endmodule + +module Mux2xOutBits4 (input [3:0] I0, input [3:0] I1, output [3:0] O, input S); +commonlib_muxn__N2__width4 coreir_commonlib_mux2x4_inst0(.in_data_0(I0), .in_data_1(I1), .in_sel(S), .out(O)); +endmodule + +module Register_comb (output [3:0] O0, output [3:0] O1, input en, input [3:0] self_value_O, input [3:0] value); +Mux2xOutBits4 Mux2xOutBits4_inst0(.I0(self_value_O), .I1(value), .O(O0), .S(en)); +assign O1 = self_value_O; +endmodule + +module Register (input CLK, output [3:0] O, input en, input [3:0] value); +wire [3:0] Register_comb_inst0_O0; +wire [3:0] reg_P_inst0_out; +Register_comb Register_comb_inst0(.O0(Register_comb_inst0_O0), .O1(O), .en(en), .self_value_O(reg_P_inst0_out), .value(value)); +coreir_reg #(.clk_posedge(1'b1), .init(4'h0), .width(4)) reg_P_inst0(.clk(CLK), .in(Register_comb_inst0_O0), .out(reg_P_inst0_out)); +endmodule + +module Mux2xOutBit (input I0, input I1, output O, input S); +wire [0:0] coreir_commonlib_mux2x1_inst0_out; +commonlib_muxn__N2__width1 coreir_commonlib_mux2x1_inst0(.in_data_0(I0), .in_data_1(I1), .in_sel(S), .out(coreir_commonlib_mux2x1_inst0_out)); +assign O = coreir_commonlib_mux2x1_inst0_out[0]; +endmodule + +module RegisterMode_comb (output [3:0] O0, output O1, output [3:0] O2, output [3:0] O3, input clk_en, input [3:0] config_data, input config_we, input [3:0] const_, input [1:0] mode, input [3:0] self_register_O, input [3:0] value); +wire Mux2xOutBit_inst0_O; +wire Mux2xOutBit_inst1_O; +wire Mux2xOutBit_inst2_O; +wire Mux2xOutBit_inst3_O; +wire Mux2xOutBit_inst4_O; +wire [3:0] Mux2xOutBits4_inst0_O; +wire [3:0] Mux2xOutBits4_inst1_O; +wire [3:0] Mux2xOutBits4_inst10_O; +wire [3:0] Mux2xOutBits4_inst11_O; +wire [3:0] Mux2xOutBits4_inst2_O; +wire [3:0] Mux2xOutBits4_inst3_O; +wire [3:0] Mux2xOutBits4_inst4_O; +wire [3:0] Mux2xOutBits4_inst5_O; +wire [3:0] Mux2xOutBits4_inst6_O; +wire [3:0] Mux2xOutBits4_inst7_O; +wire [3:0] Mux2xOutBits4_inst8_O; +wire [3:0] Mux2xOutBits4_inst9_O; +Mux2xOutBit Mux2xOutBit_inst0(.I0(clk_en), .I1(1'b0), .O(Mux2xOutBit_inst0_O), .S(mode == 2'h1)); +Mux2xOutBit Mux2xOutBit_inst1(.I0(Mux2xOutBit_inst0_O), .I1(1'b0), .O(Mux2xOutBit_inst1_O), .S(mode == 2'h0)); +Mux2xOutBit Mux2xOutBit_inst2(.I0(Mux2xOutBit_inst1_O), .I1(1'b1), .O(Mux2xOutBit_inst2_O), .S(~ (config_we ^ 1'b1))); +Mux2xOutBit Mux2xOutBit_inst3(.I0(clk_en), .I1(1'b0), .O(Mux2xOutBit_inst3_O), .S(mode == 2'h1)); +Mux2xOutBit Mux2xOutBit_inst4(.I0(Mux2xOutBit_inst3_O), .I1(1'b0), .O(Mux2xOutBit_inst4_O), .S(mode == 2'h0)); +Mux2xOutBit Mux2xOutBit_inst5(.I0(Mux2xOutBit_inst4_O), .I1(1'b1), .O(O1), .S(~ (config_we ^ 1'b1))); +Mux2xOutBits4 Mux2xOutBits4_inst0(.I0(value), .I1(value), .O(Mux2xOutBits4_inst0_O), .S(mode == 2'h1)); +Mux2xOutBits4 Mux2xOutBits4_inst1(.I0(self_register_O), .I1(self_register_O), .O(Mux2xOutBits4_inst1_O), .S(mode == 2'h1)); +Mux2xOutBits4 Mux2xOutBits4_inst10(.I0(Mux2xOutBits4_inst7_O), .I1(const_), .O(Mux2xOutBits4_inst10_O), .S(mode == 2'h0)); +Mux2xOutBits4 Mux2xOutBits4_inst11(.I0(Mux2xOutBits4_inst8_O), .I1(self_register_O), .O(Mux2xOutBits4_inst11_O), .S(mode == 2'h0)); +Mux2xOutBits4 Mux2xOutBits4_inst12(.I0(Mux2xOutBits4_inst9_O), .I1(config_data), .O(O0), .S(~ (config_we ^ 1'b1))); +Mux2xOutBits4 Mux2xOutBits4_inst13(.I0(Mux2xOutBits4_inst10_O), .I1(self_register_O), .O(O2), .S(~ (config_we ^ 1'b1))); +Mux2xOutBits4 Mux2xOutBits4_inst14(.I0(Mux2xOutBits4_inst11_O), .I1(self_register_O), .O(O3), .S(~ (config_we ^ 1'b1))); +Mux2xOutBits4 Mux2xOutBits4_inst2(.I0(Mux2xOutBits4_inst0_O), .I1(value), .O(Mux2xOutBits4_inst2_O), .S(mode == 2'h0)); +Mux2xOutBits4 Mux2xOutBits4_inst3(.I0(Mux2xOutBits4_inst1_O), .I1(self_register_O), .O(Mux2xOutBits4_inst3_O), .S(mode == 2'h0)); +Mux2xOutBits4 Mux2xOutBits4_inst4(.I0(Mux2xOutBits4_inst2_O), .I1(config_data), .O(Mux2xOutBits4_inst4_O), .S(~ (config_we ^ 1'b1))); +Mux2xOutBits4 Mux2xOutBits4_inst5(.I0(Mux2xOutBits4_inst3_O), .I1(self_register_O), .O(Mux2xOutBits4_inst5_O), .S(~ (config_we ^ 1'b1))); +Mux2xOutBits4 Mux2xOutBits4_inst6(.I0(value), .I1(value), .O(Mux2xOutBits4_inst6_O), .S(mode == 2'h1)); +Mux2xOutBits4 Mux2xOutBits4_inst7(.I0(self_register_O), .I1(value), .O(Mux2xOutBits4_inst7_O), .S(mode == 2'h1)); +Mux2xOutBits4 Mux2xOutBits4_inst8(.I0(self_register_O), .I1(self_register_O), .O(Mux2xOutBits4_inst8_O), .S(mode == 2'h1)); +Mux2xOutBits4 Mux2xOutBits4_inst9(.I0(Mux2xOutBits4_inst6_O), .I1(value), .O(Mux2xOutBits4_inst9_O), .S(mode == 2'h0)); +endmodule + +module RegisterMode (input CLK, output [3:0] O0, output [3:0] O1, input clk_en, input [3:0] config_data, input config_we, input [3:0] const_, input [1:0] mode, input [3:0] value); +wire [3:0] RegisterMode_comb_inst0_O0; +wire RegisterMode_comb_inst0_O1; +wire [3:0] Register_inst0_O; +RegisterMode_comb RegisterMode_comb_inst0(.O0(RegisterMode_comb_inst0_O0), .O1(RegisterMode_comb_inst0_O1), .O2(O0), .O3(O1), .clk_en(clk_en), .config_data(config_data), .config_we(config_we), .const_(const_), .mode(mode), .self_register_O(Register_inst0_O), .value(value)); +Register Register_inst0(.CLK(CLK), .O(Register_inst0_O), .en(RegisterMode_comb_inst0_O1), .value(RegisterMode_comb_inst0_O0)); +endmodule + diff --git a/tests/gtest/test_verilog.cpp b/tests/gtest/test_verilog.cpp index 9cd4ba69f..cf2c657a9 100644 --- a/tests/gtest/test_verilog.cpp +++ b/tests/gtest/test_verilog.cpp @@ -206,6 +206,30 @@ TEST(VerilogTests, TestDebugInfo) { deleteContext(c); } +TEST(VerilogTests, TestRegisterMode) { + Context* c = newContext(); + CoreIRLoadVerilog_coreir(c); + CoreIRLoadVerilog_corebit(c); + CoreIRLoadLibrary_commonlib(c); + Module* top; + + if (!loadFromFile(c, "register_mode.json", &top)) { + c->die(); + } + assert(top != nullptr); + c->setTop(top->getRefName()); + + const std::vector passes = { + "rungenerators", + "removebulkconnections", + "flattentypes", + "verilog --inline" + }; + c->runPasses(passes, {}); + assertPassEq(c, "register_mode_golden.v"); + deleteContext(c); +} + } // namespace int main(int argc, char **argv) {