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Day83 - RISCV Data Memory
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‎day83/design.sv

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`include "riscv_fetch.sv"
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`include "riscv_decode.sv"
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`include "riscv_regfile.sv"
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`include "riscv_execute.sv"
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`include "riscv_dmem.sv"
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module riscv_top (
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input wire clk,
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input wire reset
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);
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// Instantiate and connect all the submodules
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endmodule

‎day83/riscv_decode.sv

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module riscv_decode (
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input logic[31:0] if_dec_instr_i,
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output logic[4:0] rs1_o,
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output logic[4:0] rs2_o,
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output logic[4:0] rd_o,
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output logic[6:0] op_o,
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output logic[2:0] funct3_o,
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output logic[6:0] funct7_o,
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output logic is_r_type_o,
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output logic is_i_type_o,
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output logic is_s_type_o,
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output logic is_b_type_o,
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output logic is_u_type_o,
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output logic is_j_type_o,
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output logic[11:0] i_type_imm_o,
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output logic[11:0] s_type_imm_o,
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output logic[11:0] b_type_imm_o,
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output logic[19:0] u_type_imm_o,
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output logic[19:0] j_type_imm_o
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);
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assign rd_o = if_dec_instr_i[11:7];
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assign rs1_o = if_dec_instr_i[19:15];
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assign rs2_o = if_dec_instr_i[24:20];
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assign op_o = if_dec_instr_i[6:0];
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assign funct3_o = if_dec_instr_i[14:12];
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assign funct7_o = if_dec_instr_i[31:25];
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// Decode the type of the instruction
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always_comb begin
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is_r_type_o = 1'b0;
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is_i_type_o = 1'b0;
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is_s_type_o = 1'b0;
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is_b_type_o = 1'b0;
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is_u_type_o = 1'b0;
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is_j_type_o = 1'b0;
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case (op_o)
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7'h33 : is_r_type_o = 1'b1;
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// I-type data processing
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// I-type LW
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// JALR
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7'h13,
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7'h03,
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7'h67 : is_i_type_o = 1'b1;
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7'h23 : is_s_type_o = 1'b1;
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7'h63 : is_b_type_o = 1'b1;
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7'h6F : is_j_type_o = 1'b1;
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endcase
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end
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assign i_type_imm_o[11:0] = if_dec_instr_i[31:20];
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assign s_type_imm_o[11:0] = {if_dec_instr_i[31:25], if_dec_instr_i[11:7]};
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assign b_type_imm_o[11:0] = {if_dec_instr_i[31], if_dec_instr_i[7], if_dec_instr_i[30:25],
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if_dec_instr_i[11:8]};
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assign u_type_imm_o[19:0] = if_dec_instr_i[31:12];
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assign j_type_imm_o[19:0] = {if_dec_instr_i[31], if_dec_instr_i[19:12], if_dec_instr_i[20],
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if_dec_instr_i[30:21]};
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endmodule

‎day83/riscv_dmem.sv

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// APB Master for the data memory unit
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module riscv_dmem (
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input wire clk,
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input wire reset,
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input wire ex_dmem_valid_i, // Mem operation is valid
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input wire[31:0] ex_dmem_addr_i,
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input wire[31:0] ex_dmem_wdata_i,
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input wire ex_dmem_wnr_i, // 1 - write, 0 - read
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// ------------------------------------------------------------
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// APB Interface to memory
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// ------------------------------------------------------------
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output wire psel_o,
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output wire penable_o,
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output wire[31:0] paddr_o,
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output wire pwrite_o,
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output wire[31:0] pwdata_o,
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input wire pready_i,
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input wire[31:0] prdata_i,
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// ------------------------------------------------------------
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// Data output
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// ------------------------------------------------------------
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output logic[31:0] dmem_data_o,
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output logic dmem_done_o
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);
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// Enum for the APB state
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typedef enum logic[1:0] {ST_IDLE = 2'b00, ST_SETUP = 2'b01, ST_ACCESS = 2'b10} apb_state_t;
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apb_state_t nxt_state;
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apb_state_t state_q;
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logic [31:0] if_pc_q;
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always_ff @(posedge clk or posedge reset)
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if (reset)
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state_q <= ST_IDLE;
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else
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state_q <= nxt_state;
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always_comb begin
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nxt_state = state_q;
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case (state_q)
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ST_IDLE : nxt_state = ex_dmem_valid_i ? ST_SETUP : ST_IDLE;
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ST_SETUP : nxt_state = ST_ACCESS;
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ST_ACCESS : begin
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if (pready_i) nxt_state = ST_IDLE;
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end
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endcase
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end
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assign psel_o = (state_q == ST_SETUP) | (state_q == ST_ACCESS);
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assign penable_o = (state_q == ST_ACCESS);
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assign pwrite_o = ex_dmem_wnr_i;
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assign paddr_o = ex_dmem_addr_i; // Memory address
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assign pwdata_o = ex_dmem_wdata_i;
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assign dmem_done_o = penable_o && pready_i;
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assign dmem_data_o = prdata_i;
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endmodule

‎day83/riscv_execute.sv

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module riscv_execute (
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input wire [31:0] opr_a_i,
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input wire [31:0] opr_b_i,
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input wire [3:0] op_sel_i,
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output wire [31:0] ex_res_o
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);
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logic [31:0] alu_res;
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logic signed [31:0] sign_opr_a;
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logic signed [31:0] sign_opr_b;
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assign sign_opr_a = opr_a_i;
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assign sign_opr_b = opr_b_i;
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// Supported Operations
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localparam OP_ADD = 4'b0000;
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localparam OP_SUB = 4'b0001;
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localparam OP_SLL = 4'b0010;
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localparam OP_LSR = 4'b0011;
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localparam OP_ASR = 4'b0100;
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localparam OP_OR = 4'b0101;
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localparam OP_AND = 4'b0110;
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localparam OP_XOR = 4'b0111;
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localparam OP_EQL = 4'b1000;
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localparam OP_ULT = 4'b1001;
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localparam OP_UGT = 4'b1010;
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localparam OP_SLT = 4'b1011;
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localparam OP_SGT = 4'b1100;
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always_comb begin
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alu_res = 32'h0;
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case (op_sel_i)
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OP_ADD: alu_res = opr_a_i + opr_b_i;
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OP_SUB: alu_res = opr_a_i - opr_b_i;
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OP_SLL: alu_res = opr_a_i << opr_b_i[4:0];
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OP_LSR: alu_res = opr_a_i >> opr_b_i[4:0];
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OP_ASR: alu_res = sign_opr_a >>> opr_b_i[4:0];
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OP_OR: alu_res = opr_a_i | opr_b_i;
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OP_AND: alu_res = opr_a_i & opr_b_i;
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OP_XOR: alu_res = opr_a_i ^ opr_b_i;
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OP_EQL: alu_res = {31'h0, opr_a_i == opr_b_i};
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OP_ULT: alu_res = {31'h0, opr_a_i < opr_b_i};
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OP_UGT: alu_res = {31'h0, opr_a_i >= opr_b_i};
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OP_SLT: alu_res = {31'h0, sign_opr_a < sign_opr_b};
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OP_SGT: alu_res = {31'h0, sign_opr_a >= sign_opr_b};
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endcase
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end
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assign ex_res_o = alu_res;
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endmodule

‎day83/riscv_fetch.sv

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// APB Master for the instruction fetch unit
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module riscv_fetch (
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input wire clk,
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input wire reset,
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input wire instr_done_i,
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// ------------------------------------------------------------
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// APB Interface to memory
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// ------------------------------------------------------------
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output wire psel_o,
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output wire penable_o,
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output wire[31:0] paddr_o,
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output wire pwrite_o,
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output wire[31:0] pwdata_o,
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input wire pready_i,
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input wire[31:0] prdata_i,
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// ------------------------------------------------------------
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// Instruction output
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// ------------------------------------------------------------
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output logic if_dec_valid_o,
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output logic[31:0] if_dec_instr_o,
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input wire[31:0] ex_if_pc_i
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);
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// Enum for the APB state
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typedef enum logic[1:0] {ST_IDLE = 2'b00, ST_SETUP = 2'b01, ST_ACCESS = 2'b10} apb_state_t;
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apb_state_t nxt_state;
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apb_state_t state_q;
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logic [31:0] if_pc_q;
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logic nxt_dec_valid;
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always_ff @(posedge clk or posedge reset)
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if (reset)
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state_q <= ST_IDLE;
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else
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state_q <= nxt_state;
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always_comb begin
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nxt_state = state_q;
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case (state_q)
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// Memory responses may not be single cycle. Wait for the
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// memory request to complete before requesting the next
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// instruction
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ST_IDLE : nxt_state = instr_done_i ? ST_SETUP : ST_IDLE;
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ST_SETUP : nxt_state = ST_ACCESS;
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ST_ACCESS : begin
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if (pready_i) nxt_state = ST_IDLE;
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end
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endcase
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end
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assign psel_o = (state_q == ST_SETUP) | (state_q == ST_ACCESS);
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assign penable_o = (state_q == ST_ACCESS);
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assign pwrite_o = 1'b0; // No writes to IMEM
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assign paddr_o = if_pc_q; // Current instruction counter
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assign pwdata_o = 32'h0;
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// Start from 0x8000_0000 on reset
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always_ff @(posedge clk or posedge reset)
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if (reset)
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if_pc_q <= 32'h8000_0000;
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else
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if_pc_q <= ex_if_pc_i;
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// Capture the read data as the current instruction opcode
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always_ff @(posedge clk or posedge reset)
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if (reset) begin
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if_dec_instr_o <= 32'h0;
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end else if (penable_o && pready_i) begin
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if_dec_instr_o <= prdata_i;
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end
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always_ff @(posedge clk or posedge reset)
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if (reset) begin
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if_dec_valid_o <= 1'b0;
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end else if ((penable_o && pready_i) | if_dec_valid_o) begin
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if_dec_valid_o <= nxt_dec_valid;
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end
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// Set valid on:
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// - Valid APB transfer and clear it next cycle if no valid transfer
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// and if the flag was set
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assign nxt_dec_valid = (penable_o && pready_i);
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endmodule

‎day83/riscv_regfile.sv

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module riscv_regfile (
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input wire clk,
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input wire reset,
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// Single write address
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input wire rf_wr_en_i,
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input wire[4:0] rf_wr_addr_i,
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input wire[31:0] rf_wr_data_i,
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// Two read addresses
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input wire[4:0] rf_rd_p0_i,
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input wire[4:0] rf_rd_p1_i,
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output wire[31:0] rf_rd_p0_data_o,
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output wire[31:0] rf_rd_p1_data_o,
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);
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// Register file
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logic [31:0] reg_file [31:0];
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// Write logic
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always_ff @(posedge clk)
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if (rf_wr_en_i)
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reg_file[rf_wr_addr_i] <= rf_wr_data_i;
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// Read logic
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assign rf_rd_p0_data_o = 32'(|rf_rd_p0_i) & reg_file[rf_rd_p0_i];
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assign rf_rd_p0_data_o = 32'(|rf_rd_p1_i) & reg_file[rf_rd_p1_i];
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endmodule

‎day83/testbench.sv

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// Code your testbench here
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// or browse Examples

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