Vivado is a leading FPGA development tool in the industry, and RapidStream offers various sophisticated methods to enhance the Vivado development flow. In this tutorial, we will guide you through the different ways RapidStream optimizes Vivado-compatible projects.
These tutorials target various FPGA devices. The table below lists the tutorials available, and the features and flows showcased in all of these tutorials.
| Design | Developer | Platforms | Sources | Purpose |
| CNN | AutoBridge | U50 | Vitis HLS, Verilog | An HLS accelerator for the convolutional neural network kernel. |
| LLM | Chen et al. (TRETS) |
U280 VHK158 VP1552 VU9P |
Vitis HLS, Verilog | Large Language Model |
| cnn13x2 | AutoBridge | U50 | Manual RTL files | Pure text Vivado source project for RTL developers.. |