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dds_test.tcl
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dds_test.tcl
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#*****************************************************************************************
# Vivado (TM) v2022.2 (64-bit)
#
# dds_test.tcl: Tcl script for re-creating project 'dds_test'
#
# Generated by Vivado on Fri Sep 29 16:22:10 EDT 2023
# IP Build 3669848 on Fri Oct 14 08:30:02 MDT 2022
#
# This file contains the Vivado Tcl commands for re-creating the project to the state*
# when this script was generated. In order to re-create the project, please source this
# file in the Vivado Tcl Shell.
#
# * Note that the runs in the created project will be configured the same way as the
# original project, however they will not be launched automatically. To regenerate the
# run results please launch the synthesis/implementation runs as needed.
#
#*****************************************************************************************
# NOTE: In order to use this script for source control purposes, please make sure that the
# following files are added to the source control system:-
#
# 1. This project restoration tcl script (dds_test.tcl) that was generated.
#
# 2. The following source(s) files that were local or imported into the original project.
# (Please see the '$orig_proj_dir' and '$origin_dir' variable setting below at the start of the script)
#
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/axis.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/dds.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/lfsr16.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/dds_wrapper.v"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/lmh6401_spi.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/lmh6401_spi_wrapper.v"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/axis_x2.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/axis_x2_wrapper.v"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/dac_prescaler.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/dac_prescaler_wrapper.v"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/fifo.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/noise_event_tracker.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/sample_buffer.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/sample_buffer_wrapper.v"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/adc_axis_mux.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/adc_axis_mux_wrapper.v"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/sample_interleaver.v"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/constrs_1/new/lmh6401_io.xdc"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sim_1/new/noise_event_tracker_test.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sim_1/new/axis_x2_test.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sim_1/new/dac_prescaler_test.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sim_1/new/dds_test.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sim_1/new/fifo_test.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sim_1/new/lmh6401_spi_test.sv"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sim_1/new/sample_buffer_test.sv"
# "/home/reedf/Documents/Xilinx/dds_test/lmh6401_spi_test_behav.wcfg"
# "/home/reedf/Documents/Xilinx/dds_test/axis_x2_test_behav.wcfg"
# "/home/reedf/Documents/Xilinx/dds_test/fifo_test_behav.wcfg"
# "/home/reedf/Documents/Xilinx/dds_test/noise_event_tracker_test_behav.wcfg"
# "/home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/utils_1/imports/synth_1/top_wrapper.dcp"
#
# 3. The following remote source files that were added to the original project:-
#
# <none>
#
#*****************************************************************************************
# Check file required for this script exists
proc checkRequiredFiles { origin_dir} {
set status true
set files [list \
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/axis.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/dds.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/lfsr16.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/dds_wrapper.v"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/lmh6401_spi.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/lmh6401_spi_wrapper.v"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/axis_x2.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/axis_x2_wrapper.v"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/dac_prescaler.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/dac_prescaler_wrapper.v"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/fifo.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/noise_event_tracker.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/sample_buffer.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/sample_buffer_wrapper.v"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/adc_axis_mux.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/adc_axis_mux_wrapper.v"]"\
"[file normalize "$origin_dir/dds_test.srcs/sources_1/new/sample_interleaver.v"]"\
"[file normalize "$origin_dir/dds_test.srcs/constrs_1/new/lmh6401_io.xdc"]"\
"[file normalize "$origin_dir/dds_test.srcs/sim_1/new/noise_event_tracker_test.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sim_1/new/axis_x2_test.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sim_1/new/dac_prescaler_test.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sim_1/new/dds_test.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sim_1/new/fifo_test.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sim_1/new/lmh6401_spi_test.sv"]"\
"[file normalize "$origin_dir/dds_test.srcs/sim_1/new/sample_buffer_test.sv"]"\
"[file normalize "$origin_dir/lmh6401_spi_test_behav.wcfg"]"\
"[file normalize "$origin_dir/axis_x2_test_behav.wcfg"]"\
"[file normalize "$origin_dir/fifo_test_behav.wcfg"]"\
"[file normalize "$origin_dir/noise_event_tracker_test_behav.wcfg"]"\
"[file normalize "$origin_dir/dds_test.srcs/utils_1/imports/synth_1/top_wrapper.dcp"]"\
]
foreach ifile $files {
if { ![file isfile $ifile] } {
puts " Could not find local file $ifile "
set status false
}
}
set paths [list \
"[file normalize "$origin_dir/../../../ip_repo/myip_test_1_0"]"]"\
]
foreach ipath $paths {
if { ![file isdirectory $ipath] } {
puts " Could not access $ipath "
set status false
}
}
return $status
}
# Set the reference directory for source file relative paths (by default the value is script directory path)
set origin_dir "."
# Use origin directory path location variable, if specified in the tcl shell
if { [info exists ::origin_dir_loc] } {
set origin_dir $::origin_dir_loc
}
# Set the project name
set _xil_proj_name_ "dds_test"
# Use project name variable, if specified in the tcl shell
if { [info exists ::user_project_name] } {
set _xil_proj_name_ $::user_project_name
}
variable script_file
set script_file "dds_test.tcl"
# Help information for this script
proc print_help {} {
variable script_file
puts "\nDescription:"
puts "Recreate a Vivado project from this script. The created project will be"
puts "functionally equivalent to the original project for which this script was"
puts "generated. The script contains commands for creating a project, filesets,"
puts "runs, adding/importing sources and setting properties on various objects.\n"
puts "Syntax:"
puts "$script_file"
puts "$script_file -tclargs \[--origin_dir <path>\]"
puts "$script_file -tclargs \[--project_name <name>\]"
puts "$script_file -tclargs \[--help\]\n"
puts "Usage:"
puts "Name Description"
puts "-------------------------------------------------------------------------"
puts "\[--origin_dir <path>\] Determine source file paths wrt this path. Default"
puts " origin_dir path value is \".\", otherwise, the value"
puts " that was set with the \"-paths_relative_to\" switch"
puts " when this script was generated.\n"
puts "\[--project_name <name>\] Create project with the specified name. Default"
puts " name is the name of the project from where this"
puts " script was generated.\n"
puts "\[--help\] Print help information for this script"
puts "-------------------------------------------------------------------------\n"
exit 0
}
if { $::argc > 0 } {
for {set i 0} {$i < $::argc} {incr i} {
set option [string trim [lindex $::argv $i]]
switch -regexp -- $option {
"--origin_dir" { incr i; set origin_dir [lindex $::argv $i] }
"--project_name" { incr i; set _xil_proj_name_ [lindex $::argv $i] }
"--help" { print_help }
default {
if { [regexp {^-} $option] } {
puts "ERROR: Unknown option '$option' specified, please type '$script_file -tclargs --help' for usage info.\n"
return 1
}
}
}
}
}
# Set the directory path for the original project from where this script was exported
set orig_proj_dir "[file normalize "$origin_dir/"]"
# Check for paths and files needed for project creation
set validate_required 0
if { $validate_required } {
if { [checkRequiredFiles $origin_dir] } {
puts "Tcl file $script_file is valid. All files required for project creation is accesable. "
} else {
puts "Tcl file $script_file is not valid. Not all files required for project creation is accesable. "
return
}
}
# Create project
create_project ${_xil_proj_name_} ./${_xil_proj_name_} -part xczu28dr-ffvg1517-2-e
# Set the directory path for the new project
set proj_dir [get_property directory [current_project]]
# Set project properties
set obj [current_project]
set_property -name "board_part" -value "xilinx.com:zcu111:part0:1.4" -objects $obj
set_property -name "default_lib" -value "xil_defaultlib" -objects $obj
set_property -name "enable_resource_estimation" -value "0" -objects $obj
set_property -name "enable_vhdl_2008" -value "1" -objects $obj
set_property -name "ip_cache_permissions" -value "read write" -objects $obj
set_property -name "ip_output_repo" -value "$proj_dir/${_xil_proj_name_}.cache/ip" -objects $obj
set_property -name "mem.enable_memory_map_generation" -value "1" -objects $obj
set_property -name "platform.board_id" -value "zcu111" -objects $obj
set_property -name "revised_directory_structure" -value "1" -objects $obj
set_property -name "sim.central_dir" -value "$proj_dir/${_xil_proj_name_}.ip_user_files" -objects $obj
set_property -name "sim.ip.auto_export_scripts" -value "1" -objects $obj
set_property -name "simulator_language" -value "Mixed" -objects $obj
set_property -name "sim_compile_state" -value "1" -objects $obj
set_property -name "webtalk.xsim_launch_sim" -value "251" -objects $obj
set_property -name "xpm_libraries" -value "XPM_CDC XPM_FIFO XPM_MEMORY" -objects $obj
# Create 'sources_1' fileset (if not found)
if {[string equal [get_filesets -quiet sources_1] ""]} {
create_fileset -srcset sources_1
}
# Set IP repository paths
set obj [get_filesets sources_1]
if { $obj != {} } {
set_property "ip_repo_paths" "[file normalize "$origin_dir/../ip_repo/myip_test_1_0"]" $obj
# Rebuild user ip_repo's index before adding any source files
update_ip_catalog -rebuild
}
# Set 'sources_1' fileset object
set obj [get_filesets sources_1]
# Import local files from the original project
set files [list \
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/axis.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/dds.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/lfsr16.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/dds_wrapper.v" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/lmh6401_spi.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/lmh6401_spi_wrapper.v" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/axis_x2.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/axis_x2_wrapper.v" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/dac_prescaler.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/dac_prescaler_wrapper.v" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/fifo.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/noise_event_tracker.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/sample_buffer.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/sample_buffer_wrapper.v" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/adc_axis_mux.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/adc_axis_mux_wrapper.v" ]\
[file normalize "${origin_dir}/dds_test.srcs/sources_1/new/sample_interleaver.v" ]\
]
set imported_files [import_files -fileset sources_1 $files]
# Set 'sources_1' fileset file properties for remote files
# None
# Set 'sources_1' fileset file properties for local files
set file "new/axis.sv"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/dds.sv"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/lfsr16.sv"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/lmh6401_spi.sv"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/axis_x2.sv"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/dac_prescaler.sv"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/fifo.sv"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/noise_event_tracker.sv"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/sample_buffer.sv"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/adc_axis_mux.sv"
set file_obj [get_files -of_objects [get_filesets sources_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
# Set 'sources_1' fileset properties
set obj [get_filesets sources_1]
set_property -name "dataflow_viewer_settings" -value "min_width=16" -objects $obj
set_property -name "top" -value "top_wrapper" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
# Create 'constrs_1' fileset (if not found)
if {[string equal [get_filesets -quiet constrs_1] ""]} {
create_fileset -constrset constrs_1
}
# Set 'constrs_1' fileset object
set obj [get_filesets constrs_1]
# Add/Import constrs file and set constrs file properties
set file "[file normalize "$origin_dir/dds_test.srcs/constrs_1/new/lmh6401_io.xdc"]"
set file_imported [import_files -fileset constrs_1 [list $file]]
set file "new/lmh6401_io.xdc"
set file_obj [get_files -of_objects [get_filesets constrs_1] [list "*$file"]]
set_property -name "file_type" -value "XDC" -objects $file_obj
# Set 'constrs_1' fileset properties
set obj [get_filesets constrs_1]
# Create 'sim_1' fileset (if not found)
if {[string equal [get_filesets -quiet sim_1] ""]} {
create_fileset -simset sim_1
}
# Set 'sim_1' fileset object
set obj [get_filesets sim_1]
# Import local files from the original project
set files [list \
[file normalize "${origin_dir}/dds_test.srcs/sim_1/new/noise_event_tracker_test.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sim_1/new/axis_x2_test.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sim_1/new/dac_prescaler_test.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sim_1/new/dds_test.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sim_1/new/fifo_test.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sim_1/new/lmh6401_spi_test.sv" ]\
[file normalize "${origin_dir}/dds_test.srcs/sim_1/new/sample_buffer_test.sv" ]\
[file normalize "${origin_dir}/lmh6401_spi_test_behav.wcfg" ]\
[file normalize "${origin_dir}/axis_x2_test_behav.wcfg" ]\
[file normalize "${origin_dir}/fifo_test_behav.wcfg" ]\
[file normalize "${origin_dir}/noise_event_tracker_test_behav.wcfg" ]\
]
set imported_files [import_files -fileset sim_1 $files]
# Set 'sim_1' fileset file properties for remote files
# None
# Set 'sim_1' fileset file properties for local files
set file "new/noise_event_tracker_test.sv"
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/axis_x2_test.sv"
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/dac_prescaler_test.sv"
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/dds_test.sv"
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/fifo_test.sv"
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/lmh6401_spi_test.sv"
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
set file "new/sample_buffer_test.sv"
set file_obj [get_files -of_objects [get_filesets sim_1] [list "*$file"]]
set_property -name "file_type" -value "SystemVerilog" -objects $file_obj
# Set 'sim_1' fileset properties
set obj [get_filesets sim_1]
set_property -name "top" -value "noise_event_tracker_test" -objects $obj
set_property -name "top_auto_set" -value "0" -objects $obj
set_property -name "top_lib" -value "xil_defaultlib" -objects $obj
# Set 'utils_1' fileset object
set obj [get_filesets utils_1]
# Import local files from the original project
set files [list \
[file normalize "${origin_dir}/dds_test.srcs/utils_1/imports/synth_1/top_wrapper.dcp" ]\
]
set imported_files [import_files -fileset utils_1 $files]
# Set 'utils_1' fileset file properties for remote files
# None
# Set 'utils_1' fileset file properties for local files
set file "synth_1/top_wrapper.dcp"
set file_obj [get_files -of_objects [get_filesets utils_1] [list "*$file"]]
set_property -name "netlist_only" -value "0" -objects $file_obj
# Set 'utils_1' fileset properties
set obj [get_filesets utils_1]
# Adding sources referenced in BDs, if not already added
if { [get_files axis.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/axis.sv
}
if { [get_files dds.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/dds.sv
}
if { [get_files lfsr16.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/lfsr16.sv
}
if { [get_files dds_wrapper.v] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/dds_wrapper.v
}
if { [get_files axis.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/axis.sv
}
if { [get_files dds.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/dds.sv
}
if { [get_files lfsr16.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/lfsr16.sv
}
if { [get_files dds_wrapper.v] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/dds_wrapper.v
}
if { [get_files lmh6401_spi.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/lmh6401_spi.sv
}
if { [get_files lmh6401_spi_wrapper.v] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/lmh6401_spi_wrapper.v
}
if { [get_files axis.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/axis.sv
}
if { [get_files axis_x2.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/axis_x2.sv
}
if { [get_files axis_x2_wrapper.v] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/axis_x2_wrapper.v
}
if { [get_files axis.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/axis.sv
}
if { [get_files axis_x2.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/axis_x2.sv
}
if { [get_files axis_x2_wrapper.v] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/axis_x2_wrapper.v
}
if { [get_files axis.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/axis.sv
}
if { [get_files dac_prescaler.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/dac_prescaler.sv
}
if { [get_files dac_prescaler_wrapper.v] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/dac_prescaler_wrapper.v
}
if { [get_files axis.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/axis.sv
}
if { [get_files dac_prescaler.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/dac_prescaler.sv
}
if { [get_files dac_prescaler_wrapper.v] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/dac_prescaler_wrapper.v
}
if { [get_files axis.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/axis.sv
}
if { [get_files fifo.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/fifo.sv
}
if { [get_files noise_event_tracker.sv] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/noise_event_tracker.sv
}
if { [get_files noise_event_tracker_wrapper.v] == "" } {
import_files -quiet -fileset sources_1 /home/reedf/Documents/Xilinx/dds_test/dds_test.srcs/sources_1/new/noise_event_tracker_wrapper.v
}
# Proc to create BD top
proc cr_bd_top { parentCell } {
# The design that will be created by this Tcl proc contains the following
# module references:
# dac_prescaler_wrapper, dac_prescaler_wrapper, dds_wrapper, dds_wrapper, lmh6401_spi_wrapper, noise_event_tracker_wrapper, axis_x2_wrapper, axis_x2_wrapper
# CHANGE DESIGN NAME HERE
set design_name top
common::send_gid_msg -ssname BD::TCL -id 2010 -severity "INFO" "Currently there is no design <$design_name> in project, so creating one..."
create_bd_design $design_name
set bCheckIPsPassed 1
##################################################################
# CHECK IPs
##################################################################
set bCheckIPs 1
if { $bCheckIPs == 1 } {
set list_check_ips "\
xilinx.com:ip:clk_wiz:6.0\
xilinx.com:ip:proc_sys_reset:5.0\
xilinx.com:ip:axi_dma:7.1\
xilinx.com:ip:axi_gpio:2.0\
xilinx.com:ip:smartconnect:1.0\
xilinx.com:ip:axi_timer:2.0\
xilinx.com:ip:usp_rf_data_converter:2.6\
xilinx.com:ip:zynq_ultra_ps_e:3.4\
xilinx.com:ip:axis_data_fifo:2.0\
xilinx.com:ip:axis_dwidth_converter:1.1\
xilinx.com:ip:axi_fifo_mm_s:4.2\
xilinx.com:ip:fir_compiler:7.2\
"
set list_ips_missing ""
common::send_gid_msg -ssname BD::TCL -id 2011 -severity "INFO" "Checking if the following IPs exist in the project's IP catalog: $list_check_ips ."
foreach ip_vlnv $list_check_ips {
set ip_obj [get_ipdefs -all $ip_vlnv]
if { $ip_obj eq "" } {
lappend list_ips_missing $ip_vlnv
}
}
if { $list_ips_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2012 -severity "ERROR" "The following IPs are not found in the IP Catalog:\n $list_ips_missing\n\nResolution: Please add the repository containing the IP(s) to the project." }
set bCheckIPsPassed 0
}
}
##################################################################
# CHECK Modules
##################################################################
set bCheckModules 1
if { $bCheckModules == 1 } {
set list_check_mods "\
dac_prescaler_wrapper\
dac_prescaler_wrapper\
dds_wrapper\
dds_wrapper\
lmh6401_spi_wrapper\
noise_event_tracker_wrapper\
axis_x2_wrapper\
axis_x2_wrapper\
"
set list_mods_missing ""
common::send_gid_msg -ssname BD::TCL -id 2020 -severity "INFO" "Checking if the following modules exist in the project's sources: $list_check_mods ."
foreach mod_vlnv $list_check_mods {
if { [can_resolve_reference $mod_vlnv] == 0 } {
lappend list_mods_missing $mod_vlnv
}
}
if { $list_mods_missing ne "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2021 -severity "ERROR" "The following module(s) are not found in the project: $list_mods_missing" }
common::send_gid_msg -ssname BD::TCL -id 2022 -severity "INFO" "Please add source files for the missing module(s) above."
set bCheckIPsPassed 0
}
}
if { $bCheckIPsPassed != 1 } {
common::send_gid_msg -ssname BD::TCL -id 2023 -severity "WARNING" "Will not continue with creation of design due to the error(s) above."
return 3
}
# Hierarchical cell: adc02_energy_downsample
proc create_hier_cell_adc02_energy_downsample { parentCell nameHier } {
variable script_folder
if { $parentCell eq "" || $nameHier eq "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_adc02_energy_downsample() - Empty argument(s)!"}
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
# Create interface pins
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_DATA
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_512
# Create pins
create_bd_pin -dir I -type clk axis_aclk_150
create_bd_pin -dir I -type clk axis_aclk_256
create_bd_pin -dir I -type clk axis_aclk_512
create_bd_pin -dir I -type rst axis_aresetn_150
create_bd_pin -dir I -type rst axis_aresetn_256
create_bd_pin -dir I -type rst axis_aresetn_512
# Create instance: adc_cdc_fifo, and set properties
set adc_cdc_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 adc_cdc_fifo ]
set_property -dict [list \
CONFIG.FIFO_DEPTH {16} \
CONFIG.IS_ACLK_ASYNC {1} \
CONFIG.TDATA_NUM_BYTES {4} \
] $adc_cdc_fifo
# Create instance: adc_cdc_fifo1, and set properties
set adc_cdc_fifo1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 adc_cdc_fifo1 ]
set_property -dict [list \
CONFIG.FIFO_DEPTH {16} \
CONFIG.IS_ACLK_ASYNC {1} \
CONFIG.TDATA_NUM_BYTES {2} \
] $adc_cdc_fifo1
# Create instance: adc_dwidth_converter, and set properties
set adc_dwidth_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 adc_dwidth_converter ]
set_property -dict [list \
CONFIG.M_TDATA_NUM_BYTES {4} \
CONFIG.S_TDATA_NUM_BYTES {2} \
] $adc_dwidth_converter
# Create instance: axis_x2_wrapper_0, and set properties
set block_name axis_x2_wrapper
set block_cell_name axis_x2_wrapper_0
if { [catch {set axis_x2_wrapper_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $axis_x2_wrapper_0 eq "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: fir16d_32_2, and set properties
set fir16d_32_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 fir16d_32_2 ]
set_property -dict [list \
CONFIG.Clock_Frequency {150} \
CONFIG.CoefficientVector {686, 737, 759, 743, 686, 583, 434, 238, -1, -276, -578, -898, -1220, -1529, -1809, -2042, -2211, -2301, -2298, -2190, -1971, -1637, -1191, -641, 0, 712, 1473, 2253, 3019,\
3736, 4368, 4876, 5228, 5390, 5337, 5048, 4512, 3726, 2697, 1445, -1, -1599, -3300, -5042, -6757, -8372, -9810, -10991, -11838, -12279, -12248, -11690, -10560, -8830, -6487, -3537, 0, 4079, 8643, 13615,\
18903, 24403, 30000, 35573, 40995, 46141, 50889, 55124, 58744, 61658, 63793, 65096, 65535, 65096, 63793, 61658, 58744, 55124, 50889, 46141, 40995, 35573, 30000, 24403, 18903, 13615, 8643, 4079, 0, -3537,\
-6487, -8830, -10560, -11690, -12248, -12279, -11838, -10991, -9810, -8372, -6757, -5042, -3300, -1599, -1, 1445, 2697, 3726, 4512, 5048, 5337, 5390, 5228, 4876, 4368, 3736, 3019, 2253, 1473, 712, 0, -641,\
-1191, -1637, -1971, -2190, -2298, -2301, -2211, -2042, -1809, -1529, -1220, -898, -578, -276, -1, 238, 434, 583, 686, 743, 759, 737, 686} \
CONFIG.Coefficient_Fractional_Bits {0} \
CONFIG.Coefficient_Sets {1} \
CONFIG.Coefficient_Sign {Signed} \
CONFIG.Coefficient_Structure {Inferred} \
CONFIG.Coefficient_Width {19} \
CONFIG.ColumnConfig {2} \
CONFIG.Decimation_Rate {16} \
CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \
CONFIG.Filter_Type {Decimation} \
CONFIG.Interpolation_Rate {1} \
CONFIG.Number_Channels {1} \
CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \
CONFIG.Output_Width {16} \
CONFIG.Quantization {Integer_Coefficients} \
CONFIG.RateSpecification {Frequency_Specification} \
CONFIG.Sample_Frequency {32} \
CONFIG.Zero_Pack_Factor {1} \
] $fir16d_32_2
# Create instance: fir4d_128_32, and set properties
set fir4d_128_32 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 fir4d_128_32 ]
set_property -dict [list \
CONFIG.Clock_Frequency {150} \
CONFIG.CoefficientVector {290, 485, 401, -1, -534, -863, -693, 0, 879, 1393, 1100, -1, -1362, -2136, -1672, 0, 2042, 3190, 2492, -1, -3048, -4778, -3754, 0, 4687, 7466, 5993, -1, -7986, -13367, -11481,\
0, 19474, 41538, 58937, 65535, 58937, 41538, 19474, 0, -11481, -13367, -7986, -1, 5993, 7466, 4687, 0, -3754, -4778, -3048, -1, 2492, 3190, 2042, 0, -1672, -2136, -1362, -1, 1100, 1393, 879, 0, -693, -863,\
-534, -1, 401, 485, 290} \
CONFIG.Coefficient_Fractional_Bits {0} \
CONFIG.Coefficient_Sets {1} \
CONFIG.Coefficient_Sign {Signed} \
CONFIG.Coefficient_Structure {Inferred} \
CONFIG.Coefficient_Width {18} \
CONFIG.ColumnConfig {9} \
CONFIG.Decimation_Rate {4} \
CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \
CONFIG.Filter_Type {Decimation} \
CONFIG.Interpolation_Rate {1} \
CONFIG.Number_Channels {1} \
CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \
CONFIG.Output_Width {16} \
CONFIG.Passband_Max {0.2} \
CONFIG.Quantization {Integer_Coefficients} \
CONFIG.RateSpecification {Frequency_Specification} \
CONFIG.Sample_Frequency {128} \
CONFIG.Zero_Pack_Factor {1} \
] $fir4d_128_32
# Create instance: fir4d_512_128, and set properties
set fir4d_512_128 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 fir4d_512_128 ]
set_property -dict [list \
CONFIG.Clock_Frequency {256} \
CONFIG.CoefficientVector {686, 686, -1, -1220, -2211, -1971, 0, 3019, 5228, 4512, -1, -6757, -11838, -10560, 0, 18903, 40995, 58744, 65535, 58744, 40995, 18903, 0, -10560, -11838, -6757, -1, 4512,\
5228, 3019, 0, -1971, -2211, -1220, -1, 686, 686} \
CONFIG.Coefficient_Fanout {true} \
CONFIG.Coefficient_Fractional_Bits {0} \
CONFIG.Coefficient_Reload {false} \
CONFIG.Coefficient_Sets {1} \
CONFIG.Coefficient_Sign {Signed} \
CONFIG.Coefficient_Structure {Inferred} \
CONFIG.Coefficient_Width {18} \
CONFIG.ColumnConfig {10} \
CONFIG.Control_Broadcast_Fanout {true} \
CONFIG.Control_Column_Fanout {true} \
CONFIG.Control_LUT_Pipeline {true} \
CONFIG.Control_Path_Fanout {true} \
CONFIG.Data_Path_Broadcast {false} \
CONFIG.Data_Path_Fanout {true} \
CONFIG.Data_Width {16} \
CONFIG.Decimation_Rate {4} \
CONFIG.Disable_Half_Band_Centre_Tap {false} \
CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \
CONFIG.Filter_Type {Decimation} \
CONFIG.Interpolation_Rate {1} \
CONFIG.No_BRAM_Read_First_Mode {true} \
CONFIG.No_SRL_Attributes {false} \
CONFIG.Number_Channels {1} \
CONFIG.Optimal_Column_Lengths {true} \
CONFIG.Optimization_Goal {Speed} \
CONFIG.Optimization_List {Data_Path_Fanout,Pre-Adder_Pipeline,Coefficient_Fanout,Control_Path_Fanout,Control_Column_Fanout,Control_Broadcast_Fanout,Control_LUT_Pipeline,No_BRAM_Read_First_Mode,Optimal_Column_Lengths,Other}\
\
CONFIG.Optimization_Selection {All} \
CONFIG.Other {true} \
CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \
CONFIG.Output_Width {16} \
CONFIG.Passband_Max {0.20} \
CONFIG.Pre_Adder_Pipeline {true} \
CONFIG.Quantization {Integer_Coefficients} \
CONFIG.RateSpecification {Frequency_Specification} \
CONFIG.Sample_Frequency {512} \
CONFIG.Zero_Pack_Factor {1} \
] $fir4d_512_128
# Create interface connections
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins S_AXIS_512] [get_bd_intf_pins adc_dwidth_converter/S_AXIS]
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins M_AXIS_DATA] [get_bd_intf_pins fir16d_32_2/M_AXIS_DATA]
connect_bd_intf_net -intf_net adc00_cdc_fifo_M_AXIS [get_bd_intf_pins adc_cdc_fifo/M_AXIS] [get_bd_intf_pins fir4d_512_128/S_AXIS_DATA]
connect_bd_intf_net -intf_net adc00_dwidth_converter_M_AXIS [get_bd_intf_pins adc_cdc_fifo/S_AXIS] [get_bd_intf_pins adc_dwidth_converter/M_AXIS]
connect_bd_intf_net -intf_net adc_cdc_fifo1_M_AXIS [get_bd_intf_pins adc_cdc_fifo1/M_AXIS] [get_bd_intf_pins axis_x2_wrapper_0/s_axis]
connect_bd_intf_net -intf_net axis_x2_wrapper_0_m_axis [get_bd_intf_pins axis_x2_wrapper_0/m_axis] [get_bd_intf_pins fir4d_128_32/S_AXIS_DATA]
connect_bd_intf_net -intf_net fir4d_128_32_M_AXIS_DATA [get_bd_intf_pins fir16d_32_2/S_AXIS_DATA] [get_bd_intf_pins fir4d_128_32/M_AXIS_DATA]
connect_bd_intf_net -intf_net fir_4_down_M_AXIS_DATA [get_bd_intf_pins adc_cdc_fifo1/S_AXIS] [get_bd_intf_pins fir4d_512_128/M_AXIS_DATA]
# Create port connections
connect_bd_net -net aclk_1 [get_bd_pins axis_aclk_512] [get_bd_pins adc_cdc_fifo/s_axis_aclk] [get_bd_pins adc_dwidth_converter/aclk]
connect_bd_net -net aresetn_1 [get_bd_pins axis_aresetn_512] [get_bd_pins adc_cdc_fifo/s_axis_aresetn] [get_bd_pins adc_dwidth_converter/aresetn]
connect_bd_net -net m_axis_aclk1_1 [get_bd_pins axis_aclk_150] [get_bd_pins adc_cdc_fifo1/m_axis_aclk] [get_bd_pins axis_x2_wrapper_0/clk] [get_bd_pins fir16d_32_2/aclk] [get_bd_pins fir4d_128_32/aclk]
connect_bd_net -net m_axis_aclk_1 [get_bd_pins axis_aclk_256] [get_bd_pins adc_cdc_fifo/m_axis_aclk] [get_bd_pins adc_cdc_fifo1/s_axis_aclk] [get_bd_pins fir4d_512_128/aclk]
connect_bd_net -net reset_n_1 [get_bd_pins axis_aresetn_150] [get_bd_pins axis_x2_wrapper_0/reset_n]
connect_bd_net -net s_axis_aresetn_1 [get_bd_pins axis_aresetn_256] [get_bd_pins adc_cdc_fifo1/s_axis_aresetn]
# Restore current instance
current_bd_instance $oldCurInst
}
# Hierarchical cell: adc00_energy_downsample
proc create_hier_cell_adc00_energy_downsample { parentCell nameHier } {
variable script_folder
if { $parentCell eq "" || $nameHier eq "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2092 -severity "ERROR" "create_hier_cell_adc00_energy_downsample() - Empty argument(s)!"}
return
}
# Get object for parentCell
set parentObj [get_bd_cells $parentCell]
if { $parentObj == "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2090 -severity "ERROR" "Unable to find parent cell <$parentCell>!"}
return
}
# Make sure parentObj is hier blk
set parentType [get_property TYPE $parentObj]
if { $parentType ne "hier" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2091 -severity "ERROR" "Parent <$parentObj> has TYPE = <$parentType>. Expected to be <hier>."}
return
}
# Save current instance; Restore later
set oldCurInst [current_bd_instance .]
# Set parent object as current
current_bd_instance $parentObj
# Create cell and set as current instance
set hier_obj [create_bd_cell -type hier $nameHier]
current_bd_instance $hier_obj
# Create interface pins
create_bd_intf_pin -mode Master -vlnv xilinx.com:interface:axis_rtl:1.0 M_AXIS_DATA
create_bd_intf_pin -mode Slave -vlnv xilinx.com:interface:axis_rtl:1.0 S_AXIS_512
# Create pins
create_bd_pin -dir I -type clk axis_aclk_150
create_bd_pin -dir I -type clk axis_aclk_256
create_bd_pin -dir I -type clk axis_aclk_512
create_bd_pin -dir I -type rst axis_aresetn_150
create_bd_pin -dir I -type rst axis_aresetn_256
create_bd_pin -dir I -type rst axis_aresetn_512
# Create instance: adc_cdc_fifo, and set properties
set adc_cdc_fifo [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 adc_cdc_fifo ]
set_property -dict [list \
CONFIG.FIFO_DEPTH {16} \
CONFIG.IS_ACLK_ASYNC {1} \
CONFIG.TDATA_NUM_BYTES {4} \
] $adc_cdc_fifo
# Create instance: adc_cdc_fifo1, and set properties
set adc_cdc_fifo1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_data_fifo:2.0 adc_cdc_fifo1 ]
set_property -dict [list \
CONFIG.FIFO_DEPTH {16} \
CONFIG.IS_ACLK_ASYNC {1} \
] $adc_cdc_fifo1
# Create instance: adc_dwidth_converter, and set properties
set adc_dwidth_converter [ create_bd_cell -type ip -vlnv xilinx.com:ip:axis_dwidth_converter:1.1 adc_dwidth_converter ]
set_property -dict [list \
CONFIG.M_TDATA_NUM_BYTES {4} \
CONFIG.S_TDATA_NUM_BYTES {2} \
] $adc_dwidth_converter
# Create instance: axis_x2_wrapper_0, and set properties
set block_name axis_x2_wrapper
set block_cell_name axis_x2_wrapper_0
if { [catch {set axis_x2_wrapper_0 [create_bd_cell -type module -reference $block_name $block_cell_name] } errmsg] } {
catch {common::send_gid_msg -ssname BD::TCL -id 2095 -severity "ERROR" "Unable to add referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
} elseif { $axis_x2_wrapper_0 eq "" } {
catch {common::send_gid_msg -ssname BD::TCL -id 2096 -severity "ERROR" "Unable to referenced block <$block_name>. Please add the files for ${block_name}'s definition into the project."}
return 1
}
# Create instance: fir16d_32_2, and set properties
set fir16d_32_2 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 fir16d_32_2 ]
set_property -dict [list \
CONFIG.Clock_Frequency {150} \
CONFIG.CoefficientVector {686, 737, 759, 743, 686, 583, 434, 238, -1, -276, -578, -898, -1220, -1529, -1809, -2042, -2211, -2301, -2298, -2190, -1971, -1637, -1191, -641, 0, 712, 1473, 2253, 3019,\
3736, 4368, 4876, 5228, 5390, 5337, 5048, 4512, 3726, 2697, 1445, -1, -1599, -3300, -5042, -6757, -8372, -9810, -10991, -11838, -12279, -12248, -11690, -10560, -8830, -6487, -3537, 0, 4079, 8643, 13615,\
18903, 24403, 30000, 35573, 40995, 46141, 50889, 55124, 58744, 61658, 63793, 65096, 65535, 65096, 63793, 61658, 58744, 55124, 50889, 46141, 40995, 35573, 30000, 24403, 18903, 13615, 8643, 4079, 0, -3537,\
-6487, -8830, -10560, -11690, -12248, -12279, -11838, -10991, -9810, -8372, -6757, -5042, -3300, -1599, -1, 1445, 2697, 3726, 4512, 5048, 5337, 5390, 5228, 4876, 4368, 3736, 3019, 2253, 1473, 712, 0, -641,\
-1191, -1637, -1971, -2190, -2298, -2301, -2211, -2042, -1809, -1529, -1220, -898, -578, -276, -1, 238, 434, 583, 686, 743, 759, 737, 686} \
CONFIG.Coefficient_Fractional_Bits {0} \
CONFIG.Coefficient_Sets {1} \
CONFIG.Coefficient_Sign {Signed} \
CONFIG.Coefficient_Structure {Inferred} \
CONFIG.Coefficient_Width {19} \
CONFIG.ColumnConfig {2} \
CONFIG.Decimation_Rate {16} \
CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \
CONFIG.Filter_Type {Decimation} \
CONFIG.Interpolation_Rate {1} \
CONFIG.Number_Channels {1} \
CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \
CONFIG.Output_Width {16} \
CONFIG.Quantization {Integer_Coefficients} \
CONFIG.RateSpecification {Frequency_Specification} \
CONFIG.Sample_Frequency {32} \
CONFIG.Zero_Pack_Factor {1} \
] $fir16d_32_2
# Create instance: fir4d_128_32, and set properties
set fir4d_128_32 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 fir4d_128_32 ]
set_property -dict [list \
CONFIG.Clock_Frequency {150} \
CONFIG.CoefficientVector {290, 485, 401, -1, -534, -863, -693, 0, 879, 1393, 1100, -1, -1362, -2136, -1672, 0, 2042, 3190, 2492, -1, -3048, -4778, -3754, 0, 4687, 7466, 5993, -1, -7986, -13367, -11481,\
0, 19474, 41538, 58937, 65535, 58937, 41538, 19474, 0, -11481, -13367, -7986, -1, 5993, 7466, 4687, 0, -3754, -4778, -3048, -1, 2492, 3190, 2042, 0, -1672, -2136, -1362, -1, 1100, 1393, 879, 0, -693, -863,\
-534, -1, 401, 485, 290} \
CONFIG.Coefficient_Fractional_Bits {0} \
CONFIG.Coefficient_Sets {1} \
CONFIG.Coefficient_Sign {Signed} \
CONFIG.Coefficient_Structure {Inferred} \
CONFIG.Coefficient_Width {18} \
CONFIG.ColumnConfig {9} \
CONFIG.Decimation_Rate {4} \
CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \
CONFIG.Filter_Type {Decimation} \
CONFIG.Interpolation_Rate {1} \
CONFIG.Number_Channels {1} \
CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \
CONFIG.Output_Width {16} \
CONFIG.Passband_Max {0.2} \
CONFIG.Quantization {Integer_Coefficients} \
CONFIG.RateSpecification {Frequency_Specification} \
CONFIG.Sample_Frequency {128} \
CONFIG.Zero_Pack_Factor {1} \
] $fir4d_128_32
# Create instance: fir4d_512_128, and set properties
set fir4d_512_128 [ create_bd_cell -type ip -vlnv xilinx.com:ip:fir_compiler:7.2 fir4d_512_128 ]
set_property -dict [list \
CONFIG.Clock_Frequency {256} \
CONFIG.CoefficientVector {686, 686, -1, -1220, -2211, -1971, 0, 3019, 5228, 4512, -1, -6757, -11838, -10560, 0, 18903, 40995, 58744, 65535, 58744, 40995, 18903, 0, -10560, -11838, -6757, -1, 4512,\
5228, 3019, 0, -1971, -2211, -1220, -1, 686, 686} \
CONFIG.Coefficient_Fanout {true} \
CONFIG.Coefficient_Fractional_Bits {0} \
CONFIG.Coefficient_Reload {false} \
CONFIG.Coefficient_Sets {1} \
CONFIG.Coefficient_Sign {Signed} \
CONFIG.Coefficient_Structure {Inferred} \
CONFIG.Coefficient_Width {18} \
CONFIG.ColumnConfig {10} \
CONFIG.Control_Broadcast_Fanout {true} \
CONFIG.Control_Column_Fanout {true} \
CONFIG.Control_LUT_Pipeline {true} \
CONFIG.Control_Path_Fanout {true} \
CONFIG.Data_Path_Broadcast {false} \
CONFIG.Data_Path_Fanout {true} \
CONFIG.Data_Width {16} \
CONFIG.Decimation_Rate {4} \
CONFIG.Disable_Half_Band_Centre_Tap {false} \
CONFIG.Filter_Architecture {Systolic_Multiply_Accumulate} \
CONFIG.Filter_Type {Decimation} \
CONFIG.Interpolation_Rate {1} \
CONFIG.No_BRAM_Read_First_Mode {true} \
CONFIG.No_SRL_Attributes {false} \
CONFIG.Number_Channels {1} \
CONFIG.Optimal_Column_Lengths {true} \
CONFIG.Optimization_Goal {Speed} \
CONFIG.Optimization_List {Data_Path_Fanout,Pre-Adder_Pipeline,Coefficient_Fanout,Control_Path_Fanout,Control_Column_Fanout,Control_Broadcast_Fanout,Control_LUT_Pipeline,No_BRAM_Read_First_Mode,Optimal_Column_Lengths,Other}\
\
CONFIG.Optimization_Selection {All} \
CONFIG.Other {true} \
CONFIG.Output_Rounding_Mode {Symmetric_Rounding_to_Zero} \
CONFIG.Output_Width {16} \
CONFIG.Passband_Max {0.20} \
CONFIG.Pre_Adder_Pipeline {true} \
CONFIG.Quantization {Integer_Coefficients} \
CONFIG.RateSpecification {Frequency_Specification} \
CONFIG.Sample_Frequency {512} \
CONFIG.Zero_Pack_Factor {1} \
] $fir4d_512_128
# Create interface connections
connect_bd_intf_net -intf_net Conn1 [get_bd_intf_pins S_AXIS_512] [get_bd_intf_pins adc_dwidth_converter/S_AXIS]
connect_bd_intf_net -intf_net Conn2 [get_bd_intf_pins M_AXIS_DATA] [get_bd_intf_pins fir16d_32_2/M_AXIS_DATA]
connect_bd_intf_net -intf_net adc00_cdc_fifo_M_AXIS [get_bd_intf_pins adc_cdc_fifo/M_AXIS] [get_bd_intf_pins fir4d_512_128/S_AXIS_DATA]
connect_bd_intf_net -intf_net adc00_dwidth_converter_M_AXIS [get_bd_intf_pins adc_cdc_fifo/S_AXIS] [get_bd_intf_pins adc_dwidth_converter/M_AXIS]
connect_bd_intf_net -intf_net adc_cdc_fifo1_M_AXIS [get_bd_intf_pins adc_cdc_fifo1/M_AXIS] [get_bd_intf_pins axis_x2_wrapper_0/s_axis]
connect_bd_intf_net -intf_net axis_x2_wrapper_0_m_axis [get_bd_intf_pins axis_x2_wrapper_0/m_axis] [get_bd_intf_pins fir4d_128_32/S_AXIS_DATA]
connect_bd_intf_net -intf_net fir4d_128_32_M_AXIS_DATA [get_bd_intf_pins fir16d_32_2/S_AXIS_DATA] [get_bd_intf_pins fir4d_128_32/M_AXIS_DATA]
connect_bd_intf_net -intf_net fir_4_down_M_AXIS_DATA [get_bd_intf_pins adc_cdc_fifo1/S_AXIS] [get_bd_intf_pins fir4d_512_128/M_AXIS_DATA]
# Create port connections
connect_bd_net -net aclk_1 [get_bd_pins axis_aclk_512] [get_bd_pins adc_cdc_fifo/s_axis_aclk] [get_bd_pins adc_dwidth_converter/aclk]
connect_bd_net -net aresetn_1 [get_bd_pins axis_aresetn_512] [get_bd_pins adc_cdc_fifo/s_axis_aresetn] [get_bd_pins adc_dwidth_converter/aresetn]
connect_bd_net -net m_axis_aclk1_1 [get_bd_pins axis_aclk_150] [get_bd_pins adc_cdc_fifo1/m_axis_aclk] [get_bd_pins axis_x2_wrapper_0/clk] [get_bd_pins fir16d_32_2/aclk] [get_bd_pins fir4d_128_32/aclk]
connect_bd_net -net m_axis_aclk_1 [get_bd_pins axis_aclk_256] [get_bd_pins adc_cdc_fifo/m_axis_aclk] [get_bd_pins adc_cdc_fifo1/s_axis_aclk] [get_bd_pins fir4d_512_128/aclk]
connect_bd_net -net reset_n_1 [get_bd_pins axis_aresetn_150] [get_bd_pins axis_x2_wrapper_0/reset_n]
connect_bd_net -net s_axis_aresetn_1 [get_bd_pins axis_aresetn_256] [get_bd_pins adc_cdc_fifo1/s_axis_aresetn]
# Restore current instance
current_bd_instance $oldCurInst