From 9ee08a531bbf5c35c10ea4e44742c167a3c94d09 Mon Sep 17 00:00:00 2001 From: pp482 Date: Wed, 6 Dec 2023 17:47:12 -0500 Subject: [PATCH] [yosys] Deprecate use of yosys backend in examples/ --- examples/ex02_cksum/cksum-translate | 16 +++++++------- examples/ex02_cksum/test/ChecksumVRTL_test.py | 18 +++++++-------- examples/ex03_proc/proc-sim | 6 ++--- examples/ex03_proc/proc-translate | 16 +++++++------- examples/ex03_proc/test/ProcVRTL_test.py | 12 +++++----- examples/ex04_xcel/proc-xcel-sim | 6 ++--- examples/ex04_xcel/proc-xcel-translate | 16 +++++++------- .../ex04_xcel/test/ChecksumXcelVRTL_test.py | 22 +++++++++---------- 8 files changed, 56 insertions(+), 56 deletions(-) diff --git a/examples/ex02_cksum/cksum-translate b/examples/ex02_cksum/cksum-translate index 2bfe1962f..3c773db8f 100755 --- a/examples/ex02_cksum/cksum-translate +++ b/examples/ex02_cksum/cksum-translate @@ -3,9 +3,9 @@ # cksum-translate [options] #========================================================================= # This script imports the RTL checksum unit from ChecksumRTL.py and -# translate it into yosys-compatible SystemVerilog. The generated -# SystemVerilog file will be dumped into the current directory ( if no -# output directory is specified ) or the specified output directory. +# translate it into SystemVerilog. The generated SystemVerilog file will +# be dumped into the current directory ( if no output directory is +# specified ) or the specified output directory. # # -h --help Display this message # @@ -18,8 +18,8 @@ import argparse import os import sys -# Import the translation pass from yosys backend -from pymtl3.passes.backends.yosys import YosysTranslationPass +# Import the translation pass from verilog backend +from pymtl3.passes.backends.verilog import VerilogTranslationPass # Hack to add project root to python path cur_dir = os.path.dirname( os.path.abspath( __file__ ) ) @@ -82,7 +82,7 @@ def main(): # Tag the checksum unit as to be translated - cksum.set_metadata( YosysTranslationPass.enable, True ) + cksum.set_metadata( VerilogTranslationPass.enable, True ) # Perform translation @@ -90,12 +90,12 @@ def main(): try: cksum.elaborate() - cksum.apply( YosysTranslationPass() ) + cksum.apply( VerilogTranslationPass() ) success = True finally: if success: path = os.getcwd() + \ - f"/{cksum.get_metadata(YosysTranslationPass.translated_filename)}" + f"/{cksum.get_metadata(VerilogTranslationPass.translated_filename)}" print("\nTranslation finished successfully!") print(f"You can find the generated SystemVerilog file at {path}.") else: diff --git a/examples/ex02_cksum/test/ChecksumVRTL_test.py b/examples/ex02_cksum/test/ChecksumVRTL_test.py index afbba1df8..14bceb12c 100644 --- a/examples/ex02_cksum/test/ChecksumVRTL_test.py +++ b/examples/ex02_cksum/test/ChecksumVRTL_test.py @@ -8,7 +8,7 @@ Date : June 6, 2019 """ from pymtl3 import * -from pymtl3.passes.backends.yosys import * +from pymtl3.passes.backends.verilog import * from pymtl3.passes.tracing import * from pymtl3.stdlib.test_utils.test_helpers import finalize_verilator @@ -32,10 +32,10 @@ def checksum_vrtl( words ): dut = ChecksumRTL() dut.elaborate() - # Translate the checksum unit and import it back in using the yosys + # Translate the checksum unit and import it back in using the verilog # backend - dut.set_metadata( YosysTranslationImportPass.enable, True ) - dut = YosysTranslationImportPass()( dut ) + dut.set_metadata( VerilogTranslationImportPass.enable, True ) + dut = VerilogTranslationImportPass()( dut ) # Create a simulator dut.elaborate() @@ -99,17 +99,17 @@ def run_sim( s, th ): # Check command line arguments for vcd dumping if vcd_file_name: th.set_metadata( VcdGenerationPass.vcd_file_name, vcd_file_name ) - th.dut.set_metadata( YosysVerilatorImportPass.vl_trace, True ) - th.dut.set_metadata( YosysVerilatorImportPass.vl_trace_filename, vcd_file_name ) + th.dut.set_metadata( VerilogVerilatorImportPass.vl_trace, True ) + th.dut.set_metadata( VerilogVerilatorImportPass.vl_trace_filename, vcd_file_name ) - # Translate the DUT and import it back in using the yosys backend. - th.dut.set_metadata( YosysTranslationImportPass.enable, True ) + # Translate the DUT and import it back in using the verilog backend. + th.dut.set_metadata( VerilogTranslationImportPass.enable, True ) # ''' TUTORIAL TASK '''''''''''''''''''''''''''''''''''''''''''''''''' # Apply the translation-import and simulation passes # ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''\/ - th = YosysTranslationImportPass()( th ) + th = VerilogTranslationImportPass()( th ) th.apply( DefaultPassGroup(linetrace=False) ) # ''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''''/\ diff --git a/examples/ex03_proc/proc-sim b/examples/ex03_proc/proc-sim index bb5ec93a9..6badb8455 100755 --- a/examples/ex03_proc/proc-sim +++ b/examples/ex03_proc/proc-sim @@ -121,10 +121,10 @@ def main(): # Apply translation pass and import pass if required if opts.translate: - from pymtl3.passes.backends.yosys import YosysTranslationImportPass + from pymtl3.passes.backends.verilog import VerilogTranslationImportPass model.elaborate() - model.proc.set_metadata( YosysTranslationImportPass.enable, True ) - model = YosysTranslationImportPass()( model ) + model.proc.set_metadata( VerilogTranslationImportPass.enable, True ) + model = VerilogTranslationImportPass()( model ) model.apply( DefaultPassGroup(linetrace=opts.trace) ) diff --git a/examples/ex03_proc/proc-translate b/examples/ex03_proc/proc-translate index 5f8ff7269..7256aaa11 100755 --- a/examples/ex03_proc/proc-translate +++ b/examples/ex03_proc/proc-translate @@ -3,9 +3,9 @@ # proc-translate [options] #========================================================================= # This script imports the RTL processor from ProcRTL.py and -# translate it into yosys-compatible SystemVerilog. The generated -# SystemVerilog file will be dumped into the current directory ( if no -# output directory is specified ) or the specified output directory. +# translate it into SystemVerilog. The generated SystemVerilog file will +# be dumped into the current directory ( if no output directory is +# specified ) or the specified output directory. # # -h --help Display this message # @@ -20,8 +20,8 @@ import argparse import os import sys -# Import the translation pass from yosys backend -from pymtl3.passes.backends.yosys import YosysTranslationPass +# Import the translation pass from verilog backend +from pymtl3.passes.backends.verilog import VerilogTranslationPass # Hack to add project root to python path cur_dir = os.path.dirname( os.path.abspath( __file__ ) ) @@ -84,7 +84,7 @@ def main(): # Tag the processor as to be translated - proc.set_metadata( YosysTranslationPass.enable, True ) + proc.set_metadata( VerilogTranslationPass.enable, True ) # Perform translation @@ -92,12 +92,12 @@ def main(): try: proc.elaborate() - proc.apply( YosysTranslationPass() ) + proc.apply( VerilogTranslationPass() ) success = True finally: if success: path = os.getcwd() + \ - f"/{proc.get_metadata(YosysTranslationPass.translated_filename)}" + f"/{proc.get_metadata(VerilogTranslationPass.translated_filename)}" print("\nTranslation finished successfully!") print(f"You can find the generated SystemVerilog file at {path}.") else: diff --git a/examples/ex03_proc/test/ProcVRTL_test.py b/examples/ex03_proc/test/ProcVRTL_test.py index 174fb2c0d..a339653f2 100644 --- a/examples/ex03_proc/test/ProcVRTL_test.py +++ b/examples/ex03_proc/test/ProcVRTL_test.py @@ -13,7 +13,7 @@ from examples.ex03_proc.ProcRTL import ProcRTL from pymtl3 import * -from pymtl3.passes.backends.yosys import * +from pymtl3.passes.backends.verilog import * from pymtl3.passes.tracing import * from pymtl3.stdlib.test_utils.test_helpers import finalize_verilator @@ -53,13 +53,13 @@ def run_sim( s, th, gen_test ): # Check command line arguments for vcd dumping if vcd_file_name: th.set_metadata( VcdGenerationPass.vcd_file_name, vcd_file_name ) - th.proc.set_metadata( YosysVerilatorImportPass.vl_trace, True ) - th.proc.set_metadata( YosysVerilatorImportPass.vl_trace_filename, vcd_file_name ) + th.proc.set_metadata( VerilogVerilatorImportPass.vl_trace, True ) + th.proc.set_metadata( VerilogVerilatorImportPass.vl_trace_filename, vcd_file_name ) - # Translate the DUT and import it back in using the yosys backend. - th.proc.set_metadata( YosysTranslationImportPass.enable, True ) + # Translate the DUT and import it back in using the verilog backend. + th.proc.set_metadata( VerilogTranslationImportPass.enable, True ) - th = YosysTranslationImportPass()( th ) + th = VerilogTranslationImportPass()( th ) # Create a simulator and run simulation th.apply( DefaultPassGroup(linetrace=True) ) diff --git a/examples/ex04_xcel/proc-xcel-sim b/examples/ex04_xcel/proc-xcel-sim index 81b56d58e..0bf50b8aa 100755 --- a/examples/ex04_xcel/proc-xcel-sim +++ b/examples/ex04_xcel/proc-xcel-sim @@ -207,10 +207,10 @@ def main(): # Apply translation pass and import pass if required if opts.translate: - from pymtl3.passes.backends.yosys import YosysTranslationImportPass + from pymtl3.passes.backends.verilog import VerilogTranslationImportPass model.elaborate() - model.dut.set_metadata( YosysTranslationImportPass.enable, True ) - model = YosysTranslationImportPass()( model ) + model.dut.set_metadata( VerilogTranslationImportPass.enable, True ) + model = VerilogTranslationImportPass()( model ) model.apply( DefaultPassGroup(linetrace=opts.trace) ) diff --git a/examples/ex04_xcel/proc-xcel-translate b/examples/ex04_xcel/proc-xcel-translate index e783b8913..8aa119bd1 100755 --- a/examples/ex04_xcel/proc-xcel-translate +++ b/examples/ex04_xcel/proc-xcel-translate @@ -3,9 +3,9 @@ # proc-xcel-translate [options] #========================================================================= # This script imports the RTL processor-accelerator unit and translate it -# into yosys-compatible SystemVerilog. The generated SystemVerilog file -# will be dumped into the current directory ( if no output directory is -# specified ) or the specified output directory. +# into SystemVerilog. The generated SystemVerilog file will be dumped into +# the current directory ( if no output directory is specified ) or the +# specified output directory. # # -h --help Display this message # @@ -34,8 +34,8 @@ from examples.ex03_proc.ProcRTL import ProcRTL from examples.ex04_xcel.ChecksumXcelRTL import ChecksumXcelRTL from examples.ex04_xcel.ProcXcel import ProcXcel -# Import the translation pass from yosys backend -from pymtl3.passes.backends.yosys import YosysTranslationPass +# Import the translation pass from Verilog backend +from pymtl3.passes.backends.verilog import VerilogTranslationPass #========================================================================= # Command line processing @@ -105,7 +105,7 @@ A valid output directory should be alloy-asic/designs//rtl # Tag the processor-accelerator unit as to be translated - proc_xcel.set_metadata( YosysTranslationPass.enable, True ) + proc_xcel.set_metadata( VerilogTranslationPass.enable, True ) # Perform translation @@ -113,12 +113,12 @@ A valid output directory should be alloy-asic/designs//rtl try: proc_xcel.elaborate() - proc_xcel.apply( YosysTranslationPass() ) + proc_xcel.apply( VerilogTranslationPass() ) success = True finally: if success: path = os.getcwd() + \ - f"/{proc_xcel.get_metadata(YosysTranslationPass.translated_filename)}" + f"/{proc_xcel.get_metadata(VerilogTranslationPass.translated_filename)}" if opts.output_dir: # Upon success, symlink the file to outputs/design.v which is the diff --git a/examples/ex04_xcel/test/ChecksumXcelVRTL_test.py b/examples/ex04_xcel/test/ChecksumXcelVRTL_test.py index 62989ef8c..aded7a31e 100644 --- a/examples/ex04_xcel/test/ChecksumXcelVRTL_test.py +++ b/examples/ex04_xcel/test/ChecksumXcelVRTL_test.py @@ -10,7 +10,7 @@ import pytest from pymtl3 import * -from pymtl3.passes.backends.yosys import YosysTranslationImportPass +from pymtl3.passes.backends.verilog import VerilogTranslationImportPass from pymtl3.stdlib.test_utils.test_helpers import finalize_verilator from ..ChecksumXcelRTL import ChecksumXcelRTL @@ -20,7 +20,7 @@ # Wrap Xcel into a function #------------------------------------------------------------------------- # [checksum_xcel_vrtl] creates an RTL checksum accelerator, translates -# it using the yosys backend and imports the translated model back, feeds +# it using the verilog backend and imports the translated model back, feeds # in the input, ticks it, gets the response, and returns the result. def checksum_xcel_vrtl( words ): @@ -30,10 +30,10 @@ def checksum_xcel_vrtl( words ): dut = ChecksumXcelRTL() dut.elaborate() - # Translate the checksum unit and import it back in using the yosys + # Translate the checksum unit and import it back in using the verilog # backend - dut.set_metadata( YosysTranslationImportPass.enable, True ) - dut = YosysTranslationImportPass()( dut ) + dut.set_metadata( VerilogTranslationImportPass.enable, True ) + dut = VerilogTranslationImportPass()( dut ) # Create a simulator dut.elaborate() @@ -92,19 +92,19 @@ def run_sim( s, th ): vcd_file_name = s.__class__.cmdline_opts["dump_vcd"] max_cycles = s.__class__.cmdline_opts["max_cycles"] or 10000 - # Translate the DUT and import it back in using the yosys backend. + # Translate the DUT and import it back in using the verilog backend. th.elaborate() # Check command line arguments for vcd dumping if vcd_file_name: th.set_metadata( VcdGenerationPass.vcd_file_name, vcd_file_name ) - th.dut.set_metadata( YosysVerilatorImportPass.vl_trace, True ) - th.dut.set_metadata( YosysVerilatorImportPass.vl_trace_filename, vcd_file_name ) + th.dut.set_metadata( VerilogVerilatorImportPass.vl_trace, True ) + th.dut.set_metadata( VerilogVerilatorImportPass.vl_trace_filename, vcd_file_name ) - # Translate the DUT and import it back in using the yosys backend. - th.dut.set_metadata( YosysTranslationImportPass.enable, True ) + # Translate the DUT and import it back in using the verilog backend. + th.dut.set_metadata( VerilogTranslationImportPass.enable, True ) - th = YosysTranslationImportPass()( th ) + th = VerilogTranslationImportPass()( th ) # Create a simulator th.apply( DefaultPassGroup() )