From 7d3af4482f1611a949a9e2170a089be7e870339c Mon Sep 17 00:00:00 2001 From: decaday Date: Wed, 13 Nov 2024 14:12:54 +0800 Subject: [PATCH 1/5] fix: "non-local impl definition" warning from recent nightlies --- src/lib.rs | 10 +++++++++- 1 file changed, 9 insertions(+), 1 deletion(-) diff --git a/src/lib.rs b/src/lib.rs index b0651ed..b341a5b 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -163,10 +163,18 @@ macro_rules! bind_interrupts { $(#[cfg($cond_handler)])? <$handler as $crate::interrupt::typelevel::Handler<$crate::interrupt::typelevel::$irq>>::on_interrupt(); + )* + } + $(#[cfg($cond_irq)])? + $crate::bind_interrupts!(@inner + $( $(#[cfg($cond_handler)])? unsafe impl $crate::interrupt::typelevel::Binding<$crate::interrupt::typelevel::$irq, $handler> for $name {} )* - } + ); )* }; + (@inner $($t:tt)*) => { + $($t)* + } } \ No newline at end of file From bee8e4681ad2ebf968d0e3c76af7774d18b83634 Mon Sep 17 00:00:00 2001 From: decaday Date: Wed, 13 Nov 2024 14:14:36 +0800 Subject: [PATCH 2/5] feat: enable ADC CKMode config --- src/adc/v1.rs | 8 ++++---- 1 file changed, 4 insertions(+), 4 deletions(-) diff --git a/src/adc/v1.rs b/src/adc/v1.rs index bc91491..a580d76 100644 --- a/src/adc/v1.rs +++ b/src/adc/v1.rs @@ -176,10 +176,10 @@ impl<'d, T: Instance> Adc<'d, T> { T::regs().cfgr1().modify(|reg| reg.set_res(resolution.into())); } - // pub fn set_ckmode(&mut self, ckmode: Ckmode) { - // // set ADC clock mode - // T::regs().cfgr2().modify(|reg| reg.set_ckmode(ckmode)); - // } + pub fn set_ckmode(&mut self, ckmode: Ckmode) { + // set ADC clock mode + T::regs().cfgr2().modify(|reg| reg.set_ckmode(ckmode)); + } pub async fn read(&mut self, channel: &mut impl AdcChannel) -> u16 { let ch_num = channel.channel(); From a8781735cc594dddf521032968c5f20c2564ac4f Mon Sep 17 00:00:00 2001 From: decaday Date: Wed, 13 Nov 2024 14:20:05 +0800 Subject: [PATCH 3/5] chore: remove unused --- build.rs | 174 ++++++++++++++++++++++++------------------------- src/dma.rs | 64 +++++++++--------- src/gpio.rs | 36 +++++----- src/i2c/mod.rs | 4 +- src/i2c/v1.rs | 24 +++---- src/lib.rs | 1 - src/macros.rs | 2 + src/rcc/mod.rs | 14 ++-- 8 files changed, 160 insertions(+), 159 deletions(-) diff --git a/build.rs b/build.rs index 1fdf278..9b1cfcf 100644 --- a/build.rs +++ b/build.rs @@ -1,4 +1,4 @@ -use std::collections::{BTreeMap, BTreeSet, HashMap, HashSet}; +use std::collections::{BTreeMap, BTreeSet, HashMap/*, HashSet*/}; use std::fmt::Write as _; use std::io::Write; use std::path::{Path, PathBuf}; @@ -9,7 +9,7 @@ use proc_macro2::{Ident, TokenStream}; use quote::{format_ident, quote}; use py32_metapac::metadata::ir::BitOffset; use py32_metapac::metadata::{ - MemoryRegionKind, PeripheralRccKernelClock, PeripheralRccRegister, PeripheralRegisters, StopMode, + MemoryRegionKind, PeripheralRccKernelClock, PeripheralRccRegister, PeripheralRegisters, /*StopMode,*/ // ALL_CHIPS, ALL_PERIPHERAL_VERSIONS, METADATA, }; @@ -135,36 +135,36 @@ fn main() { struct SplitFeature { feature_name: String, pin_name_with_c: String, - #[cfg(feature = "_split-pins-enabled")] - pin_name_without_c: String, + // #[cfg(feature = "_split-pins-enabled")] + // pin_name_without_c: String, } // Extra analog switch pins available on most H7 chips let split_features: Vec = vec![ - #[cfg(feature = "split-pa0")] - SplitFeature { - feature_name: "split-pa0".to_string(), - pin_name_with_c: "PA0_C".to_string(), - pin_name_without_c: "PA0".to_string(), - }, - #[cfg(feature = "split-pa1")] - SplitFeature { - feature_name: "split-pa1".to_string(), - pin_name_with_c: "PA1_C".to_string(), - pin_name_without_c: "PA1".to_string(), - }, - #[cfg(feature = "split-pc2")] - SplitFeature { - feature_name: "split-pc2".to_string(), - pin_name_with_c: "PC2_C".to_string(), - pin_name_without_c: "PC2".to_string(), - }, - #[cfg(feature = "split-pc3")] - SplitFeature { - feature_name: "split-pc3".to_string(), - pin_name_with_c: "PC3_C".to_string(), - pin_name_without_c: "PC3".to_string(), - }, + // #[cfg(feature = "split-pa0")] + // SplitFeature { + // feature_name: "split-pa0".to_string(), + // pin_name_with_c: "PA0_C".to_string(), + // pin_name_without_c: "PA0".to_string(), + // }, + // #[cfg(feature = "split-pa1")] + // SplitFeature { + // feature_name: "split-pa1".to_string(), + // pin_name_with_c: "PA1_C".to_string(), + // pin_name_without_c: "PA1".to_string(), + // }, + // #[cfg(feature = "split-pc2")] + // SplitFeature { + // feature_name: "split-pc2".to_string(), + // pin_name_with_c: "PC2_C".to_string(), + // pin_name_without_c: "PC2".to_string(), + // }, + // #[cfg(feature = "split-pc3")] + // SplitFeature { + // feature_name: "split-pc3".to_string(), + // pin_name_with_c: "PC3_C".to_string(), + // pin_name_without_c: "PC3".to_string(), + // }, ]; for split_feature in &split_features { @@ -1455,18 +1455,18 @@ fn main() { // Add the "_C" variant to the table. The solution is not optimal, though. // Adding them only when the corresponding GPIOx also appears. // This should avoid unintended side-effects as much as possible. - #[cfg(feature = "_split-pins-enabled")] - for split_feature in &split_features { - if split_feature.pin_name_without_c == pin_name { - pins_table.push(vec![ - split_feature.pin_name_with_c.to_string(), - p.name.to_string(), - port_num.to_string(), - pin_num.to_string(), - format!("EXTI{}", pin_num), - ]); - } - } + // #[cfg(feature = "_split-pins-enabled")] + // for split_feature in &split_features { + // if split_feature.pin_name_without_c == pin_name { + // pins_table.push(vec![ + // split_feature.pin_name_with_c.to_string(), + // p.name.to_string(), + // port_num.to_string(), + // pin_num.to_string(), + // format!("EXTI{}", pin_num), + // ]); + // } + // } } } @@ -1638,59 +1638,59 @@ fn main() { // ======== // Configs for multicore and for targeting groups of chips - fn get_chip_cfgs(chip_name: &str) -> Vec { - let mut cfgs = Vec::new(); + // fn get_chip_cfgs(chip_name: &str) -> Vec { + // let mut cfgs = Vec::new(); - // Multicore + // // Multicore - let mut s = chip_name.split('_'); - let mut chip_name: String = s.next().unwrap().to_string(); - let core_name = if let Some(c) = s.next() { - if !c.starts_with("CM") { - chip_name.push('_'); - chip_name.push_str(c); - None - } else { - Some(c) - } - } else { - None - }; + // let mut s = chip_name.split('_'); + // let mut chip_name: String = s.next().unwrap().to_string(); + // let core_name = if let Some(c) = s.next() { + // if !c.starts_with("CM") { + // chip_name.push('_'); + // chip_name.push_str(c); + // None + // } else { + // Some(c) + // } + // } else { + // None + // }; - if let Some(core) = core_name { - cfgs.push(format!("{}_{}", &chip_name[..chip_name.len() - 2], core)); - } + // if let Some(core) = core_name { + // cfgs.push(format!("{}_{}", &chip_name[..chip_name.len() - 2], core)); + // } - // Configs for targeting groups of chips - if &chip_name[..8] == "stm32wba" { - cfgs.push(chip_name[..8].to_owned()); // stm32wba - cfgs.push(chip_name[..10].to_owned()); // stm32wba52 - cfgs.push(format!("package_{}", &chip_name[10..11])); - cfgs.push(format!("flashsize_{}", &chip_name[11..12])); - } else { - if &chip_name[..8] == "stm32h7r" || &chip_name[..8] == "stm32h7s" { - cfgs.push("stm32h7rs".to_owned()); - } else { - cfgs.push(chip_name[..7].to_owned()); // stm32f4 - } - cfgs.push(chip_name[..9].to_owned()); // stm32f429 - cfgs.push(format!("{}x", &chip_name[..8])); // stm32f42x - cfgs.push(format!("{}x{}", &chip_name[..7], &chip_name[8..9])); // stm32f4x9 - cfgs.push(format!("package_{}", &chip_name[9..10])); - cfgs.push(format!("flashsize_{}", &chip_name[10..11])); - } + // // Configs for targeting groups of chips + // if &chip_name[..8] == "stm32wba" { + // cfgs.push(chip_name[..8].to_owned()); // stm32wba + // cfgs.push(chip_name[..10].to_owned()); // stm32wba52 + // cfgs.push(format!("package_{}", &chip_name[10..11])); + // cfgs.push(format!("flashsize_{}", &chip_name[11..12])); + // } else { + // if &chip_name[..8] == "stm32h7r" || &chip_name[..8] == "stm32h7s" { + // cfgs.push("stm32h7rs".to_owned()); + // } else { + // cfgs.push(chip_name[..7].to_owned()); // stm32f4 + // } + // cfgs.push(chip_name[..9].to_owned()); // stm32f429 + // cfgs.push(format!("{}x", &chip_name[..8])); // stm32f42x + // cfgs.push(format!("{}x{}", &chip_name[..7], &chip_name[8..9])); // stm32f4x9 + // cfgs.push(format!("package_{}", &chip_name[9..10])); + // cfgs.push(format!("flashsize_{}", &chip_name[10..11])); + // } - // Mark the L4+ chips as they have many differences to regular L4. - if &chip_name[..7] == "stm32l4" { - if "pqrs".contains(&chip_name[7..8]) { - cfgs.push("stm32l4_plus".to_owned()); - } else { - cfgs.push("stm32l4_nonplus".to_owned()); - } - } + // // Mark the L4+ chips as they have many differences to regular L4. + // if &chip_name[..7] == "stm32l4" { + // if "pqrs".contains(&chip_name[7..8]) { + // cfgs.push("stm32l4_plus".to_owned()); + // } else { + // cfgs.push("stm32l4_nonplus".to_owned()); + // } + // } - cfgs - } + // cfgs + // } // cfgs.enable_all(&get_chip_cfgs(&chip_name)); // for &chip_name in ALL_CHIPS.iter() { diff --git a/src/dma.rs b/src/dma.rs index 9f37703..a8e4b13 100644 --- a/src/dma.rs +++ b/src/dma.rs @@ -25,12 +25,12 @@ use embassy_hal_internal::{impl_peripheral, Peripheral}; -#[derive(Debug, Copy, Clone, PartialEq, Eq)] -#[cfg_attr(feature = "defmt", derive(defmt::Format))] -enum Dir { - MemoryToPeripheral, - PeripheralToMemory, -} +// #[derive(Debug, Copy, Clone, PartialEq, Eq)] +// #[cfg_attr(feature = "defmt", derive(defmt::Format))] +// enum Dir { +// MemoryToPeripheral, +// PeripheralToMemory, +// } // /// DMA request type alias. (also known as DMA channel number in some chips) // #[cfg(any(dma_v2, bdma_v2, gpdma, dmamux))] @@ -43,10 +43,10 @@ pub(crate) trait SealedChannel { fn id(&self) -> u8; } -pub(crate) trait ChannelInterrupt { - #[cfg_attr(not(feature = "rt"), allow(unused))] - unsafe fn on_irq(); -} +// pub(crate) trait ChannelInterrupt { +// #[cfg_attr(not(feature = "rt"), allow(unused))] +// unsafe fn on_irq(); +// } /// DMA channel. #[allow(private_bounds)] @@ -62,28 +62,28 @@ pub trait Channel: SealedChannel + Peripheral

+ Into + 'st } } -macro_rules! dma_channel_impl { - ($channel_peri:ident, $index:expr) => { - impl crate::dma::SealedChannel for crate::peripherals::$channel_peri { - fn id(&self) -> u8 { - $index - } - } - impl crate::dma::ChannelInterrupt for crate::peripherals::$channel_peri { - unsafe fn on_irq() { - crate::dma::AnyChannel { id: $index }.on_irq(); - } - } - - impl crate::dma::Channel for crate::peripherals::$channel_peri {} - - impl From for crate::dma::AnyChannel { - fn from(x: crate::peripherals::$channel_peri) -> Self { - crate::dma::Channel::degrade(x) - } - } - }; -} +// macro_rules! dma_channel_impl { +// ($channel_peri:ident, $index:expr) => { +// impl crate::dma::SealedChannel for crate::peripherals::$channel_peri { +// fn id(&self) -> u8 { +// $index +// } +// } +// impl crate::dma::ChannelInterrupt for crate::peripherals::$channel_peri { +// unsafe fn on_irq() { +// crate::dma::AnyChannel { id: $index }.on_irq(); +// } +// } + +// impl crate::dma::Channel for crate::peripherals::$channel_peri {} + +// impl From for crate::dma::AnyChannel { +// fn from(x: crate::peripherals::$channel_peri) -> Self { +// crate::dma::Channel::degrade(x) +// } +// } +// }; +// } /// Type-erased DMA channel. pub struct AnyChannel { diff --git a/src/gpio.rs b/src/gpio.rs index 2a2c575..b1c4d88 100644 --- a/src/gpio.rs +++ b/src/gpio.rs @@ -543,19 +543,19 @@ fn set_as_analog(pin_port: u8) { r.moder().modify(|w| w.set_moder(n, vals::Moder::ANALOG)); } -#[inline(never)] -fn get_pull(pin_port: u8) -> Pull { - let pin = unsafe { AnyPin::steal(pin_port) }; - let r = pin.block(); - let n = pin._pin() as usize; - - return match r.pupdr().read().pupdr(n) { - vals::Pupdr::FLOATING => Pull::None, - vals::Pupdr::PULLDOWN => Pull::Down, - vals::Pupdr::PULLUP => Pull::Up, - vals::Pupdr::_RESERVED_3 => Pull::None, - }; -} +// #[inline(never)] +// fn get_pull(pin_port: u8) -> Pull { +// let pin = unsafe { AnyPin::steal(pin_port) }; +// let r = pin.block(); +// let n = pin._pin() as usize; + +// return match r.pupdr().read().pupdr(n) { +// vals::Pupdr::FLOATING => Pull::None, +// vals::Pupdr::PULLDOWN => Pull::Down, +// vals::Pupdr::PULLUP => Pull::Up, +// vals::Pupdr::_RESERVED_3 => Pull::None, +// }; +// } pub(crate) trait SealedPin { fn pin_port(&self) -> u8; @@ -611,11 +611,11 @@ pub(crate) trait SealedPin { self.set_as_analog(); } - /// Get the pull-up configuration. - #[inline] - fn pull(&self) -> Pull { - critical_section::with(|_| get_pull(self.pin_port())) - } + // /// Get the pull-up configuration. + // #[inline] + // fn pull(&self) -> Pull { + // critical_section::with(|_| get_pull(self.pin_port())) + // } } /// GPIO pin trait. diff --git a/src/i2c/mod.rs b/src/i2c/mod.rs index abd3de9..f1a122e 100644 --- a/src/i2c/mod.rs +++ b/src/i2c/mod.rs @@ -99,7 +99,7 @@ impl Config { /// I2C driver. pub struct I2c<'d, M: Mode> { info: &'static Info, - state: &'static State, + _state: &'static State, kernel_clock: Hertz, scl: Option>, sda: Option>, @@ -171,7 +171,7 @@ impl<'d, M: Mode> I2c<'d, M> { let mut this = Self { info: T::info(), - state: T::state(), + _state: T::state(), kernel_clock: T::frequency(), scl, sda, diff --git a/src/i2c/v1.rs b/src/i2c/v1.rs index 561e09f..47519e6 100644 --- a/src/i2c/v1.rs +++ b/src/i2c/v1.rs @@ -4,12 +4,12 @@ //! //! All other devices (as of 2023-12-28) use [`v2`](super::v2) instead. -use core::future::poll_fn; -use core::task::Poll; +// use core::future::poll_fn; +// use core::task::Poll; use embassy_embedded_hal::SetConfig; -use embassy_futures::select::{select, Either}; -use embassy_hal_internal::drop::OnDrop; +// use embassy_futures::select::{select, Either}; +// use embassy_hal_internal::drop::OnDrop; use embedded_hal_1::i2c::Operation; use super::*; @@ -343,15 +343,15 @@ impl<'d, M: PeriMode> I2c<'d, M> { Ok(()) } - // Async + // // Async - #[inline] // pretty sure this should always be inlined - fn enable_interrupts(info: &'static Info) -> () { - info.regs.cr2().modify(|w| { - w.set_iterren(true); - w.set_itevten(true); - }); - } + // #[inline] // pretty sure this should always be inlined + // fn enable_interrupts(info: &'static Info) -> () { + // info.regs.cr2().modify(|w| { + // w.set_iterren(true); + // w.set_itevten(true); + // }); + // } } // impl<'d> I2c<'d, Async> { diff --git a/src/lib.rs b/src/lib.rs index b341a5b..ce159f3 100644 --- a/src/lib.rs +++ b/src/lib.rs @@ -6,7 +6,6 @@ mod fmt; include!(concat!(env!("OUT_DIR"), "/_macros.rs")); mod macros; -use macros::*; pub use py32_metapac as pac; diff --git a/src/macros.rs b/src/macros.rs index ae53deb..024df12 100644 --- a/src/macros.rs +++ b/src/macros.rs @@ -23,6 +23,7 @@ macro_rules! peri_trait { }; } +#[allow(unused)] macro_rules! peri_trait_impl { ($instance:ident, $info:expr) => { #[allow(private_interfaces)] @@ -85,6 +86,7 @@ macro_rules! dma_trait_impl { }; } +#[allow(unused)] macro_rules! new_dma { ($name:ident) => {{ let dma = $name.into_ref(); diff --git a/src/rcc/mod.rs b/src/rcc/mod.rs index a759a7f..4882661 100644 --- a/src/rcc/mod.rs +++ b/src/rcc/mod.rs @@ -86,13 +86,13 @@ pub(crate) struct RccInfo { // stop_mode: StopMode, } -#[cfg(feature = "low-power")] -#[allow(dead_code)] -pub(crate) enum StopMode { - Standby, - Stop2, - Stop1, -} +// #[cfg(feature = "low-power")] +// #[allow(dead_code)] +// pub(crate) enum StopMode { +// Standby, +// Stop2, +// Stop1, +// } impl RccInfo { /// Safety: From 13b29832af0ef40a0ea5d8d79ddef9dc0198a6c3 Mon Sep 17 00:00:00 2001 From: decaday Date: Wed, 13 Nov 2024 14:25:36 +0800 Subject: [PATCH 4/5] docs: update readme --- README.md | 20 ++++++++++++++------ 1 file changed, 14 insertions(+), 6 deletions(-) diff --git a/README.md b/README.md index 2864d38..fff5134 100644 --- a/README.md +++ b/README.md @@ -46,19 +46,19 @@ For a full list of chip capabilities and peripherals, check the [py32-data](http | GPIO | | ✅ | | | | INTERRUPT | | ✅ | | | | DMA | N/A | | | | -| EXTI* | | ✅ | | | +| EXTI | | ✅+ | | | | USART | | | | | -| I2C* | | | | | -| SPI* | | | | | -| ADC* | | ✅ | | | +| I2C | | ✅ | | | +| SPI | | | | | +| ADC | | ✅+ | | | | RTC | | | | | | Timer(PWM) | | ✅ | | | -| USB/OTG | N/A | N/A | | | +| USB/OTG | N/A | N/A | | | - ✅ : Expected to work - ❌ : Not implemented - ❓ : Not tested -- `*` marks the async driver +- `+` : marks the async driver - TODO: I haven't got a dev board yet, help-wanted - N/A: Not available @@ -66,6 +66,14 @@ For a full list of chip capabilities and peripherals, check the [py32-data](http Too many... +- DMA Support (Channel Map, Codegen, API, RingBuffer, I2C...) + +- Other series + +- SPI, USART + +- ... + ## time-driver This crate provides an implementation of the Embassy `time-driver`. From c8f567cb0e9c18ff380aa68f1167fca66d88b435 Mon Sep 17 00:00:00 2001 From: decaday Date: Wed, 13 Nov 2024 14:25:58 +0800 Subject: [PATCH 5/5] style: cargo fmt --- examples/py32f030/src/bin/adc.rs | 2 +- examples/py32f030/src/bin/blinky.rs | 2 +- examples/py32f030/src/bin/button_exti.rs | 1 - examples/py32f030/src/bin/pwm.rs | 12 ++++++++++-- examples/py32f030/src/bin/rcc_48mhz.rs | 10 ++++++---- 5 files changed, 18 insertions(+), 9 deletions(-) diff --git a/examples/py32f030/src/bin/adc.rs b/examples/py32f030/src/bin/adc.rs index a7244c8..8d95798 100644 --- a/examples/py32f030/src/bin/adc.rs +++ b/examples/py32f030/src/bin/adc.rs @@ -4,10 +4,10 @@ use defmt::*; use embassy_executor::Spawner; +use embassy_time::Timer; use py32_hal::adc::{Adc, SampleTime}; use py32_hal::peripherals::ADC; use py32_hal::{adc, bind_interrupts}; -use embassy_time::Timer; use {defmt_rtt as _, panic_probe as _}; bind_interrupts!(struct Irqs { diff --git a/examples/py32f030/src/bin/blinky.rs b/examples/py32f030/src/bin/blinky.rs index 811143f..ad55219 100644 --- a/examples/py32f030/src/bin/blinky.rs +++ b/examples/py32f030/src/bin/blinky.rs @@ -3,9 +3,9 @@ #![feature(impl_trait_in_assoc_type)] use defmt::*; -use py32_hal::gpio::{Level, Output, Speed}; use embassy_executor::Spawner; use embassy_time::Timer; +use py32_hal::gpio::{Level, Output, Speed}; use {defmt_rtt as _, panic_halt as _}; // main is itself an async function. diff --git a/examples/py32f030/src/bin/button_exti.rs b/examples/py32f030/src/bin/button_exti.rs index 80b3e11..d81ed7e 100644 --- a/examples/py32f030/src/bin/button_exti.rs +++ b/examples/py32f030/src/bin/button_exti.rs @@ -28,4 +28,3 @@ async fn main(_spawner: Spawner) { info!("Released!"); } } - diff --git a/examples/py32f030/src/bin/pwm.rs b/examples/py32f030/src/bin/pwm.rs index 3b64885..7f272e0 100644 --- a/examples/py32f030/src/bin/pwm.rs +++ b/examples/py32f030/src/bin/pwm.rs @@ -4,10 +4,10 @@ use defmt::*; use embassy_executor::Spawner; +use embassy_time::Timer; use py32_hal::gpio::OutputType; use py32_hal::time::khz; use py32_hal::timer::simple_pwm::{PwmPin, SimplePwm}; -use embassy_time::Timer; use {defmt_rtt as _, panic_probe as _}; #[embassy_executor::main] @@ -16,7 +16,15 @@ async fn main(_spawner: Spawner) { info!("Hello World!"); let ch4_pin = PwmPin::new_ch4(p.PA1, OutputType::PushPull); - let mut pwm = SimplePwm::new(p.TIM1, None, None, None, Some(ch4_pin), khz(10), Default::default()); + let mut pwm = SimplePwm::new( + p.TIM1, + None, + None, + None, + Some(ch4_pin), + khz(10), + Default::default(), + ); let mut ch4 = pwm.ch4(); ch4.enable(); diff --git a/examples/py32f030/src/bin/rcc_48mhz.rs b/examples/py32f030/src/bin/rcc_48mhz.rs index 9ecf062..14facac 100644 --- a/examples/py32f030/src/bin/rcc_48mhz.rs +++ b/examples/py32f030/src/bin/rcc_48mhz.rs @@ -1,18 +1,20 @@ #![no_std] #![no_main] +use cortex_m_rt::entry; use defmt::*; use py32_hal::gpio::{Level, Output, Speed}; -use py32_hal::rcc::{PllSource, Pll, Sysclk}; +use py32_hal::rcc::{Pll, PllSource, Sysclk}; use py32_hal::time::Hertz; use {defmt_rtt as _, panic_halt as _}; -use cortex_m_rt::entry; #[entry] fn main() -> ! { let mut cfg: py32_hal::Config = Default::default(); cfg.rcc.hsi = Some(Hertz::mhz(24)); - cfg.rcc.pll = Some(Pll { src: PllSource::HSI }); + cfg.rcc.pll = Some(Pll { + src: PllSource::HSI, + }); cfg.rcc.sys = Sysclk::PLL; let p = py32_hal::init(cfg); @@ -30,4 +32,4 @@ fn main() -> ! { cortex_m::asm::delay(8_000_000); } -} \ No newline at end of file +}