feat: chips, peripheral_versions cfgs generate

Author: decaday

build.rs

@@ -10,7 +10,7 @@ use quote::{format_ident, quote};
 use py32_metapac::metadata::ir::BitOffset;
 use py32_metapac::metadata::{
     MemoryRegionKind, PeripheralRccKernelClock, PeripheralRccRegister, PeripheralRegisters, /*StopMode,*/
-    // ALL_CHIPS, ALL_PERIPHERAL_VERSIONS,
+    ALL_CHIPS, ALL_PERIPHERAL_VERSIONS,
     METADATA,
 };
 
@@ -43,12 +43,12 @@ fn main() {
         }
     }
 
-    // for &(kind, versions) in ALL_PERIPHERAL_VERSIONS.iter() {
-    //     cfgs.declare(kind);
-    //     for &version in versions.iter() {
-    //         cfgs.declare(format!("{}_{}", kind, version));
-    //     }
-    // }
+    for &(kind, versions) in ALL_PERIPHERAL_VERSIONS.iter() {
+        cfgs.declare(kind);
+        for &version in versions.iter() {
+            cfgs.declare(format!("{}_{}", kind, version));
+        }
+    }
 
     // ========
     // Generate singletons
@@ -561,7 +561,7 @@ fn main() {
                     .unwrap()
                     .byte_offset;
                 let reg_offset: u8 = (reg_offset / 4).try_into().unwrap();
-
+                
                 let bit_offset = &rcc_registers
                     .ir
                     .fieldsets
@@ -1635,64 +1635,53 @@ fn main() {
     // ========
     // Configs for multicore and for targeting groups of chips
 
-    // fn get_chip_cfgs(chip_name: &str) -> Vec<String> {
-    //     let mut cfgs = Vec::new();
+    fn get_chip_cfgs(chip_name: &str) -> Vec<String> {
+        let mut cfgs = Vec::new();
 
-    //     // Multicore
+        // Multicore
 
-    //     let mut s = chip_name.split('_');
-    //     let mut chip_name: String = s.next().unwrap().to_string();
-    //     let core_name = if let Some(c) = s.next() {
-    //         if !c.starts_with("CM") {
-    //             chip_name.push('_');
-    //             chip_name.push_str(c);
-    //             None
-    //         } else {
-    //             Some(c)
-    //         }
-    //     } else {
-    //         None
-    //     };
-
-    //     if let Some(core) = core_name {
-    //         cfgs.push(format!("{}_{}", &chip_name[..chip_name.len() - 2], core));
-    //     }
+        let mut s = chip_name.split('_');
+        let mut chip_name: String = s.next().unwrap().to_string();
+        let core_name = if let Some(c) = s.next() {
+            if !c.starts_with("CM") {
+                chip_name.push('_');
+                chip_name.push_str(c);
+                None
+            } else {
+                Some(c)
+            }
+        } else {
+            None
+        };
 
-    //     // Configs for targeting groups of chips
-    //     if &chip_name[..8] == "stm32wba" {
-    //         cfgs.push(chip_name[..8].to_owned()); // stm32wba
-    //         cfgs.push(chip_name[..10].to_owned()); // stm32wba52
-    //         cfgs.push(format!("package_{}", &chip_name[10..11]));
-    //         cfgs.push(format!("flashsize_{}", &chip_name[11..12]));
-    //     } else {
-    //         if &chip_name[..8] == "stm32h7r" || &chip_name[..8] == "stm32h7s" {
-    //             cfgs.push("stm32h7rs".to_owned());
-    //         } else {
-    //             cfgs.push(chip_name[..7].to_owned()); // stm32f4
-    //         }
-    //         cfgs.push(chip_name[..9].to_owned()); // stm32f429
-    //         cfgs.push(format!("{}x", &chip_name[..8])); // stm32f42x
-    //         cfgs.push(format!("{}x{}", &chip_name[..7], &chip_name[8..9])); // stm32f4x9
-    //         cfgs.push(format!("package_{}", &chip_name[9..10]));
-    //         cfgs.push(format!("flashsize_{}", &chip_name[10..11]));
-    //     }
+        if let Some(core) = core_name {
+            cfgs.push(format!("{}_{}", &chip_name[..chip_name.len() - 2], core));
+        }
 
-    //     // Mark the L4+ chips as they have many differences to regular L4.
-    //     if &chip_name[..7] == "stm32l4" {
-    //         if "pqrs".contains(&chip_name[7..8]) {
-    //             cfgs.push("stm32l4_plus".to_owned());
-    //         } else {
-    //             cfgs.push("stm32l4_nonplus".to_owned());
-    //         }
-    //     }
+        // Configs for targeting groups of chips
+        if &chip_name[..9] == "py32f002a" || &chip_name[..9] == "py32f002b" {
+            cfgs.push(chip_name[..6].to_owned()); // py32f0
+            cfgs.push(chip_name[..9].to_owned()); // py32f002a
+            // TODO
+        }
+        else {
+            cfgs.push(chip_name[..6].to_owned()); // py32f0
+            cfgs.push(chip_name[..8].to_owned()); // py32f030
+            cfgs.push(format!("package_{}", &chip_name[8..10]));
+            cfgs.push(format!("flashsize_{}", &chip_name[10..11]));
+        }
+        
+        // cfgs.push(format!("{}x", &chip_name[..8])); // stm32f42x
+        // cfgs.push(format!("{}x{}", &chip_name[..7], &chip_name[8..9])); // stm32f4x9
+        
 
-    //     cfgs
-    // }
+        cfgs
+    }
 
-    // cfgs.enable_all(&get_chip_cfgs(&chip_name));
-    // for &chip_name in ALL_CHIPS.iter() {
-    //     cfgs.declare_all(&get_chip_cfgs(&chip_name.to_ascii_lowercase()));
-    // }
+    cfgs.enable_all(&get_chip_cfgs(&chip_name));
+    for &chip_name in ALL_CHIPS.iter() {
+        cfgs.declare_all(&get_chip_cfgs(&chip_name.to_ascii_lowercase()));
+    }
 
     println!("cargo:rerun-if-changed=build.rs");
 }