From ecf8f3b5d6681d079cc815c4777fdfd2bdee52b6 Mon Sep 17 00:00:00 2001 From: Michael Rogenmoser Date: Thu, 22 Aug 2024 18:31:34 +0200 Subject: [PATCH] Add icache control registers --- Bender.yml | 2 + rtl/safety_island_top.sv | 129 ++- rtl/soc_ctrl/boot_addr_icache.patch | 23 + rtl/soc_ctrl/reg_html.css | 74 -- rtl/soc_ctrl/safety_soc_ctrl.html | 64 -- rtl/soc_ctrl/safety_soc_ctrl.md | 300 +++++++ rtl/soc_ctrl/safety_soc_ctrl_icache.h | 85 ++ rtl/soc_ctrl/safety_soc_ctrl_icache.md | 680 +++++++++++++++ .../safety_soc_ctrl_icache_reg_pkg.sv | 168 ++++ .../safety_soc_ctrl_icache_reg_top.sv | 813 ++++++++++++++++++ rtl/soc_ctrl/safety_soc_ctrl_regs.hjson | 3 +- .../safety_soc_ctrl_regs_icache.hjson | 126 +++ safed.mk | 14 +- 13 files changed, 2308 insertions(+), 173 deletions(-) create mode 100644 rtl/soc_ctrl/boot_addr_icache.patch delete mode 100644 rtl/soc_ctrl/reg_html.css delete mode 100644 rtl/soc_ctrl/safety_soc_ctrl.html create mode 100644 rtl/soc_ctrl/safety_soc_ctrl.md create mode 100644 rtl/soc_ctrl/safety_soc_ctrl_icache.h create mode 100644 rtl/soc_ctrl/safety_soc_ctrl_icache.md create mode 100644 rtl/soc_ctrl/safety_soc_ctrl_icache_reg_pkg.sv create mode 100644 rtl/soc_ctrl/safety_soc_ctrl_icache_reg_top.sv create mode 100644 rtl/soc_ctrl/safety_soc_ctrl_regs_icache.hjson diff --git a/Bender.yml b/Bender.yml index e0eebb8..e1bd72b 100644 --- a/Bender.yml +++ b/Bender.yml @@ -29,6 +29,7 @@ sources: # Level 1 - rtl/safety_island_pkg.sv - rtl/soc_ctrl/safety_soc_ctrl_reg_pkg.sv + - rtl/soc_ctrl/safety_soc_ctrl_icache_reg_pkg.sv - target: carfield files: - rtl/safety_island_bootrom_carfield.sv @@ -43,6 +44,7 @@ sources: # Level 2 - rtl/safety_core_wrap.sv - rtl/soc_ctrl/safety_soc_ctrl_reg_top.sv + - rtl/soc_ctrl/safety_soc_ctrl_icache_reg_top.sv # Level 3 - rtl/safety_island_top.sv - rtl/synth/safety_island_synth_pkg.sv diff --git a/rtl/safety_island_top.sv b/rtl/safety_island_top.sv index 0ae0e42..b5775b5 100644 --- a/rtl/safety_island_top.sv +++ b/rtl/safety_island_top.sv @@ -474,6 +474,10 @@ module safety_island_top import safety_island_pkg::*; #( .fetch_enable_i ( fetch_enable ) ); + logic icache_enable_prefetching, icache_flush_valid, icache_flush_ready; + snitch_icache_pkg::icache_l0_events_t icache_l0_events; + snitch_icache_pkg::icache_l1_events_t icache_l1_events; + // Instruction Cache for core if (SafetyIslandCfg.UseICache) begin : gen_icache logic sel_icache; @@ -553,11 +557,11 @@ module safety_island_top import safety_island_pkg::*; #( .fetch_rdata_o ( icache_obi_rsp[0].r.rdata ), .fetch_rerror_o ( icache_obi_rsp[0].r.err ), - .enable_prefetching_i('0), - .icache_l0_events_o (), - .icache_l1_events_o (), - .flush_valid_i ('0), - .flush_ready_o (), + .enable_prefetching_i( icache_enable_prefetching ), + .icache_l0_events_o ( icache_l0_events ), + .icache_l1_events_o ( icache_l1_events ), + .flush_valid_i ( icache_flush_valid ), + .flush_ready_o ( icache_flush_ready ), .sram_cfg_data_i ('0), .sram_cfg_tag_i ('0), @@ -582,6 +586,10 @@ module safety_island_top import safety_island_pkg::*; #( `OBI_ASSIGN_R_STRUCT(core_instr_obi_rsp.r, direct_instr_obi_rsp.r) assign core_instr_obi_rsp.gnt = direct_instr_obi_rsp.gnt; assign core_instr_obi_rsp.rvalid = direct_instr_obi_rsp.rvalid; + + assign icache_l0_events = '0; + assign icache_l1_events = '0; + assign icache_flush_ready = '0; end // ----------------- @@ -1003,15 +1011,6 @@ module safety_island_top import safety_island_pkg::*; #( assign soc_ctrl_obi_rsp.r.r_optional = '0; logic first_cycle; - safety_soc_ctrl_reg_pkg::safety_soc_ctrl_reg2hw_t soc_ctrl_reg2hw; - safety_soc_ctrl_reg_pkg::safety_soc_ctrl_hw2reg_t soc_ctrl_hw2reg; - // allow control of fetch_enable from hardware - assign soc_ctrl_hw2reg.bootmode.d = bootmode_i; - assign soc_ctrl_hw2reg.bootmode.de = first_cycle; - assign soc_ctrl_hw2reg.fetchen.d = bootmode_i == Jtag; - assign soc_ctrl_hw2reg.fetchen.de = first_cycle; - assign fetch_enable = soc_ctrl_reg2hw.fetchen.q | fetch_enable_i; - assign boot_addr = soc_ctrl_reg2hw.bootaddr.q; always_ff @(posedge clk_i or negedge rst_ni) begin : proc_initial_ff @@ -1022,19 +1021,95 @@ module safety_island_top import safety_island_pkg::*; #( end end - safety_soc_ctrl_reg_top #( - .reg_req_t( safety_reg_req_t ), - .reg_rsp_t( safety_reg_rsp_t ), - .BootAddrDefault ( PeriphBaseAddr + BootROMAddrOffset + 32'h80 ) - ) i_soc_ctrl ( - .clk_i, - .rst_ni, - .reg_req_i ( soc_ctrl_reg_req ), - .reg_rsp_o ( soc_ctrl_reg_rsp ), - .reg2hw ( soc_ctrl_reg2hw ), - .hw2reg ( soc_ctrl_hw2reg ), - .devmode_i ( 1'b0 ) - ); + if (SafetyIslandCfg.UseICache) begin : gen_soc_ctrl_icache_regs + safety_soc_ctrl_icache_reg_pkg::safety_soc_ctrl_icache_reg2hw_t soc_ctrl_reg2hw; + safety_soc_ctrl_icache_reg_pkg::safety_soc_ctrl_icache_hw2reg_t soc_ctrl_hw2reg; + safety_soc_ctrl_icache_reg_pkg::safety_soc_ctrl_icache_hw2reg_counters_mreg_t [8:0] counters_reg; + + // allow control of fetch_enable from hardware + assign soc_ctrl_hw2reg.bootmode.d = bootmode_i; + assign soc_ctrl_hw2reg.bootmode.de = first_cycle; + assign soc_ctrl_hw2reg.fetchen.d = bootmode_i == Jtag; + assign soc_ctrl_hw2reg.fetchen.de = first_cycle; + assign fetch_enable = soc_ctrl_reg2hw.fetchen.q | fetch_enable_i; + assign boot_addr = soc_ctrl_reg2hw.bootaddr.q; + + safety_soc_ctrl_icache_reg_top #( + .reg_req_t ( safety_reg_req_t ), + .reg_rsp_t ( safety_reg_rsp_t ), + .BootAddrDefault( PeriphBaseAddr + BootROMAddrOffset + 32'h80 ) + ) i_soc_ctrl ( + .clk_i, + .rst_ni, + .reg_req_i ( soc_ctrl_reg_req ), + .reg_rsp_o ( soc_ctrl_reg_rsp ), + .reg2hw ( soc_ctrl_reg2hw ), + .hw2reg ( soc_ctrl_hw2reg ), + .devmode_i ( 1'b0 ) + ); + + assign icache_enable_prefetching = soc_ctrl_reg2hw.icache_enable_prefetch.q; + assign icache_flush_valid = soc_ctrl_reg2hw.icache_flush.q & soc_ctrl_reg2hw.icache_flush.qe; + + assign soc_ctrl_hw2reg.icache_flush.d = ~icache_flush_ready; + assign soc_ctrl_hw2reg.icache_perfctr_ctrl.enable.de = 1'b0; + assign soc_ctrl_hw2reg.icache_perfctr_ctrl.enable.d = 1'b1; + assign soc_ctrl_hw2reg.icache_perfctr_ctrl.clear_all.d = 1'b0; + assign soc_ctrl_hw2reg.icache_perfctr_ctrl.clear_all.de = 1'b1; + assign soc_ctrl_hw2reg.counters = counters_reg; + + always_comb begin + for (int unsigned i = 0; i < 9; i++) begin + counters_reg[i].d = soc_ctrl_reg2hw.counters[i].q + 1; + counters_reg[i].de = '0; + end + + counters_reg[0].de = soc_ctrl_reg2hw.icache_perfctr_ctrl.enable.q & icache_l1_events.l1_miss; + counters_reg[1].de = soc_ctrl_reg2hw.icache_perfctr_ctrl.enable.q & icache_l1_events.l1_hit; + counters_reg[2].de = soc_ctrl_reg2hw.icache_perfctr_ctrl.enable.q & icache_l1_events.l1_stall; + counters_reg[3].de = soc_ctrl_reg2hw.icache_perfctr_ctrl.enable.q & icache_l1_events.l1_handler_stall; + counters_reg[4].de = soc_ctrl_reg2hw.icache_perfctr_ctrl.enable.q & icache_l0_events.l0_miss; + counters_reg[5].de = soc_ctrl_reg2hw.icache_perfctr_ctrl.enable.q & icache_l0_events.l0_hit; + counters_reg[6].de = soc_ctrl_reg2hw.icache_perfctr_ctrl.enable.q & icache_l0_events.l0_prefetch; + counters_reg[7].de = soc_ctrl_reg2hw.icache_perfctr_ctrl.enable.q & icache_l0_events.l0_double_hit; + counters_reg[8].de = soc_ctrl_reg2hw.icache_perfctr_ctrl.enable.q & icache_l0_events.l0_stall; + + if (soc_ctrl_reg2hw.icache_perfctr_ctrl.clear_all.q) begin + for (int unsigned i = 0; i < 9; i++) begin + counters_reg[i].d = '0; + counters_reg[i].de = 1'b1; + end + end + end + + end else begin : gen_soc_ctrl_regs + safety_soc_ctrl_reg_pkg::safety_soc_ctrl_reg2hw_t soc_ctrl_reg2hw; + safety_soc_ctrl_reg_pkg::safety_soc_ctrl_hw2reg_t soc_ctrl_hw2reg; + // allow control of fetch_enable from hardware + assign soc_ctrl_hw2reg.bootmode.d = bootmode_i; + assign soc_ctrl_hw2reg.bootmode.de = first_cycle; + assign soc_ctrl_hw2reg.fetchen.d = bootmode_i == Jtag; + assign soc_ctrl_hw2reg.fetchen.de = first_cycle; + assign fetch_enable = soc_ctrl_reg2hw.fetchen.q | fetch_enable_i; + assign boot_addr = soc_ctrl_reg2hw.bootaddr.q; + + safety_soc_ctrl_reg_top #( + .reg_req_t( safety_reg_req_t ), + .reg_rsp_t( safety_reg_rsp_t ), + .BootAddrDefault ( PeriphBaseAddr + BootROMAddrOffset + 32'h80 ) + ) i_soc_ctrl ( + .clk_i, + .rst_ni, + .reg_req_i ( soc_ctrl_reg_req ), + .reg_rsp_o ( soc_ctrl_reg_rsp ), + .reg2hw ( soc_ctrl_reg2hw ), + .hw2reg ( soc_ctrl_hw2reg ), + .devmode_i ( 1'b0 ) + ); + + assign icache_enable_prefetching = '0; + assign icache_flush_valid = '0; + end // Boot ROM safety_island_bootrom #( diff --git a/rtl/soc_ctrl/boot_addr_icache.patch b/rtl/soc_ctrl/boot_addr_icache.patch new file mode 100644 index 0000000..0db0699 --- /dev/null +++ b/rtl/soc_ctrl/boot_addr_icache.patch @@ -0,0 +1,23 @@ +diff --git a/rtl/soc_ctrl/safety_soc_ctrl_icache_reg_top.sv b/rtl/soc_ctrl/safety_soc_ctrl_icache_reg_top.sv +index 7aac4c6..8c9c575 100644 +--- a/rtl/soc_ctrl/safety_soc_ctrl_icache_reg_top.sv ++++ b/rtl/soc_ctrl/safety_soc_ctrl_icache_reg_top.sv +@@ -10,7 +10,8 @@ + module safety_soc_ctrl_icache_reg_top #( + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, +- parameter int AW = 6 ++ parameter int AW = 6, ++ parameter int unsigned BootAddrDefault = 32'h0 + ) ( + input logic clk_i, + input logic rst_ni, +@@ -128,7 +129,7 @@ module safety_soc_ctrl_icache_reg_top #( + prim_subreg #( + .DW (32), + .SWACCESS("RW"), +- .RESVAL (32'h1a000000) ++ .RESVAL (BootAddrDefault) + ) u_bootaddr ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), diff --git a/rtl/soc_ctrl/reg_html.css b/rtl/soc_ctrl/reg_html.css deleted file mode 100644 index 4cb48ed..0000000 --- a/rtl/soc_ctrl/reg_html.css +++ /dev/null @@ -1,74 +0,0 @@ -/* Stylesheet for reggen HTML register output */ -/* Copyright lowRISC contributors. */ -/* Licensed under the Apache License, Version 2.0, see LICENSE for details. */ -/* SPDX-License-Identifier: Apache-2.0 */ - -table.regpic { - width: 95%; - border-collapse: collapse; - margin-left:auto; - margin-right:auto; - table-layout:fixed; -} - -table.regdef { - border: 1px solid black; - width: 80%; - border-collapse: collapse; - margin-left:auto; - margin-right:auto; - table-layout:auto; -} - -table.regdef th { - border: 1px solid black; - font-family: sans-serif; - -} - -td.bitnum { - font-size: 60%; - text-align: center; -} - -td.unused { - border: 1px solid black; - background-color: gray; -} - -td.fname { - border: 1px solid black; - text-align: center; - font-family: sans-serif; -} - - -td.regbits, td.regperm, td.regrv { - border: 1px solid black; - text-align: center; - font-family: sans-serif; -} - -td.regde, td.regfn { - border: 1px solid black; -} - -table.cfgtable { - border: 1px solid black; - width: 80%; - border-collapse: collapse; - margin-left:auto; - margin-right:auto; - table-layout:auto; -} - -table.cfgtable th { - border: 1px solid black; - font-family: sans-serif; - font-weight: bold; -} - -table.cfgtable td { - border: 1px solid black; - font-family: sans-serif; -} diff --git a/rtl/soc_ctrl/safety_soc_ctrl.html b/rtl/soc_ctrl/safety_soc_ctrl.html deleted file mode 100644 index 07b4cfa..0000000 --- a/rtl/soc_ctrl/safety_soc_ctrl.html +++ /dev/null @@ -1,64 +0,0 @@ - - - - - - - - - - -
-
safety_soc_ctrl.bootaddr @ 0x0
-

Core Boot Address

-
Reset default = 0x1a000000, mask 0xffffffff
-
- - -
31302928272625242322212019181716
bootaddr...
1514131211109876543210
...bootaddr
BitsTypeResetNameDescription
31:0rw0x1a000000bootaddr

Boot Address

-
- - - - - -
-
safety_soc_ctrl.fetchen @ 0x4
-

Core Fetch Enable

-
Reset default = 0x0, mask 0x1
-
- - - -
31302928272625242322212019181716
 
1514131211109876543210
 fetchen
BitsTypeResetNameDescription
0rw0x0fetchen

Fetch Enable

-
- - - - - -
-
safety_soc_ctrl.corestatus @ 0x8
-

Core Return Status (return value, EOC)

-
Reset default = 0x0, mask 0xffffffff
-
- - -
31302928272625242322212019181716
core_status...
1514131211109876543210
...core_status
BitsTypeResetNameDescription
31:0rw0x0core_status

Core Return Status (EOC(bit[31]) and status(bit[30:0]))

-
- - - - - -
-
safety_soc_ctrl.bootmode @ 0xc
-

Core Boot Mode

-
Reset default = 0x0, mask 0x3
-
- - - -
31302928272625242322212019181716
 
1514131211109876543210
 bootmode
BitsTypeResetNameDescription
1:0rw0x0bootmode

Boot Mode

-
- diff --git a/rtl/soc_ctrl/safety_soc_ctrl.md b/rtl/soc_ctrl/safety_soc_ctrl.md new file mode 100644 index 0000000..94b5915 --- /dev/null +++ b/rtl/soc_ctrl/safety_soc_ctrl.md @@ -0,0 +1,300 @@ +## Summary + +| Name | Offset | Length | Description | +|:--------------------------------------------|:---------|---------:|:---------------------------------------| +| safety_soc_ctrl.[`bootaddr`](#bootaddr) | 0x0 | 4 | Core Boot Address | +| safety_soc_ctrl.[`fetchen`](#fetchen) | 0x4 | 4 | Core Fetch Enable | +| safety_soc_ctrl.[`corestatus`](#corestatus) | 0x8 | 4 | Core Return Status (return value, EOC) | +| safety_soc_ctrl.[`bootmode`](#bootmode) | 0xc | 4 | Core Boot Mode | + +## bootaddr +Core Boot Address +- Offset: `0x0` +- Reset default: `0x1a000000` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "bootaddr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:----------:|:---------|:--------------| +| 31:0 | rw | 0x1a000000 | bootaddr | Boot Address | + +## fetchen +Core Fetch Enable +- Offset: `0x4` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "fetchen", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | fetchen | Fetch Enable | + +## corestatus +Core Return Status (return value, EOC) +- Offset: `0x8` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "core_status", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:--------------------------------------------------------| +| 31:0 | rw | 0x0 | core_status | Core Return Status (EOC(bit[31]) and status(bit[30:0])) | + +## bootmode +Core Boot Mode +- Offset: `0xc` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "bootmode", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------|:--------------| +| 31:2 | | | | Reserved | +| 1:0 | rw | 0x0 | bootmode | Boot Mode | + +## Summary + +| Name | Offset | Length | Description | +|:--------------------------------------------|:---------|---------:|:---------------------------------------| +| safety_soc_ctrl.[`bootaddr`](#bootaddr) | 0x0 | 4 | Core Boot Address | +| safety_soc_ctrl.[`fetchen`](#fetchen) | 0x4 | 4 | Core Fetch Enable | +| safety_soc_ctrl.[`corestatus`](#corestatus) | 0x8 | 4 | Core Return Status (return value, EOC) | +| safety_soc_ctrl.[`bootmode`](#bootmode) | 0xc | 4 | Core Boot Mode | + +## bootaddr +Core Boot Address +- Offset: `0x0` +- Reset default: `0x1a000000` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "bootaddr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:----------:|:---------|:--------------| +| 31:0 | rw | 0x1a000000 | bootaddr | Boot Address | + +## fetchen +Core Fetch Enable +- Offset: `0x4` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "fetchen", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | fetchen | Fetch Enable | + +## corestatus +Core Return Status (return value, EOC) +- Offset: `0x8` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "core_status", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:--------------------------------------------------------| +| 31:0 | rw | 0x0 | core_status | Core Return Status (EOC(bit[31]) and status(bit[30:0])) | + +## bootmode +Core Boot Mode +- Offset: `0xc` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "bootmode", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------|:--------------| +| 31:2 | | | | Reserved | +| 1:0 | rw | 0x0 | bootmode | Boot Mode | + +## Summary + +| Name | Offset | Length | Description | +|:--------------------------------------------|:---------|---------:|:---------------------------------------| +| safety_soc_ctrl.[`bootaddr`](#bootaddr) | 0x0 | 4 | Core Boot Address | +| safety_soc_ctrl.[`fetchen`](#fetchen) | 0x4 | 4 | Core Fetch Enable | +| safety_soc_ctrl.[`corestatus`](#corestatus) | 0x8 | 4 | Core Return Status (return value, EOC) | +| safety_soc_ctrl.[`bootmode`](#bootmode) | 0xc | 4 | Core Boot Mode | + +## bootaddr +Core Boot Address +- Offset: `0x0` +- Reset default: `0x1a000000` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "bootaddr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:----------:|:---------|:--------------| +| 31:0 | rw | 0x1a000000 | bootaddr | Boot Address | + +## fetchen +Core Fetch Enable +- Offset: `0x4` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "fetchen", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | fetchen | Fetch Enable | + +## corestatus +Core Return Status (return value, EOC) +- Offset: `0x8` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "core_status", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:--------------------------------------------------------| +| 31:0 | rw | 0x0 | core_status | Core Return Status (EOC(bit[31]) and status(bit[30:0])) | + +## bootmode +Core Boot Mode +- Offset: `0xc` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "bootmode", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------|:--------------| +| 31:2 | | | | Reserved | +| 1:0 | rw | 0x0 | bootmode | Boot Mode | + +## Summary + +| Name | Offset | Length | Description | +|:--------------------------------------------|:---------|---------:|:---------------------------------------| +| safety_soc_ctrl.[`bootaddr`](#bootaddr) | 0x0 | 4 | Core Boot Address | +| safety_soc_ctrl.[`fetchen`](#fetchen) | 0x4 | 4 | Core Fetch Enable | +| safety_soc_ctrl.[`corestatus`](#corestatus) | 0x8 | 4 | Core Return Status (return value, EOC) | +| safety_soc_ctrl.[`bootmode`](#bootmode) | 0xc | 4 | Core Boot Mode | + +## bootaddr +Core Boot Address +- Offset: `0x0` +- Reset default: `0x1a000000` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "bootaddr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:----------:|:---------|:--------------| +| 31:0 | rw | 0x1a000000 | bootaddr | Boot Address | + +## fetchen +Core Fetch Enable +- Offset: `0x4` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "fetchen", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | fetchen | Fetch Enable | + +## corestatus +Core Return Status (return value, EOC) +- Offset: `0x8` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "core_status", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:--------------------------------------------------------| +| 31:0 | rw | 0x0 | core_status | Core Return Status (EOC(bit[31]) and status(bit[30:0])) | + +## bootmode +Core Boot Mode +- Offset: `0xc` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "bootmode", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------|:--------------| +| 31:2 | | | | Reserved | +| 1:0 | rw | 0x0 | bootmode | Boot Mode | + diff --git a/rtl/soc_ctrl/safety_soc_ctrl_icache.h b/rtl/soc_ctrl/safety_soc_ctrl_icache.h new file mode 100644 index 0000000..55f915e --- /dev/null +++ b/rtl/soc_ctrl/safety_soc_ctrl_icache.h @@ -0,0 +1,85 @@ +// Generated register defines for safety_soc_ctrl_icache + +// Copyright information found in source file: +// Copyright 2023 ETH Zurich and University of Bologna + +// Licensing information found in source file: +// +// SPDX-License-Identifier: SHL-0.51 + +#ifndef _SAFETY_SOC_CTRL_ICACHE_REG_DEFS_ +#define _SAFETY_SOC_CTRL_ICACHE_REG_DEFS_ + +#ifdef __cplusplus +extern "C" { +#endif +// Register width +#define SAFETY_SOC_CTRL_ICACHE_PARAM_REG_WIDTH 32 + +// Core Boot Address +#define SAFETY_SOC_CTRL_ICACHE_BOOTADDR_REG_OFFSET 0x0 + +// Core Fetch Enable +#define SAFETY_SOC_CTRL_ICACHE_FETCHEN_REG_OFFSET 0x4 +#define SAFETY_SOC_CTRL_ICACHE_FETCHEN_FETCHEN_BIT 0 + +// Core Return Status (return value, EOC) +#define SAFETY_SOC_CTRL_ICACHE_CORESTATUS_REG_OFFSET 0x8 + +// Core Boot Mode +#define SAFETY_SOC_CTRL_ICACHE_BOOTMODE_REG_OFFSET 0xc +#define SAFETY_SOC_CTRL_ICACHE_BOOTMODE_BOOTMODE_MASK 0x3 +#define SAFETY_SOC_CTRL_ICACHE_BOOTMODE_BOOTMODE_OFFSET 0 +#define SAFETY_SOC_CTRL_ICACHE_BOOTMODE_BOOTMODE_FIELD \ + ((bitfield_field32_t) { .mask = SAFETY_SOC_CTRL_ICACHE_BOOTMODE_BOOTMODE_MASK, .index = SAFETY_SOC_CTRL_ICACHE_BOOTMODE_BOOTMODE_OFFSET }) + +// Enable iCache prefetching +#define SAFETY_SOC_CTRL_ICACHE_ICACHE_ENABLE_PREFETCH_REG_OFFSET 0x10 +#define SAFETY_SOC_CTRL_ICACHE_ICACHE_ENABLE_PREFETCH_PREFETCH_ENABLE_BIT 0 + +// Flush iCache +#define SAFETY_SOC_CTRL_ICACHE_ICACHE_FLUSH_REG_OFFSET 0x14 +#define SAFETY_SOC_CTRL_ICACHE_ICACHE_FLUSH_FLUSH_BIT 0 + +// iCache Performance Counter Control +#define SAFETY_SOC_CTRL_ICACHE_ICACHE_PERFCTR_CTRL_REG_OFFSET 0x18 +#define SAFETY_SOC_CTRL_ICACHE_ICACHE_PERFCTR_CTRL_ENABLE_BIT 0 +#define SAFETY_SOC_CTRL_ICACHE_ICACHE_PERFCTR_CTRL_CLEAR_ALL_BIT 16 + +// Performance counters (common parameters) +#define SAFETY_SOC_CTRL_ICACHE_COUNTERS_COUNTER_FIELD_WIDTH 32 +#define SAFETY_SOC_CTRL_ICACHE_COUNTERS_COUNTER_FIELDS_PER_REG 1 +#define SAFETY_SOC_CTRL_ICACHE_COUNTERS_MULTIREG_COUNT 9 + +// Performance counters +#define SAFETY_SOC_CTRL_ICACHE_COUNTERS_0_REG_OFFSET 0x1c + +// Performance counters +#define SAFETY_SOC_CTRL_ICACHE_COUNTERS_1_REG_OFFSET 0x20 + +// Performance counters +#define SAFETY_SOC_CTRL_ICACHE_COUNTERS_2_REG_OFFSET 0x24 + +// Performance counters +#define SAFETY_SOC_CTRL_ICACHE_COUNTERS_3_REG_OFFSET 0x28 + +// Performance counters +#define SAFETY_SOC_CTRL_ICACHE_COUNTERS_4_REG_OFFSET 0x2c + +// Performance counters +#define SAFETY_SOC_CTRL_ICACHE_COUNTERS_5_REG_OFFSET 0x30 + +// Performance counters +#define SAFETY_SOC_CTRL_ICACHE_COUNTERS_6_REG_OFFSET 0x34 + +// Performance counters +#define SAFETY_SOC_CTRL_ICACHE_COUNTERS_7_REG_OFFSET 0x38 + +// Performance counters +#define SAFETY_SOC_CTRL_ICACHE_COUNTERS_8_REG_OFFSET 0x3c + +#ifdef __cplusplus +} // extern "C" +#endif +#endif // _SAFETY_SOC_CTRL_ICACHE_REG_DEFS_ +// End generated register defines for safety_soc_ctrl_icache \ No newline at end of file diff --git a/rtl/soc_ctrl/safety_soc_ctrl_icache.md b/rtl/soc_ctrl/safety_soc_ctrl_icache.md new file mode 100644 index 0000000..5ff42f7 --- /dev/null +++ b/rtl/soc_ctrl/safety_soc_ctrl_icache.md @@ -0,0 +1,680 @@ +## Summary + +| Name | Offset | Length | Description | +|:---------------------------------------------------------------------------|:---------|---------:|:---------------------------------------| +| safety_soc_ctrl_icache.[`bootaddr`](#bootaddr) | 0x0 | 4 | Core Boot Address | +| safety_soc_ctrl_icache.[`fetchen`](#fetchen) | 0x4 | 4 | Core Fetch Enable | +| safety_soc_ctrl_icache.[`corestatus`](#corestatus) | 0x8 | 4 | Core Return Status (return value, EOC) | +| safety_soc_ctrl_icache.[`bootmode`](#bootmode) | 0xc | 4 | Core Boot Mode | +| safety_soc_ctrl_icache.[`icache_enable_prefetch`](#icache_enable_prefetch) | 0x10 | 4 | Enable iCache prefetching | +| safety_soc_ctrl_icache.[`icache_flush`](#icache_flush) | 0x14 | 4 | Flush iCache | +| safety_soc_ctrl_icache.[`icache_perfctr_ctrl`](#icache_perfctr_ctrl) | 0x18 | 4 | iCache Performance Counter Control | +| safety_soc_ctrl_icache.[`counters_0`](#counters) | 0x1c | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_1`](#counters) | 0x20 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_2`](#counters) | 0x24 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_3`](#counters) | 0x28 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_4`](#counters) | 0x2c | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_5`](#counters) | 0x30 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_6`](#counters) | 0x34 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_7`](#counters) | 0x38 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_8`](#counters) | 0x3c | 4 | Performance counters | + +## bootaddr +Core Boot Address +- Offset: `0x0` +- Reset default: `0x1a000000` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "bootaddr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:----------:|:---------|:--------------| +| 31:0 | rw | 0x1a000000 | bootaddr | Boot Address | + +## fetchen +Core Fetch Enable +- Offset: `0x4` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "fetchen", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | fetchen | Fetch Enable | + +## corestatus +Core Return Status (return value, EOC) +- Offset: `0x8` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "core_status", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:--------------------------------------------------------| +| 31:0 | rw | 0x0 | core_status | Core Return Status (EOC(bit[31]) and status(bit[30:0])) | + +## bootmode +Core Boot Mode +- Offset: `0xc` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "bootmode", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------|:--------------| +| 31:2 | | | | Reserved | +| 1:0 | rw | 0x0 | bootmode | Boot Mode | + +## icache_enable_prefetch +Enable iCache prefetching +- Offset: `0x10` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "prefetch_enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------|:-------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x1 | prefetch_enable | Enable prefetching | + +## icache_flush +Flush iCache +- Offset: `0x14` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "flush", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | flush | Flush | + +## icache_perfctr_ctrl +iCache Performance Counter Control +- Offset: `0x18` +- Reset default: `0x1` +- Reset mask: `0x10001` + +### Fields + +```wavejson +{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 15}, {"name": "clear_all", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 15}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------|:-------------------------------| +| 31:17 | | | | Reserved | +| 16 | rw | 0x0 | clear_all | Clear all performance counters | +| 15:1 | | | | Reserved | +| 0 | rw | 0x1 | enable | Enable performance counters | + +## counters +Performance counters +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-----------|:---------| +| counters_0 | 0x1c | +| counters_1 | 0x20 | +| counters_2 | 0x24 | +| counters_3 | 0x28 | +| counters_4 | 0x2c | +| counters_5 | 0x30 | +| counters_6 | 0x34 | +| counters_7 | 0x38 | +| counters_8 | 0x3c | + + +### Fields + +```wavejson +{"reg": [{"name": "counter", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:--------------| +| 31:0 | rw0c | 0x0 | counter | | + +## Summary + +| Name | Offset | Length | Description | +|:---------------------------------------------------------------------------|:---------|---------:|:---------------------------------------| +| safety_soc_ctrl_icache.[`bootaddr`](#bootaddr) | 0x0 | 4 | Core Boot Address | +| safety_soc_ctrl_icache.[`fetchen`](#fetchen) | 0x4 | 4 | Core Fetch Enable | +| safety_soc_ctrl_icache.[`corestatus`](#corestatus) | 0x8 | 4 | Core Return Status (return value, EOC) | +| safety_soc_ctrl_icache.[`bootmode`](#bootmode) | 0xc | 4 | Core Boot Mode | +| safety_soc_ctrl_icache.[`icache_enable_prefetch`](#icache_enable_prefetch) | 0x10 | 4 | Enable iCache prefetching | +| safety_soc_ctrl_icache.[`icache_flush`](#icache_flush) | 0x14 | 4 | Flush iCache | +| safety_soc_ctrl_icache.[`icache_perfctr_ctrl`](#icache_perfctr_ctrl) | 0x18 | 4 | iCache Performance Counter Control | +| safety_soc_ctrl_icache.[`counters_0`](#counters) | 0x1c | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_1`](#counters) | 0x20 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_2`](#counters) | 0x24 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_3`](#counters) | 0x28 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_4`](#counters) | 0x2c | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_5`](#counters) | 0x30 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_6`](#counters) | 0x34 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_7`](#counters) | 0x38 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_8`](#counters) | 0x3c | 4 | Performance counters | + +## bootaddr +Core Boot Address +- Offset: `0x0` +- Reset default: `0x1a000000` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "bootaddr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:----------:|:---------|:--------------| +| 31:0 | rw | 0x1a000000 | bootaddr | Boot Address | + +## fetchen +Core Fetch Enable +- Offset: `0x4` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "fetchen", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | fetchen | Fetch Enable | + +## corestatus +Core Return Status (return value, EOC) +- Offset: `0x8` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "core_status", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:--------------------------------------------------------| +| 31:0 | rw | 0x0 | core_status | Core Return Status (EOC(bit[31]) and status(bit[30:0])) | + +## bootmode +Core Boot Mode +- Offset: `0xc` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "bootmode", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------|:--------------| +| 31:2 | | | | Reserved | +| 1:0 | rw | 0x0 | bootmode | Boot Mode | + +## icache_enable_prefetch +Enable iCache prefetching +- Offset: `0x10` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "prefetch_enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------|:-------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x1 | prefetch_enable | Enable prefetching | + +## icache_flush +Flush iCache +- Offset: `0x14` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "flush", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | flush | Flush | + +## icache_perfctr_ctrl +iCache Performance Counter Control +- Offset: `0x18` +- Reset default: `0x1` +- Reset mask: `0x10001` + +### Fields + +```wavejson +{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 15}, {"name": "clear_all", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 15}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------|:-------------------------------| +| 31:17 | | | | Reserved | +| 16 | rw | 0x0 | clear_all | Clear all performance counters | +| 15:1 | | | | Reserved | +| 0 | rw | 0x1 | enable | Enable performance counters | + +## counters +Performance counters +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-----------|:---------| +| counters_0 | 0x1c | +| counters_1 | 0x20 | +| counters_2 | 0x24 | +| counters_3 | 0x28 | +| counters_4 | 0x2c | +| counters_5 | 0x30 | +| counters_6 | 0x34 | +| counters_7 | 0x38 | +| counters_8 | 0x3c | + + +### Fields + +```wavejson +{"reg": [{"name": "counter", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:--------------| +| 31:0 | rw0c | 0x0 | counter | | + +## Summary + +| Name | Offset | Length | Description | +|:---------------------------------------------------------------------------|:---------|---------:|:---------------------------------------| +| safety_soc_ctrl_icache.[`bootaddr`](#bootaddr) | 0x0 | 4 | Core Boot Address | +| safety_soc_ctrl_icache.[`fetchen`](#fetchen) | 0x4 | 4 | Core Fetch Enable | +| safety_soc_ctrl_icache.[`corestatus`](#corestatus) | 0x8 | 4 | Core Return Status (return value, EOC) | +| safety_soc_ctrl_icache.[`bootmode`](#bootmode) | 0xc | 4 | Core Boot Mode | +| safety_soc_ctrl_icache.[`icache_enable_prefetch`](#icache_enable_prefetch) | 0x10 | 4 | Enable iCache prefetching | +| safety_soc_ctrl_icache.[`icache_flush`](#icache_flush) | 0x14 | 4 | Flush iCache | +| safety_soc_ctrl_icache.[`icache_perfctr_ctrl`](#icache_perfctr_ctrl) | 0x18 | 4 | iCache Performance Counter Control | +| safety_soc_ctrl_icache.[`counters_0`](#counters) | 0x1c | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_1`](#counters) | 0x20 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_2`](#counters) | 0x24 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_3`](#counters) | 0x28 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_4`](#counters) | 0x2c | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_5`](#counters) | 0x30 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_6`](#counters) | 0x34 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_7`](#counters) | 0x38 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_8`](#counters) | 0x3c | 4 | Performance counters | + +## bootaddr +Core Boot Address +- Offset: `0x0` +- Reset default: `0x1a000000` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "bootaddr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:----------:|:---------|:--------------| +| 31:0 | rw | 0x1a000000 | bootaddr | Boot Address | + +## fetchen +Core Fetch Enable +- Offset: `0x4` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "fetchen", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | fetchen | Fetch Enable | + +## corestatus +Core Return Status (return value, EOC) +- Offset: `0x8` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "core_status", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:--------------------------------------------------------| +| 31:0 | rw | 0x0 | core_status | Core Return Status (EOC(bit[31]) and status(bit[30:0])) | + +## bootmode +Core Boot Mode +- Offset: `0xc` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "bootmode", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------|:--------------| +| 31:2 | | | | Reserved | +| 1:0 | rw | 0x0 | bootmode | Boot Mode | + +## icache_enable_prefetch +Enable iCache prefetching +- Offset: `0x10` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "prefetch_enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------|:-------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x1 | prefetch_enable | Enable prefetching | + +## icache_flush +Flush iCache +- Offset: `0x14` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "flush", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | flush | Flush | + +## icache_perfctr_ctrl +iCache Performance Counter Control +- Offset: `0x18` +- Reset default: `0x1` +- Reset mask: `0x10001` + +### Fields + +```wavejson +{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 15}, {"name": "clear_all", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 15}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------|:-------------------------------| +| 31:17 | | | | Reserved | +| 16 | rw | 0x0 | clear_all | Clear all performance counters | +| 15:1 | | | | Reserved | +| 0 | rw | 0x1 | enable | Enable performance counters | + +## counters +Performance counters +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-----------|:---------| +| counters_0 | 0x1c | +| counters_1 | 0x20 | +| counters_2 | 0x24 | +| counters_3 | 0x28 | +| counters_4 | 0x2c | +| counters_5 | 0x30 | +| counters_6 | 0x34 | +| counters_7 | 0x38 | +| counters_8 | 0x3c | + + +### Fields + +```wavejson +{"reg": [{"name": "counter", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:--------------| +| 31:0 | rw0c | 0x0 | counter | | + +## Summary + +| Name | Offset | Length | Description | +|:---------------------------------------------------------------------------|:---------|---------:|:---------------------------------------| +| safety_soc_ctrl_icache.[`bootaddr`](#bootaddr) | 0x0 | 4 | Core Boot Address | +| safety_soc_ctrl_icache.[`fetchen`](#fetchen) | 0x4 | 4 | Core Fetch Enable | +| safety_soc_ctrl_icache.[`corestatus`](#corestatus) | 0x8 | 4 | Core Return Status (return value, EOC) | +| safety_soc_ctrl_icache.[`bootmode`](#bootmode) | 0xc | 4 | Core Boot Mode | +| safety_soc_ctrl_icache.[`icache_enable_prefetch`](#icache_enable_prefetch) | 0x10 | 4 | Enable iCache prefetching | +| safety_soc_ctrl_icache.[`icache_flush`](#icache_flush) | 0x14 | 4 | Flush iCache | +| safety_soc_ctrl_icache.[`icache_perfctr_ctrl`](#icache_perfctr_ctrl) | 0x18 | 4 | iCache Performance Counter Control | +| safety_soc_ctrl_icache.[`counters_0`](#counters) | 0x1c | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_1`](#counters) | 0x20 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_2`](#counters) | 0x24 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_3`](#counters) | 0x28 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_4`](#counters) | 0x2c | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_5`](#counters) | 0x30 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_6`](#counters) | 0x34 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_7`](#counters) | 0x38 | 4 | Performance counters | +| safety_soc_ctrl_icache.[`counters_8`](#counters) | 0x3c | 4 | Performance counters | + +## bootaddr +Core Boot Address +- Offset: `0x0` +- Reset default: `0x1a000000` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "bootaddr", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:----------:|:---------|:--------------| +| 31:0 | rw | 0x1a000000 | bootaddr | Boot Address | + +## fetchen +Core Fetch Enable +- Offset: `0x4` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "fetchen", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 90}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | fetchen | Fetch Enable | + +## corestatus +Core Return Status (return value, EOC) +- Offset: `0x8` +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Fields + +```wavejson +{"reg": [{"name": "core_status", "bits": 32, "attr": ["rw"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:------------|:--------------------------------------------------------| +| 31:0 | rw | 0x0 | core_status | Core Return Status (EOC(bit[31]) and status(bit[30:0])) | + +## bootmode +Core Boot Mode +- Offset: `0xc` +- Reset default: `0x0` +- Reset mask: `0x3` + +### Fields + +```wavejson +{"reg": [{"name": "bootmode", "bits": 2, "attr": ["rw"], "rotate": -90}, {"bits": 30}], "config": {"lanes": 1, "fontsize": 10, "vspace": 100}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:---------|:--------------| +| 31:2 | | | | Reserved | +| 1:0 | rw | 0x0 | bootmode | Boot Mode | + +## icache_enable_prefetch +Enable iCache prefetching +- Offset: `0x10` +- Reset default: `0x1` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "prefetch_enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 170}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------------|:-------------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x1 | prefetch_enable | Enable prefetching | + +## icache_flush +Flush iCache +- Offset: `0x14` +- Reset default: `0x0` +- Reset mask: `0x1` + +### Fields + +```wavejson +{"reg": [{"name": "flush", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 31}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:-------|:--------------| +| 31:1 | | | | Reserved | +| 0 | rw | 0x0 | flush | Flush | + +## icache_perfctr_ctrl +iCache Performance Counter Control +- Offset: `0x18` +- Reset default: `0x1` +- Reset mask: `0x10001` + +### Fields + +```wavejson +{"reg": [{"name": "enable", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 15}, {"name": "clear_all", "bits": 1, "attr": ["rw"], "rotate": -90}, {"bits": 15}], "config": {"lanes": 1, "fontsize": 10, "vspace": 110}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:----------|:-------------------------------| +| 31:17 | | | | Reserved | +| 16 | rw | 0x0 | clear_all | Clear all performance counters | +| 15:1 | | | | Reserved | +| 0 | rw | 0x1 | enable | Enable performance counters | + +## counters +Performance counters +- Reset default: `0x0` +- Reset mask: `0xffffffff` + +### Instances + +| Name | Offset | +|:-----------|:---------| +| counters_0 | 0x1c | +| counters_1 | 0x20 | +| counters_2 | 0x24 | +| counters_3 | 0x28 | +| counters_4 | 0x2c | +| counters_5 | 0x30 | +| counters_6 | 0x34 | +| counters_7 | 0x38 | +| counters_8 | 0x3c | + + +### Fields + +```wavejson +{"reg": [{"name": "counter", "bits": 32, "attr": ["rw0c"], "rotate": 0}], "config": {"lanes": 1, "fontsize": 10, "vspace": 80}} +``` + +| Bits | Type | Reset | Name | Description | +|:------:|:------:|:-------:|:--------|:--------------| +| 31:0 | rw0c | 0x0 | counter | | + diff --git a/rtl/soc_ctrl/safety_soc_ctrl_icache_reg_pkg.sv b/rtl/soc_ctrl/safety_soc_ctrl_icache_reg_pkg.sv new file mode 100644 index 0000000..f9146dd --- /dev/null +++ b/rtl/soc_ctrl/safety_soc_ctrl_icache_reg_pkg.sv @@ -0,0 +1,168 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Package auto-generated by `reggen` containing data structure + +package safety_soc_ctrl_icache_reg_pkg; + + // Address widths within the block + parameter int BlockAw = 6; + + //////////////////////////// + // Typedefs for registers // + //////////////////////////// + + typedef struct packed { + logic [31:0] q; + } safety_soc_ctrl_icache_reg2hw_bootaddr_reg_t; + + typedef struct packed { + logic q; + } safety_soc_ctrl_icache_reg2hw_fetchen_reg_t; + + typedef struct packed { + logic [31:0] q; + } safety_soc_ctrl_icache_reg2hw_corestatus_reg_t; + + typedef struct packed { + logic [1:0] q; + } safety_soc_ctrl_icache_reg2hw_bootmode_reg_t; + + typedef struct packed { + logic q; + } safety_soc_ctrl_icache_reg2hw_icache_enable_prefetch_reg_t; + + typedef struct packed { + logic q; + logic qe; + } safety_soc_ctrl_icache_reg2hw_icache_flush_reg_t; + + typedef struct packed { + struct packed { + logic q; + } enable; + struct packed { + logic q; + } clear_all; + } safety_soc_ctrl_icache_reg2hw_icache_perfctr_ctrl_reg_t; + + typedef struct packed { + logic [31:0] q; + } safety_soc_ctrl_icache_reg2hw_counters_mreg_t; + + typedef struct packed { + logic d; + logic de; + } safety_soc_ctrl_icache_hw2reg_fetchen_reg_t; + + typedef struct packed { + logic [1:0] d; + logic de; + } safety_soc_ctrl_icache_hw2reg_bootmode_reg_t; + + typedef struct packed { + logic d; + } safety_soc_ctrl_icache_hw2reg_icache_flush_reg_t; + + typedef struct packed { + struct packed { + logic d; + logic de; + } enable; + struct packed { + logic d; + logic de; + } clear_all; + } safety_soc_ctrl_icache_hw2reg_icache_perfctr_ctrl_reg_t; + + typedef struct packed { + logic [31:0] d; + logic de; + } safety_soc_ctrl_icache_hw2reg_counters_mreg_t; + + // Register -> HW type + typedef struct packed { + safety_soc_ctrl_icache_reg2hw_bootaddr_reg_t bootaddr; // [359:328] + safety_soc_ctrl_icache_reg2hw_fetchen_reg_t fetchen; // [327:327] + safety_soc_ctrl_icache_reg2hw_corestatus_reg_t corestatus; // [326:295] + safety_soc_ctrl_icache_reg2hw_bootmode_reg_t bootmode; // [294:293] + safety_soc_ctrl_icache_reg2hw_icache_enable_prefetch_reg_t icache_enable_prefetch; // [292:292] + safety_soc_ctrl_icache_reg2hw_icache_flush_reg_t icache_flush; // [291:290] + safety_soc_ctrl_icache_reg2hw_icache_perfctr_ctrl_reg_t icache_perfctr_ctrl; // [289:288] + safety_soc_ctrl_icache_reg2hw_counters_mreg_t [8:0] counters; // [287:0] + } safety_soc_ctrl_icache_reg2hw_t; + + // HW -> register type + typedef struct packed { + safety_soc_ctrl_icache_hw2reg_fetchen_reg_t fetchen; // [306:305] + safety_soc_ctrl_icache_hw2reg_bootmode_reg_t bootmode; // [304:302] + safety_soc_ctrl_icache_hw2reg_icache_flush_reg_t icache_flush; // [301:301] + safety_soc_ctrl_icache_hw2reg_icache_perfctr_ctrl_reg_t icache_perfctr_ctrl; // [300:297] + safety_soc_ctrl_icache_hw2reg_counters_mreg_t [8:0] counters; // [296:0] + } safety_soc_ctrl_icache_hw2reg_t; + + // Register offsets + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_BOOTADDR_OFFSET = 6'h 0; + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_FETCHEN_OFFSET = 6'h 4; + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_CORESTATUS_OFFSET = 6'h 8; + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_BOOTMODE_OFFSET = 6'h c; + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_ICACHE_ENABLE_PREFETCH_OFFSET = 6'h 10; + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_ICACHE_FLUSH_OFFSET = 6'h 14; + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_ICACHE_PERFCTR_CTRL_OFFSET = 6'h 18; + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_COUNTERS_0_OFFSET = 6'h 1c; + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_COUNTERS_1_OFFSET = 6'h 20; + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_COUNTERS_2_OFFSET = 6'h 24; + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_COUNTERS_3_OFFSET = 6'h 28; + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_COUNTERS_4_OFFSET = 6'h 2c; + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_COUNTERS_5_OFFSET = 6'h 30; + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_COUNTERS_6_OFFSET = 6'h 34; + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_COUNTERS_7_OFFSET = 6'h 38; + parameter logic [BlockAw-1:0] SAFETY_SOC_CTRL_ICACHE_COUNTERS_8_OFFSET = 6'h 3c; + + // Reset values for hwext registers and their fields + parameter logic [0:0] SAFETY_SOC_CTRL_ICACHE_ICACHE_FLUSH_RESVAL = 1'h 0; + parameter logic [0:0] SAFETY_SOC_CTRL_ICACHE_ICACHE_FLUSH_FLUSH_RESVAL = 1'h 0; + + // Register index + typedef enum int { + SAFETY_SOC_CTRL_ICACHE_BOOTADDR, + SAFETY_SOC_CTRL_ICACHE_FETCHEN, + SAFETY_SOC_CTRL_ICACHE_CORESTATUS, + SAFETY_SOC_CTRL_ICACHE_BOOTMODE, + SAFETY_SOC_CTRL_ICACHE_ICACHE_ENABLE_PREFETCH, + SAFETY_SOC_CTRL_ICACHE_ICACHE_FLUSH, + SAFETY_SOC_CTRL_ICACHE_ICACHE_PERFCTR_CTRL, + SAFETY_SOC_CTRL_ICACHE_COUNTERS_0, + SAFETY_SOC_CTRL_ICACHE_COUNTERS_1, + SAFETY_SOC_CTRL_ICACHE_COUNTERS_2, + SAFETY_SOC_CTRL_ICACHE_COUNTERS_3, + SAFETY_SOC_CTRL_ICACHE_COUNTERS_4, + SAFETY_SOC_CTRL_ICACHE_COUNTERS_5, + SAFETY_SOC_CTRL_ICACHE_COUNTERS_6, + SAFETY_SOC_CTRL_ICACHE_COUNTERS_7, + SAFETY_SOC_CTRL_ICACHE_COUNTERS_8 + } safety_soc_ctrl_icache_id_e; + + // Register width information to check illegal writes + parameter logic [3:0] SAFETY_SOC_CTRL_ICACHE_PERMIT [16] = '{ + 4'b 1111, // index[ 0] SAFETY_SOC_CTRL_ICACHE_BOOTADDR + 4'b 0001, // index[ 1] SAFETY_SOC_CTRL_ICACHE_FETCHEN + 4'b 1111, // index[ 2] SAFETY_SOC_CTRL_ICACHE_CORESTATUS + 4'b 0001, // index[ 3] SAFETY_SOC_CTRL_ICACHE_BOOTMODE + 4'b 0001, // index[ 4] SAFETY_SOC_CTRL_ICACHE_ICACHE_ENABLE_PREFETCH + 4'b 0001, // index[ 5] SAFETY_SOC_CTRL_ICACHE_ICACHE_FLUSH + 4'b 0111, // index[ 6] SAFETY_SOC_CTRL_ICACHE_ICACHE_PERFCTR_CTRL + 4'b 1111, // index[ 7] SAFETY_SOC_CTRL_ICACHE_COUNTERS_0 + 4'b 1111, // index[ 8] SAFETY_SOC_CTRL_ICACHE_COUNTERS_1 + 4'b 1111, // index[ 9] SAFETY_SOC_CTRL_ICACHE_COUNTERS_2 + 4'b 1111, // index[10] SAFETY_SOC_CTRL_ICACHE_COUNTERS_3 + 4'b 1111, // index[11] SAFETY_SOC_CTRL_ICACHE_COUNTERS_4 + 4'b 1111, // index[12] SAFETY_SOC_CTRL_ICACHE_COUNTERS_5 + 4'b 1111, // index[13] SAFETY_SOC_CTRL_ICACHE_COUNTERS_6 + 4'b 1111, // index[14] SAFETY_SOC_CTRL_ICACHE_COUNTERS_7 + 4'b 1111 // index[15] SAFETY_SOC_CTRL_ICACHE_COUNTERS_8 + }; + +endpackage + diff --git a/rtl/soc_ctrl/safety_soc_ctrl_icache_reg_top.sv b/rtl/soc_ctrl/safety_soc_ctrl_icache_reg_top.sv new file mode 100644 index 0000000..3edc717 --- /dev/null +++ b/rtl/soc_ctrl/safety_soc_ctrl_icache_reg_top.sv @@ -0,0 +1,813 @@ +// Copyright lowRISC contributors. +// Licensed under the Apache License, Version 2.0, see LICENSE for details. +// SPDX-License-Identifier: Apache-2.0 +// +// Register Top module auto-generated by `reggen` + + +`include "common_cells/assertions.svh" + +module safety_soc_ctrl_icache_reg_top #( + parameter type reg_req_t = logic, + parameter type reg_rsp_t = logic, + parameter int AW = 6, + parameter int unsigned BootAddrDefault = 32'h0 +) ( + input logic clk_i, + input logic rst_ni, + input reg_req_t reg_req_i, + output reg_rsp_t reg_rsp_o, + // To HW + output safety_soc_ctrl_icache_reg_pkg::safety_soc_ctrl_icache_reg2hw_t reg2hw, // Write + input safety_soc_ctrl_icache_reg_pkg::safety_soc_ctrl_icache_hw2reg_t hw2reg, // Read + + + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + + import safety_soc_ctrl_icache_reg_pkg::* ; + + localparam int DW = 32; + localparam int DBW = DW/8; // Byte Width + + // register signals + logic reg_we; + logic reg_re; + logic [BlockAw-1:0] reg_addr; + logic [DW-1:0] reg_wdata; + logic [DBW-1:0] reg_be; + logic [DW-1:0] reg_rdata; + logic reg_error; + + logic addrmiss, wr_err; + + logic [DW-1:0] reg_rdata_next; + + // Below register interface can be changed + reg_req_t reg_intf_req; + reg_rsp_t reg_intf_rsp; + + + assign reg_intf_req = reg_req_i; + assign reg_rsp_o = reg_intf_rsp; + + + assign reg_we = reg_intf_req.valid & reg_intf_req.write; + assign reg_re = reg_intf_req.valid & ~reg_intf_req.write; + assign reg_addr = reg_intf_req.addr[BlockAw-1:0]; + assign reg_wdata = reg_intf_req.wdata; + assign reg_be = reg_intf_req.wstrb; + assign reg_intf_rsp.rdata = reg_rdata; + assign reg_intf_rsp.error = reg_error; + assign reg_intf_rsp.ready = 1'b1; + + assign reg_rdata = reg_rdata_next ; + assign reg_error = (devmode_i & addrmiss) | wr_err; + + + // Define SW related signals + // Format: __{wd|we|qs} + // or _{wd|we|qs} if field == 1 or 0 + logic [31:0] bootaddr_qs; + logic [31:0] bootaddr_wd; + logic bootaddr_we; + logic fetchen_qs; + logic fetchen_wd; + logic fetchen_we; + logic [31:0] corestatus_qs; + logic [31:0] corestatus_wd; + logic corestatus_we; + logic [1:0] bootmode_qs; + logic [1:0] bootmode_wd; + logic bootmode_we; + logic icache_enable_prefetch_qs; + logic icache_enable_prefetch_wd; + logic icache_enable_prefetch_we; + logic icache_flush_qs; + logic icache_flush_wd; + logic icache_flush_we; + logic icache_flush_re; + logic icache_perfctr_ctrl_enable_qs; + logic icache_perfctr_ctrl_enable_wd; + logic icache_perfctr_ctrl_enable_we; + logic icache_perfctr_ctrl_clear_all_qs; + logic icache_perfctr_ctrl_clear_all_wd; + logic icache_perfctr_ctrl_clear_all_we; + logic [31:0] counters_0_qs; + logic [31:0] counters_0_wd; + logic counters_0_we; + logic [31:0] counters_1_qs; + logic [31:0] counters_1_wd; + logic counters_1_we; + logic [31:0] counters_2_qs; + logic [31:0] counters_2_wd; + logic counters_2_we; + logic [31:0] counters_3_qs; + logic [31:0] counters_3_wd; + logic counters_3_we; + logic [31:0] counters_4_qs; + logic [31:0] counters_4_wd; + logic counters_4_we; + logic [31:0] counters_5_qs; + logic [31:0] counters_5_wd; + logic counters_5_we; + logic [31:0] counters_6_qs; + logic [31:0] counters_6_wd; + logic counters_6_we; + logic [31:0] counters_7_qs; + logic [31:0] counters_7_wd; + logic counters_7_we; + logic [31:0] counters_8_qs; + logic [31:0] counters_8_wd; + logic counters_8_we; + + // Register instances + // R[bootaddr]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (BootAddrDefault) + ) u_bootaddr ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (bootaddr_we), + .wd (bootaddr_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.bootaddr.q ), + + // to register interface (read) + .qs (bootaddr_qs) + ); + + + // R[fetchen]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_fetchen ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (fetchen_we), + .wd (fetchen_wd), + + // from internal hardware + .de (hw2reg.fetchen.de), + .d (hw2reg.fetchen.d ), + + // to internal hardware + .qe (), + .q (reg2hw.fetchen.q ), + + // to register interface (read) + .qs (fetchen_qs) + ); + + + // R[corestatus]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("RW"), + .RESVAL (32'h0) + ) u_corestatus ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (corestatus_we), + .wd (corestatus_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.corestatus.q ), + + // to register interface (read) + .qs (corestatus_qs) + ); + + + // R[bootmode]: V(False) + + prim_subreg #( + .DW (2), + .SWACCESS("RW"), + .RESVAL (2'h0) + ) u_bootmode ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (bootmode_we), + .wd (bootmode_wd), + + // from internal hardware + .de (hw2reg.bootmode.de), + .d (hw2reg.bootmode.d ), + + // to internal hardware + .qe (), + .q (reg2hw.bootmode.q ), + + // to register interface (read) + .qs (bootmode_qs) + ); + + + // R[icache_enable_prefetch]: V(False) + + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_icache_enable_prefetch ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (icache_enable_prefetch_we), + .wd (icache_enable_prefetch_wd), + + // from internal hardware + .de (1'b0), + .d ('0 ), + + // to internal hardware + .qe (), + .q (reg2hw.icache_enable_prefetch.q ), + + // to register interface (read) + .qs (icache_enable_prefetch_qs) + ); + + + // R[icache_flush]: V(True) + + prim_subreg_ext #( + .DW (1) + ) u_icache_flush ( + .re (icache_flush_re), + .we (icache_flush_we), + .wd (icache_flush_wd), + .d (hw2reg.icache_flush.d), + .qre (), + .qe (reg2hw.icache_flush.qe), + .q (reg2hw.icache_flush.q ), + .qs (icache_flush_qs) + ); + + + // R[icache_perfctr_ctrl]: V(False) + + // F[enable]: 0:0 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h1) + ) u_icache_perfctr_ctrl_enable ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (icache_perfctr_ctrl_enable_we), + .wd (icache_perfctr_ctrl_enable_wd), + + // from internal hardware + .de (hw2reg.icache_perfctr_ctrl.enable.de), + .d (hw2reg.icache_perfctr_ctrl.enable.d ), + + // to internal hardware + .qe (), + .q (reg2hw.icache_perfctr_ctrl.enable.q ), + + // to register interface (read) + .qs (icache_perfctr_ctrl_enable_qs) + ); + + + // F[clear_all]: 16:16 + prim_subreg #( + .DW (1), + .SWACCESS("RW"), + .RESVAL (1'h0) + ) u_icache_perfctr_ctrl_clear_all ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (icache_perfctr_ctrl_clear_all_we), + .wd (icache_perfctr_ctrl_clear_all_wd), + + // from internal hardware + .de (hw2reg.icache_perfctr_ctrl.clear_all.de), + .d (hw2reg.icache_perfctr_ctrl.clear_all.d ), + + // to internal hardware + .qe (), + .q (reg2hw.icache_perfctr_ctrl.clear_all.q ), + + // to register interface (read) + .qs (icache_perfctr_ctrl_clear_all_qs) + ); + + + + // Subregister 0 of Multireg counters + // R[counters_0]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("W0C"), + .RESVAL (32'h0) + ) u_counters_0 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (counters_0_we), + .wd (counters_0_wd), + + // from internal hardware + .de (hw2reg.counters[0].de), + .d (hw2reg.counters[0].d ), + + // to internal hardware + .qe (), + .q (reg2hw.counters[0].q ), + + // to register interface (read) + .qs (counters_0_qs) + ); + + // Subregister 1 of Multireg counters + // R[counters_1]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("W0C"), + .RESVAL (32'h0) + ) u_counters_1 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (counters_1_we), + .wd (counters_1_wd), + + // from internal hardware + .de (hw2reg.counters[1].de), + .d (hw2reg.counters[1].d ), + + // to internal hardware + .qe (), + .q (reg2hw.counters[1].q ), + + // to register interface (read) + .qs (counters_1_qs) + ); + + // Subregister 2 of Multireg counters + // R[counters_2]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("W0C"), + .RESVAL (32'h0) + ) u_counters_2 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (counters_2_we), + .wd (counters_2_wd), + + // from internal hardware + .de (hw2reg.counters[2].de), + .d (hw2reg.counters[2].d ), + + // to internal hardware + .qe (), + .q (reg2hw.counters[2].q ), + + // to register interface (read) + .qs (counters_2_qs) + ); + + // Subregister 3 of Multireg counters + // R[counters_3]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("W0C"), + .RESVAL (32'h0) + ) u_counters_3 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (counters_3_we), + .wd (counters_3_wd), + + // from internal hardware + .de (hw2reg.counters[3].de), + .d (hw2reg.counters[3].d ), + + // to internal hardware + .qe (), + .q (reg2hw.counters[3].q ), + + // to register interface (read) + .qs (counters_3_qs) + ); + + // Subregister 4 of Multireg counters + // R[counters_4]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("W0C"), + .RESVAL (32'h0) + ) u_counters_4 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (counters_4_we), + .wd (counters_4_wd), + + // from internal hardware + .de (hw2reg.counters[4].de), + .d (hw2reg.counters[4].d ), + + // to internal hardware + .qe (), + .q (reg2hw.counters[4].q ), + + // to register interface (read) + .qs (counters_4_qs) + ); + + // Subregister 5 of Multireg counters + // R[counters_5]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("W0C"), + .RESVAL (32'h0) + ) u_counters_5 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (counters_5_we), + .wd (counters_5_wd), + + // from internal hardware + .de (hw2reg.counters[5].de), + .d (hw2reg.counters[5].d ), + + // to internal hardware + .qe (), + .q (reg2hw.counters[5].q ), + + // to register interface (read) + .qs (counters_5_qs) + ); + + // Subregister 6 of Multireg counters + // R[counters_6]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("W0C"), + .RESVAL (32'h0) + ) u_counters_6 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (counters_6_we), + .wd (counters_6_wd), + + // from internal hardware + .de (hw2reg.counters[6].de), + .d (hw2reg.counters[6].d ), + + // to internal hardware + .qe (), + .q (reg2hw.counters[6].q ), + + // to register interface (read) + .qs (counters_6_qs) + ); + + // Subregister 7 of Multireg counters + // R[counters_7]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("W0C"), + .RESVAL (32'h0) + ) u_counters_7 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (counters_7_we), + .wd (counters_7_wd), + + // from internal hardware + .de (hw2reg.counters[7].de), + .d (hw2reg.counters[7].d ), + + // to internal hardware + .qe (), + .q (reg2hw.counters[7].q ), + + // to register interface (read) + .qs (counters_7_qs) + ); + + // Subregister 8 of Multireg counters + // R[counters_8]: V(False) + + prim_subreg #( + .DW (32), + .SWACCESS("W0C"), + .RESVAL (32'h0) + ) u_counters_8 ( + .clk_i (clk_i ), + .rst_ni (rst_ni ), + + // from register interface + .we (counters_8_we), + .wd (counters_8_wd), + + // from internal hardware + .de (hw2reg.counters[8].de), + .d (hw2reg.counters[8].d ), + + // to internal hardware + .qe (), + .q (reg2hw.counters[8].q ), + + // to register interface (read) + .qs (counters_8_qs) + ); + + + + + logic [15:0] addr_hit; + always_comb begin + addr_hit = '0; + addr_hit[ 0] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_BOOTADDR_OFFSET); + addr_hit[ 1] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_FETCHEN_OFFSET); + addr_hit[ 2] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_CORESTATUS_OFFSET); + addr_hit[ 3] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_BOOTMODE_OFFSET); + addr_hit[ 4] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_ICACHE_ENABLE_PREFETCH_OFFSET); + addr_hit[ 5] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_ICACHE_FLUSH_OFFSET); + addr_hit[ 6] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_ICACHE_PERFCTR_CTRL_OFFSET); + addr_hit[ 7] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_COUNTERS_0_OFFSET); + addr_hit[ 8] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_COUNTERS_1_OFFSET); + addr_hit[ 9] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_COUNTERS_2_OFFSET); + addr_hit[10] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_COUNTERS_3_OFFSET); + addr_hit[11] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_COUNTERS_4_OFFSET); + addr_hit[12] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_COUNTERS_5_OFFSET); + addr_hit[13] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_COUNTERS_6_OFFSET); + addr_hit[14] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_COUNTERS_7_OFFSET); + addr_hit[15] = (reg_addr == SAFETY_SOC_CTRL_ICACHE_COUNTERS_8_OFFSET); + end + + assign addrmiss = (reg_re || reg_we) ? ~|addr_hit : 1'b0 ; + + // Check sub-word write is permitted + always_comb begin + wr_err = (reg_we & + ((addr_hit[ 0] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[ 0] & ~reg_be))) | + (addr_hit[ 1] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[ 1] & ~reg_be))) | + (addr_hit[ 2] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[ 2] & ~reg_be))) | + (addr_hit[ 3] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[ 3] & ~reg_be))) | + (addr_hit[ 4] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[ 4] & ~reg_be))) | + (addr_hit[ 5] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[ 5] & ~reg_be))) | + (addr_hit[ 6] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[ 6] & ~reg_be))) | + (addr_hit[ 7] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[ 7] & ~reg_be))) | + (addr_hit[ 8] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[ 8] & ~reg_be))) | + (addr_hit[ 9] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[ 9] & ~reg_be))) | + (addr_hit[10] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[10] & ~reg_be))) | + (addr_hit[11] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[11] & ~reg_be))) | + (addr_hit[12] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[12] & ~reg_be))) | + (addr_hit[13] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[13] & ~reg_be))) | + (addr_hit[14] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[14] & ~reg_be))) | + (addr_hit[15] & (|(SAFETY_SOC_CTRL_ICACHE_PERMIT[15] & ~reg_be))))); + end + + assign bootaddr_we = addr_hit[0] & reg_we & !reg_error; + assign bootaddr_wd = reg_wdata[31:0]; + + assign fetchen_we = addr_hit[1] & reg_we & !reg_error; + assign fetchen_wd = reg_wdata[0]; + + assign corestatus_we = addr_hit[2] & reg_we & !reg_error; + assign corestatus_wd = reg_wdata[31:0]; + + assign bootmode_we = addr_hit[3] & reg_we & !reg_error; + assign bootmode_wd = reg_wdata[1:0]; + + assign icache_enable_prefetch_we = addr_hit[4] & reg_we & !reg_error; + assign icache_enable_prefetch_wd = reg_wdata[0]; + + assign icache_flush_we = addr_hit[5] & reg_we & !reg_error; + assign icache_flush_wd = reg_wdata[0]; + assign icache_flush_re = addr_hit[5] & reg_re & !reg_error; + + assign icache_perfctr_ctrl_enable_we = addr_hit[6] & reg_we & !reg_error; + assign icache_perfctr_ctrl_enable_wd = reg_wdata[0]; + + assign icache_perfctr_ctrl_clear_all_we = addr_hit[6] & reg_we & !reg_error; + assign icache_perfctr_ctrl_clear_all_wd = reg_wdata[16]; + + assign counters_0_we = addr_hit[7] & reg_we & !reg_error; + assign counters_0_wd = reg_wdata[31:0]; + + assign counters_1_we = addr_hit[8] & reg_we & !reg_error; + assign counters_1_wd = reg_wdata[31:0]; + + assign counters_2_we = addr_hit[9] & reg_we & !reg_error; + assign counters_2_wd = reg_wdata[31:0]; + + assign counters_3_we = addr_hit[10] & reg_we & !reg_error; + assign counters_3_wd = reg_wdata[31:0]; + + assign counters_4_we = addr_hit[11] & reg_we & !reg_error; + assign counters_4_wd = reg_wdata[31:0]; + + assign counters_5_we = addr_hit[12] & reg_we & !reg_error; + assign counters_5_wd = reg_wdata[31:0]; + + assign counters_6_we = addr_hit[13] & reg_we & !reg_error; + assign counters_6_wd = reg_wdata[31:0]; + + assign counters_7_we = addr_hit[14] & reg_we & !reg_error; + assign counters_7_wd = reg_wdata[31:0]; + + assign counters_8_we = addr_hit[15] & reg_we & !reg_error; + assign counters_8_wd = reg_wdata[31:0]; + + // Read data return + always_comb begin + reg_rdata_next = '0; + unique case (1'b1) + addr_hit[0]: begin + reg_rdata_next[31:0] = bootaddr_qs; + end + + addr_hit[1]: begin + reg_rdata_next[0] = fetchen_qs; + end + + addr_hit[2]: begin + reg_rdata_next[31:0] = corestatus_qs; + end + + addr_hit[3]: begin + reg_rdata_next[1:0] = bootmode_qs; + end + + addr_hit[4]: begin + reg_rdata_next[0] = icache_enable_prefetch_qs; + end + + addr_hit[5]: begin + reg_rdata_next[0] = icache_flush_qs; + end + + addr_hit[6]: begin + reg_rdata_next[0] = icache_perfctr_ctrl_enable_qs; + reg_rdata_next[16] = icache_perfctr_ctrl_clear_all_qs; + end + + addr_hit[7]: begin + reg_rdata_next[31:0] = counters_0_qs; + end + + addr_hit[8]: begin + reg_rdata_next[31:0] = counters_1_qs; + end + + addr_hit[9]: begin + reg_rdata_next[31:0] = counters_2_qs; + end + + addr_hit[10]: begin + reg_rdata_next[31:0] = counters_3_qs; + end + + addr_hit[11]: begin + reg_rdata_next[31:0] = counters_4_qs; + end + + addr_hit[12]: begin + reg_rdata_next[31:0] = counters_5_qs; + end + + addr_hit[13]: begin + reg_rdata_next[31:0] = counters_6_qs; + end + + addr_hit[14]: begin + reg_rdata_next[31:0] = counters_7_qs; + end + + addr_hit[15]: begin + reg_rdata_next[31:0] = counters_8_qs; + end + + default: begin + reg_rdata_next = '1; + end + endcase + end + + // Unused signal tieoff + + // wdata / byte enable are not always fully used + // add a blanket unused statement to handle lint waivers + logic unused_wdata; + logic unused_be; + assign unused_wdata = ^reg_wdata; + assign unused_be = ^reg_be; + + // Assertions for Register Interface + `ASSERT(en2addrHit, (reg_we || reg_re) |-> $onehot0(addr_hit)) + +endmodule + +module safety_soc_ctrl_icache_reg_top_intf +#( + parameter int AW = 6, + localparam int DW = 32 +) ( + input logic clk_i, + input logic rst_ni, + REG_BUS.in regbus_slave, + // To HW + output safety_soc_ctrl_icache_reg_pkg::safety_soc_ctrl_icache_reg2hw_t reg2hw, // Write + input safety_soc_ctrl_icache_reg_pkg::safety_soc_ctrl_icache_hw2reg_t hw2reg, // Read + // Config + input devmode_i // If 1, explicit error return for unmapped register access +); + localparam int unsigned STRB_WIDTH = DW/8; + +`include "register_interface/typedef.svh" +`include "register_interface/assign.svh" + + // Define structs for reg_bus + typedef logic [AW-1:0] addr_t; + typedef logic [DW-1:0] data_t; + typedef logic [STRB_WIDTH-1:0] strb_t; + `REG_BUS_TYPEDEF_ALL(reg_bus, addr_t, data_t, strb_t) + + reg_bus_req_t s_reg_req; + reg_bus_rsp_t s_reg_rsp; + + // Assign SV interface to structs + `REG_BUS_ASSIGN_TO_REQ(s_reg_req, regbus_slave) + `REG_BUS_ASSIGN_FROM_RSP(regbus_slave, s_reg_rsp) + + + + safety_soc_ctrl_icache_reg_top #( + .reg_req_t(reg_bus_req_t), + .reg_rsp_t(reg_bus_rsp_t), + .AW(AW) + ) i_regs ( + .clk_i, + .rst_ni, + .reg_req_i(s_reg_req), + .reg_rsp_o(s_reg_rsp), + .reg2hw, // Write + .hw2reg, // Read + .devmode_i + ); + +endmodule + + diff --git a/rtl/soc_ctrl/safety_soc_ctrl_regs.hjson b/rtl/soc_ctrl/safety_soc_ctrl_regs.hjson index 411f9b5..8e52d5b 100644 --- a/rtl/soc_ctrl/safety_soc_ctrl_regs.hjson +++ b/rtl/soc_ctrl/safety_soc_ctrl_regs.hjson @@ -50,7 +50,7 @@ resval: 0 } ] - } + }, { name: "bootmode", desc: "Core Boot Mode", swaccess: "rw", @@ -62,7 +62,6 @@ resval: 0x0 } ] - }, ], } diff --git a/rtl/soc_ctrl/safety_soc_ctrl_regs_icache.hjson b/rtl/soc_ctrl/safety_soc_ctrl_regs_icache.hjson new file mode 100644 index 0000000..294547d --- /dev/null +++ b/rtl/soc_ctrl/safety_soc_ctrl_regs_icache.hjson @@ -0,0 +1,126 @@ +# Copyright 2023 ETH Zurich and University of Bologna +# Solderpad Hardware License, Version 0.51, see LICENSE for details. +# SPDX-License-Identifier: SHL-0.51 + +{ + name: "safety_soc_ctrl_icache", + clock_primary: "clk_i", + reset_primary: "rst_ni", + bus_interfaces: [ + { protocol: "reg_iface", + direction: "device" + } + ], + + regwidth: "32", + registers: [ + { name: "bootaddr", + desc: "Core Boot Address", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "31:0", + name: "bootaddr", + desc: "Boot Address", + resval: 0x1A00_0000 + } + ] + + }, + { name: "fetchen", + desc: "Core Fetch Enable", + swaccess: "rw", + hwaccess: "hrw", + fields: [ + { bits: "0", + name: "fetchen", + desc: "Fetch Enable", + resval: 0 + } + ] + }, + { name: "corestatus", + desc: "Core Return Status (return value, EOC)", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "31:0", + name: "core_status", + desc: "Core Return Status (EOC(bit[31]) and status(bit[30:0]))", + resval: 0 + } + ] + }, + { name: "bootmode", + desc: "Core Boot Mode", + swaccess: "rw", + hwaccess: "hrw", + fields: [ + { bits: "1:0", + name: "bootmode", + desc: "Boot Mode", + resval: 0x0 + } + ] + }, + { name: "icache_enable_prefetch", + desc: "Enable iCache prefetching", + swaccess: "rw", + hwaccess: "hro", + fields: [ + { bits: "0", + name: "prefetch_enable", + desc: "Enable prefetching", + resval: 0x1 + } + ] + }, + { name: "icache_flush", + desc: "Flush iCache", + swaccess: "rw", + hwaccess: "hrw", + hwqe: "true", + hwext: "true", + fields: [ + { bits: "0", + name: "flush", + desc: "Flush", + resval: 0x0 + } + ] + }, + { name: "icache_perfctr_ctrl", + desc: "iCache Performance Counter Control", + swaccess: "rw", + hwaccess: "hrw", + fields: [ + { bits: "0", + name: "enable", + desc: "Enable performance counters", + resval: 0x1 + }, + { bits: "16", + name: "clear_all", + desc: "Clear all performance counters", + resval: 0x0 + } + ] + }, + { multireg: { + name: "counters", + desc: "Performance counters", + count: "9", + cname: "id", + swaccess: "rw0c", + hwaccess: "hrw", + fields: [ + { bits: "31:0", + name: "counter", + desc: "", + resval: 0x0000_0000 + } + ] + } + }, + ], +} diff --git a/safed.mk b/safed.mk index 7d4d4fc..2a4439b 100644 --- a/safed.mk +++ b/safed.mk @@ -45,16 +45,17 @@ nonfree-init: ##################### # Generate Hardware # ##################### -REG_HTML_STRING = "\n\n\n\n\n" - $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl_reg_pkg.sv $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl_reg_top.sv: $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl_regs.hjson $(REGGEN) $< -t $(SAFED_HW_DIR)/soc_ctrl -r cd $(SAFED_ROOT) && git apply $(SAFED_HW_DIR)/soc_ctrl/boot_addr.patch - printf $(REG_HTML_STRING) > $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl.html - $(REGGEN) $< -d >> $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl.html - printf "\n" >> $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl.html + $(REGGEN) $< -d >> $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl.md $(REGGEN) $< -D > $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl.h - cp $(shell $(BENDER) path register_interface)/vendor/lowrisc_opentitan/util/reggen/reg_html.css $(SAFED_HW_DIR)/soc_ctrl + +$(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl_icache_reg_pkg.sv $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl_icache_reg_top.sv: $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl_regs_icache.hjson + $(REGGEN) $< -t $(SAFED_HW_DIR)/soc_ctrl -r + cd $(SAFED_ROOT) && git apply $(SAFED_HW_DIR)/soc_ctrl/boot_addr_icache.patch + $(REGGEN) $< -d >> $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl_icache.md + $(REGGEN) $< -D > $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl_icache.h $(SAFED_HW_DIR)/safety_island_bootrom.sv: $(MAKE) -C$(SAFED_BOOT_DIR) clean safety_island_bootrom.sv @@ -67,6 +68,7 @@ $(SAFED_HW_DIR)/safety_island_bootrom_carfield.sv: .PHONY: safed-hw-gen safed-bootrom-gen ## Generate Safety Island HW sources safed-hw-gen: $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl_reg_pkg.sv $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl_reg_top.sv +safed-hw-gen: $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl_icache_reg_pkg.sv $(SAFED_HW_DIR)/soc_ctrl/safety_soc_ctrl_icache_reg_top.sv ## Generate Safety Island bootrom safed-bootrom-gen: $(SAFED_HW_DIR)/safety_island_bootrom.sv $(SAFED_HW_DIR)/safety_island_bootrom_carfield.sv