diff --git a/.gitlab-ci.yml b/.gitlab-ci.yml index 4d474d8..efae436 100644 --- a/.gitlab-ci.yml +++ b/.gitlab-ci.yml @@ -4,9 +4,15 @@ # # Yvan Tortorella +.base: + artifacts: + when: always + expire_in: 1 week + stages: - init - build + - test init: stage: init @@ -15,13 +21,8 @@ init: artifacts: when: always expire_in: 1 week - paths: [ golden-model/venv ] - - -.base: - artifacts: - when: always - expire_in: 1 week + paths: + - golden-model/venv .redmule-build-tpl: extends: .base @@ -40,7 +41,11 @@ redmule-build-hwpe: artifacts: when: always expire_in: 1 week - paths: [ golden-model/venv, .bender, scripts/compile.tcl, work ] + paths: + - .bender + - scripts/compile.tcl + - work + - transcript redmule-build-complex: extends: .redmule-build-tpl @@ -49,33 +54,44 @@ redmule-build-complex: artifacts: when: always expire_in: 1 week - paths: [ golden-model/venv, .bender, scripts/compile.tcl, work ] + paths: + - .bender + - scripts/compile.tcl + - work + - transcript + +.redmule-vsim-tpl: + extends: .base + stage: test + script: + - SETUP_CONFIG=${SETUP_CONFIG} + - source scripts/${SETUP_CONFIG}.sh + - make golden M=${M} N=${N} K=${K} + - make clean all + - make run + - '(grep -rn "Success!" ./transcript)' + - (! grep -rn "Fail!" ./transcript) + artifacts: + when: always + expire_in: 1 week + paths: + - work + - transcript + +hwpe-test: + extends: .redmule-vsim-tpl + needs: [ redmule-build-hwpe ] + variables: + SETUP_CONFIG: "setup-hwpe" + parallel: + matrix: + - { M: 96, N: 96, K: 96 } -# .redmule-vsim-tpl: -# extends: .base -# needs: [ build ] -# stage: test -# script: -# - SETUP-CONFIG=${SETUP-CONFIG} -# - source scripts/${SETUP-CONFIG}.sh -# - make goden M=${M} N=${N} K=${K} -# - make clean all -# - make run -# - '(grep -rn Success!" ./work/transcript)' -# - (! grep -rn "Fail!" ./work/transcript) -# -# hwpe-test: -# extends: .redmule-vsim-tpl -# variables: -# SETUP-CONFIG: "setup-hwpe" -# parallel: -# matrix: -# - { M: 32, N=32, K=32 } -# -# complex-test: -# extends: .redmule-vsim-tpl -# variables: -# SETUP-CONFIG: "setup-complex" -# parallel: -# matrix: -# - { M: 32, N=32, K=32 } +complex-test: + extends: .redmule-vsim-tpl + needs: [ redmule-build-complex ] + variables: + SETUP_CONFIG: "setup-complex" + parallel: + matrix: + - { M: 96, N: 96, K: 96 } diff --git a/Makefile b/Makefile index b7b9d21..e1f47e2 100644 --- a/Makefile +++ b/Makefile @@ -10,7 +10,7 @@ mkfile_path := $(dir $(abspath $(firstword $(MAKEFILE_LIST)))) SW ?= $(mkfile_path)/sw BUILD_DIR ?= $(mkfile_path)/work -QUESTA ?= questa-2020.1 +QUESTA ?= questa-2023.4 BENDER_DIR ?= . BENDER ?= bender ISA ?= riscv @@ -26,7 +26,7 @@ endif compile_script ?= scripts/compile.tcl compile_script_synth ?= scripts/synth_compile.tcl -compile_flag ?= -suppress 2583 -suppress 13314 +compile_flag ?= -permissive -suppress 2583 -suppress 13314 INI_PATH = $(mkfile_path)/modelsim.ini WORK_PATH = $(BUILD_DIR) @@ -99,15 +99,15 @@ all: $(STIM_INSTR) $(STIM_DATA) dis # Run the simulation run: $(CRT) ifeq ($(gui), 0) - cd $(BUILD_DIR)/$(TEST_SRCS); \ - $(QUESTA) vsim -c vopt_tb -do "run -a" \ - -gSTIM_INSTR=stim_instr.txt \ - -gSTIM_DATA=stim_data.txt \ + cd $(BUILD_DIR)/$(TEST_SRCS); \ + $(QUESTA) vsim -c $(tb)_opt -do "run -a" \ + -gSTIM_INSTR=stim_instr.txt \ + -gSTIM_DATA=stim_data.txt \ -gPROB_STALL=$(P_STALL) else cd $(BUILD_DIR)/$(TEST_SRCS); \ - $(QUESTA) vsim vopt_tb \ - -do "add log -r sim:/$(tb)/*" \ + $(QUESTA) vsim $(tb)_opt \ + -do "log -r /*" \ -do "source $(WAVES)" \ -gSTIM_INSTR=stim_instr.txt \ -gSTIM_DATA=stim_data.txt \ @@ -123,20 +123,12 @@ include bender_common.mk include bender_sim.mk include bender_synth.mk -bender_defs += -D COREV_ASSERT_OFF - -bender_targs += -t rtl -bender_targs += -t test -bender_targs += -t cv32e40p_exclude_tracer - ifeq ($(REDMULE_COMPLEX),1) tb := redmule_complex_tb WAVES := $(mkfile_path)/wave_complex_xif.do - bender_targs += -t redmule_complex else tb := redmule_tb WAVES := $(mkfile_path)/wave.do - bender_targs += -t redmule_hwpe endif update-ips: @@ -144,9 +136,10 @@ update-ips: $(BENDER) script vsim \ --vlog-arg="$(compile_flag)" \ --vcom-arg="-pedanticerrors" \ - $(bender_targs) $(bender_defs) \ - $(sim_targs) $(sim_deps) \ + $(common_targs) $(common_defs) \ + $(sim_targs) \ > ${compile_script} + echo 'vopt $(compile_flag) $(tb) -o $(tb)_opt' >> ${compile_script} synth-ips: $(BENDER) update @@ -193,11 +186,8 @@ hw-clean-all: rm -rf transcript rm -rf .cached_ipdb.json -hw-opt: - $(QUESTA) vopt +acc=npr -o vopt_tb $(tb) -floatparameters+$(tb) -work $(BUILD_DIR) - hw-compile: - $(QUESTA) vsim -c +incdir+$(UVM_HOME) -do 'quit -code [source $(compile_script)]' + $(QUESTA) vsim -c -do 'quit -code [source $(compile_script)]' hw-lib: @touch modelsim.ini @@ -210,4 +200,4 @@ hw-clean: rm -rf transcript rm -rf modelsim.ini -hw-all: hw-clean hw-lib hw-compile hw-opt +hw-all: hw-clean hw-compile diff --git a/tb/redmule_complex_tb.sv b/tb/redmule_complex_tb.sv index 13baf10..de85971 100644 --- a/tb/redmule_complex_tb.sv +++ b/tb/redmule_complex_tb.sv @@ -24,8 +24,8 @@ import redmule_pkg::*; parameter int unsigned PULP_ZFINX = 0; parameter logic [31:0] BASE_ADDR = 32'h1c000000; parameter logic [31:0] HWPE_ADDR_BASE_BIT = 20; - parameter string STIM_INSTR = "../../stim_instr.txt"; - parameter string STIM_DATA = "../../stim_data.txt"; + parameter string STIM_INSTR = "./stim_instr.txt"; + parameter string STIM_DATA = "./stim_data.txt"; // global signals logic clk; @@ -381,12 +381,15 @@ import redmule_pkg::*; redmule_complex_tb.i_dummy_dmemory.cnt_wr[7] + redmule_complex_tb.i_dummy_dmemory.cnt_wr[8]; - $display("cnt_rd=%-8d", cnt_rd); - $display("cnt_wr=%-8d", cnt_wr); - if(errors != 0) - $error("errors=%08x", errors); - else - $display("errors=%08x", errors); + $display("[TB] - cnt_rd=%-8d", cnt_rd); + $display("[TB] - cnt_wr=%-8d", cnt_wr); + if(errors != 0) begin + $error("[TB] - errors=%08x", errors); + $display("[TB] - Fail!"); + end else begin + $display("[TB] - errors=%08x", errors); + $display("[TB] - Success!"); + end $finish; end diff --git a/tb/redmule_tb.sv b/tb/redmule_tb.sv index 7adcbf1..6e078cc 100644 --- a/tb/redmule_tb.sv +++ b/tb/redmule_tb.sv @@ -24,8 +24,8 @@ import redmule_pkg::*; parameter int unsigned PULP_ZFINX = 0; parameter logic [31:0] BASE_ADDR = 32'h1c000000; parameter logic [31:0] HWPE_ADDR_BASE_BIT = 20; - parameter string STIM_INSTR = "../../stim_instr.txt"; - parameter string STIM_DATA = "../../stim_data.txt"; + parameter string STIM_INSTR = "./stim_instr.txt"; + parameter string STIM_DATA = "./stim_data.txt"; // global signals logic clk; @@ -380,12 +380,15 @@ import redmule_pkg::*; #(TCP); cnt_rd = redmule_tb.i_dummy_dmemory.cnt_rd[0] + redmule_tb.i_dummy_dmemory.cnt_rd[1] + redmule_tb.i_dummy_dmemory.cnt_rd[2] + redmule_tb.i_dummy_dmemory.cnt_rd[3] + redmule_tb.i_dummy_dmemory.cnt_rd[4] + redmule_tb.i_dummy_dmemory.cnt_rd[5] + redmule_tb.i_dummy_dmemory.cnt_rd[6] + redmule_tb.i_dummy_dmemory.cnt_rd[7] + redmule_tb.i_dummy_dmemory.cnt_rd[8]; cnt_wr = redmule_tb.i_dummy_dmemory.cnt_wr[0] + redmule_tb.i_dummy_dmemory.cnt_wr[1] + redmule_tb.i_dummy_dmemory.cnt_wr[2] + redmule_tb.i_dummy_dmemory.cnt_wr[3] + redmule_tb.i_dummy_dmemory.cnt_wr[4] + redmule_tb.i_dummy_dmemory.cnt_wr[5] + redmule_tb.i_dummy_dmemory.cnt_wr[6] + redmule_tb.i_dummy_dmemory.cnt_wr[7] + redmule_tb.i_dummy_dmemory.cnt_wr[8]; - $display("cnt_rd=%-8d", cnt_rd); - $display("cnt_wr=%-8d", cnt_wr); - if(errors != 0) - $error("errors=%08x", errors); - else - $display("errors=%08x", errors); + $display("[TB] - cnt_rd=%-8d", cnt_rd); + $display("[TB] - cnt_wr=%-8d", cnt_wr); + if(errors != 0) begin + $error("[TB] - errors=%08x", errors); + $display("[TB] - Fail!"); + end else begin + $display("[TB] - errors=%08x", errors); + $display("[TB] - Success!"); + end $finish; end