From a2ae35beef87607cbc1d901c3de7296baac52a59 Mon Sep 17 00:00:00 2001
From: Thomas Benz <tbenz@iis.ee.ethz.ch>
Date: Wed, 28 Feb 2024 10:43:09 +0100
Subject: [PATCH] Switch default target for sim

---
 Bender.yml | 2 +-
 idma.mk    | 4 ++--
 2 files changed, 3 insertions(+), 3 deletions(-)

diff --git a/Bender.yml b/Bender.yml
index ec522b0a..ec9e7ea6 100644
--- a/Bender.yml
+++ b/Bender.yml
@@ -98,7 +98,7 @@ sources:
       - src/midend/idma_rt_midend_synth.sv
 
   # Testbenches
-  - target: test
+  - target: idma_test
     files:
       # Level 0
       - test/frontend/tb_idma_desc64_top.sv
diff --git a/idma.mk b/idma.mk
index 5bd50fb8..3d034837 100644
--- a/idma.mk
+++ b/idma.mk
@@ -282,7 +282,7 @@ endef
 $(IDMA_VSIM_DIR)/compile.tcl: $(IDMA_BENDER_FILES) $(IDMA_TB_ALL) $(IDMA_RTL_ALL)
 	$(BENDER) update
 	$(BENDER) checkout
-	$(call idma_generate_vsim, $@, -t sim -t test -t synth -t rtl -t asic -t snitch_cluster,../../..)
+	$(call idma_generate_vsim, $@, -t sim -t idma_test -t synth -t rtl -t asic -t snitch_cluster,../../..)
 
 idma_sim_clean:
 	rm -rf $(IDMA_VSIM_DIR)/compile.tcl
@@ -323,7 +323,7 @@ IDMA_VCS_PARAMS  ?=
 $(IDMA_VCS_DIR)/compile.sh: $(IDMA_BENDER_FILES) $(IDMA_TB_ALL) $(IDMA_RTL_ALL)
 	$(BENDER) update
 	$(BENDER) checkout
-	$(BENDER) script vcs -t test -t rtl -t synth -t simulation -t snitch_cluster --vlog-arg "\$(IDMA_VLOGAN_ARGS)" --vlogan-bin "$(VLOGAN)" $(IDMA_VLOGAN_REL_PATHS) > $@
+	$(BENDER) script vcs -t idma_test -t rtl -t synth -t simulation -t snitch_cluster --vlog-arg "\$(IDMA_VLOGAN_ARGS)" --vlogan-bin "$(VLOGAN)" $(IDMA_VLOGAN_REL_PATHS) > $@
 	chmod +x $@
 
 idma_vcs_compile: $(IDMA_VCS_DIR)/compile.sh