target/xilinx: Add block design flow

Bender.yml

@@ -68,12 +68,19 @@ sources:
     files:
       - target/synth/carfield_synth_wrap.sv
 
-  - target: all(xilinx, fpga)
+  - target: all(xilinx, fpga, xilinx_vanilla)
     files:
-      - target/xilinx/src/carfield_top_xilinx.sv
-      - target/xilinx/src/dram_wrapper_xilinx.sv
       - target/xilinx/src/cdc_dst_axi_err.sv
       - target/xilinx/src/overrides/tc_clk_xilinx.sv
+      - target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv
+      - target/xilinx/flavor_vanilla/src/dram_wrapper_xilinx.sv
+
+  - target: all(xilinx, fpga, xilinx_bd)
+    files:
+      - target/xilinx/src/cdc_dst_axi_err.sv
+      - target/xilinx/src/overrides/tc_clk_xilinx.sv
+      - target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv
+      - target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx_ip.v
 
   - target: intel16_elab_only
     files:

bender-xilinx.mk

@@ -5,22 +5,27 @@
 # Author: Cyril Koenig <[email protected]>
 
 # bender targets
-xilinx_targs += -t fpga
+xilinx_targs_common += -t fpga
 
 # bender defines
-xilinx_defs += -D PULP_FPGA_EMUL
+xilinx_defs_common += -D PULP_FPGA_EMUL
 
 # Conditionally add GEN_{island} to bender define
 define check_enable_island
 ifeq ($($(1)),1)
-xilinx_defs += -D$(1)=1
+xilinx_defs_common += -D$(1)=1
 endif
 endef
 
 $(eval $(call check_enable_island,GEN_PULP_CLUSTER))
 $(eval $(call check_enable_island,GEN_SAFETY_ISLAND))
 $(eval $(call check_enable_island,GEN_SPATZ_CLUSTER))
 $(eval $(call check_enable_island,GEN_OPEN_TITAN))
-$(eval $(call check_enable_island,NO_HYPERBUS))
+$(eval $(call check_enable_island,GEN_NO_HYPERBUS))
+$(eval $(call check_enable_island,GEN_EXT_JTAG))
+
+ifeq ($(GEN_EXT_JTAG),0)
+xilinx_targs_common += -t bscane
+endif
 
 # note : bender targets are later modified in xilinx.mk

carfield.mk

@@ -118,7 +118,7 @@ endif
 ######################
 
 CAR_NONFREE_REMOTE ?= [email protected]:carfield/carfield-nonfree.git
-CAR_NONFREE_COMMIT ?= db82219a845b66a645bbdc174ea2651046422c99
+CAR_NONFREE_COMMIT ?= e446a8e30d3e5556d14ff74953c51f1bbf8c670f
 
 ## Clone the non-free verification IP for the Carfield TB
 car-nonfree-init:

hw/carfield.sv

@@ -25,7 +25,7 @@ module carfield
   parameter islands_cfg_t IslandsCfg = carfield_pkg::IslandsCfgDefault,
   parameter int unsigned HypNumPhys  = 2,
   parameter int unsigned HypNumChips = 2,
-`ifdef NO_HYPERBUS // bender-xilinx.mk
+`ifdef GEN_NO_HYPERBUS // bender-xilinx.mk
   parameter int unsigned LlcIdWidth,
   parameter int unsigned LlcArWidth,
   parameter int unsigned LlcAwWidth,
@@ -130,7 +130,6 @@ module carfield
   output logic [SlinkNumChan-1:0]                     slink_rcv_clk_o,
   input  logic [SlinkNumChan-1:0][SlinkNumLanes-1:0]  slink_i,
   output logic [SlinkNumChan-1:0][SlinkNumLanes-1:0]  slink_o,
-`ifndef NO_HYPERBUS // bender-xilinx.mk
   // HyperBus interface
   output logic [HypNumPhys-1:0][HypNumChips-1:0]      hyper_cs_no,
   output logic [HypNumPhys-1:0]                       hyper_ck_o,
@@ -142,7 +141,7 @@ module carfield
   output logic [HypNumPhys-1:0][7:0]                  hyper_dq_o,
   output logic [HypNumPhys-1:0]                       hyper_dq_oe_o,
   output logic [HypNumPhys-1:0]                       hyper_reset_no,
-`else
+`ifdef GEN_NO_HYPERBUS
   // LLC interface
   output logic [LlcArWidth-1:0] llc_ar_data,
   output logic [    LogDepth:0] llc_ar_wptr,
@@ -159,7 +158,7 @@ module carfield
   output logic [ LlcWWidth-1:0] llc_w_data,
   output logic [    LogDepth:0] llc_w_wptr,
   input  logic [    LogDepth:0] llc_w_rptr,
-`endif // NO_HYPERBUS
+`endif // GEN_NO_HYPERBUS
 
   // External reg interface slaves (async)
   // Currently for PLL and Padframe
@@ -429,7 +428,7 @@ localparam int unsigned IntClusterAxiMstRWidth  =
 carfield_reg_req_t [iomsb(NumSyncRegSlv):0] ext_reg_req, ext_reg_req_cut;
 carfield_reg_rsp_t [iomsb(NumSyncRegSlv):0] ext_reg_rsp, ext_reg_rsp_cut;
 
-`ifndef NO_HYPERBUS // bender-xilinx.mk
+`ifndef GEN_NO_HYPERBUS // bender-xilinx.mk
 localparam int unsigned LlcIdWidth = Cfg.AxiMstIdWidth   +
                                      $clog2(AxiIn.num_in)+
                                      Cfg.LlcNotBypass    ;
@@ -468,7 +467,7 @@ logic [ LlcWWidth-1:0] llc_w_data;
 logic [    LogDepth:0] llc_w_wptr;
 logic [    LogDepth:0] llc_w_rptr;
 
-`endif // NO_HYPERBUS
+`endif // GEN_NO_HYPERBUS
 
 logic hyper_isolate_req, hyper_isolated_rsp;
 logic security_island_isolate_req;
@@ -1139,7 +1138,7 @@ cheshire i_cheshire_wrap                 (
   .vga_blue_o  (                 )
 );
 
-`ifndef NO_HYPERBUS // bender-xilinx.mk
+`ifndef GEN_NO_HYPERBUS // bender-xilinx.mk
 // Hyperbus
 hyperbus_wrap      #(
   .NumChips         ( HypNumChips                           ),
@@ -1211,7 +1210,7 @@ hyperbus_wrap      #(
   .hyper_dq_oe_o,
   .hyper_reset_no
 );
-`endif // NO_HYPERBUS
+`endif // GEN_NO_HYPERBUS
 
 // Reconfigurable L2 Memory
 // Host Clock Domain

sw/boot/carfield.dts → sw/boot/carfield.dtsi

@@ -38,6 +38,11 @@
       };
     };
   };
+  sysclk: virt_50mhz {
+    #clock-cells = <0>;
+    compatible = "fixed-clock";
+    clock-frequency = <50000000>;
+  };
   soc: soc {
     #address-cells = <2>;
     #size-cells = <2>;
@@ -48,6 +53,10 @@
       reg-names = "control";
       reg = <0x0 0x0 0x0 0x1000>;
     };
+    ctrl-regs@3000000 {
+      compatible = "eth,control-regs";
+      reg = <0x0 0x3000000 0x0 0x1000>;
+    };
     axi_llc@3001000 {
       compatible = "eth,axi-llc";
       reg = <0x0 0x3001000 0x0 0x5000>;
@@ -109,6 +118,11 @@
       riscv,ndev = <51>;
       reg = <0x0 0x4000000 0x0 0x4000000>;
     };
+    gpio@3005000 {
+      compatible = "gpio,carfield";
+      reg = <0x0 0x3005000 0x0 0x1000>;
+      interrupts-extended = <&PLIC0 19 &PLIC0 21 &PLIC0 22 &PLIC0 24>;
+    };
     tcdm@10000000 {
       reg = <0x0 0x10000000 0x0 0x400000>;
     };

sw/boot/carfield_bd_vcu128.dts

@@ -0,0 +1,84 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Cyril Koenig <[email protected]>
+
+
+/include/ "carfield.dtsi"
+
+&soc {
+  eth_dma0: eth_dma@141e00000 {
+    #dma-cells = <1>;
+    #address-cells = <1>;
+    #size-cells = <1>;
+    compatible = "xlnx,axi-dma-1.00.a";
+    reg = <0x1 0x41e00000 0x0 0x10000>;
+    interrupts-extended = <&PLIC0 21 &PLIC0 22>;
+    xlnx,addrwidth = <0x40>;
+    xlnx,include-sg;
+    dma-channel@141e00000 {
+      compatible = "xlnx,axi-dma-mm2s-channel";
+      reg = <0 0>;
+      dma-channels = <0x1>;
+      interrupts-extended = <&PLIC0 21>;
+      xlnx,datawidth = <0x20>;
+      xlnx,device-id = <0x0>;
+      xlnx,include-dre ;
+    };
+    dma-channel@141e00030 {
+      compatible = "xlnx,axi-dma-s2mm-channel";
+      reg = <0 0>;
+      dma-channels = <0x1>;
+      interrupts-extended = <&PLIC0 22>;
+      xlnx,datawidth = <0x20>;
+      xlnx,device-id = <0x0>;
+      xlnx,include-dre ;
+    };
+  };
+  eth0: eth0@140c00000 {
+    compatible = "xlnx,axi-ethernet-1.00.a";
+    reg = <0x1 0x40c00000 0x0 0x40000>;
+    // attacked to system clock, provide name for matching
+    clocks = <&sysclk>, <&sysclk>;
+    clock-names = "s_axi_lite_clk", "axis_clk";
+    // interrupt and mac_irq
+    interrupts-extended = <&PLIC0 19 &PLIC0 24>;
+    //local-mac-address = [ 00 0A 35 04 E1 60 ]; // hero-vcu128-01
+    local-mac-address = [ 00 0A 35 04 E1 52 ]; // hero-vcu128-02
+    mac-address = [ 00 0A 35 04 E1 52 ];
+    device_type = "network";
+    axistream-connected = <&eth_dma0>;
+    axistream-control-connected = <&eth_dma0>;
+    phy-handle = <&dp83867_0>;
+    // xlnx,phy-type = <0x4>; // XAE_PHY_TYPE_SGMII. linux: deprecated, use phy-mode
+    phy-mode = "sgmii";
+    xlnx,phyaddr = <0x0>;
+    xlnx,rxcsum = <0x2>; // 0, 1, 2 for no/partial/full offloading
+    xlnx,rxmem = <0x1000>;
+    xlnx,txcsum = <0x2>; // 0, 1, 2 for no/partial/full offloading
+    xlnx,txmem = <0x1000>;
+
+    mdio: mdio {
+      #address-cells = <1>;
+      #size-cells = <0>;
+      // reset-gpios = <&tca6416a 6 GPIO_ACTIVE_LOW>;
+      // reset-delay-us = <2>;
+      // PCS/PMA PHY
+      xilinx_phy: ethernet-phy@0 {
+        #phy-cells = <1>;
+        device_type = "ethernet-phy";
+        reg = <0>;
+      };
+      // External PHY
+      dp83867_0: ethernet-phy@3 {
+        compatible = "ethernet-phy-ieee802.3-c22";
+        reg = <3>;
+        #phy-cells = <1>;
+        device_type = "ethernet-phy";
+        ti,sgmii-ref-clock-output-enable;
+        ti,dp83867-rxctrl-strap-quirk;
+      };
+    };
+  };
+};

sw/boot/carfield_vanilla_vcu128.dts

@@ -0,0 +1,8 @@
+// Copyright 2022 ETH Zurich and University of Bologna.
+// Solderpad Hardware License, Version 0.51, see LICENSE for details.
+// SPDX-License-Identifier: SHL-0.51
+//
+// Cyril Koenig <[email protected]>
+
+
+/include/ "carfield.dtsi"

sw/sw.mk

@@ -35,6 +35,9 @@ car-sw-libs: $(CAR_SW_LIBS)
 
 # Compilation
 
+carfield_%.dtb: carfield_%.dts
+	$(CHS_SW_DTC) -I dts -O dtb -i $(CAR_SW_DIR)/boot -o $@ $<
+
 # All objects require up-to-date patches and headers
 %.car.o: %.c
 	@echo $(CAR_SW_INCLUDES)
@@ -145,9 +148,15 @@ mibench-automotive-susan: automotive-susan
 # GPT Linux image #
 ###################
 
+CAR_SW_DISK_SIZE := 16M
+
+$(CAR_SW_DIR)/boot/install64/%:
+	@echo "Error: Linux images not found, did you build the cva6-sdk?"
+	@exit 1
+
 # Create full Linux disk image
-$(CAR_SW_DIR)/boot/linux.gpt.bin: $(CHS_SW_DIR)/boot/zsl.rom.bin $(CAR_SW_DIR)/boot/carfield.dtb $(CAR_SW_DIR)/boot/install64/fw_payload.bin $(CAR_SW_DIR)/boot/install64/uImage
-	truncate -s $(CHS_SW_DISK_SIZE) $@
+$(CAR_SW_DIR)/boot/linux_carfield_%.gpt.bin: $(CHS_SW_DIR)/boot/zsl.rom.bin $(CAR_SW_DIR)/boot/carfield_%.dtb $(CAR_SW_DIR)/boot/install64/fw_payload.bin $(CAR_SW_DIR)/boot/install64/uImage
+	truncate -s $(CAR_SW_DISK_SIZE) $@
 	sgdisk --clear -g --set-alignment=1 \
 		--new=1:64:96 --typecode=1:$(CHS_SW_ZSL_TGUID) \
 		--new=2:128:159 --typecode=2:$(CHS_SW_DTB_TGUID) \

target/xilinx/README.md

@@ -1,13 +1,7 @@
-# VCU128 emulation
+## Xilinx compile flow
 
-```bash
-# Build the bitstream:
-make
-# Re-build the bitstream without
-# re-building the IPs:
-make rebuild-top
-# Simulate with the IPs
-# Note you need to generate the
-# Vivado IP models before
-make sim
-```
+The Xilinx compile flow is divided in flavors:
+- vanilla : A pure-verilog compile flow which does not use block design but pre-generates IPs source code.
+- bd : A block design based compile flow which pre-packages a Carfield IP and builds a bitstream out of it.
+
+User inputs variables are defined in xilinx.mk and written in capital letters (ex: XILINX_BOARD), while derived variables are writted in lower case (ex: xilinx_bit).

target/xilinx/flavor_bd/.gitignore

@@ -0,0 +1,6 @@
+.Xil
+carfield_*
+scripts/add_sources.tcl*
+scripts/add_includes.tcl
+out/
+probes.ltx