From ed1e468383d26b80942add21eadca0d854159eb3 Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sat, 20 Jan 2024 11:33:43 +0100 Subject: [PATCH] Unified enablers and address ranges in configuration structure. Fixed errors in interrupt assignment for Spatz. --- hw/carfield.sv | 467 ++++++++++++++++++++--------------------- hw/carfield_cfg_pkg.sv | 259 +++++++++-------------- hw/carfield_pkg.sv | 5 +- hw/cheshire_wrap.sv | 2 +- 4 files changed, 335 insertions(+), 398 deletions(-) diff --git a/hw/carfield.sv b/hw/carfield.sv index c0d0fd245..9ca243278 100644 --- a/hw/carfield.sv +++ b/hw/carfield.sv @@ -23,7 +23,6 @@ module carfield import spatz_cluster_pkg::*; #( parameter cheshire_cfg_t Cfg = carfield_pkg::CarfieldCfgDefault, - parameter islands_cfg_t IslandsCfg = carfield_pkg::IslandsCfgDefault, parameter int unsigned HypNumPhys = 2, parameter int unsigned HypNumChips = 2, `ifdef GEN_NO_HYPERBUS // bender-xilinx.mk @@ -1206,7 +1205,7 @@ localparam int unsigned SpatzMboxOffset = HostdMboxOffset + 3*CheshireNumIntHart // Reconfigurable L2 Memory // Host Clock Domain -if (CarfieldEnIslands.l2) begin +if (CarfieldIslandsCfg.l2_port0.enable) begin: gen_l2 assign reset_vector[CarfieldDomainIdx.l2] = car_regs_reg2hw.l2_rst.q; `ifndef L2_WRAP_NETLIST @@ -1262,7 +1261,7 @@ if (CarfieldEnIslands.l2) begin .l2_ecc_reg_async_mst_data_o ( ext_reg_async_slv_data_in [L2EccIdx-NumSyncRegSlv] ), .ecc_error_o ( l2_ecc_err ) ); -end else begin +end else begin: gen_no_l2 assign l2_ecc_err = '0; end @@ -1315,7 +1314,7 @@ assign safed_intrs = { }; // verilog_lint: waive-stop line-length -if (CarfieldEnIslands.safed) begin : gen_safety_island +if (CarfieldIslandsCfg.safed.enable) begin : gen_safety_island assign reset_vector[CarfieldDomainIdx.safed] = car_regs_reg2hw.safety_island_rst.q; `ifndef SAFED_NETLIST @@ -1476,7 +1475,7 @@ assign car_regs_hw2reg.pulp_cluster_eoc.de = 1'b1; assign car_regs_hw2reg.pulp_cluster_busy.de = 1'b1; assign car_regs_hw2reg.pulp_cluster_eoc.d = pulpcl_eoc; -if (CarfieldEnIslands.pulp) begin : gen_pulp_cluster +if (CarfieldIslandsCfg.pulp.enable) begin : gen_pulp_cluster assign reset_vector[CarfieldDomainIdx.pulp] = car_regs_reg2hw.pulp_cluster_rst.q; `ifndef INT_CLUSTER_NETLIST @@ -1632,7 +1631,7 @@ logic [spatz_cluster_pkg::NumCores-1:0] spatzcl_mbox_intr; // mti (machine timer interrupt) : hostd (RISC-V clint) // verilog_lint: waive-start line-length logic [spatz_cluster_pkg::NumCores-1:0] spatzcl_timer_intr; -if (CarfieldEnIslands.spatz) begin : gen_spatz_cluster +if (CarfieldIslandsCfg.spatz.enable) begin : gen_spatz_cluster assign reset_vector[CarfieldDomainIdx.spatz] = car_regs_reg2hw.spatz_cluster_rst.q; @@ -1743,9 +1742,10 @@ if (CarfieldEnIslands.spatz) begin : gen_spatz_cluster ); for (genvar i = 0; i < spatz_cluster_pkg::NumCores; i++ ) begin : gen_spatzcl_mbox_intrs_spatz_harts - assign safed_spatzcl_mbox_intr[i] = snd_mbox_intrs[i]; - for (genvar j = 0; j < CheshireNumIntHarts; j++ ) begin : gen_spatzcl_mbox_intrs_host_harts - assign hostd_spatzcl_mbox_intr[i][j] = snd_mbox_intrs[spatz_cluster_pkg::NumCores + (spatz_cluster_pkg::NumCores * j) + i]; + assign safed_spatzcl_mbox_intr[i] = snd_mbox_intrs[i]; + for (genvar j = 0; j < CheshireNumIntHarts; j++ ) begin : gen_spatzcl_mbox_intrs_host_harts + assign hostd_spatzcl_mbox_intr[i][j] = snd_mbox_intrs[spatz_cluster_pkg::NumCores + (spatz_cluster_pkg::NumCores * j) + i]; + end end for (genvar i = 0; i < CheshireNumIntHarts; i++ ) begin : gen_spatzcl_mbox_intrs @@ -1762,7 +1762,7 @@ if (CarfieldEnIslands.spatz) begin : gen_spatz_cluster // host domain and the safe domain assign spatzcl_mbox_intr = hostd_spatzcl_mbox_intr_ored | safed_spatzcl_mbox_intr; -end end else begin : gen_no_spatz_cluster +end else begin : gen_no_spatz_cluster assign spatzcl_mbox_intr = '0; assign spatzcl_timer_intr = '0; assign car_regs_hw2reg.spatz_cluster_busy.d = '0; @@ -1777,7 +1777,7 @@ end // Security Island logic secd_mbox_intr; -if (CarfieldEnIslands.secured) begin : gen_secure_subsystem +if (CarfieldIslandsCfg.secured.enable) begin : gen_secure_subsystem assign reset_vector[CarfieldDomainIdx.secured] = car_regs_reg2hw.security_island_rst.q; @@ -2033,244 +2033,243 @@ mailbox_unit #( carfield_axi_slv_req_t axi_ethernet_req; carfield_axi_slv_rsp_t axi_ethernet_rsp; -if (IslandsCfg.EnEthernet) begin : gen_ethernet -axi_cdc_dst #( - .LogDepth ( LogDepth ), - .SyncStages ( SyncStages ), - .aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .w_chan_t ( carfield_axi_slv_w_chan_t ), - .b_chan_t ( carfield_axi_slv_b_chan_t ), - .ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_resp_t ( carfield_axi_slv_rsp_t ) -) i_ethernet_cdc_dst ( - .async_data_slave_aw_data_i ( axi_slv_ext_aw_data [EthernetSlvIdx] ), - .async_data_slave_aw_wptr_i ( axi_slv_ext_aw_wptr [EthernetSlvIdx] ), - .async_data_slave_aw_rptr_o ( axi_slv_ext_aw_rptr [EthernetSlvIdx] ), - .async_data_slave_w_data_i ( axi_slv_ext_w_data [EthernetSlvIdx] ), - .async_data_slave_w_wptr_i ( axi_slv_ext_w_wptr [EthernetSlvIdx] ), - .async_data_slave_w_rptr_o ( axi_slv_ext_w_rptr [EthernetSlvIdx] ), - .async_data_slave_b_data_o ( axi_slv_ext_b_data [EthernetSlvIdx] ), - .async_data_slave_b_wptr_o ( axi_slv_ext_b_wptr [EthernetSlvIdx] ), - .async_data_slave_b_rptr_i ( axi_slv_ext_b_rptr [EthernetSlvIdx] ), - .async_data_slave_ar_data_i ( axi_slv_ext_ar_data [EthernetSlvIdx] ), - .async_data_slave_ar_wptr_i ( axi_slv_ext_ar_wptr [EthernetSlvIdx] ), - .async_data_slave_ar_rptr_o ( axi_slv_ext_ar_rptr [EthernetSlvIdx] ), - .async_data_slave_r_data_o ( axi_slv_ext_r_data [EthernetSlvIdx] ), - .async_data_slave_r_wptr_o ( axi_slv_ext_r_wptr [EthernetSlvIdx] ), - .async_data_slave_r_rptr_i ( axi_slv_ext_r_rptr [EthernetSlvIdx] ), - .dst_clk_i ( periph_clk ), - .dst_rst_ni ( periph_rst_n ), - .dst_req_o ( axi_ethernet_req ), - .dst_resp_i ( axi_ethernet_rsp ) -); +if (carfield_pkg::IslandsCfgDefault.EnEthernet) begin : gen_ethernet + axi_cdc_dst #( + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ), + .aw_chan_t ( carfield_axi_slv_aw_chan_t ), + .w_chan_t ( carfield_axi_slv_w_chan_t ), + .b_chan_t ( carfield_axi_slv_b_chan_t ), + .ar_chan_t ( carfield_axi_slv_ar_chan_t ), + .r_chan_t ( carfield_axi_slv_r_chan_t ), + .axi_req_t ( carfield_axi_slv_req_t ), + .axi_resp_t ( carfield_axi_slv_rsp_t ) + ) i_ethernet_cdc_dst ( + .async_data_slave_aw_data_i ( axi_slv_ext_aw_data [EthernetSlvIdx] ), + .async_data_slave_aw_wptr_i ( axi_slv_ext_aw_wptr [EthernetSlvIdx] ), + .async_data_slave_aw_rptr_o ( axi_slv_ext_aw_rptr [EthernetSlvIdx] ), + .async_data_slave_w_data_i ( axi_slv_ext_w_data [EthernetSlvIdx] ), + .async_data_slave_w_wptr_i ( axi_slv_ext_w_wptr [EthernetSlvIdx] ), + .async_data_slave_w_rptr_o ( axi_slv_ext_w_rptr [EthernetSlvIdx] ), + .async_data_slave_b_data_o ( axi_slv_ext_b_data [EthernetSlvIdx] ), + .async_data_slave_b_wptr_o ( axi_slv_ext_b_wptr [EthernetSlvIdx] ), + .async_data_slave_b_rptr_i ( axi_slv_ext_b_rptr [EthernetSlvIdx] ), + .async_data_slave_ar_data_i ( axi_slv_ext_ar_data [EthernetSlvIdx] ), + .async_data_slave_ar_wptr_i ( axi_slv_ext_ar_wptr [EthernetSlvIdx] ), + .async_data_slave_ar_rptr_o ( axi_slv_ext_ar_rptr [EthernetSlvIdx] ), + .async_data_slave_r_data_o ( axi_slv_ext_r_data [EthernetSlvIdx] ), + .async_data_slave_r_wptr_o ( axi_slv_ext_r_wptr [EthernetSlvIdx] ), + .async_data_slave_r_rptr_i ( axi_slv_ext_r_rptr [EthernetSlvIdx] ), + .dst_clk_i ( periph_clk ), + .dst_rst_ni ( periph_rst_n ), + .dst_req_o ( axi_ethernet_req ), + .dst_resp_i ( axi_ethernet_rsp ) + ); -AXI_BUS #( - .AXI_ADDR_WIDTH( Cfg.AddrWidth ), - .AXI_DATA_WIDTH( Cfg.AxiDataWidth ), - .AXI_ID_WIDTH ( AxiSlvIdWidth ), - .AXI_USER_WIDTH( Cfg.AxiUserWidth ) -) axi_ethernet (); - -`AXI_ASSIGN_FROM_REQ(axi_ethernet, axi_ethernet_req); -`AXI_ASSIGN_TO_RESP(axi_ethernet_rsp, axi_ethernet); - -// The Ethernet RGMII interfaces mandates a clock of 125MHz (in 1GBit mode) for both TX and RX -// clocks. We generate a 125MHz clock starting from the `periph_clk`. The (integer) division value -// is SW-programmable. -localparam int unsigned EthRgmiiPhyClkDivWidth = 20; -// We assume a peripheral clock of 250MHz to get the 125MHz clock for the RGMII interface. Hence, -// the default division value after PoR is 250/125. -localparam int unsigned EthRgmiiPhyClkDivDefaultValue = 2; -logic [EthRgmiiPhyClkDivWidth-1:0] eth_rgmii_phy_clk_div_value; -logic eth_rgmii_phy_clk_div_value_valid; -logic eth_rgmii_phy_clk_div_value_ready; -logic eth_rgmii_phy_clk0; - -// The register file does not support back pressure directly. I.e the hardware side cannot tell -// the regfile that a reg value cannot be written at the moment. This is a problem since the clk -// divider input of the clk_int_div module will stall the transaction until it is safe to change -// the clock division factor. The stream_deposit module converts between these two protocols -// (write-pulse only protocol <-> ready-valid protocol). See the documentation in the header of -// the module for more details. -lossy_valid_to_stream #( - .DATA_WIDTH(EthRgmiiPhyClkDivWidth) -) i_eth_rgmii_phy_clk_div_config_decouple ( - .clk_i ( periph_clk ), - .rst_ni ( periph_rst_n ), - .valid_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_value.qe ), - .data_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_value.q ), - .valid_o ( eth_rgmii_phy_clk_div_value_valid ), - .ready_i ( eth_rgmii_phy_clk_div_value_ready ), - .data_o ( eth_rgmii_phy_clk_div_value ), - .busy_o ( ) -); + AXI_BUS #( + .AXI_ADDR_WIDTH( Cfg.AddrWidth ), + .AXI_DATA_WIDTH( Cfg.AxiDataWidth ), + .AXI_ID_WIDTH ( AxiSlvIdWidth ), + .AXI_USER_WIDTH( Cfg.AxiUserWidth ) + ) axi_ethernet (); + + `AXI_ASSIGN_FROM_REQ(axi_ethernet, axi_ethernet_req); + `AXI_ASSIGN_TO_RESP(axi_ethernet_rsp, axi_ethernet); + + // The Ethernet RGMII interfaces mandates a clock of 125MHz (in 1GBit mode) for both TX and RX + // clocks. We generate a 125MHz clock starting from the `periph_clk`. The (integer) division value + // is SW-programmable. + localparam int unsigned EthRgmiiPhyClkDivWidth = 20; + // We assume a peripheral clock of 250MHz to get the 125MHz clock for the RGMII interface. Hence, + // the default division value after PoR is 250/125. + localparam int unsigned EthRgmiiPhyClkDivDefaultValue = 2; + logic [EthRgmiiPhyClkDivWidth-1:0] eth_rgmii_phy_clk_div_value; + logic eth_rgmii_phy_clk_div_value_valid; + logic eth_rgmii_phy_clk_div_value_ready; + logic eth_rgmii_phy_clk0; -(* no_ungroup *) -(* no_boundary_optimization *) -clk_int_div #( - .DIV_VALUE_WIDTH ( EthRgmiiPhyClkDivWidth ), - .DEFAULT_DIV_VALUE ( EthRgmiiPhyClkDivDefaultValue ), - .ENABLE_CLOCK_IN_RESET ( 0 ) -) i_eth_rgmii_phy_clk_int_div ( - .clk_i ( periph_clk ), - .rst_ni ( periph_rst_n ), - .en_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_en.q ), - .test_mode_en_i ( test_mode_i ), - .div_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_value.q ), - .div_valid_i ( eth_rgmii_phy_clk_div_value_valid ), - .div_ready_o ( eth_rgmii_phy_clk_div_value_ready ), - .clk_o ( eth_rgmii_phy_clk0 ), - .cycl_count_o ( ) -); + // The register file does not support back pressure directly. I.e the hardware side cannot tell + // the regfile that a reg value cannot be written at the moment. This is a problem since the clk + // divider input of the clk_int_div module will stall the transaction until it is safe to change + // the clock division factor. The stream_deposit module converts between these two protocols + // (write-pulse only protocol <-> ready-valid protocol). See the documentation in the header of + // the module for more details. + lossy_valid_to_stream #( + .DATA_WIDTH(EthRgmiiPhyClkDivWidth) + ) i_eth_rgmii_phy_clk_div_config_decouple ( + .clk_i ( periph_clk ), + .rst_ni ( periph_rst_n ), + .valid_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_value.qe ), + .data_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_value.q ), + .valid_o ( eth_rgmii_phy_clk_div_value_valid ), + .ready_i ( eth_rgmii_phy_clk_div_value_ready ), + .data_o ( eth_rgmii_phy_clk_div_value ), + .busy_o ( ) + ); + (* no_ungroup *) + (* no_boundary_optimization *) + clk_int_div #( + .DIV_VALUE_WIDTH ( EthRgmiiPhyClkDivWidth ), + .DEFAULT_DIV_VALUE ( EthRgmiiPhyClkDivDefaultValue ), + .ENABLE_CLOCK_IN_RESET ( 0 ) + ) i_eth_rgmii_phy_clk_int_div ( + .clk_i ( periph_clk ), + .rst_ni ( periph_rst_n ), + .en_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_en.q ), + .test_mode_en_i ( test_mode_i ), + .div_i ( car_regs_reg2hw.eth_rgmii_phy_clk_div_value.q ), + .div_valid_i ( eth_rgmii_phy_clk_div_value_valid ), + .div_ready_o ( eth_rgmii_phy_clk_div_value_ready ), + .clk_o ( eth_rgmii_phy_clk0 ), + .cycl_count_o ( ) + ); -// The Ethernet MDIO interfaces mandates a clock of 2.5MHz. We generate a 2.5MHz clock starting from -// the `periph_clk`. The (integer) division value is SW-programmable. -localparam int unsigned EthMdioClkDivWidth = 20; -// We assume a default peripheral clock of 250 MHz to get the 2.5MHz required for the MDIO -// interface. Hence, the default division value after PoR is 250/2.5 -localparam int unsigned EthMdioClkDivDefaultValue = 100; -logic [EthRgmiiPhyClkDivWidth-1:0] eth_mdio_clk_div_value; -logic eth_mdio_clk_div_value_valid; -logic eth_mdio_clk_div_value_ready; -logic eth_mdio_clk; - -lossy_valid_to_stream #( - .DATA_WIDTH(EthMdioClkDivWidth) -) i_eth_mdio_clk_div_config_decouple ( - .clk_i ( periph_clk ), - .rst_ni ( periph_rst_n ), - .valid_i ( car_regs_reg2hw.eth_mdio_clk_div_value.qe ), - .data_i ( car_regs_reg2hw.eth_mdio_clk_div_value.q ), - .valid_o ( eth_mdio_clk_div_value_valid ), - .ready_i ( eth_mdio_clk_div_value_ready ), - .data_o ( eth_mdio_clk_div_value ), - .busy_o ( ) -); -(* no_ungroup *) -(* no_boundary_optimization *) -clk_int_div #( - .DIV_VALUE_WIDTH ( EthMdioClkDivWidth ), - .DEFAULT_DIV_VALUE ( EthMdioClkDivDefaultValue ), - .ENABLE_CLOCK_IN_RESET ( 0 ) -) i_eth_mdio_clk_int_div ( - .clk_i ( periph_clk ), - .rst_ni ( periph_rst_n ), - .en_i ( car_regs_reg2hw.eth_mdio_clk_div_en.q ), - .test_mode_en_i ( test_mode_i ), - .div_i ( car_regs_reg2hw.eth_mdio_clk_div_value.q ), - .div_valid_i ( eth_mdio_clk_div_value_valid ), - .div_ready_o ( eth_mdio_clk_div_value_ready ), - .clk_o ( eth_mdio_clk ), - .cycl_count_o ( ) -); + // The Ethernet MDIO interfaces mandates a clock of 2.5MHz. We generate a 2.5MHz clock starting from + // the `periph_clk`. The (integer) division value is SW-programmable. + localparam int unsigned EthMdioClkDivWidth = 20; + // We assume a default peripheral clock of 250 MHz to get the 2.5MHz required for the MDIO + // interface. Hence, the default division value after PoR is 250/2.5 + localparam int unsigned EthMdioClkDivDefaultValue = 100; + logic [EthRgmiiPhyClkDivWidth-1:0] eth_mdio_clk_div_value; + logic eth_mdio_clk_div_value_valid; + logic eth_mdio_clk_div_value_ready; + logic eth_mdio_clk; -// Ethernet IP -eth_rgmii #( - .AXI_ADDR_WIDTH ( Cfg.AddrWidth ), - .AXI_DATA_WIDTH ( Cfg.AxiDataWidth ), - .AXI_ID_WIDTH ( AxiSlvIdWidth ), - .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) -) i_eth_rgmii ( - .clk_i ( eth_mdio_clk ), - .clk_200MHz_i ( '0 ), // Only used with FPGA mapping for genesysII in IDELAYCTRL cell's - // ref clk (see IP) - .rst_ni ( periph_rst_n ), - .eth_clk_i ( '0 ), // quadrature (90deg) clk to `phy_tx_clk_i` -> disabled when `USE_CLK90 == - // FALSE` in ethernet IP. See `eth_mac_1g_rgmii_fifo`. In carfieldv1, - // USE_CLK90 == 0, hence changing the clock phase is left to PHY chips on - // the PCB. - - .ethernet ( axi_ethernet ), - - .eth_rxck ( eth_rxck_i ), - .eth_rxctl ( eth_rxctl_i ), - .eth_rxd ( eth_rxd_i ), - - .eth_txck ( eth_txck_o ), - .eth_txctl ( eth_txctl_o ), - .eth_txd ( eth_txd_o ), - - .eth_rst_n ( eth_rst_n_o ), - .phy_tx_clk_i ( eth_rgmii_phy_clk0 ), // in phase (0deg) clk - - // MDIO - .eth_mdio_i ( eth_md_i ), - .eth_mdio_o ( eth_md_o ), - .eth_mdio_oe_o ( eth_md_oe ), - .eth_mdc_o ( eth_mdc_o ), - - .eth_irq ( car_eth_intr ) -); + lossy_valid_to_stream #( + .DATA_WIDTH(EthMdioClkDivWidth) + ) i_eth_mdio_clk_div_config_decouple ( + .clk_i ( periph_clk ), + .rst_ni ( periph_rst_n ), + .valid_i ( car_regs_reg2hw.eth_mdio_clk_div_value.qe ), + .data_i ( car_regs_reg2hw.eth_mdio_clk_div_value.q ), + .valid_o ( eth_mdio_clk_div_value_valid ), + .ready_i ( eth_mdio_clk_div_value_ready ), + .data_o ( eth_mdio_clk_div_value ), + .busy_o ( ) + ); -end else begin : gen_no_ethernet + (* no_ungroup *) + (* no_boundary_optimization *) + clk_int_div #( + .DIV_VALUE_WIDTH ( EthMdioClkDivWidth ), + .DEFAULT_DIV_VALUE ( EthMdioClkDivDefaultValue ), + .ENABLE_CLOCK_IN_RESET ( 0 ) + ) i_eth_mdio_clk_int_div ( + .clk_i ( periph_clk ), + .rst_ni ( periph_rst_n ), + .en_i ( car_regs_reg2hw.eth_mdio_clk_div_en.q ), + .test_mode_en_i ( test_mode_i ), + .div_i ( car_regs_reg2hw.eth_mdio_clk_div_value.q ), + .div_valid_i ( eth_mdio_clk_div_value_valid ), + .div_ready_o ( eth_mdio_clk_div_value_ready ), + .clk_o ( eth_mdio_clk ), + .cycl_count_o ( ) + ); -axi_cdc_dst #( - .LogDepth ( LogDepth ), - .SyncStages ( SyncStages ), - .aw_chan_t ( carfield_axi_slv_aw_chan_t ), - .w_chan_t ( carfield_axi_slv_w_chan_t ), - .b_chan_t ( carfield_axi_slv_b_chan_t ), - .ar_chan_t ( carfield_axi_slv_ar_chan_t ), - .r_chan_t ( carfield_axi_slv_r_chan_t ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_resp_t ( carfield_axi_slv_rsp_t ) -) i_ethernet_cdc_dst ( - .async_data_slave_aw_data_i ( axi_slv_ext_aw_data [EthernetSlvIdx] ), - .async_data_slave_aw_wptr_i ( axi_slv_ext_aw_wptr [EthernetSlvIdx] ), - .async_data_slave_aw_rptr_o ( axi_slv_ext_aw_rptr [EthernetSlvIdx] ), - .async_data_slave_w_data_i ( axi_slv_ext_w_data [EthernetSlvIdx] ), - .async_data_slave_w_wptr_i ( axi_slv_ext_w_wptr [EthernetSlvIdx] ), - .async_data_slave_w_rptr_o ( axi_slv_ext_w_rptr [EthernetSlvIdx] ), - .async_data_slave_b_data_o ( axi_slv_ext_b_data [EthernetSlvIdx] ), - .async_data_slave_b_wptr_o ( axi_slv_ext_b_wptr [EthernetSlvIdx] ), - .async_data_slave_b_rptr_i ( axi_slv_ext_b_rptr [EthernetSlvIdx] ), - .async_data_slave_ar_data_i ( axi_slv_ext_ar_data [EthernetSlvIdx] ), - .async_data_slave_ar_wptr_i ( axi_slv_ext_ar_wptr [EthernetSlvIdx] ), - .async_data_slave_ar_rptr_o ( axi_slv_ext_ar_rptr [EthernetSlvIdx] ), - .async_data_slave_r_data_o ( axi_slv_ext_r_data [EthernetSlvIdx] ), - .async_data_slave_r_wptr_o ( axi_slv_ext_r_wptr [EthernetSlvIdx] ), - .async_data_slave_r_rptr_i ( axi_slv_ext_r_rptr [EthernetSlvIdx] ), - .dst_clk_i ( periph_clk ), - .dst_rst_ni ( periph_rst_n ), - .dst_req_o ( axi_ethernet_req ), - .dst_resp_i ( axi_ethernet_rsp ) -); + // Ethernet IP + eth_rgmii #( + .AXI_ADDR_WIDTH ( Cfg.AddrWidth ), + .AXI_DATA_WIDTH ( Cfg.AxiDataWidth ), + .AXI_ID_WIDTH ( AxiSlvIdWidth ), + .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) + ) i_eth_rgmii ( + .clk_i ( eth_mdio_clk ), + .clk_200MHz_i ( '0 ), // Only used with FPGA mapping for genesysII in IDELAYCTRL cell's + // ref clk (see IP) + .rst_ni ( periph_rst_n ), + .eth_clk_i ( '0 ), // quadrature (90deg) clk to `phy_tx_clk_i` -> disabled when `USE_CLK90 == + // FALSE` in ethernet IP. See `eth_mac_1g_rgmii_fifo`. In carfieldv1, + // USE_CLK90 == 0, hence changing the clock phase is left to PHY chips on + // the PCB. + + .ethernet ( axi_ethernet ), + + .eth_rxck ( eth_rxck_i ), + .eth_rxctl ( eth_rxctl_i ), + .eth_rxd ( eth_rxd_i ), + + .eth_txck ( eth_txck_o ), + .eth_txctl ( eth_txctl_o ), + .eth_txd ( eth_txd_o ), + + .eth_rst_n ( eth_rst_n_o ), + .phy_tx_clk_i ( eth_rgmii_phy_clk0 ), // in phase (0deg) clk + + // MDIO + .eth_mdio_i ( eth_md_i ), + .eth_mdio_o ( eth_md_o ), + .eth_mdio_oe_o ( eth_md_oe ), + .eth_mdc_o ( eth_mdc_o ), + + .eth_irq ( car_eth_intr ) + ); -axi_err_slv #( - .AxiIdWidth ( AxiSlvIdWidth ), - .axi_req_t ( carfield_axi_slv_req_t ), - .axi_resp_t ( carfield_axi_slv_rsp_t ), - .Resp ( axi_pkg::RESP_DECERR ), - .ATOPs ( 1'b0 ), - .MaxTrans ( 4 ) -) i_axi_err_slv_ethernet ( - .clk_i ( periph_clk ), - .rst_ni ( periph_pwr_on_rst_n ), - .test_i ( test_mode_i ), - // slave port - .slv_req_i ( axi_ethernet_req ), - .slv_resp_o ( axi_ethernet_rsp ) -); +end else begin : gen_no_ethernet + + axi_cdc_dst #( + .LogDepth ( LogDepth ), + .SyncStages ( SyncStages ), + .aw_chan_t ( carfield_axi_slv_aw_chan_t ), + .w_chan_t ( carfield_axi_slv_w_chan_t ), + .b_chan_t ( carfield_axi_slv_b_chan_t ), + .ar_chan_t ( carfield_axi_slv_ar_chan_t ), + .r_chan_t ( carfield_axi_slv_r_chan_t ), + .axi_req_t ( carfield_axi_slv_req_t ), + .axi_resp_t ( carfield_axi_slv_rsp_t ) + ) i_ethernet_cdc_dst ( + .async_data_slave_aw_data_i ( axi_slv_ext_aw_data [EthernetSlvIdx] ), + .async_data_slave_aw_wptr_i ( axi_slv_ext_aw_wptr [EthernetSlvIdx] ), + .async_data_slave_aw_rptr_o ( axi_slv_ext_aw_rptr [EthernetSlvIdx] ), + .async_data_slave_w_data_i ( axi_slv_ext_w_data [EthernetSlvIdx] ), + .async_data_slave_w_wptr_i ( axi_slv_ext_w_wptr [EthernetSlvIdx] ), + .async_data_slave_w_rptr_o ( axi_slv_ext_w_rptr [EthernetSlvIdx] ), + .async_data_slave_b_data_o ( axi_slv_ext_b_data [EthernetSlvIdx] ), + .async_data_slave_b_wptr_o ( axi_slv_ext_b_wptr [EthernetSlvIdx] ), + .async_data_slave_b_rptr_i ( axi_slv_ext_b_rptr [EthernetSlvIdx] ), + .async_data_slave_ar_data_i ( axi_slv_ext_ar_data [EthernetSlvIdx] ), + .async_data_slave_ar_wptr_i ( axi_slv_ext_ar_wptr [EthernetSlvIdx] ), + .async_data_slave_ar_rptr_o ( axi_slv_ext_ar_rptr [EthernetSlvIdx] ), + .async_data_slave_r_data_o ( axi_slv_ext_r_data [EthernetSlvIdx] ), + .async_data_slave_r_wptr_o ( axi_slv_ext_r_wptr [EthernetSlvIdx] ), + .async_data_slave_r_rptr_i ( axi_slv_ext_r_rptr [EthernetSlvIdx] ), + .dst_clk_i ( periph_clk ), + .dst_rst_ni ( periph_rst_n ), + .dst_req_o ( axi_ethernet_req ), + .dst_resp_i ( axi_ethernet_rsp ) + ); -assign car_eth_intr = '0; -assign eth_md_o = '0; -assign eth_md_oe = '0; -assign eth_mdc_o = '0; -assign eth_rst_n_o = '0; -assign eth_txck_o = '0; -assign eth_txctl_o = '0; -assign eth_txd_o = '0; + axi_err_slv #( + .AxiIdWidth ( AxiSlvIdWidth ), + .axi_req_t ( carfield_axi_slv_req_t ), + .axi_resp_t ( carfield_axi_slv_rsp_t ), + .Resp ( axi_pkg::RESP_DECERR ), + .ATOPs ( 1'b0 ), + .MaxTrans ( 4 ) + ) i_axi_err_slv_ethernet ( + .clk_i ( periph_clk ), + .rst_ni ( periph_pwr_on_rst_n ), + .test_i ( test_mode_i ), + // slave port + .slv_req_i ( axi_ethernet_req ), + .slv_resp_o ( axi_ethernet_rsp ) + ); + assign car_eth_intr = '0; + assign eth_md_o = '0; + assign eth_md_oe = '0; + assign eth_mdc_o = '0; + assign eth_rst_n_o = '0; + assign eth_txck_o = '0; + assign eth_txctl_o = '0; + assign eth_txd_o = '0; end // APB peripherals // Periph Clock Domain // axi_cdc -> axi_amos -> axi_cut -> axi_to_axilite -> axilite_to_apb -> periph devices -if (CarfieldEnIslands.periph) begin: gen_periph // Handle with care... +if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... assign reset_vector[CarfieldDomainIdx.periph] = car_regs_reg2hw.periph_rst.q; carfield_axi_slv_req_t axi_d64_a48_peripherals_req; carfield_axi_slv_rsp_t axi_d64_a48_peripherals_rsp; @@ -2646,7 +2645,7 @@ if (CarfieldEnIslands.periph) begin: gen_periph // Handle with care... // CAN bus logic [63:0] can_timestamp; assign can_timestamp = '1; - if (IslandsCfg.EnCan) begin : gen_can + if (carfield_pkg::IslandsCfgDefault.EnCan) begin : gen_can can_top_apb #( .rx_buffer_size ( 32 ), .txt_buffer_count ( 2 ), diff --git a/hw/carfield_cfg_pkg.sv b/hw/carfield_cfg_pkg.sv index 681ad8c34..a9d76600d 100644 --- a/hw/carfield_cfg_pkg.sv +++ b/hw/carfield_cfg_pkg.sv @@ -9,39 +9,23 @@ package carfield_cfg_pkg; import cheshire_pkg::*; -// Structure where each field defines if an island -// is present or not. 1: present; 0: not present. typedef struct packed { - bit l2; - bit l2_dualport; - bit safed; - bit ethernet; - bit periph; - bit spatz; - bit pulp; - bit secured; -} enable_islands_t; + bit enable; + doub_bt base; + doub_bt size; +} islands_properties_t; -// Structure used to define the address range of each island. -// N.B. island_cfg_t and enable_islands_t structures could be -// packed into a single one. typedef struct packed { - doub_bt l2_port0_base; - doub_bt l2_port1_base; - doub_bt l2_size; - doub_bt safed_base; - doub_bt safed_size; - doub_bt ethernet_base; - doub_bt ethernet_size; - doub_bt periph_base; - doub_bt periph_size; - doub_bt spatz_base; - doub_bt spatz_size; - doub_bt pulp_base; - doub_bt pulp_size; - doub_bt otmbox_base; - doub_bt otmbox_size; -} island_cfg_t; + islands_properties_t l2_port0; + islands_properties_t l2_port1; + islands_properties_t safed; + islands_properties_t ethernet; + islands_properties_t periph; + islands_properties_t spatz; + islands_properties_t pulp; + islands_properties_t secured; + islands_properties_t mbox; +} islands_cfg_t; // Types are obtained from Cheshire package // Parameter MaxExtAxiSlvWidth is obtained from Cheshire @@ -75,207 +59,162 @@ typedef struct packed { // TODO: specify this is for AXI // Generate the number of AXI slave devices to be connected to the // crossbar starting from the islands enable structure. -function automatic int unsigned gen_num_slave(enable_islands_t en); +function automatic int unsigned gen_num_slave(islands_cfg_t island_cfg); int unsigned ret = 0; // Number of slaves starts from 0 - if (en.l2) begin + if (island_cfg.l2_port0.enable) begin ret++; // If we enable L2, we increase by 1 - if (en.l2_dualport) + if (island_cfg.l2_port1.enable) ret++; // If the L2 is dualport, increase again end - if (en.safed ) begin ret++; end - if (en.periph ) begin ret++; end - if (en.ethernet) begin ret++; end - if (en.spatz ) begin ret++; end - if (en.pulp ) begin ret++; end - if (en.secured ) begin ret++; end + if (island_cfg.safed.enable ) begin ret++; end + if (island_cfg.periph.enable ) begin ret++; end + if (island_cfg.ethernet.enable) begin ret++; end + if (island_cfg.spatz.enable ) begin ret++; end + if (island_cfg.pulp.enable ) begin ret++; end + if (island_cfg.mbox.enable ) begin ret++; end return ret; endfunction // TODO: specify this is for AXI // Generate the IDs for each AXI slave device -// function automatic carfield_slave_idx_t carfield_gen_slave_idx(enable_islands_t en); -// carfield_slave_idx_t ret = 0; // Initialize struct first -// int unsigned i = 0; -// if (en.l2) begin ret.l2_port0 = i; i++; -// if (en.l2_dualport) begin ret.l2_port1 = i; i++; end -// end -// if (en.safed ) begin ret.safed = i; i++; end -// if (en.ethernet) begin ret.ethernet = i; i++; end -// if (en.periph ) begin ret.periph = i; i++; end -// if (en.spatz ) begin ret.spatz = i; i++; end -// if (en.pulp ) begin ret.pulp = i; i++; end -// if (en.secured ) begin ret.mbox = i; i++; end -// return ret; -// endfunction - -function automatic carfield_slave_idx_t carfield_gen_slave_idx(enable_islands_t en); +function automatic carfield_slave_idx_t carfield_gen_slave_idx(islands_cfg_t island_cfg); carfield_slave_idx_t ret = '{default: '1}; // Initialize struct first int unsigned i = 0; int unsigned j = 0; - if (en.l2) begin ret.l2_port0 = i; i++; - if (en.l2_dualport) begin ret.l2_port1 = i; i++; end + if (island_cfg.l2_port0.enable) begin ret.l2_port0 = i; i++; + if (island_cfg.l2_port1.enable) begin ret.l2_port1 = i; i++; end end else begin ret.l2_port0 = ret.l2_port0 - j; j++; ret.l2_port1 = ret.l2_port1 - j; j++; end - if (en.safed ) begin ret.safed = i; i++; + if (island_cfg.safed.enable) begin ret.safed = i; i++; end else begin j++; ret.safed = ret.safed - j; end - if (en.ethernet) begin ret.ethernet = i; i++; + if (island_cfg.ethernet.enable) begin ret.ethernet = i; i++; end else begin j++; ret.ethernet = ret.ethernet - j; end - if (en.periph ) begin ret.periph = i; i++; + if (island_cfg.periph.enable) begin ret.periph = i; i++; end else begin j++; ret.periph = ret.periph - j; end - if (en.spatz ) begin ret.spatz = i; i++; + if (island_cfg.spatz.enable) begin ret.spatz = i; i++; end else begin j++; ret.spatz = ret.spatz - j; end - if (en.pulp ) begin ret.pulp = i; i++; + if (island_cfg.pulp.enable) begin ret.pulp = i; i++; end else begin j++; ret.pulp = ret.pulp - j; end - if (en.secured ) begin ret.mbox = i; i++; + if (island_cfg.mbox.enable) begin ret.mbox = i; i++; end else begin j++; ret.mbox = ret.mbox - j; end - - // $info("L2 port 0 index is %d", ret.l2_port0); - // $info("L2 port 1 index is %d", ret.l2_port1); - // $info("Safed index is %d", ret.safed); - // $info("Ethernet index is %d", ret.ethernet); - // $info("Peripheral index is %d", ret.periph); - // $info("Spatz index is %d", ret.spatz); - // $info("PULP index is %d", ret.pulp); - // $info("Mailbox index is %d", ret.mbox); return ret; endfunction // TODO: specify this is for AXI // Generate the number of AXI master devices that connect to the // crossbar starting from the islands enable structure. -function automatic int unsigned gen_num_master(enable_islands_t en); +function automatic int unsigned gen_num_master(islands_cfg_t island_cfg); int unsigned ret = 0; // Number of masters starts from 0 - if (en.safed ) begin ret++; end - if (en.spatz ) begin ret++; end - if (en.pulp ) begin ret++; end - if (en.secured) begin ret++; end + if (island_cfg.safed.enable ) begin ret++; end + if (island_cfg.spatz.enable ) begin ret++; end + if (island_cfg.pulp.enable ) begin ret++; end + if (island_cfg.secured.enable) begin ret++; end return ret; endfunction // TODO: specify this is for AXI // Generate the IDs for each AXI master device -function automatic carfield_master_idx_t carfield_gen_master_idx(enable_islands_t en); +function automatic carfield_master_idx_t carfield_gen_master_idx(islands_cfg_t island_cfg); carfield_master_idx_t ret = '{default: '0}; // Initialize struct first int unsigned i = 0; int unsigned j = 0; - if (en.safed ) begin ret.safed = i; i++; end else begin j++; ret.safed = ret.safed - j; end - if (en.secured ) begin ret.secured = i; i++; end else begin j++; ret.secured = ret.secured - j; end - if (en.spatz ) begin ret.spatz = i; i++; end else begin j++; ret.spatz = ret.spatz - j; end - if (en.pulp ) begin ret.pulp = i; i++; end else begin j++; ret.pulp = ret.pulp - j; end + if (island_cfg.safed.enable ) begin ret.safed = i; i++; end else begin j++; ret.safed = ret.safed - j; end + if (island_cfg.secured.enable ) begin ret.secured = i; i++; end else begin j++; ret.secured = ret.secured - j; end + if (island_cfg.spatz.enable ) begin ret.spatz = i; i++; end else begin j++; ret.spatz = ret.spatz - j; end + if (island_cfg.pulp.enable ) begin ret.pulp = i; i++; end else begin j++; ret.pulp = ret.pulp - j; end return ret; endfunction -// Starting from the islands map and the islands enable structures, -// this function will generate structure to be passed for the -// generation or not of AXI crossbar ports for each slave. -function automatic axi_struct_t carfield_gen_axi_map(int unsigned NumSlave, enable_islands_t en_islands, island_cfg_t island_cfg); +function automatic axi_struct_t carfield_gen_axi_map(int unsigned NumSlave, islands_cfg_t island_cfg); axi_struct_t ret = '0; // Initialize the map first int unsigned i = 0; - if (en_islands.l2) begin + if (island_cfg.l2_port0.enable) begin ret.AxiIdx[i] = i; - ret.AxiStart[i] = island_cfg.l2_port0_base; - ret.AxiEnd[i] = island_cfg.l2_port0_base + island_cfg.l2_size; + ret.AxiStart[i] = island_cfg.l2_port0.base; + ret.AxiEnd[i] = island_cfg.l2_port0.base + island_cfg.l2_port0.size; if (i < NumSlave - 1) i++; - if (en_islands.l2_dualport) begin + if (island_cfg.l2_port1.enable) begin ret.AxiIdx[i] = i; - ret.AxiStart[i] = island_cfg.l2_port1_base; - ret.AxiEnd[i] = island_cfg.l2_port1_base + island_cfg.l2_size; + ret.AxiStart[i] = island_cfg.l2_port1.base; + ret.AxiEnd[i] = island_cfg.l2_port1.base + island_cfg.l2_port1.size; if (i < NumSlave - 1) i++; end end - if (en_islands.safed) begin + if (island_cfg.safed.enable) begin ret.AxiIdx[i] = i; - ret.AxiStart[i] = island_cfg.safed_base; - ret.AxiEnd[i] = island_cfg.safed_base + island_cfg.safed_size; + ret.AxiStart[i] = island_cfg.safed.base; + ret.AxiEnd[i] = island_cfg.safed.base + island_cfg.safed.size; if (i < NumSlave - 1) i++; end - if (en_islands.ethernet) begin + if (island_cfg.ethernet.enable) begin ret.AxiIdx[i] = i; - ret.AxiStart[i] = island_cfg.ethernet_base; - ret.AxiEnd[i] = island_cfg.ethernet_base + island_cfg.ethernet_size; + ret.AxiStart[i] = island_cfg.ethernet.base; + ret.AxiEnd[i] = island_cfg.ethernet.base + island_cfg.ethernet.size; if (i < NumSlave - 1) i++; end - if (en_islands.periph) begin + if (island_cfg.periph.enable) begin ret.AxiIdx[i] = i; - ret.AxiStart[i] = island_cfg.periph_base; - ret.AxiEnd[i] = island_cfg.periph_base + island_cfg.periph_size; + ret.AxiStart[i] = island_cfg.periph.base; + ret.AxiEnd[i] = island_cfg.periph.base + island_cfg.periph.size; if (i < NumSlave - 1) i++; end - if (en_islands.spatz) begin + if (island_cfg.spatz.enable) begin ret.AxiIdx[i] = i; - ret.AxiStart[i] = island_cfg.spatz_base; - ret.AxiEnd[i] = island_cfg.spatz_base + island_cfg.spatz_size; + ret.AxiStart[i] = island_cfg.spatz.base; + ret.AxiEnd[i] = island_cfg.spatz.base + island_cfg.spatz.size; if (i < NumSlave - 1) i++; end - if (en_islands.pulp) begin + if (island_cfg.pulp.enable) begin ret.AxiIdx[i] = i; - ret.AxiStart[i] = island_cfg.pulp_base; - ret.AxiEnd[i] = island_cfg.pulp_base + island_cfg.pulp_size; + ret.AxiStart[i] = island_cfg.pulp.base; + ret.AxiEnd[i] = island_cfg.pulp.base + island_cfg.pulp.size; if (i < NumSlave - 1) i++; end - if (en_islands.secured) begin + if (island_cfg.mbox.enable) begin ret.AxiIdx[i] = i; - ret.AxiStart[i] = island_cfg.otmbox_base; - ret.AxiEnd[i] = island_cfg.otmbox_base + island_cfg.otmbox_size; + ret.AxiStart[i] = island_cfg.mbox.base; + ret.AxiEnd[i] = island_cfg.mbox.base + island_cfg.mbox.size; if (i < NumSlave - 1) i++; end return ret; endfunction // Generate number of existent domains -function automatic int unsigned gen_carfield_domains(enable_islands_t en); +function automatic int unsigned gen_carfield_domains(islands_cfg_t island_cfg); int unsigned ret = 0; // Number of availale domains starts from 0 - if (en.l2 ) begin ret++; end - if (en.safed ) begin ret++; end - if (en.periph ) begin ret++; end - if (en.spatz ) begin ret++; end - if (en.pulp ) begin ret++; end - if (en.secured ) begin ret++; end + if (island_cfg.l2_port0.enable) begin ret++; end + if (island_cfg.safed.enable ) begin ret++; end + if (island_cfg.periph.enable ) begin ret++; end + if (island_cfg.spatz.enable ) begin ret++; end + if (island_cfg.pulp.enable ) begin ret++; end + if (island_cfg.secured.enable ) begin ret++; end return ret; endfunction -localparam enable_islands_t CarfieldEnIslands = '{ - l2: 1, - l2_dualport: 1, - safed: 1, - ethernet: 0, - periph: 1, - spatz: 0, - pulp: 1, - secured: 1 -}; - -localparam island_cfg_t CarfieldIslandCfg = '{ - l2_port0_base: 'h78000000, - l2_port1_base: 'h78200000, - l2_size: 'h00200000, - safed_base: 'h60000000, - safed_size: 'h00800000, - ethernet_base: 'h20000000, - ethernet_size: 'h00001000, - periph_base: 'h20001000, - periph_size: 'h00009000, - spatz_base: 'h51000000, - spatz_size: 'h00800000, - pulp_base: 'h50000000, - pulp_size: 'h00800000, - otmbox_base: 'h40000000, - otmbox_size: 'h00001000 +// All fields below are in the form: '{enable, base address, address size}. +localparam islands_cfg_t CarfieldIslandsCfg = '{ + l2_port0: '{1, 'h78000000, 'h00200000}, + l2_port1: '{1, 'h78200000, 'h00200000}, + safed: '{1, 'h60000000, 'h00800000}, + ethernet: '{1, 'h20000000, 'h00001000}, + periph: '{1, 'h20010000, 'h00009000}, + spatz: '{1, 'h51000000, 'h00800000}, + pulp: '{1, 'h50000000, 'h00800000}, + secured: '{1, '1, '1 }, // We do not address opentitan, base address and size are not used. + mbox: '{1, 'h40000000, 'h00001000} }; // TODO: specify this is for AXI -localparam int unsigned CarfieldNumSlaves = gen_num_slave(CarfieldEnIslands); -localparam carfield_slave_idx_t CarfieldSlvIdx = carfield_gen_slave_idx(CarfieldEnIslands); -localparam int unsigned CarfieldNumMasters = gen_num_master(CarfieldEnIslands); -localparam carfield_master_idx_t CarfieldMstIdx = carfield_gen_master_idx(CarfieldEnIslands); - -localparam axi_struct_t CarfieldAxiMap = carfield_gen_axi_map(CarfieldNumSlaves, CarfieldEnIslands, CarfieldIslandCfg); +localparam int unsigned CarfieldNumSlaves = gen_num_slave(CarfieldIslandsCfg); +localparam carfield_slave_idx_t CarfieldSlvIdx = carfield_gen_slave_idx(CarfieldIslandsCfg); +localparam int unsigned CarfieldNumMasters = gen_num_master(CarfieldIslandsCfg); +localparam carfield_master_idx_t CarfieldMstIdx = carfield_gen_master_idx(CarfieldIslandsCfg); -// localparam int unsigned CarfieldNumDomains = gen_num_domains(CarfieldEnIslands); +localparam axi_struct_t CarfieldAxiMap = carfield_gen_axi_map(CarfieldNumSlaves, CarfieldIslandsCfg); -localparam int unsigned CarfieldNumDomains = gen_carfield_domains(CarfieldEnIslands); +localparam int unsigned CarfieldNumDomains = gen_carfield_domains(CarfieldIslandsCfg); typedef struct { int unsigned clock_div_value[CarfieldNumDomains]; @@ -298,18 +237,18 @@ typedef struct packed { byte_bt periph; } carfield_domain_idx_t; -function automatic carfield_domain_idx_t gen_domain_idx(enable_islands_t en); +function automatic carfield_domain_idx_t gen_domain_idx(islands_cfg_t island_cfg); carfield_domain_idx_t ret = '{default: '0}; int unsigned i = 0; - if (en.l2 ) begin ret.l2 = i; i++; end - if (en.spatz ) begin ret.spatz = i; i++; end - if (en.pulp ) begin ret.pulp = i; i++; end - if (en.secured ) begin ret.secured = i; i++; end - if (en.safed ) begin ret.safed = i; i++; end - if (en.periph ) begin ret.periph = i; i++; end + if (island_cfg.l2_port0.enable ) begin ret.l2 = i; i++; end + if (island_cfg.spatz.enable ) begin ret.spatz = i; i++; end + if (island_cfg.pulp.enable ) begin ret.pulp = i; i++; end + if (island_cfg.secured.enable ) begin ret.secured = i; i++; end + if (island_cfg.safed.enable ) begin ret.safed = i; i++; end + if (island_cfg.periph.enable ) begin ret.periph = i; i++; end return ret; endfunction -localparam carfield_domain_idx_t CarfieldDomainIdx = gen_domain_idx(CarfieldEnIslands); +localparam carfield_domain_idx_t CarfieldDomainIdx = gen_domain_idx(CarfieldIslandsCfg); endpackage diff --git a/hw/carfield_pkg.sv b/hw/carfield_pkg.sv index 13876f50d..8334852e2 100644 --- a/hw/carfield_pkg.sv +++ b/hw/carfield_pkg.sv @@ -409,10 +409,10 @@ typedef struct packed { bit EnOpenTitan; bit EnCan; bit EnEthernet; -} islands_cfg_t; +} islands_fpga_cfg_t; // Enable all islands by default -localparam islands_cfg_t IslandsCfgDefault = '{ +localparam islands_fpga_cfg_t IslandsCfgDefault = '{ EnPulpCluster : 1, EnSafetyIsland : 1, EnSpatzCluster : 1, @@ -502,7 +502,6 @@ typedef logic [IntClusterAxiIdOutWidth-1:0] intclust_idout_t; // 6 clock gateable Subdomains in Carfield: periph_domain, safety_island, security_isalnd, spatz & // pulp_cluster, L2 shared memory -// localparam int unsigned NumDomains = carfield_cfg_pkg::CarfieldNumDomains; localparam int unsigned NumDomains = carfield_cfg_pkg::CarfieldNumDomains; typedef struct packed { diff --git a/hw/cheshire_wrap.sv b/hw/cheshire_wrap.sv index d817cd9f4..89cf9408e 100644 --- a/hw/cheshire_wrap.sv +++ b/hw/cheshire_wrap.sv @@ -594,7 +594,7 @@ axi_cdc_src #( .async_data_master_r_rptr_o ( llc_mst_r_rptr_o ) ); -if (CarfieldEnIslands.pulp) begin : gen_pulp_cluster +if (carfield_cfg_pkg::CarfieldIslandsCfg.pulp) begin : gen_pulp_cluster // Integer Cluster slave bus axi_intcluster_slv_req_t axi_intcluster_ser_slv_req, axi_intcluster_ser_isolated_slv_req; axi_intcluster_slv_rsp_t axi_intcluster_ser_slv_rsp, axi_intcluster_ser_isolated_slv_rsp;