fpga: Refactor xilinx_ips

Bender.yml

@@ -79,8 +79,8 @@ sources:
     files:
       - target/xilinx/src/cdc_dst_axi_err.sv
       - target/xilinx/src/overrides/tc_clk_xilinx.sv
-      - target/xilinx/flavor_bd/src/carfield_xilinx.sv
-      - target/xilinx/flavor_bd/src/carfield_xilinx_ip.v
+      - target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv
+      - target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx_ip.v
 
   - target: intel16_elab_only
     files:

bender-xilinx.mk

@@ -5,15 +5,15 @@
 # Author: Cyril Koenig <[email protected]>
 
 # bender targets
-xilinx_targs += -t fpga
+xilinx_targs_common += -t fpga
 
 # bender defines
-xilinx_defs += -D PULP_FPGA_EMUL
+xilinx_defs_common += -D PULP_FPGA_EMUL
 
 # Conditionally add GEN_{island} to bender define
 define check_enable_island
 ifeq ($($(1)),1)
-xilinx_defs += -D$(1)=1
+xilinx_defs_common += -D$(1)=1
 endif
 endef
 
@@ -25,7 +25,7 @@ $(eval $(call check_enable_island,GEN_NO_HYPERBUS))
 $(eval $(call check_enable_island,GEN_EXT_JTAG))
 
 ifeq ($(GEN_EXT_JTAG),0)
-xilinx_targs += -t bscane
+xilinx_targs_common += -t bscane
 endif
 
 # note : bender targets are later modified in xilinx.mk

target/xilinx/flavor_bd/flavor_bd.mk

@@ -7,6 +7,11 @@
 # Output bitstream
 xilinx_bit_bd = $(CAR_XIL_DIR)/flavor_bd/out/design_1_wrapper.bit
 
+# This flavor requires pre-compiled Xilinx IPs
+xilinx_ips_names_bd := carfield_ip
+# Path to compiled ips
+xilinx_ips_paths_bd := $(foreach ip-name,$(xilinx_ips_names_bd),$(xilinx_ip_dir)/$(ip-name)/$(ip-name).srcs/sources_1/ip/$(ip-name)/$(ip-name).xci)
+
 # Vivado variables
 vivado_env_bd := \
     XILINX_PROJECT=$(XILINX_PROJECT) \
@@ -24,33 +29,23 @@ vivado_env_bd := \
     XILINX_ELABORATION_ONLY=$(XILINX_ELABORATION_ONLY)
 
 # Flavor specific bender args
-xilinx_targs_bd := $(xilinx_targs) -t xilinx_bd -t $(XILINX_BOARD)
-xilinx_defs_bd := $(xilinx_defs)
-
-# Add source files for ip
-$(CAR_XIL_DIR)/flavor_bd/scripts/add_sources.tcl: Bender.yml
-	$(BENDER) script vivado $(common_targs) $(xilinx_targs_bd) $(common_defs) $(xilinx_defs_bd) > $@
-	cp $@ $@.bak
-# Remove ibex's vendored prim includes as they conflict with opentitan's vendored prim includes
-	grep -v -P "lowrisc_ip/ip/prim/rtl" $@ > $@-tmp
-	mv $@-tmp $@
-# Override system verilog files
-	target/xilinx/scripts/overrides.sh $@
-	echo "" >> $@
-
-# Build Carfield IP
-$(CAR_XIL_DIR)/flavor_bd/carfield_ip/carfield_ip.xpr: $(CAR_XIL_DIR)/flavor_bd/scripts/add_sources.tcl
-	cd $(CAR_XIL_DIR)/flavor_bd && $(vivado_env) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run_carfield_ip.tcl
+xilinx_targs_bd := $(common_targs) $(xilinx_targs_common) -t xilinx_bd -t $(XILINX_BOARD)
+xilinx_defs_bd := $(common_defs) $(xilinx_defs_common)
 
 # Add includes files for block design
 $(CAR_XIL_DIR)/flavor_bd/scripts/add_includes.tcl:
-	${BENDER} script vivado --only-defines --only-includes $(common_targs) $(xilinx_targs_bd) $(common_defs) $(xilinx_defs_bd) > $@
+	${BENDER} script vivado --only-defines --only-includes $(xilinx_targs_bd) $(xilinx_defs_bd) > $@
 # Remove ibex's vendored prim includes as they conflict with opentitan's vendored prim includes
 	grep -v -P "lowrisc_ip/ip/prim/rtl" $@ > $@-tmp
 	mv $@-tmp $@
 
 # Build block design bitstream
-$(CAR_XIL_DIR)/flavor_bd/out/%.bit: $(CAR_XIL_DIR)/flavor_bd/scripts/add_includes.tcl $(CAR_XIL_DIR)/flavor_bd/carfield_ip/carfield_ip.xpr
+$(CAR_XIL_DIR)/flavor_bd/out/%.bit: $(xilinx_ips_paths_bd) $(CAR_XIL_DIR)/flavor_bd/scripts/add_includes.tcl
 	mkdir -p $(CAR_XIL_DIR)/flavor_bd/out
 	cd $(CAR_XIL_DIR)/flavor_bd && $(vivado_env_bd) $(VIVADO) $(VIVADO_FLAGS) -source scripts/run.tcl
 	find $(CAR_XIL_DIR)/flavor_bd -name "*.ltx" -o -name "*.bit" -o -name "*routed.rpt" | xargs -I {} cp {} $(CAR_XIL_DIR)/flavor_bd/out
+
+car-xil-clean-bd:
+	cd $(CAR_XIL_DIR)/flavor_bd && rm -rf scripts/add_includes.tcl* *.log *.jou *.str *.mif carfield_$(XILINX_BOARD) .Xil/
+
+.PHONY: car-xil-clean-bd

target/xilinx/flavor_bd/scripts/run.tcl

@@ -14,16 +14,17 @@ set_property XPM_LIBRARIES XPM_MEMORY [current_project]
 # set number of threads to 8 (maximum, unfortunately)
 set_param general.maxThreads 8
 
-# Define sources
-set_property ip_repo_paths ./carfield_ip [current_project]
+# Include custom IP
+set_property ip_repo_paths ../xilinx_ips/carfield_ip [current_project]
 update_ip_catalog
 
+# Define sources
 import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD).xdc
+source scripts/add_includes.tcl
 
+# Build block design
 source scripts/carfield_bd_$::env(XILINX_BOARD).tcl
 
-source scripts/add_includes.tcl
-
 # Add the ext_jtag pins to block design
 if {[info exists ::env(GEN_EXT_JTAG)] && ($::env(GEN_EXT_JTAG)==1)} {
   source scripts/carfield_bd_ext_jtag.tcl

target/xilinx/flavor_vanilla/flavor_vanilla.mk

@@ -15,9 +15,9 @@ xilinx_ips_paths_vanilla = $(foreach ip-name,$(xilinx_ips_names_vanilla),$(xilin
 
 # Flavor specific bender args
 # (added enabled ips in bender args, used by phy_definitions.svh)
-xilinx_targs_vanilla  = $(xilinx_targs) $(foreach ip-name,$(xilinx_ips_names_vanilla),$(addprefix -t ,$(ip-name)))
+xilinx_targs_vanilla  = $(xilinx_targs_common) $(foreach ip-name,$(xilinx_ips_names_vanilla),$(addprefix -t ,$(ip-name)))
 xilinx_targs_vanilla += -t xilinx_vanilla $(addprefix -t ,$(XILINX_BOARD))
-xilinx_defs_vanilla := $(xilinx_defs)
+xilinx_defs_vanilla := $(common_defs) $(xilinx_defs_common)
 
 # Vivado variables
 vivado_env_vanilla := \
@@ -53,3 +53,5 @@ $(CAR_XIL_DIR)/flavor_vanilla/out/%.bit: $(xilinx_ips_paths_vanilla) $(CAR_XIL_D
 
 car-xil-clean-vanilla:
 	cd $(CAR_XIL_DIR)/flavor_vanilla && rm -rf scripts/add_sources.tcl* *.log *.jou *.str *.mif carfield.* .Xil/
+
+.PHONY: car-xil-clean-vanilla

target/xilinx/flavor_vanilla/scripts/run.tcl

@@ -33,8 +33,8 @@ set_property top ${project}_top_xilinx [current_fileset]
 
 update_compile_order -fileset sources_1
 
-if {[info exists ::env(ELABORATION_ONLY)] && $::env(XILINX_ELABORATION_ONLY)==1} {
-  puts "Running with ELABORATION_ONLY"
+if {[info exists ::env(XILINX_ELABORATION_ONLY)] && $::env(XILINX_ELABORATION_ONLY)==1} {
+  puts "Running with XILINX_ELABORATION_ONLY"
   set_property XPM_LIBRARIES XPM_MEMORY [current_project]
 
   synth_design -rtl -name rtl_1 -sfcu

target/xilinx/xilinx.mk

@@ -5,7 +5,7 @@
 # Cyril Koenig <[email protected]>
 
 #
-# User input Makefile variables
+# Makefile variables (user inputs are in capital letters)
 #
 
 XILINX_PROJECT ?= carfield
@@ -30,13 +30,11 @@ XILINX_CHECK_TIMING ?= 0
 VIVADO_MODE  ?= batch
 VIVADO_FLAGS ?= -nojournal -mode $(VIVADO_MODE)
 
-xilinx_ip_dir  := $(CAR_XIL_DIR)/xilinx_ips
-xilinx_ip_dirs := $(wildcard $(xilinx_ip_dir)/*)
-
+xilinx_ip_dir := $(CAR_XIL_DIR)/xilinx_ips
 xilinx_bit := $(CAR_XIL_DIR)/out/$(XILINX_PROJECT)_$(XILINX_FLAVOR)_$(XILINX_BOARD).bit
 
 #
-# Include flavors
+# Include other makefiles flavors
 #
 
 include $(CAR_XIL_DIR)/flavor_vanilla/flavor_vanilla.mk
@@ -47,19 +45,20 @@ include $(CAR_XIL_DIR)/flavor_bd/flavor_bd.mk
 #
 
 vivado_env := $(vivado_env_$(XILINX_FLAVOR))
+xilinx_targs := $(xilinx_targs_$(XILINX_FLAVOR))
+xilinx_defs := $(xilinx_defs_$(XILINX_FLAVOR))
 
 #
-# Rules
+# IPs compile rules
 #
 
-# Generate ips
-%.xci:
-	${MAKE} -C $(xilinx_ip_dir)/$(basename $(notdir $@)) \
-	XILINX_USE_ARTIFACTS=$(XILINX_USE_ARTIFACTS) \
-	XILINX_ARTIFACTS_ROOT=$(XILINX_ARTIFACTS_ROOT) \
-	vivado_env="$(subst ",\",$(vivado_env))" \
-	VIVADO="$(VIVADO)" \
-	clean all
+# Note: at the moment xilinx_ips uses vivado_env defined above,
+# but it could re-define its own vivado_env and xilinx_targs
+include $(CAR_XIL_DIR)/xilinx_ips/xilinx_ips.mk
+
+#
+# Top level compile rules
+#
 
 # Copy bitstream and probe file to final output location (/target/xilinx/out)
 $(CAR_XIL_DIR)/out/%.bit: $(xilinx_bit_$(XILINX_FLAVOR))
@@ -69,8 +68,8 @@ $(CAR_XIL_DIR)/out/%.bit: $(xilinx_bit_$(XILINX_FLAVOR))
 		cp $(patsubst %.bit,%.ltx,$< $@); \
 	fi
 
-# Build a bitstream
-car-xil-all: car-xil-clean-ips $(xilinx_bit)
+# Build bitstream
+car-xil-all: $(xilinx_bit)
 
 # Program last bitstream
 car-xil-program:
@@ -81,12 +80,6 @@ car-xil-program:
 car-xil-flash: $(CAR_SW_DIR)/boot/linux_carfield_$(XILINX_FLAVOR)_$(XILINX_BOARD).gpt.bin
 	$(vivado_env) FILE=$< OFFSET=0 $(VIVADO) $(VIVADO_FLAGS) -source $(CAR_XIL_DIR)/scripts/flash_spi.tcl
 
-# Clean a given IP folder
-%-xlnx-ip-clean: %
-	make -C $< clean
-# Clean all IP folder using rule above
-car-xil-clean-ips: $(addsuffix -xlnx-ip-clean,$(shell find $(xilinx_ip_dir)/ -maxdepth 1 -mindepth 1 -type d))
-
-car-xil-clean: car-xil-clean-ips car-xil-clean-vanilla
+car-xil-clean: car-xil-clean-vanilla car-xil-clean-bd xilinx-ip-clean-all
 
-.PHONY: car-xil-program car-xil-flash car-xil-clean car-xil-all car-xil-clean-ips
+.PHONY: car-xil-program car-xil-flash car-xil-clean car-xil-all

target/xilinx/xilinx_ips/.gitignore

@@ -1,5 +1,10 @@
-xlnx*/*
-!xlnx*/tcl
-!Makefile
-!common.mk
-!*.prj
+*.cache
+*.gen
+*.hw
+*.srcs
+*.xpr
+component.xml
+xgui
+*.jou
+*.log
+add_sources.*

target/xilinx/xilinx_ips/carfield_ip/carfield_ip.mk

@@ -0,0 +1,21 @@
+# Copyright 2022 ETH Zurich and University of Bologna.
+# Licensed under the Apache License, Version 2.0, see LICENSE for details.
+# SPDX-License-Identifier: Apache-2.0
+
+ROOT_carfield_ip                 := $(CAR_XIL_DIR)/xilinx_ips/carfield_ip
+XILINX_USE_ARTIFACTS_carfield_ip := 0
+
+# Add additional requirements for this ip
+IP_DEP_carfield_ip := $(CAR_XIL_DIR)/xilinx_ips/carfield_ip/tcl/add_sources.tcl
+
+# Generate the bender script for the ip
+$(CAR_XIL_DIR)/xilinx_ips/carfield_ip/tcl/add_sources.tcl: Bender.yml
+# Add source files for ip
+	$(BENDER) script vivado $(xilinx_targs) $(common_defs) $(xilinx_defs_bd) > $@
+	cp $@ [email protected]
+# Remove ibex's vendored prim includes as they conflict with opentitan's vendored prim includes
+	grep -v -P "lowrisc_ip/ip/prim/rtl" $@ > $@-tmp
+	mv $@-tmp $@
+# Override system verilog files
+	target/xilinx/scripts/overrides.sh $@
+	echo "" >> $@

target/xilinx/flavor_bd/scripts/run_carfield_ip.tcl → target/xilinx/xilinx_ips/carfield_ip/tcl/run.tcl

@@ -7,14 +7,14 @@
 # Create project
 set project carfield_ip
 
-create_project $project ./$project -force -part $::env(XILINX_PART)
+create_project $project . -force -part $::env(XILINX_PART)
 set_property XPM_LIBRARIES XPM_MEMORY [current_project]
 
 # set number of threads to 8 (maximum, unfortunately)
 set_param general.maxThreads 8
 
 # Define sources
-source scripts/add_sources.tcl
+source tcl/add_sources.tcl
 
 # Add constraints
 add_files -fileset constrs_1 constraints/ooc_carfield_ip.xdc
@@ -24,9 +24,17 @@ add_files -fileset constrs_1 constraints/carfield_ip.xdc
 # Package IP
 set_property top carfield_xilinx_ip [current_fileset]
 
+# Attention SFCU is only used because of Carfield's structure
 update_compile_order -fileset sources_1
 synth_design -rtl -name rtl_1 -sfcu
 
-ipx::package_project -root_dir ./${project} -vendor ethz.ch -library user -taxonomy /UserIP -set_current true
+ipx::package_project -root_dir . -vendor ethz.ch -library user -taxonomy /UserIP -set_current false
+
+# If we don't reopen project, Vivado does not find the newly created ip_repo
+close_project
+open_project $project.xpr
+# Export this IP as a .xci too for coherence with Xilinx IPs
+set_property ip_repo_paths . [current_project]
+create_ip -verbose -module_name $project -vlnv ethz.ch:user:carfield_xilinx_ip
 
 exit