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tg/sim/index.html

@@ -748,7 +748,7 @@ <h1 id="simulation">Simulation</h1>
 <li>Questa Advanced Simulator (QuestaSim) <code>&gt;= 2022.3</code></li>
 </ul>
 <p>We plan on supporting more simulators in the future. If your situation requires it, simulating
-Cheshire on other setups should be straightforward.</p>
+Carfield on other setups should be straightforward.</p>
 <h2 id="testbench">Testbench</h2>
 <p>Carfield comprises several bootable domains, that are described in the
 <a href="../../um/arch/#domains">Architecture</a> section.</p>
@@ -761,13 +761,17 @@ <h2 id="testbench">Testbench</h2>
 <p>Note that while runtime offloading can be exploited by RTL simulation with reasonably-sized
 programs, we suggest to follow the <a href="../xilinx/">FPGA mapping</a> steps and use <a href="../../um/sw/">OpenMP-based
 offload</a> with heterogeneous cross-compilation.</p>
+<hr />
 <p>We provide a single SystemVerilog testbench for <code>carfield_soc</code> that handles standalone execution of
 baremetal programs for each domain. The code for domain <code>X</code> is preloaded through simulated interface
 drivers. In addition, some domains can read from external memory models from their boot ROM and then jump to
 execution.</p>
 <p>As for Cheshire, Carfield testbench employs physical interfaces (JTAG or Serial Link) for memory
 preload by default. This could increase the memory preload time (independently from the target
-memory: dynamic SPM, LLC-SPM, or DRAM), significantly based on the ELF size.</p>
+memory: dynamic SPM, LLC-SPM, or DRAM), significantly based on the ELF size. </p>
+<p>Since by default all domains are clock gated and isolated after POR except for the <em>host domain</em>
+(Cheshire), as described in <a href="../../um/arch/">Architecture</a>, the testbench handles the wake-up
+process.</p>
 <p>To speed up the process, the external DRAM can be initialized in simulation (namely, at time <code>0ns</code>)
 for domain <code>X</code> through the make variable <code>HYP_USER_PRELOAD</code>. Carfield <a href="../../um/sw/">SW Stack</a>
 provides automatic generation of the required <code>*.slm</code> files, targeting an HyperRAM configured with
@@ -832,11 +836,11 @@ <h3 id="autonomous-boot">Autonomous boot</h3>
 <h2 id="questasim">QuestaSim</h2>
 <p>After building Carfield, the design can be compiled and simulated with QuestaSim. Below, we provide
 an example with <code>Serial Link</code> passive preload of a baremetal program <code>helloworld.car.l2.elf</code> to be
-executed on the Cheshire domain (<code>X=CHS</code>):</p>
+executed on the <em>host domain</em> (Cheshire, i.e., <code>X=CHS</code>):</p>
 <pre><code class="language-tcl"># Compile design
 make car-hw-build
 
-# Preload `helloworld.spm.elf` through serial link, then start and run simulation
+# Preload `helloworld.car.l2.elf` through serial link, then start and run simulation
 make car-hw-sim CHS_BOOTMODE=0 CHS_PRELMODE=1 CHS_BINARY=./sw/tests/bare-metal/hostd/helloworld.car.l2.elf
 </code></pre>
 <p>The design needs to be recompiled only when hardware is changed.</p>

um/arch/index.html

@@ -560,15 +560,6 @@
     </span>
   </a>
 
-</li>
-
-        <li class="md-nav__item">
-  <a href="#clock-and-reset" class="md-nav__link">
-    <span class="md-ellipsis">
-      Clock and reset
-    </span>
-  </a>
-
 </li>
 
         <li class="md-nav__item">
@@ -707,6 +698,15 @@
       </ul>
     </nav>
 
+</li>
+
+        <li class="md-nav__item">
+  <a href="#clock-reset-and-isolation" class="md-nav__link">
+    <span class="md-ellipsis">
+      Clock, reset and isolation
+    </span>
+  </a>
+
 </li>
 
     </ul>
@@ -788,15 +788,6 @@
     </span>
   </a>
 
-</li>
-
-        <li class="md-nav__item">
-  <a href="#clock-and-reset" class="md-nav__link">
-    <span class="md-ellipsis">
-      Clock and reset
-    </span>
-  </a>
-
 </li>
 
         <li class="md-nav__item">
@@ -935,6 +926,15 @@
       </ul>
     </nav>
 
+</li>
+
+        <li class="md-nav__item">
+  <a href="#clock-reset-and-isolation" class="md-nav__link">
+    <span class="md-ellipsis">
+      Clock, reset and isolation
+    </span>
+  </a>
+
 </li>
 
     </ul>
@@ -2691,19 +2691,10 @@ <h2 id="interrupt-map">Interrupt map</h2>
 </tr>
 </tbody>
 </table>
-<h2 id="clock-and-reset">Clock and reset</h2>
-<p>Carfield is fed with 3 clocks:</p>
-<ul>
-<li><code>host_clk_i</code>:</li>
-<li><code>alt_clk_i</code>:</li>
-<li><code>per_clk_i</code>:</li>
-</ul>
-<p>TODO @angelo write about clock domains, AXI isolation, clock propagation (gate domains etc) and
-reset propagation</p>
 <h2 id="domains">Domains</h2>
 <p>Carfield's domains live in dedicated repositories. We invite the reader to consult the documentation
 of each domain for more information. Below, we briefly describe each domain and focus on integration
-parameterization. </p>
+parameterization.</p>
 <h3 id="host-domain-cheshire"><a href="https://github.com/pulp-platform/cheshire">Host domain (Cheshire)</a></h3>
 <p>The <em>host domain</em> (Cheshire) embeds all the necessary components required to run
 embedded OS such as embedded Linux. It can work in two orthogonal <em>operation modes</em>.</p>
@@ -2794,6 +2785,7 @@ <h3 id="secure-domain"><a href="https://github.com/pulp-platform/opentitan/tree/
 through cryptographic acceleration services.</p>
 <p>Compared to vanilla OpenTitan, the <em>secure domain</em> integrated in Carfield is modified/configured as follows:</p>
 <p>TODO</p>
+<p>TODO Mention <code>SECURE BOOT</code> mode</p>
 <h3 id="accelerator-domain">Accelerator domain</h3>
 <p>To augment computational capabilities, Carfield incorporates two general-purpose accelerators</p>
 <h4 id="hmr-integer-pmca"><a href="https://github.com/pulp-platform/pulp_cluster/tree/yt/rapidrecovery">HMR integer PMCA</a></h4>
@@ -3016,6 +3008,33 @@ <h3 id="ethernet">Ethernet</h3>
 <p>For more information, read the dedicated
 <a href="http://alexforencich.com/wiki/en/verilog/ethernet/start">documentation</a> of Ethernet components from
 its original repository.</p>
+<h2 id="clock-reset-and-isolation">Clock, reset and isolation</h2>
+<p>Currently, Carfield is provided with 3 clocks:</p>
+<ul>
+<li><code>host_clk_i</code>: clock of the <em>host domain</em></li>
+<li><code>alt_clk_i</code>: clock of <em>alternate</em> domains, namely <em>safe domain</em>, <em>secure domain</em>, <em>accelerator
+  domain</em></li>
+<li><code>per_clk_i</code>: clock of <em>peripheral domain</em></li>
+</ul>
+<p>Out of the 7 <em>domains</em> described above, 6 can be clock gated and isolated (<em>safe domain</em>, <em>secure
+domain</em>).</p>
+<p>Isolation means that, when a domain is isolated, data transfers through the bus targeting the domain
+are terminated and never reach it. An <em>isolation</em> module is placed in front of each domain.</p>
+<p>The only domain that is always-on and de-isolated is the <em>host domain</em> (Cheshire). If required,
+clock gating and/or isolation of it can be handled at higher levels of hierarchy, e.g. in a
+dedicated ASIC wrapper.</p>
+<p>Each of the 6 clock gateable domains have the following clock distribution scheme:</p>
+<ul>
+<li>For each domain the user selects one of the 3 different clock sources. Each of these main clocks
+  are either supplied externally, by a dedicated PLL per clock source or by a single PLL that
+  supplies all three clock sources. The configuration of the clock source is handled by the external
+  PLL wrapper configuration registers, e.g. in a ASIC top level.</li>
+<li>The selected clock source for the domain is fed into a default-bypassed arbitrary integer clock
+  divider with 50% duty cycle. This allows to use different integer clock divisions for every target
+  domain to use different clock frequencies.</li>
+<li>The internal clock gate of the clock divider is used to provide clock gating for the domain.</li>
+</ul>
+<p>Currently, Carfield is configured with all domains clock gated after power-on reset (POR) event.</p>