diff --git a/sitemap.xml.gz b/sitemap.xml.gz
index 137e864c..db5c0e3a 100644
Binary files a/sitemap.xml.gz and b/sitemap.xml.gz differ
diff --git a/tg/synth/index.html b/tg/synth/index.html
index 829a2daa..a84a6cfb 100644
--- a/tg/synth/index.html
+++ b/tg/synth/index.html
@@ -650,6 +650,19 @@ <h3 id="memory-requirements-for-physical-implementation">Memory requirements for
 <p>Given Carfield's complexity and heterogeneity, in the following we provide an overview of Carfield's
 on-chip memory requirements to help ASIC developers who wants to implement Carfield or integrate it
 into larger platforms.</p>
+<p>Carfield makes large use of scratchpad memories (SPM), implemented as SRAMs and explicitely managed
+in SW. To help the reader, we consider an SPM as described by the following parameters:</p>
+<ul>
+<li><code>NumWords</code>: The number of words. Assuming the SPM as a matrix, it corresponds to the number of
+  rows. Assuming the <em>domain</em>'s memory system has address width <code>AddrWidth</code>, then <code>NumWords =
+  2**(AddrWidth)</code>, i.e. <code>2**AddrWidth</code> data words can be addressed.</li>
+<li><code>DataWidth</code>: The data width of a <em>word</em> in the <em>domain</em>'s memory system. Typically, it is 32-bit
+  or 64-bit. If ECC is implemented, it is larger to account for the extra bits.</li>
+<li><code>NumBanks</code>: number of banks of size <code>(NumWords*DataWidth)/8</code> B.</li>
+</ul>
+<p>The total size is computed as</p>
+<pre><code>Total size [B] = (NumWords * DataWidth [bit] * NumBanks)/8 [B]
+</code></pre>
 <p>TODO</p>
 
 
diff --git a/um/arch/index.html b/um/arch/index.html
index 5ef49952..35213fc1 100644
--- a/um/arch/index.html
+++ b/um/arch/index.html
@@ -1211,8 +1211,8 @@ <h1 id="architecture">Architecture</h1>
 </li>
 </ul>
 <h2 id="memory-map">Memory Map</h2>
-<p>This section shows Carfield's memory map. The group <code>Internal to Cheshire</code> in the table below
-mirrors the memory map described in the dedicatd <a href="https://pulp-platform.github.io/cheshire/um/arch/">documentation for
+<p>This section shows Carfield's memory map. The group <code>Internal to Cheshire</code> in the table below only
+recalls the memory map described in the dedicatd <a href="https://pulp-platform.github.io/cheshire/um/arch/">documentation for
 Cheshire</a> and is explicitely shown here for
 clarity.</p>
 <table>
@@ -1222,6 +1222,9 @@ <h2 id="memory-map">Memory Map</h2>
 <th><strong>End Address (excl.)</strong></th>
 <th><strong>Length</strong></th>
 <th><strong>Size</strong></th>
+<th><strong>Permissions</strong></th>
+<th><strong>Cacheable</strong></th>
+<th><strong>Atomics</strong></th>
 <th><strong>Region</strong></th>
 <th><strong>Device</strong></th>
 </tr>
@@ -1234,12 +1237,18 @@ <h2 id="memory-map">Memory Map</h2>
 <td></td>
 <td></td>
 <td></td>
+<td></td>
+<td></td>
+<td></td>
 </tr>
 <tr>
 <td><code>0x0000_0000</code></td>
 <td><code>0x0004_0000</code></td>
 <td><code>0x04_0000</code></td>
 <td>256 KiB</td>
+<td>(debug)</td>
+<td></td>
+<td></td>
 <td>Debug</td>
 <td>Debug CVA6</td>
 </tr>
@@ -1248,6 +1257,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x0100_0000</code></td>
 <td></td>
 <td></td>
+<td></td>
+<td></td>
+<td></td>
 <td><em>Reserved</em></td>
 <td></td>
 </tr>
@@ -1256,6 +1268,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x0100_1000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Config</td>
 <td>AXI DMA Config</td>
 </tr>
@@ -1264,6 +1279,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x0200_0000</code></td>
 <td></td>
 <td></td>
+<td></td>
+<td></td>
+<td></td>
 <td><em>Reserved</em></td>
 <td></td>
 </tr>
@@ -1272,6 +1290,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x0204_0000</code></td>
 <td><code>0x04_0000</code></td>
 <td>256 KiB</td>
+<td>rx</td>
+<td></td>
+<td></td>
 <td>Memory</td>
 <td>Boot ROM</td>
 </tr>
@@ -1280,6 +1301,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x0208_0000</code></td>
 <td><code>0x04_0000</code></td>
 <td>256 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Irq</td>
 <td>CLINT</td>
 </tr>
@@ -1288,6 +1312,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x020c_0000</code></td>
 <td><code>0x04_0000</code></td>
 <td>256 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Irq</td>
 <td>IRQ Routing</td>
 </tr>
@@ -1296,6 +1323,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x0210_0000</code></td>
 <td><code>0x04_0000</code></td>
 <td>256 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Irq</td>
 <td>AXI-REALM unit</td>
 </tr>
@@ -1304,6 +1334,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x0300_0000</code></td>
 <td></td>
 <td></td>
+<td></td>
+<td></td>
+<td></td>
 <td><em>Reserved</em></td>
 <td></td>
 </tr>
@@ -1312,14 +1345,20 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x0300_1000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Config</td>
-<td>CSRs</td>
+<td>Cheshire PCRs</td>
 </tr>
 <tr>
 <td><code>0x0300_1000</code></td>
 <td><code>0x0300_2000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Config</td>
 <td>LLC</td>
 </tr>
@@ -1328,38 +1367,53 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x0300_3000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
-<td>UART</td>
+<td><a href="https://opentitan.org/book/hw/ip/uart/doc/registers.html">UART</a></td>
 </tr>
 <tr>
 <td><code>0x0300_3000</code></td>
 <td><code>0x0300_4000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
-<td>I2C</td>
+<td><a href="https://opentitan.org/book/hw/ip/i2c/doc/registers.html">I2C</a></td>
 </tr>
 <tr>
 <td><code>0x0300_4000</code></td>
 <td><code>0x0300_5000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
-<td>SPIM</td>
+<td><a href="https://opentitan.org/book/hw/ip/spi_host/doc/registers.html">SPIM</a></td>
 </tr>
 <tr>
 <td><code>0x0300_5000</code></td>
 <td><code>0x0300_6000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
-<td>GPIO</td>
+<td><a href="https://opentitan.org/book/hw/ip/gpio/doc/registers.html">GPIO</a></td>
 </tr>
 <tr>
 <td><code>0x0300_6000</code></td>
 <td><code>0x0300_7000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Config</td>
 <td>Serial Link</td>
 </tr>
@@ -1368,6 +1422,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x0300_8000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Config</td>
 <td>VGA</td>
 </tr>
@@ -1376,6 +1433,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x0300_A000</code></td>
 <td><code>0x00_1000</code></td>
 <td>8 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Config</td>
 <td>UNBENT (bus error unit)</td>
 </tr>
@@ -1384,14 +1444,20 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x0300_B000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Config</td>
-<td>Tagger (cache partitioning)</td>
+<td>Tagger (LLC partitioning)</td>
 </tr>
 <tr>
 <td><code>0x0300_8000</code></td>
 <td><code>0x0400_0000</code></td>
 <td></td>
 <td></td>
+<td></td>
+<td></td>
+<td></td>
 <td><em>Reserved</em></td>
 <td></td>
 </tr>
@@ -1400,6 +1466,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x1000_0000</code></td>
 <td><code>0x40_0000</code></td>
 <td>64 MiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Irq</td>
 <td>PLIC</td>
 </tr>
@@ -1408,6 +1477,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x0C00_0000</code></td>
 <td><code>0x40_0000</code></td>
 <td>64 MiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Irq</td>
 <td>CLICs</td>
 </tr>
@@ -1416,6 +1488,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x1400_0000</code></td>
 <td><code>0x40_0000</code></td>
 <td>64 MiB</td>
+<td>rwx</td>
+<td>yes</td>
+<td>yes</td>
 <td>Memory</td>
 <td>LLC Scratchpad</td>
 </tr>
@@ -1424,6 +1499,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x1800_0000</code></td>
 <td><code>0x40_0000</code></td>
 <td>64 MiB</td>
+<td>rwx</td>
+<td></td>
+<td>yes</td>
 <td>Memory</td>
 <td>LLC Scratchpad</td>
 </tr>
@@ -1432,6 +1510,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x2000_0000</code></td>
 <td></td>
 <td></td>
+<td></td>
+<td></td>
+<td></td>
 <td><em>Reserved</em></td>
 <td></td>
 </tr>
@@ -1440,6 +1521,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td></td>
 <td></td>
 <td></td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td></td>
 <td></td>
 </tr>
@@ -1448,14 +1532,20 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x2000_1000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
-<td>ETHERNET</td>
+<td>Ethernet</td>
 </tr>
 <tr>
 <td><code>0x2000_1000</code></td>
 <td><code>0x2000_2000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
 <td>CAN BUS</td>
 </tr>
@@ -1464,6 +1554,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x2000_3000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
 <td>(empty)</td>
 </tr>
@@ -1472,6 +1565,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x2000_4000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
 <td>(empty)</td>
 </tr>
@@ -1480,38 +1576,53 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x2000_5000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
-<td>GP TIMER 1 (System timer)</td>
+<td>GP timer 1 (System timer)</td>
 </tr>
 <tr>
 <td><code>0x2000_5000</code></td>
 <td><code>0x2000_6000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
-<td>GP TIMER 2 (Advanced timer)</td>
+<td>GP timer 2 (Advanced timer)</td>
 </tr>
 <tr>
 <td><code>0x2000_6000</code></td>
 <td><code>0x2000_7000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
-<td>GP TIMER 3</td>
+<td>GP timer 3</td>
 </tr>
 <tr>
 <td><code>0x2000_7000</code></td>
 <td><code>0x2000_8000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
-<td>WATCHDOG timer</td>
+<td>Watchdog timer</td>
 </tr>
 <tr>
 <td><code>0x2000_8000</code></td>
 <td><code>0x2000_9000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
 <td>(empty)</td>
 </tr>
@@ -1520,6 +1631,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x2000_a000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
 <td>HyperBUS</td>
 </tr>
@@ -1528,6 +1642,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x2000_b000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
 <td>Pad Config</td>
 </tr>
@@ -1536,6 +1653,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x2000_c000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
 <td>L2 ECC Config</td>
 </tr>
@@ -1544,6 +1664,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x2001_1000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
 <td>Carfield Control and Status</td>
 </tr>
@@ -1552,14 +1675,20 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x2002_1000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>I/O</td>
-<td>PLL/CLOCK</td>
+<td>(if any) PLL/CLOCK</td>
 </tr>
 <tr>
 <td><code>0x2800_1000</code></td>
 <td><code>0x4000_0000</code></td>
 <td></td>
 <td></td>
+<td></td>
+<td></td>
+<td></td>
 <td><em>Reserved</em></td>
 <td></td>
 </tr>
@@ -1568,6 +1697,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x4000_1000</code></td>
 <td><code>0x00_1000</code></td>
 <td>4 KiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Irq</td>
 <td>Mailboxes</td>
 </tr>
@@ -1576,6 +1708,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x5000_0000</code></td>
 <td></td>
 <td></td>
+<td></td>
+<td></td>
+<td></td>
 <td><em>Reserved</em></td>
 <td></td>
 </tr>
@@ -1584,6 +1719,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x5080_0000</code></td>
 <td><code>0x80_0000</code></td>
 <td>8 MiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Accelerators</td>
 <td>Integer Cluster</td>
 </tr>
@@ -1592,6 +1730,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x5100_0000</code></td>
 <td></td>
 <td></td>
+<td></td>
+<td></td>
+<td></td>
 <td><em>Reserved</em></td>
 <td></td>
 </tr>
@@ -1600,6 +1741,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x5180_0000</code></td>
 <td><code>0x80_0000</code></td>
 <td>8 MiB</td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Accelerators</td>
 <td>FP Cluster</td>
 </tr>
@@ -1608,6 +1752,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x6000_0000</code></td>
 <td></td>
 <td></td>
+<td></td>
+<td></td>
+<td></td>
 <td><em>Reserved</em></td>
 <td></td>
 </tr>
@@ -1616,6 +1763,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x6002_0000</code></td>
 <td><code>0x02_0000</code></td>
 <td>128 KiB</td>
+<td>rw</td>
+<td></td>
+<td>yes</td>
 <td>Safe domain</td>
 <td>Safety Island Memory</td>
 </tr>
@@ -1624,6 +1774,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x6020_0000</code></td>
 <td><code>0x1e_0000</code></td>
 <td></td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Safe domain</td>
 <td>reserved</td>
 </tr>
@@ -1631,7 +1784,10 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x6020_0000</code></td>
 <td><code>0x6030_0000</code></td>
 <td><code>0x10_0000</code></td>
+<td>1 MiB</td>
+<td>rw</td>
 <td></td>
+<td>yes</td>
 <td>Safe domain</td>
 <td>Safety Island Peripherals</td>
 </tr>
@@ -1640,6 +1796,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x6080_0000</code></td>
 <td><code>0x50_0000</code></td>
 <td></td>
+<td>rw</td>
+<td></td>
+<td></td>
 <td>Safe domain</td>
 <td>reserved</td>
 </tr>
@@ -1648,6 +1807,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x7000_0000</code></td>
 <td></td>
 <td></td>
+<td></td>
+<td></td>
+<td></td>
 <td><em>Reserved</em></td>
 <td></td>
 </tr>
@@ -1656,6 +1818,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x7002_0000</code></td>
 <td><code>0x02_0000</code></td>
 <td>128 KiB</td>
+<td>rwx</td>
+<td>yes</td>
+<td>yes</td>
 <td>Memory</td>
 <td>LLC Scratchpad</td>
 </tr>
@@ -1664,6 +1829,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x7810_0000</code></td>
 <td><code>0x10_0000</code></td>
 <td>1 MiB</td>
+<td>rwx</td>
+<td>yes</td>
+<td>yes</td>
 <td>Memory</td>
 <td>L2 Scratchpad (Port 1, interleaved)</td>
 </tr>
@@ -1672,6 +1840,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x7820_0000</code></td>
 <td><code>0x10_0000</code></td>
 <td>1 MiB</td>
+<td>rwx</td>
+<td>yes</td>
+<td>yes</td>
 <td>Memory</td>
 <td>L2 Scratchpad (Port 1, non-interleaved)</td>
 </tr>
@@ -1680,6 +1851,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x7830_0000</code></td>
 <td><code>0x10_0000</code></td>
 <td>1 MiB</td>
+<td>rwx</td>
+<td>yes</td>
+<td>yes</td>
 <td>Memory</td>
 <td>L2 Scratchpad (Port 2, interleaved)</td>
 </tr>
@@ -1688,6 +1862,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x7840_0000</code></td>
 <td><code>0x10_0000</code></td>
 <td>1 MiB</td>
+<td>rwx</td>
+<td>yes</td>
+<td>yes</td>
 <td>Memory</td>
 <td>L2 Scratchpad (Port 2, non-interleaved)</td>
 </tr>
@@ -1696,6 +1873,9 @@ <h2 id="memory-map">Memory Map</h2>
 <td><code>0x20_8000_0000</code></td>
 <td><code>0x20_0000_0000</code></td>
 <td>128 GiB</td>
+<td>rwx</td>
+<td>yes</td>
+<td>yes</td>
 <td>Memory</td>
 <td>LLC/DRAM</td>
 </tr>

End Address (excl.)	Length	Size	Permissions	Cacheable	Atomics	Region	Device

`0x0000_0000`	`0x0004_0000`	`0x04_0000`	256 KiB	(debug)			Debug	Debug CVA6
`0x0100_0000`						Reserved
`0x0100_1000`	`0x00_1000`	4 KiB	rw			Config	AXI DMA Config
`0x0200_0000`						Reserved
`0x0204_0000`	`0x04_0000`	256 KiB	rx			Memory	Boot ROM
`0x0208_0000`	`0x04_0000`	256 KiB	rw			Irq	CLINT
`0x020c_0000`	`0x04_0000`	256 KiB	rw			Irq	IRQ Routing
`0x0210_0000`	`0x04_0000`	256 KiB	rw			Irq	AXI-REALM unit
`0x0300_0000`						Reserved
`0x0300_1000`	`0x00_1000`	4 KiB	rw			Config	CSRs	Cheshire PCRs
`0x0300_1000`	`0x0300_2000`	`0x00_1000`	4 KiB	rw			Config	LLC
`0x0300_3000`	`0x00_1000`	4 KiB	rw			I/O	UART	UART
`0x0300_3000`	`0x0300_4000`	`0x00_1000`	4 KiB	rw			I/O	I2C	I2C
`0x0300_4000`	`0x0300_5000`	`0x00_1000`	4 KiB	rw			I/O	SPIM	SPIM
`0x0300_5000`	`0x0300_6000`	`0x00_1000`	4 KiB	rw			I/O	GPIO	GPIO
`0x0300_6000`	`0x0300_7000`	`0x00_1000`	4 KiB	rw			Config	Serial Link
`0x0300_8000`	`0x00_1000`	4 KiB	rw			Config	VGA
`0x0300_A000`	`0x00_1000`	8 KiB	rw			Config	UNBENT (bus error unit)
`0x0300_B000`	`0x00_1000`	4 KiB	rw			Config	Tagger (cache partitioning)	Tagger (LLC partitioning)
`0x0300_8000`	`0x0400_0000`						Reserved
`0x1000_0000`	`0x40_0000`	64 MiB	rw			Irq	PLIC
`0x0C00_0000`	`0x40_0000`	64 MiB	rw			Irq	CLICs
`0x1400_0000`	`0x40_0000`	64 MiB	rwx	yes	yes	Memory	LLC Scratchpad
`0x1800_0000`	`0x40_0000`	64 MiB	rwx		yes	Memory	LLC Scratchpad
`0x2000_0000`						Reserved
			rw
`0x2000_1000`	`0x00_1000`	4 KiB	rw			I/O	ETHERNET	Ethernet
`0x2000_1000`	`0x2000_2000`	`0x00_1000`	4 KiB	rw			I/O	CAN BUS
`0x2000_3000`	`0x00_1000`	4 KiB	rw			I/O	(empty)
`0x2000_4000`	`0x00_1000`	4 KiB	rw			I/O	(empty)
`0x2000_5000`	`0x00_1000`	4 KiB	rw			I/O	GP TIMER 1 (System timer)	GP timer 1 (System timer)
`0x2000_5000`	`0x2000_6000`	`0x00_1000`	4 KiB	rw			I/O	GP TIMER 2 (Advanced timer)	GP timer 2 (Advanced timer)
`0x2000_6000`	`0x2000_7000`	`0x00_1000`	4 KiB	rw			I/O	GP TIMER 3	GP timer 3
`0x2000_7000`	`0x2000_8000`	`0x00_1000`	4 KiB	rw			I/O	WATCHDOG timer	Watchdog timer
`0x2000_8000`	`0x2000_9000`	`0x00_1000`	4 KiB	rw			I/O	(empty)
`0x2000_a000`	`0x00_1000`	4 KiB	rw			I/O	HyperBUS
`0x2000_b000`	`0x00_1000`	4 KiB	rw			I/O	Pad Config
`0x2000_c000`	`0x00_1000`	4 KiB	rw			I/O	L2 ECC Config
`0x2001_1000`	`0x00_1000`	4 KiB	rw			I/O	Carfield Control and Status
`0x2002_1000`	`0x00_1000`	4 KiB	rw			I/O	PLL/CLOCK	(if any) PLL/CLOCK
`0x2800_1000`	`0x4000_0000`						Reserved
`0x4000_1000`	`0x00_1000`	4 KiB	rw			Irq	Mailboxes
`0x5000_0000`						Reserved
`0x5080_0000`	`0x80_0000`	8 MiB	rw			Accelerators	Integer Cluster
`0x5100_0000`						Reserved
`0x5180_0000`	`0x80_0000`	8 MiB	rw			Accelerators	FP Cluster
`0x6000_0000`						Reserved
`0x6002_0000`	`0x02_0000`	128 KiB	rw		yes	Safe domain	Safety Island Memory
`0x6020_0000`	`0x1e_0000`		rw			Safe domain	reserved
`0x6020_0000`	`0x6030_0000`	`0x10_0000`	1 MiB	rw		yes	Safe domain	Safety Island Peripherals
`0x6080_0000`	`0x50_0000`		rw			Safe domain	reserved
`0x7000_0000`						Reserved
`0x7002_0000`	`0x02_0000`	128 KiB	rwx	yes	yes	Memory	LLC Scratchpad
`0x7810_0000`	`0x10_0000`	1 MiB	rwx	yes	yes	Memory	L2 Scratchpad (Port 1, interleaved)
`0x7820_0000`	`0x10_0000`	1 MiB	rwx	yes	yes	Memory	L2 Scratchpad (Port 1, non-interleaved)
`0x7830_0000`	`0x10_0000`	1 MiB	rwx	yes	yes	Memory	L2 Scratchpad (Port 2, interleaved)
`0x7840_0000`	`0x10_0000`	1 MiB	rwx	yes	yes	Memory	L2 Scratchpad (Port 2, non-interleaved)
`0x20_8000_0000`	`0x20_0000_0000`	128 GiB	rwx	yes	yes	Memory	LLC/DRAM