From 9db33de014cae59b09dabb4d207786b0cdb52eb7 Mon Sep 17 00:00:00 2001
From: aottaviano Memory Map
mirrors the memory map described in the dedicatd documentation for
Cheshire and is explicitely shown here for
clarity.
| Start Address | End Address (excl.) | Length | Size | Region | Device |
-| Internal to Cheshire | | | | | |
-| 0x0000_0000
| 0x0004_0000
| 0x04_0000
| 256 KiB | Debug | Debug CVA6 |
-| 0x0004_0000
| 0x0100_0000
| | | Reserved | |
-| 0x0100_0000
| 0x0100_1000
| 0x00_1000
| 4 KiB | Config | AXI DMA Config |
-| 0x0100_1000
| 0x0200_0000
| | | Reserved | |
-| 0x0200_0000
| 0x0204_0000
| 0x04_0000
| 256 KiB | Memory | Boot ROM |
-| 0x0204_0000
| 0x0208_0000
| 0x04_0000
| 256 KiB | Irq | CLINT |
-| 0x0208_0000
| 0x020c_0000
| 0x04_0000
| 256 KiB | Irq | IRQ Routing |
-| 0x020c_0000
| 0x0210_0000
| 0x04_0000
| 256 KiB | Irq | AXI-REALM unit |
-| 0x020c_0000
| 0x0300_0000
| | | Reserved | |
-| 0x0300_0000
| 0x0300_1000
| 0x00_1000
| 4 KiB | Config | CSRs |
-| 0x0300_1000
| 0x0300_2000
| 0x00_1000
| 4 KiB | Config | LLC |
-| 0x0300_2000
| 0x0300_3000
| 0x00_1000
| 4 KiB | I/O | UART |
-| 0x0300_3000
| 0x0300_4000
| 0x00_1000
| 4 KiB | I/O | I2C |
-| 0x0300_4000
| 0x0300_5000
| 0x00_1000
| 4 KiB | I/O | SPIM |
-| 0x0300_5000
| 0x0300_6000
| 0x00_1000
| 4 KiB | I/O | GPIO |
-| 0x0300_6000
| 0x0300_7000
| 0x00_1000
| 4 KiB | Config | Serial Link |
-| 0x0300_7000
| 0x0300_8000
| 0x00_1000
| 4 KiB | Config | VGA |
-| 0x0300_8000
| 0x0300_A000
| 0x00_1000
| 8 KiB | Config | UNBENT (bus error unit) |
-| 0x0300_A000
| 0x0300_B000
| 0x00_1000
| 4 KiB | Config | Tagger (cache partitioning) |
-| 0x0300_8000
| 0x0400_0000
| | | Reserved | |
-| 0x0400_0000
| 0x1000_0000
| 0x40_0000
| 64 MiB | Irq | PLIC |
-| 0x0800_0000
| 0x0C00_0000
| 0x40_0000
| 64 MiB | Irq | CLICs |
-| 0x1000_0000
| 0x1400_0000
| 0x40_0000
| 64 MiB | Memory | LLC Scratchpad |
-| 0x1400_0000
| 0x1800_0000
| 0x40_0000
| 64 MiB | Memory | LLC Scratchpad |
-| 0x1800_0000
| 0x2000_0000
| | | Reserved | |
-| External to Cheshire | | | | | |
-| 0x2000_0000
| 0x2000_1000
| 0x00_1000
| 4 KiB | I/O | ETHERNET |
-| 0x2000_1000
| 0x2000_2000
| 0x00_1000
| 4 KiB | I/O | CAN BUS |
-| 0x2000_2000
| 0x2000_3000
| 0x00_1000
| 4 KiB | I/O | (empty) |
-| 0x2000_3000
| 0x2000_4000
| 0x00_1000
| 4 KiB | I/O | (empty) |
-| 0x2000_4000
| 0x2000_5000
| 0x00_1000
| 4 KiB | I/O | GP TIMER 1 (System timer) |
-| 0x2000_5000
| 0x2000_6000
| 0x00_1000
| 4 KiB | I/O | GP TIMER 2 (Advanced timer) |
-| 0x2000_6000
| 0x2000_7000
| 0x00_1000
| 4 KiB | I/O | GP TIMER 3 |
-| 0x2000_7000
| 0x2000_8000
| 0x00_1000
| 4 KiB | I/O | WATCHDOG timer |
-| 0x2000_8000
| 0x2000_9000
| 0x00_1000
| 4 KiB | I/O | (empty) |
-| 0x2000_9000
| 0x2000_a000
| 0x00_1000
| 4 KiB | I/O | HyperBUS |
-| 0x2000_a000
| 0x2000_b000
| 0x00_1000
| 4 KiB | I/O | Pad Config |
-| 0x2000_b000
| 0x2000_c000
| 0x00_1000
| 4 KiB | I/O | L2 ECC Config |
-| 0x2001_0000
| 0x2001_1000
| 0x00_1000
| 4 KiB | I/O | Carfield Control and Status |
-| 0x2002_0000
| 0x2002_1000
| 0x00_1000
| 4 KiB | I/O | PLL/CLOCK |
-| 0x2800_1000
| 0x4000_0000
| | | Reserved | |
-| 0x4000_0000
| 0x4000_1000
| 0x00_1000
| 4 KiB | Irq | Mailboxes |
-| 0x4000_1000
| 0x5000_0000
| | | Reserved | |
-| 0x5000_0000
| 0x5080_0000
| 0x80_0000
| 8 MiB | Accelerators | Integer Cluster |
-| 0x5080_0000
| 0x5100_0000
| | | Reserved | |
-| 0x5100_0000
| 0x5180_0000
| 0x80_0000
| 8 MiB | Accelerators | FP Cluster |
-| 0x5100_0000
| 0x6000_0000
| | | Reserved | |
-| 0x6000_0000
| 0x6002_0000
| 0x02_0000
| 128 KiB | Safe domain | Safety Island Memory |
-| 0x6002_0000
| 0x6020_0000
| 0x1e_0000
| | Safe domain | reserved |
-| 0x6020_0000
| 0x6030_0000
| 0x10_0000
| | Safe domain | Safety Island Peripherals |
-| 0x6030_0000
| 0x6080_0000
| 0x50_0000
| | Safe domain | reserved |
-| 0x6080_0000
| 0x7000_0000
| | | Reserved | |
-| 0x7000_0000
| 0x7002_0000
| 0x02_0000
| 128 KiB | Memory | LLC Scratchpad |
-| 0x7800_0000
| 0x7810_0000
| 0x10_0000
| 1 MiB | Memory | L2 Scratchpad (Port 1, interleaved) |
-| 0x7810_0000
| 0x7820_0000
| 0x10_0000
| 1 MiB | Memory | L2 Scratchpad (Port 1, non-interleaved) |
-| 0x7820_0000
| 0x7830_0000
| 0x10_0000
| 1 MiB | Memory | L2 Scratchpad (Port 2, interleaved) |
-| 0x7830_0000
| 0x7840_0000
| 0x10_0000
| 1 MiB | Memory | L2 Scratchpad (Port 2, non-interleaved) |
-| 0x8000_0000
| 0x20_8000_0000
| 0x20_0000_0000
| 128 GiB | Memory | LLC/DRAM |
Start Address | +End Address (excl.) | +Length | +Size | +Region | +Device | +
---|---|---|---|---|---|
Internal to Cheshire | ++ | + | + | + | + |
0x0000_0000 |
+0x0004_0000 |
+0x04_0000 |
+256 KiB | +Debug | +Debug CVA6 | +
0x0004_0000 |
+0x0100_0000 |
++ | + | Reserved | ++ |
0x0100_0000 |
+0x0100_1000 |
+0x00_1000 |
+4 KiB | +Config | +AXI DMA Config | +
0x0100_1000 |
+0x0200_0000 |
++ | + | Reserved | ++ |
0x0200_0000 |
+0x0204_0000 |
+0x04_0000 |
+256 KiB | +Memory | +Boot ROM | +
0x0204_0000 |
+0x0208_0000 |
+0x04_0000 |
+256 KiB | +Irq | +CLINT | +
0x0208_0000 |
+0x020c_0000 |
+0x04_0000 |
+256 KiB | +Irq | +IRQ Routing | +
0x020c_0000 |
+0x0210_0000 |
+0x04_0000 |
+256 KiB | +Irq | +AXI-REALM unit | +
0x020c_0000 |
+0x0300_0000 |
++ | + | Reserved | ++ |
0x0300_0000 |
+0x0300_1000 |
+0x00_1000 |
+4 KiB | +Config | +CSRs | +
0x0300_1000 |
+0x0300_2000 |
+0x00_1000 |
+4 KiB | +Config | +LLC | +
0x0300_2000 |
+0x0300_3000 |
+0x00_1000 |
+4 KiB | +I/O | +UART | +
0x0300_3000 |
+0x0300_4000 |
+0x00_1000 |
+4 KiB | +I/O | +I2C | +
0x0300_4000 |
+0x0300_5000 |
+0x00_1000 |
+4 KiB | +I/O | +SPIM | +
0x0300_5000 |
+0x0300_6000 |
+0x00_1000 |
+4 KiB | +I/O | +GPIO | +
0x0300_6000 |
+0x0300_7000 |
+0x00_1000 |
+4 KiB | +Config | +Serial Link | +
0x0300_7000 |
+0x0300_8000 |
+0x00_1000 |
+4 KiB | +Config | +VGA | +
0x0300_8000 |
+0x0300_A000 |
+0x00_1000 |
+8 KiB | +Config | +UNBENT (bus error unit) | +
0x0300_A000 |
+0x0300_B000 |
+0x00_1000 |
+4 KiB | +Config | +Tagger (cache partitioning) | +
0x0300_8000 |
+0x0400_0000 |
++ | + | Reserved | ++ |
0x0400_0000 |
+0x1000_0000 |
+0x40_0000 |
+64 MiB | +Irq | +PLIC | +
0x0800_0000 |
+0x0C00_0000 |
+0x40_0000 |
+64 MiB | +Irq | +CLICs | +
0x1000_0000 |
+0x1400_0000 |
+0x40_0000 |
+64 MiB | +Memory | +LLC Scratchpad | +
0x1400_0000 |
+0x1800_0000 |
+0x40_0000 |
+64 MiB | +Memory | +LLC Scratchpad | +
0x1800_0000 |
+0x2000_0000 |
++ | + | Reserved | ++ |
-------------------------- | +------------------------- | +------------------ | +---------- | +-------------- | +----------------------------------------- | +
External to Cheshire | ++ | + | + | + | + |
0x2000_0000 |
+0x2000_1000 |
+0x00_1000 |
+4 KiB | +I/O | +ETHERNET | +
0x2000_1000 |
+0x2000_2000 |
+0x00_1000 |
+4 KiB | +I/O | +CAN BUS | +
0x2000_2000 |
+0x2000_3000 |
+0x00_1000 |
+4 KiB | +I/O | +(empty) | +
0x2000_3000 |
+0x2000_4000 |
+0x00_1000 |
+4 KiB | +I/O | +(empty) | +
0x2000_4000 |
+0x2000_5000 |
+0x00_1000 |
+4 KiB | +I/O | +GP TIMER 1 (System timer) | +
0x2000_5000 |
+0x2000_6000 |
+0x00_1000 |
+4 KiB | +I/O | +GP TIMER 2 (Advanced timer) | +
0x2000_6000 |
+0x2000_7000 |
+0x00_1000 |
+4 KiB | +I/O | +GP TIMER 3 | +
0x2000_7000 |
+0x2000_8000 |
+0x00_1000 |
+4 KiB | +I/O | +WATCHDOG timer | +
0x2000_8000 |
+0x2000_9000 |
+0x00_1000 |
+4 KiB | +I/O | +(empty) | +
0x2000_9000 |
+0x2000_a000 |
+0x00_1000 |
+4 KiB | +I/O | +HyperBUS | +
0x2000_a000 |
+0x2000_b000 |
+0x00_1000 |
+4 KiB | +I/O | +Pad Config | +
0x2000_b000 |
+0x2000_c000 |
+0x00_1000 |
+4 KiB | +I/O | +L2 ECC Config | +
0x2001_0000 |
+0x2001_1000 |
+0x00_1000 |
+4 KiB | +I/O | +Carfield Control and Status | +
0x2002_0000 |
+0x2002_1000 |
+0x00_1000 |
+4 KiB | +I/O | +PLL/CLOCK | +
0x2800_1000 |
+0x4000_0000 |
++ | + | Reserved | ++ |
0x4000_0000 |
+0x4000_1000 |
+0x00_1000 |
+4 KiB | +Irq | +Mailboxes | +
0x4000_1000 |
+0x5000_0000 |
++ | + | Reserved | ++ |
0x5000_0000 |
+0x5080_0000 |
+0x80_0000 |
+8 MiB | +Accelerators | +Integer Cluster | +
0x5080_0000 |
+0x5100_0000 |
++ | + | Reserved | ++ |
0x5100_0000 |
+0x5180_0000 |
+0x80_0000 |
+8 MiB | +Accelerators | +FP Cluster | +
0x5100_0000 |
+0x6000_0000 |
++ | + | Reserved | ++ |
0x6000_0000 |
+0x6002_0000 |
+0x02_0000 |
+128 KiB | +Safe domain | +Safety Island Memory | +
0x6002_0000 |
+0x6020_0000 |
+0x1e_0000 |
++ | Safe domain | +reserved | +
0x6020_0000 |
+0x6030_0000 |
+0x10_0000 |
++ | Safe domain | +Safety Island Peripherals | +
0x6030_0000 |
+0x6080_0000 |
+0x50_0000 |
++ | Safe domain | +reserved | +
0x6080_0000 |
+0x7000_0000 |
++ | + | Reserved | ++ |
0x7000_0000 |
+0x7002_0000 |
+0x02_0000 |
+128 KiB | +Memory | +LLC Scratchpad | +
0x7800_0000 |
+0x7810_0000 |
+0x10_0000 |
+1 MiB | +Memory | +L2 Scratchpad (Port 1, interleaved) | +
0x7810_0000 |
+0x7820_0000 |
+0x10_0000 |
+1 MiB | +Memory | +L2 Scratchpad (Port 1, non-interleaved) | +
0x7820_0000 |
+0x7830_0000 |
+0x10_0000 |
+1 MiB | +Memory | +L2 Scratchpad (Port 2, interleaved) | +
0x7830_0000 |
+0x7840_0000 |
+0x10_0000 |
+1 MiB | +Memory | +L2 Scratchpad (Port 2, non-interleaved) | +
0x8000_0000 |
+0x20_8000_0000 |
+0x20_0000_0000 |
+128 GiB | +Memory | +LLC/DRAM | +
Carfield's interrupt components are exhaustivly described in the dedicated section of the documentation for