diff --git a/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl
index b9c2db50..6159e3aa 100644
--- a/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl
+++ b/target/xilinx/flavor_bd/scripts/carfield_bd_vcu128.tcl
@@ -131,7 +131,6 @@ xilinx.com:ip:clk_wiz:6.0\
 xilinx.com:ip:xlconcat:2.1\
 xilinx.com:ip:ddr4:2.2\
 xilinx.com:ip:xlconstant:1.1\
-xilinx.com:ip:ila:6.2\
 xilinx.com:ip:proc_sys_reset:5.0\
 xilinx.com:ip:util_ds_buf:2.1\
 xilinx.com:ip:vio:3.0\
@@ -327,12 +326,6 @@ proc create_root_design { parentCell } {
   # Create instance: high, and set properties
   set high [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 high ]
 
-  # Create instance: ila_0, and set properties
-  set ila_0 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.2 ila_0 ]
-
-  # Create instance: ila_1, and set properties
-  set ila_1 [ create_bd_cell -type ip -vlnv xilinx.com:ip:ila:6.2 ila_1 ]
-
   # Create instance: low, and set properties
   set low [ create_bd_cell -type ip -vlnv xilinx.com:ip:xlconstant:1.1 low ]
   set_property -dict [ list \
@@ -455,10 +448,8 @@ proc create_root_design { parentCell } {
   connect_bd_intf_net -intf_net xbar_periph_out_M01_AXI [get_bd_intf_pins axi_dma_0/S_AXI_LITE] [get_bd_intf_pins xbar_periph_out/M01_AXI]
   connect_bd_intf_net -intf_net xbar_periph_out_M02_AXI [get_bd_intf_pins ddr4_0/C0_DDR4_S_AXI_CTRL] [get_bd_intf_pins xbar_periph_out/M02_AXI]
   connect_bd_intf_net -intf_net xbar_periph_out_M03_AXI [get_bd_intf_pins xbar_periph_out/M03_AXI] [get_bd_intf_pins xdma_0/S_AXI_B]
-connect_bd_intf_net -intf_net [get_bd_intf_nets xbar_periph_out_M03_AXI] [get_bd_intf_pins ila_0/SLOT_0_AXI] [get_bd_intf_pins xbar_periph_out/M03_AXI]
   connect_bd_intf_net -intf_net xbar_periph_out_M04_AXI [get_bd_intf_pins xbar_periph_out/M04_AXI] [get_bd_intf_pins xdma_0/S_AXI_LITE]
   connect_bd_intf_net -intf_net xdma_0_M_AXI_B [get_bd_intf_pins xbar_periph_in/S03_AXI] [get_bd_intf_pins xdma_0/M_AXI_B]
-connect_bd_intf_net -intf_net [get_bd_intf_nets xdma_0_M_AXI_B] [get_bd_intf_pins ila_1/SLOT_0_AXI] [get_bd_intf_pins xdma_0/M_AXI_B]
   connect_bd_intf_net -intf_net xdma_0_pcie_mgt [get_bd_intf_ports pci_express_x4] [get_bd_intf_pins xdma_0/pcie_mgt]
 
   # Create port connections
@@ -502,7 +493,7 @@ connect_bd_intf_net -intf_net [get_bd_intf_nets xdma_0_M_AXI_B] [get_bd_intf_pin
   connect_bd_net -net vio_0_probe_out0 [get_bd_pins carfield_xilinx_ip_0/boot_mode_i] [get_bd_pins vio_0/probe_out0]
   connect_bd_net -net vio_0_probe_out1 [get_bd_pins carfield_xilinx_ip_0/boot_mode_safety_i] [get_bd_pins vio_0/probe_out1]
   connect_bd_net -net vio_0_probe_out2 [get_bd_pins psr_10/aux_reset_in] [get_bd_pins psr_333/aux_reset_in] [get_bd_pins vio_0/probe_out2]
-  connect_bd_net -net xdma_0_axi_aclk [get_bd_pins ila_0/clk] [get_bd_pins ila_1/clk] [get_bd_pins xbar_periph_in/aclk1] [get_bd_pins xbar_periph_out/aclk3] [get_bd_pins xdma_0/axi_aclk]
+  connect_bd_net -net xdma_0_axi_aclk [get_bd_pins xbar_periph_in/aclk1] [get_bd_pins xbar_periph_out/aclk3] [get_bd_pins xdma_0/axi_aclk]
 
   # Create address segments
   assign_bd_address -offset 0x00000000 -range 0x0001000000000000 -target_address_space [get_bd_addr_spaces axi_dma_0/Data_SG] [get_bd_addr_segs carfield_xilinx_ip_0/periph_axi_s/reg0] -force