More work on docs

README.md

@@ -8,19 +8,22 @@ University of Bologna.
 
 ## Motivation
 
-The rapid evolution of AI algorithms, the massive amount of sensed data and the pervasive influence
-of AI-enhanced applications across application-domains such as Automotive, Space and Cyber-Physical
-embedded systems (CPSs), call for a paradigm shift from simple micro-controllers towards powerful
-and heterogeneous edge computers in the design of **next generation of mixed-criticality systems
-(MCSs)**. These must not only deliver outstanding performance and energy efficiency but also ensure
-steadfast safety, resilience, and security.
+The rapid evolution of AI algorithms and the massive amount of sensed data across
+application-domains such as Automotive, Space and Cyber-Physical embedded systems (CPSs), call for a
+*paradigm shift* in the design of **next generation of mixed-criticality systems (MCSs)**, from
+simple micro-controllers towards powerful and heterogeneous edge computers.
+
+These must not only deliver outstanding performance and energy efficiency but also ensure steadfast
+safety, resilience, and security.
 
 The Carfield platform aims to tackle these architectural challenges establishing itself as a
-pre-competitive heterogeneous platform for MCSs, underpinned by fully open-source Intellectual
-Properties (IPs). Carfield showcases pioneering hardware solutions, addressing challenges related to
-time-predictable on/off-chip communication, robust fault recovery mechanisms, secure boot processes,
-cryptographic acceleration services, hardware-assisted virtualization, and accelerated computation
-for both floating-point and integer workloads.
+pre-competitive heterogeneous platform for MCSs, underpinned by **fully open-source Intellectual
+Properties (IPs)**.
+
+Carfield showcases pioneering hardware solutions, addressing challenges related to time-predictable
+on/off-chip communication, robust fault recovery mechanisms, secure boot processes, cryptographic
+acceleration services, hardware-assisted virtualization, and accelerated computation for both
+floating-point and integer workloads.
 
 ## Quick Start
 
@@ -32,16 +35,26 @@ for both floating-point and integer workloads.
   Manual](https://pulp-platform.github.io/carfield/um/).
 
 If you are impatient and have all needed
-[dependencies](https://pulp-platform.github.io/carfield/gs/#dependencies), you can run:
+[dependencies](https://pulp-platform.github.io/carfield/gs/#dependencies), type:
 
 ```
 make car-all
 ```
 
-and then run a [simulation](https://pulp-platform.github.io/carfield/tg/sim) by typing:
+and then run a [simulation](https://pulp-platform.github.io/carfield/tg/sim) with Questasim by
+typing:
+
+```
+make car-vsim-sim-build
+cd target/sim/vsim && car-vsim-sim-run CHS_BINARY=../../../sw/tests/bare-metal/hostd/helloworld.car.l2.elf
+```
+
+---
+
+To display the main *Make* build targets and their usage, from the root repository type:
 
 ```
-make car-hw-build car-hw-sim CHS_BINARY=./sw/tests/bare-metal/hostd/helloworld.car.l2.elf
+make help
 ```
 
 ## License

docs/tg/sim.md

@@ -79,11 +79,11 @@ an example with `Serial Link` passive preload of a baremetal program `helloworld
 executed on the *host domain* (Cheshire, i.e., `X=CHS`):
 
 ```tcl
-# Compile design
-make car-hw-build
+# Compile the design
+make car-vsim-sim-build
 
-# Preload `helloworld.car.l2.elf` through serial link, then start and run simulation
-make car-hw-sim CHS_BOOTMODE=0 CHS_PRELMODE=1 CHS_BINARY=./sw/tests/bare-metal/hostd/helloworld.car.l2.elf
+# Preload `helloworld.car.l2.elf` in passive bootmode through serial link, then start the simulation
+cd target/sim/vsim && make car-vsim-sim-run CHS_BOOTMODE=0 CHS_PRELMODE=1 CHS_BINARY=../../../sw/tests/bare-metal/hostd/helloworld.car.l2.elf
 ```
 
 The design needs to be recompiled only when hardware is changed.

docs/um/arch.md

@@ -398,15 +398,15 @@ Compared to vanilla OpenTitan, the secure domain integrated in Carfield is modif
   (TL-UL) internally used by OpenTitan. By only exposing a manager port, unwanted access to the
   secure domain is prevented.
 
-* Embedded flash memory replaced with a simple SRAM preloaded before secure boot procedure from an
+* Embedded flash memory replaced with an SRAM preloaded before secure boot procedure from an
   external SPI flash through OpenTitan private SPI peripheral. Once preload is over, the OpenTitan
-  secure boot framework is unchanged compared to the original.
+  secure boot framework is unchanged compared to the vanilla version.
 
 * Finally, a *boot manager* module has been designed and integrated to manage the [two available
-  bootmodes](./sw.md). In secure mode, the systems executes the secure boot as soon as the reset is
-  asserted, loading code from the external SPI and performing the signature check on its content.
-  Otherwise, the *secure domain* is clock gated and must be clocked and woken-up by an external
-  entity (e.g., *host domain*)
+  bootmodes](./sw.md). In **Secure** mode, the systems executes the secure boot framework as soon as
+  the reset is asserted, loading code from the external SPI and performing the signature check on
+  its content. Otherwise, in **Non-secure** mode, the *secure domain* is clock gated and must be
+  clocked and woken-up by an external entity (e.g., *host domain*)
 
 #### Accelerator domain
 
@@ -443,8 +443,6 @@ and 64-bit integer computation.
 
 The CCs share access to 128KB of L1 scratchpad memory divided into 16 SRAM banks.
 
-We
-
 ### Memory Domain
 
 #### [Dynamic scratchpad memory (SPM)](https://github.com/pulp-platform/dyn_spm)