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fpga: Changing STARTUPE3 tie-off
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CyrilKoe committed Jan 13, 2025
1 parent 7df6ba6 commit 91f1ae5
Showing 1 changed file with 4 additions and 4 deletions.
8 changes: 4 additions & 4 deletions target/xilinx/xilinx_ips/carfield_ip/src/carfield_xilinx.sv
Original file line number Diff line number Diff line change
Expand Up @@ -576,11 +576,11 @@ module carfield_xilinx
.SIM_CCLK_FREQ(0.0)
)
STARTUPE3_inst (
.CFGCLK (),
.CFGMCLK (),
.CFGCLK ( /* Output */ ),
.CFGMCLK ( /* Output */ ),
.DI (qspi_dqi),
.EOS (),
.PREQ (),
.EOS ( /* Output */ ),
.PREQ ( /* Output */ ),
.DO (qspi_dqo),
.DTS (qspi_dqo_ts),
.FCSBO (qspi_cs_b[1]),
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