From 834a2289bd09266c17944bedeaa68aca0a39287c Mon Sep 17 00:00:00 2001 From: Yvan Tortorella Date: Sun, 21 Jan 2024 00:19:28 +0100 Subject: [PATCH] Create config files for different design targets. --- .github/workflows/lint.yml | 1 + Bender.yml | 5 ++ hw/carfield.sv | 4 +- hw/carfield_cfg_pkg.sv | 22 +++---- hw/carfield_pkg.sv | 21 ------- hw/configs/carfield_default_cfg.sv | 50 +++++++++++++++ hw/configs/carfield_fpga_cfg.sv | 63 +++++++++++++++++++ .../flavor_vanilla/src/carfield_top_xilinx.sv | 24 ------- 8 files changed, 131 insertions(+), 59 deletions(-) create mode 100644 hw/configs/carfield_default_cfg.sv create mode 100644 hw/configs/carfield_fpga_cfg.sv diff --git a/.github/workflows/lint.yml b/.github/workflows/lint.yml index ee199735b..7db655b5a 100644 --- a/.github/workflows/lint.yml +++ b/.github/workflows/lint.yml @@ -42,6 +42,7 @@ jobs: uses: chipsalliance/verible-linter-action@main with: paths: hw + exclude_paths: hw/configs extra_args: "--waiver_files .github/verible.waiver" github_token: ${{ secrets.GITHUB_TOKEN }} fail_on_error: true diff --git a/Bender.yml b/Bender.yml index 839bf8891..e30cc07ff 100644 --- a/Bender.yml +++ b/Bender.yml @@ -42,6 +42,7 @@ sources: # package. Files in level 1 only depend on files in level 0, files in level 2 on files in # levels 1 and 0, etc. Files within a level are ordered alphabetically. # Level 0 + - hw/configs/carfield_default_cfg.sv - hw/carfield_cfg_pkg.sv - hw/carfield_pkg.sv - hw/regs/carfield_reg_pkg.sv @@ -69,6 +70,10 @@ sources: files: - target/synth/carfield_synth_wrap.sv + - target: all(xilinx, fpga, xilinx_vanilla, xilinx_bd) + files: + - hw/configs/carfield_fpga_cfg.sv + - target: all(xilinx, fpga, xilinx_vanilla) files: - target/xilinx/src/cdc_dst_axi_err.sv diff --git a/hw/carfield.sv b/hw/carfield.sv index 2740ca899..36f4e815d 100644 --- a/hw/carfield.sv +++ b/hw/carfield.sv @@ -2045,7 +2045,7 @@ mailbox_unit #( carfield_axi_slv_req_t axi_ethernet_req; carfield_axi_slv_rsp_t axi_ethernet_rsp; -if (carfield_pkg::IslandsCfgDefault.EnEthernet) begin : gen_ethernet +if (CarfieldIslandsCfg.ethernet.enable) begin : gen_ethernet axi_cdc_dst #( .LogDepth ( LogDepth ), .SyncStages ( SyncStages ), @@ -2661,7 +2661,7 @@ if (CarfieldIslandsCfg.periph.enable) begin: gen_periph // Handle with care... // CAN bus logic [63:0] can_timestamp; assign can_timestamp = '1; - if (carfield_pkg::IslandsCfgDefault.EnCan) begin : gen_can + if (carfield_configuration::CanEnable) begin : gen_can can_top_apb #( .rx_buffer_size ( 32 ), .txt_buffer_count ( 2 ), diff --git a/hw/carfield_cfg_pkg.sv b/hw/carfield_cfg_pkg.sv index 49260fc88..809b2978f 100644 --- a/hw/carfield_cfg_pkg.sv +++ b/hw/carfield_cfg_pkg.sv @@ -8,6 +8,7 @@ package carfield_cfg_pkg; import cheshire_pkg::*; +import carfield_configuration::*; typedef struct packed { bit enable; @@ -199,19 +200,16 @@ function automatic int unsigned gen_carfield_domains(islands_cfg_t island_cfg); return ret; endfunction -// All fields below are in the form: '{enable, base address, address size}. -// The Secure Domain can only be a master of the crossbar. For this reason -// we can only enable it, and provide fake address ranges. localparam islands_cfg_t CarfieldIslandsCfg = '{ - l2_port0: '{1, 'h78000000, 'h00200000}, - l2_port1: '{1, 'h78200000, 'h00200000}, - safed: '{1, 'h60000000, 'h00800000}, - ethernet: '{1, 'h20000000, 'h00001000}, - periph: '{1, 'h20001000, 'h00009000}, - spatz: '{1, 'h51000000, 'h00800000}, - pulp: '{1, 'h50000000, 'h00800000}, - secured: '{1, '0, '0 }, - mbox: '{1, 'h40000000, 'h00001000} + l2_port0: '{L2Port0Enable, L2Port0Base, L2Port0Size}, + l2_port1: '{L2Port1Enable, L2Port1Base, L2Port1Size}, + safed: '{SafetyIslandEnable, SafetyIslandBase, SafetyIslandSize}, + ethernet: '{EthernetEnable, EthernetBase, EthernetSize}, + periph: '{PeriphEnable, PeriphBase, PeriphSize}, + spatz: '{SpatzClusterEnable, SpatzClusterBase, SpatzClusterSize}, + pulp: '{PulpClusterEnable, PulpClusterBase, PulpClusterSize}, + secured: '{SecurityIslandEnable, SecurityIslandBase, SecurityIslandSize}, + mbox: '{MailboxEnable, MailboxBase, MailboxSize} }; // TODO: specify this is for AXI diff --git a/hw/carfield_pkg.sv b/hw/carfield_pkg.sv index 8334852e2..420ed8efc 100644 --- a/hw/carfield_pkg.sv +++ b/hw/carfield_pkg.sv @@ -401,27 +401,6 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{ }; // verilog_lint: waive-stop line-length -// Control which island to add -typedef struct packed { - bit EnPulpCluster; - bit EnSafetyIsland; - bit EnSpatzCluster; - bit EnOpenTitan; - bit EnCan; - bit EnEthernet; -} islands_fpga_cfg_t; - -// Enable all islands by default -localparam islands_fpga_cfg_t IslandsCfgDefault = '{ - EnPulpCluster : 1, - EnSafetyIsland : 1, - EnSpatzCluster : 1, - EnOpenTitan : 1, - EnCan : 1, - EnEthernet : 0, - default : '1 -}; - // CDC FIFO parameters (FIFO depth). localparam int unsigned LogDepth = 3; diff --git a/hw/configs/carfield_default_cfg.sv b/hw/configs/carfield_default_cfg.sv new file mode 100644 index 000000000..868c59e23 --- /dev/null +++ b/hw/configs/carfield_default_cfg.sv @@ -0,0 +1,50 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +package carfield_configuration; + +import cheshire_pkg::*; + +//L2, port 0 +localparam bit L2Port0Enable = 1; +localparam doub_bt L2Port0Base = 'h78000000; +localparam doub_bt L2Port0Size = 'h00200000; +// L2, port 1 +localparam bit L2Port1Enable = 1; +localparam doub_bt L2Port1Base = L2Port0Base; +localparam doub_bt L2Port1Size = L2Port0Size; +// Safety Island +localparam bit SafetyIslandEnable = 1; +localparam doub_bt SafetyIslandBase = 'h60000000; +localparam doub_bt SafetyIslandSize = 'h00800000; +// Ethernet +localparam bit EthernetEnable = 0; +localparam doub_bt EthernetBase = 'h20000000; +localparam doub_bt EthernetSize = 'h00001000; +// Peripherals +localparam bit PeriphEnable = 1; +localparam doub_bt PeriphBase = 'h20001000; +localparam doub_bt PeriphSize = 'h00009000; +// Spatz cluster +localparam bit SpatzClusterEnable = 1; +localparam doub_bt SpatzClusterBase = 'h51000000; +localparam doub_bt SpatzClusterSize = 'h00800000; +// PULP cluster +localparam bit PulpClusterEnable = 1; +localparam doub_bt PulpClusterBase = 'h50000000; +localparam doub_bt PulpClusterSize = 'h00800000; +// Security Island +localparam bit SecurityIslandEnable = 1; +localparam doub_bt SecurityIslandBase = 'h0; +localparam doub_bt SecurityIslandSize = 'h0; +// Mailbox +localparam bit MailboxEnable = 1; +localparam doub_bt MailboxBase = 'h40000000; +localparam doub_bt MailboxSize = 'h00001000; +// Can +localparam bit CanEnable = 1; + +endpackage diff --git a/hw/configs/carfield_fpga_cfg.sv b/hw/configs/carfield_fpga_cfg.sv new file mode 100644 index 000000000..d1271627b --- /dev/null +++ b/hw/configs/carfield_fpga_cfg.sv @@ -0,0 +1,63 @@ +// Copyright 2022 ETH Zurich and University of Bologna. +// Solderpad Hardware License, Version 0.51, see LICENSE for details. +// SPDX-License-Identifier: SHL-0.51 +// +// Yvan Tortorella + +package carfield_configuration; + +import cheshire_pkg::*; + +`ifndef GEN_PULP_CLUSTER +`define GEN_PULP_CLUSTER 0 +`endif +`ifndef GEN_SAFETY_ISLAND +`define GEN_SAFETY_ISLAND 0 +`endif +`ifndef GEN_SPATZ_CLUSTER +`define GEN_SPATZ_CLUSTER 0 +`endif +`ifndef GEN_OPEN_TITAN +`define GEN_OPEN_TITAN 0 +`endif + +//L2, port 0 +localparam bit L2Port0Enable = 1; +localparam doub_bt L2Port0Base = 'h78000000; +localparam doub_bt L2Port0Size = 'h00200000; +// L2, port 1 +localparam bit L2Port1Enable = 1; +localparam doub_bt L2Port1Base = L2Port0Base; +localparam doub_bt L2Port1Size = L2Port0Size; +// Safety Island +localparam bit SafetyIslandEnable = `GEN_SAFETY_ISLAND; +localparam doub_bt SafetyIslandBase = 'h60000000; +localparam doub_bt SafetyIslandSize = 'h00800000; +// Ethernet +localparam bit EthernetEnable = 0; +localparam doub_bt EthernetBase = 'h20000000; +localparam doub_bt EthernetSize = 'h00001000; +// Peripherals +localparam bit PeriphEnable = 1; +localparam doub_bt PeriphBase = 'h20001000; +localparam doub_bt PeriphSize = 'h00009000; +// Spatz cluster +localparam bit SpatzClusterEnable = `GEN_SPATZ_CLUSTER; +localparam doub_bt SpatzClusterBase = 'h51000000; +localparam doub_bt SpatzClusterSize = 'h00800000; +// PULP cluster +localparam bit PulpClusterEnable = `GEN_PULP_CLUSTER; +localparam doub_bt PulpClusterBase = 'h50000000; +localparam doub_bt PulpClusterSize = 'h00800000; +// Security Island +localparam bit SecurityIslandEnable = `GEN_OPEN_TITAN; +localparam doub_bt SecurityIslandBase = 'h0; +localparam doub_bt SecurityIslandSize = 'h0; +// Mailbox +localparam bit MailboxEnable = 1; +localparam doub_bt MailboxBase = 'h40000000; +localparam doub_bt MailboxSize = 'h00001000; +// Can +localparam bit CanEnable = 0; + +endpackage diff --git a/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv b/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv index 23ba5d3d7..01377427b 100644 --- a/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv +++ b/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv @@ -399,32 +399,9 @@ module carfield_top_xilinx // Carfield Cfg // ////////////////// -`ifndef GEN_PULP_CLUSTER -`define GEN_PULP_CLUSTER 0 -`endif -`ifndef GEN_SAFETY_ISLAND -`define GEN_SAFETY_ISLAND 0 -`endif -`ifndef GEN_SPATZ_CLUSTER -`define GEN_SPATZ_CLUSTER 0 -`endif -`ifndef GEN_OPEN_TITAN -`define GEN_OPEN_TITAN 0 -`endif - localparam cheshire_cfg_t Cfg = carfield_pkg::CarfieldCfgDefault; `CHESHIRE_TYPEDEF_ALL(carfield_, Cfg) - localparam islands_cfg_t IslandsCfg = '{ - EnPulpCluster : `GEN_PULP_CLUSTER, - EnSafetyIsland : `GEN_SAFETY_ISLAND, - EnSpatzCluster : `GEN_SPATZ_CLUSTER, - EnOpenTitan : `GEN_OPEN_TITAN, - EnCan : 0, - EnEthernet : 0, - default : '1 - }; - /////////////////// // LLC interface // /////////////////// @@ -498,7 +475,6 @@ module carfield_top_xilinx carfield #( .Cfg (carfield_pkg::CarfieldCfgDefault), - .IslandsCfg(IslandsCfg), .reg_req_t(carfield_reg_req_t), .reg_rsp_t(carfield_reg_rsp_t), `ifdef GEN_NO_HYPERBUS