diff --git a/docs/img/arch.svg b/docs/img/arch.svg index ef0e6e719..82e97a623 100644 --- a/docs/img/arch.svg +++ b/docs/img/arch.svg @@ -1,3 +1,4 @@ + -
Last Level Cache
(LLC)
Last Level C...
HyperRAM
Mem Ctrl
HyperRAM...
Host Domain (Cheshire)
Host Domain (Cheshire)
64-b AXI-4 RT System Interconnect 
64-b AXI-4 RT System Interconnect 
System iDMA
System iDMA
JTAG Debug
JTAG Debug
Heterogeneous Cluster Interconnect
Heterogeneous Cluster Interconnect
256 kB L1 Multi-Banked SPM
256 kB L1 Multi-Banked SPM
I$
I$
Tensor
Core
(RedMule)
Tensor...
32-b
RV
0
32-b...
32-b
RV
11
32-b...
. . .
. . .
HMR Wrapper
HMR Wrapper
DMA
DMA
AXI
AXI
L1 D$
L1 D$
L1 I$
L1 I$
CLIC
CLIC
FPU
FPU
MMU
MMU
CVA6
RV64GCH
CVA6...
Linux Peripherals
Linux Periphera...
UART
UART
QSPI
QSPI
SLINK
SLINK
GPIOs
GPIOs
I2C
I2C
VGA
VGA
PLIC
&
CLINT
PLIC...
Secure Bus Interconnect (TLUL)
Secure Bus Interconnect (TLUL)
32-b IBEX
32-b I...
PMP
PMP
PLIC
PLIC
RV Debug
RV Debug
JTAG 
JTAG 
Key Mngr
Key Mngr
RoT
RoT
Life-Cyc
Control
Life-Cyc...
512 kB
SRAM
512 kB...
16 kB
ROM
16 kB...
16 kb OTP 
MEMORY
16 kb OTP...
TLUL to AXI
TLUL to...
Bridge
Bridge
Timers
Timers
Watchdog
Watchdog
Memory Region
Memory Region
SPI-M
SPI-M
Core Region
Core Region
Secure Domain
Secure Domain
32-b IBEX
32-b I...
Lockstep
Lockstep
RNG
RNG
AES128
AES128
SHA2
SHA2
OTBN
OTBN
KMAC
KMAC
HMAC
HMAC
Crypto-Acc.
Crypto-Acc.
CAN-FD
CAN-FD
Ethernet
Ethernet
Generic
Timers
Generic...
Watchdog
Timer
Watchdog...
Cluster Interconnect
Cluster Interconnect
DMA
DMA
128kB L1 Multi-Banked SPM
128kB L1 Multi-Banked SPM
CTRL CC
CTRL CC
FP Vector Cluster (Spatz)
FP Vector Cluster (Spatz)
I$
I$
VRF
VRF
FPU
FPU
FPU
FPU
CC0
CC0
PE1
PE1
VRF
VRF
FPU
FPU
FPU
FPU
CC0
CC0
PE0
PE0
AXI
AXI
AXI CDC
AXI CDC
AXI CDC
AXI CDC
AXI CDC
AXI CDC
APB
APB
Integer HMR Cluster (PULP)
Integer HMR Cluster (PULP)
Platform
Ctrl
Registers
Platform...
APB
APB
Mailbox
Unit
Mailbox...
32-b
RV
1
32-b...
AXI CDC
AXI CDC
AXI CDC
AXI CDC
AXI CDC
AXI CDC
PWM
Timers
PWM...
CV32
RT
0
CV32...
OBI Interconnect
OBI Interconnect
Demux
Demux
Local
Periph
Local...
Boot
Rom
Boot...
ECC
Mgr
ECC...
ERR
ERR
Private
DSPM
Privat...
Private
ISPM
Privat...
CV32
RT
0
CV32...
CV32
RT
0
CV32...
Triple-Core-Lockstep
Triple-Core-Lockstep
CLIC
CLIC
RV Debug
RV Debug
JTAG 
JTAG 
Insn
Insn
Data
Data
Shadow
Shadow
Safety
Domain
Safety...
AXI-OBI
AXI-OBI
AXI to MEM
AXI to MEM
Bank group (N-1)
Bank group (N-1)
AXI to MEM
AXI to MEM
Dynamic Addressing
Mode
Dynamic Addressing...
ECC
ECC
32b MEM
Bank
32b MEM...
ECC
ECC
32b MEM
Bank
32b MEM...
Bank group 0
Bank group 0
ECC
ECC
32b MEM
Bank
32b MEM...
ECC
ECC
32b MEM
Bank
32b MEM...
Memory Interconnect
Memory Interconnect
L1 D$
L1 D$
L1 I$
L1 I$
CLIC
CLIC
FPU
FPU
MMU
MMU
CVA6
RV64GCH
CVA6...
Dynamic SPM
Dynamic SPMText is not SVG - cannot display \ No newline at end of file +
Partitionable hybrid LLC/SPM
Partitionable...
HyperRAM
controller
HyperRAM...
Host Domain (Cheshire)
Host Domain (Cheshire)
System Bus (64-bit AXI4 matrix)
System Bus (64-bit AXI4 matrix)
DMA
DMA
JTAG Debug
JTAG Debug
System Bus (TLUL)
System Bus (TLUL)
Ibex RV32
Ibex RV...
PLIC
PLIC
Life Cyc.
Life Cyc...
Main SPM
Main SPM
OTP mem.
OTP mem.
Ibex RV32
Ibex RV...
Dual Lockstep
Dual Lockstep
RNG
RNG
AES128
AES128
SHA2
SHA2
OTBN
OTBN
KMAC
KMAC
HMAC
HMAC
Crypto DSAs
Crypto DSAs
CAN x1
CAN x1
ETH x1
ETH x1
Generic
Timers
Generic...
WDT x1
WDT x1
Low-latency TCDM bus
Low-latency TCDM bus
DMA
DMA
SPM interleaved (M banks)
SPM interleaved (M banks)
I$
I$
VRF
VRF
FPU0
FPU0
Integer PMCA
Integer PMCA
PCRs
PCRs
Mailbox
Unit
Mailbox...
PWM
Timers
PWM...
CV32
RT
CV32...
System bus (OBI)
System bus (OBI)
Peripheral bus (Regbus/APB)
Peripheral bus (Regbus/APB)
PCRs
PCRs
Boot
ROM
Boot...
ECC
Mgr
ECC...
Private
DSPM + ECC
Private...
Triple-Core-Lockstep
Triple-Core-Lockstep
CLIC
CLIC
JTAG
Dbg
JTAG...
Dyn. addressing switch
Dyn. addressing switch
Bank group 0
Bank group 0
SPM bank + ECC
SPM bank + ECC
SPM bank + ECC
SPM bank + ECC
Bank group arbiter
Bank group arbiter
Peripheral bus (Regbus/APB)
Peripheral bus (Regbus/APB)
Boot & Host interfaces
Boot & Host interfaces
UART x1
UART x1
QSPIM x1
QSPIM x1
I2CM x1
I2CM x1
USB x1
USB x1
PLIC x1
PLIC x1
CLINT/CLIC (per-core)
CLINT/CLIC (...
Intr. Router
Intr. Router
BootROM
BootROM
Host PCRs
Host PCRs
L1 D$ & I$
L1 D$ & I$
FPU
FPU
MMU
MMU
CVA6RT
RV64GCH
CVA6RT...
Peripheral bus (TLUL)
Peripheral bus (TLUL)
Timers
Timers
OTP ctrl.
OTP ctrl...
UART
UART
Pwr. mgr.
Pwr. mgr.
Clk. mgr.
Clk. mgr.
Rst. mgr.
Rst. mgr.
Key mngr.
Key mng...
DMA
DMA
WDT
WDT
SPIM
SPIM
Alert
Alert
FPU
FPU
MMU
MMU
CVA6RT
RV64GCH
CVA6RT...
Self-inv. cache coher.
Self-inv. cache coh...
Serial Link
Serial Link
Peripheral bus (APB)
Peripheral bus (APB)
Peripherals
Peripherals
AON
AON
JTAG Dbg
JTAG D...
CV32
RT
CV32...
CV32
RT
CV32...
FPU
FPU
FPU
FPU
FPU
FPU
Gen. Timer
Gen. T...
Private
ISPM + ECC
Private...
BootROM
BootROM
L1 D$ & I$
L1 D$ & I$
Self-inv. cache coher.
Self-inv. cache coh...
Bank group N-1
Bank group N-1
SPM bank + ECC
SPM bank + ECC
SPM bank + ECC
SPM bank + ECC
FPU3
FPU3
IPU
IPU
Snitch
RV32
Snitch...
Spatz RVV coproc.
Spatz RVV...
Snitch
RV32
Snitch...
VRF
VRF
FPU0
FPU0
FPU3
FPU3
IPU
IPU
Snitch
RV32
Snitch...
Spatz RVV coproc.
Spatz RVV...
CV32
#0
CV32...
Tensor
DSA
(RedMulE)
Tensor...
Low-latency TCDM bus
Low-latency TCDM bus
DMA
DMA
SPM interleaved (M banks)
SPM interleaved (M banks)
I$
I$
HMR Mngr.
HMR Mngr.
Peripherals
Peripherals
Vector PMCA
Vector PMCA
Accelerator Domain
Accelerator Domain
Dynamic SPM
Dynamic SPM
Safe domain
Safe domain
Secure domain (OpenTitan)
Secure domain (OpenTitan)
CV32
#1
CV32...
CV32
#11
CV32...
HMR cluster
HMR cluster
Legend
Legend
AXI-REALM Guard & Cfg.
AXI-REALM...
GPIO x32
GPIO x32
AXI-REALM real-time monitoring and regulation unit for managers
AXI-REALM real-time monitoring and regulation unit for managers
Bus protocol adapter
Bus protocol adapterText is not SVG - cannot display \ No newline at end of file diff --git a/docs/tg/index.md b/docs/tg/index.md index 18b46b641..025d16bd3 100644 --- a/docs/tg/index.md +++ b/docs/tg/index.md @@ -4,7 +4,7 @@ A *target* refers to an end use of Carfield. This could be a simulation setup, a implementation, or the less common integration into other SoCs. Target setups can either be *included* in this repository or live in an *external* repository and -use Cheshire as a dependency. +use Carfield as a dependency. ## Included Targets @@ -12,7 +12,7 @@ Included target setups live in the `target` directory. Each included target has page* in this chapter: - [Simulation](sim.md) -- [Synthesis](synth.md) +- [Synthesis and physical implementation](synth.md) - [Xilinx FPGAs](xilinx.md) ## External Targets diff --git a/docs/tg/integr.md b/docs/tg/integr.md index 8a56437c2..9db36172c 100644 --- a/docs/tg/integr.md +++ b/docs/tg/integr.md @@ -60,12 +60,12 @@ localparam cheshire_cfg_t CheshireCfg = gen_cheshire_cfg(); ); ``` -## Verifying Cheshire In-System +## Verifying Carfield In-System -To simplify the simulation and verification of Carfield in other systems, we provide a monolithic -block of verification IPs called `carfield_vip`. This is used along with the `X_vip` modules of -other domains, such as Cheshire, Safe domain and Secure domain. Their description can be found in -the associated domain's documentation. In particular, `carfield_ip` currently includes: +To simplify the simulation and verification of Carfield in other systems or top-level wrappers +(e.g., ASIC), we provide a monolithic block of verification IPs called `carfield_vip`. This is used +along with the `X_vip` modules provided for other domains. Their description can be found in the +dedicated domain's documentation. In particular, `carfield_vip` currently includes: * Preloadable Cypress HyperRAM models (used to simulate boot). diff --git a/docs/tg/synth.md b/docs/tg/synth.md index aad267199..43dc0f38c 100644 --- a/docs/tg/synth.md +++ b/docs/tg/synth.md @@ -1,4 +1,4 @@ -# Synthesis +# Logic synthesis and physical implementation Currently, synthesis of Carfield is available with closed source tools, and hence its scripts are added in the `nonfree` repository mentioned in the [Getting Started](../gs.md) section. @@ -7,3 +7,10 @@ Once open-EDA and open-PDK flow is available, it will be updated in this page. For independent synthesis of carfield by external users, we provide a wrapper under `target/synth/carfield_synth_wrap.sv`. + +### Memory requirements for physical implementation + +TODO + + + diff --git a/docs/um/arch.md b/docs/um/arch.md index 03f59bf23..b2fc2f9c8 100644 --- a/docs/um/arch.md +++ b/docs/um/arch.md @@ -11,27 +11,28 @@ interconnect ports and interrupts. The above block diagram depicts a fully-featured Carfield SoC, which currently provides: -- **Computing Domain**: +- **Domains**: - *Host domain* (Cheshire), a Linux-capable RV64 system based on dual-core CVA6 processors with self-invalidation coherency mechanism - *Safe domain*, a Triple-Core-Lockstep (TCLS) RV32 microcontroller system based on CV32E40P, with fast interrupt handling through the RISC-V CLIC - *Secure domain*, a Dual-Core-Lockstep (DCLS) RV32 Hardware Root of Trust (HW RoT) systems that - ensures the secure boot for the whole platform, serves as secure monitor for the entire - system, and provides crypto acceleration services through various crypto-accelerators + ensures the secure boot for the whole platform, serves as secure monitor for the entire + system, and provides crypto acceleration services through various crypto-accelerators - *Accelerator domain*, comprises two programmable multi-core accelerators (PMCAs), an 12-cores integer cluster with Hybrid Modular Redundancy (HMR) capabilities oriented to compute intensive integer workloads such as AI, and a vectorial cluster with floating point vector processing capabilities to accelerate intensive control tasks -- **Memory Domain**: +- **On-chip and off-chip memory endpoints**: - *Dynamic SPM*: dynamically configurable scratchpad memory (SPM) for *interleaved* or *contiguous* accesses aiming at reducing systematic bus conflicts to improve the time-predictability of the on-chip communication - - *LLC SPM*: the last-level cache (*host domain*) can be configured as SPM at runtime, as - described in Cheshire's [Architecture](https://pulp-platform.github.io/cheshire/um/arch/) + - *Partitionable hybrid LLC SPM*: the last-level cache (*host domain*) can be configured as SPM + at runtime, as described in Cheshire's + [Architecture](https://pulp-platform.github.io/cheshire/um/arch/) - *External DRAM*: off-chip HyperRAM (Infineon) interfaced with in-house, open-source AXI4 - Hyberbus memory controller and digital PHY + Hyberbus memory controller and digital PHY connected to Cheshire's LLC - **Mailbox unit** - Main communication vehicle among domains, based on an interrupt notification mechanism @@ -67,67 +68,64 @@ clarity. | **Start Address** | **End Address (excl.)** | **Length** | **Size** | **Region** | **Device** | |--------------------------|-------------------------|------------------|----------|--------------|-----------------------------------------| | **Internal to Cheshire** | | | | | | -|--------------------------|-------------------------|------------------|----------|--------------|-----------------------------------------| -| `0x0000_0000_0000` | `0x0000_0004_0000` | `0x04_0000` | 256 KiB | Debug | Debug CVA6 | -| `0x0000_0004_0000` | `0x0000_0100_0000` | | | *Reserved* | | -| `0x0000_0100_0000` | `0x0000_0100_1000` | `0x00_1000` | 4 KiB | Config | AXI DMA Config | -| `0x0000_0100_1000` | `0x0000_0200_0000` | | | *Reserved* | | -| `0x0000_0200_0000` | `0x0000_0204_0000` | `0x04_0000` | 256 KiB | Memory | Boot ROM | -| `0x0000_0204_0000` | `0x0000_0208_0000` | `0x04_0000` | 256 KiB | Irq | CLINT | -| `0x0000_0208_0000` | `0x0000_020c_0000` | `0x04_0000` | 256 KiB | Irq | IRQ Routing | -| `0x0000_020c_0000` | `0x0000_0210_0000` | `0x04_0000` | 256 KiB | Irq | AXI-REALM unit | -| `0x0000_020c_0000` | `0x0000_0300_0000` | | | *Reserved* | | -| `0x0000_0300_0000` | `0x0000_0300_1000` | `0x00_1000` | 4 KiB | Config | CSRs | -| `0x0000_0300_1000` | `0x0000_0300_2000` | `0x00_1000` | 4 KiB | Config | LLC | -| `0x0000_0300_2000` | `0x0000_0300_3000` | `0x00_1000` | 4 KiB | I/O | UART | -| `0x0000_0300_3000` | `0x0000_0300_4000` | `0x00_1000` | 4 KiB | I/O | I2C | -| `0x0000_0300_4000` | `0x0000_0300_5000` | `0x00_1000` | 4 KiB | I/O | SPIM | -| `0x0000_0300_5000` | `0x0000_0300_6000` | `0x00_1000` | 4 KiB | I/O | GPIO | -| `0x0000_0300_6000` | `0x0000_0300_7000` | `0x00_1000` | 4 KiB | Config | Serial Link | -| `0x0000_0300_7000` | `0x0000_0300_8000` | `0x00_1000` | 4 KiB | Config | VGA | -| `0x0000_0300_8000` | `0x0000_0300_A000` | `0x00_1000` | 8 KiB | Config | UNBENT (bus error unit) | -| `0x0000_0300_A000` | `0x0000_0300_B000` | `0x00_1000` | 4 KiB | Config | Tagger (cache partitioning) | -| `0x0000_0300_8000` | `0x0000_0400_0000` | | | *Reserved* | | -| `0x0000_0400_0000` | `0x0000_1000_0000` | `0x40_0000` | 64 MiB | Irq | PLIC | -| `0x0000_0800_0000` | `0x0000_0C00_0000` | `0x40_0000` | 64 MiB | Irq | CLICs | -| `0x0000_1000_0000` | `0x0000_1400_0000` | `0x40_0000` | 64 MiB | Memory | LLC Scratchpad | -| `0x0000_1400_0000` | `0x0000_1800_0000` | `0x40_0000` | 64 MiB | Memory | LLC Scratchpad | -| `0x0000_1800_0000` | `0x0000_2000_0000` | | | *Reserved* | | -|--------------------------|-------------------------|------------------|----------|--------------|-----------------------------------------| +| `0x0000_0000` | `0x0004_0000` | `0x04_0000` | 256 KiB | Debug | Debug CVA6 | +| `0x0004_0000` | `0x0100_0000` | | | *Reserved* | | +| `0x0100_0000` | `0x0100_1000` | `0x00_1000` | 4 KiB | Config | AXI DMA Config | +| `0x0100_1000` | `0x0200_0000` | | | *Reserved* | | +| `0x0200_0000` | `0x0204_0000` | `0x04_0000` | 256 KiB | Memory | Boot ROM | +| `0x0204_0000` | `0x0208_0000` | `0x04_0000` | 256 KiB | Irq | CLINT | +| `0x0208_0000` | `0x020c_0000` | `0x04_0000` | 256 KiB | Irq | IRQ Routing | +| `0x020c_0000` | `0x0210_0000` | `0x04_0000` | 256 KiB | Irq | AXI-REALM unit | +| `0x020c_0000` | `0x0300_0000` | | | *Reserved* | | +| `0x0300_0000` | `0x0300_1000` | `0x00_1000` | 4 KiB | Config | CSRs | +| `0x0300_1000` | `0x0300_2000` | `0x00_1000` | 4 KiB | Config | LLC | +| `0x0300_2000` | `0x0300_3000` | `0x00_1000` | 4 KiB | I/O | UART | +| `0x0300_3000` | `0x0300_4000` | `0x00_1000` | 4 KiB | I/O | I2C | +| `0x0300_4000` | `0x0300_5000` | `0x00_1000` | 4 KiB | I/O | SPIM | +| `0x0300_5000` | `0x0300_6000` | `0x00_1000` | 4 KiB | I/O | GPIO | +| `0x0300_6000` | `0x0300_7000` | `0x00_1000` | 4 KiB | Config | Serial Link | +| `0x0300_7000` | `0x0300_8000` | `0x00_1000` | 4 KiB | Config | VGA | +| `0x0300_8000` | `0x0300_A000` | `0x00_1000` | 8 KiB | Config | UNBENT (bus error unit) | +| `0x0300_A000` | `0x0300_B000` | `0x00_1000` | 4 KiB | Config | Tagger (cache partitioning) | +| `0x0300_8000` | `0x0400_0000` | | | *Reserved* | | +| `0x0400_0000` | `0x1000_0000` | `0x40_0000` | 64 MiB | Irq | PLIC | +| `0x0800_0000` | `0x0C00_0000` | `0x40_0000` | 64 MiB | Irq | CLICs | +| `0x1000_0000` | `0x1400_0000` | `0x40_0000` | 64 MiB | Memory | LLC Scratchpad | +| `0x1400_0000` | `0x1800_0000` | `0x40_0000` | 64 MiB | Memory | LLC Scratchpad | +| `0x1800_0000` | `0x2000_0000` | | | *Reserved* | | | **External to Cheshire** | | | | | | -|--------------------------|-------------------------|------------------|----------|--------------|-----------------------------------------| -| `0x0000_2000_0000` | `0x0000_2000_1000` | `0x00_1000` | 4 KiB | I/O | ETHERNET | -| `0x0000_2000_1000` | `0x0000_2000_2000` | `0x00_1000` | 4 KiB | I/O | CAN BUS | -| `0x0000_2000_2000` | `0x0000_2000_3000` | `0x00_1000` | 4 KiB | I/O | (empty) | -| `0x0000_2000_3000` | `0x0000_2000_4000` | `0x00_1000` | 4 KiB | I/O | (empty) | -| `0x0000_2000_4000` | `0x0000_2000_5000` | `0x00_1000` | 4 KiB | I/O | GP TIMER 1 (System timer) | -| `0x0000_2000_5000` | `0x0000_2000_6000` | `0x00_1000` | 4 KiB | I/O | GP TIMER 2 (Advanced timer) | -| `0x0000_2000_6000` | `0x0000_2000_7000` | `0x00_1000` | 4 KiB | I/O | GP TIMER 3 | -| `0x0000_2000_7000` | `0x0000_2000_8000` | `0x00_1000` | 4 KiB | I/O | WATCHDOG timer | -| `0x0000_2000_8000` | `0x0000_2000_9000` | `0x00_1000` | 4 KiB | I/O | (empty) | -| `0x0000_2000_9000` | `0x0000_2000_a000` | `0x00_1000` | 4 KiB | I/O | HyperBUS | -| `0x0000_2000_a000` | `0x0000_2000_b000` | `0x00_1000` | 4 KiB | I/O | Pad Config | -| `0x0000_2000_b000` | `0x0000_2000_c000` | `0x00_1000` | 4 KiB | I/O | L2 ECC Config | -| `0x0000_2001_0000` | `0x0000_2001_1000` | `0x00_1000` | 4 KiB | I/O | Carfield Control and Status | -| `0x0000_2002_0000` | `0x0000_2002_1000` | `0x00_1000` | 4 KiB | I/O | PLL/CLOCK | -| `0x0000_2800_1000` | `0x0000_4000_0000` | | | *Reserved* | | -| `0x0000_4000_0000` | `0x0000_4000_1000` | `0x00_1000` | 4 KiB | Irq | Mailboxes | -| `0x0000_4000_1000` | `0x0000_5000_0000` | | | *Reserved* | | -| `0x0000_5000_0000` | `0x0000_5080_0000` | `0x80_0000` | 8 MiB | Accelerators | Integer Cluster | -| `0x0000_5080_0000` | `0x0000_5100_0000` | | | *Reserved* | | -| `0x0000_5100_0000` | `0x0000_5180_0000` | `0x80_0000` | 8 MiB | Accelerators | FP Cluster | -| `0x0000_5100_0000` | `0x0000_6000_0000` | | | *Reserved* | | -| `0x0000_6000_0000` | `0x0000_6002_0000` | `0x02_0000` | 128 KiB | Safe domain | Safety Island Memory | -| `0x0000_6002_0000` | `0x0000_6020_0000` | `0x1e_0000` | | Safe domain | reserved | -| `0x0000_6020_0000` | `0x0000_6030_0000` | `0x10_0000` | | Safe domain | Safety Island Peripherals | -| `0x0000_6030_0000` | `0x0000_6080_0000` | `0x50_0000` | | Safe domain | reserved | -| `0x0000_6080_0000` | `0x0000_7000_0000` | | | *Reserved* | | -| `0x0000_7000_0000` | `0x0000_7002_0000` | `0x02_0000` | 128 KiB | Memory | LLC Scratchpad | -| `0x0000_7800_0000` | `0x0000_7810_0000` | `0x10_0000` | 1 MiB | Memory | L2 Scratchpad (Port 1, interleaved) | -| `0x0000_7810_0000` | `0x0000_7820_0000` | `0x10_0000` | 1 MiB | Memory | L2 Scratchpad (Port 1, non-interleaved) | -| `0x0000_7820_0000` | `0x0000_7830_0000` | `0x10_0000` | 1 MiB | Memory | L2 Scratchpad (Port 2, interleaved) | -| `0x0000_7830_0000` | `0x0000_7840_0000` | `0x10_0000` | 1 MiB | Memory | L2 Scratchpad (Port 2, non-interleaved) | -| `0x0000_8000_0000` | `0x0020_8000_0000` | `0x20_0000_0000` | 128 GiB | Memory | LLC/DRAM | +| `0x2000_0000` | `0x2000_1000` | `0x00_1000` | 4 KiB | I/O | ETHERNET | +| `0x2000_1000` | `0x2000_2000` | `0x00_1000` | 4 KiB | I/O | CAN BUS | +| `0x2000_2000` | `0x2000_3000` | `0x00_1000` | 4 KiB | I/O | (empty) | +| `0x2000_3000` | `0x2000_4000` | `0x00_1000` | 4 KiB | I/O | (empty) | +| `0x2000_4000` | `0x2000_5000` | `0x00_1000` | 4 KiB | I/O | GP TIMER 1 (System timer) | +| `0x2000_5000` | `0x2000_6000` | `0x00_1000` | 4 KiB | I/O | GP TIMER 2 (Advanced timer) | +| `0x2000_6000` | `0x2000_7000` | `0x00_1000` | 4 KiB | I/O | GP TIMER 3 | +| `0x2000_7000` | `0x2000_8000` | `0x00_1000` | 4 KiB | I/O | WATCHDOG timer | +| `0x2000_8000` | `0x2000_9000` | `0x00_1000` | 4 KiB | I/O | (empty) | +| `0x2000_9000` | `0x2000_a000` | `0x00_1000` | 4 KiB | I/O | HyperBUS | +| `0x2000_a000` | `0x2000_b000` | `0x00_1000` | 4 KiB | I/O | Pad Config | +| `0x2000_b000` | `0x2000_c000` | `0x00_1000` | 4 KiB | I/O | L2 ECC Config | +| `0x2001_0000` | `0x2001_1000` | `0x00_1000` | 4 KiB | I/O | Carfield Control and Status | +| `0x2002_0000` | `0x2002_1000` | `0x00_1000` | 4 KiB | I/O | PLL/CLOCK | +| `0x2800_1000` | `0x4000_0000` | | | *Reserved* | | +| `0x4000_0000` | `0x4000_1000` | `0x00_1000` | 4 KiB | Irq | Mailboxes | +| `0x4000_1000` | `0x5000_0000` | | | *Reserved* | | +| `0x5000_0000` | `0x5080_0000` | `0x80_0000` | 8 MiB | Accelerators | Integer Cluster | +| `0x5080_0000` | `0x5100_0000` | | | *Reserved* | | +| `0x5100_0000` | `0x5180_0000` | `0x80_0000` | 8 MiB | Accelerators | FP Cluster | +| `0x5100_0000` | `0x6000_0000` | | | *Reserved* | | +| `0x6000_0000` | `0x6002_0000` | `0x02_0000` | 128 KiB | Safe domain | Safety Island Memory | +| `0x6002_0000` | `0x6020_0000` | `0x1e_0000` | | Safe domain | reserved | +| `0x6020_0000` | `0x6030_0000` | `0x10_0000` | | Safe domain | Safety Island Peripherals | +| `0x6030_0000` | `0x6080_0000` | `0x50_0000` | | Safe domain | reserved | +| `0x6080_0000` | `0x7000_0000` | | | *Reserved* | | +| `0x7000_0000` | `0x7002_0000` | `0x02_0000` | 128 KiB | Memory | LLC Scratchpad | +| `0x7800_0000` | `0x7810_0000` | `0x10_0000` | 1 MiB | Memory | L2 Scratchpad (Port 1, interleaved) | +| `0x7810_0000` | `0x7820_0000` | `0x10_0000` | 1 MiB | Memory | L2 Scratchpad (Port 1, non-interleaved) | +| `0x7820_0000` | `0x7830_0000` | `0x10_0000` | 1 MiB | Memory | L2 Scratchpad (Port 2, interleaved) | +| `0x7830_0000` | `0x7840_0000` | `0x10_0000` | 1 MiB | Memory | L2 Scratchpad (Port 2, non-interleaved) | +| `0x8000_0000` | `0x20_8000_0000` | `0x20_0000_0000` | 128 GiB | Memory | LLC/DRAM | ## Interrupt map @@ -135,172 +133,152 @@ Carfield's interrupt components are exhaustivly described in the dedicated section of the [documentation for Cheshire](https://pulp-platform.github.io/cheshire/um/arch/). This section describes Carfield's interrupt map. -| **Interrupt Source** | **Interrupt sink** | **Bitwidth** | **Connection** | **Type** | **Comment** | -|---------------------------|--------------------|--------------|-------------------------------------------------------------|-----------------|---------------------------| -| **Carfield peripherals** | | | | | | -|---------------------------|--------------------|--------------|-------------------------------------------------------------|-----------------|---------------------------| -| intr_wkup_timer_expired_o | | 1 | car_wdt_intrs[0] | level-sensitive | | -| intr_wdog_timer_bark_o | | 1 | car_wdt_intrs[1] | level-sensitive | | -| nmi_wdog_timer_bark_o | | 1 | car_wdt_intrs[2] | level-sensitive | | -| wkup_req_o | | 1 | car_wdt_intrs[3] | level-sensitive | | -| aon_timer_rst_req_o | | 1 | car_wdt_intrs[4] | level-sensitive | | -| irq | | 1 | car_can_intr | level-sensitive | | -| ch_0_o[0] | | 1 | car_adv_timer_ch0 | edge-sensitive | | -| ch_0_o[1] | | 1 | car_adv_timer_ch1 | edge-sensitive | | -| ch_0_o[2] | | 1 | car_adv_timer_ch2 | edge-sensitive | | -| ch_0_o[3] | | 1 | car_adv_timer_ch3 | edge-sensitive | | -| events_o[0] | | 1 | car_adv_timer_events[0] | edge-sensitive | | -| events_o[1] | | 1 | car_adv_timer_events[1] | edge-sensitive | | -| events_o[2] | | 1 | car_adv_timer_events[2] | edge-sensitive | | -| events_o[3] | | 1 | car_adv_timer_events[3] | edge-sensitive | | -| irq_lo_o | | 1 | car_sys_timer_lo | edge-sensitive | | -| irq_hi_o | | 1 | car_sys_timer_hi | edge-sensitive | | -|---------------------------|--------------------|--------------|-------------------------------------------------------------|-----------------|---------------------------| -| **Cheshire peripherals** | | | | | | -|---------------------------|--------------------|--------------|-------------------------------------------------------------|-----------------|---------------------------| -| zero | | 1 | zero | level-sensitive | | -| uart | | 1 | uart | level-sensitive | | -| i2c_fmt_threshold | | 1 | i2c_fmt_threshold | level-sensitive | | -| i2c_rx_threshold | | 1 | i2c_rx_threshold | level-sensitive | | -| i2c_fmt_overflow | | 1 | i2c_fmt_overflow | level-sensitive | | -| i2c_rx_overflow | | 1 | i2c_rx_overflow | level-sensitive | | -| i2c_nak | | 1 | i2c_nak | level-sensitive | | -| i2c_scl_interference | | 1 | i2c_scl_interference | level-sensitive | | -| i2c_sda_interference | | 1 | i2c_sda_interference | level-sensitive | | -| i2c_stretch_timeout | | 1 | i2c_stretch_timeout | level-sensitive | | -| i2c_sda_unstable | | 1 | i2c_sda_unstable | level-sensitive | | -| i2c_cmd_complete | | 1 | i2c_cmd_complete | level-sensitive | | -| i2c_tx_stretch | | 1 | i2c_tx_stretch | level-sensitive | | -| i2c_tx_overflow | | 1 | i2c_tx_overflow | level-sensitive | | -| i2c_acq_full | | 1 | i2c_acq_full | level-sensitive | | -| i2c_unexp_stop | | 1 | i2c_unexp_stop | level-sensitive | | -| i2c_host_timeout | | 1 | i2c_host_timeout | level-sensitive | | -| spih_error | | 1 | spih_error | level-sensitive | | -| spih_spi_event | | 1 | spih_spi_event | level-sensitive | | -| gpio | | 32 | gpio | level-sensitive | | -|---------------------------|--------------------|--------------|-------------------------------------------------------------|-----------------|---------------------------| -| **Spatz cluster** | | | | | | -|---------------------------|--------------------|--------------|-------------------------------------------------------------|-----------------|---------------------------| -| | msip_i[0] | 1 | (hostd_spatzcl_mb_intr_ored[0] \| safed_spatzcl_intr_mb[0]) | level-sensitive | Snitch core #0 | -| | msip_i[1] | 1 | (hostd_spatzcl_mb_intr_ored[1] \| safed_spatzcl_intr_mb[1]) | level-sensitive | Snitch core #1 | -| | mtip_i[0] | 1 | chs_mti[0] | level-sensitive | Snitch core #0 | -| | mtip_i[1] | 1 | chs_mti[1] | level-sensitive | Snitch core #1 | -| | meip_i | 2 | \- | | unconnected | -| | seip_i | 2 | \- | | unconnected | -|---------------------------|--------------------|--------------|-------------------------------------------------------------|-----------------|---------------------------| -| **HRM integer cluster** | | | | | | -|---------------------------|--------------------|--------------|-------------------------------------------------------------|-----------------|---------------------------| -| eoc_o | | 1 | pulpcl_eoc | level-sensitive | | -| | mbox_irq_i | 1 | (hostd_pulpcl_mb_intr_ored \| safed_pulpcl_intr_mb) | level-sensitive | to offload binaries | -|---------------------------|--------------------|--------------|-------------------------------------------------------------|-----------------|---------------------------| -| **Secure domain** | | | | | | -|---------------------------|--------------------|--------------|-------------------------------------------------------------|-----------------|---------------------------| -| | irq_ibex_i | 1 | (hostd_secd_mb_intr_ored \| safed_secd_intr_mb) | level-sensitive | to wake-up Ibex core | -|---------------------------|--------------------|--------------|-------------------------------------------------------------|-----------------|---------------------------| -| **Safe domain** | | | | | | -|---------------------------|--------------------|--------------|-------------------------------------------------------------|-----------------|---------------------------| -| | irqs_i[0] | 1 | hostd_safed_mbox_intr[0] | level-sensitive | from host domain CVA6#0 | -| | irqs_i[1] | 1 | hostd_safed_mbox_intr[1] | level-sensitive | from host domain CVA6#1 | -| | irqs_i[2] | 1 | secd_safed_mbox_intr | level-sensitive | from secure domain | -| | irqs_i[3] | 1 | pulpcl_safed_mbox_intr | level-sensitive | from HMR custer | -| | irqs_i[4] | 1 | spatzcl_safed_mbox_intr | level-sensitive | from vectorial cluster | -| | irqs[5] | 1 | irqs_distributed_249 | level-sensitive | tied to 0 | -| | irqs[6] | 1 | irqs_distributed_250 | level-sensitive | host domain UART | -| | irqs[7] | 1 | irqs_distributed_251 | level-sensitive | i2c_fmt_threshold | -| | irqs[8] | 1 | irqs_distributed_252 | level-sensitive | i2c_rx_threshold | -| | irqs[9] | 1 | irqs_distributed_253 | level-sensitive | i2c_fmt_overview | -| | irqs[10] | 1 | irqs_distributed_254 | level-sensitive | i2c_rx_overflow | -| | irqs[11] | 1 | irqs_distributed_255 | level-sensitive | i2c_nak | -| | irqs[12] | 1 | irqs_distributed_256 | level-sensitive | i2c_scl_interference | -| | irqs[13] | 1 | irqs_distributed_257 | level-sensitive | i2c_sda_interference | -| | irqs[14] | 1 | irqs_distributed_258 | level-sensitive | i2c_stret h_timeout | -| | irqs[15] | 1 | irqs_distributed_259 | level-sensitive | i2c_sda_unstable | -| | irqs[16] | 1 | irqs_distributed_260 | level-sensitive | i2c_cmd_complete | -| | irqs[17] | 1 | irqs_distributed_261 | level-sensitive | i2c_tx_stretch | -| | irqs[18] | 1 | irqs_distributed_262 | level-sensitive | i2c_tx_overflow | -| | irqs[19] | 1 | irqs_distributed_263 | level-sensitive | i2c_acq_full | -| | irqs[20] | 1 | irqs_distributed_264 | level-sensitive | i2c_unexp_stop | -| | irqs[21] | 1 | irqs_distributed_265 | level-sensitive | i2c_host_timeout | -| | irqs[22] | 1 | irqs_distributed_266 | level-sensitive | spih_error | -| | irqs[23] | 1 | irqs_distributed_267 | level-sensitive | spih_spi_event | -| | irqs[55:24] | 32 | irqs_distributed_299:268 | level-sensitive | gpio | -| | irqs_i[56] | 1 | irqs_distributed_300 | level-sensitive | pulpcl_eoc | -| | irqs_i[57] | 1 | irqs_distributed_309 | level-sensitive | car_wdt_intrs[0] | -| | irqs_i[58] | 1 | irqs_distributed_310 | level-sensitive | car_wdt_intrs[1] | -| | irqs_i[59] | 1 | irqs_distributed_311 | level-sensitive | car_wdt_intrs[2] | -| | irqs_i[60] | 1 | irqs_distributed_312 | level-sensitive | car_wdt_intrs[3] | -| | irqs_i[61] | 1 | irqs_distributed_313 | level-sensitive | car_wdt_intrs[4] | -| | irqs_i[62] | 1 | irqs_distributed_314 | level-sensitive | car_can_intr | -| | irqs_i[63] | 1 | irqs_distributed_315 | edge-sensitive | car_adv_timer_ch0 | -| | irqs_i[64] | 1 | irqs_distributed_316 | edge-sensitive | car_adv_timer_ch1 | -| | irqs_i[65] | 1 | irqs_distributed_317 | edge-sensitive | car_adv_timer_ch2 | -| | irqs_i[66] | 1 | irqs_distributed_318 | edge-sensitive | car_adv_timer_ch3 | -| | irqs_i[67] | 1 | irqs_distributed_319 | edge-sensitive | car_adv_timer_events[0] | -| | irqs_i[68] | 1 | irqs_distributed_320 | edge-sensitive | car_adv_timer_events[1] | -| | irqs_i[69] | 1 | irqs_distributed_321 | edge-sensitive | car_adv_timer_events[2] | -| | irqs_i[70] | 1 | irqs_distributed_322 | edge-sensitive | car_adv_timer_events[0] | -| | irqs_i[71] | 1 | irqs_distributed_323 | edge-sensitive | car_sys_timer_lo | -| | irqs_i[72] | 1 | irqs_distributed_324 | edge-sensitive | car_sys_timer_hi | -| | irqs_i[127:73] | 54 | irqs_distributed_331:325 | - | tied to 0 | -|---------------------------|--------------------|--------------|-------------------------------------------------------------|-----------------|---------------------------| -| **Cheshire** | | | | | | -|---------------------------|--------------------|--------------|-------------------------------------------------------------|-----------------|---------------------------| -| | intr_ext_i[0] | 1 | pulpcl_eoc | level-sensitive | from HMR cluster | -| | intr_ext_i[2:1] | 2 | pulpcl_hostd_mbox_intr | level-sensitive | from HMR cluster | -| | intr_ext_i[4:3] | 2 | spatzcl_hostd_mbox_intr | level-sensitive | from vectorial cluster | -| | intr_ext_i[6:5] | 2 | safed_hostd_mbox_intr | level-sensitive | from safe domain | -| | intr_ext_i[8:7] | 2 | secd_hostd_mbox_intr | level-sensitive | from secure domain | -| | intr_ext_i[9] | 1 | car_wdt_intrs[0] | level-sensitive | from carfield peripherals | -| | intr_ext_i[10] | 1 | car_wdt_intrs[1] | level-sensitive | from carfield peripherals | -| | intr_ext_i[11] | 1 | car_wdt_intrs[2] | level-sensitive | from carfield peripherals | -| | intr_ext_i[12] | 1 | car_wdt_intrs[3] | level-sensitive | from carfield peripherals | -| | intr_ext_i[13] | 1 | car_wdt_intrs[4] | level-sensitive | from carfield peripherals | -| | intr_ext_i[14] | 1 | car_can_intr | level-sensitive | from carfield peripherals | -| | intr_ext_i[15] | 1 | car_adv_timer_ch0 | edge-sensitive | from carfield peripherals | -| | intr_ext_i[16] | 1 | car_adv_timer_ch1 | edge-sensitive | from carfield peripherals | -| | intr_ext_i[17] | 1 | car_adv_timer_ch2 | edge-sensitive | from carfield peripherals | -| | intr_ext_i[18] | 1 | car_adv_timer_ch3 | edge-sensitive | from carfield peripherals | -| | intr_ext_i[19] | 1 | car_adv_timer_events[0] | edge-sensitive | from carfield peripherals | -| | intr_ext_i[20] | 1 | car_adv_timer_events[1] | edge-sensitive | from carfield peripherals | -| | intr_ext_i[21] | 1 | car_adv_timer_events[2] | edge-sensitive | from carfield peripherals | -| | intr_ext_i[22] | 1 | car_adv_timer_events[3] | edge-sensitive | from carfield peripherals | -| | intr_ext_i[23] | 1 | car_sys_timer_lo | edge-sensitive | from carfield peripherals | -| | intr_ext_i[24] | 1 | car_sys_timer_hi | edge-sensitive | from carfield peripherals | -| | intr_ext_i[31:25] | 7 | 0 | | tied to 0 | -| meip_ext_o[0] | | \- | | level-sensitive | unconnected | -| meip_ext_o[1] | | \- | | level-sensitive | unconnected | -| meip_ext_o[2] | | \- | | level-sensitive | unconnected | -| seip_ext_o[0] | | \- | | level-sensitive | unconnected | -| seip_ext_o[1] | | \- | | level-sensitive | unconnected | -| seip_ext_o[2] | | \- | | level-sensitive | unconnected | -| msip_ext_o[0] | | \- | | level-sensitive | unconnected | -| msip_ext_o[1] | | \- | | level-sensitive | unconnected | -| msip_ext_o[2] | | \- | | level-sensitive | unconnected | -| mtip_ext_o[0] | | \- | | level-sensitive | Snitch core #0 | -| mtip_ext_o[1] | | \- | | level-sensitive | Snitch core #1 | -| mtip_ext_o[2] | | \- | | level-sensitive | unconnected | +| **Interrupt Source** | **Interrupt sink** | **Bitwidth** | **Connection** | **Type** | **Comment** | +|-----------------------------|---------------------|--------------|---------------------------------------------------------------|-----------------|---------------------------| +| **Carfield peripherals** | | | | | | +| `intr_wkup_timer_expired_o` | | 1 | `car_wdt_intrs[0] ` | level-sensitive | | +| `intr_wdog_timer_bark_o ` | | 1 | `car_wdt_intrs[1] ` | level-sensitive | | +| `nmi_wdog_timer_bark_o ` | | 1 | `car_wdt_intrs[2] ` | level-sensitive | | +| `wkup_req_o ` | | 1 | `car_wdt_intrs[3] ` | level-sensitive | | +| `aon_timer_rst_req_o ` | | 1 | `car_wdt_intrs[4] ` | level-sensitive | | +| `irq ` | | 1 | `car_can_intr ` | level-sensitive | | +| `ch_0_o[0] ` | | 1 | `car_adv_timer_ch0 ` | edge-sensitive | | +| `ch_0_o[1] ` | | 1 | `car_adv_timer_ch1 ` | edge-sensitive | | +| `ch_0_o[2] ` | | 1 | `car_adv_timer_ch2 ` | edge-sensitive | | +| `ch_0_o[3] ` | | 1 | `car_adv_timer_ch3 ` | edge-sensitive | | +| `events_o[0] ` | | 1 | `car_adv_timer_events[0]` | edge-sensitive | | +| `events_o[1] ` | | 1 | `car_adv_timer_events[1]` | edge-sensitive | | +| `events_o[2] ` | | 1 | `car_adv_timer_events[2]` | edge-sensitive | | +| `events_o[3] ` | | 1 | `car_adv_timer_events[3]` | edge-sensitive | | +| `irq_lo_o ` | | 1 | `car_sys_timer_lo ` | edge-sensitive | | +| `irq_hi_o ` | | 1 | `car_sys_timer_hi ` | edge-sensitive | | +| **Cheshire peripherals** | | | | | | +| `zero ` | | 1 | `zero ` | level-sensitive | | +| `uart ` | | 1 | `uart ` | level-sensitive | | +| `i2c_fmt_threshold ` | | 1 | `i2c_fmt_threshold ` | level-sensitive | | +| `i2c_rx_threshold ` | | 1 | `i2c_rx_threshold ` | level-sensitive | | +| `i2c_fmt_overflow ` | | 1 | `i2c_fmt_overflow ` | level-sensitive | | +| `i2c_rx_overflow ` | | 1 | `i2c_rx_overflow ` | level-sensitive | | +| `i2c_nak ` | | 1 | `i2c_nak ` | level-sensitive | | +| `i2c_scl_interference` | | 1 | `i2c_scl_interference` | level-sensitive | | +| `i2c_sda_interference` | | 1 | `i2c_sda_interference` | level-sensitive | | +| `i2c_stretch_timeout ` | | 1 | `i2c_stretch_timeout ` | level-sensitive | | +| `i2c_sda_unstable ` | | 1 | `i2c_sda_unstable ` | level-sensitive | | +| `i2c_cmd_complete ` | | 1 | `i2c_cmd_complete ` | level-sensitive | | +| `i2c_tx_stretch ` | | 1 | `i2c_tx_stretch ` | level-sensitive | | +| `i2c_tx_overflow ` | | 1 | `i2c_tx_overflow ` | level-sensitive | | +| `i2c_acq_full ` | | 1 | `i2c_acq_full ` | level-sensitive | | +| `i2c_unexp_stop ` | | 1 | `i2c_unexp_stop ` | level-sensitive | | +| `i2c_host_timeout ` | | 1 | `i2c_host_timeout ` | level-sensitive | | +| `spih_error ` | | 1 | `spih_error ` | level-sensitive | | +| `spih_spi_event ` | | 1 | `spih_spi_event ` | level-sensitive | | +| `gpio ` | | 32 | `gpio ` | level-sensitive | | +| **Spatz cluster** | | | | | | +| | `msip_i[0]` | 1 | `(hostd_spatzcl_mb_intr_ored[0] \| safed_spatzcl_intr_mb[0])` | level-sensitive | Snitch core #0 | +| | `msip_i[1]` | 1 | `(hostd_spatzcl_mb_intr_ored[1] \| safed_spatzcl_intr_mb[1])` | level-sensitive | Snitch core #1 | +| | `mtip_i[0]` | 1 | `chs_mti[0] ` | level-sensitive | Snitch core #0 | +| | `mtip_i[1]` | 1 | `chs_mti[1] ` | level-sensitive | Snitch core #1 | +| | `meip_i ` | 2 | `\- ` | | unconnected | +| | `seip_i ` | 2 | `\- ` | | unconnected | +| **HRM integer cluster** | | | | | | +| `eoc_o` | | 1 | `pulpcl_eoc ` | level-sensitive | | +| | `mbox_irq_i` | 1 | `(hostd_pulpcl_mb_intr_ored \| safed_pulpcl_intr_mb)` | level-sensitive | to offload binaries | +| **Secure domain** | | | | | | +| | `irq_ibex_i` | 1 | `(hostd_secd_mb_intr_ored \| safed_secd_intr_mb)` | level-sensitive | to wake-up Ibex core | +| **Safe domain** | | | | | | +| | `irqs_i[0] ` | 1 | `hostd_safed_mbox_intr[0] ` | level-sensitive | from host domain CVA6#0 | +| | `irqs_i[1] ` | 1 | `hostd_safed_mbox_intr[1] ` | level-sensitive | from host domain CVA6#1 | +| | `irqs_i[2] ` | 1 | `secd_safed_mbox_intr ` | level-sensitive | from secure domain | +| | `irqs_i[3] ` | 1 | `pulpcl_safed_mbox_intr ` | level-sensitive | from HMR custer | +| | `irqs_i[4] ` | 1 | `spatzcl_safed_mbox_intr ` | level-sensitive | from vectorial cluster | +| | `irqs[5] ` | 1 | `irqs_distributed_249 ` | level-sensitive | tied to 0 | +| | `irqs[6] ` | 1 | `irqs_distributed_250 ` | level-sensitive | host domain UART | +| | `irqs[7] ` | 1 | `irqs_distributed_251 ` | level-sensitive | i2c_fmt_threshold | +| | `irqs[8] ` | 1 | `irqs_distributed_252 ` | level-sensitive | i2c_rx_threshold | +| | `irqs[9] ` | 1 | `irqs_distributed_253 ` | level-sensitive | i2c_fmt_overview | +| | `irqs[10] ` | 1 | `irqs_distributed_254 ` | level-sensitive | i2c_rx_overflow | +| | `irqs[11] ` | 1 | `irqs_distributed_255 ` | level-sensitive | i2c_nak | +| | `irqs[12] ` | 1 | `irqs_distributed_256 ` | level-sensitive | i2c_scl_interference | +| | `irqs[13] ` | 1 | `irqs_distributed_257 ` | level-sensitive | i2c_sda_interference | +| | `irqs[14] ` | 1 | `irqs_distributed_258 ` | level-sensitive | i2c_stret h_timeout | +| | `irqs[15] ` | 1 | `irqs_distributed_259 ` | level-sensitive | i2c_sda_unstable | +| | `irqs[16] ` | 1 | `irqs_distributed_260 ` | level-sensitive | i2c_cmd_complete | +| | `irqs[17] ` | 1 | `irqs_distributed_261 ` | level-sensitive | i2c_tx_stretch | +| | `irqs[18] ` | 1 | `irqs_distributed_262 ` | level-sensitive | i2c_tx_overflow | +| | `irqs[19] ` | 1 | `irqs_distributed_263 ` | level-sensitive | i2c_acq_full | +| | `irqs[20] ` | 1 | `irqs_distributed_264 ` | level-sensitive | i2c_unexp_stop | +| | `irqs[21] ` | 1 | `irqs_distributed_265 ` | level-sensitive | i2c_host_timeout | +| | `irqs[22] ` | 1 | `irqs_distributed_266 ` | level-sensitive | spih_error | +| | `irqs[23] ` | 1 | `irqs_distributed_267 ` | level-sensitive | spih_spi_event | +| | `irqs[55:24] ` | 32 | `irqs_distributed_299:268 ` | level-sensitive | gpio | +| | `irqs_i[56] ` | 1 | `irqs_distributed_300 ` | level-sensitive | pulpcl_eoc | +| | `irqs_i[57] ` | 1 | `irqs_distributed_309 ` | level-sensitive | car_wdt_intrs[0] | +| | `irqs_i[58] ` | 1 | `irqs_distributed_310 ` | level-sensitive | car_wdt_intrs[1] | +| | `irqs_i[59] ` | 1 | `irqs_distributed_311 ` | level-sensitive | car_wdt_intrs[2] | +| | `irqs_i[60] ` | 1 | `irqs_distributed_312 ` | level-sensitive | car_wdt_intrs[3] | +| | `irqs_i[61] ` | 1 | `irqs_distributed_313 ` | level-sensitive | car_wdt_intrs[4] | +| | `irqs_i[62] ` | 1 | `irqs_distributed_314 ` | level-sensitive | car_can_intr | +| | `irqs_i[63] ` | 1 | `irqs_distributed_315 ` | edge-sensitive | car_adv_timer_ch0 | +| | `irqs_i[64] ` | 1 | `irqs_distributed_316 ` | edge-sensitive | car_adv_timer_ch1 | +| | `irqs_i[65] ` | 1 | `irqs_distributed_317 ` | edge-sensitive | car_adv_timer_ch2 | +| | `irqs_i[66] ` | 1 | `irqs_distributed_318 ` | edge-sensitive | car_adv_timer_ch3 | +| | `irqs_i[67] ` | 1 | `irqs_distributed_319 ` | edge-sensitive | car_adv_timer_events[0] | +| | `irqs_i[68] ` | 1 | `irqs_distributed_320 ` | edge-sensitive | car_adv_timer_events[1] | +| | `irqs_i[69] ` | 1 | `irqs_distributed_321 ` | edge-sensitive | car_adv_timer_events[2] | +| | `irqs_i[70] ` | 1 | `irqs_distributed_322 ` | edge-sensitive | car_adv_timer_events[0] | +| | `irqs_i[71] ` | 1 | `irqs_distributed_323 ` | edge-sensitive | car_sys_timer_lo | +| | `irqs_i[72] ` | 1 | `irqs_distributed_324 ` | edge-sensitive | car_sys_timer_hi | +| | `irqs_i[127:73]` | 54 | `irqs_distributed_331:325 ` | - | tied to 0 | +| **Cheshire** | | | | | | +| | `intr_ext_i[0] ` | 1 | `pulpcl_eoc ` | level-sensitive | from HMR cluster | +| | `intr_ext_i[2:1] ` | 2 | `pulpcl_hostd_mbox_intr ` | level-sensitive | from HMR cluster | +| | `intr_ext_i[4:3] ` | 2 | `spatzcl_hostd_mbox_intr` | level-sensitive | from vectorial cluster | +| | `intr_ext_i[6:5] ` | 2 | `safed_hostd_mbox_intr ` | level-sensitive | from safe domain | +| | `intr_ext_i[8:7] ` | 2 | `secd_hostd_mbox_intr ` | level-sensitive | from secure domain | +| | `intr_ext_i[9] ` | 1 | `car_wdt_intrs[0] ` | level-sensitive | from carfield peripherals | +| | `intr_ext_i[10] ` | 1 | `car_wdt_intrs[1] ` | level-sensitive | from carfield peripherals | +| | `intr_ext_i[11] ` | 1 | `car_wdt_intrs[2] ` | level-sensitive | from carfield peripherals | +| | `intr_ext_i[12] ` | 1 | `car_wdt_intrs[3] ` | level-sensitive | from carfield peripherals | +| | `intr_ext_i[13] ` | 1 | `car_wdt_intrs[4] ` | level-sensitive | from carfield peripherals | +| | `intr_ext_i[14] ` | 1 | `car_can_intr ` | level-sensitive | from carfield peripherals | +| | `intr_ext_i[15] ` | 1 | `car_adv_timer_ch0 ` | edge-sensitive | from carfield peripherals | +| | `intr_ext_i[16] ` | 1 | `car_adv_timer_ch1 ` | edge-sensitive | from carfield peripherals | +| | `intr_ext_i[17] ` | 1 | `car_adv_timer_ch2 ` | edge-sensitive | from carfield peripherals | +| | `intr_ext_i[18] ` | 1 | `car_adv_timer_ch3 ` | edge-sensitive | from carfield peripherals | +| | `intr_ext_i[19] ` | 1 | `car_adv_timer_events[0]` | edge-sensitive | from carfield peripherals | +| | `intr_ext_i[20] ` | 1 | `car_adv_timer_events[1]` | edge-sensitive | from carfield peripherals | +| | `intr_ext_i[21] ` | 1 | `car_adv_timer_events[2]` | edge-sensitive | from carfield peripherals | +| | `intr_ext_i[22] ` | 1 | `car_adv_timer_events[3]` | edge-sensitive | from carfield peripherals | +| | `intr_ext_i[23] ` | 1 | `car_sys_timer_lo ` | edge-sensitive | from carfield peripherals | +| | `intr_ext_i[24] ` | 1 | `car_sys_timer_hi ` | edge-sensitive | from carfield peripherals | +| | `intr_ext_i[31:25]` | 7 | `0 ` | | tied to 0 | +| `meip_ext_o[0]` | | \- | | level-sensitive | unconnected | +| `meip_ext_o[1]` | | \- | | level-sensitive | unconnected | +| `meip_ext_o[2]` | | \- | | level-sensitive | unconnected | +| `seip_ext_o[0]` | | \- | | level-sensitive | unconnected | +| `seip_ext_o[1]` | | \- | | level-sensitive | unconnected | +| `seip_ext_o[2]` | | \- | | level-sensitive | unconnected | +| `msip_ext_o[0]` | | \- | | level-sensitive | unconnected | +| `msip_ext_o[1]` | | \- | | level-sensitive | unconnected | +| `msip_ext_o[2]` | | \- | | level-sensitive | unconnected | +| `mtip_ext_o[0]` | | \- | | level-sensitive | Snitch core #0 | +| `mtip_ext_o[1]` | | \- | | level-sensitive | Snitch core #1 | +| `mtip_ext_o[2]` | | \- | | level-sensitive | unconnected | ## Domains -We divide Carfield domains in two macro groups, the [Computing Domain](#computing-domains) and the -[Memory Domain](#memory-domain). They are both fragmented into smaller domains, described in the -following two sections. +The total number of domains is 7: *host domain*, *safe domain*, *secure domain*, *integer PMCA +domain*, *vectorial PMCA domain*, *peripheral domain*, *dynamic SPM*. -The total number of domains is 7 (**computing**: *host domain*, *safe domain*, *secure domain*, -*integer PMCA domain*, *vectorial PMCA domain*, *peripheral domain*, **memory**: *dynamic SPM -domain*). +Carfield's domains live in dedicated repositories. We therefore invite the reader to consult the +documentation of each domain. ---- - -**Note for the reader** - -Carfield's domains live in dedicated repositories. We invite the reader to consult the documentation -of each domain for more information. Below, we focus on integration parameterization within -Carfield. +For more information about domains' memory requirements, visit [Synthesis and physical +implementation](../tg/synth.md). -### Computing Domain +Below, we focus on domains' parameterization within Carfield. -#### [Host domain (Cheshire)](https://github.com/pulp-platform/cheshire) +### [Host domain (Cheshire)](https://github.com/pulp-platform/cheshire) The *host domain* (Cheshire) embeds all the necessary components required to run OSs such as embedded Linux. It has two orthogonal *operation modes*. @@ -330,8 +308,7 @@ Cheshire is configured as follows: * Two 64-bit, RISC-V CVA6 cores, with lightweight self-invalidation cache coherency, fast interrupt and virtualization support. -layer -* 8 external AXI manager ports added to the matrix crossbar: +* 8 external AXI manager ports (`AxiNumExtSlv`) added to the matrix crossbar: - Dynamic SPM port 0 - Dynamic SPM port 1 - Safe domain @@ -340,28 +317,30 @@ layer - Mailbox unit - Ethernet - Peripherals -* 4 external AXI subordinate ports added to the matrix crossbar: +* 4 external AXI subordinate ports (`AxiNumExtMst`) added to the matrix crossbar: - Safe domain - Secure domain - HMR cluster - Vectorial cluster -* External regbus subordinate ports: +* 4 external regbus subordinate ports (`NumTotalRegSlv`): - PCRs: control domains enable, clock gate, isolation - PLL control registers: for ASIC top-levels, leave unconnected otherwise - Padmux control registers: for ASIC top-levels, leave unconnected otherwise - Dynamic SPM ECC control registers * [AXI-REALM](https://arxiv.org/abs/2311.09662) unit for bandwidth regulation and monitoring integrated in front of each AXI matrix crossbar manager -* Last-level cache with HW spatial partitioning -* 32 external input interrupts (`CarfieldNumExtIntrs`), see [Interrupt map](#interrupt-map). Unused - are tied to 0 (currently 9/32) +* Last-level cache (LLC) with HW spatial partitioning +* 32 *external* input interrupts (`CarfieldNumExtIntrs`), see [Interrupt map](#interrupt-map) in + addition to Cheshire's own internal interrupts. Unused are tied to 0 (currently 9/32) * 2 external interruptible harts (`CarfieldNumInterruptibleHarts`). The interruptible harts are Snitch core \#0 and \#1 in the vectorial cluster. * An interrupt router with 1 external target (`CarfieldNUmRouterTargets`), tasked to distribute N input interrupts to M targets. In Carfield, the external target is the `safe domain`. -* All default Cheshire peripherals, except for VGA +* All Cheshire peripherals, except for VGA -#### [Safe domain](https://github.com/pulp-platform/safety_island) +By default, Cheshire hosts 128KiB of hybrid LLC/SPM, user-configurable. + +### [Safe domain](https://github.com/pulp-platform/safety_island) The *safe domain* is a simple MCU-like domain that comprises three 32-bit real-time CV32E40P (CV32RT) RISC-V cores operating in triple-core-lockstep mode (TCLS). @@ -382,11 +361,15 @@ The *safe domain* is configured as follows: domain* is the same integrated in [Carfield's *peripheral domain*](#peripheral-domain). * CLIC RISC-V interrupt controller; as opposed to Cheshire, currently the CLIC is configured to run run in M-mode. +* 128 *external* input interrupts. Unused are tied to 0. * Fast interrupt extension that extends CV32 with additional logic to accelerate context switching. From here, the name [CV32RT](https://arxiv.org/abs/2311.08320) * 1 32-bit per-core FPU with down to float-16 precision, totaling 3 FPUs -#### [Secure domain](https://github.com/pulp-platform/opentitan/tree/carfield-soc) +By default, the processing elements share access to 128KiB of SPM for instructions and data, +user-configurable. + +### [Secure domain](https://github.com/pulp-platform/opentitan/tree/carfield-soc) The secure domain, based on the [OpenTitan project](https://opentitan.org/book/doc/introduction.html), serves as the Hardware Root-of-Trust @@ -409,20 +392,22 @@ Compared to vanilla OpenTitan, the secure domain integrated in Carfield is modif its content. Otherwise, in **Non-secure** mode, the *secure domain* is clock gated and must be clocked and woken-up by an external entity (e.g., *host domain*) -#### Accelerator domain +By default, the secure domain hosts 512KiB of main SPM, and 16KiB of OTP memory, user-configurable. + +### Accelerator domain To augment computational capabilities, Carfield incorporates two PMCAs, described below. Both PMCAs integrate DMA engines to independently fetch data from the on-chip SPM or external DRAM. -##### [HMR integer PMCA](https://github.com/pulp-platform/pulp_cluster/tree/yt/rapidrecovery) +#### [HMR integer PMCA](https://github.com/pulp-platform/pulp_cluster/tree/yt/rapidrecovery) The [hybrid modular redundancy (HMR) *integer PMCA*](https://arxiv.org/abs/2303.08706) is specialized in accelerating the inference of Deep Learning and Machine Learning models. The multicore accelerator is built around 12 32-bit RISC-V cores empowered with ISA extensions, enabling -integer arithmetic from 32-bit down to 2-bit precision. +integer arithmetic from 32-bit down to 2-bit precision. The integer PMCA does not integrate a fully-fledged FPU co-processor. Nevertheless, it features a -highly specialized domain specific architecture (DSA), +highly specialized domain specific accelerator (DSA), [RedMulE](https://www.sciencedirect.com/science/article/pii/S0167739X23002546), which enables fast and energy-efficient floating-point GEMM on 16-bit and 8-bit data formats. This makes the PMCA capable of on-chip training of generalized Deep Learning models. @@ -444,10 +429,13 @@ The PMCA can be configured in multiple redundant modes: either hardware extension or software mechanisms to recover from incurring faults. The PMCA provides the highest fault resilience in this configuration, at the cost of reduced performance. -##### [Vectorial PMCA](https://github.com/pulp-platform/spatz) +By default, the integer PMCA's processing elements and tensor accelerator share access to 256KiB of +L1 SPM, user-configurable. + +#### [Vectorial PMCA](https://github.com/pulp-platform/spatz) The [*vectorial PMCA*, or Spatz PMCA](https://dl.acm.org/doi/abs/10.1145/3508352.3549367) handles -vectorizable multi-format floating-point workloads. +vectorizable multi-format floating-point workloads. A Spatz vector unit acts as a coprocessor of the [Snitch core](https://github.com/pulp-platform/snitch_cluster), a tiny RV32IMA core which decodes and @@ -463,11 +451,11 @@ PMCA is composed by two CCs, each with the following configuration: Each FPU supports *FP8*, *FP16*, *FP32*, and *FP64* computation, while the IPU supports 8, 16, 32, and 64-bit integer computation. -The CCs share access to 128KB of L1 scratchpad memory divided into 16 SRAM banks. +By default, the CCs share access to 128KiB of L1 SPM, user-configurable. -### Memory Domain +## On-chip and off-chip memory endpoints -#### [Dynamic scratchpad memory (SPM)](https://github.com/pulp-platform/dyn_spm) +### [Dynamic scratchpad memory (SPM)](https://github.com/pulp-platform/dyn_spm) The dynamic SPM features dynamically switching address mapping policy. It manages the following features: @@ -479,23 +467,30 @@ features: * Every address space points to the same physical SRAM through a low-latency matrix crossbar * ECC-equipped memory banks -#### External DRAM +By default, Carfield hosts 1MiB of dynamic SPM, user-configurable. + +### [Partitionable hybrid LLC/SPM](https://github.com/pulp-platform/axi_llc) + +Carfield hosts a LLC optionaly reconfigurable as SPM during runtime. In addition, the LLC supports +HW-based partitioning to exploit intra-process or inter-processes isolation, improving the system's +predictability. The LLC is described in detail in Cheshire's +[Architecture](https://pulp-platform.github.io/cheshire/um/arch). -Carfield integrates a in-house, open-source implementation of Infineon' [HyperBus off-chip -link](https://github.com/pulp-platform/hyperbus) to connect to external HyperRAM modules. +### [HyperBus off-chip link](https://github.com/pulp-platform/hyperbus) -Despite describing it as part of the Memory Domain, the HyperBus is logically part of the -*peripheral domain*. +Carfield integrates a in-house, open-source implementation of Infineon' HyperBus off-chip controller +to connect to external HyperRAM modules. It manages the following features: -* An AXI interface; in Carfield, it attaches to Cheshire's LLC +* An AXI interface that attaches to Cheshire's [partitionable hybrid + LLC/SPM](#partitionable-hybrid-llc-spm) * A configurable number of physical HyperRAM chips it can be attached to; by default, support for 2 physical chips is provided * Support for HyperRAM chips with different densities (from 8MiB to 64MiB per chip aligned with specs). -## Interconnect +## System bus interconnect The interconnect is composed of a main [AXI4](https://github.com/pulp-platform/axi) matrix (or crossbar) with AXI5 atomic operations (ATOPs) support. The crossbar extends Cheshire's with @@ -618,7 +613,7 @@ other devices. | `ETH_MDIO_CLK_DIV_EN` | `0xf4` | `4` | Ethernet MDIO clock divider enable bit | | `ETH_MDIO_CLK_DIV_VALUE` | `0xf8` | `4` | Ethernet MDIO clock divider value | -## Peripheral Domain +## Peripherals Carfield enhances Cheshire's peripheral subsystem with additional capabilities. diff --git a/mkdocs.yml b/mkdocs.yml index 42a271958..30a63cd05 100644 --- a/mkdocs.yml +++ b/mkdocs.yml @@ -14,6 +14,21 @@ theme: - navigation.indexes - navigation.footer +plugins: + - glightbox: + touchNavigation: true + loop: false + effect: zoom + slide_effect: slide + width: 100% + height: auto + zoomable: true + draggable: true + skip_classes: + - custom-skip-class-name + auto_caption: false + caption_position: bottom + repo_url: https://github.com/pulp-platform/carfield repo_name: pulp-platform/carfield @@ -24,7 +39,7 @@ nav: - Targets: - tg/index.md - Simulation: tg/sim.md - - Synthesis: tg/synth.md + - Synthesis and physical implementation: tg/synth.md - Xilinx FPGAs: tg/xilinx.md - Integration: tg/integr.md - User Manual: