From 3f67a481f28f49712e133857b21c5e843c92db07 Mon Sep 17 00:00:00 2001 From: "Amir Kiamarzi amirhossein.kiamarz2@unibo.it" Date: Mon, 23 Dec 2024 12:24:21 +0100 Subject: [PATCH] Add support for ZCU102 --- hw/carfield_pkg.sv | 6 +- target/sim/vsim/logs/trace_hart_00010.dasm | 12 +++ target/sim/vsim/logs/trace_hart_00011.dasm | 12 +++ target/sim/vsim/uart | 0 .../flavor_vanilla/constraints/zcu102.xdc | 73 ++++++++++++++----- .../xilinx/flavor_vanilla/flavor_vanilla.mk | 1 + target/xilinx/flavor_vanilla/scripts/run.tcl | 10 +++ .../flavor_vanilla/src/phy_definitions.svh | 2 +- target/xilinx/xilinx.mk | 5 ++ 9 files changed, 97 insertions(+), 24 deletions(-) create mode 100644 target/sim/vsim/logs/trace_hart_00010.dasm create mode 100644 target/sim/vsim/logs/trace_hart_00011.dasm create mode 100644 target/sim/vsim/uart diff --git a/hw/carfield_pkg.sv b/hw/carfield_pkg.sv index d3701bdd..c0856254 100644 --- a/hw/carfield_pkg.sv +++ b/hw/carfield_pkg.sv @@ -519,7 +519,7 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{ // [0x7000_0000, 0x8000_0000) is CIE Cva6ExtCieOnTop : 1, // Harts - NumCores : 2, + NumCores : 1, CoreMaxTxns : 8, CoreMaxTxnsPerId : 4, CoreUserAmoOffs : 0, // Convention: lower AMO bits for cores, MSB for serial link @@ -572,8 +572,8 @@ localparam cheshire_cfg_t CarfieldCfgDefault = '{ // Features Bootrom : 1, Uart : 1, - I2c : 1, - SpiHost : 1, + I2c : 0, + SpiHost : 0, Gpio : 1, Dma : 1, SerialLink : 1, diff --git a/target/sim/vsim/logs/trace_hart_00010.dasm b/target/sim/vsim/logs/trace_hart_00010.dasm new file mode 100644 index 00000000..f084b911 --- /dev/null +++ b/target/sim/vsim/logs/trace_hart_00010.dasm @@ -0,0 +1,12 @@ + 557020ns x 3 0x00001000 DASM(00000317) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0x0, 'rs2': 0x0, 'rd': 0x6, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1004, 'opa': 0x0, 'opb': 0x1000, 'opa_select': 0x3, 'opb_select': 0x7, 'write_rd': 0x1, 'csr_addr': 0x0, 'writeback': 0x1000, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x0, 'lsu_rd': 0x0, 'retire_load': 0x0, 'alu_result': 0x1000, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 557180ns x 3 0x00001004 DASM(07832303) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0x6, 'rs2': 0x18, 'rd': 0x6, 'is_load': 0x1, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1008, 'opa': 0x1000, 'opb': 0x78, 'opa_select': 0x1, 'opb_select': 0x2, 'write_rd': 0x0, 'csr_addr': 0x78, 'writeback': 0x1078, 'gpr_rdata_1': 0x0, 'ls_size': 0x2, 'ld_result_32': 0x0, 'lsu_rd': 0x0, 'retire_load': 0x0, 'alu_result': 0x1078, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 557400ns x 3 0x00001008 DASM(30531073) #; {'source': 0x0, 'stall': 0x1, 'exception': 0x0, 'rs1': 0x6, 'rs2': 0x5, 'rd': 0x0, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1008, 'opa': 0x1000, 'opb': 0x0, 'opa_select': 0x1, 'opb_select': 0x0, 'write_rd': 0x1, 'csr_addr': 0x305, 'writeback': 0x1000, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x1044, 'lsu_rd': 0x6, 'retire_load': 0x1, 'alu_result': 0x1000, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 557540ns x 3 0x00001008 DASM(30531073) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0x6, 'rs2': 0x5, 'rd': 0x0, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x100c, 'opa': 0x1044, 'opb': 0x0, 'opa_select': 0x1, 'opb_select': 0x0, 'write_rd': 0x1, 'csr_addr': 0x305, 'writeback': 0x1044, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x0, 'lsu_rd': 0x6, 'retire_load': 0x0, 'alu_result': 0x1044, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 557740ns x 3 0x0000100c DASM(f1402573) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0x0, 'rs2': 0x14, 'rd': 0xa, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1010, 'opa': 0x0, 'opb': 0x10, 'opa_select': 0x1, 'opb_select': 0x8, 'write_rd': 0x1, 'csr_addr': 0xf14, 'writeback': 0x10, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x0, 'lsu_rd': 0x6, 'retire_load': 0x0, 'alu_result': 0x10, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 557900ns x 3 0x00001010 DASM(00000597) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0x0, 'rs2': 0x0, 'rd': 0xb, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1014, 'opa': 0x0, 'opb': 0x1010, 'opa_select': 0x3, 'opb_select': 0x7, 'write_rd': 0x1, 'csr_addr': 0x0, 'writeback': 0x1010, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x0, 'lsu_rd': 0x6, 'retire_load': 0x0, 'alu_result': 0x1010, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 558060ns x 3 0x00001014 DASM(06c5a583) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0xb, 'rs2': 0xc, 'rd': 0xb, 'is_load': 0x1, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1018, 'opa': 0x1010, 'opb': 0x6c, 'opa_select': 0x1, 'opb_select': 0x2, 'write_rd': 0x0, 'csr_addr': 0x6c, 'writeback': 0x107c, 'gpr_rdata_1': 0x0, 'ls_size': 0x2, 'ld_result_32': 0x0, 'lsu_rd': 0x6, 'retire_load': 0x0, 'alu_result': 0x107c, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 558220ns x 3 0x00001018 DASM(30402673) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0x0, 'rs2': 0x4, 'rd': 0xc, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x101c, 'opa': 0x0, 'opb': 0x0, 'opa_select': 0x1, 'opb_select': 0x8, 'write_rd': 0x1, 'csr_addr': 0x304, 'writeback': 0x0, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x0, 'lsu_rd': 0xb, 'retire_load': 0x0, 'alu_result': 0x0, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 558280ns x 3 0x0000101c DASM(30402673) #; {'source': 0x0, 'stall': 0x1, 'exception': 0x0, 'rs1': 0x0, 'rs2': 0x4, 'rd': 0xc, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x101c, 'opa': 0x0, 'opb': 0x0, 'opa_select': 0x1, 'opb_select': 0x8, 'write_rd': 0x1, 'csr_addr': 0x304, 'writeback': 0x0, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x1048, 'lsu_rd': 0xb, 'retire_load': 0x1, 'alu_result': 0x0, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 558420ns x 3 0x0000101c DASM(00866613) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0xc, 'rs2': 0x8, 'rd': 0xc, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1020, 'opa': 0x0, 'opb': 0x8, 'opa_select': 0x1, 'opb_select': 0x2, 'write_rd': 0x1, 'csr_addr': 0x8, 'writeback': 0x8, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x1048, 'lsu_rd': 0xb, 'retire_load': 0x0, 'alu_result': 0x8, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 558620ns x 3 0x00001020 DASM(30461073) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0xc, 'rs2': 0x4, 'rd': 0x0, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1024, 'opa': 0x8, 'opb': 0x0, 'opa_select': 0x1, 'opb_select': 0x0, 'write_rd': 0x1, 'csr_addr': 0x304, 'writeback': 0x0, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x1048, 'lsu_rd': 0xb, 'retire_load': 0x0, 'alu_result': 0x8, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 558780ns x 3 0x00001024 DASM(10500073) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0x0, 'rs2': 0x5, 'rd': 0x0, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1028, 'opa': 0x0, 'opb': 0x0, 'opa_select': 0x0, 'opb_select': 0x0, 'write_rd': 0x1, 'csr_addr': 0x105, 'writeback': 0x0, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x1048, 'lsu_rd': 0xb, 'retire_load': 0x0, 'alu_result': 0x0, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } diff --git a/target/sim/vsim/logs/trace_hart_00011.dasm b/target/sim/vsim/logs/trace_hart_00011.dasm new file mode 100644 index 00000000..02364820 --- /dev/null +++ b/target/sim/vsim/logs/trace_hart_00011.dasm @@ -0,0 +1,12 @@ + 557100ns x 3 0x00001000 DASM(00000317) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0x0, 'rs2': 0x0, 'rd': 0x6, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1004, 'opa': 0x0, 'opb': 0x1000, 'opa_select': 0x3, 'opb_select': 0x7, 'write_rd': 0x1, 'csr_addr': 0x0, 'writeback': 0x1000, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x0, 'lsu_rd': 0x0, 'retire_load': 0x0, 'alu_result': 0x1000, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 557260ns x 3 0x00001004 DASM(07832303) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0x6, 'rs2': 0x18, 'rd': 0x6, 'is_load': 0x1, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1008, 'opa': 0x1000, 'opb': 0x78, 'opa_select': 0x1, 'opb_select': 0x2, 'write_rd': 0x0, 'csr_addr': 0x78, 'writeback': 0x1078, 'gpr_rdata_1': 0x0, 'ls_size': 0x2, 'ld_result_32': 0x0, 'lsu_rd': 0x0, 'retire_load': 0x0, 'alu_result': 0x1078, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 557600ns x 3 0x00001008 DASM(30531073) #; {'source': 0x0, 'stall': 0x1, 'exception': 0x0, 'rs1': 0x6, 'rs2': 0x5, 'rd': 0x0, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1008, 'opa': 0x1000, 'opb': 0x0, 'opa_select': 0x1, 'opb_select': 0x0, 'write_rd': 0x1, 'csr_addr': 0x305, 'writeback': 0x1000, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x1044, 'lsu_rd': 0x6, 'retire_load': 0x1, 'alu_result': 0x1000, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 557660ns x 3 0x00001008 DASM(30531073) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0x6, 'rs2': 0x5, 'rd': 0x0, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x100c, 'opa': 0x1044, 'opb': 0x0, 'opa_select': 0x1, 'opb_select': 0x0, 'write_rd': 0x1, 'csr_addr': 0x305, 'writeback': 0x1044, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x0, 'lsu_rd': 0x6, 'retire_load': 0x0, 'alu_result': 0x1044, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 557820ns x 3 0x0000100c DASM(f1402573) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0x0, 'rs2': 0x14, 'rd': 0xa, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1010, 'opa': 0x0, 'opb': 0x11, 'opa_select': 0x1, 'opb_select': 0x8, 'write_rd': 0x1, 'csr_addr': 0xf14, 'writeback': 0x11, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x0, 'lsu_rd': 0x6, 'retire_load': 0x0, 'alu_result': 0x11, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 557980ns x 3 0x00001010 DASM(00000597) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0x0, 'rs2': 0x0, 'rd': 0xb, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1014, 'opa': 0x0, 'opb': 0x1010, 'opa_select': 0x3, 'opb_select': 0x7, 'write_rd': 0x1, 'csr_addr': 0x0, 'writeback': 0x1010, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x0, 'lsu_rd': 0x6, 'retire_load': 0x0, 'alu_result': 0x1010, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 558140ns x 3 0x00001014 DASM(06c5a583) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0xb, 'rs2': 0xc, 'rd': 0xb, 'is_load': 0x1, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1018, 'opa': 0x1010, 'opb': 0x6c, 'opa_select': 0x1, 'opb_select': 0x2, 'write_rd': 0x0, 'csr_addr': 0x6c, 'writeback': 0x107c, 'gpr_rdata_1': 0x0, 'ls_size': 0x2, 'ld_result_32': 0x0, 'lsu_rd': 0x6, 'retire_load': 0x0, 'alu_result': 0x107c, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 558340ns x 3 0x00001018 DASM(30402673) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0x0, 'rs2': 0x4, 'rd': 0xc, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x101c, 'opa': 0x0, 'opb': 0x0, 'opa_select': 0x1, 'opb_select': 0x8, 'write_rd': 0x1, 'csr_addr': 0x304, 'writeback': 0x0, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x0, 'lsu_rd': 0xb, 'retire_load': 0x0, 'alu_result': 0x0, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 558480ns x 3 0x0000101c DASM(30402673) #; {'source': 0x0, 'stall': 0x1, 'exception': 0x0, 'rs1': 0x0, 'rs2': 0x4, 'rd': 0xc, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x101c, 'opa': 0x0, 'opb': 0x0, 'opa_select': 0x1, 'opb_select': 0x8, 'write_rd': 0x1, 'csr_addr': 0x304, 'writeback': 0x0, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x1048, 'lsu_rd': 0xb, 'retire_load': 0x1, 'alu_result': 0x0, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 558540ns x 3 0x0000101c DASM(00866613) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0xc, 'rs2': 0x8, 'rd': 0xc, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1020, 'opa': 0x0, 'opb': 0x8, 'opa_select': 0x1, 'opb_select': 0x2, 'write_rd': 0x1, 'csr_addr': 0x8, 'writeback': 0x8, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x1048, 'lsu_rd': 0xb, 'retire_load': 0x0, 'alu_result': 0x8, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 558700ns x 3 0x00001020 DASM(30461073) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0xc, 'rs2': 0x4, 'rd': 0x0, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1024, 'opa': 0x8, 'opb': 0x0, 'opa_select': 0x1, 'opb_select': 0x0, 'write_rd': 0x1, 'csr_addr': 0x304, 'writeback': 0x0, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x1048, 'lsu_rd': 0xb, 'retire_load': 0x0, 'alu_result': 0x8, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } + 558860ns x 3 0x00001024 DASM(10500073) #; {'source': 0x0, 'stall': 0x0, 'exception': 0x0, 'rs1': 0x0, 'rs2': 0x5, 'rd': 0x0, 'is_load': 0x0, 'is_store': 0x0, 'is_branch': 0x0, 'pc_d': 0x1028, 'opa': 0x0, 'opb': 0x0, 'opa_select': 0x0, 'opb_select': 0x0, 'write_rd': 0x1, 'csr_addr': 0x105, 'writeback': 0x0, 'gpr_rdata_1': 0x0, 'ls_size': 0x0, 'ld_result_32': 0x1048, 'lsu_rd': 0xb, 'retire_load': 0x0, 'alu_result': 0x0, 'ls_amo': 0x0, 'retire_acc': 0x0, 'acc_pid': 0x0, 'acc_pdata_32': 0x0, 'fpu_offload': 0x0, 'is_seq_insn': 0x0, } diff --git a/target/sim/vsim/uart b/target/sim/vsim/uart new file mode 100644 index 00000000..e69de29b diff --git a/target/xilinx/flavor_vanilla/constraints/zcu102.xdc b/target/xilinx/flavor_vanilla/constraints/zcu102.xdc index c27d0f18..2ddbf110 100644 --- a/target/xilinx/flavor_vanilla/constraints/zcu102.xdc +++ b/target/xilinx/flavor_vanilla/constraints/zcu102.xdc @@ -96,10 +96,18 @@ set_clock_latency [expr ${rwds_input_delay}] clk_rwds_sample0 #set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C0_SCL_LS"] ;# Bank 50 VCCO - VCC3V3 - IO_L1N_AD15N_50 #set_property PACKAGE_PIN J11 [get_ports "PL_I2C0_SDA_LS"] ;# Bank 50 VCCO - VCC3V3 - IO_L1P_AD15P_50 #set_property IOSTANDARD LVCMOS33 [get_ports "PL_I2C0_SDA_LS"] ;# Bank 50 VCCO - VCC3V3 - IO_L1P_AD15P_50 -set_property PACKAGE_PIN E13 [get_ports "uart_tx_o"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 -set_property IOSTANDARD LVCMOS33 [get_ports "uart_tx_o"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 -set_property PACKAGE_PIN F13 [get_ports "uart_rx_i"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 -set_property IOSTANDARD LVCMOS33 [get_ports "uart_rx_i"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 + +#******************************************************************************************************* +# set_property PACKAGE_PIN E13 [get_ports "uart_tx_o"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 +# set_property IOSTANDARD LVCMOS33 [get_ports "uart_tx_o"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 +# set_property PACKAGE_PIN F13 [get_ports "uart_rx_i"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 +# set_property IOSTANDARD LVCMOS33 [get_ports "uart_rx_i"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 +#******************************************************************************************************* +set_property PACKAGE_PIN E13 [get_ports "uart_rx_i"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 +set_property IOSTANDARD LVCMOS33 [get_ports "uart_rx_i"] ;# Bank 49 VCCO - VCC3V3 - IO_L12N_AD8N_49 +set_property PACKAGE_PIN F13 [get_ports "uart_tx_o"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 +set_property IOSTANDARD LVCMOS33 [get_ports "uart_tx_o"] ;# Bank 49 VCCO - VCC3V3 - IO_L12P_AD8P_49 +#******************************************************************************************************* #set_property PACKAGE_PIN D12 [get_ports "UART2_RTS_O_B"] ;# Bank 49 VCCO - VCC3V3 - IO_L11N_AD9N_49 #set_property IOSTANDARD LVCMOS33 [get_ports "UART2_RTS_O_B"] ;# Bank 49 VCCO - VCC3V3 - IO_L11N_AD9N_49 #set_property PACKAGE_PIN E12 [get_ports "UART2_CTS_I_B"] ;# Bank 49 VCCO - VCC3V3 - IO_L11P_AD9P_49 @@ -192,14 +200,16 @@ set_property IOSTANDARD LVCMOS33 [get_ports "uart_rx_i"] ;# Bank 49 VCCO - VCC #set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA4"] ;# Bank 48 VCCO - VCC3V3 - IO_L1N_AD15N_48 #set_property PACKAGE_PIN H18 [get_ports "TRACEDATA3"] ;# Bank 48 VCCO - VCC3V3 - IO_L1P_AD15P_48 #set_property IOSTANDARD LVCMOS33 [get_ports "TRACEDATA3"] ;# Bank 48 VCCO - VCC3V3 - IO_L1P_AD15P_48 -#set_property PACKAGE_PIN A20 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 -#set_property PACKAGE_PIN B20 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 -#set_property PACKAGE_PIN A22 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47 -#set_property PACKAGE_PIN A21 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47 -#set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47 +#********************************************************************************************************** +set_property PACKAGE_PIN A20 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 +set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12N_AD0N_47 +set_property PACKAGE_PIN B20 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 +set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L12P_AD0P_47 +set_property PACKAGE_PIN A22 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47 +set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L11N_AD1N_47 +set_property PACKAGE_PIN A21 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47 +set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L11P_AD1P_47 +#********************************************************************************************************** #set_property PACKAGE_PIN B21 [get_ports "PMOD0_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L10N_AD2N_47 #set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L10N_AD2N_47 #set_property PACKAGE_PIN C21 [get_ports "PMOD0_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L10P_AD2P_47 @@ -208,14 +218,16 @@ set_property IOSTANDARD LVCMOS33 [get_ports "uart_rx_i"] ;# Bank 49 VCCO - VCC #set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_6"] ;# Bank 47 VCCO - VCC3V3 - IO_L9N_AD3N_47 #set_property PACKAGE_PIN D21 [get_ports "PMOD0_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L9P_AD3P_47 #set_property IOSTANDARD LVCMOS33 [get_ports "PMOD0_7"] ;# Bank 47 VCCO - VCC3V3 - IO_L9P_AD3P_47 -set_property PACKAGE_PIN D20 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47 -set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47 -set_property PACKAGE_PIN E20 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47 -set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47 -set_property PACKAGE_PIN D22 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47 -set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47 -set_property PACKAGE_PIN E22 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_47 -set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_47 +#********************************************************************************************************** +# set_property PACKAGE_PIN D20 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47 +# set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tms_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8N_HDGC_AD4N_47 +# set_property PACKAGE_PIN E20 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47 +# set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdi_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L8P_HDGC_AD4P_47 +# set_property PACKAGE_PIN D22 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47 +# set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tdo_o"] ;# Bank 47 VCCO - VCC3V3 - IO_L7N_HDGC_AD5N_47 +# set_property PACKAGE_PIN E22 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_47 +# set_property IOSTANDARD LVCMOS33 [get_ports "jtag_tck_i"] ;# Bank 47 VCCO - VCC3V3 - IO_L7P_HDGC_AD5P_47 +#********************************************************************************************************** #set_property PACKAGE_PIN F20 [get_ports "PMOD1_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_47 #set_property IOSTANDARD LVCMOS33 [get_ports "PMOD1_4"] ;# Bank 47 VCCO - VCC3V3 - IO_L6N_HDGC_AD6N_47 #set_property PACKAGE_PIN G20 [get_ports "PMOD1_5"] ;# Bank 47 VCCO - VCC3V3 - IO_L6P_HDGC_AD6P_47 @@ -1094,3 +1106,24 @@ set_property IOSTANDARD LVCMOS18 [get_ports "pad_hyper_dq[0][4]"] ;# Bank 66 V #Other net PACKAGE_PIN U32 - GTR_REF_CLK_DP_C_N Bank 505 - PS_MGTREFCLK3N_505 #Other net PACKAGE_PIN U31 - GTR_REF_CLK_DP_C_P Bank 505 - PS_MGTREFCLK3P_505 #Other net PACKAGE_PIN AB28 - 69N5804 Bank 505 - PS_MGTRREF_505 +############################################################################################################## +# set_property BOARD_PART_PIN default_100mhz_clk_n [get_ports sys_clk_n] +# set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_n] +# set_property BOARD_PART_PIN default_100mhz_clk_p [get_ports sys_clk_p] +# set_property IOSTANDARD DIFF_SSTL12 [get_ports sys_clk_p] +# set_property PACKAGE_PIN G21 [get_ports sys_clk_p] +# set_property PACKAGE_PIN F21 [get_ports sys_clk_n] + +#set_property PACKAGE_PIN AN7 [get_ports "DDR4_CK_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L10P_T1U_N6_QBC_AD4P_64 +#set_property IOSTANDARD DIFF_SSTL12 [get_ports "DDR4_CK_T"] ;# Bank 64 VCCO - VCC1V2 - IO_L10P_T1U_N6_QBC_AD4P_64 + +set_property PACKAGE_PIN AL7 [get_ports "sys_clk_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 +set_property IOSTANDARD DIFF_SSTL12 [get_ports "sys_clk_n"] ;# Bank 47 VCCO - VCC3V3 - IO_L5N_HDGC_AD7N_47 + +set_property PACKAGE_PIN AL8 [get_ports "sys_clk_p"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 +set_property IOSTANDARD DIFF_SSTL12 [get_ports "sys_clk_p"] ;# Bank 47 VCCO - VCC3V3 - IO_L5P_HDGC_AD7P_47 + + + +# set_property -dict {PACKAGE_PIN F21 IOSTANDARD LVDS_25} [get_ports sys_clk_n] +# set_property -dict {PACKAGE_PIN G21 IOSTANDARD LVDS_25} [get_ports sys_clk_p] \ No newline at end of file diff --git a/target/xilinx/flavor_vanilla/flavor_vanilla.mk b/target/xilinx/flavor_vanilla/flavor_vanilla.mk index ecbf97af..54ac7b05 100644 --- a/target/xilinx/flavor_vanilla/flavor_vanilla.mk +++ b/target/xilinx/flavor_vanilla/flavor_vanilla.mk @@ -9,6 +9,7 @@ xilinx_bit_vanilla := $(CAR_XIL_DIR)/flavor_vanilla/out/carfield_top_xilinx.bit # This flavor requires pre-compiled Xilinx IPs (which may depend on the board) xilinx_ips_names_vanilla_vcu128 := xlnx_mig_ddr4 xlnx_clk_wiz xlnx_vio +xilinx_ips_names_vanilla_zcu102 := xlnx_mig_ddr4 xlnx_clk_wiz xlnx_vio xilinx_ips_names_vanilla := $(xilinx_ips_names_vanilla_${XILINX_BOARD}) # Path to compiled ips xilinx_ips_paths_vanilla = $(foreach ip-name,$(xilinx_ips_names_vanilla),$(xilinx_ip_dir)/$(ip-name)/$(ip-name).srcs/sources_1/ip/$(ip-name)/$(ip-name).xci) diff --git a/target/xilinx/flavor_vanilla/scripts/run.tcl b/target/xilinx/flavor_vanilla/scripts/run.tcl index c14efe8e..91eb1157 100644 --- a/target/xilinx/flavor_vanilla/scripts/run.tcl +++ b/target/xilinx/flavor_vanilla/scripts/run.tcl @@ -24,6 +24,16 @@ switch $::env(XILINX_BOARD) { set_property SCOPED_TO_REF carfield [get_files carfield.xdc] set_property processing_order LATE [get_files carfield.xdc] } + "zcu102" { + import_files -fileset constrs_1 -norecurse constraints/$::env(XILINX_BOARD).xdc + import_files -fileset constrs_1 -norecurse constraints/carfield_top_xilinx.xdc + # General constraints + import_files -fileset constrs_1 -norecurse ../constraints/carfield_islands.tcl + # Make sure carfield.xdc executes after carfield_islands.tcl (that generates the clocks) + import_files -fileset constrs_1 -norecurse ../constraints/carfield.xdc + set_property SCOPED_TO_REF carfield [get_files carfield.xdc] + set_property processing_order LATE [get_files carfield.xdc] + } default { exit 1 } diff --git a/target/xilinx/flavor_vanilla/src/phy_definitions.svh b/target/xilinx/flavor_vanilla/src/phy_definitions.svh index 98ad955a..2863521c 100644 --- a/target/xilinx/flavor_vanilla/src/phy_definitions.svh +++ b/target/xilinx/flavor_vanilla/src/phy_definitions.svh @@ -24,7 +24,7 @@ `define HypNumChips 1 `define HypNumPhys 1 `ifdef GEN_NO_HYPERBUS - `define USE_DDR4 + // `define USE_DDR4 `endif `define USE_VIO `endif diff --git a/target/xilinx/xilinx.mk b/target/xilinx/xilinx.mk index 14fb4347..be27ee23 100644 --- a/target/xilinx/xilinx.mk +++ b/target/xilinx/xilinx.mk @@ -28,6 +28,11 @@ ifeq ($(XILINX_BOARD),vcu128) xilinx_board_long := xilinx.com:vcu128:part0:1.0 endif +ifeq ($(XILINX_BOARD),zcu102) + xilinx_part := xczu9eg-ffvb1156-2-e + xilinx_board_long := xilinx.com:zcu102:part0:3.4 +endif + XILINX_USE_ARTIFACTS ?= 0 XILINX_ARTIFACTS_ROOT ?= XILINX_ELABORATION_ONLY ?= 0