diff --git a/hw/carfield.sv b/hw/carfield.sv index 9ca24327..2740ca89 100644 --- a/hw/carfield.sv +++ b/hw/carfield.sv @@ -1199,8 +1199,12 @@ hyperbus_wrap #( // Temporary Mailbox parameters (evaluate if we can move everything here). // The best approach would be to move all these parameters to the package. -localparam int unsigned HostdMboxOffset = (spatz_cluster_pkg::NumCores + spatz_cluster_pkg::NumCores * CheshireNumIntHarts); -localparam int unsigned SpatzMboxOffset = HostdMboxOffset + 3*CheshireNumIntHarts; +localparam int unsigned HostdMboxOffset = (spatz_cluster_pkg::NumCores + + (spatz_cluster_pkg::NumCores * + CheshireNumIntHarts ) + ); +localparam int unsigned SpatzMboxOffset = HostdMboxOffset + + 3*CheshireNumIntHarts; // Reconfigurable L2 Memory // Host Clock Domain @@ -1298,7 +1302,6 @@ end // Collect interrupts for the safety island: private interrupts from mailboxes, shared interrupts // from the interrupt router. -// verilog_lint: waive-start line-length assign safed_intrs = { {(SafetyIslandCfg.NumInterrupts-(NumIntIntrs+CarfieldNumExtIntrs+NumMailboxesSafed)){1'b0}}, // Pad remaining interrupts // Shared interrupts (cheshire and carfield's peripherals interrupts) @@ -1581,8 +1584,7 @@ if (CarfieldIslandsCfg.pulp.enable) begin : gen_pulp_cluster .async_data_master_b_wptr_i ( axi_mst_intcluster_b_wptr ), .async_data_master_b_rptr_o ( axi_mst_intcluster_b_rptr ) ); - end - else begin : gen_no_pulp_cluster + end else begin : gen_no_pulp_cluster cdc_dst_axi_err #( .AxiInIdWidth ( IntClusterAxiIdInWidth ), .LogDepth ( LogDepth ), @@ -1594,14 +1596,24 @@ if (CarfieldIslandsCfg.pulp.enable) begin : gen_pulp_cluster .axi_in_r_chan_t ( axi_intcluster_slv_r_chan_t ), .axi_in_resp_t ( axi_intcluster_slv_rsp_t ), .axi_in_req_t ( axi_intcluster_slv_req_t ), - .AsyncAxiInAwWidth ( (2**LogDepth)*axi_pkg::aw_width(Cfg.AddrWidth,IntClusterAxiIdInWidth, - Cfg.AxiUserWidth)), - .AsyncAxiInWWidth ( (2**LogDepth)*axi_pkg::w_width(Cfg.AxiDataWidth,Cfg.AxiUserWidth) ), - .AsyncAxiInBWidth ( (2**LogDepth)*axi_pkg::b_width(IntClusterAxiIdInWidth,Cfg.AxiUserWidth) ), - .AsyncAxiInArWidth ( (2**LogDepth)*axi_pkg::ar_width(Cfg.AddrWidth,IntClusterAxiIdInWidth, - Cfg.AxiUserWidth)), - .AsyncAxiInRWidth ( (2**LogDepth)*axi_pkg::r_width(Cfg.AxiDataWidth,IntClusterAxiIdInWidth, - Cfg.AxiUserWidth)) + .AsyncAxiInAwWidth ( (2**LogDepth)* + axi_pkg::aw_width(Cfg.AddrWidth, + IntClusterAxiIdInWidth, + Cfg.AxiUserWidth)), + .AsyncAxiInWWidth ( (2**LogDepth)* + axi_pkg::w_width(Cfg.AxiDataWidth, + Cfg.AxiUserWidth) ), + .AsyncAxiInBWidth ( (2**LogDepth)* + axi_pkg::b_width(IntClusterAxiIdInWidth, + Cfg.AxiUserWidth) ), + .AsyncAxiInArWidth ( (2**LogDepth)* + axi_pkg::ar_width(Cfg.AddrWidth, + IntClusterAxiIdInWidth, + Cfg.AxiUserWidth)), + .AsyncAxiInRWidth ( (2**LogDepth)* + axi_pkg::r_width(Cfg.AxiDataWidth, + IntClusterAxiIdInWidth, + Cfg.AxiUserWidth)) ) i_pulp_cluster_axi_err ( .clk_i ( pulp_clk ), .rst_ni ( pulp_rst_n ), @@ -1761,7 +1773,7 @@ if (CarfieldIslandsCfg.spatz.enable) begin : gen_spatz_cluster // For the spatz FP cluster SW interrupt in machine mode (msi), OR together interrupts coming from the // host domain and the safe domain assign spatzcl_mbox_intr = hostd_spatzcl_mbox_intr_ored | safed_spatzcl_mbox_intr; - + // verilog_lint: waive-stop line-length end else begin : gen_no_spatz_cluster assign spatzcl_mbox_intr = '0; assign spatzcl_timer_intr = '0; @@ -2176,13 +2188,17 @@ if (carfield_pkg::IslandsCfgDefault.EnEthernet) begin : gen_ethernet .AXI_USER_WIDTH ( Cfg.AxiUserWidth ) ) i_eth_rgmii ( .clk_i ( eth_mdio_clk ), - .clk_200MHz_i ( '0 ), // Only used with FPGA mapping for genesysII in IDELAYCTRL cell's - // ref clk (see IP) + /* Clock 200MHz */ + // Only used with FPGA mapping for genesysII + // in IDELAYCTRL cell's ref clk (see IP) + .clk_200MHz_i ( '0 ), .rst_ni ( periph_rst_n ), - .eth_clk_i ( '0 ), // quadrature (90deg) clk to `phy_tx_clk_i` -> disabled when `USE_CLK90 == - // FALSE` in ethernet IP. See `eth_mac_1g_rgmii_fifo`. In carfieldv1, - // USE_CLK90 == 0, hence changing the clock phase is left to PHY chips on - // the PCB. + /* Ethernet Clock */ + // Quadrature (90deg) clk to `phy_tx_clk_i` -> disabled when + // `USE_CLK90 == FALSE` in ethernet IP. See `eth_mac_1g_rgmii_fifo`. + // In carfieldv1, USE_CLK90 == 0, hence changing the clock phase + // is left to PHY chips on the PCB. + .eth_clk_i ( '0 ), .ethernet ( axi_ethernet ), diff --git a/hw/carfield_cfg_pkg.sv b/hw/carfield_cfg_pkg.sv index 4fab03ee..5bc93220 100644 --- a/hw/carfield_cfg_pkg.sv +++ b/hw/carfield_cfg_pkg.sv @@ -120,14 +120,20 @@ function automatic carfield_master_idx_t carfield_gen_master_idx(islands_cfg_t i carfield_master_idx_t ret = '{default: '0}; // Initialize struct first int unsigned i = 0; int unsigned j = 0; - if (island_cfg.safed.enable ) begin ret.safed = i; i++; end else begin j++; ret.safed = ret.safed - j; end - if (island_cfg.secured.enable ) begin ret.secured = i; i++; end else begin j++; ret.secured = ret.secured - j; end - if (island_cfg.spatz.enable ) begin ret.spatz = i; i++; end else begin j++; ret.spatz = ret.spatz - j; end - if (island_cfg.pulp.enable ) begin ret.pulp = i; i++; end else begin j++; ret.pulp = ret.pulp - j; end + if (island_cfg.safed.enable) begin ret.safed = i; i++; end + else begin j++; ret.safed = ret.safed - j; end + if (island_cfg.secured.enable) begin ret.secured = i; i++; + end else begin j++; ret.secured = ret.secured - j; end + if (island_cfg.spatz.enable) begin ret.spatz = i; i++; end + else begin j++; ret.spatz = ret.spatz - j; end + if (island_cfg.pulp.enable) begin ret.pulp = i; i++; end + else begin j++; ret.pulp = ret.pulp - j; end return ret; endfunction +// verilog_lint: waive-start line-length function automatic axi_struct_t carfield_gen_axi_map(int unsigned NumSlave, islands_cfg_t island_cfg); +// verilog_lint: waive-stop line-length axi_struct_t ret = '0; // Initialize the map first int unsigned i = 0; if (island_cfg.l2_port0.enable) begin @@ -194,6 +200,8 @@ function automatic int unsigned gen_carfield_domains(islands_cfg_t island_cfg); endfunction // All fields below are in the form: '{enable, base address, address size}. +// The Secure Domain can only be a master of the crossbar. For this reason +// we can only enable it, and provide fake address ranges. localparam islands_cfg_t CarfieldIslandsCfg = '{ l2_port0: '{1, 'h78000000, 'h00200000}, l2_port1: '{1, 'h78200000, 'h00200000}, @@ -202,17 +210,19 @@ localparam islands_cfg_t CarfieldIslandsCfg = '{ periph: '{1, 'h20001000, 'h00009000}, spatz: '{1, 'h51000000, 'h00800000}, pulp: '{1, 'h50000000, 'h00800000}, - secured: '{1, '1, '1 }, // We do not address opentitan, base address and size are not used. + secured: '{1, '0, '0 }, mbox: '{1, 'h40000000, 'h00001000} }; // TODO: specify this is for AXI -localparam int unsigned CarfieldNumSlaves = gen_num_slave(CarfieldIslandsCfg); -localparam carfield_slave_idx_t CarfieldSlvIdx = carfield_gen_slave_idx(CarfieldIslandsCfg); -localparam int unsigned CarfieldNumMasters = gen_num_master(CarfieldIslandsCfg); -localparam carfield_master_idx_t CarfieldMstIdx = carfield_gen_master_idx(CarfieldIslandsCfg); +localparam int unsigned CarfieldNumSlaves = gen_num_slave(CarfieldIslandsCfg); +localparam carfield_slave_idx_t CarfieldSlvIdx = carfield_gen_slave_idx(CarfieldIslandsCfg); +localparam int unsigned CarfieldNumMasters = gen_num_master(CarfieldIslandsCfg); +localparam carfield_master_idx_t CarfieldMstIdx = carfield_gen_master_idx(CarfieldIslandsCfg); +// verilog_lint: waive-start line-length localparam axi_struct_t CarfieldAxiMap = carfield_gen_axi_map(CarfieldNumSlaves, CarfieldIslandsCfg); +// verilog_lint: waive-stop line-length localparam int unsigned CarfieldNumDomains = gen_carfield_domains(CarfieldIslandsCfg); @@ -226,7 +236,9 @@ function automatic carfield_clk_div_values_t gen_carfield_clk_div_value(int unsi return ret; endfunction +// verilog_lint: waive-start line-length localparam carfield_clk_div_values_t CarfieldClkDivValue = gen_carfield_clk_div_value(CarfieldNumDomains); +// verilog_lint: waive-stop line-length typedef struct packed { byte_bt l2;