diff --git a/target/xilinx/constraints/carfield_islands.tcl b/target/xilinx/constraints/carfield_islands.tcl
index bbd77c93..a123895b 100644
--- a/target/xilinx/constraints/carfield_islands.tcl
+++ b/target/xilinx/constraints/carfield_islands.tcl
@@ -41,13 +41,31 @@ handle_domain_clock_mux [get_cells -hier u_l2_clk_sel] 0 l2_domain_clk
 # Carfield CDCs #
 #################
 
-# Safety Island
-################
+## Find the first parent cell of matching module from a list of object paths
+## @param strs children objects paths
+## @param ref_to_find the module type of the parent cell
+proc find_parent_cell { strs ref_to_find } {
+  foreach str $strs {
+    set path ".";
+    foreach cell [split $str '/'] {
+      if {[get_cells -quiet $path] != ""} {
+        if { [get_property "ORIG_REF_NAME" [get_cell $path]] == $ref_to_find } {
+          return $path
+        }
+        if { [get_property "REF_NAME" [get_cell $path]] == $ref_to_find } {
+          return $path
+        }
+      }
+      set path $path/$cell;
+    }
+  }
+  return ""
+}
 
 proc handle_slv_cdc { slv_cdc_path } {
   upvar SOC_TCK SOC_TCK
   # Start from a known slv cdc_dst and get fanout to find the mst cdc_src
-  set mst_cdc_path [lindex [regexp -inline {.*i_cheshire_ext_slv_cdc_src|.*i_intcluster_slv_cdc} [lindex [filter [all_fanout -flat [get_pins $slv_cdc_path/*rptr*]] -filter {NAME =~ *gen_ext_slv_src_cdc* || NAME =~ *gen_pulp_cluster*}] 0]] 0]
+  set mst_cdc_path [find_parent_cell [all_fanout -flat [get_pins $slv_cdc_path/*rptr*]] "axi_cdc_src"]
   if { $mst_cdc_path != "" } {
     set_max_delay -datapath \
      -from [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*reg*/C] \
@@ -66,7 +84,6 @@ proc handle_slv_cdc { slv_cdc_path } {
      -to [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \
      "$SOC_TCK"
   }
-
 }
 
 handle_slv_cdc [get_cells -hier gen_periph.i_cdc_dst_peripherals]
@@ -76,12 +93,12 @@ handle_slv_cdc [get_cells -hier gen_safety_island.i_safety_island_wrap]/i_cdc_in
 handle_slv_cdc [get_cells -hier gen_spatz_cluster.i_fp_cluster_wrapper]/i_spatz_cluster_cdc_dst
 handle_slv_cdc [get_cells -hier gen_pulp_cluster.i_integer_cluster]/axi_slave_cdc_i
 handle_slv_cdc [get_cells -hier gen_l2.i_reconfigurable_l2]/gen_cdc_fifos[0].i_dst_cdc
+handle_slv_cdc [get_cells -hier i_hyperbus_wrap]/i_hyper_cdc_dst
 
 proc handle_mst_cdc { mst_cdc_path } {
   upvar SOC_TCK SOC_TCK
-  # Get the dst_cdc in cheshire
-  set slv_cdc_path [lindex [regexp -inline {.*i_cheshire_ext_mst_cdc_dst|.*i_intcluster_mst_cdc} [lindex [filter [all_fanout -flat [get_pins $mst_cdc_path/*wptr*]] -filter {NAME =~ *gen_ext_mst_dst_cdc* || NAME =~ *gen_pulp_cluster*}] 0]] 0]
-
+  # Start from a known mst cdc_src and get fanout to find the slv cdc_dst
+  set slv_cdc_path [find_parent_cell [all_fanout -flat [get_pins $mst_cdc_path/*rptr*]] "axi_cdc_dst"]
   if { $slv_cdc_path != "" } {
     # From Safety Island master
     set_max_delay -datapath \
@@ -101,7 +118,6 @@ proc handle_mst_cdc { mst_cdc_path } {
      -to [get_pins $mst_cdc_path/i_cdc_fifo_gray_*/*i_sync/*reg*/D] \
      "$SOC_TCK"
   }
-
 }
 
 handle_mst_cdc [get_cells -hier gen_safety_island.i_safety_island_wrap]/i_cdc_out
diff --git a/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv b/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv
index 1d35fbd5..b16266de 100644
--- a/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv
+++ b/target/xilinx/flavor_vanilla/src/carfield_top_xilinx.sv
@@ -151,6 +151,15 @@ module carfield_top_xilinx
   logic jtag_trst_ni;
   assign jtag_trst_ni = '1;
 `endif
+`ifndef USE_JTAG
+  logic jtag_tck_i;
+  logic jtag_tms_i;
+  logic jtag_tdi_i;
+  logic jtag_tdo_o;
+  assign jtag_tck_i = '0;
+  assign jtag_tms_i = '0;
+  assign jtag_tdi_i = '0;
+`endif
 
   //////////////////
   // Clock Wizard //
diff --git a/target/xilinx/flavor_vanilla/src/phy_definitions.svh b/target/xilinx/flavor_vanilla/src/phy_definitions.svh
index 98ad955a..d2c76f98 100644
--- a/target/xilinx/flavor_vanilla/src/phy_definitions.svh
+++ b/target/xilinx/flavor_vanilla/src/phy_definitions.svh
@@ -6,8 +6,10 @@
 
 `ifdef TARGET_VCU128
   `define USE_RESET
-  `define USE_JTAG
-  `define USE_JTAG_VDDGND
+  `ifdef GEN_EXT_JTAG
+    `define USE_JTAG
+    `define USE_JTAG_VDDGND
+  `endif
   `define USE_QSPI
   `define USE_STARTUPE3
   `define USE_VIO
@@ -18,16 +20,6 @@
   `endif
 `endif
 
-`ifdef TARGET_ZCU102
-  `define USE_RESET
-  `define USE_JTAG
-  `define HypNumChips 1
-  `define HypNumPhys 1
-  `ifdef GEN_NO_HYPERBUS
-    `define USE_DDR4
-  `endif  `define USE_VIO
-`endif
-
 /////////////////////
 // DRAM INTERFACES //
 /////////////////////