maths

Maths - Verilog Library

Maths Verilog designs from Project F, including division, square root, and transcendental functions. You can freely build on these MIT licensed designs. Get an overview of the whole lib from the Verilog Library blog.

Verilog Modules

• Division
  • div.sv - signed fixed-point with Gaussian rounding
  • divu.sv - unsigned fixed-point that rounds towards zero
  • divu_int.sv - unsigned integer with remainder
• Linear Feedback Shift Register: lfsr.sv
• Multiplication: mul.sv - signed fixed-point with Gaussian rounding
• Square Root
  • sqrt.sv - fixed point
  • sqrt_int.sv - integer
• Trigonometry
  • sine_table.sv - sine and cosine from lookup table (ROM)

Test Benches

Modules in the Verilog library have test benches for cocotb and/or Vivado. Cocotb test bench coverage will expand during 2023.

cocotb

You can find cocotb test benches using Icarus Verilog in the test directory. Use the included Makefile to run tests.

Some tests use the Simple Python Fixed-Point Module: spfpm

Add the following to a Verilog module to generate a VCD waveform file from cocotb test benches:

// generate waveform file with cocotb
`ifdef COCOTB_SIM
initial begin
    $dumpfile($sformatf("%m.vcd"));
    $dumpvars;
end
`endif

Vivado

You can find Vivado test benches in the xc7 directory. Associated waveform configuration is in xc7/vivado.

Blog Posts

The following blog posts document and make use of these maths designs:

• Ad Astra - animated starfields using LFSR
• Division - explains how the division algorithms work
• Sine Table - lookup sine and cosine from ROM
  • sine2fmem - Python script to generate sine tables for ROM
• Square Root - calculate square roots for integers and fixed-point

SystemVerilog?

These modules use a little SystemVerilog to make Verilog more pleasant, see the main Library README for details.