From c7600d35d7b5ded3a2dc0aa00c149446a13904ef Mon Sep 17 00:00:00 2001 From: Aditya Badole Date: Wed, 23 Aug 2023 14:45:55 +0800 Subject: [PATCH] #5 Re-issue rescheduled load --- src/arch/riscvcapstone/isa/decoder.isa | 27 ++++++++++++--------- src/arch/riscvcapstone/isa/formats/tags.isa | 2 ++ src/arch/riscvcapstone/o3/commit.cc | 2 +- src/arch/riscvcapstone/o3/iew.cc | 5 +++- src/arch/riscvcapstone/o3/inst_queue.cc | 1 - src/arch/riscvcapstone/o3/lsq_unit.cc | 9 ++++--- src/arch/riscvcapstone/o3/ncq_unit.cc | 3 ++- 7 files changed, 29 insertions(+), 20 deletions(-) diff --git a/src/arch/riscvcapstone/isa/decoder.isa b/src/arch/riscvcapstone/isa/decoder.isa index d8c7913fee..5480d5e361 100644 --- a/src/arch/riscvcapstone/isa/decoder.isa +++ b/src/arch/riscvcapstone/isa/decoder.isa @@ -736,6 +736,7 @@ decode QUADRANT default Unknown::unknown() { assert(Rs1_trv.getTag()); NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId(); + if(dyn_inst->nodeQueryN == 0) dyn_inst->initiateNodeCommand(new NodeQuery(node_id)); }}, {{ Addr EA = Rs1_trv.getRegVal().capVal().cursor(); @@ -757,26 +758,26 @@ decode QUADRANT default Unknown::unknown() { return std::make_shared( "Rs1 doesn't have the necessary perms", machInst); - EA = EA & ~(sizeof(RegVal) - 1); - Fault fault = dyn_inst->initiateGetTag(EA); + //EA = EA & ~(sizeof(RegVal) - 1); + //Fault fault = dyn_inst->initiateGetTag(EA); }}, {{ ConstTaggedRegVal temp_regval; - gem5::RiscvcapstoneISA::o3::Cap& cap = Mem_rv.capVal(); + //gem5::RiscvcapstoneISA::o3::Cap& cap = Mem_ub.capVal(); - getMemLE(pkt, cap, traceData); + getMemLE(pkt, Mem_ub, traceData); - Addr EA = Rs1_trv.getRegVal().capVal().cursor(); - EA = EA & ~(sizeof(RegVal) - 1); + //Addr EA = Rs1_trv.getRegVal().capVal().cursor(); + //EA = EA & ~(sizeof(RegVal) - 1); - temp_regval.getRegVal() = (uint8_t)Mem_rv; + temp_regval.getRegVal() = (uint8_t)Mem_ub; temp_regval.setTag(false); - bool tag_res = dyn_inst->getTagQueryRes(0); + /*bool tag_res = dyn_inst->getTagQueryRes(0); if(tag_res) { dyn_inst->initiateSetTag(EA, false); NodeID nodeId = Mem_rv.capVal().nodeId(); dyn_inst->initiateNodeCommand(new NodeRcUpdate(nodeId, -1)); - } + }*/ Rd_trv = temp_regval; //Rd_trv.setTag(false); @@ -785,6 +786,7 @@ decode QUADRANT default Unknown::unknown() { assert(Rs1_trv.getTag()); NodeID node_id = Rs1_trv.getRegVal().capVal().nodeId(); + if(dyn_inst->nodeQueryN == 0) dyn_inst->initiateNodeCommand(new NodeQuery(node_id)); }}, {{ Addr EA = Rs1_trv.getRegVal().capVal().cursor(); @@ -807,7 +809,8 @@ decode QUADRANT default Unknown::unknown() { "Rs1 doesn't have the necessary perms", machInst); EA = EA & ~(sizeof(RegVal) - 1); - Fault fault = dyn_inst->initiateGetTag(EA); + //if(dyn_inst->tagQueryN == 0) + // Fault fault = dyn_inst->initiateGetTag(EA); }}, {{ ConstTaggedRegVal temp_regval; gem5::RiscvcapstoneISA::o3::Cap& cap = Mem_rv.capVal(); @@ -820,12 +823,12 @@ decode QUADRANT default Unknown::unknown() { temp_regval.getRegVal() = (uint64_t)Mem_rv; temp_regval.setTag(false); - bool tag_res = dyn_inst->getTagQueryRes(0); + /*bool tag_res = dyn_inst->getTagQueryRes(0); if(tag_res) { dyn_inst->initiateSetTag(EA, false); NodeID nodeId = Mem_rv.capVal().nodeId(); dyn_inst->initiateNodeCommand(new NodeRcUpdate(nodeId, -1)); - } + }*/ Rd_trv = temp_regval; //Rd_trv.setTag(false); diff --git a/src/arch/riscvcapstone/isa/formats/tags.isa b/src/arch/riscvcapstone/isa/formats/tags.isa index 69e6ac4cb5..a6f57df63f 100644 --- a/src/arch/riscvcapstone/isa/formats/tags.isa +++ b/src/arch/riscvcapstone/isa/formats/tags.isa @@ -110,6 +110,8 @@ def template TagAccessExecute {{ %(code)s; + dyn_inst->setLoadEffAddrs(EA, 1); + return NoFault; } }}; diff --git a/src/arch/riscvcapstone/o3/commit.cc b/src/arch/riscvcapstone/o3/commit.cc index 1de342be59..d4280fba41 100644 --- a/src/arch/riscvcapstone/o3/commit.cc +++ b/src/arch/riscvcapstone/o3/commit.cc @@ -1228,7 +1228,7 @@ Commit::commitHead(const DynInstPtr &head_inst, unsigned inst_num) //seriously, there has to be a better way to do this. //how would split change RC? need to check the spec std::string mnemonic = head_inst->staticInst->getName(); - if(head_inst->staticInst->opClass() != No_OpClass && mnemonic != "capperm" && + if(head_inst->fault != NoFault && head_inst->staticInst->opClass() != No_OpClass && mnemonic != "capperm" && mnemonic != "captype" && mnemonic != "capnode" && mnemonic != "capbound" && mnemonic != "stc" && mnemonic != "std" && mnemonic != "stb" && diff --git a/src/arch/riscvcapstone/o3/iew.cc b/src/arch/riscvcapstone/o3/iew.cc index dbc7f52b40..77ee1dad22 100644 --- a/src/arch/riscvcapstone/o3/iew.cc +++ b/src/arch/riscvcapstone/o3/iew.cc @@ -1295,7 +1295,10 @@ IEW::executeInsts() if(fault == NoFault) { DPRINTF(IEW, "Execute instruction %i -> %s\n", inst->seqNum, inst->staticInst->getName()); fault = inst->execute(); - inst->setExecuteCalled(); + //only one case will not mark executecalled -> when it's a rescheduled load + if(!inst->isLoad() || (inst->isLoad() && inst->loadEffAddrValid()) || inst->fault != NoFault) + inst->setExecuteCalled(); + if(inst->isMemRef()) { DPRINTF(IEW, "Memref fault = %d\n", fault == NoFault); } else { diff --git a/src/arch/riscvcapstone/o3/inst_queue.cc b/src/arch/riscvcapstone/o3/inst_queue.cc index 58b292dd61..cdd94233d1 100644 --- a/src/arch/riscvcapstone/o3/inst_queue.cc +++ b/src/arch/riscvcapstone/o3/inst_queue.cc @@ -1097,7 +1097,6 @@ InstructionQueue::rescheduleMemInst(const DynInstPtr &resched_inst) resched_inst->translationCompleted(false); resched_inst->clearCanIssue(); - //resched_inst->clearExecuteCalled(); memDepUnit[resched_inst->threadNumber].reschedule(resched_inst); } diff --git a/src/arch/riscvcapstone/o3/lsq_unit.cc b/src/arch/riscvcapstone/o3/lsq_unit.cc index 83839e484f..f29d274f79 100644 --- a/src/arch/riscvcapstone/o3/lsq_unit.cc +++ b/src/arch/riscvcapstone/o3/lsq_unit.cc @@ -473,7 +473,7 @@ LSQUnit::checkSnoop(PacketPtr pkt) LSQRequest *request = iter->request(); // Check that this snoop didn't just invalidate our lock flag - if (ld_inst->effAddrValid() && + if (ld_inst->loadEffAddrValid() && request->isCacheBlockHit(invalidate_addr, cacheBlockMask) && ld_inst->memReqFlags & Request::LLSC) { ld_inst->tcBase()->getIsaPtr()->handleLockedSnoopHit(ld_inst.get()); @@ -485,7 +485,7 @@ LSQUnit::checkSnoop(PacketPtr pkt) ld_inst = iter->instruction(); assert(ld_inst); request = iter->request(); - if (!ld_inst->effAddrValid() || ld_inst->strictlyOrdered()) + if (!ld_inst->loadEffAddrValid() || ld_inst->strictlyOrdered()) continue; DPRINTF(LSQUnit, "-- inst [sn:%lli] to pktAddr:%#x\n", @@ -1435,7 +1435,7 @@ LSQUnit::read(LSQRequest *request, ssize_t load_idx) // rescheduled eventually iewStage->rescheduleMemInst(load_inst); load_inst->clearIssued(); - load_inst->effAddrValid(false); + load_inst->loadEffAddrValid(false); ++stats.rescheduledLoads; DPRINTF(LSQUnit, "Strictly ordered load [sn:%lli] PC %s\n", load_inst->seqNum, load_inst->pcState()); @@ -1659,7 +1659,8 @@ LSQUnit::read(LSQRequest *request, ssize_t load_idx) // rescheduled eventually iewStage->rescheduleMemInst(load_inst); load_inst->clearIssued(); - load_inst->effAddrValid(false); + load_inst->loadEffAddrValid(false); + load_inst->memReadN--; ++stats.rescheduledLoads; // Do not generate a writeback event as this instruction is not diff --git a/src/arch/riscvcapstone/o3/ncq_unit.cc b/src/arch/riscvcapstone/o3/ncq_unit.cc index f01dccda34..53377b47ca 100644 --- a/src/arch/riscvcapstone/o3/ncq_unit.cc +++ b/src/arch/riscvcapstone/o3/ncq_unit.cc @@ -92,7 +92,8 @@ NCQUnit::cleanupCommands(){ DPRINTF(NCQ, "Cleaning up commands\n"); while(!ncQueue.empty()) { auto& front = ncQueue.front(); - DPRINTF(NCQ, "cleanupCommands: inst %u, canWB %u, completed() %u, commands size() %u", front.inst->seqNum, front.canWB, front.completed(), front.commands.size()); + DPRINTF(NCQ, "cleanupCommands: inst %u, canWB %u, completedCommands %u, commands size() %u\n", + front.inst->seqNum, front.canWB, front.completedCommands, front.commands.size()); if(front.canWB && front.completed()) { DPRINTF(NCQ, "Removing NCQEntry for instruction %u\n", front.inst->seqNum); front.inst->ncqIdx = -1;