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Verilog.tmLanguage
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<?xml version="1.0" encoding="UTF-8"?>
<!DOCTYPE plist
PUBLIC '-//Apple//DTD PLIST 1.0//EN'
'http://www.apple.com/DTDs/PropertyList-1.0.dtd'>
<plist>
<dict>
<key>fileTypes</key>
<array>
<string>v</string>
<string>V</string>
</array>
<key>foldingStartMarker</key>
<string>(begin)\s*(//.*)?$</string>
<key>foldingStopMarker</key>
<string>^\s*(end)$</string>
<key>name</key>
<string>Verilog</string>
<key>patterns</key>
<array>
<!-- module XXX -->
<dict>
<key>captures</key>
<dict>
<key>1</key>
<dict>
<key>name</key>
<string>storage.verilog</string>
</dict>
<key>2</key>
<dict>
<key>name</key>
<string>entity.name.type.class.verilog</string>
</dict>
</dict>
<key>match</key>
<string>^\s*(module|function|primitive)\s+\b([a-zA-Z_][a-zA-Z0-9_]*)\b</string>
<key>name</key>
<string>meta.entity.module.verilog</string>
</dict>
<dict>
<!-- modulename instancename ( -->
<key>captures</key>
<dict>
<key>1</key>
<dict>
<key>name</key>
<string>entity.name.type.class.verilog</string>
</dict>
<key>2</key>
<dict>
<key>name</key>
<string>variable.function.verilog</string>
</dict>
<key>3</key>
<dict>
<key>name</key>
<string>text.operator.parenthesis.round.verilog</string>
</dict>
</dict>
<key>match</key>
<string>^\s*(?!else)(?!begin)([a-zA-Z_][a-zA-Z0-9_]*)\s+([a-zA-Z_][a-zA-Z0-9_]*)\s*(\()</string>
<key>name</key>
<string>meta.definition.verilog</string>
</dict>
<dict>
<!-- modulename #(something,something,etc) instancename ( -->
<key>captures</key>
<dict>
<key>1</key>
<dict>
<key>name</key>
<string>entity.name.type.class.verilog</string>
</dict>
<key>2</key> <!-- # -->
<dict>
<key>name</key>
<string>keyword.other.verilog</string>
</dict>
<key>3</key> <!-- ( -->
<dict>
<key>name</key>
<string>text.operator.parenthesis.round.verilog</string>
</dict>
<key>4</key> <!-- something,something -->
<dict>
<key>name</key>
<string>keyword.other.verilog</string>
</dict>
<key>5</key> <!-- ) -->
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<key>name</key>
<string>text.operator.parenthesis.round.verilog</string>
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<key>6</key>
<dict>
<key>name</key>
<string>entity.name.type.instance.verilog</string>
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<string>text.operator.parenthesis.round.verilog</string>
</dict>
</dict>
<key>match</key>
<string>^\s*(?!else)(?!begin)([a-zA-Z_][a-zA-Z0-9_]*)\s+([#])(\()([ ._+`,a-zA-Z0-9]+)(\))\s+([a-zA-Z_][a-zA-Z0-9_]*)\s*(\()</string>
<key>name</key>
<string>meta.definition.withparameter.verilog</string>
</dict>
<dict>
<!-- IODELAY # -->
<key>captures</key>
<dict>
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<dict>
<key>name</key>
<string>entity.name.type.class.verilog</string>
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<dict>
<key>name</key>
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<string>^\s*\b(?!else)(?!begin)([a-zA-Z_][a-zA-Z0-9_]*)\b\s+([#])</string>
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<string>meta.definition.withparameter.verilog</string>
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<dict>
<!-- defparam instancename.parameter = -->
<key>captures</key>
<dict>
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<dict>
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<key>name</key>
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</dict>
<key>3</key>
<dict>
<key>name</key>
<string>meta.module.parameters.verilog</string>
</dict>
<key>4</key>
<dict>
<key>name</key>
<string>keyword.other.verilog</string>
</dict>
</dict>
<key>match</key>
<string>^\s*(defparam)\s+([a-zA-Z_][a-zA-Z0-9_]*)(.[a-zA-Z_][a-zA-Z0-9_]*)\s*(=)</string>
<key>name</key>
<string>meta.definition.defparam.verilog</string>
</dict>
<dict>
<key>match</key>
<string>\b(timeunit|timeprecision|automatic|cell|config|deassign|defparam|design|disable|edge|endconfig|endgenerate|endspecify|endtable|endtask|event|generate|genvar|ifnone|incdir|include|instance|liblist|library|localparam|macromodule|negedge|noshowcancelled|posedge|pulsestyle_onevent|pulsestyle_ondetect|real|realtime|scalared|showcancelled|specify|specparam|table|task|time|use|vectored)\b</string>
<key>name</key>
<string>keyword.other.verilog</string>
</dict>
<dict>
<key>match</key>
<string>(#[0-9]+)</string>
<key>name</key>
<string>keyword.delay.verilog</string>
</dict>
<dict>
<key>match</key>
<string>\b(initial|final|always|wait|force|release|assign)\b</string>
<key>name</key>
<string>keyword.control.verilog</string>
</dict>
<dict>
<key>match</key>
<string>\b(begin|end|fork|join)\b</string>
<key>name</key>
<string>keyword.other.verilog</string>
</dict>
<dict>
<key>match</key>
<string>\b(forever|repeat|while|for|if|else|case|casex|casez|default|endcase)\b</string>
<key>name</key>
<string>keyword.control.verilog</string>
</dict>
<dict>
<key>captures</key>
<dict>
<key>1</key>
<dict>
<key>name</key>
<!-- <string>keyword.other.verilog</string> -->
<string>keyword.preprocessor.verilog</string>
</dict>
<key>2</key>
<dict>
<key>name</key>
<string>entity.name.filename.include.verilog</string>
</dict>
</dict>
<key>match</key>
<string>^\s*(`include)\s+(["<].*[">])</string>
<key>name</key>
<string>meta.include.verilog</string>
</dict>
<dict>
<key>captures</key>
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<dict>
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<key>name</key>
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</dict>
<key>match</key>
<string>^\s*(`ifdef|`ifndef|`undef|`define)\s+([a-zA-Z_][a-zA-Z0-9_]*)\b</string>
<key>name</key>
<string>meta.preprocessor.ifdef.verilog</string>
</dict>
<dict> <!-- must come after meta.preprocess.ifdef -->
<key>match</key>
<string>`(celldefine|default_nettype|define|else|elsif|endcelldefine|endif|ifdef|ifndef|include|line|nounconnected_drive|resetall|timescale|unconnected_drive|undef)\b</string>
<key>name</key>
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</dict>
<dict>
<key>match</key>
<string>[.][_a-zA-Z0-9]+</string>
<key>name</key>
<string>meta.module.parameters.verilog</string>
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<key>match</key>
<string>`\b([a-zA-Z_][a-zA-Z0-9_]*)\b</string>
<key>name</key>
<string>constant.other.define.verilog</string>
</dict>
<dict>
<key>include</key>
<string>#comments</string>
</dict>
<dict>
<key>match</key>
<string>\b(endmodule|endfunction|endprimitive)\b</string>
<key>name</key>
<string>storage.verilog</string>
</dict>
<dict>
<key>captures</key>
<dict>
<key>1</key>
<dict>
<key>name</key>
<string>entity.name.state.verilog</string>
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<key>2</key>
<dict>
<key>name</key>
<string>keyword.operator.bitwise.verilog</string>
</dict>
</dict>
<key>match</key>
<string>^\s*\b([a-zA-Z_][a-zA-Z0-9_]*)\b\s*(:)\s*</string>
<key>name</key>
<string>meta.case.verilog</string>
</dict>
<dict>
<key>include</key>
<string>#all-types</string>
</dict>
<dict>
<key>match</key>
<string>(===|==|!==|!=|<=|>=|<|>)</string>
<key>name</key>
<string>keyword.operator.comparison.verilog</string>
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<dict>
<key>match</key>
<string>(\-|\+|\*|\/|%)</string>
<key>name</key>
<string>keyword.operator.arithmetic.verilog</string>
</dict>
<dict>
<key>match</key>
<string>(!|&&|\|\|)</string>
<key>name</key>
<string>keyword.operator.logical.verilog</string>
</dict>
<dict>
<key>match</key>
<string>(&|\||\^|~|<<|>>|\?|:)</string>
<key>name</key>
<string>keyword.operator.bitwise.verilog</string>
</dict>
<!-- <dict>
<key>match</key>
<string>({|})</string>
<key>name</key>
<string>keyword.operator.parenthesis.curly.verilog</string>
</dict>
<dict>
<key>match</key>
<string>(\(|\))</string>
<key>name</key>
<string>keyword.operator.parenthesis.round.verilog</string>
</dict>
<dict>
<key>match</key>
<string>(\[|\])</string>
<key>name</key>
<string>keyword.operator.parenthesis.square.verilog</string>
</dict>
<dict>
<key>match</key>
<string>([;,])</string>
<key>name</key>
<string>keyword.delimiter.verilog</string>
</dict> -->
<dict>
<key>match</key>
<string>(#|@|=)</string>
<key>name</key>
<string>keyword.other.verilog</string>
</dict>
<dict>
<key>match</key>
<string>\b(output|input|inout|and|nand|nor|or|xor|xnor|buf|not|bufif[01]|notif[01]|r?[npc]mos|tran|r?tranif[01]|pullup|pulldown)\b</string>
<key>name</key>
<string>support.type.verilog</string>
</dict>
<dict>
<key>match</key>
<string>((\b\d+)?'s?([bB]\s*(([0-1_xXzZ?]+)|(`[A-Z]+[_0-9a-zA-Z]*))|[oO]\s*(([0-7_xXzZ?]+)|(`[A-Z]+[_0-9a-zA-Z]*))|[dD]\s*(([0-9_xXzZ?]+)|(`[A-Z]+[_0-9a-zA-Z]*))|[hH]\s*(([0-9a-fA-F_xXzZ?]+)|(`[A-Z]+[_0-9a-zA-Z]*)))((e|E)(\+|-)?[0-9]+)?\b)|(\b\d+\b)</string>
<key>name</key>
<string>constant.numeric.verilog</string>
</dict>
<dict>
<key>include</key>
<string>#strings</string>
</dict>
<dict>
<key>match</key>
<string>\$\b([a-zA-Z_][a-zA-Z0-9_]*)\b</string>
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</dict>
<!-- capital constants
<dict>
<key>match</key>
<string>\b([A-Z][A-Z0-9_]+)\b</string>
<key>name</key>
<string>constant.other.verilog</string>
</dict>
-->
</array>
<key>repository</key>
<dict>
<key>all-types</key>
<dict>
<key>patterns</key>
<array>
<dict>
<key>include</key>
<string>#storage-type-verilog</string>
</dict>
<dict>
<key>include</key>
<string>#storage-modifier-verilog</string>
</dict>
</array>
</dict>
<key>comments</key>
<dict>
<key>patterns</key>
<array>
<dict>
<key>begin</key>
<string>/\*</string>
<key>captures</key>
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<dict>
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</dict>
</dict>
<key>end</key>
<string>\*/</string>
<key>name</key>
<string>comment.block.verilog</string>
</dict>
<dict>
<key>captures</key>
<dict>
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<dict>
<key>name</key>
<string>punctuation.definition.comment.verilog</string>
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</dict>
<key>match</key>
<string>(//).*$\n?</string>
<key>name</key>
<string>comment.line.double-slash.verilog</string>
</dict>
</array>
</dict>
<key>storage-type-verilog</key>
<dict>
<key>match</key>
<string>\b(wire|tri|tri[01]|supply[01]|wand|triand|wor|trior|trireg|reg|parameter|integer)\b</string>
<key>name</key>
<string>storage.type.verilog</string>
</dict>
<key>storage-modifier-verilog</key>
<dict>
<key>match</key>
<string>\b(signed|unsigned|small|medium|large|supply[01]|strong[01]|pull[01]|weak[01]|highz[01])\b</string>
<key>name</key>
<string>storage.modifier.verilog</string>
</dict>
<key>strings</key>
<dict>
<key>patterns</key>
<array>
<dict>
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<string>"</string>
<key>beginCaptures</key>
<dict>
<key>0</key>
<dict>
<key>name</key>
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</dict>
</dict>
<key>end</key>
<string>"</string>
<key>endCaptures</key>
<dict>
<key>0</key>
<dict>
<key>name</key>
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</dict>
</dict>
<key>name</key>
<string>string.quoted.double.verilog</string>
<key>patterns</key>
<array>
<dict>
<key>match</key>
<string>\\.</string>
<key>name</key>
<string>constant.character.escape.verilog</string>
</dict>
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<!-- single quotes are not used for strings
<dict>
<key>begin</key>
<string>'</string>
<key>beginCaptures</key>
<dict>
<key>0</key>
<dict>
<key>name</key>
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</dict>
</dict>
<key>end</key>
<string>'</string>
<key>endCaptures</key>
<dict>
<key>0</key>
<dict>
<key>name</key>
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</dict>
</dict>
<key>name</key>
<string>string.quoted.single.verilog</string>
<key>patterns</key>
<array>
<dict>
<key>match</key>
<string>\\.</string>
<key>name</key>
<string>constant.character.escape.verilog</string>
</dict>
</array>
</dict>
-->
</array>
</dict>
</dict>
<key>scopeName</key>
<string>source.verilog</string>
<key>uuid</key>
<string>6856ea09-6f82-3ead-a3ae-2dd2d81453b9</string>
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</plist>