From 668b791b1fc2e671dcfc76541395c222ee08181b Mon Sep 17 00:00:00 2001
From: wanda-phi <145241585+wanda-phi@users.noreply.github.com>
Date: Sun, 2 Jun 2024 06:47:16 +0000
Subject: [PATCH] =?UTF-8?q?Deploying=20to=20gh-pages=20from=20=20@=205bb6b?=
 =?UTF-8?q?dc3cf8d3cc25064a2abf374f8f7e23018cd=20=F0=9F=9A=80?=
MIME-Version: 1.0
Content-Type: text/plain; charset=UTF-8
Content-Transfer-Encoding: 8bit

---
 _sources/xilinx/virtex2/corner.rst.txt |  184 +++
 _sources/xilinx/virtex2/index.rst.txt  |    1 +
 objects.inv                            |  Bin 1581 -> 1608 bytes
 searchindex.js                         |    2 +-
 xilinx/index.html                      |    1 +
 xilinx/spartan3/index.html             |    4 +-
 xilinx/virtex2/bram.html               |    1 +
 xilinx/virtex2/clb.html                |    1 +
 xilinx/virtex2/clock.html              |    5 +-
 xilinx/virtex2/corner.html             | 2089 ++++++++++++++++++++++++
 xilinx/virtex2/index.html              |    8 +
 xilinx/virtex2/interconnect.html       |    3 +-
 xilinx/virtex2/intro.html              |    3 +-
 xilinx/virtex2/structure.html          |    1 +
 14 files changed, 2296 insertions(+), 7 deletions(-)
 create mode 100644 _sources/xilinx/virtex2/corner.rst.txt
 create mode 100644 xilinx/virtex2/corner.html

diff --git a/_sources/xilinx/virtex2/corner.rst.txt b/_sources/xilinx/virtex2/corner.rst.txt
new file mode 100644
index 00000000..b93c10e4
--- /dev/null
+++ b/_sources/xilinx/virtex2/corner.rst.txt
@@ -0,0 +1,184 @@
+.. _virtex2-corner:
+
+Corners — Virtex 2, Spartan 3
+#############################
+
+.. todo:: document
+
+
+Lower left
+==========
+
+.. todo:: document
+
+
+``LL`` — Virtex 2
+-----------------
+
+This tile is used on Virtex 2.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc2v-LL.html
+
+
+``LL.S3``
+---------
+
+This tile is used on Spartan 3.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-LL.S3.html
+
+
+``LL.S3E``
+----------
+
+This tile is used on Spartan 3E.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-LL.S3E.html
+
+
+``LL.S3A``
+----------
+
+This tile is used on Spartan 3A.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-LL.S3A.html
+
+
+Upper left
+==========
+
+.. todo:: document
+
+
+``UL`` — Virtex 2
+-----------------
+
+This tile is used on Virtex 2.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc2v-UL.html
+
+
+``UL.S3``
+---------
+
+This tile is used on Spartan 3.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-UL.S3.html
+
+
+``UL.S3E``
+----------
+
+This tile is used on Spartan 3E.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-UL.S3E.html
+
+
+``UL.S3A``
+----------
+
+This tile is used on Spartan 3A.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-UL.S3A.html
+
+
+Lower right
+===========
+
+.. todo:: document
+
+
+``LR`` — Virtex 2
+-----------------
+
+This tile is used on Virtex 2.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc2v-LR.html
+
+
+``LR.S3``
+---------
+
+This tile is used on Spartan 3.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-LR.S3.html
+
+
+``LR.S3E``
+----------
+
+This tile is used on Spartan 3E.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-LR.S3E.html
+
+
+``LR.S3A``
+----------
+
+This tile is used on Spartan 3A.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-LR.S3A.html
+
+
+Upper right
+===========
+
+.. todo:: document
+
+
+``UR.V2``
+---------
+
+This tile is used on Virtex 2.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc2v-UR.V2.html
+
+
+
+``UR.V2P``
+----------
+
+This tile is used on Virtex 2 Pro.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc2v-UR.V2P.html
+
+
+``UR.S3``
+---------
+
+This tile is used on Spartan 3.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-UR.S3.html
+
+
+``UR.S3E``
+----------
+
+This tile is used on Spartan 3E.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-UR.S3E.html
+
+
+``UR.S3A``
+----------
+
+This tile is used on Spartan 3A.
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-UR.S3A.html
diff --git a/_sources/xilinx/virtex2/index.rst.txt b/_sources/xilinx/virtex2/index.rst.txt
index 49833984..616032f0 100644
--- a/_sources/xilinx/virtex2/index.rst.txt
+++ b/_sources/xilinx/virtex2/index.rst.txt
@@ -13,3 +13,4 @@ Xilinx Virtex 2 FPGAs
    clb
    bram
    clock
+   corner
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diff --git a/searchindex.js b/searchindex.js
index 3bb8e987..8f23171e 100644
--- a/searchindex.js
+++ b/searchindex.js
@@ -1 +1 @@
-Search.setIndex({"alltitles": {"AIM and FB inputs": [[14, "aim-and-fb-inputs"]], "BRAM (Virtex 2)": [[51, "bram-virtex-2"]], "BRAM.S3": [[51, "bram-s3"]], "BRAM.S3A": [[51, "bram-s3a"]], "BRAM.S3ADSP": [[51, "bram-s3adsp"]], "BRAM.S3E": [[51, "bram-s3e"]], "Backbone": [[42, "backbone"], [55, "backbone"]], "Bank configuration": [[14, "bank-configuration"]], "Bitsteam \u2014 interface tiles": [[47, "bitsteam-interface-tiles"]], "Bitstream": [[38, "bitstream"], [40, "bitstream"], [49, "bitstream"], [51, "bitstream"], [52, "bitstream"], [58, "bitstream"], [59, "bitstream"], [61, "bitstream"], [63, "bitstream"]], "Bitstream geometry": [[44, "bitstream-geometry"], [57, "bitstream-geometry"]], "Bitstream structure": [[1, "bitstream-structure"], [68, "bitstream-structure"]], "Bitstream structure \u2014 XC9500": [[15, "bitstream-structure-xc9500"]], "Bitstream structure \u2014 XC9500XL/XV": [[16, "bitstream-structure-xc9500xl-xv"]], "Bitstream \u2014 IOI tile": [[47, "bitstream-ioi-tile"]], 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[35, "boundary-scan-register"], [79, "boundary-scan-register"]], "CLBLL": [[62, "clbll"], [62, "id1"], [62, "id3"]], "CLBLM": [[62, "clblm"], [62, "id2"], [62, "id4"]], "CLEXL": [[62, "clexl"]], "CLEXM": [[62, "clexm"]], "CLKB.S3": [[39, "clkb-s3"]], "CLKB.S3A": [[39, "clkb-s3a"]], "CLKB.S3E": [[39, "clkb-s3e"]], "CLKB.V2": [[53, "clkb-v2"]], "CLKB.V2P": [[53, "clkb-v2p"]], "CLKB.V2PX": [[53, "clkb-v2px"]], "CLKL.S3A": [[39, "clkl-s3a"]], "CLKL.S3E": [[39, "clkl-s3e"]], "CLKR.S3A": [[39, "clkr-s3a"]], "CLKR.S3E": [[39, "clkr-s3e"]], "CLKT.S3": [[39, "clkt-s3"]], "CLKT.S3A": [[39, "clkt-s3a"]], "CLKT.S3E": [[39, "clkt-s3e"]], "CLKT.V2": [[53, "clkt-v2"]], "CLKT.V2P": [[53, "clkt-v2p"]], "CLKT.V2PX": [[53, "clkt-v2px"]], "Carry logic": [[38, "carry-logic"], [52, "carry-logic"]], "Clock divider": [[14, "clock-divider"]], "Clock interconnect": [[39, "clock-interconnect"], [45, "clock-interconnect"], [53, "clock-interconnect"]], "Clock rows": [[44, "clock-rows"], [57, "clock-rows"]], "Clock source \u2014 left and right": [[39, "clock-source-left-and-right"]], "Clock source \u2014 spine bottom and top": [[39, "clock-source-spine-bottom-and-top"], [53, "clock-source-spine-bottom-and-top"]], "Clock spine": [[57, "clock-spine"]], "Clock spine top and bottom": [[55, "clock-spine-top-and-bottom"]], "Configurable Logic Block": [[52, "configurable-logic-block"]], "Configurable Logic Block \u2014 Spartan 3, Virtex 4": [[38, "configurable-logic-block-spartan-3-virtex-4"]], "Configurable Logic Block \u2014 Virtex": [[49, "configurable-logic-block-virtex"]], "Configurable Logic Block \u2014 Virtex 5, Virtex 6, Series 7, Spartan 6": [[62, "configurable-logic-block-virtex-5-virtex-6-series-7-spartan-6"]], "Configuration pull-ups": [[36, "configuration-pull-ups"]], "Contents:": [[0, null], [10, null], [11, null], [32, null], [33, null], [37, null], [41, null], [46, null], [50, null], [54, null], [60, null], [64, null], [67, null], [76, null], [77, null]], "DCM output bus": [[53, "dcm-output-bus"]], "DCMCONN.BOT": [[53, "dcmconn-bot"]], "DCMCONN.TOP": [[53, "dcmconn-top"]], "DSP": [[59, "dsp"], [63, "dsp"], [66, "dsp"]], "DSP \u2014 Spartan 3A DSP, Spartan 6": [[40, "dsp-spartan-3a-dsp-spartan-6"]], "Database schema": [[17, "database-schema"], [69, "database-schema"]], "Database \u2014 devices": [[10, "database-devices"], [32, "database-devices"], [76, "database-devices"]], "Default option attributes": [[39, "default-option-attributes"]], "Default option values": [[51, "default-option-values"]], "Device": [[17, "device"], [69, "device"]], "Device geometry": [[44, "device-geometry"], [57, "device-geometry"]], "Device pins": [[12, "device-pins"], [34, "device-pins"], [78, "device-pins"]], "Device structure": [[14, "device-structure"], [36, "device-structure"], [80, "device-structure"]], "Device table": [[43, "device-table"], [56, "device-table"]], "Devices": [[12, "devices"], [34, "devices"], [78, "devices"]], "Dual-port 16\u00d7X RAM": [[38, "dual-port-16x-ram"], [52, "dual-port-16x-ram"]], "Dual-port 32\u00d7X RAM": [[52, "dual-port-32x-ram"]], "Dual-port 64\u00d71 RAM": [[52, "dual-port-641-ram"]], "ECC mode": [[58, "ecc-mode"]], "Entering and exiting ISP mode \u2014 XC9500": [[35, "entering-and-exiting-isp-mode-xc9500"]], "Entering and exiting ISP mode \u2014 XC9500XL/XV": [[35, "entering-and-exiting-isp-mode-xc9500xl-xv"]], "Erasing fuses \u2014 XC9500": [[35, "erasing-fuses-xc9500"]], "Erasing fuses \u2014 XC9500XL/XV": [[35, "erasing-fuses-xc9500xl-xv"]], "FB columns and rows": [[80, "fb-columns-and-rows"]], "FB global fuses": [[36, "fb-global-fuses"]], "FCLK networks": [[80, "fclk-networks"]], "FIFO mode": [[58, "fifo-mode"]], "Flip-flop": [[36, "flip-flop"]], "Frequency": [[35, "frequency"]], "Fuses \u2014 FB inputs": [[15, "fuses-fb-inputs"], [16, "fuses-fb-inputs"]], "Fuses \u2014 FBs": [[68, "fuses-fbs"]], "Fuses \u2014 IMUX bits": [[68, "fuses-imux-bits"]], "Fuses \u2014 UIM wire-AND": [[15, "fuses-uim-wire-and"]], "Fuses \u2014 global bits": [[68, "fuses-global-bits"]], "Fuses \u2014 input buffer enable": [[15, "fuses-input-buffer-enable"]], "Fuses \u2014 macrocells": [[15, "fuses-macrocells"], [16, "fuses-macrocells"], [68, "fuses-macrocells"]], "Fuses \u2014 per-FB bits and globals": [[15, "fuses-per-fb-bits-and-globals"], [16, "fuses-per-fb-bits-and-globals"]], "Fuses \u2014 product and sum terms": [[68, "fuses-product-and-sum-terms"]], "Fuses \u2014 product terms": [[15, "fuses-product-terms"], [16, "fuses-product-terms"]], "GCLKC": [[53, "gclkc"]], "GCLKC.B": [[53, "gclkc-b"]], "GCLKC.T": [[53, "gclkc-t"]], "GCLKH": [[39, "gclkh"], [53, "gclkh"]], "GCLKH.N": [[39, "gclkh-n"]], "GCLKH.S": [[39, "gclkh-s"]], "GCLKH.UNI": [[39, "gclkh-uni"]], "GCLKH.UNI.N": [[39, "gclkh-uni-n"]], "GCLKH.UNI.S": [[39, "gclkh-uni-s"]], "GCLKVM.S3": [[39, "gclkvm-s3"]], "GCLKVM.S3E": [[39, "gclkvm-s3e"]], "General interconnect": [[42, "general-interconnect"], [47, "general-interconnect"], [55, "general-interconnect"]], "General structure": [[44, "general-structure"], [57, "general-structure"]], "Global bits": [[2, "global-bits"], [3, "global-bits"], [4, "global-bits"], [5, "global-bits"], [6, "global-bits"], [7, "global-bits"], [8, "global-bits"], [9, "global-bits"], [70, "global-bits"], [71, "global-bits"], [72, "global-bits"], [73, "global-bits"], [74, "global-bits"], [75, "global-bits"]], "Global networks": [[14, "global-networks"]], "Global networks \u2014 XC9500": [[36, "global-networks-xc9500"]], "Global networks \u2014 XC9500XL/XV": [[36, "global-networks-xc9500xl-xv"]], "Horizontal clock spine": [[44, "horizontal-clock-spine"]], "I/O pins": [[2, "i-o-pins"], [3, "i-o-pins"], [4, "i-o-pins"], [5, "i-o-pins"], [6, "i-o-pins"], [7, "i-o-pins"], [8, "i-o-pins"], [9, "i-o-pins"], [18, "i-o-pins"], [19, "i-o-pins"], [20, "i-o-pins"], [21, "i-o-pins"], [22, "i-o-pins"], [23, "i-o-pins"], [24, "i-o-pins"], [25, "i-o-pins"], [26, "i-o-pins"], [27, "i-o-pins"], [28, "i-o-pins"], [29, "i-o-pins"], [30, "i-o-pins"], [31, "i-o-pins"], [70, "i-o-pins"], [71, "i-o-pins"], [72, "i-o-pins"], [73, "i-o-pins"], [74, "i-o-pins"], [75, "i-o-pins"]], "IDCODE": [[35, "idcode"], [79, "idcode"]], "IMUX bits": [[2, "imux-bits"], [3, "imux-bits"], [4, "imux-bits"], [5, "imux-bits"], [6, "imux-bits"], [7, "imux-bits"], [8, "imux-bits"], [9, "imux-bits"], [18, "imux-bits"], [19, "imux-bits"], [20, "imux-bits"], [21, "imux-bits"], [22, "imux-bits"], [23, "imux-bits"], [24, "imux-bits"], [25, "imux-bits"], [26, "imux-bits"], [27, "imux-bits"], [28, "imux-bits"], [29, "imux-bits"], [30, "imux-bits"], [31, "imux-bits"], [70, "imux-bits"], [71, "imux-bits"], [72, "imux-bits"], [73, "imux-bits"], [74, "imux-bits"], [75, "imux-bits"]], "INT.BRAM": [[55, "int-bram"]], "INT.BRAM.S3": [[42, "int-bram-s3"]], "INT.BRAM.S3A.03": [[42, "int-bram-s3a-03"]], "INT.BRAM.S3A.12": [[42, "int-bram-s3a-12"]], "INT.BRAM.S3ADSP": [[42, "int-bram-s3adsp"]], "INT.BRAM.S3E": [[42, "int-bram-s3e"]], "INT.CLB": [[42, "int-clb"], [55, "int-clb"]], "INT.CNR": [[55, "int-cnr"]], "INT.DCM": [[42, "int-dcm"]], "INT.DCM.S3E.DUMMY": [[42, "int-dcm-s3e-dummy"]], "INT.DCM.V2": [[55, "int-dcm-v2"]], "INT.DCM.V2P": [[55, "int-dcm-v2p"]], "INT.GT.CLKPAD": [[55, "int-gt-clkpad"]], "INT.IOI": [[55, "int-ioi"]], "INT.IOI.CLK_B": [[55, "int-ioi-clk-b"]], "INT.IOI.CLK_T": [[55, "int-ioi-clk-t"]], "INT.IOI.S3": [[42, "int-ioi-s3"]], "INT.IOI.S3A.LR": [[42, "int-ioi-s3a-lr"]], "INT.IOI.S3A.TB": [[42, "int-ioi-s3a-tb"]], "INT.IOI.S3E": [[42, "int-ioi-s3e"]], "INT.PPC": [[55, "int-ppc"]], "INTF": [[47, "intf"], [65, "intf"], [65, "id1"], [65, "id3"]], "INTF.BRAM": [[65, "intf-bram"]], "INTF.CMT": [[47, "intf-cmt"]], "INTF.CMT.IOI": [[47, "intf-cmt-ioi"]], "INTF.DELAY": [[65, "intf-delay"], [65, "id2"], [65, "id4"]], "INTF.DSP": [[42, "intf-dsp"]], "INTF.GT.B0": [[55, "intf-gt-b0"]], "INTF.GT.B123": [[55, "intf-gt-b123"]], "INTF.GT.BCLKPAD": [[55, "intf-gt-bclkpad"]], "INTF.GT.T0": [[55, "intf-gt-t0"]], "INTF.GT.T123": [[55, "intf-gt-t123"]], "INTF.GT.TCLKPAD": [[55, "intf-gt-tclkpad"]], "INTF.IOI": [[47, "intf-ioi"]], "INTF.PPC": [[55, "intf-ppc"]], "IO banks and IO buffers": [[44, "io-banks-and-io-buffers"], [57, "io-banks-and-io-buffers"]], "IR": [[13, "ir"], [35, "ir"], [79, "ir"]], "ISP DR registers \u2014 XC9500": [[35, "isp-dr-registers-xc9500"]], "ISP DR registers \u2014 XC9500XL/XV": [[35, "isp-dr-registers-xc9500xl-xv"]], "ISP instructions": [[13, "isp-instructions"], [79, "isp-instructions"]], "ISP instructions \u2014 XC9500": [[35, "isp-instructions-xc9500"]], "ISP instructions \u2014 XC9500XL/XV": [[35, "isp-instructions-xc9500xl-xv"]], "Input multiplexers": [[42, "input-multiplexers"], [55, "input-multiplexers"]], "Input/output buffer": [[14, "input-output-buffer"], [36, "input-output-buffer"], [80, "input-output-buffer"]], "Interconnect": [[61, "interconnect"]], "Interconnect \u2014 Virtex 5, Virtex 6, Series 7": [[65, "interconnect-virtex-5-virtex-6-series-7"]], "Introduction": [[12, "introduction"], [34, "introduction"], [43, "introduction"], [56, "introduction"], [78, "introduction"]], "JED bits": [[69, "jed-bits"]], "JED format mapping": [[15, "jed-format-mapping"], [16, "jed-format-mapping"]], "JED mapping": [[2, "jed-mapping"], [3, "jed-mapping"], [4, "jed-mapping"], [4, "id1"], [5, "jed-mapping"], [5, "id1"], [6, "jed-mapping"], [7, "jed-mapping"], [8, "jed-mapping"], [8, "id1"], [9, "jed-mapping"], [9, "id1"], [68, "jed-mapping"], [70, "jed-mapping"], [71, "jed-mapping"], [72, "jed-mapping"], [73, "jed-mapping"], [74, "jed-mapping"], [75, "jed-mapping"]], "JED mapping \u2014 MCs with IOBs": [[2, "jed-mapping-mcs-with-iobs"], [3, "jed-mapping-mcs-with-iobs"], [6, "jed-mapping-mcs-with-iobs"], [7, "jed-mapping-mcs-with-iobs"]], "JED mapping \u2014 MCs without IOBs": [[2, "jed-mapping-mcs-without-iobs"], [3, "jed-mapping-mcs-without-iobs"], [6, "jed-mapping-mcs-without-iobs"], [7, "jed-mapping-mcs-without-iobs"]], "JED mapping \u2014 macrocells with IOB": [[68, "jed-mapping-macrocells-with-iob"]], "JED mapping \u2014 macrocells without IOB": [[68, "jed-mapping-macrocells-without-iob"]], "JED structure": [[68, "jed-structure"]], "JTAG interface": [[13, "jtag-interface"], [35, "jtag-interface"], [79, "jtag-interface"]], "LLH": [[42, "llh"]], "LLH.CLKB.S3A": [[42, "llh-clkb-s3a"]], "LLH.CLKT.S3A": [[42, "llh-clkt-s3a"]], "LLV.S3A": [[42, "llv-s3a"]], "LLV.S3E": [[42, "llv-s3e"]], "LUT RAM": [[38, "lut-ram"], [52, "lut-ram"]], "LUTs": [[38, "luts"], [52, "luts"]], "Local control terms": [[80, "local-control-terms"]], "Long line splitters": [[42, "long-line-splitters"]], "MC bits": [[2, "mc-bits"], [3, "mc-bits"], [4, "mc-bits"], [5, "mc-bits"], [6, "mc-bits"], [7, "mc-bits"], [8, "mc-bits"], [9, "mc-bits"]], "Macrocell and IOB outputs": [[14, "macrocell-and-iob-outputs"], [80, "macrocell-and-iob-outputs"]], "Macrocell output \u2014 XC9500": [[36, "macrocell-output-xc9500"]], "Macrocell output \u2014 XC9500XL/XV": [[36, "macrocell-output-xc9500xl-xv"]], "Misc configuration": [[14, "misc-configuration"], [36, "misc-configuration"], [80, "misc-configuration"]], "Output multiplexers": [[52, "output-multiplexers"]], "Output multiplexers \u2014 Spartan 3": [[38, "output-multiplexers-spartan-3"]], "Output multiplexers \u2014 Virtex 4": [[38, "output-multiplexers-virtex-4"]], "Overview": [[14, "overview"], [36, "overview"], [80, "overview"]], "PCI logic": [[57, "pci-logic"]], "PPC.E": [[55, "ppc-e"]], "PPC.N": [[55, "ppc-n"]], "PPC.S": [[55, "ppc-s"]], "PPC.W": [[55, "ppc-w"]], "PT import/export": [[36, "pt-import-export"]], "Packages": [[12, "packages"], [34, "packages"], [78, "packages"]], "Part": [[17, "part"], [69, "part"]], "PowerPC holes": [[55, "powerpc-holes"], [57, "powerpc-holes"]], "Primary vertical clock spine": [[44, "primary-vertical-clock-spine"]], "Primitive outputs": [[42, "primitive-outputs"], [55, "primitive-outputs"]], "Product terms": [[14, "product-terms"], [36, "product-terms"], [80, "product-terms"]], "Programming fuses \u2014 XC9500": [[35, "programming-fuses-xc9500"]], "Programming fuses \u2014 XC9500XL/XV": [[35, "programming-fuses-xc9500xl-xv"]], "Programming sequence": [[13, "programming-sequence"], [35, "programming-sequence"], [79, "programming-sequence"]], "Project Combine": [[0, "project-combine"]], "Reading fuses \u2014 XC9500": [[35, "reading-fuses-xc9500"]], "Reading fuses \u2014 XC9500XL/XV": [[35, "reading-fuses-xc9500xl-xv"]], "Register": [[14, "register"], [80, "register"]], "Registers": [[38, "registers"], [52, "registers"]], "Secondary vertical clock spines": [[44, "secondary-vertical-clock-spines"]], "Shift registers": [[38, "shift-registers"], [52, "shift-registers"]], "Single-port 128\u00d71 RAM": [[52, "single-port-1281-ram"]], "Single-port 16\u00d7X RAM": [[38, "single-port-16x-ram"], [52, "single-port-16x-ram"]], "Single-port 32\u00d7X RAM": [[38, "single-port-32x-ram"], [52, "single-port-32x-ram"]], "Single-port 64\u00d71 RAM": [[38, "single-port-641-ram"]], "Single-port 64\u00d7X RAM": [[52, "single-port-64x-ram"]], "Spartan 3": [[38, "spartan-3"]], "Spartan 3A DCMs": [[44, "spartan-3a-dcms"]], "Spartan 3A DSP": [[40, "spartan-3a-dsp"]], "Spartan 3A and 3A DSP BRAM columns": [[44, "spartan-3a-and-3a-dsp-bram-columns"]], "Spartan 3E BRAM columns": [[44, "spartan-3e-bram-columns"]], "Spartan 3E DCMs": [[44, "spartan-3e-dcms"]], "Spartan 6": [[40, "spartan-6"]], "Speed": [[17, "speed"], [69, "speed"]], "Speed data": [[2, "speed-data"], [3, "speed-data"], [4, "speed-data"], [5, "speed-data"], [6, "speed-data"], [7, "speed-data"], [8, "speed-data"], [9, "speed-data"], [18, "speed-data"], [19, "speed-data"], [20, "speed-data"], [21, "speed-data"], [22, "speed-data"], [23, "speed-data"], [24, "speed-data"], [25, "speed-data"], [26, "speed-data"], [27, "speed-data"], [28, "speed-data"], [29, "speed-data"], [30, "speed-data"], [31, "speed-data"], [70, "speed-data"], [71, "speed-data"], [72, "speed-data"], [73, "speed-data"], [74, "speed-data"], [75, "speed-data"]], "Sum of products": [[52, "sum-of-products"]], "Sum term, LUT2": [[80, "sum-term-lut2"]], "Sum term, XOR gate": [[14, "sum-term-xor-gate"], [36, "sum-term-xor-gate"]], "TERM.E": [[55, "term-e"]], "TERM.N": [[55, "term-n"]], "TERM.S": [[55, "term-s"]], "TERM.W": [[55, "term-w"]], "Terminators": [[42, "terminators"], [55, "terminators"]], "The BRAM bel": [[51, "the-bram-bel"]], "The CLKC clock center tile": [[39, "the-clkc-clock-center-tile"]], "The CLKC_50A clock center tile": [[39, "the-clkc-50a-clock-center-tile"]], "The GCLKC clock spine distribution tiles": [[53, "the-gclkc-clock-spine-distribution-tiles"]], "The GCLKH clock row distribution tiles": [[39, "the-gclkh-clock-row-distribution-tiles"]], "The GCLKVC clock spine distribution tiles": [[39, "the-gclkvc-clock-spine-distribution-tiles"]], "The GCLKVM secondary clock center tiles": [[39, "the-gclkvm-secondary-clock-center-tiles"]], "The MULT bel \u2014 Spartan 3E and Spartan 3A": [[51, "the-mult-bel-spartan-3e-and-spartan-3a"]], "The MULT bel \u2014 Virtex 2 and Spartan 3": [[51, "the-mult-bel-virtex-2-and-spartan-3"]], "The clock row distribution tiles": [[53, "the-clock-row-distribution-tiles"]], "Tile": [[17, "tile"], [69, "tile"]], "Todo": [[1, "id1"], [12, "id1"], [13, "id1"], [13, "id2"], [13, "id3"], [13, "id4"], [14, "id1"], [14, "id2"], [14, "id3"], [14, "id4"], [14, "id5"], [14, "id6"], [14, "id7"], [14, "id8"], [14, "id9"], [14, "id10"], [35, "id1"], [35, "id2"], [36, "id1"], [36, "id2"], [38, "id1"], [39, "id1"], [39, "id2"], [39, "id3"], [39, "id4"], [39, "id5"], [39, "id6"], [39, "id7"], [39, "id8"], [39, "id9"], [39, "id10"], [40, "id1"], [41, "id1"], [43, "id1"], [44, "id1"], [46, "id1"], [50, "id1"], [51, "id1"], [51, "id2"], [51, "id3"], [51, "id4"], [52, "id1"], [52, "id2"], [52, "id3"], [53, "id1"], [53, "id2"], [53, "id3"], [53, "id4"], [53, "id5"], [54, "id1"], [55, "id1"], [56, "id1"], [57, "id1"], [58, "id1"], [58, "id2"], [58, "id3"], [60, "id1"], [64, "id1"], [67, "id1"], [79, "id1"], [79, "id2"], [79, "id3"], [80, "id1"], [80, "id2"]], "Top level": [[17, "top-level"], [69, "top-level"]], "Tristate buses and TBUFs": [[52, "tristate-buses-and-tbufs"]], "UIM IBUF bits": [[23, "uim-ibuf-bits"]], "UIM and FB inputs \u2014 XC9500": [[36, "uim-and-fb-inputs-xc9500"]], "UIM and FB inputs \u2014 XC9500XL/XV": [[36, "uim-and-fb-inputs-xc9500xl-xv"]], "Universal control terms": [[80, "universal-control-terms"]], "Virtex 4": [[38, "virtex-4"]], "Wide multiplexers": [[38, "wide-multiplexers"], [52, "wide-multiplexers"]], "Write protection \u2014 XC9500": [[35, "write-protection-xc9500"]], "Write protection \u2014 XC9500XL/XV": [[35, "write-protection-xc9500xl-xv"]], "XC2C128, XA2C128": [[2, "xc2c128-xa2c128"]], "XC2C256, XA2C256": [[3, "xc2c256-xa2c256"]], "XC2C32": [[4, "xc2c32"]], "XC2C32A, XA2C32A": [[5, "xc2c32a-xa2c32a"]], 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52, 62], "circuit": 35, "circuitri": [35, 36, 38, 44, 52], "cki0010": [39, 53], "cki010": 39, "ckil00010": 39, "ckir00100": 39, "clamp": [13, 35, 79], "classic": [36, 80], "clb": [38, 44, 52, 57], "clear": 35, "clk": [14, 36, 38, 39, 42, 44, 51, 52, 53, 55, 58, 80], "clk0": [39, 42, 47, 53, 55, 61, 65], "clk00": 47, "clk000": 65, "clk00001": 65, "clk00001000001": 55, "clk01": 61, "clk0int": [42, 55], "clk1": [39, 42, 47, 53, 55, 61, 65], "clk100": 65, "clk10001000010": 55, "clk10010": 65, "clk11": [47, 61], "clk1int": [42, 55], "clk2": [39, 42, 53, 55, 61], "clk20001000001": 55, "clk21": 61, "clk2int": [42, 55], "clk3": [39, 42, 53, 55, 61], "clk30001000010": 55, "clk30mux": 42, "clk31": 61, "clk3int": [42, 55], "clk4": 53, "clk5": 53, "clk6": 53, "clk7": 53, "clk_ddr": [2, 3, 4, 5, 6, 7, 8, 9], "clk_inv": [2, 3, 4, 5, 6, 7, 8, 9, 36, 68, 80], "clk_inv35": 16, "clk_mux": [2, 3, 4, 5, 6, 7, 8, 9, 36, 68, 80], "clk_mux3433": 16, "clk_mux3736": 15, "clka": 58, "clkainv": 48, "clkb": [44, 57, 58], "clkbinv": 48, "clkc": [41, 44, 57], "clkc_50a": [41, 44], "clkc_mux": 59, "clkdiv_delay_en": [2, 3, 6, 7], "clkdiv_div": [2, 3, 6, 7], "clkdiv_en": [2, 3, 6, 7], "clkfb011": 42, "clkin011": 42, "clkinv": [40, 49, 62, 63, 66], "clkinvdsp0": 66, "clkinvdsp1": 66, "clkinvslice0": [49, 62], "clkinvslice1": 62, "clkl": 44, "clkmux": [39, 53], "clkpad": [42, 57], "clkpad0000100000100": 55, "clkpad0001000000010000": 42, "clkpad1000100001000": 55, "clkpad1001000000100000": 42, "clkpad2001000000100": 55, "clkpad2001000001000000": 42, "clkpad3001000001000": 55, "clkpad3001000010000000": 42, "clkpad4010000000100": 55, "clkpad5010000001000": 55, "clkpad6100000000100": 55, "clkpad7100000001000": 55, "clkr": 44, "clkt": [44, 57], "clock": [11, 12, 34, 35, 36, 37, 38, 41, 42, 43, 46, 51, 52, 54, 56, 58, 69, 78, 80], "clock_invert_m": 63, "clock_invert_p": 63, "clock_invert_pdsp1": 63, "clockwis": [44, 57], "close": [44, 51], "closest": 44, "cmo": 14, "cnr": [44, 57], "code": 35, "col": [2, 3, 4, 5, 6, 7, 8, 9, 70, 71, 72, 73, 74, 75], "col_hi": [15, 16], "col_lo": [15, 16], "coloc": [44, 51], "column": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 35, 38, 39, 42, 51, 52, 53, 55, 57, 68, 69, 70, 71, 72, 73, 74, 75, 77, 79], "comb": 36, "comb0": 15, "comb1": 16, "combin": [36, 38, 42, 51, 52, 55, 80], "combination": 51, "combinatori": [14, 36, 80], "come": [12, 34, 36, 38, 44, 51, 57, 78, 80], "commerci": [17, 69], "commonli": 68, "compat": [12, 34, 78], "compens": 52, "complet": [12, 13, 16, 34, 35, 36, 68, 78], "complex": [15, 16], "comput": [51, 68], "concaten": [15, 16, 51, 58], "conceptu": 44, "config": [15, 16, 68], "configur": [11, 12, 15, 33, 34, 35, 37, 39, 41, 42, 43, 50, 54, 55, 56, 57, 64, 68, 77], "configuraton": [15, 16], "conjunct": 36, "connect": [35, 36, 38, 44, 51, 52, 55, 56, 58, 79, 80], "consid": 35, "consist": [35, 36, 51], "const": [13, 14, 35, 36, 38, 52, 79, 80], "constant": [36, 38, 52], "constraint": 12, "construct": 80, "consult": 15, "contain": [15, 17, 34, 38, 42, 43, 44, 51, 52, 55, 56, 57, 58, 79, 80], "content": [35, 38, 52], "contigu": [15, 16], "continu": 35, "control": [12, 14, 35, 36, 38, 43, 52, 56, 58], "convert": [15, 16], "coolrunn": [0, 12, 14], "coordin": [16, 17, 36, 44, 57, 68, 69, 80], "core": [12, 34, 36, 42, 55, 56, 57, 78, 80], "corner": [42, 43, 44, 54, 55, 56, 57], "correct": 58, "correspond": [12, 14, 15, 16, 17, 34, 35, 36, 38, 39, 40, 42, 44, 51, 52, 53, 55, 57, 58, 69, 80], "could": 35, "count": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 38, 44, 51, 57, 70, 71, 72, 73, 74, 75], "cout": [38, 52], "coutmux": 62, "coutmuxslice1": 62, "cover": 80, "cp132": [2, 3, 12], "cp56": [4, 5, 8, 9, 12, 71, 78], "cpld": [0, 12, 34, 36, 78, 80], "crammod": 62, "creat": [42, 55, 57], "creg": [40, 59, 63, 66], "cregdsp": 40, "cregdsp0": [63, 66], "cregdsp1": 66, "cross": [44, 55], "cs144": [20, 21, 34, 72, 78], "cs280": [24, 25, 34, 73, 78], "cs48": [26, 27, 28, 30, 31, 34, 70, 71, 78], "ct": 14, "ct4111": [2, 3, 4, 5, 6, 7, 8, 9], "ct501": [2, 3, 4, 5, 6, 7, 8, 9], "ct601": [2, 3, 4, 5, 6, 7, 8, 9], "ct70001": [2, 3, 4, 5, 6, 7, 8, 9], "ctc": 14, "cte": 14, "ctlgo001": 42, "ctlmode011": 42, "ctlosc1001": 42, "ctlosc2001": 42, "ctlsel0011": 42, "ctlsel1101": 42, "ctlsel2100": 42, "ctr": 14, "ctrl0": 65, "ctrl00001": 65, "ctrl1": 65, "ctrl10010": 65, "ctrl2": 65, "ctrl3": 65, "curious": [12, 34], "current": [35, 38, 52], "cut": [43, 44], "cv100": [2, 12], "cv64": [5, 9, 12], "cx0": 62, "cx0100": 62, "cx1": 62, "cx10": 62, "cx1010": 62, "cy0": 49, "cy0111": 62, "cy0f": [38, 52], "cy0g": [38, 52], "cy1010": 62, "cy110": 62, "cycl": [35, 51, 58], "cyinit": [38, 49, 52, 62], "cyinitslice0": [38, 49, 62], "cyinitslice1": [38, 49, 62], "cyinitslice2": 38, "cyinitslice3": 38, "cyself": [38, 49, 52], "cyselfslice0": 49, "cyselfslice1": [38, 49], "cyselfslice3": 38, "cyselg": [38, 49, 52], "cyselgslice0": [49, 52], "cyselgslice1": [38, 49, 52], "cyselgslice3": 38, "d": [14, 36, 51, 58, 80], "d0_mux": 66, "d1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 70, 71, 72, 73, 74, 75, 80], "d10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 71, 72, 73, 74, 75], "d10_mux": 66, "d11": [3, 6, 7, 20, 21, 22, 23, 24, 25, 72, 73, 74, 75], "d11_mux": 66, "d12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 72, 73, 74, 75], "d12_mux": 66, "d13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 72, 73, 74, 75], "d13_mux": 66, "d14": [2, 3, 6, 7, 22, 23, 24, 25, 73, 74, 75], "d14_mux": 66, "d15": [3, 6, 7, 22, 23, 24, 25, 73, 74, 75], "d15_mux": 66, "d16": [3, 6, 7, 22, 23, 24, 25, 73, 74, 75], "d16_mux": 66, "d17": [6, 7, 22, 23, 24, 25, 73, 74, 75], "d17_mux": 66, "d18": [6, 7, 22, 23, 24, 25, 73, 74, 75], "d18_mux": 66, "d19": [6, 7, 22, 23, 24, 25, 73, 74, 75], "d19_mux": 66, "d1_mux": 66, "d2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 70, 71, 72, 73, 74, 75], "d20": [6, 7, 22, 23, 24, 74, 75], "d20_mux": 66, "d21": [6, 7, 22, 23, 74, 75], "d21_mux": 66, "d22": [6, 7, 22, 23, 74, 75], "d22_mux": 66, "d23": [22, 23], "d23_mux": 66, "d24": [22, 23], "d24_mux": 66, "d25": [22, 23], "d26": [22, 23], "d2_mux": 66, "d3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 70, 71, 72, 73, 74, 75], "d3_mux": 66, "d4": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 70, 71, 72, 73, 74, 75], "d4_mux": 66, "d5": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 72, 73, 74, 75], "d5_mux": 66, "d5ffinit": 62, "d5ffinitslice0": 62, "d5ffmux": 62, "d5ffsr": 62, "d5ffsrinit": 62, "d5ffsrinitslice0": 62, "d5ffsrslice1": 62, "d5q0": 62, "d5q0100": 62, "d6": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 70, 71, 72, 73, 74, 75], "d6_mux": 66, "d6lut": 62, "d7": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 70, 71, 72, 73, 74, 75], "d7_mux": 66, "d8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 71, 72, 73, 74, 75], "d8_mux": 66, "d9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 72, 73, 74, 75], "d9_mux": 66, "data": [10, 12, 14, 17, 32, 35, 38, 40, 42, 44, 48, 51, 52, 55, 57, 58, 68, 69, 76, 80], "data0": [42, 55], "data00001000001": 55, "data00001000100": 55, "data00mux": 42, "data1": [42, 55], "data10": 42, "data10001000010": 55, "data10001001000": 55, "data101mux": 42, "data10mux": 42, "data11": 42, "data110mux": 42, "data11mux": 42, "data12": 42, "data13": 42, "data130mux": 42, "data131mux": 42, "data14": 42, "data140mux": 42, "data15": 42, "data16": 42, "data160mux": 42, "data17": 42, "data170mux": 42, "data171mux": 42, "data18": 42, "data180mux": 42, "data181mux": 42, "data19": 42, "data190mux": 42, "data2": [42, 55], "data20": 42, "data20001000100": 55, "data20001010000": 55, "data20mux": 42, "data21": 42, "data210mux": 42, "data21mux": 42, "data22": 42, "data220mux": 42, "data221mux": 42, "data23": 42, "data24": 42, "data240mux": 42, "data25": 42, "data250mux": 42, "data251mux": 42, "data26": 42, "data261mux": 42, "data27": 42, "data270mux": 42, "data28": 42, "data29": 42, "data290mux": 42, "data3": [42, 55], "data30": 42, "data30001001000": 55, "data30001100000": 55, "data300mux": 42, "data301mux": 42, "data30mux": 42, "data31": 42, "data4": [42, 55], "data40001000001": 55, "data40001000010": 55, "data40001000100": 55, "data5": [42, 55], "data50001000010": 55, "data50001000100": 55, "data50001001000": 55, "data50mux": 42, "data51mux": 42, "data6": [42, 55], "data60001000100": 55, "data60001001000": 55, "data60001010000": 55, "data60mux": 42, "data7": [42, 55], "data70001001000": 55, "data70001010000": 55, "data70001100000": 55, "data8": 42, "data80mux": 42, "data9": 42, "data90mux": 42, "data91mux": 42, "data_width_": 51, "data_width_a": 51, "data_width_b": 51, "databas": [11, 15, 16, 33, 35, 36, 68, 77, 79, 80], "datap": [51, 58], "datareg": 13, "datastream": [17, 69], "dbl": [39, 42, 47, 53, 55, 61, 65], "dbl0001010000": 65, "dbl0001100000": 65, "dbl0010010000": 65, "dbl0010100000": 65, "dbl0100010000": 65, "dbl0100100000": 65, "dbl1000010000": 65, "dbl1000100000": 65, "dci": [43, 55, 56], "dcm": [43, 51, 54, 57], "dcm_out100": 39, "dcm_out_l0100": [39, 53], "dcm_out_l01000": 39, "dcm_out_r1000": [39, 53], "dcm_out_r10000": 39, "dcmclk": 55, "dcmclk0": 55, "dcmclk00001000001": 55, "dcmclk1": 55, "dcmclk10001000010": 55, "dcmclk2": 55, "dcmclk20001000001": 55, "dcmclk3": 55, "dcmclk30001000010": 55, "dcy0": 62, "dcy0slice0": 62, "dcy0slice1": 62, "dd1": 34, "ddel_a": 51, "ddel_a_default": 51, "ddel_b": 51, "ddel_b_default": 51, "ddr": [43, 56], "deal": [44, 55, 57], "decod": 58, "dedic": [12, 14, 34, 36, 38, 43, 44, 51, 52, 55, 56, 57, 58, 69, 78, 80], "def": [15, 16], "default": [17, 35, 54], "defin": 80, "del_clk_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "del_d_q_comb": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_d_q_latch": [2, 3, 4, 5, 6, 7, 8, 9, 70, 71, 72, 73, 74, 75], "del_exp_d": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_exp_exp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_d": [2, 3, 4, 5, 6, 7, 8, 9, 70, 71, 72, 73, 74, 75], "del_ibuf_fclk": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "del_ibuf_fo": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_fsr": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "del_ibuf_plain": [2, 3, 4, 5, 6, 7, 8, 9], "del_ibuf_schmitt": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_ct": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_d_hp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_d_lp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_fbn": [70, 71, 72, 73, 74, 75], "del_imux_or": [2, 3, 4, 5, 6, 7, 8, 9, 70, 71, 72, 73, 74, 75], "del_imux_pt": [2, 3, 4, 5, 6, 7, 8, 9, 70, 71, 72, 73, 74, 75], "del_imux_pt_c": [20, 21, 24, 25, 27, 28, 30, 31], "del_imux_pt_clk": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "del_imux_pt_o": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_pt_sr": [20, 21, 24, 25, 27, 28, 30, 31], "del_mc_fo": [2, 3, 4, 5, 6, 7, 8, 9], "del_obuf_fast": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "del_obuf_o": [2, 3, 4, 5, 6, 7, 8, 9, 70, 71, 72, 73, 74, 75], "del_obuf_slow": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "del_pt_ut": [70, 71, 72, 73, 74, 75], "del_sr_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "del_uim_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 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73, 74, 75], "p47": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p48": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p49": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p5": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "p50": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p51": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p52": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p53": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p54": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p55": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p56": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p57": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p58": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p59": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p6": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "p60": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p61": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p62": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p63": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p64": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 71, 72, 73, 74, 75], "p65": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p66": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p67": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p68": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p69": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p7": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "p70": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p71": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p72": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p73": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p74": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p75": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p76": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p77": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p78": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p79": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p8": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "p80": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p81": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p82": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p83": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p84": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p85": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p86": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p87": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p88": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p89": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p9": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "p90": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p91": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p92": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p93": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p94": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p95": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p96": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p97": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p98": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p99": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 71, 72, 73, 74, 75], "p_d": 51, "packag": [11, 17, 33, 36, 43, 69, 77, 79], "pad": [2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 16, 17, 34, 36, 42, 55, 69, 78, 80], "pair": [17, 44, 52, 58, 69], "parallel": 16, "paramet": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 69, 70, 71, 72, 73, 74, 75], "pariti": [51, 58], "part": [2, 3, 4, 5, 6, 7, 8, 9, 12, 33, 34, 38, 44, 52, 58, 70, 71, 72, 73, 74, 75, 77, 79], "partial": [34, 51, 58, 79], "particip": 36, "particular": [17, 69], "particularli": 38, "pass": [35, 42, 44, 55], "passthrough": 55, "patdet1": 63, "path": [36, 51], "pattern": [57, 63, 66], "pattern0": [63, 66], "pc44": [4, 5, 8, 9, 12, 26, 27, 28, 29, 30, 31, 34, 70, 71, 78], "pc84": [18, 29, 34], "pci": [43, 44, 54, 55, 56], "pci000": 55, "pci100": 55, "pcilog": [44, 54, 55, 57], "pcilogics": [39, 44], "pent": 65, "pent00010100": 65, "pent00011000": 65, "pent00100100": 65, "pent00101000": 65, "pent01000100": 65, "pent01001000": 65, "pent10000100": 65, "pent10001000": 65, "per": [12, 14, 17, 33, 34, 35, 36, 38, 42, 43, 44, 51, 55, 56, 58, 68, 69, 79, 80], "perform": [35, 36, 80], "perman": 39, "person": 35, "phi": 35, "philip": [78, 79], "physic": [42, 68], "pick": [38, 52, 58], "picosecond": [17, 69], "pin": [10, 11, 14, 17, 32, 33, 36, 38, 51, 52, 55, 58, 69, 76, 77, 79, 80], "pipelin": [43, 51, 58], "pitch": [12, 34, 78], "pla": [68, 80], "place": [12, 35, 36, 42, 44, 55], "placement": 44, "plain": [12, 17, 34, 44, 56, 57, 58, 69, 78], "plain0": [4, 5, 8, 9], "plain00": [2, 3, 6, 7], "plane": [51, 58, 68, 69], "plastic": [12, 34, 78], "platic": 34, "plcc": [12, 34, 78], "pmv": [43, 56], "point": 52, "polar": [34, 36, 80], "por": 80, "port": [43, 51, 55, 56, 58], "port_en": [69, 70, 71, 72, 73, 74, 75, 78, 80], "porta_attr": 48, "portb_attr": 48, "posedg": [36, 38, 52, 80], "posit": [35, 68], "possess": 35, "possibl": [17, 42, 51, 55, 69, 80], "potenti": 36, "power": [12, 17, 34, 35, 36, 69, 78, 80], "powerpc": [52, 54, 56, 58], "ppc": [54, 57], "pq100": [18, 19, 29, 34], "pq160": [18, 19, 22, 34], "pq208": [3, 6, 7, 12, 24, 25, 34, 73, 74, 75, 78], "practic": 55, "pre": 36, "preassign": 12, "precyinit": 62, "precyinit0": 62, "prefix": 55, "preg": [40, 51, 59, 63, 66], "preg_clkinvers": 51, "pregdsp": 40, "prepar": 35, "present": [12, 35, 42, 44, 55], "pretend": [36, 80], "pretti": 51, "prevent": [34, 55], "previou": [35, 38, 51, 52, 58, 80], "previous": [51, 58], "primari": [39, 41, 42], "primit": [38, 41, 43, 44, 51, 52, 54, 56, 57, 58], "prioriti": [38, 51, 52], "pro": [53, 55, 56, 57], "problem": 34, "process": [38, 43, 52, 56], "prod": [38, 52], "prod010": 38, "prod100": [38, 52], "prod11": 49, "product": [11, 33, 38, 54, 77, 79], "program": [11, 14, 15, 16, 17, 33, 36, 68, 77, 78, 80], "program_tim": 17, "programm": [35, 36, 42, 55, 80], "progress": 35, "propag": [36, 38, 52], "protect": [14, 36, 68, 80], "provid": [17, 44, 57, 68, 69], "psclk101": 42, "psen010": 42, "psincdec100": 42, "pt": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 68, 69, 70, 71, 72, 73, 74, 75, 80], "pt0": [16, 80], "pt00": [2, 3, 4, 5, 6, 7, 8, 9, 15], "pt000": 16, "pt0010": [2, 3, 4, 5, 6, 7, 8, 9], "pt01": [2, 3, 4, 5, 6, 7, 8, 9], "pt010": 68, "pt1": [15, 68], "pt11": 16, "pt110": [2, 3, 4, 5, 6, 7, 8, 9], "pt111": 15, "pt2": 36, "pt201": 16, "pt3": 36, "pt310": 16, "pt4": 14, "pt40": 80, "pt5": 14, "pt6": 14, "pt7": 14, "pt8": 80, "pt9": 80, "pt_col": [68, 69], "pt_inv10": [2, 3, 4, 5, 6, 7, 8, 9], "pta": 14, "ptb": 14, "ptc": 14, "pte2omux": 42, "pte2omux0": 42, "pte2omux1": 42, "pte2omux2": 42, "pte2omux3": 42, "pull": [33, 35, 80], "pullup": [42, 55, 80], "pullup0000": 39, "pullup000000": [42, 53], "pullup00000000": [42, 47, 55], "pullup000000000": 55, "pullup0000000000": [42, 55, 65], "pullup00000000000": 65, "pullup000000000000": 55, "pullup0000000000000": [55, 61], "pullup000000000000000": 42, "pullup1": [2, 3, 4, 5, 6, 7, 8, 9], "pullup111": 68, "pullup_dis": [15, 16, 36], "puls": [38, 52, 80], "purpos": [12, 15, 34, 35, 36, 38, 51, 52, 55, 58, 78, 79, 80], "put": 35, "q": [14, 38, 80], "qf32": 12, "qf48": 12, "qfg32": [5, 12], "qfg48": [9, 12], "qfn": 12, "qfp": [12, 34, 78], "quad": [47, 65], "quadrant": 44, "quantiti": 12, "quit": 36, "r1": [3, 6, 7, 22, 23, 24, 25, 73, 74, 75], "r10": [3, 6, 7, 24, 25, 73, 74, 75], "r11": [3, 6, 7, 24, 25, 73, 74, 75], "r12": [3, 6, 7, 24, 25, 73, 74, 75], "r13": [3, 6, 7, 24, 25, 73, 74, 75], "r14": [3, 6, 7, 24, 25, 73, 74, 75], "r15": [3, 6, 7, 24, 25, 73, 74, 75], "r16": [3, 6, 7, 24, 25, 73, 74, 75], "r17": [24, 25, 73], "r18": [24, 25, 73], "r19": [6, 7, 24, 25, 73, 74, 75], "r2": [3, 6, 7, 22, 23, 24, 25, 73, 74, 75], "r20": [6, 7, 24, 74, 75], "r21": [6, 7, 74, 75], "r22": [6, 7, 74, 75], "r23": [22, 23], "r24": [22, 23], "r25": [22, 23], "r26": [22, 23], "r3": [3, 6, 7, 22, 23, 24, 25, 73, 74, 75], "r4": [3, 6, 7, 22, 23, 24, 25, 73, 74, 75], "r5": [3, 6, 7, 24, 25, 73, 74, 75], "r6": [3, 6, 7, 24, 25, 73, 74, 75], "r7": [3, 6, 7, 24, 25, 73, 74, 75], "r8": [3, 6, 7, 24, 25, 73, 74, 75], "r9": [3, 6, 7, 24, 25, 73, 74, 75], "rail": [12, 34], "ram": [37, 42, 43, 50, 54, 55, 56, 60], "ram0": 58, "ram32011": 62, "ram64001": 62, "ram_extension_": 58, "ram_extension_a": 58, "ram_extension_b": 58, "ramb16": 58, "ramb16_": 51, "ramb16bwe_": 51, "ramb16bwer": 51, "ramb32_s64_ecc": 58, "ramconfig": 49, "random": 35, "rang": [2, 3, 4, 5, 6, 7, 8, 9, 35, 44, 57, 68, 70, 71, 72, 73, 74, 75], "rare": 35, "rate": [14, 36, 80], "ratio": 43, "raw": 68, "rclk000011000": 61, "rclk001000100": 61, "rclk001001000": 61, "rclk010000001": 65, "rclk100011000": 61, "rclk100100010": 61, "rclk110000010": [61, 65], "rclk210000100": 65, "rclk310001000": 65, "rdclk": 58, "rdcount": 58, "rden": 58, "rderr": 58, "re": 35, "reach": [42, 55], "read": [14, 15, 16, 36, 38, 51, 52, 58, 68, 80], "read_first": [51, 58], "read_first00": 58, "read_first10": 51, "read_prot": [2, 3, 4, 5, 6, 7, 8, 9, 16, 35, 36, 68, 70, 71, 72, 73, 74, 75, 80], "read_prot_": 36, "read_prot_a": 15, "read_prot_b": 15, "read_width_": 58, "read_width_a": 58, "read_width_b": 58, "readabl": [17, 35, 36, 69], "readout": 35, "realli": [36, 51], "reason": 35, "reconfigur": [51, 58], "recovery_sr_clk": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "rectangular": [44, 57], "redund": 36, "reenter": 35, "reexport": 36, "refer": [14, 55], "referenc": [17, 69], "reflect": [42, 55], "reg": [51, 80], "reg0": [2, 3, 4, 5, 6, 7, 8, 9, 68], "reg01": [2, 3, 4, 5, 6, 7, 8, 9], "reg_d": 80, "reg_d_ireg": [68, 80], "reg_d_mux": [2, 3, 4, 5, 6, 7, 8, 9], "reg_d_shift": [68, 80], "reg_d_shift_dir": [68, 80], "reg_init": [2, 3, 4, 5, 6, 7, 8, 9, 15, 36], "reg_init42": 16, "reg_init43": 15, "reg_mod": [2, 3, 4, 5, 6, 7, 8, 9, 36, 68, 80], "reg_mode39": 16, "reg_mode40": 15, "regardless": [34, 35, 36, 80], "regb": 45, "regc": [51, 58], "regcea": 58, "region": 43, "regist": [11, 33, 36, 41, 43, 44, 51, 54, 56, 57, 58, 77], "regt": 45, "rel": 69, "relat": 51, "relev": [36, 42, 44, 55, 80], "reliabl": 79, "reload": 35, "remain": [35, 42, 44, 55, 57, 80], "remov": [34, 38, 43, 44, 55], "replac": [14, 38, 43, 44, 51, 55], "repres": [15, 16, 69], "repurpos": [42, 44, 58], "requir": [17, 35, 58], "reset": [12, 14, 34, 35, 36, 38, 42, 43, 51, 52, 55, 58, 80], "reset_match01": 66, "reset_not_match11": 66, "resistor": [36, 80], "resourc": [38, 42, 51, 52, 55], "respect": [38, 44, 52, 57, 80], "rest": [42, 55], "restrict": 51, "result": [35, 80], "retain": 80, "return": [15, 16, 35], "reus": [44, 55], "revis": [12, 35], "rewir": 55, "right": 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42, 44, 53, 55, 56, 57, 78, 80], "x0": 49, "x00000": 38, "x1": [38, 52], "xa": [12, 34], "xa2c128": [10, 11, 12], "xa2c256": [10, 11, 12], "xa2c32a": [10, 11, 12], "xa2c384": [10, 11, 12], "xa2c64a": [10, 11, 12], "xa3s1000001": 51, "xa3s100001": 51, "xa3s100e00": 51, "xa3s100e100": 51, "xa3s1200e00": 51, "xa3s1200e100": 51, "xa3s1400a00": 51, "xa3s1400a011": 51, "xa3s1400alow": 39, "xa3s1500001": 51, "xa3s150001": 51, "xa3s1600e00": 51, "xa3s1600e100": 51, "xa3s20000": 51, "xa3s200000": 51, "xa3s200a00": 51, "xa3s200a011": 51, "xa3s200alow": 39, "xa3s250e00": 51, "xa3s250e100": 51, "xa3s40000": 51, "xa3s400000": 51, "xa3s400a00": 51, "xa3s400a011": 51, "xa3s400alow": 39, "xa3s50001": 51, "xa3s5001": 51, "xa3s500e00": 51, "xa3s500e100": 51, "xa3s700a00": 51, "xa3s700a011": 51, "xa3s700alow": 39, "xa3sd1800a00": 51, "xa3sd1800a011": 51, "xa3sd1800alow": 39, "xa3sd3400a00": 51, "xa3sd3400a011": 51, "xa3sd3400alow": 39, "xa95144xl": [32, 33, 34], "xa9536xl": [32, 33, 34], "xa9572xl": [32, 33, 34], "xb": [38, 42, 52, 55], "xb00101": 38, "xbmux": [38, 52], "xbmuxslice0": 52, "xbmuxslice1": 52, "xc": [12, 34], "xc2c128": [10, 11, 12], "xc2c256": [10, 11, 12], "xc2c32": [10, 11, 12], "xc2c32a": [10, 11, 12], "xc2c384": [10, 11, 12], "xc2c512": [10, 11, 12], "xc2c64": [10, 11, 12], "xc2c64a": [10, 11, 12], "xc2v40": 57, "xc3s1000001": 51, "xc3s100001": 51, "xc3s1000l001": 51, "xc3s1000l01": 51, "xc3s100e": 44, "xc3s100e00": 51, "xc3s100e100": 51, "xc3s1200e00": 51, "xc3s1200e100": 51, "xc3s1400a00": 51, "xc3s1400a011": 51, "xc3s1400alow": 39, "xc3s1400an00": 51, "xc3s1400an011": 51, "xc3s1400anlow": 39, "xc3s1500001": 51, "xc3s150001": 51, "xc3s1500l001": 51, "xc3s1500l01": 51, "xc3s1600e00": 51, "xc3s1600e100": 51, "xc3s20000": 51, "xc3s200000": 51, "xc3s2000001": 51, "xc3s200001": 51, "xc3s200a00": 51, "xc3s200a011": 51, "xc3s200alow": 39, "xc3s200an00": 51, "xc3s200an011": 51, "xc3s200anlow": 39, "xc3s250e00": 51, "xc3s250e100": 51, "xc3s40000": 51, "xc3s400000": 51, "xc3s4000001": 51, "xc3s400001": 51, "xc3s4000l001": 51, "xc3s4000l01": 51, "xc3s400a00": 51, "xc3s400a011": 51, "xc3s400alow": 39, "xc3s400an00": 51, "xc3s400an011": 51, "xc3s400anlow": 39, "xc3s5000001": 51, "xc3s500001": 51, "xc3s50001": 51, "xc3s5001": 51, "xc3s500e00": 51, "xc3s500e100": 51, "xc3s50a": [39, 44], "xc3s50a00": 51, "xc3s50a011": 51, "xc3s50ame": 39, "xc3s50an00": 51, "xc3s50an011": 51, "xc3s50anm": 39, "xc3s700a00": 51, "xc3s700a011": 51, "xc3s700alow": 39, "xc3s700an00": 51, "xc3s700an011": 51, "xc3s700anlow": 39, "xc3sd1800a00": 51, "xc3sd1800a011": 51, "xc3sd1800alow": 39, "xc3sd3400a00": 51, "xc3sd3400a011": 51, "xc3sd3400alow": 39, "xc7200": 34, "xc7300": 34, "xc9500": [0, 12, 16, 17, 34], "xc9500xl": [0, 17, 34], "xc9500xv": [0, 16, 17, 34, 35, 36], "xc95108": [32, 33, 34, 36], "xc95144": [32, 33, 34, 36], "xc95144xl": [32, 33, 34], "xc95144xv": [32, 33, 34], "xc95216": [32, 33, 34, 36], "xc95288": [15, 17, 32, 33, 34, 36], "xc95288xl": [32, 33, 34], "xc95288xv": [32, 33, 34], "xc9536": [32, 33, 34, 36], "xc9536xl": [32, 33, 34], "xc9536xv": [32, 33, 34], "xc9572": [32, 33, 34, 36], "xc9572xl": [32, 33, 34], "xc9572xv": [32, 33, 34], "xc995288": 17, "xcr3032xl": [76, 77, 78, 80], "xcr3064xl": [76, 77, 78], "xcr3128xl": [76, 77, 78], "xcr3256xl": [76, 77, 78], "xcr3384xl": [76, 77, 78, 80], "xcr3512xl": [76, 77, 78, 80], "xilinx": [0, 12, 34, 38, 51, 52, 78, 79], "xl": 36, "xmux": 38, "xor": [11, 33, 80], "xor00": [2, 3, 4, 5, 6, 7, 8, 9], "xor0010": 62, "xor010": 62, "xor0110": 62, "xor1": [2, 3, 4, 5, 6, 7, 8, 9], "xor_mux": [2, 3, 4, 5, 6, 7, 8, 9], "xorci": [38, 52], "xpla": 78, "xpla2": 78, "xpla3": [0, 12, 68, 69, 78, 80], "xq": [38, 42, 52, 55], "xv": 33, "xx": [2, 6, 7, 15, 16, 26, 27, 28, 70, 71, 72, 73, 74, 75], "xxx": [6, 7, 20, 21, 29, 30, 31, 70, 71, 80], "xxxx": [2, 6, 8, 9, 18, 19, 22, 29, 68, 70, 71, 72, 73, 74, 75], "xxxxx": [3, 4, 5, 8, 9, 19, 20, 21, 22, 23, 24, 25, 68, 70, 71, 73, 74], "xxxxxx": [3, 4, 5, 8, 9, 23, 75], "xxxxxxx": [2, 3, 4, 5, 6, 7], "xxxxxxxx": [4, 5, 6, 7, 15, 16, 70, 74], "xxxxxxxxx": [3, 4, 5, 6, 8, 9, 15, 16], "xxxxxxxxxx": [3, 9], "xxxxxxxxxxxx": 2, "xxxxxxxxxxxxxxx": [2, 6, 7, 72, 73, 74, 75], "xxxxxxxxxxxxxxxx": [7, 8, 9], "xxxxxxxxxxxxxxxxx": 71, "xxxxxxxxxxxxxxxxxx": 23, "xxxxxxxxxxxxxxxxxxxxxxxxxxx": 72, "xxxxxxxxxxxxxxxxxxxxxxxxxxxx": 2, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": [2, 3, 4, 5, 6, 7, 8, 9], "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 73, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": [3, 70, 71], "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 74, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 6, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 75, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 7, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 72, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 73, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 75, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 75, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 74, "xy": [38, 42, 52, 55], "y": [38, 42, 52, 55], "y0": 49, "y00000": 38, "y1": [6, 7, 22, 23, 24, 38, 52, 74, 75], "y10": [6, 7, 24, 74, 75], "y11": [6, 7, 24, 74, 75], "y12": [6, 7, 24, 74, 75], "y13": [6, 7, 24, 74, 75], "y14": [6, 7, 24, 74, 75], "y15": [6, 7, 24, 74, 75], "y16": [6, 7, 24, 74, 75], "y17": [6, 7, 24, 74, 75], "y18": [6, 7, 24, 74, 75], "y19": [6, 7, 24, 74, 75], "y2": [6, 7, 22, 23, 24, 74, 75], "y20": [6, 7, 24, 74, 75], "y21": [6, 7, 74, 75], "y22": [6, 7, 74, 75], "y23": [22, 23], "y24": [22, 23], "y25": [22, 23], "y26": [22, 23], "y3": [6, 7, 22, 23, 24, 74, 75], "y4": [6, 7, 22, 23, 24, 74, 75], "y5": [6, 7, 24, 74, 75], "y6": [6, 7, 24, 74, 75], "y7": [6, 7, 24, 74, 75], "y8": [6, 7, 24, 74, 75], "y9": [6, 7, 24, 74, 75], "yb": [38, 42, 52, 55], "yb00101": 38, "ybmux": [38, 49, 52], "ybmuxslice0": 49, "ybmuxslice1": 49, "ymux": 38, "you": 35, "your": 35, "yq": [38, 42, 52, 55], "z": 35, "zero": 80, "zia": [14, 77, 79], "zia_gclk": [68, 80], "zia_gclk0_en": [70, 71, 72, 73, 74, 75], "zia_gclk1_en": [70, 71, 72, 73, 74, 75], "zia_gclk2_en": [70, 71, 72, 73, 74, 75], "zia_gclk3_en": [70, 71, 72, 73, 74, 75], "\u00b5": [17, 35]}, "titles": ["Project Combine", "Bitstream structure", "XC2C128, XA2C128", "XC2C256, XA2C256", "XC2C32", "XC2C32A, XA2C32A", "XC2C384, XA2C384", "XC2C512", "XC2C64", "XC2C64A, XA2C64A", "Database \u2014 devices", "Xilinx Coolrunner II CPLDs", "Introduction", "JTAG interface", "Device structure", "Bitstream structure \u2014 XC9500", "Bitstream structure \u2014 XC9500XL/XV", "Database schema", "XC95108", "XC95144", "XC95144XL, XA95144XL", "XC95144XV", "XC95216", "XC95288", "XC95288XL", "XC95288XV", "XC9536", "XC9536XL, XA9536XL", "XC9536XV", "XC9572", "XC9572XL, XA9572XL", "XC9572XV", "Database \u2014 devices", "Xilinx XC9500, XC9500XL, XC9500XV CPLDs", "Introduction", "JTAG interface", "Device structure", "Xilinx FPGAs", "Configurable Logic Block \u2014 Spartan 3, Virtex 4", "Clock interconnect", "DSP \u2014 Spartan 3A DSP, Spartan 6", "Xilinx Spartan 3 FPGAs", "General interconnect", "Introduction", "Device geometry", "Clock interconnect", "Xilinx Spartan 6 FPGAs", "General interconnect", "Block RAM \u2014 Virtex", "Configurable Logic Block \u2014 Virtex", "Xilinx Virtex, Virtex E, Spartan 2, Spartan 2E FPGAs", "Block RAM \u2014 Virtex 2, Spartan 3", "Configurable Logic Block", "Clock interconnect", "Xilinx Virtex 2 FPGAs", "General interconnect", "Introduction", "Device geometry", "Block RAM", "DSP", "Xilinx Virtex 4 FPGAs", "Interconnect", "Configurable Logic Block \u2014 Virtex 5, Virtex 6, Series 7, Spartan 6", "DSP", "Xilinx Virtex 5 FPGAs", "Interconnect \u2014 Virtex 5, Virtex 6, Series 7", "DSP", "Xilinx Virtex 6 FPGAs", "Bitstream structure", "Database schema", "XCR3032XL", "XCR3064XL", "XCR3128XL", "XCR3256XL", "XCR3384XL", "XCR3512XL", "Database \u2014 devices", "Xilinx XPLA3 CPLDs", "Introduction", "JTAG interface", "Device structure"], "titleterms": {"": [39, 55], "03": 42, "1": [38, 52], "12": 42, "128": 52, "16": [38, 52], "2": [50, 51, 54], "2e": 50, "3": [38, 41, 51], "32": [38, 52], "3a": [40, 44, 51], "3e": [44, 51], "4": [38, 60], "5": [62, 64, 65], "6": [40, 46, 62, 65, 66, 67], "64": [38, 52], "7": [62, 65, 66], "AND": 15, "The": [39, 51, 53], "aim": 14, "attribut": 39, "b": 53, "b0": 55, "b123": 55, "backbon": [42, 55], "bank": [14, 44, 57], "bclkpad": 55, "bel": 51, "bit": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 68, 69, 70, 71, 72, 73, 74, 75], "bitsteam": 47, "bitstream": [1, 15, 16, 38, 39, 40, 42, 44, 45, 47, 48, 49, 51, 52, 53, 55, 57, 58, 59, 61, 62, 63, 65, 66, 68], "blank": 35, "block": [38, 48, 49, 51, 52, 58, 62], "bond": [17, 69], "bot": 53, "bottom": [39, 45, 53, 55], "boundari": [13, 35, 79], "bram": [42, 44, 51, 55, 65], "bu": [36, 53], "buffer": [14, 15, 36, 44, 57, 80], "buse": 52, "carri": [38, 52], "center": 39, "check": 35, "clb": [42, 55], "clbll": 62, "clblm": 62, "clexl": 62, "clexm": 62, "clk_b": 55, "clk_t": 55, "clkb": [39, 42, 53], "clkc": 39, "clkc_50a": 39, "clkl": 39, "clkpad": 55, "clkr": 39, "clkt": [39, 42, 53], "clock": [14, 39, 44, 45, 53, 55, 57], "cmt": 47, "cnr": 55, "column": [44, 80], "combin": 0, "configur": [14, 36, 38, 49, 52, 62, 80], "content": [0, 10, 11, 32, 33, 37, 41, 46, 50, 54, 60, 64, 67, 76, 77], "control": 80, "coolrunn": 11, "cpld": [11, 33, 77], "data": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "databas": [10, 17, 32, 69, 76], "dcm": [42, 44, 53, 55], "dcmconn": 53, "default": [39, 51], "delai": 65, "devic": [10, 12, 14, 17, 32, 34, 36, 43, 44, 56, 57, 69, 76, 78, 80], "distribut": [39, 53], "divid": 14, "dr": 35, "dsp": [40, 42, 44, 59, 63, 66], "dual": [38, 52], "dummi": 42, "e": [50, 55], "ecc": 58, "enabl": 15, "enter": 35, "eras": 35, "exit": 35, "export": 36, "fb": [14, 15, 16, 36, 68, 80], "fclk": 80, "fifo": 58, "flip": 36, "flop": 36, "format": [15, 16], "fpga": [37, 41, 46, 50, 54, 60, 64, 67], "frequenc": 35, "fuse": [15, 16, 35, 36, 68], "gate": [14, 36], "gclkc": 53, "gclkh": [39, 53], "gclkvc": 39, "gclkvm": 39, "gener": [42, 44, 47, 55, 57], "geometri": [44, 57], "global": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 36, 68, 70, 71, 72, 73, 74, 75], "gt": 55, "hole": [55, 57], "horizont": 44, "i": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "ibuf": 23, "idcod": [35, 79], "ii": 11, "import": 36, "imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 68, 70, 71, 72, 73, 74, 75], "input": [14, 15, 16, 36, 42, 55, 80], "instruct": [13, 35, 79], "int": [42, 55], "interconnect": [39, 42, 45, 47, 53, 55, 61, 65], "interfac": [13, 35, 42, 47, 55, 61, 79], "intf": [42, 47, 55, 65], "introduct": [12, 34, 43, 56, 78], "io": [44, 57], "iob": [2, 3, 6, 7, 14, 68, 80], "ioi": [42, 47, 55], "ir": [13, 35, 79], "isp": [13, 35, 79], "jed": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 68, 69, 70, 71, 72, 73, 74, 75], "jtag": [13, 35, 79], "keeper": 36, "left": [39, 48], "level": [17, 69], "line": 42, "llh": 42, "llv": 42, "local": 80, "logic": [38, 49, 52, 57, 62], "long": 42, "lr": 42, "lut": [38, 52], "lut2": 80, "macrocel": [14, 15, 16, 36, 68, 80], "map": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 68, 70, 71, 72, 73, 74, 75], "mc": [2, 3, 4, 5, 6, 7, 8, 9], "middl": 48, "misc": [14, 36, 80], "mode": [35, 58], "mult": 51, "multiplex": [38, 42, 52, 55], "n": [39, 55], "network": [14, 36, 80], "normal": 47, "o": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75], "option": [39, 51], "output": [14, 36, 38, 42, 52, 53, 55, 80], "overview": [14, 36, 80], "packag": [12, 34, 78], "part": [17, 69], "pci": 57, "per": [15, 16], "pin": [2, 3, 4, 5, 6, 7, 8, 9, 12, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34, 70, 71, 72, 73, 74, 75, 78], "port": [38, 52], "powerpc": [55, 57], "ppc": 55, "primari": 44, "primit": [42, 55], "product": [14, 15, 16, 36, 52, 68, 80], "program": [13, 35, 79], "project": 0, "protect": 35, "pt": 36, "pull": 36, "ram": [38, 48, 51, 52, 58], "read": 35, "regist": [13, 14, 35, 38, 52, 79, 80], "right": [39, 48], "row": [39, 44, 53, 57, 80], "s3": [39, 42, 51], "s3a": [39, 42, 51], "s3adsp": [42, 51], "s3e": [39, 42, 51], "scan": [13, 35, 79], "schema": [17, 69], "secondari": [39, 44], "sequenc": [13, 35, 79], "seri": [62, 65, 66], "shift": [38, 52], "side": 48, "singl": [38, 52], "sourc": [39, 53], "spartan": [38, 40, 41, 44, 46, 50, 51, 62], "speed": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 69, 70, 71, 72, 73, 74, 75], "spine": [39, 44, 53, 55, 57], "splitter": 42, "structur": [1, 14, 15, 16, 36, 44, 57, 68, 80], "sum": [14, 36, 52, 68, 80], "t": 53, "t0": 55, "t123": 55, "tabl": [43, 56], "tb": 42, "tbuf": 52, "tclkpad": 55, "term": [14, 15, 16, 36, 55, 68, 80], "termin": [42, 55], "tile": [17, 39, 42, 45, 47, 53, 55, 61, 69], "todo": [1, 12, 13, 14, 35, 36, 38, 39, 40, 41, 43, 44, 46, 50, 51, 52, 53, 54, 55, 56, 57, 58, 60, 64, 67, 79, 80], "top": [17, 39, 45, 53, 55, 69], "tristat": 52, "uim": [15, 23, 36], "uni": 39, "univers": 80, "up": 36, "v2": [53, 55], "v2p": [53, 55], "v2px": 53, "valu": 51, "vertic": 44, "virtex": [38, 48, 49, 50, 51, 54, 60, 62, 64, 65, 66, 67], "w": 55, "wide": [38, 52], "wire": 15, "without": [2, 3, 6, 7, 68], "write": 35, "x": [38, 52], "xa2c128": 2, "xa2c256": 3, "xa2c32a": 5, "xa2c384": 6, "xa2c64a": 9, "xa95144xl": 20, "xa9536xl": 27, "xa9572xl": 30, "xc2c128": 2, "xc2c256": 3, "xc2c32": 4, "xc2c32a": 5, "xc2c384": 6, "xc2c512": 7, "xc2c64": 8, "xc2c64a": 9, "xc9500": [15, 33, 35, 36], "xc9500xl": [16, 33, 35, 36], "xc9500xv": 33, "xc95108": 18, "xc95144": 19, "xc95144xl": 20, "xc95144xv": 21, "xc95216": 22, "xc95288": 23, "xc95288xl": 24, "xc95288xv": 25, "xc9536": 26, "xc9536xl": 27, "xc9536xv": 28, "xc9572": 29, "xc9572xl": 30, "xc9572xv": 31, "xcr3032xl": 70, "xcr3064xl": 71, "xcr3128xl": 72, "xcr3256xl": 73, "xcr3384xl": 74, "xcr3512xl": 75, "xilinx": [11, 33, 37, 41, 46, 50, 54, 60, 64, 67, 77], "xor": [14, 36], "xpla3": 77, "xv": [16, 35, 36], "zia": 80}})
\ No newline at end of file
+Search.setIndex({"alltitles": {"AIM and FB inputs": [[14, "aim-and-fb-inputs"]], "BRAM (Virtex 2)": [[51, "bram-virtex-2"]], "BRAM.S3": [[51, "bram-s3"]], "BRAM.S3A": [[51, "bram-s3a"]], "BRAM.S3ADSP": [[51, "bram-s3adsp"]], "BRAM.S3E": [[51, "bram-s3e"]], "Backbone": [[42, "backbone"], [56, "backbone"]], "Bank configuration": [[14, "bank-configuration"]], "Bitsteam \u2014 interface tiles": [[47, "bitsteam-interface-tiles"]], "Bitstream": [[38, "bitstream"], [40, "bitstream"], [49, "bitstream"], [51, "bitstream"], [52, "bitstream"], [59, "bitstream"], [60, "bitstream"], [62, "bitstream"], [64, "bitstream"]], "Bitstream geometry": [[44, "bitstream-geometry"], [58, "bitstream-geometry"]], "Bitstream structure": [[1, "bitstream-structure"], [69, "bitstream-structure"]], "Bitstream structure \u2014 XC9500": [[15, "bitstream-structure-xc9500"]], "Bitstream structure \u2014 XC9500XL/XV": [[16, "bitstream-structure-xc9500xl-xv"]], "Bitstream \u2014 IOI tile": [[47, "bitstream-ioi-tile"]], "Bitstream \u2014 LLH tiles": [[42, "bitstream-llh-tiles"]], "Bitstream \u2014 LLV tiles": [[42, "bitstream-llv-tiles"]], "Bitstream \u2014 PowerPC hole tiles": [[56, "bitstream-powerpc-hole-tiles"]], "Bitstream \u2014 Series 7": [[63, "bitstream-series-7"], [66, "bitstream-series-7"], [67, "bitstream-series-7"]], "Bitstream \u2014 Spartan 6": [[63, "bitstream-spartan-6"]], "Bitstream \u2014 Virtex 5": [[63, "bitstream-virtex-5"], [66, "bitstream-virtex-5"]], "Bitstream \u2014 Virtex 6": [[63, "bitstream-virtex-6"], [66, "bitstream-virtex-6"], [67, "bitstream-virtex-6"]], "Bitstream \u2014 bottom tile": [[45, "bitstream-bottom-tile"]], "Bitstream \u2014 bottom tiles": [[39, "bitstream-bottom-tiles"], [53, "bitstream-bottom-tiles"]], "Bitstream \u2014 interconnect tiles": [[42, "bitstream-interconnect-tiles"], [56, "bitstream-interconnect-tiles"]], "Bitstream \u2014 interface tile": [[62, "bitstream-interface-tile"]], "Bitstream \u2014 interface tiles": [[42, "bitstream-interface-tiles"], [56, "bitstream-interface-tiles"]], "Bitstream \u2014 left side": [[48, "bitstream-left-side"]], "Bitstream \u2014 left tiles": [[39, "bitstream-left-tiles"]], "Bitstream \u2014 middle": [[48, "bitstream-middle"]], "Bitstream \u2014 normal tile": [[47, "bitstream-normal-tile"]], "Bitstream \u2014 right side": [[48, "bitstream-right-side"]], "Bitstream \u2014 right tiles": [[39, "bitstream-right-tiles"]], "Bitstream \u2014 terminator tiles": [[56, "bitstream-terminator-tiles"]], "Bitstream \u2014 top tile": [[45, "bitstream-top-tile"]], "Bitstream \u2014 top tiles": [[39, "bitstream-top-tiles"], [53, "bitstream-top-tiles"]], "Blank check \u2014 XC9500XL/XV": [[35, "blank-check-xc9500xl-xv"]], "Block RAM": [[59, "block-ram"]], "Block RAM \u2014 Virtex": [[48, "block-ram-virtex"]], "Block RAM \u2014 Virtex 2, Spartan 3": [[51, "block-ram-virtex-2-spartan-3"]], "Bond": [[17, "bond"], [70, "bond"]], "Boundary scan register": [[13, "boundary-scan-register"], [35, "boundary-scan-register"], [80, "boundary-scan-register"]], "CLBLL": [[63, "clbll"], [63, "id1"], [63, "id3"]], "CLBLM": [[63, "clblm"], [63, "id2"], [63, "id4"]], "CLEXL": [[63, "clexl"]], "CLEXM": [[63, "clexm"]], "CLKB.S3": [[39, "clkb-s3"]], "CLKB.S3A": [[39, "clkb-s3a"]], "CLKB.S3E": [[39, "clkb-s3e"]], "CLKB.V2": [[53, "clkb-v2"]], "CLKB.V2P": [[53, "clkb-v2p"]], "CLKB.V2PX": [[53, "clkb-v2px"]], "CLKL.S3A": [[39, "clkl-s3a"]], "CLKL.S3E": [[39, "clkl-s3e"]], "CLKR.S3A": [[39, "clkr-s3a"]], "CLKR.S3E": [[39, "clkr-s3e"]], "CLKT.S3": [[39, "clkt-s3"]], "CLKT.S3A": [[39, "clkt-s3a"]], "CLKT.S3E": [[39, "clkt-s3e"]], "CLKT.V2": [[53, "clkt-v2"]], "CLKT.V2P": [[53, "clkt-v2p"]], "CLKT.V2PX": [[53, "clkt-v2px"]], "Carry logic": [[38, "carry-logic"], [52, "carry-logic"]], "Clock divider": [[14, "clock-divider"]], "Clock interconnect": [[39, "clock-interconnect"], [45, "clock-interconnect"], [53, "clock-interconnect"]], "Clock rows": [[44, "clock-rows"], [58, "clock-rows"]], "Clock source \u2014 left and right": [[39, "clock-source-left-and-right"]], "Clock source \u2014 spine bottom and top": [[39, "clock-source-spine-bottom-and-top"], [53, "clock-source-spine-bottom-and-top"]], "Clock spine": [[58, "clock-spine"]], "Clock spine top and bottom": [[56, "clock-spine-top-and-bottom"]], "Configurable Logic Block": [[52, "configurable-logic-block"]], "Configurable Logic Block \u2014 Spartan 3, Virtex 4": [[38, "configurable-logic-block-spartan-3-virtex-4"]], "Configurable Logic Block \u2014 Virtex": [[49, "configurable-logic-block-virtex"]], "Configurable Logic Block \u2014 Virtex 5, Virtex 6, Series 7, Spartan 6": [[63, "configurable-logic-block-virtex-5-virtex-6-series-7-spartan-6"]], "Configuration pull-ups": [[36, "configuration-pull-ups"]], "Contents:": [[0, null], [10, null], [11, null], [32, null], [33, null], [37, null], [41, null], [46, null], [50, null], [55, null], [61, null], [65, null], [68, null], [77, null], [78, null]], "Corners \u2014 Virtex 2, Spartan 3": [[54, "corners-virtex-2-spartan-3"]], "DCM output bus": [[53, "dcm-output-bus"]], "DCMCONN.BOT": [[53, "dcmconn-bot"]], "DCMCONN.TOP": [[53, "dcmconn-top"]], "DSP": [[60, "dsp"], [64, "dsp"], [67, "dsp"]], "DSP \u2014 Spartan 3A DSP, Spartan 6": [[40, "dsp-spartan-3a-dsp-spartan-6"]], "Database schema": [[17, "database-schema"], [70, "database-schema"]], "Database \u2014 devices": [[10, "database-devices"], [32, "database-devices"], [77, "database-devices"]], "Default option attributes": [[39, "default-option-attributes"]], "Default option values": [[51, "default-option-values"]], "Device": [[17, "device"], [70, "device"]], "Device geometry": [[44, "device-geometry"], [58, "device-geometry"]], "Device pins": [[12, "device-pins"], [34, "device-pins"], [79, "device-pins"]], "Device structure": [[14, "device-structure"], [36, "device-structure"], [81, "device-structure"]], "Device table": [[43, "device-table"], [57, "device-table"]], "Devices": [[12, "devices"], [34, "devices"], [79, "devices"]], "Dual-port 16\u00d7X RAM": [[38, "dual-port-16x-ram"], [52, "dual-port-16x-ram"]], "Dual-port 32\u00d7X RAM": [[52, "dual-port-32x-ram"]], "Dual-port 64\u00d71 RAM": [[52, "dual-port-641-ram"]], "ECC mode": [[59, "ecc-mode"]], "Entering and exiting ISP mode \u2014 XC9500": [[35, "entering-and-exiting-isp-mode-xc9500"]], "Entering and exiting ISP mode \u2014 XC9500XL/XV": [[35, "entering-and-exiting-isp-mode-xc9500xl-xv"]], "Erasing fuses \u2014 XC9500": [[35, "erasing-fuses-xc9500"]], "Erasing fuses \u2014 XC9500XL/XV": [[35, "erasing-fuses-xc9500xl-xv"]], "FB columns and rows": [[81, "fb-columns-and-rows"]], "FB global fuses": [[36, "fb-global-fuses"]], "FCLK networks": [[81, "fclk-networks"]], "FIFO mode": [[59, "fifo-mode"]], "Flip-flop": [[36, "flip-flop"]], "Frequency": [[35, "frequency"]], "Fuses \u2014 FB inputs": [[15, "fuses-fb-inputs"], [16, "fuses-fb-inputs"]], "Fuses \u2014 FBs": [[69, "fuses-fbs"]], "Fuses \u2014 IMUX bits": [[69, "fuses-imux-bits"]], "Fuses \u2014 UIM wire-AND": [[15, "fuses-uim-wire-and"]], "Fuses \u2014 global bits": [[69, "fuses-global-bits"]], "Fuses \u2014 input buffer enable": [[15, "fuses-input-buffer-enable"]], "Fuses \u2014 macrocells": [[15, "fuses-macrocells"], [16, "fuses-macrocells"], [69, "fuses-macrocells"]], "Fuses \u2014 per-FB bits and globals": [[15, "fuses-per-fb-bits-and-globals"], [16, "fuses-per-fb-bits-and-globals"]], "Fuses \u2014 product and sum terms": [[69, "fuses-product-and-sum-terms"]], "Fuses \u2014 product terms": [[15, "fuses-product-terms"], [16, "fuses-product-terms"]], "GCLKC": [[53, "gclkc"]], "GCLKC.B": [[53, "gclkc-b"]], "GCLKC.T": [[53, "gclkc-t"]], "GCLKH": [[39, "gclkh"], [53, "gclkh"]], "GCLKH.N": [[39, "gclkh-n"]], "GCLKH.S": [[39, "gclkh-s"]], "GCLKH.UNI": [[39, "gclkh-uni"]], "GCLKH.UNI.N": [[39, "gclkh-uni-n"]], "GCLKH.UNI.S": [[39, "gclkh-uni-s"]], "GCLKVM.S3": [[39, "gclkvm-s3"]], "GCLKVM.S3E": [[39, "gclkvm-s3e"]], "General interconnect": [[42, "general-interconnect"], [47, "general-interconnect"], [56, "general-interconnect"]], "General structure": [[44, "general-structure"], [58, "general-structure"]], "Global bits": [[2, "global-bits"], [3, "global-bits"], [4, "global-bits"], [5, "global-bits"], [6, "global-bits"], [7, "global-bits"], [8, "global-bits"], [9, "global-bits"], [71, "global-bits"], [72, "global-bits"], [73, "global-bits"], [74, "global-bits"], [75, "global-bits"], [76, "global-bits"]], "Global networks": [[14, "global-networks"]], "Global networks \u2014 XC9500": [[36, "global-networks-xc9500"]], "Global networks \u2014 XC9500XL/XV": [[36, "global-networks-xc9500xl-xv"]], "Horizontal clock spine": [[44, "horizontal-clock-spine"]], "I/O pins": [[2, "i-o-pins"], [3, "i-o-pins"], [4, "i-o-pins"], [5, "i-o-pins"], [6, "i-o-pins"], [7, "i-o-pins"], [8, "i-o-pins"], [9, "i-o-pins"], [18, "i-o-pins"], [19, "i-o-pins"], [20, "i-o-pins"], [21, "i-o-pins"], [22, "i-o-pins"], [23, "i-o-pins"], [24, "i-o-pins"], [25, "i-o-pins"], [26, "i-o-pins"], [27, "i-o-pins"], [28, "i-o-pins"], [29, "i-o-pins"], [30, "i-o-pins"], [31, "i-o-pins"], [71, "i-o-pins"], [72, "i-o-pins"], [73, "i-o-pins"], [74, "i-o-pins"], [75, "i-o-pins"], [76, "i-o-pins"]], "IDCODE": [[35, "idcode"], [80, "idcode"]], "IMUX bits": [[2, "imux-bits"], [3, "imux-bits"], [4, "imux-bits"], [5, "imux-bits"], [6, "imux-bits"], [7, "imux-bits"], [8, "imux-bits"], [9, "imux-bits"], [18, "imux-bits"], [19, "imux-bits"], [20, "imux-bits"], [21, "imux-bits"], [22, "imux-bits"], [23, "imux-bits"], [24, "imux-bits"], [25, "imux-bits"], [26, "imux-bits"], [27, "imux-bits"], [28, "imux-bits"], [29, "imux-bits"], [30, "imux-bits"], [31, "imux-bits"], [71, "imux-bits"], [72, "imux-bits"], [73, "imux-bits"], [74, "imux-bits"], [75, "imux-bits"], [76, "imux-bits"]], "INT.BRAM": [[56, "int-bram"]], "INT.BRAM.S3": [[42, "int-bram-s3"]], "INT.BRAM.S3A.03": [[42, "int-bram-s3a-03"]], "INT.BRAM.S3A.12": [[42, "int-bram-s3a-12"]], "INT.BRAM.S3ADSP": [[42, "int-bram-s3adsp"]], "INT.BRAM.S3E": [[42, "int-bram-s3e"]], "INT.CLB": [[42, "int-clb"], [56, "int-clb"]], "INT.CNR": [[56, "int-cnr"]], "INT.DCM": [[42, "int-dcm"]], "INT.DCM.S3E.DUMMY": [[42, "int-dcm-s3e-dummy"]], "INT.DCM.V2": [[56, "int-dcm-v2"]], "INT.DCM.V2P": [[56, "int-dcm-v2p"]], "INT.GT.CLKPAD": [[56, "int-gt-clkpad"]], "INT.IOI": [[56, "int-ioi"]], "INT.IOI.CLK_B": [[56, "int-ioi-clk-b"]], "INT.IOI.CLK_T": [[56, "int-ioi-clk-t"]], "INT.IOI.S3": [[42, "int-ioi-s3"]], "INT.IOI.S3A.LR": [[42, "int-ioi-s3a-lr"]], "INT.IOI.S3A.TB": [[42, "int-ioi-s3a-tb"]], "INT.IOI.S3E": [[42, "int-ioi-s3e"]], "INT.PPC": [[56, "int-ppc"]], "INTF": [[47, "intf"], [66, "intf"], [66, "id1"], [66, "id3"]], "INTF.BRAM": [[66, "intf-bram"]], "INTF.CMT": [[47, "intf-cmt"]], "INTF.CMT.IOI": [[47, "intf-cmt-ioi"]], "INTF.DELAY": [[66, "intf-delay"], [66, "id2"], [66, "id4"]], "INTF.DSP": [[42, "intf-dsp"]], "INTF.GT.B0": [[56, "intf-gt-b0"]], "INTF.GT.B123": [[56, "intf-gt-b123"]], "INTF.GT.BCLKPAD": [[56, "intf-gt-bclkpad"]], "INTF.GT.T0": [[56, "intf-gt-t0"]], "INTF.GT.T123": [[56, "intf-gt-t123"]], "INTF.GT.TCLKPAD": [[56, "intf-gt-tclkpad"]], "INTF.IOI": [[47, "intf-ioi"]], "INTF.PPC": [[56, "intf-ppc"]], "IO banks and IO buffers": [[44, "io-banks-and-io-buffers"], [58, "io-banks-and-io-buffers"]], "IR": [[13, "ir"], [35, "ir"], [80, "ir"]], "ISP DR registers \u2014 XC9500": [[35, "isp-dr-registers-xc9500"]], "ISP DR registers \u2014 XC9500XL/XV": [[35, "isp-dr-registers-xc9500xl-xv"]], "ISP instructions": [[13, "isp-instructions"], [80, "isp-instructions"]], "ISP instructions \u2014 XC9500": [[35, "isp-instructions-xc9500"]], "ISP instructions \u2014 XC9500XL/XV": [[35, "isp-instructions-xc9500xl-xv"]], "Input multiplexers": [[42, "input-multiplexers"], [56, "input-multiplexers"]], "Input/output buffer": [[14, "input-output-buffer"], [36, "input-output-buffer"], [81, "input-output-buffer"]], "Interconnect": [[62, "interconnect"]], "Interconnect \u2014 Virtex 5, Virtex 6, Series 7": [[66, "interconnect-virtex-5-virtex-6-series-7"]], "Introduction": [[12, "introduction"], [34, "introduction"], [43, "introduction"], [57, "introduction"], [79, "introduction"]], "JED bits": [[70, "jed-bits"]], "JED format mapping": [[15, "jed-format-mapping"], [16, "jed-format-mapping"]], "JED mapping": [[2, "jed-mapping"], [3, "jed-mapping"], [4, "jed-mapping"], [4, "id1"], [5, "jed-mapping"], [5, "id1"], [6, "jed-mapping"], [7, "jed-mapping"], [8, "jed-mapping"], [8, "id1"], [9, "jed-mapping"], [9, "id1"], [69, "jed-mapping"], [71, "jed-mapping"], [72, "jed-mapping"], [73, "jed-mapping"], [74, "jed-mapping"], [75, "jed-mapping"], [76, "jed-mapping"]], "JED mapping \u2014 MCs with IOBs": [[2, "jed-mapping-mcs-with-iobs"], [3, "jed-mapping-mcs-with-iobs"], [6, "jed-mapping-mcs-with-iobs"], [7, "jed-mapping-mcs-with-iobs"]], "JED mapping \u2014 MCs without IOBs": [[2, "jed-mapping-mcs-without-iobs"], [3, "jed-mapping-mcs-without-iobs"], [6, "jed-mapping-mcs-without-iobs"], [7, "jed-mapping-mcs-without-iobs"]], "JED mapping \u2014 macrocells with IOB": [[69, "jed-mapping-macrocells-with-iob"]], "JED mapping \u2014 macrocells without IOB": [[69, "jed-mapping-macrocells-without-iob"]], "JED structure": [[69, "jed-structure"]], "JTAG interface": [[13, "jtag-interface"], [35, "jtag-interface"], [80, "jtag-interface"]], "LL \u2014 Virtex 2": [[54, "ll-virtex-2"]], "LL.S3": [[54, "ll-s3"]], "LL.S3A": [[54, "ll-s3a"]], "LL.S3E": [[54, "ll-s3e"]], "LLH": [[42, "llh"]], "LLH.CLKB.S3A": [[42, "llh-clkb-s3a"]], "LLH.CLKT.S3A": [[42, "llh-clkt-s3a"]], "LLV.S3A": [[42, "llv-s3a"]], "LLV.S3E": [[42, "llv-s3e"]], "LR \u2014 Virtex 2": [[54, "lr-virtex-2"]], "LR.S3": [[54, "lr-s3"]], "LR.S3A": [[54, "lr-s3a"]], "LR.S3E": [[54, "lr-s3e"]], "LUT RAM": [[38, "lut-ram"], [52, "lut-ram"]], "LUTs": [[38, "luts"], [52, "luts"]], "Local control terms": [[81, "local-control-terms"]], "Long line splitters": [[42, "long-line-splitters"]], "Lower left": [[54, "lower-left"]], "Lower right": [[54, "lower-right"]], "MC bits": [[2, "mc-bits"], [3, "mc-bits"], [4, "mc-bits"], [5, "mc-bits"], [6, "mc-bits"], [7, "mc-bits"], [8, "mc-bits"], [9, "mc-bits"]], "Macrocell and IOB outputs": [[14, "macrocell-and-iob-outputs"], [81, "macrocell-and-iob-outputs"]], "Macrocell output \u2014 XC9500": [[36, "macrocell-output-xc9500"]], "Macrocell output \u2014 XC9500XL/XV": [[36, "macrocell-output-xc9500xl-xv"]], "Misc configuration": [[14, "misc-configuration"], [36, "misc-configuration"], [81, "misc-configuration"]], "Output multiplexers": [[52, "output-multiplexers"]], "Output multiplexers \u2014 Spartan 3": [[38, "output-multiplexers-spartan-3"]], "Output multiplexers \u2014 Virtex 4": [[38, "output-multiplexers-virtex-4"]], "Overview": [[14, "overview"], [36, "overview"], [81, "overview"]], "PCI logic": [[58, "pci-logic"]], "PPC.E": [[56, "ppc-e"]], "PPC.N": [[56, "ppc-n"]], "PPC.S": [[56, "ppc-s"]], "PPC.W": [[56, "ppc-w"]], "PT import/export": [[36, "pt-import-export"]], "Packages": [[12, "packages"], [34, "packages"], [79, "packages"]], "Part": [[17, "part"], [70, "part"]], "PowerPC holes": [[56, "powerpc-holes"], [58, "powerpc-holes"]], "Primary vertical clock spine": [[44, "primary-vertical-clock-spine"]], "Primitive outputs": [[42, "primitive-outputs"], [56, "primitive-outputs"]], "Product terms": [[14, "product-terms"], [36, "product-terms"], [81, "product-terms"]], "Programming fuses \u2014 XC9500": [[35, "programming-fuses-xc9500"]], "Programming fuses \u2014 XC9500XL/XV": [[35, "programming-fuses-xc9500xl-xv"]], "Programming sequence": [[13, "programming-sequence"], [35, "programming-sequence"], [80, "programming-sequence"]], "Project Combine": [[0, "project-combine"]], "Reading fuses \u2014 XC9500": [[35, "reading-fuses-xc9500"]], "Reading fuses \u2014 XC9500XL/XV": [[35, "reading-fuses-xc9500xl-xv"]], "Register": [[14, "register"], [81, "register"]], "Registers": [[38, "registers"], [52, "registers"]], "Secondary vertical clock spines": [[44, "secondary-vertical-clock-spines"]], "Shift registers": [[38, "shift-registers"], [52, "shift-registers"]], "Single-port 128\u00d71 RAM": [[52, "single-port-1281-ram"]], "Single-port 16\u00d7X RAM": [[38, "single-port-16x-ram"], [52, "single-port-16x-ram"]], "Single-port 32\u00d7X RAM": [[38, "single-port-32x-ram"], [52, "single-port-32x-ram"]], "Single-port 64\u00d71 RAM": [[38, "single-port-641-ram"]], "Single-port 64\u00d7X RAM": [[52, "single-port-64x-ram"]], "Spartan 3": [[38, "spartan-3"]], "Spartan 3A DCMs": [[44, "spartan-3a-dcms"]], "Spartan 3A DSP": [[40, "spartan-3a-dsp"]], "Spartan 3A and 3A DSP BRAM columns": [[44, "spartan-3a-and-3a-dsp-bram-columns"]], "Spartan 3E BRAM columns": [[44, "spartan-3e-bram-columns"]], "Spartan 3E DCMs": [[44, "spartan-3e-dcms"]], "Spartan 6": [[40, "spartan-6"]], "Speed": [[17, "speed"], [70, "speed"]], "Speed data": [[2, "speed-data"], [3, "speed-data"], [4, "speed-data"], [5, "speed-data"], [6, "speed-data"], [7, "speed-data"], [8, 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"byp5": [62, 66], "byp6": [62, 66], "byp7": [62, 66], "bypass": [13, 35, 38, 51, 52, 56, 80], "byte": [15, 16, 35, 43, 51, 59], "c001": 67, "c1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 64, 67, 71, 72, 73, 74, 75, 76], "c10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 72, 73, 74, 75, 76], "c11": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "c12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "c13": [3, 6, 7, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "c14": [2, 3, 6, 7, 22, 23, 24, 25, 74, 75, 76], "c15": [3, 6, 7, 22, 23, 24, 25, 74, 75, 76], "c16": [3, 6, 7, 22, 23, 24, 25, 74, 75, 76], "c17": [6, 7, 22, 23, 24, 25, 74, 75, 76], "c18": [6, 7, 22, 23, 24, 25, 74, 75, 76], "c19": [6, 7, 22, 23, 24, 25, 74, 75, 76], "c2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "c20": [6, 7, 22, 23, 24, 75, 76], "c21": [6, 7, 22, 23, 75, 76], "c22": [6, 7, 22, 23, 75, 76], "c23": [22, 23], "c24": [22, 23], "c25": [22, 23], "c26": [22, 23], "c3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "c4": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "c5": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "c5ffinit": 63, "c5ffinitslice0": 63, "c5ffmux": 63, "c5ffsr": 63, "c5ffsrinit": 63, "c5ffsrinitslice0": 63, "c5ffsrslice0": 63, "c5ffsrslice1": 63, "c5q0": 63, "c5q0100": 63, "c6": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "c6lut": 63, "c7": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "c8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 72, 73, 74, 75, 76], "c9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "calcul": [15, 16], "call": [36, 42, 44, 56, 58, 81], "came": [35, 56], "can": [12, 14, 17, 34, 35, 36, 38, 42, 43, 44, 51, 52, 56, 58, 59, 69, 70, 79, 80, 81], "cannot": [35, 38, 52, 59, 81], "capabl": [12, 34, 38, 57, 59], "captur": [38, 43, 52, 57, 80], "cardin": [42, 56], "care": 35, "carri": [41, 55], "carryin0": 40, "carryininv": [60, 64, 67], "carryininvdsp0": [64, 67], "carryininvdsp1": [64, 67], "carryinreg": [40, 60, 64, 67], "carryinregdsp": 40, "carryinregdsp0": 67, "carryinregdsp1": 67, "carryinsel": 40, "carryinsel0inv": 60, "carryinsel1inv": 60, "carryinsel2_mux": 67, "carryinseldsp": 40, "carryinselreg": [60, 64, 67], "carryinselregdsp0": 67, "carryinselregdsp1": 67, "carryoutreg": 40, "carryoutregdsp": 40, "cascad": [51, 56, 59], "cascade1": [40, 51, 60, 64, 67], "cascadein": 59, "cascadeout": 59, "case": [36, 56, 81], "cclk2pin": 54, "cclkpin": 54, "ccy0": 63, "ccy0slice0": 63, "ccy0slice1": 63, "cdi1mux": 63, "cdi1muxslice0": 63, "cdr": [2, 3, 6, 7], "cdrst": [12, 14], "ce": [14, 36, 38, 42, 51, 52, 56, 81], "ce0": [42, 56, 62], "ce00001000001": 56, "ce00mux": 42, "ce01": 62, "ce0int": [42, 56], "ce1": [42, 56, 62, 63], "ce10001000010": 56, "ce10mux": 42, "ce11": 62, "ce1int": [42, 56], "ce2": [42, 56, 62], "ce20": 42, "ce20001000001": 56, "ce20mux": 42, "ce21": 62, "ce2int": [42, 56], "ce3": [42, 56, 62], "ce30001000010": 56, "ce30mux": 42, "ce31": 62, "ce3int": [42, 56], "ce_mux": [36, 69, 81], "ce_mux3736": 16, "cea": 51, "cead_mux": 67, "ceainv": 40, "cealumode_mux": 67, "ceb": 51, "cebinv": 40, "cecarryininv": 40, "cecarryininvdsp": 40, "cecinv": 40, "ced_mux": 67, "cedinv": 40, "cedinvdsp": 40, "ceinmode_mux": 67, "ceinv": 49, "ceinvslice0": 49, "cell": [35, 80], "ceminv": 40, "center": 41, "ceopmodeinv": 40, "cep": 51, "cepinv": 40, "cepinvdsp": 40, "cff_latch": 63, "cff_latchslice0": 63, "cffinit": 63, "cffinitslice0": 63, "cffinitslice1": 63, "cffmux": 63, "cffmuxslice1": 63, "cffsr": 63, "cffsrinit": 63, "cffsrinitslice0": 63, "cffsrinitslice1": 63, "cffsrslice1": 63, "cfuse": [15, 16], "cgate111": 54, "cgate1111": 54, "chain": [36, 38, 51, 52, 59], "chanc": 51, "chang": [34, 35, 38, 43, 44], "charact": 81, "check": 69, "chip": [12, 34, 36, 79], "choic": [56, 81], "ci1": 63, "cin": [38, 52], "cin0": 49, "cin1": [38, 52, 63], "circuit": 35, "circuitri": [35, 36, 38, 44, 52], "cki0010": [39, 53], "cki010": 39, "ckil00010": 39, "ckir00100": 39, "clamp": [13, 35, 80], "classic": [36, 81], "clb": [38, 44, 52, 58], "clear": 35, "clk": [14, 36, 38, 39, 42, 44, 51, 52, 53, 56, 59, 81], "clk0": [39, 42, 47, 53, 56, 62, 66], "clk00": 47, "clk000": 66, "clk00001": 66, "clk00001000001": 56, "clk01": 62, "clk0int": [42, 56], "clk1": [39, 42, 47, 53, 56, 62, 66], "clk100": 66, "clk10001000010": 56, "clk10010": 66, "clk11": [47, 62], "clk1int": [42, 56], "clk2": [39, 42, 53, 56, 62], "clk20001000001": 56, "clk21": 62, "clk2int": [42, 56], "clk3": [39, 42, 53, 56, 62], "clk30001000010": 56, "clk30mux": 42, "clk31": 62, "clk3int": [42, 56], "clk4": 53, "clk5": 53, "clk6": 53, "clk7": 53, "clk_ddr": [2, 3, 4, 5, 6, 7, 8, 9], "clk_inv": [2, 3, 4, 5, 6, 7, 8, 9, 36, 69, 81], "clk_inv35": 16, "clk_mux": [2, 3, 4, 5, 6, 7, 8, 9, 36, 69, 81], "clk_mux3433": 16, "clk_mux3736": 15, "clka": 59, "clkainv": 48, "clkb": [44, 58, 59], "clkbinv": 48, "clkc": [41, 44, 58], "clkc_50a": [41, 44], "clkc_mux": 60, "clkdiv_delay_en": [2, 3, 6, 7], "clkdiv_div": [2, 3, 6, 7], "clkdiv_en": [2, 3, 6, 7], "clkfb011": 42, "clkin011": 42, "clkinv": [40, 49, 63, 64, 67], "clkinvdsp0": 67, "clkinvdsp1": 67, "clkinvslice0": [49, 63], "clkinvslice1": 63, "clkl": 44, "clkmux": [39, 53], "clkpad": [42, 58], "clkpad0000100000100": 56, "clkpad0001000000010000": 42, "clkpad1000100001000": 56, "clkpad1001000000100000": 42, "clkpad2001000000100": 56, "clkpad2001000001000000": 42, "clkpad3001000001000": 56, "clkpad3001000010000000": 42, "clkpad4010000000100": 56, "clkpad5010000001000": 56, "clkpad6100000000100": 56, "clkpad7100000001000": 56, "clkr": 44, "clkt": [44, 58], "clock": [11, 12, 34, 35, 36, 37, 38, 41, 42, 43, 46, 51, 52, 55, 57, 59, 70, 79, 81], "clock_invert_m": 64, "clock_invert_p": 64, "clock_invert_pdsp1": 64, "clockwis": [44, 58], "close": [44, 51], "closest": 44, "cmo": 14, "cnr": [44, 58], "code": 35, "col": [2, 3, 4, 5, 6, 7, 8, 9, 71, 72, 73, 74, 75, 76], "col_hi": [15, 16], "col_lo": [15, 16], "coloc": [44, 51], "column": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 35, 38, 39, 42, 51, 52, 53, 56, 58, 69, 70, 71, 72, 73, 74, 75, 76, 78, 80], "comb": 36, "comb0": 15, "comb1": 16, "combin": [36, 38, 42, 51, 52, 56, 81], "combination": 51, "combinatori": [14, 36, 81], "come": [12, 34, 36, 38, 44, 51, 58, 79, 81], "commerci": [17, 70], "commonli": 69, "compat": [12, 34, 79], "compens": 52, "complet": [12, 13, 16, 34, 35, 36, 69, 79], "complex": [15, 16], "comput": [51, 69], "concaten": [15, 16, 51, 59], "conceptu": 44, "config": [15, 16, 69], "configur": [11, 12, 15, 33, 34, 35, 37, 39, 41, 42, 43, 50, 55, 56, 57, 58, 65, 69, 78], "configuraton": [15, 16], "conjunct": 36, "connect": [35, 36, 38, 44, 51, 52, 56, 57, 59, 80, 81], "consid": 35, "consist": [35, 36, 51], "const": [13, 14, 35, 36, 38, 52, 80, 81], "constant": [36, 38, 52], "constraint": 12, "construct": 81, "consult": 15, "contain": [15, 17, 34, 38, 42, 43, 44, 51, 52, 56, 57, 58, 59, 80, 81], "content": [35, 38, 52], "contigu": [15, 16], "continu": 35, "control": [12, 14, 35, 36, 38, 43, 52, 57, 59], "convert": [15, 16], "coolrunn": [0, 12, 14], "coordin": [16, 17, 36, 44, 58, 69, 70, 81], "core": [12, 34, 36, 42, 56, 57, 58, 79, 81], "corner": [37, 42, 43, 44, 55, 56, 57, 58], "correct": 59, "correspond": [12, 14, 15, 16, 17, 34, 35, 36, 38, 39, 40, 42, 44, 51, 52, 53, 56, 58, 59, 70, 81], "could": 35, "count": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 38, 44, 51, 58, 71, 72, 73, 74, 75, 76], "cout": [38, 52], "coutmux": 63, "coutmuxslice1": 63, "cover": 81, "cp132": [2, 3, 12], "cp56": [4, 5, 8, 9, 12, 72, 79], "cpld": [0, 12, 34, 36, 79, 81], "crammod": 63, "creat": [42, 56, 58], "creg": [40, 60, 64, 67], "cregdsp": 40, "cregdsp0": [64, 67], "cregdsp1": 67, "cross": [44, 56], "cs144": [20, 21, 34, 73, 79], "cs280": [24, 25, 34, 74, 79], "cs48": [26, 27, 28, 30, 31, 34, 71, 72, 79], "cso2pin": 54, "ct": 14, "ct4111": [2, 3, 4, 5, 6, 7, 8, 9], "ct501": [2, 3, 4, 5, 6, 7, 8, 9], "ct601": [2, 3, 4, 5, 6, 7, 8, 9], "ct70001": [2, 3, 4, 5, 6, 7, 8, 9], "ctc": 14, "cte": 14, "ctlgo001": 42, "ctlmode011": 42, "ctlosc1001": 42, "ctlosc2001": 42, "ctlsel0011": 42, "ctlsel1101": 42, "ctlsel2100": 42, "ctr": 14, "ctrl0": 66, "ctrl00001": 66, "ctrl1": 66, "ctrl10010": 66, "ctrl2": 66, "ctrl3": 66, "curious": [12, 34], "current": [35, 38, 52], "cut": [43, 44], "cv100": [2, 12], "cv64": [5, 9, 12], "cx0": 63, "cx0100": 63, "cx1": 63, "cx10": 63, "cx1010": 63, "cy0": 49, "cy0111": 63, "cy0f": [38, 52], "cy0g": [38, 52], "cy1010": 63, "cy110": 63, "cycl": [35, 51, 59], "cyinit": [38, 49, 52, 63], "cyinitslice0": [38, 49, 63], "cyinitslice1": [38, 49, 63], "cyinitslice2": 38, "cyinitslice3": 38, "cyself": [38, 49, 52], "cyselfslice0": 49, "cyselfslice1": [38, 49], "cyselfslice3": 38, "cyselg": [38, 49, 52], "cyselgslice0": [49, 52], "cyselgslice1": [38, 49, 52], "cyselgslice3": 38, "d": [14, 36, 51, 59, 81], "d0_mux": 67, "d1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76, 81], "d10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 72, 73, 74, 75, 76], "d10_mux": 67, "d11": [3, 6, 7, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "d11_mux": 67, "d12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "d12_mux": 67, "d13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "d13_mux": 67, "d14": [2, 3, 6, 7, 22, 23, 24, 25, 74, 75, 76], "d14_mux": 67, "d15": [3, 6, 7, 22, 23, 24, 25, 74, 75, 76], "d15_mux": 67, "d16": [3, 6, 7, 22, 23, 24, 25, 74, 75, 76], "d16_mux": 67, "d17": [6, 7, 22, 23, 24, 25, 74, 75, 76], "d17_mux": 67, "d18": [6, 7, 22, 23, 24, 25, 74, 75, 76], "d18_mux": 67, "d19": [6, 7, 22, 23, 24, 25, 74, 75, 76], "d19_mux": 67, "d1_mux": 67, "d2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "d20": [6, 7, 22, 23, 24, 75, 76], "d20_mux": 67, "d21": [6, 7, 22, 23, 75, 76], "d21_mux": 67, "d22": [6, 7, 22, 23, 75, 76], "d22_mux": 67, "d23": [22, 23], "d23_mux": 67, "d24": [22, 23], "d24_mux": 67, "d25": [22, 23], "d26": [22, 23], "d2_mux": 67, "d3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "d3_mux": 67, "d4": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "d4_mux": 67, "d5": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "d5_mux": 67, "d5ffinit": 63, "d5ffinitslice0": 63, "d5ffmux": 63, "d5ffsr": 63, "d5ffsrinit": 63, "d5ffsrinitslice0": 63, "d5ffsrslice1": 63, "d5q0": 63, "d5q0100": 63, "d6": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "d6_mux": 67, "d6lut": 63, "d7": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "d7_mux": 67, "d8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 72, 73, 74, 75, 76], "d8_mux": 67, "d9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "d9_mux": 67, "data": [10, 12, 14, 17, 32, 35, 38, 40, 42, 44, 48, 51, 52, 56, 58, 59, 69, 70, 77, 81], "data0": [42, 56], "data00001000001": 56, "data00001000100": 56, "data00mux": 42, "data1": [42, 56], "data10": 42, "data10001000010": 56, "data10001001000": 56, "data101mux": 42, "data10mux": 42, "data11": 42, "data110mux": 42, "data11mux": 42, "data12": 42, "data13": 42, "data130mux": 42, "data131mux": 42, "data14": 42, "data140mux": 42, "data15": 42, "data16": 42, "data160mux": 42, "data17": 42, "data170mux": 42, "data171mux": 42, "data18": 42, "data180mux": 42, "data181mux": 42, "data19": 42, "data190mux": 42, "data2": [42, 56], "data20": 42, "data20001000100": 56, "data20001010000": 56, "data20mux": 42, "data21": 42, "data210mux": 42, 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72, 73, 74, 75, 76], "p56": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 72, 73, 74, 75, 76], "p57": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 72, 73, 74, 75, 76], "p58": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 72, 73, 74, 75, 76], "p59": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 72, 73, 74, 75, 76], "p6": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "p60": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 72, 73, 74, 75, 76], "p61": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 72, 73, 74, 75, 76], "p62": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 72, 73, 74, 75, 76], "p63": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 72, 73, 74, 75, 76], "p64": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 27, 29, 30, 31, 72, 73, 74, 75, 76], "p65": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p66": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p67": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p68": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p69": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p7": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "p70": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p71": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p72": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p73": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p74": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p75": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p76": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p77": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p78": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p79": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p8": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "p80": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p81": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p82": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p83": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p84": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p85": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p86": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p87": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p88": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p89": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p9": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "p90": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p91": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p92": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p93": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p94": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p95": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p96": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p97": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p98": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p99": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 72, 73, 74, 75, 76], "p_d": 51, "packag": [11, 17, 33, 36, 43, 70, 78, 80], "pad": [2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 16, 17, 34, 36, 42, 56, 70, 79, 81], "pair": [17, 44, 52, 59, 70], "parallel": 16, "paramet": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75, 76], "pariti": [51, 59], "part": [2, 3, 4, 5, 6, 7, 8, 9, 12, 33, 34, 38, 44, 52, 59, 71, 72, 73, 74, 75, 76, 78, 80], "partial": [34, 51, 59, 80], "particip": 36, "particular": [17, 70], "particularli": 38, "pass": [35, 42, 44, 56], "passthrough": 56, "patdet1": 64, "path": [36, 51], "pattern": [58, 64, 67], "pattern0": [64, 67], "pc44": [4, 5, 8, 9, 12, 26, 27, 28, 29, 30, 31, 34, 71, 72, 79], "pc84": [18, 29, 34], "pci": [43, 44, 55, 56, 57], "pci000": 56, "pci100": 56, "pcilog": [44, 55, 56, 58], "pcilogics": [39, 44], "pent": 66, "pent00010100": 66, "pent00011000": 66, "pent00100100": 66, "pent00101000": 66, "pent01000100": 66, "pent01001000": 66, "pent10000100": 66, "pent10001000": 66, "per": [12, 14, 17, 33, 34, 35, 36, 38, 42, 43, 44, 51, 56, 57, 59, 69, 70, 80, 81], "perform": [35, 36, 81], "perman": 39, "person": 35, "pgate011": 54, "pgate0111": 54, "phi": 35, "philip": [79, 80], "physic": [42, 69], "pick": [38, 52, 59], "picosecond": [17, 70], "pin": [10, 11, 14, 17, 32, 33, 36, 38, 51, 52, 56, 59, 70, 77, 78, 80, 81], "pipelin": [43, 51, 59], "pitch": [12, 34, 79], "pla": [69, 81], "place": [12, 35, 36, 42, 44, 56], "placement": 44, "plain": [12, 17, 34, 44, 57, 58, 59, 70, 79], "plain0": [4, 5, 8, 9], "plain00": [2, 3, 6, 7], "plane": [51, 59, 69, 70], "plastic": [12, 34, 79], "platic": 34, "plcc": [12, 34, 79], "pmv": [43, 57], "point": 52, "polar": [34, 36, 81], "por": 81, "port": [43, 51, 56, 57, 59], "port_en": [70, 71, 72, 73, 74, 75, 76, 79, 81], "porta_attr": 48, "portb_attr": 48, "posedg": [36, 38, 52, 81], "posit": [35, 69], "possess": 35, "possibl": [17, 42, 51, 56, 70, 81], "potenti": 36, "power": [12, 17, 34, 35, 36, 70, 79, 81], "powerdownpin": 54, "powerdownpinmisc": 54, "powerpc": [52, 55, 57, 59], "ppc": [55, 58], "pq100": [18, 19, 29, 34], "pq160": [18, 19, 22, 34], "pq208": [3, 6, 7, 12, 24, 25, 34, 74, 75, 76, 79], "practic": 56, "pre": 36, "preassign": 12, "precyinit": 63, "precyinit0": 63, "prefix": 56, "preg": [40, 51, 60, 64, 67], "preg_clkinvers": 51, "pregdsp": 40, "prepar": 35, "present": [12, 35, 42, 44, 56], "pretend": [36, 81], "pretti": 51, "prevent": [34, 56], "previou": [35, 38, 51, 52, 59, 81], "previous": [51, 59], "primari": [39, 41, 42], "primit": [38, 41, 43, 44, 51, 52, 55, 57, 58, 59], "prioriti": [38, 51, 52], "pro": [53, 54, 56, 57, 58], "problem": 34, "process": [38, 43, 52, 57], "prod": [38, 52], "prod010": 38, "prod100": [38, 52], "prod11": 49, "product": [11, 33, 38, 55, 78, 80], "progpin": 54, "program": [11, 14, 15, 16, 17, 33, 36, 69, 78, 79, 81], "program_tim": 17, "programm": [35, 36, 42, 56, 81], "progress": 35, "propag": [36, 38, 52], "protect": [14, 36, 69, 81], "provid": [17, 44, 58, 69, 70], "psclk101": 42, "psen010": 42, "psincdec100": 42, "pt": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 69, 70, 71, 72, 73, 74, 75, 76, 81], "pt0": [16, 81], "pt00": [2, 3, 4, 5, 6, 7, 8, 9, 15], "pt000": 16, "pt0010": [2, 3, 4, 5, 6, 7, 8, 9], "pt01": [2, 3, 4, 5, 6, 7, 8, 9], "pt010": 69, "pt1": [15, 69], "pt11": 16, "pt110": [2, 3, 4, 5, 6, 7, 8, 9], "pt111": 15, "pt2": 36, "pt201": 16, "pt3": 36, "pt310": 16, "pt4": 14, "pt40": 81, "pt5": 14, "pt6": 14, "pt7": 14, "pt8": 81, "pt9": 81, "pt_col": [69, 70], "pt_inv10": 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51], "output": [14, 36, 38, 42, 52, 53, 56, 81], "overview": [14, 36, 81], "packag": [12, 34, 79], "part": [17, 70], "pci": 58, "per": [15, 16], "pin": [2, 3, 4, 5, 6, 7, 8, 9, 12, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34, 71, 72, 73, 74, 75, 76, 79], "port": [38, 52], "powerpc": [56, 58], "ppc": 56, "primari": 44, "primit": [42, 56], "product": [14, 15, 16, 36, 52, 69, 81], "program": [13, 35, 80], "project": 0, "protect": 35, "pt": 36, "pull": 36, "ram": [38, 48, 51, 52, 59], "read": 35, "regist": [13, 14, 35, 38, 52, 80, 81], "right": [39, 48, 54], "row": [39, 44, 53, 58, 81], "s3": [39, 42, 51, 54], "s3a": [39, 42, 51, 54], "s3adsp": [42, 51], "s3e": [39, 42, 51, 54], "scan": [13, 35, 80], "schema": [17, 70], "secondari": [39, 44], "sequenc": [13, 35, 80], "seri": [63, 66, 67], "shift": [38, 52], "side": 48, "singl": [38, 52], "sourc": [39, 53], "spartan": [38, 40, 41, 44, 46, 50, 51, 54, 63], "speed": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75, 76], "spine": [39, 44, 53, 56, 58], "splitter": 42, "structur": [1, 14, 15, 16, 36, 44, 58, 69, 81], "sum": [14, 36, 52, 69, 81], "t": 53, "t0": 56, "t123": 56, "tabl": [43, 57], "tb": 42, "tbuf": 52, "tclkpad": 56, "term": [14, 15, 16, 36, 56, 69, 81], "termin": [42, 56], "tile": [17, 39, 42, 45, 47, 53, 56, 62, 70], "todo": [1, 12, 13, 14, 35, 36, 38, 39, 40, 41, 43, 44, 46, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 61, 65, 68, 80, 81], "top": [17, 39, 45, 53, 56, 70], "tristat": 52, "uim": [15, 23, 36], "ul": 54, "uni": 39, "univers": 81, "up": 36, "upper": 54, "ur": 54, "v2": [53, 54, 56], "v2p": [53, 54, 56], "v2px": 53, "valu": 51, "vertic": 44, "virtex": [38, 48, 49, 50, 51, 54, 55, 61, 63, 65, 66, 67, 68], "w": 56, "wide": [38, 52], "wire": 15, "without": [2, 3, 6, 7, 69], "write": 35, "x": [38, 52], "xa2c128": 2, "xa2c256": 3, "xa2c32a": 5, "xa2c384": 6, "xa2c64a": 9, "xa95144xl": 20, "xa9536xl": 27, "xa9572xl": 30, "xc2c128": 2, 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\ No newline at end of file
diff --git a/xilinx/index.html b/xilinx/index.html
index 6cec5f66..97c72abe 100644
--- a/xilinx/index.html
+++ b/xilinx/index.html
@@ -100,6 +100,7 @@ <h1>Xilinx FPGAs<a class="headerlink" href="#xilinx-fpgas" title="Link to this h
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index 6a9ca7d8..40f1faa5 100644
--- a/xilinx/spartan3/index.html
+++ b/xilinx/spartan3/index.html
@@ -20,7 +20,7 @@
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+        <a href="../virtex2/corner.html" class="btn btn-neutral float-left" title="Corners — Virtex 2, Spartan 3" accesskey="p" rel="prev"><span class="fa fa-arrow-circle-left" aria-hidden="true"></span> Previous</a>
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index 8b3073e5..bb7011cd 100644
--- a/xilinx/virtex2/bram.html
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@@ -63,6 +63,7 @@
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+<li class="toctree-l3"><a class="reference internal" href="corner.html">Corners — Virtex 2, Spartan 3</a></li>
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index 0c7ba391..62618285 100644
--- a/xilinx/virtex2/clb.html
+++ b/xilinx/virtex2/clb.html
@@ -66,6 +66,7 @@
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index 0b6fb673..9cc08a8b 100644
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@@ -62,6 +62,7 @@
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 </ul>
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+<li class="toctree-l3"><a class="reference internal" href="corner.html">Corners — Virtex 2, Spartan 3</a></li>
 </ul>
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 <li class="toctree-l2"><a class="reference internal" href="../spartan3/index.html">Xilinx Spartan 3 FPGAs</a></li>
@@ -3933,7 +3934,7 @@ <h3><code class="docutils literal notranslate"><span class="pre">DCMCONN.TOP</sp
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new file mode 100644
index 00000000..899acb2e
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+++ b/xilinx/virtex2/corner.html
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+<!DOCTYPE html>
+<html class="writer-html5" lang="en" >
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+<ul class="current">
+<li class="toctree-l1"><a class="reference internal" href="../../xc9500/index.html">Xilinx XC9500, XC9500XL, XC9500XV CPLDs</a></li>
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+<li class="toctree-l1"><a class="reference internal" href="../../xc2c/index.html">Xilinx Coolrunner II CPLDs</a></li>
+<li class="toctree-l1 current"><a class="reference internal" href="../index.html">Xilinx FPGAs</a><ul class="current">
+<li class="toctree-l2"><a class="reference internal" href="../virtex/index.html">Xilinx Virtex, Virtex E, Spartan 2, Spartan 2E FPGAs</a></li>
+<li class="toctree-l2 current"><a class="reference internal" href="index.html">Xilinx Virtex 2 FPGAs</a><ul class="current">
+<li class="toctree-l3"><a class="reference internal" href="intro.html">Introduction</a></li>
+<li class="toctree-l3"><a class="reference internal" href="structure.html">Device geometry</a></li>
+<li class="toctree-l3"><a class="reference internal" href="interconnect.html">General interconnect</a></li>
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+<li class="toctree-l3"><a class="reference internal" href="bram.html">Block RAM — Virtex 2, Spartan 3</a></li>
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+<li class="toctree-l3 current"><a class="current reference internal" href="#">Corners — Virtex 2, Spartan 3</a><ul>
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+<li class="toctree-l4"><a class="reference internal" href="#upper-left">Upper left</a></li>
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+<li class="toctree-l4"><a class="reference internal" href="#upper-right">Upper right</a></li>
+</ul>
+</li>
+</ul>
+</li>
+<li class="toctree-l2"><a class="reference internal" href="../spartan3/index.html">Xilinx Spartan 3 FPGAs</a></li>
+<li class="toctree-l2"><a class="reference internal" href="../spartan6/index.html">Xilinx Spartan 6 FPGAs</a></li>
+<li class="toctree-l2"><a class="reference internal" href="../virtex4/index.html">Xilinx Virtex 4 FPGAs</a></li>
+<li class="toctree-l2"><a class="reference internal" href="../virtex5/index.html">Xilinx Virtex 5 FPGAs</a></li>
+<li class="toctree-l2"><a class="reference internal" href="../virtex6/index.html">Xilinx Virtex 6 FPGAs</a></li>
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+      <li class="breadcrumb-item active">Corners — Virtex 2, Spartan 3</li>
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+            <a href="../../_sources/xilinx/virtex2/corner.rst.txt" rel="nofollow"> View page source</a>
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+          <div role="main" class="document" itemscope="itemscope" itemtype="http://schema.org/Article">
+           <div itemprop="articleBody">
+             
+  <section id="corners-virtex-2-spartan-3">
+<span id="virtex2-corner"></span><h1>Corners — Virtex 2, Spartan 3<a class="headerlink" href="#corners-virtex-2-spartan-3" title="Link to this heading"></a></h1>
+<div class="admonition-todo admonition" id="id1">
+<p class="admonition-title">Todo</p>
+<p>document</p>
+</div>
+<section id="lower-left">
+<h2>Lower left<a class="headerlink" href="#lower-left" title="Link to this heading"></a></h2>
+<div class="admonition-todo admonition" id="id2">
+<p class="admonition-title">Todo</p>
+<p>document</p>
+</div>
+<section id="ll-virtex-2">
+<h3><code class="docutils literal notranslate"><span class="pre">LL</span></code> — Virtex 2<a class="headerlink" href="#ll-virtex-2" title="Link to this heading"></a></h3>
+<p>This tile is used on Virtex 2.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="0">Column</th></tr><tr></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="20">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th><th>7</th><th>8</th><th>9</th><th>10</th><th>11</th><th>12</th><th>13</th><th>14</th><th>15</th><th>16</th><th>17</th><th>18</th><th>19</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL-MISC:DISABLEBANDGAP" title="MISC:DISABLEBANDGAP">MISC:DISABLEBANDGAP</a></td><td><a href="#bits-xc2v-LL-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[2]">MISC:BCLK_DIV2[2]</a></td><td>-</td><td><a href="#bits-xc2v-LL-MISC:RAISEVGG" title="MISC:RAISEVGG[0]">MISC:RAISEVGG[0]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL-MISC:M2PIN" title="MISC:M2PIN[0]">MISC:M2PIN[0]</a></td><td><a href="#bits-xc2v-LL-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[3]">MISC:BCLK_DIV2[3]</a></td><td>-</td><td><a href="#bits-xc2v-LL-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[3]">MISC:ZCLK_DIV2[3]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL-MISC:M2PIN" title="MISC:M2PIN[1]">MISC:M2PIN[1]</a></td><td><a href="#bits-xc2v-LL-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[4]">MISC:BCLK_DIV2[4]</a></td><td><a href="#bits-xc2v-LL-MISC:DISABLEVGGGENERATION" title="MISC:DISABLEVGGGENERATION">MISC:DISABLEVGGGENERATION</a></td><td><a href="#bits-xc2v-LL-MISC:RAISEVGG" title="MISC:RAISEVGG[1]">MISC:RAISEVGG[1]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL-MISC:M1PIN" title="MISC:M1PIN[0]">MISC:M1PIN[0]</a></td><td><a href="#bits-xc2v-LL-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[1]">MISC:BCLK_DIV2[1]</a></td><td>-</td><td><a href="#bits-xc2v-LL-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[1]">MISC:ZCLK_DIV2[1]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL-MISC:M0PIN" title="MISC:M0PIN[0]">MISC:M0PIN[0]</a></td><td><a href="#bits-xc2v-LL-MISC:BCLK_DIV2" title="MISC:BCLK_DIV2[0]">MISC:BCLK_DIV2[0]</a></td><td>-</td><td><a href="#bits-xc2v-LL-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[4]">MISC:ZCLK_DIV2[4]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-LL-MISC:M0PIN" title="MISC:M0PIN[1]">MISC:M0PIN[1]</a></td><td><a href="#bits-xc2v-LL-MISC:M1PIN" title="MISC:M1PIN[1]">MISC:M1PIN[1]</a></td><td><a href="#bits-xc2v-LL-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[0]">MISC:ZCLK_DIV2[0]</a></td><td><a href="#bits-xc2v-LL-MISC:ZCLK_DIV2" title="MISC:ZCLK_DIV2[2]">MISC:ZCLK_DIV2[2]</a></td></tr>
+</table>
+<div id="bits-xc2v-LL-MISC:DISABLEBANDGAP"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:DISABLEBANDGAP</th><th>[1, 16, 10]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-LL-MISC:M2PIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:M2PIN</th><th>[1, 16, 12]</th><th>[1, 16, 11]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLDOWN</td><td>0</td><td>1</td></tr>
+<tr><td>PULLNONE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc2v-LL-MISC:M1PIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:M1PIN</th><th>[1, 17, 15]</th><th>[1, 16, 13]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLDOWN</td><td>0</td><td>1</td></tr>
+<tr><td>PULLNONE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc2v-LL-MISC:M0PIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:M0PIN</th><th>[1, 16, 15]</th><th>[1, 16, 14]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLDOWN</td><td>0</td><td>1</td></tr>
+<tr><td>PULLNONE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc2v-LL-MISC:BCLK_DIV2"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:BCLK_DIV2</th><th>[1, 17, 12]</th><th>[1, 17, 11]</th><th>[1, 17, 10]</th><th>[1, 17, 13]</th><th>[1, 17, 14]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-LL-MISC:DISABLEVGGGENERATION"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:DISABLEVGGGENERATION</th><th>[1, 18, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-LL-MISC:ZCLK_DIV2"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:ZCLK_DIV2</th><th>[1, 19, 14]</th><th>[1, 19, 11]</th><th>[1, 19, 15]</th><th>[1, 19, 13]</th><th>[1, 18, 15]</th></tr>
+<tr><td>Non-inverted</td><td>[4]</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-LL-MISC:RAISEVGG"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:RAISEVGG</th><th>[1, 19, 12]</th><th>[1, 19, 10]</th></tr>
+<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
+</table>
+</section>
+<section id="ll-s3">
+<h3><code class="docutils literal notranslate"><span class="pre">LL.S3</span></code><a class="headerlink" href="#ll-s3" title="Link to this heading"></a></h3>
+<p>This tile is used on Spartan 3.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="2">Column</th></tr><tr><th>0</th><th>1</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3-MISC:GATE_GHIGH" title="MISC:GATE_GHIGH">MISC:GATE_GHIGH</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3-MISC:DCI_OSC_SEL" title="MISC:DCI_OSC_SEL[0]">MISC:DCI_OSC_SEL[0]</a></td></tr>
+<tr><td>3</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3-MISC:DCI_OSC_SEL" title="MISC:DCI_OSC_SEL[1]">MISC:DCI_OSC_SEL[1]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3-MISC:DCI_OSC_SEL" title="MISC:DCI_OSC_SEL[2]">MISC:DCI_OSC_SEL[2]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td></tr>
+<tr><td>8</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3-MISC:SEND_VGG" title="MISC:SEND_VGG[0]">MISC:SEND_VGG[0]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3-MISC:SEND_VGG" title="MISC:SEND_VGG[1]">MISC:SEND_VGG[1]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3-MISC:SEND_VGG" title="MISC:SEND_VGG[2]">MISC:SEND_VGG[2]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3-MISC:SEND_VGG" title="MISC:SEND_VGG[3]">MISC:SEND_VGG[3]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3-MISC:VGG_SENDMAX" title="MISC:VGG_SENDMAX">MISC:VGG_SENDMAX</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3-MISC:VGG_ENABLE_OFFCHIP" title="MISC:VGG_ENABLE_OFFCHIP">MISC:VGG_ENABLE_OFFCHIP</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td></tr>
+<tr><td>25</td>
+<td><a href="#bits-xc3s-LL.S3-MISC:M1PIN" title="MISC:M1PIN[1]">MISC:M1PIN[1]</a></td><td>-</td></tr>
+<tr><td>26</td>
+<td><a href="#bits-xc3s-LL.S3-MISC:M1PIN" title="MISC:M1PIN[0]">MISC:M1PIN[0]</a></td><td>-</td></tr>
+<tr><td>27</td>
+<td><a href="#bits-xc3s-LL.S3-MISC:M0PIN" title="MISC:M0PIN[1]">MISC:M0PIN[1]</a></td><td>-</td></tr>
+<tr><td>28</td>
+<td><a href="#bits-xc3s-LL.S3-MISC:M0PIN" title="MISC:M0PIN[0]">MISC:M0PIN[0]</a></td><td>-</td></tr>
+<tr><td>29</td>
+<td><a href="#bits-xc3s-LL.S3-MISC:M2PIN" title="MISC:M2PIN[1]">MISC:M2PIN[1]</a></td><td>-</td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc3s-LL.S3-MISC:M2PIN" title="MISC:M2PIN[0]">MISC:M2PIN[0]</a></td><td>-</td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td></tr>
+<tr><td>63</td>
+<td><a href="#bits-xc3s-LL.S3-DCIRESET1:ENABLE" title="DCIRESET1:ENABLE">DCIRESET1:ENABLE</a></td><td><a href="#bits-xc3s-LL.S3-DCIRESET0:ENABLE" title="DCIRESET0:ENABLE">DCIRESET0:ENABLE</a></td></tr>
+</table>
+<div id="bits-xc3s-LL.S3-MISC:M1PIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:M1PIN</th><th>[0, 0, 25]</th><th>[0, 0, 26]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3-MISC:M0PIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:M0PIN</th><th>[0, 0, 27]</th><th>[0, 0, 28]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3-MISC:M2PIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:M2PIN</th><th>[0, 0, 29]</th><th>[0, 0, 30]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3-DCIRESET0:ENABLE"></div>
+<div id="bits-xc3s-LL.S3-DCIRESET1:ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCIRESET0:ENABLE</th><th>[0, 1, 63]</th></tr>
+<tr><th>DCIRESET1:ENABLE</th><th>[0, 0, 63]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3-MISC:GATE_GHIGH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:GATE_GHIGH</th><th>[0, 1, 1]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3-MISC:DCI_OSC_SEL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:DCI_OSC_SEL</th><th>[0, 1, 4]</th><th>[0, 1, 3]</th><th>[0, 1, 2]</th></tr>
+<tr><td>Non-inverted</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3-MISC:SEND_VGG"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:SEND_VGG</th><th>[0, 1, 11]</th><th>[0, 1, 10]</th><th>[0, 1, 9]</th><th>[0, 1, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3-MISC:VGG_SENDMAX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:VGG_SENDMAX</th><th>[0, 1, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3-MISC:VGG_ENABLE_OFFCHIP"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:VGG_ENABLE_OFFCHIP</th><th>[0, 1, 13]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+</section>
+<section id="ll-s3e">
+<h3><code class="docutils literal notranslate"><span class="pre">LL.S3E</span></code><a class="headerlink" href="#ll-s3e" title="Link to this heading"></a></h3>
+<p>This tile is used on Spartan 3E.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="2">Column</th></tr><tr><th>0</th><th>1</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td></tr>
+<tr><td>8</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-MISC:SEND_VGG" title="MISC:SEND_VGG[0]">MISC:SEND_VGG[0]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-MISC:SEND_VGG" title="MISC:SEND_VGG[1]">MISC:SEND_VGG[1]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-MISC:SEND_VGG" title="MISC:SEND_VGG[2]">MISC:SEND_VGG[2]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-MISC:SEND_VGG" title="MISC:SEND_VGG[3]">MISC:SEND_VGG[3]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-MISC:VGG_SENDMAX" title="MISC:VGG_SENDMAX">MISC:VGG_SENDMAX</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-MISC:VGG_ENABLE_OFFCHIP" title="MISC:VGG_ENABLE_OFFCHIP">MISC:VGG_ENABLE_OFFCHIP</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td></tr>
+<tr><td>17</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-MISC:TEMPSENSOR" title="MISC:TEMPSENSOR[2]">MISC:TEMPSENSOR[2]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-MISC:TEMPSENSOR" title="MISC:TEMPSENSOR[1]">MISC:TEMPSENSOR[1]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3E-MISC:TEMPSENSOR" title="MISC:TEMPSENSOR[0]">MISC:TEMPSENSOR[0]</a></td></tr>
+</table>
+<div id="bits-xc3s-LL.S3E-MISC:SEND_VGG"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:SEND_VGG</th><th>[0, 1, 11]</th><th>[0, 1, 10]</th><th>[0, 1, 9]</th><th>[0, 1, 8]</th></tr>
+<tr><td>Non-inverted</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3E-MISC:VGG_SENDMAX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:VGG_SENDMAX</th><th>[0, 1, 12]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3E-MISC:VGG_ENABLE_OFFCHIP"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:VGG_ENABLE_OFFCHIP</th><th>[0, 1, 13]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3E-MISC:TEMPSENSOR"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TEMPSENSOR</th><th>[0, 1, 17]</th><th>[0, 1, 18]</th><th>[0, 1, 21]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>THERM</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>PGATE</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>BG</td><td>1</td><td>0</td><td>1</td></tr>
+<tr><td>CGATE</td><td>1</td><td>1</td><td>1</td></tr>
+</table>
+</section>
+<section id="ll-s3a">
+<h3><code class="docutils literal notranslate"><span class="pre">LL.S3A</span></code><a class="headerlink" href="#ll-s3a" title="Link to this heading"></a></h3>
+<p>This tile is used on Spartan 3A.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="2">Column</th></tr><tr><th>0</th><th>1</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3A-MISC:TEMPSENSOR" title="MISC:TEMPSENSOR[2]">MISC:TEMPSENSOR[2]</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3A-MISC:TEMPSENSOR" title="MISC:TEMPSENSOR[3]">MISC:TEMPSENSOR[3]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td><a href="#bits-xc3s-LL.S3A-MISC:TEMPSENSOR" title="MISC:TEMPSENSOR[0]">MISC:TEMPSENSOR[0]</a></td><td><a href="#bits-xc3s-LL.S3A-MISC:TEMPSENSOR" title="MISC:TEMPSENSOR[1]">MISC:TEMPSENSOR[1]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td></tr>
+<tr><td>15</td>
+<td><a href="#bits-xc3s-LL.S3A-MISC:CCLK2PIN" title="MISC:CCLK2PIN[0]">MISC:CCLK2PIN[0]</a></td><td><a href="#bits-xc3s-LL.S3A-MISC:CCLK2PIN" title="MISC:CCLK2PIN[1]">MISC:CCLK2PIN[1]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td></tr>
+<tr><td>18</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3A-MISC:SEND_VGG" title="MISC:SEND_VGG[0]">MISC:SEND_VGG[0]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3A-MISC:SEND_VGG" title="MISC:SEND_VGG[1]">MISC:SEND_VGG[1]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3A-MISC:SEND_VGG" title="MISC:SEND_VGG[2]">MISC:SEND_VGG[2]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3A-MISC:SEND_VGG" title="MISC:SEND_VGG[3]">MISC:SEND_VGG[3]</a></td></tr>
+<tr><td>22</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3A-MISC:VGG_SENDMAX" title="MISC:VGG_SENDMAX">MISC:VGG_SENDMAX</a></td></tr>
+<tr><td>23</td>
+<td>-</td><td><a href="#bits-xc3s-LL.S3A-MISC:VGG_ENABLE_OFFCHIP" title="MISC:VGG_ENABLE_OFFCHIP">MISC:VGG_ENABLE_OFFCHIP</a></td></tr>
+<tr><td>24</td>
+<td><a href="#bits-xc3s-LL.S3A-MISC:MOSI2PIN" title="MISC:MOSI2PIN[1]">MISC:MOSI2PIN[1]</a></td><td><a href="#bits-xc3s-LL.S3A-MISC:MOSI2PIN" title="MISC:MOSI2PIN[0]">MISC:MOSI2PIN[0]</a></td></tr>
+</table>
+<div id="bits-xc3s-LL.S3A-MISC:TEMPSENSOR"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TEMPSENSOR</th><th>[0, 1, 4]</th><th>[0, 1, 3]</th><th>[0, 1, 7]</th><th>[0, 0, 7]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>THERM</td><td>0</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>PGATE</td><td>0</td><td>1</td><td>1</td><td>1</td></tr>
+<tr><td>BG</td><td>1</td><td>0</td><td>1</td><td>1</td></tr>
+<tr><td>CGATE</td><td>1</td><td>1</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3A-MISC:CCLK2PIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:CCLK2PIN</th><th>[0, 1, 15]</th><th>[0, 0, 15]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3A-MISC:SEND_VGG"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:SEND_VGG</th><th>[0, 1, 21]</th><th>[0, 1, 20]</th><th>[0, 1, 19]</th><th>[0, 1, 18]</th></tr>
+<tr><td>Non-inverted</td><td>[3]</td><td>[2]</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3A-MISC:VGG_SENDMAX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:VGG_SENDMAX</th><th>[0, 1, 22]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3A-MISC:VGG_ENABLE_OFFCHIP"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:VGG_ENABLE_OFFCHIP</th><th>[0, 1, 23]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LL.S3A-MISC:MOSI2PIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:MOSI2PIN</th><th>[0, 0, 24]</th><th>[0, 1, 24]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+</section>
+</section>
+<section id="upper-left">
+<h2>Upper left<a class="headerlink" href="#upper-left" title="Link to this heading"></a></h2>
+<div class="admonition-todo admonition" id="id3">
+<p class="admonition-title">Todo</p>
+<p>document</p>
+</div>
+<section id="ul-virtex-2">
+<h3><code class="docutils literal notranslate"><span class="pre">UL</span></code> — Virtex 2<a class="headerlink" href="#ul-virtex-2" title="Link to this heading"></a></h3>
+<p>This tile is used on Virtex 2.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="0">Column</th></tr><tr></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="7">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th><th>4</th><th>5</th><th>6</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL-MISC:TDIPIN" title="MISC:TDIPIN[1]">MISC:TDIPIN[1]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL-MISC:TDIPIN" title="MISC:TDIPIN[0]">MISC:TDIPIN[0]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL-MISC:HSWAPENPIN" title="MISC:HSWAPENPIN[1]">MISC:HSWAPENPIN[1]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL-MISC:HSWAPENPIN" title="MISC:HSWAPENPIN[0]">MISC:HSWAPENPIN[0]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UL-MISC:PROGPIN" title="MISC:PROGPIN">MISC:PROGPIN</a></td></tr>
+</table>
+<div id="bits-xc2v-UL-MISC:TDIPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TDIPIN</th><th>[1, 6, 6]</th><th>[1, 6, 7]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLDOWN</td><td>0</td><td>1</td></tr>
+<tr><td>PULLNONE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc2v-UL-MISC:HSWAPENPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:HSWAPENPIN</th><th>[1, 6, 8]</th><th>[1, 6, 10]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLDOWN</td><td>0</td><td>1</td></tr>
+<tr><td>PULLNONE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc2v-UL-MISC:PROGPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:PROGPIN</th><th>[1, 6, 11]</th></tr>
+<tr><td>PULLUP</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>1</td></tr>
+</table>
+</section>
+<section id="ul-s3">
+<h3><code class="docutils literal notranslate"><span class="pre">UL.S3</span></code><a class="headerlink" href="#ul-s3" title="Link to this heading"></a></h3>
+<p>This tile is used on Spartan 3.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="2">Column</th></tr><tr><th>0</th><th>1</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td></tr>
+<tr><td>25</td>
+<td>-</td><td><a href="#bits-xc3s-UL.S3-MISC:PROGPIN" title="MISC:PROGPIN">MISC:PROGPIN</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td><a href="#bits-xc3s-UL.S3-MISC:HSWAPENPIN" title="MISC:HSWAPENPIN[1]">MISC:HSWAPENPIN[1]</a></td></tr>
+<tr><td>27</td>
+<td>-</td><td><a href="#bits-xc3s-UL.S3-MISC:HSWAPENPIN" title="MISC:HSWAPENPIN[0]">MISC:HSWAPENPIN[0]</a></td></tr>
+<tr><td>28</td>
+<td>-</td><td><a href="#bits-xc3s-UL.S3-MISC:TDIPIN" title="MISC:TDIPIN[0]">MISC:TDIPIN[0]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td><a href="#bits-xc3s-UL.S3-MISC:TDIPIN" title="MISC:TDIPIN[1]">MISC:TDIPIN[1]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td><a href="#bits-xc3s-UL.S3-MISC:TESTLL" title="MISC:TESTLL">MISC:TESTLL</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td></tr>
+<tr><td>63</td>
+<td><a href="#bits-xc3s-UL.S3-DCIRESET0:ENABLE" title="DCIRESET0:ENABLE">DCIRESET0:ENABLE</a></td><td><a href="#bits-xc3s-UL.S3-DCIRESET1:ENABLE" title="DCIRESET1:ENABLE">DCIRESET1:ENABLE</a></td></tr>
+</table>
+<div id="bits-xc3s-UL.S3-DCIRESET0:ENABLE"></div>
+<div id="bits-xc3s-UL.S3-DCIRESET1:ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCIRESET0:ENABLE</th><th>[0, 0, 63]</th></tr>
+<tr><th>DCIRESET1:ENABLE</th><th>[0, 1, 63]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-UL.S3-MISC:PROGPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:PROGPIN</th><th>[0, 1, 25]</th></tr>
+<tr><td>PULLUP</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UL.S3-MISC:HSWAPENPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:HSWAPENPIN</th><th>[0, 1, 26]</th><th>[0, 1, 27]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UL.S3-MISC:TDIPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TDIPIN</th><th>[0, 1, 29]</th><th>[0, 1, 28]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UL.S3-MISC:TESTLL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TESTLL</th><th>[0, 1, 32]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+</section>
+<section id="ul-s3e">
+<h3><code class="docutils literal notranslate"><span class="pre">UL.S3E</span></code><a class="headerlink" href="#ul-s3e" title="Link to this heading"></a></h3>
+<p>This tile is used on Spartan 3E.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="2">Column</th></tr><tr><th>0</th><th>1</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td></tr>
+<tr><td>25</td>
+<td>-</td><td><a href="#bits-xc3s-UL.S3E-MISC:PROGPIN" title="MISC:PROGPIN">MISC:PROGPIN</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td></tr>
+<tr><td>28</td>
+<td>-</td><td><a href="#bits-xc3s-UL.S3E-MISC:TDIPIN" title="MISC:TDIPIN[0]">MISC:TDIPIN[0]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td><a href="#bits-xc3s-UL.S3E-MISC:TDIPIN" title="MISC:TDIPIN[1]">MISC:TDIPIN[1]</a></td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td><a href="#bits-xc3s-UL.S3E-MISC:TESTLL" title="MISC:TESTLL">MISC:TESTLL</a></td></tr>
+</table>
+<div id="bits-xc3s-UL.S3E-MISC:PROGPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:PROGPIN</th><th>[0, 1, 25]</th></tr>
+<tr><td>PULLUP</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UL.S3E-MISC:TDIPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TDIPIN</th><th>[0, 1, 29]</th><th>[0, 1, 28]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UL.S3E-MISC:TESTLL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TESTLL</th><th>[0, 1, 32]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+</section>
+<section id="ul-s3a">
+<h3><code class="docutils literal notranslate"><span class="pre">UL.S3A</span></code><a class="headerlink" href="#ul-s3a" title="Link to this heading"></a></h3>
+<p>This tile is used on Spartan 3A.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="2">Column</th></tr><tr><th>0</th><th>1</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td></tr>
+<tr><td>25</td>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-MISC:PROGPIN" title="MISC:PROGPIN">MISC:PROGPIN</a></td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td></tr>
+<tr><td>28</td>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-MISC:TDIPIN" title="MISC:TDIPIN[0]">MISC:TDIPIN[0]</a></td></tr>
+<tr><td>29</td>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-MISC:TDIPIN" title="MISC:TDIPIN[1]">MISC:TDIPIN[1]</a></td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc3s-UL.S3A-MISC:TMSPIN" title="MISC:TMSPIN[0]">MISC:TMSPIN[0]</a></td><td>-</td></tr>
+<tr><td>31</td>
+<td><a href="#bits-xc3s-UL.S3A-MISC:TMSPIN" title="MISC:TMSPIN[1]">MISC:TMSPIN[1]</a></td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td><a href="#bits-xc3s-UL.S3A-MISC:TESTLL" title="MISC:TESTLL">MISC:TESTLL</a></td></tr>
+</table>
+<div id="bits-xc3s-UL.S3A-MISC:TMSPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TMSPIN</th><th>[0, 0, 31]</th><th>[0, 0, 30]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UL.S3A-MISC:PROGPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:PROGPIN</th><th>[0, 1, 25]</th></tr>
+<tr><td>PULLUP</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UL.S3A-MISC:TDIPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TDIPIN</th><th>[0, 1, 29]</th><th>[0, 1, 28]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UL.S3A-MISC:TESTLL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TESTLL</th><th>[0, 1, 32]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+</section>
+</section>
+<section id="lower-right">
+<h2>Lower right<a class="headerlink" href="#lower-right" title="Link to this heading"></a></h2>
+<div class="admonition-todo admonition" id="id4">
+<p class="admonition-title">Todo</p>
+<p>document</p>
+</div>
+<section id="lr-virtex-2">
+<h3><code class="docutils literal notranslate"><span class="pre">LR</span></code> — Virtex 2<a class="headerlink" href="#lr-virtex-2" title="Link to this heading"></a></h3>
+<p>This tile is used on Virtex 2.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR-STARTUP:GTS_GSR_ENABLE" title="STARTUP:GTS_GSR_ENABLE">STARTUP:GTS_GSR_ENABLE</a></td><td><a href="#bits-xc2v-LR-STARTUP:GWE_SYNC" title="STARTUP:GWE_SYNC">STARTUP:GWE_SYNC</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR-STARTUP:GTS_SYNC" title="STARTUP:GTS_SYNC">STARTUP:GTS_SYNC</a></td><td><a href="#bits-xc2v-LR-STARTUP:GSR_SYNC" title="STARTUP:GSR_SYNC">STARTUP:GSR_SYNC</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR-ICAP:ENABLE" title="ICAP:ENABLE">ICAP:ENABLE</a></td><td><a href="#bits-xc2v-LR-MISC:DONEPIN" title="MISC:DONEPIN">MISC:DONEPIN</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-LR-MISC:POWERDOWNPIN" title="MISC:POWERDOWNPIN">MISC:POWERDOWNPIN</a></td><td><a href="#bits-xc2v-LR-MISC:CCLKPIN" title="MISC:CCLKPIN">MISC:CCLKPIN</a></td></tr>
+</table>
+<div id="bits-xc2v-LR-STARTUP:GTS_GSR_ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>STARTUP:GTS_GSR_ENABLE</th><th>[0, 2, 4]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-LR-STARTUP:GTS_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>STARTUP:GTS_SYNC</th><th>[0, 2, 5]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-LR-ICAP:ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>ICAP:ENABLE</th><th>[0, 2, 6]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-LR-MISC:POWERDOWNPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:POWERDOWNPIN</th><th>[0, 2, 7]</th></tr>
+<tr><td>PULLUP</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>1</td></tr>
+</table>
+<div id="bits-xc2v-LR-STARTUP:GWE_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>STARTUP:GWE_SYNC</th><th>[0, 3, 4]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-LR-STARTUP:GSR_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>STARTUP:GSR_SYNC</th><th>[0, 3, 5]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-LR-MISC:DONEPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:DONEPIN</th><th>[0, 3, 6]</th></tr>
+<tr><td>PULLUP</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>1</td></tr>
+</table>
+<div id="bits-xc2v-LR-MISC:CCLKPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:CCLKPIN</th><th>[0, 3, 7]</th></tr>
+<tr><td>PULLUP</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>1</td></tr>
+</table>
+</section>
+<section id="lr-s3">
+<h3><code class="docutils literal notranslate"><span class="pre">LR.S3</span></code><a class="headerlink" href="#lr-s3" title="Link to this heading"></a></h3>
+<p>This tile is used on Spartan 3.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="2">Column</th></tr><tr><th>0</th><th>1</th></tr>
+<tr><td>0</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-STARTUP:GSR_SYNC" title="STARTUP:GSR_SYNC">STARTUP:GSR_SYNC</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-STARTUP:GTS_SYNC" title="STARTUP:GTS_SYNC">STARTUP:GTS_SYNC</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-ICAP:ENABLE" title="ICAP:ENABLE">ICAP:ENABLE</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-STARTUP:GTS_GSR_ENABLE" title="STARTUP:GTS_GSR_ENABLE">STARTUP:GTS_GSR_ENABLE</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td></tr>
+<tr><td>14</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-MISC:DONEPIN" title="MISC:DONEPIN">MISC:DONEPIN</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3-MISC:CCLKPIN" title="MISC:CCLKPIN">MISC:CCLKPIN</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td></tr>
+<tr><td>63</td>
+<td><a href="#bits-xc3s-LR.S3-DCIRESET0:ENABLE" title="DCIRESET0:ENABLE">DCIRESET0:ENABLE</a></td><td><a href="#bits-xc3s-LR.S3-DCIRESET1:ENABLE" title="DCIRESET1:ENABLE">DCIRESET1:ENABLE</a></td></tr>
+</table>
+<div id="bits-xc3s-LR.S3-DCIRESET0:ENABLE"></div>
+<div id="bits-xc3s-LR.S3-DCIRESET1:ENABLE"></div>
+<div id="bits-xc3s-LR.S3-ICAP:ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCIRESET0:ENABLE</th><th>[0, 0, 63]</th></tr>
+<tr><th>DCIRESET1:ENABLE</th><th>[0, 1, 63]</th></tr>
+<tr><th>ICAP:ENABLE</th><th>[0, 1, 3]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LR.S3-STARTUP:GSR_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>STARTUP:GSR_SYNC</th><th>[0, 1, 0]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LR.S3-STARTUP:GTS_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>STARTUP:GTS_SYNC</th><th>[0, 1, 1]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LR.S3-STARTUP:GTS_GSR_ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>STARTUP:GTS_GSR_ENABLE</th><th>[0, 1, 4]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LR.S3-MISC:DONEPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:DONEPIN</th><th>[0, 1, 14]</th></tr>
+<tr><td>PULLUP</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-LR.S3-MISC:CCLKPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:CCLKPIN</th><th>[0, 1, 15]</th></tr>
+<tr><td>PULLUP</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>1</td></tr>
+</table>
+</section>
+<section id="lr-s3e">
+<h3><code class="docutils literal notranslate"><span class="pre">LR.S3E</span></code><a class="headerlink" href="#lr-s3e" title="Link to this heading"></a></h3>
+<p>This tile is used on Spartan 3E.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="2">Column</th></tr><tr><th>0</th><th>1</th></tr>
+<tr><td>0</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-STARTUP:GSR_SYNC" title="STARTUP:GSR_SYNC">STARTUP:GSR_SYNC</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-STARTUP:GTS_SYNC" title="STARTUP:GTS_SYNC">STARTUP:GTS_SYNC</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-STARTUP:GTS_GSR_ENABLE" title="STARTUP:GTS_GSR_ENABLE">STARTUP:GTS_GSR_ENABLE</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td></tr>
+<tr><td>14</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-MISC:DONEPIN" title="MISC:DONEPIN">MISC:DONEPIN</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3E-MISC:CCLKPIN" title="MISC:CCLKPIN">MISC:CCLKPIN</a></td></tr>
+</table>
+<div id="bits-xc3s-LR.S3E-STARTUP:GSR_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>STARTUP:GSR_SYNC</th><th>[0, 1, 0]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LR.S3E-STARTUP:GTS_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>STARTUP:GTS_SYNC</th><th>[0, 1, 1]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LR.S3E-STARTUP:GTS_GSR_ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>STARTUP:GTS_GSR_ENABLE</th><th>[0, 1, 4]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LR.S3E-MISC:DONEPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:DONEPIN</th><th>[0, 1, 14]</th></tr>
+<tr><td>PULLUP</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-LR.S3E-MISC:CCLKPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:CCLKPIN</th><th>[0, 1, 15]</th></tr>
+<tr><td>PULLUP</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>1</td></tr>
+</table>
+</section>
+<section id="lr-s3a">
+<h3><code class="docutils literal notranslate"><span class="pre">LR.S3A</span></code><a class="headerlink" href="#lr-s3a" title="Link to this heading"></a></h3>
+<p>This tile is used on Spartan 3A.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="2">Column</th></tr><tr><th>0</th><th>1</th></tr>
+<tr><td>0</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3A-STARTUP:GSR_SYNC" title="STARTUP:GSR_SYNC">STARTUP:GSR_SYNC</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3A-STARTUP:GTS_SYNC" title="STARTUP:GTS_SYNC">STARTUP:GTS_SYNC</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3A-SPI_ACCESS:ENABLE" title="SPI_ACCESS:ENABLE">SPI_ACCESS:ENABLE</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3A-STARTUP:GTS_GSR_ENABLE" title="STARTUP:GTS_GSR_ENABLE">STARTUP:GTS_GSR_ENABLE</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td><a href="#bits-xc3s-LR.S3A-MISC:DONEPIN" title="MISC:DONEPIN">MISC:DONEPIN</a></td></tr>
+</table>
+<div id="bits-xc3s-LR.S3A-STARTUP:GSR_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>STARTUP:GSR_SYNC</th><th>[0, 1, 0]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LR.S3A-STARTUP:GTS_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>STARTUP:GTS_SYNC</th><th>[0, 1, 1]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LR.S3A-SPI_ACCESS:ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>SPI_ACCESS:ENABLE</th><th>[0, 1, 3]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LR.S3A-STARTUP:GTS_GSR_ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>STARTUP:GTS_GSR_ENABLE</th><th>[0, 1, 4]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-LR.S3A-MISC:DONEPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:DONEPIN</th><th>[0, 1, 6]</th></tr>
+<tr><td>PULLUP</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>1</td></tr>
+</table>
+</section>
+</section>
+<section id="upper-right">
+<h2>Upper right<a class="headerlink" href="#upper-right" title="Link to this heading"></a></h2>
+<div class="admonition-todo admonition" id="id5">
+<p class="admonition-title">Todo</p>
+<p>document</p>
+</div>
+<section id="ur-v2">
+<h3><code class="docutils literal notranslate"><span class="pre">UR.V2</span></code><a class="headerlink" href="#ur-v2" title="Link to this heading"></a></h3>
+<p>This tile is used on Virtex 2.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[0]">~BSCAN:USERID[0]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[1]">~BSCAN:USERID[1]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[2]">~BSCAN:USERID[2]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[3]">~BSCAN:USERID[3]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[4]">~BSCAN:USERID[4]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[5]">~BSCAN:USERID[5]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[6]">~BSCAN:USERID[6]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[7]">~BSCAN:USERID[7]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[8]">~BSCAN:USERID[8]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[9]">~BSCAN:USERID[9]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[10]">~BSCAN:USERID[10]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[11]">~BSCAN:USERID[11]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[12]">~BSCAN:USERID[12]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[13]">~BSCAN:USERID[13]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[14]">~BSCAN:USERID[14]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[15]">~BSCAN:USERID[15]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[16]">~BSCAN:USERID[16]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[17]">~BSCAN:USERID[17]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[18]">~BSCAN:USERID[18]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[19]">~BSCAN:USERID[19]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[20]">~BSCAN:USERID[20]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[21]">~BSCAN:USERID[21]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[22]">~BSCAN:USERID[22]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[23]">~BSCAN:USERID[23]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[24]">~BSCAN:USERID[24]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[25]">~BSCAN:USERID[25]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[26]">~BSCAN:USERID[26]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[27]">~BSCAN:USERID[27]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[28]">~BSCAN:USERID[28]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[29]">~BSCAN:USERID[29]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[30]">~BSCAN:USERID[30]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:USERID" title="~BSCAN:USERID[31]">~BSCAN:USERID[31]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-BSCAN:TDO_ENABLE" title="BSCAN:TDO_ENABLE[0]">BSCAN:TDO_ENABLE[0]</a></td><td><a href="#bits-xc2v-UR.V2-BSCAN:TDO_ENABLE" title="BSCAN:TDO_ENABLE[1]">BSCAN:TDO_ENABLE[1]</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TMSPIN" title="MISC:TMSPIN[1]">MISC:TMSPIN[1]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TCKPIN" title="MISC:TCKPIN[1]">MISC:TCKPIN[1]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TMSPIN" title="MISC:TMSPIN[0]">MISC:TMSPIN[0]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TDOPIN" title="MISC:TDOPIN[1]">MISC:TDOPIN[1]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TCKPIN" title="MISC:TCKPIN[0]">MISC:TCKPIN[0]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2-MISC:TDOPIN" title="MISC:TDOPIN[0]">MISC:TDOPIN[0]</a></td></tr>
+</table>
+<div id="bits-xc2v-UR.V2-BSCAN:USERID"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>BSCAN:USERID</th><th>[0, 3, 19]</th><th>[0, 2, 19]</th><th>[0, 3, 18]</th><th>[0, 2, 18]</th><th>[0, 3, 17]</th><th>[0, 2, 17]</th><th>[0, 3, 16]</th><th>[0, 2, 16]</th><th>[0, 3, 15]</th><th>[0, 2, 15]</th><th>[0, 3, 14]</th><th>[0, 2, 14]</th><th>[0, 3, 13]</th><th>[0, 2, 13]</th><th>[0, 3, 12]</th><th>[0, 2, 12]</th><th>[0, 3, 11]</th><th>[0, 2, 11]</th><th>[0, 3, 10]</th><th>[0, 2, 10]</th><th>[0, 3, 9]</th><th>[0, 2, 9]</th><th>[0, 3, 8]</th><th>[0, 2, 8]</th><th>[0, 3, 7]</th><th>[0, 2, 7]</th><th>[0, 3, 6]</th><th>[0, 2, 6]</th><th>[0, 3, 5]</th><th>[0, 2, 5]</th><th>[0, 3, 4]</th><th>[0, 2, 4]</th></tr>
+<tr><td>Inverted</td><td>~[31]</td><td>~[30]</td><td>~[29]</td><td>~[28]</td><td>~[27]</td><td>~[26]</td><td>~[25]</td><td>~[24]</td><td>~[23]</td><td>~[22]</td><td>~[21]</td><td>~[20]</td><td>~[19]</td><td>~[18]</td><td>~[17]</td><td>~[16]</td><td>~[15]</td><td>~[14]</td><td>~[13]</td><td>~[12]</td><td>~[11]</td><td>~[10]</td><td>~[9]</td><td>~[8]</td><td>~[7]</td><td>~[6]</td><td>~[5]</td><td>~[4]</td><td>~[3]</td><td>~[2]</td><td>~[1]</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-UR.V2-BSCAN:TDO_ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>BSCAN:TDO_ENABLE</th><th>[0, 3, 20]</th><th>[0, 2, 20]</th></tr>
+<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-UR.V2-MISC:TMSPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TMSPIN</th><th>[1, 3, 6]</th><th>[1, 3, 8]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLDOWN</td><td>0</td><td>1</td></tr>
+<tr><td>PULLNONE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc2v-UR.V2-MISC:TCKPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TCKPIN</th><th>[1, 3, 7]</th><th>[1, 3, 10]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLDOWN</td><td>0</td><td>1</td></tr>
+<tr><td>PULLNONE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc2v-UR.V2-MISC:TDOPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TDOPIN</th><th>[1, 3, 9]</th><th>[1, 3, 11]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLDOWN</td><td>0</td><td>1</td></tr>
+<tr><td>PULLNONE</td><td>1</td><td>0</td></tr>
+</table>
+</section>
+<section id="ur-v2p">
+<h3><code class="docutils literal notranslate"><span class="pre">UR.V2P</span></code><a class="headerlink" href="#ur-v2p" title="Link to this heading"></a></h3>
+<p>This tile is used on Virtex 2 Pro.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[0]">~BSCAN:USERID[0]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[1]">~BSCAN:USERID[1]</a></td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[2]">~BSCAN:USERID[2]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[3]">~BSCAN:USERID[3]</a></td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[4]">~BSCAN:USERID[4]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[5]">~BSCAN:USERID[5]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[6]">~BSCAN:USERID[6]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[7]">~BSCAN:USERID[7]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[8]">~BSCAN:USERID[8]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[9]">~BSCAN:USERID[9]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[10]">~BSCAN:USERID[10]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[11]">~BSCAN:USERID[11]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[12]">~BSCAN:USERID[12]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[13]">~BSCAN:USERID[13]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[14]">~BSCAN:USERID[14]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[15]">~BSCAN:USERID[15]</a></td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[16]">~BSCAN:USERID[16]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[17]">~BSCAN:USERID[17]</a></td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[18]">~BSCAN:USERID[18]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[19]">~BSCAN:USERID[19]</a></td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[20]">~BSCAN:USERID[20]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[21]">~BSCAN:USERID[21]</a></td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[22]">~BSCAN:USERID[22]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[23]">~BSCAN:USERID[23]</a></td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[24]">~BSCAN:USERID[24]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[25]">~BSCAN:USERID[25]</a></td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[26]">~BSCAN:USERID[26]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[27]">~BSCAN:USERID[27]</a></td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[28]">~BSCAN:USERID[28]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[29]">~BSCAN:USERID[29]</a></td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[30]">~BSCAN:USERID[30]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:USERID" title="~BSCAN:USERID[31]">~BSCAN:USERID[31]</a></td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-BSCAN:TDO_ENABLE" title="BSCAN:TDO_ENABLE[0]">BSCAN:TDO_ENABLE[0]</a></td><td><a href="#bits-xc2v-UR.V2P-BSCAN:TDO_ENABLE" title="BSCAN:TDO_ENABLE[1]">BSCAN:TDO_ENABLE[1]</a></td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-JTAGPPC:ENABLE" title="JTAGPPC:ENABLE">JTAGPPC:ENABLE</a></td></tr>
+</table>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TMSPIN" title="MISC:TMSPIN[1]">MISC:TMSPIN[1]</a></td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TCKPIN" title="MISC:TCKPIN[1]">MISC:TCKPIN[1]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TMSPIN" title="MISC:TMSPIN[0]">MISC:TMSPIN[0]</a></td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TDOPIN" title="MISC:TDOPIN[1]">MISC:TDOPIN[1]</a></td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TCKPIN" title="MISC:TCKPIN[0]">MISC:TCKPIN[0]</a></td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-UR.V2P-MISC:TDOPIN" title="MISC:TDOPIN[0]">MISC:TDOPIN[0]</a></td></tr>
+</table>
+<div id="bits-xc2v-UR.V2P-BSCAN:USERID"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>BSCAN:USERID</th><th>[0, 3, 19]</th><th>[0, 2, 19]</th><th>[0, 3, 18]</th><th>[0, 2, 18]</th><th>[0, 3, 17]</th><th>[0, 2, 17]</th><th>[0, 3, 16]</th><th>[0, 2, 16]</th><th>[0, 3, 15]</th><th>[0, 2, 15]</th><th>[0, 3, 14]</th><th>[0, 2, 14]</th><th>[0, 3, 13]</th><th>[0, 2, 13]</th><th>[0, 3, 12]</th><th>[0, 2, 12]</th><th>[0, 3, 11]</th><th>[0, 2, 11]</th><th>[0, 3, 10]</th><th>[0, 2, 10]</th><th>[0, 3, 9]</th><th>[0, 2, 9]</th><th>[0, 3, 8]</th><th>[0, 2, 8]</th><th>[0, 3, 7]</th><th>[0, 2, 7]</th><th>[0, 3, 6]</th><th>[0, 2, 6]</th><th>[0, 3, 5]</th><th>[0, 2, 5]</th><th>[0, 3, 4]</th><th>[0, 2, 4]</th></tr>
+<tr><td>Inverted</td><td>~[31]</td><td>~[30]</td><td>~[29]</td><td>~[28]</td><td>~[27]</td><td>~[26]</td><td>~[25]</td><td>~[24]</td><td>~[23]</td><td>~[22]</td><td>~[21]</td><td>~[20]</td><td>~[19]</td><td>~[18]</td><td>~[17]</td><td>~[16]</td><td>~[15]</td><td>~[14]</td><td>~[13]</td><td>~[12]</td><td>~[11]</td><td>~[10]</td><td>~[9]</td><td>~[8]</td><td>~[7]</td><td>~[6]</td><td>~[5]</td><td>~[4]</td><td>~[3]</td><td>~[2]</td><td>~[1]</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-UR.V2P-BSCAN:TDO_ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>BSCAN:TDO_ENABLE</th><th>[0, 3, 20]</th><th>[0, 2, 20]</th></tr>
+<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-UR.V2P-JTAGPPC:ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>JTAGPPC:ENABLE</th><th>[0, 3, 42]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-UR.V2P-MISC:TMSPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TMSPIN</th><th>[1, 3, 6]</th><th>[1, 3, 8]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLDOWN</td><td>0</td><td>1</td></tr>
+<tr><td>PULLNONE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc2v-UR.V2P-MISC:TCKPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TCKPIN</th><th>[1, 3, 7]</th><th>[1, 3, 10]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLDOWN</td><td>0</td><td>1</td></tr>
+<tr><td>PULLNONE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc2v-UR.V2P-MISC:TDOPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TDOPIN</th><th>[1, 3, 9]</th><th>[1, 3, 11]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLDOWN</td><td>0</td><td>1</td></tr>
+<tr><td>PULLNONE</td><td>1</td><td>0</td></tr>
+</table>
+</section>
+<section id="ur-s3">
+<h3><code class="docutils literal notranslate"><span class="pre">UR.S3</span></code><a class="headerlink" href="#ur-s3" title="Link to this heading"></a></h3>
+<p>This tile is used on Spartan 3.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="2">Column</th></tr><tr><th>0</th><th>1</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td></tr>
+<tr><td>13</td>
+<td><a href="#bits-xc3s-UR.S3-MISC:TDOPIN" title="MISC:TDOPIN[1]">MISC:TDOPIN[1]</a></td><td><a href="#bits-xc3s-UR.S3-MISC:TDOPIN" title="MISC:TDOPIN[0]">MISC:TDOPIN[0]</a></td></tr>
+<tr><td>14</td>
+<td><a href="#bits-xc3s-UR.S3-MISC:TCKPIN" title="MISC:TCKPIN[0]">MISC:TCKPIN[0]</a></td><td><a href="#bits-xc3s-UR.S3-MISC:TCKPIN" title="MISC:TCKPIN[1]">MISC:TCKPIN[1]</a></td></tr>
+<tr><td>15</td>
+<td><a href="#bits-xc3s-UR.S3-MISC:TMSPIN" title="MISC:TMSPIN[1]">MISC:TMSPIN[1]</a></td><td><a href="#bits-xc3s-UR.S3-MISC:TMSPIN" title="MISC:TMSPIN[0]">MISC:TMSPIN[0]</a></td></tr>
+<tr><td>16</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:TDO_ENABLE" title="BSCAN:TDO_ENABLE[0]">BSCAN:TDO_ENABLE[0]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:TDO_ENABLE" title="BSCAN:TDO_ENABLE[1]">BSCAN:TDO_ENABLE[1]</a></td></tr>
+<tr><td>17</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[31]">~BSCAN:USERID[31]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[30]">~BSCAN:USERID[30]</a></td></tr>
+<tr><td>18</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[28]">~BSCAN:USERID[28]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[29]">~BSCAN:USERID[29]</a></td></tr>
+<tr><td>19</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[27]">~BSCAN:USERID[27]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[26]">~BSCAN:USERID[26]</a></td></tr>
+<tr><td>20</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[24]">~BSCAN:USERID[24]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[25]">~BSCAN:USERID[25]</a></td></tr>
+<tr><td>21</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[23]">~BSCAN:USERID[23]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[22]">~BSCAN:USERID[22]</a></td></tr>
+<tr><td>22</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[21]">~BSCAN:USERID[21]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[20]">~BSCAN:USERID[20]</a></td></tr>
+<tr><td>23</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[19]">~BSCAN:USERID[19]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[18]">~BSCAN:USERID[18]</a></td></tr>
+<tr><td>24</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[17]">~BSCAN:USERID[17]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[16]">~BSCAN:USERID[16]</a></td></tr>
+<tr><td>25</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[15]">~BSCAN:USERID[15]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[14]">~BSCAN:USERID[14]</a></td></tr>
+<tr><td>26</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[13]">~BSCAN:USERID[13]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[12]">~BSCAN:USERID[12]</a></td></tr>
+<tr><td>27</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[11]">~BSCAN:USERID[11]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[10]">~BSCAN:USERID[10]</a></td></tr>
+<tr><td>28</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[9]">~BSCAN:USERID[9]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[8]">~BSCAN:USERID[8]</a></td></tr>
+<tr><td>29</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[7]">~BSCAN:USERID[7]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[6]">~BSCAN:USERID[6]</a></td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[5]">~BSCAN:USERID[5]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[4]">~BSCAN:USERID[4]</a></td></tr>
+<tr><td>31</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[3]">~BSCAN:USERID[3]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[2]">~BSCAN:USERID[2]</a></td></tr>
+<tr><td>32</td>
+<td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[1]">~BSCAN:USERID[1]</a></td><td><a href="#bits-xc3s-UR.S3-BSCAN:USERID" title="~BSCAN:USERID[0]">~BSCAN:USERID[0]</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td></tr>
+<tr><td>59</td>
+<td>-</td><td>-</td></tr>
+<tr><td>60</td>
+<td>-</td><td>-</td></tr>
+<tr><td>61</td>
+<td>-</td><td>-</td></tr>
+<tr><td>62</td>
+<td>-</td><td>-</td></tr>
+<tr><td>63</td>
+<td><a href="#bits-xc3s-UR.S3-DCIRESET0:ENABLE" title="DCIRESET0:ENABLE">DCIRESET0:ENABLE</a></td><td><a href="#bits-xc3s-UR.S3-DCIRESET1:ENABLE" title="DCIRESET1:ENABLE">DCIRESET1:ENABLE</a></td></tr>
+</table>
+<div id="bits-xc3s-UR.S3-MISC:TCKPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TCKPIN</th><th>[0, 1, 14]</th><th>[0, 0, 14]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UR.S3-BSCAN:TDO_ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>BSCAN:TDO_ENABLE</th><th>[0, 1, 16]</th><th>[0, 0, 16]</th></tr>
+<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-UR.S3-DCIRESET0:ENABLE"></div>
+<div id="bits-xc3s-UR.S3-DCIRESET1:ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>DCIRESET0:ENABLE</th><th>[0, 0, 63]</th></tr>
+<tr><th>DCIRESET1:ENABLE</th><th>[0, 1, 63]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-UR.S3-MISC:TDOPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TDOPIN</th><th>[0, 0, 13]</th><th>[0, 1, 13]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UR.S3-MISC:TMSPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TMSPIN</th><th>[0, 0, 15]</th><th>[0, 1, 15]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UR.S3-BSCAN:USERID"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>BSCAN:USERID</th><th>[0, 0, 17]</th><th>[0, 1, 17]</th><th>[0, 1, 18]</th><th>[0, 0, 18]</th><th>[0, 0, 19]</th><th>[0, 1, 19]</th><th>[0, 1, 20]</th><th>[0, 0, 20]</th><th>[0, 0, 21]</th><th>[0, 1, 21]</th><th>[0, 0, 22]</th><th>[0, 1, 22]</th><th>[0, 0, 23]</th><th>[0, 1, 23]</th><th>[0, 0, 24]</th><th>[0, 1, 24]</th><th>[0, 0, 25]</th><th>[0, 1, 25]</th><th>[0, 0, 26]</th><th>[0, 1, 26]</th><th>[0, 0, 27]</th><th>[0, 1, 27]</th><th>[0, 0, 28]</th><th>[0, 1, 28]</th><th>[0, 0, 29]</th><th>[0, 1, 29]</th><th>[0, 0, 30]</th><th>[0, 1, 30]</th><th>[0, 0, 31]</th><th>[0, 1, 31]</th><th>[0, 0, 32]</th><th>[0, 1, 32]</th></tr>
+<tr><td>Inverted</td><td>~[31]</td><td>~[30]</td><td>~[29]</td><td>~[28]</td><td>~[27]</td><td>~[26]</td><td>~[25]</td><td>~[24]</td><td>~[23]</td><td>~[22]</td><td>~[21]</td><td>~[20]</td><td>~[19]</td><td>~[18]</td><td>~[17]</td><td>~[16]</td><td>~[15]</td><td>~[14]</td><td>~[13]</td><td>~[12]</td><td>~[11]</td><td>~[10]</td><td>~[9]</td><td>~[8]</td><td>~[7]</td><td>~[6]</td><td>~[5]</td><td>~[4]</td><td>~[3]</td><td>~[2]</td><td>~[1]</td><td>~[0]</td></tr>
+</table>
+</section>
+<section id="ur-s3e">
+<h3><code class="docutils literal notranslate"><span class="pre">UR.S3E</span></code><a class="headerlink" href="#ur-s3e" title="Link to this heading"></a></h3>
+<p>This tile is used on Spartan 3E.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="2">Column</th></tr><tr><th>0</th><th>1</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td></tr>
+<tr><td>13</td>
+<td><a href="#bits-xc3s-UR.S3E-MISC:TDOPIN" title="MISC:TDOPIN[1]">MISC:TDOPIN[1]</a></td><td><a href="#bits-xc3s-UR.S3E-MISC:TDOPIN" title="MISC:TDOPIN[0]">MISC:TDOPIN[0]</a></td></tr>
+<tr><td>14</td>
+<td><a href="#bits-xc3s-UR.S3E-MISC:TCKPIN" title="MISC:TCKPIN[0]">MISC:TCKPIN[0]</a></td><td><a href="#bits-xc3s-UR.S3E-MISC:TCKPIN" title="MISC:TCKPIN[1]">MISC:TCKPIN[1]</a></td></tr>
+<tr><td>15</td>
+<td><a href="#bits-xc3s-UR.S3E-MISC:TMSPIN" title="MISC:TMSPIN[1]">MISC:TMSPIN[1]</a></td><td><a href="#bits-xc3s-UR.S3E-MISC:TMSPIN" title="MISC:TMSPIN[0]">MISC:TMSPIN[0]</a></td></tr>
+<tr><td>16</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:TDO_ENABLE" title="BSCAN:TDO_ENABLE[0]">BSCAN:TDO_ENABLE[0]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:TDO_ENABLE" title="BSCAN:TDO_ENABLE[1]">BSCAN:TDO_ENABLE[1]</a></td></tr>
+<tr><td>17</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[31]">~BSCAN:USERID[31]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[30]">~BSCAN:USERID[30]</a></td></tr>
+<tr><td>18</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[28]">~BSCAN:USERID[28]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[29]">~BSCAN:USERID[29]</a></td></tr>
+<tr><td>19</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[27]">~BSCAN:USERID[27]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[26]">~BSCAN:USERID[26]</a></td></tr>
+<tr><td>20</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[24]">~BSCAN:USERID[24]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[25]">~BSCAN:USERID[25]</a></td></tr>
+<tr><td>21</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[23]">~BSCAN:USERID[23]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[22]">~BSCAN:USERID[22]</a></td></tr>
+<tr><td>22</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[21]">~BSCAN:USERID[21]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[20]">~BSCAN:USERID[20]</a></td></tr>
+<tr><td>23</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[19]">~BSCAN:USERID[19]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[18]">~BSCAN:USERID[18]</a></td></tr>
+<tr><td>24</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[17]">~BSCAN:USERID[17]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[16]">~BSCAN:USERID[16]</a></td></tr>
+<tr><td>25</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[15]">~BSCAN:USERID[15]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[14]">~BSCAN:USERID[14]</a></td></tr>
+<tr><td>26</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[13]">~BSCAN:USERID[13]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[12]">~BSCAN:USERID[12]</a></td></tr>
+<tr><td>27</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[11]">~BSCAN:USERID[11]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[10]">~BSCAN:USERID[10]</a></td></tr>
+<tr><td>28</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[9]">~BSCAN:USERID[9]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[8]">~BSCAN:USERID[8]</a></td></tr>
+<tr><td>29</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[7]">~BSCAN:USERID[7]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[6]">~BSCAN:USERID[6]</a></td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[5]">~BSCAN:USERID[5]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[4]">~BSCAN:USERID[4]</a></td></tr>
+<tr><td>31</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[3]">~BSCAN:USERID[3]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[2]">~BSCAN:USERID[2]</a></td></tr>
+<tr><td>32</td>
+<td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[1]">~BSCAN:USERID[1]</a></td><td><a href="#bits-xc3s-UR.S3E-BSCAN:USERID" title="~BSCAN:USERID[0]">~BSCAN:USERID[0]</a></td></tr>
+</table>
+<div id="bits-xc3s-UR.S3E-MISC:TCKPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TCKPIN</th><th>[0, 1, 14]</th><th>[0, 0, 14]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UR.S3E-BSCAN:TDO_ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>BSCAN:TDO_ENABLE</th><th>[0, 1, 16]</th><th>[0, 0, 16]</th></tr>
+<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-UR.S3E-MISC:TDOPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TDOPIN</th><th>[0, 0, 13]</th><th>[0, 1, 13]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UR.S3E-MISC:TMSPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TMSPIN</th><th>[0, 0, 15]</th><th>[0, 1, 15]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UR.S3E-BSCAN:USERID"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>BSCAN:USERID</th><th>[0, 0, 17]</th><th>[0, 1, 17]</th><th>[0, 1, 18]</th><th>[0, 0, 18]</th><th>[0, 0, 19]</th><th>[0, 1, 19]</th><th>[0, 1, 20]</th><th>[0, 0, 20]</th><th>[0, 0, 21]</th><th>[0, 1, 21]</th><th>[0, 0, 22]</th><th>[0, 1, 22]</th><th>[0, 0, 23]</th><th>[0, 1, 23]</th><th>[0, 0, 24]</th><th>[0, 1, 24]</th><th>[0, 0, 25]</th><th>[0, 1, 25]</th><th>[0, 0, 26]</th><th>[0, 1, 26]</th><th>[0, 0, 27]</th><th>[0, 1, 27]</th><th>[0, 0, 28]</th><th>[0, 1, 28]</th><th>[0, 0, 29]</th><th>[0, 1, 29]</th><th>[0, 0, 30]</th><th>[0, 1, 30]</th><th>[0, 0, 31]</th><th>[0, 1, 31]</th><th>[0, 0, 32]</th><th>[0, 1, 32]</th></tr>
+<tr><td>Inverted</td><td>~[31]</td><td>~[30]</td><td>~[29]</td><td>~[28]</td><td>~[27]</td><td>~[26]</td><td>~[25]</td><td>~[24]</td><td>~[23]</td><td>~[22]</td><td>~[21]</td><td>~[20]</td><td>~[19]</td><td>~[18]</td><td>~[17]</td><td>~[16]</td><td>~[15]</td><td>~[14]</td><td>~[13]</td><td>~[12]</td><td>~[11]</td><td>~[10]</td><td>~[9]</td><td>~[8]</td><td>~[7]</td><td>~[6]</td><td>~[5]</td><td>~[4]</td><td>~[3]</td><td>~[2]</td><td>~[1]</td><td>~[0]</td></tr>
+</table>
+</section>
+<section id="ur-s3a">
+<h3><code class="docutils literal notranslate"><span class="pre">UR.S3A</span></code><a class="headerlink" href="#ur-s3a" title="Link to this heading"></a></h3>
+<p>This tile is used on Spartan 3A.</p>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="2">Column</th></tr><tr><th>0</th><th>1</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td><a href="#bits-xc3s-UR.S3A-MISC:TDOPIN" title="MISC:TDOPIN[0]">MISC:TDOPIN[0]</a></td><td><a href="#bits-xc3s-UR.S3A-MISC:TDOPIN" title="MISC:TDOPIN[1]">MISC:TDOPIN[1]</a></td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td></tr>
+<tr><td>44</td>
+<td><a href="#bits-xc3s-UR.S3A-MISC:TCKPIN" title="MISC:TCKPIN[0]">MISC:TCKPIN[0]</a></td><td><a href="#bits-xc3s-UR.S3A-MISC:TCKPIN" title="MISC:TCKPIN[1]">MISC:TCKPIN[1]</a></td></tr>
+<tr><td>45</td>
+<td><a href="#bits-xc3s-UR.S3A-MISC:MISO2PIN" title="MISC:MISO2PIN[0]">MISC:MISO2PIN[0]</a></td><td><a href="#bits-xc3s-UR.S3A-MISC:MISO2PIN" title="MISC:MISO2PIN[1]">MISC:MISO2PIN[1]</a></td></tr>
+<tr><td>46</td>
+<td><a href="#bits-xc3s-UR.S3A-MISC:CSO2PIN" title="MISC:CSO2PIN[1]">MISC:CSO2PIN[1]</a></td><td><a href="#bits-xc3s-UR.S3A-MISC:CSO2PIN" title="MISC:CSO2PIN[0]">MISC:CSO2PIN[0]</a></td></tr>
+<tr><td>47</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[31]">~BSCAN:USERID[31]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[30]">~BSCAN:USERID[30]</a></td></tr>
+<tr><td>48</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[29]">~BSCAN:USERID[29]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[28]">~BSCAN:USERID[28]</a></td></tr>
+<tr><td>49</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[27]">~BSCAN:USERID[27]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[26]">~BSCAN:USERID[26]</a></td></tr>
+<tr><td>50</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[25]">~BSCAN:USERID[25]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[24]">~BSCAN:USERID[24]</a></td></tr>
+<tr><td>51</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[23]">~BSCAN:USERID[23]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[22]">~BSCAN:USERID[22]</a></td></tr>
+<tr><td>52</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[21]">~BSCAN:USERID[21]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[20]">~BSCAN:USERID[20]</a></td></tr>
+<tr><td>53</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[19]">~BSCAN:USERID[19]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[18]">~BSCAN:USERID[18]</a></td></tr>
+<tr><td>54</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[17]">~BSCAN:USERID[17]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[16]">~BSCAN:USERID[16]</a></td></tr>
+<tr><td>55</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[15]">~BSCAN:USERID[15]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[14]">~BSCAN:USERID[14]</a></td></tr>
+<tr><td>56</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[13]">~BSCAN:USERID[13]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[12]">~BSCAN:USERID[12]</a></td></tr>
+<tr><td>57</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[11]">~BSCAN:USERID[11]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[10]">~BSCAN:USERID[10]</a></td></tr>
+<tr><td>58</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[9]">~BSCAN:USERID[9]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[8]">~BSCAN:USERID[8]</a></td></tr>
+<tr><td>59</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[7]">~BSCAN:USERID[7]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[6]">~BSCAN:USERID[6]</a></td></tr>
+<tr><td>60</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[5]">~BSCAN:USERID[5]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[4]">~BSCAN:USERID[4]</a></td></tr>
+<tr><td>61</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[3]">~BSCAN:USERID[3]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[2]">~BSCAN:USERID[2]</a></td></tr>
+<tr><td>62</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[1]">~BSCAN:USERID[1]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:USERID" title="~BSCAN:USERID[0]">~BSCAN:USERID[0]</a></td></tr>
+<tr><td>63</td>
+<td><a href="#bits-xc3s-UR.S3A-BSCAN:TDO_ENABLE" title="BSCAN:TDO_ENABLE[0]">BSCAN:TDO_ENABLE[0]</a></td><td><a href="#bits-xc3s-UR.S3A-BSCAN:TDO_ENABLE" title="BSCAN:TDO_ENABLE[1]">BSCAN:TDO_ENABLE[1]</a></td></tr>
+</table>
+<div id="bits-xc3s-UR.S3A-MISC:TDOPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TDOPIN</th><th>[0, 1, 7]</th><th>[0, 0, 7]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UR.S3A-MISC:TCKPIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:TCKPIN</th><th>[0, 1, 44]</th><th>[0, 0, 44]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UR.S3A-MISC:MISO2PIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:MISO2PIN</th><th>[0, 1, 45]</th><th>[0, 0, 45]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UR.S3A-BSCAN:TDO_ENABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>BSCAN:TDO_ENABLE</th><th>[0, 1, 63]</th><th>[0, 0, 63]</th></tr>
+<tr><td>Non-inverted</td><td>[1]</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-UR.S3A-MISC:CSO2PIN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>MISC:CSO2PIN</th><th>[0, 0, 46]</th><th>[0, 1, 46]</th></tr>
+<tr><td>PULLUP</td><td>0</td><td>0</td></tr>
+<tr><td>PULLNONE</td><td>0</td><td>1</td></tr>
+<tr><td>PULLDOWN</td><td>1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-UR.S3A-BSCAN:USERID"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>BSCAN:USERID</th><th>[0, 0, 47]</th><th>[0, 1, 47]</th><th>[0, 0, 48]</th><th>[0, 1, 48]</th><th>[0, 0, 49]</th><th>[0, 1, 49]</th><th>[0, 0, 50]</th><th>[0, 1, 50]</th><th>[0, 0, 51]</th><th>[0, 1, 51]</th><th>[0, 0, 52]</th><th>[0, 1, 52]</th><th>[0, 0, 53]</th><th>[0, 1, 53]</th><th>[0, 0, 54]</th><th>[0, 1, 54]</th><th>[0, 0, 55]</th><th>[0, 1, 55]</th><th>[0, 0, 56]</th><th>[0, 1, 56]</th><th>[0, 0, 57]</th><th>[0, 1, 57]</th><th>[0, 0, 58]</th><th>[0, 1, 58]</th><th>[0, 0, 59]</th><th>[0, 1, 59]</th><th>[0, 0, 60]</th><th>[0, 1, 60]</th><th>[0, 0, 61]</th><th>[0, 1, 61]</th><th>[0, 0, 62]</th><th>[0, 1, 62]</th></tr>
+<tr><td>Inverted</td><td>~[31]</td><td>~[30]</td><td>~[29]</td><td>~[28]</td><td>~[27]</td><td>~[26]</td><td>~[25]</td><td>~[24]</td><td>~[23]</td><td>~[22]</td><td>~[21]</td><td>~[20]</td><td>~[19]</td><td>~[18]</td><td>~[17]</td><td>~[16]</td><td>~[15]</td><td>~[14]</td><td>~[13]</td><td>~[12]</td><td>~[11]</td><td>~[10]</td><td>~[9]</td><td>~[8]</td><td>~[7]</td><td>~[6]</td><td>~[5]</td><td>~[4]</td><td>~[3]</td><td>~[2]</td><td>~[1]</td><td>~[0]</td></tr>
+</table>
+</section>
+</section>
+</section>
+
+
+           </div>
+          </div>
+          <footer><div class="rst-footer-buttons" role="navigation" aria-label="Footer">
+        <a href="clock.html" class="btn btn-neutral float-left" title="Clock interconnect" accesskey="p" rel="prev"><span class="fa fa-arrow-circle-left" aria-hidden="true"></span> Previous</a>
+        <a href="../spartan3/index.html" class="btn btn-neutral float-right" title="Xilinx Spartan 3 FPGAs" accesskey="n" rel="next">Next <span class="fa fa-arrow-circle-right" aria-hidden="true"></span></a>
+    </div>
+
+  <hr/>
+
+  <div role="contentinfo">
+    <p>&#169; Copyright 2023, Wanda.</p>
+  </div>
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+  Built with <a href="https://www.sphinx-doc.org/">Sphinx</a> using a
+    <a href="https://github.com/readthedocs/sphinx_rtd_theme">theme</a>
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+      jQuery(function () {
+          SphinxRtdTheme.Navigation.enable(true);
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+  </script> 
+
+</body>
+</html>
\ No newline at end of file
diff --git a/xilinx/virtex2/index.html b/xilinx/virtex2/index.html
index 2d64c539..07e754df 100644
--- a/xilinx/virtex2/index.html
+++ b/xilinx/virtex2/index.html
@@ -56,6 +56,7 @@
 <li class="toctree-l3"><a class="reference internal" href="clb.html">Configurable Logic Block</a></li>
 <li class="toctree-l3"><a class="reference internal" href="bram.html">Block RAM — Virtex 2, Spartan 3</a></li>
 <li class="toctree-l3"><a class="reference internal" href="clock.html">Clock interconnect</a></li>
+<li class="toctree-l3"><a class="reference internal" href="corner.html">Corners — Virtex 2, Spartan 3</a></li>
 </ul>
 </li>
 <li class="toctree-l2"><a class="reference internal" href="../spartan3/index.html">Xilinx Spartan 3 FPGAs</a></li>
@@ -153,6 +154,13 @@ <h1>Xilinx Virtex 2 FPGAs<a class="headerlink" href="#xilinx-virtex-2-fpgas" tit
 <li class="toctree-l2"><a class="reference internal" href="clock.html#dcm-output-bus">DCM output bus</a></li>
 </ul>
 </li>
+<li class="toctree-l1"><a class="reference internal" href="corner.html">Corners — Virtex 2, Spartan 3</a><ul>
+<li class="toctree-l2"><a class="reference internal" href="corner.html#lower-left">Lower left</a></li>
+<li class="toctree-l2"><a class="reference internal" href="corner.html#upper-left">Upper left</a></li>
+<li class="toctree-l2"><a class="reference internal" href="corner.html#lower-right">Lower right</a></li>
+<li class="toctree-l2"><a class="reference internal" href="corner.html#upper-right">Upper right</a></li>
+</ul>
+</li>
 </ul>
 </div>
 </section>
diff --git a/xilinx/virtex2/interconnect.html b/xilinx/virtex2/interconnect.html
index 2608882c..3e2979cb 100644
--- a/xilinx/virtex2/interconnect.html
+++ b/xilinx/virtex2/interconnect.html
@@ -68,6 +68,7 @@
 <li class="toctree-l3"><a class="reference internal" href="clb.html">Configurable Logic Block</a></li>
 <li class="toctree-l3"><a class="reference internal" href="bram.html">Block RAM — Virtex 2, Spartan 3</a></li>
 <li class="toctree-l3"><a class="reference internal" href="clock.html">Clock interconnect</a></li>
+<li class="toctree-l3"><a class="reference internal" href="corner.html">Corners — Virtex 2, Spartan 3</a></li>
 </ul>
 </li>
 <li class="toctree-l2"><a class="reference internal" href="../spartan3/index.html">Xilinx Spartan 3 FPGAs</a></li>
@@ -113,7 +114,7 @@
 <li><p><code class="docutils literal notranslate"><span class="pre">INT.BRAM</span></code>, the interconnect tile associated with <a class="reference internal" href="bram.html#virtex2-bram"><span class="std std-ref">block RAMs</span></a></p></li>
 <li><p><code class="docutils literal notranslate"><span class="pre">INT.{IOI|IOI.CLK_B|IOI.CLK_T}</span></code>, the interconnect tile associated with <span class="xref std std-ref">I/O tiles</span></p></li>
 <li><p><code class="docutils literal notranslate"><span class="pre">INT.DCM.{V2|V2P}</span></code>, the interconnect tiles associated with <span class="xref std std-ref">digital clock managers</span></p></li>
-<li><p><code class="docutils literal notranslate"><span class="pre">INT.CNR</span></code>, the interconnect tile associated with <span class="xref std std-ref">corner tiles</span></p></li>
+<li><p><code class="docutils literal notranslate"><span class="pre">INT.CNR</span></code>, the interconnect tile associated with <a class="reference internal" href="corner.html#virtex2-corner"><span class="std std-ref">corner tiles</span></a></p></li>
 <li><p><code class="docutils literal notranslate"><span class="pre">INT.PPC</span></code>, the interconnect tile associated with <span class="xref std std-ref">PowerPC cores</span> and multi-gigabit transceivers</p></li>
 <li><p><code class="docutils literal notranslate"><span class="pre">INT.GT.CLKPAD</span></code>, the interconnect tile associated with multi-gigabit transceivers in the I/O row</p></li>
 </ul>
diff --git a/xilinx/virtex2/intro.html b/xilinx/virtex2/intro.html
index d04d7dd0..5c597931 100644
--- a/xilinx/virtex2/intro.html
+++ b/xilinx/virtex2/intro.html
@@ -59,6 +59,7 @@
 <li class="toctree-l3"><a class="reference internal" href="clb.html">Configurable Logic Block</a></li>
 <li class="toctree-l3"><a class="reference internal" href="bram.html">Block RAM — Virtex 2, Spartan 3</a></li>
 <li class="toctree-l3"><a class="reference internal" href="clock.html">Clock interconnect</a></li>
+<li class="toctree-l3"><a class="reference internal" href="corner.html">Corners — Virtex 2, Spartan 3</a></li>
 </ul>
 </li>
 <li class="toctree-l2"><a class="reference internal" href="../spartan3/index.html">Xilinx Spartan 3 FPGAs</a></li>
@@ -118,7 +119,7 @@
 </li>
 <li><p>new <span class="xref std std-ref">input-output tiles</span>, with DDR register and DCI (digitally controlled impedance) support</p></li>
 <li><p>new <span class="xref std std-ref">digital clock managers</span>, a new version of the <span class="xref std std-ref">Virtex DLLs</span> with added frequency synthesis capability</p></li>
-<li><p><span class="xref std std-ref">corner tiles</span>, with various global bits of logic:</p>
+<li><p><a class="reference internal" href="corner.html#virtex2-corner"><span class="std std-ref">corner tiles</span></a>, with various global bits of logic:</p>
 <ul>
 <li><p><code class="docutils literal notranslate"><span class="pre">BSCAN</span></code> primitive, allowing access to FPGA fabric via dedicated JTAG instructions</p></li>
 <li><p><code class="docutils literal notranslate"><span class="pre">JTAGPPC</span></code> primitive (Virtex 2 Pro), for connecting the PowerPC cores to JTAG</p></li>
diff --git a/xilinx/virtex2/structure.html b/xilinx/virtex2/structure.html
index 855ceaa3..591f7b3f 100644
--- a/xilinx/virtex2/structure.html
+++ b/xilinx/virtex2/structure.html
@@ -64,6 +64,7 @@
 <li class="toctree-l3"><a class="reference internal" href="clb.html">Configurable Logic Block</a></li>
 <li class="toctree-l3"><a class="reference internal" href="bram.html">Block RAM — Virtex 2, Spartan 3</a></li>
 <li class="toctree-l3"><a class="reference internal" href="clock.html">Clock interconnect</a></li>
+<li class="toctree-l3"><a class="reference internal" href="corner.html">Corners — Virtex 2, Spartan 3</a></li>
 </ul>
 </li>
 <li class="toctree-l2"><a class="reference internal" href="../spartan3/index.html">Xilinx Spartan 3 FPGAs</a></li>