From 51fa6588f9c4555deac7ef6efee1241cfb014bd1 Mon Sep 17 00:00:00 2001
From: wanda-phi <145241585+wanda-phi@users.noreply.github.com>
Date: Mon, 3 Jun 2024 05:49:09 +0000
Subject: [PATCH] =?UTF-8?q?Deploying=20to=20gh-pages=20from=20=20@=2003946?=
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---
 _sources/xilinx/virtex2/index.rst.txt |    1 +
 _sources/xilinx/virtex2/io.rst.txt    |  109 +
 objects.inv                           |  Bin 1608 -> 1636 bytes
 searchindex.js                        |    2 +-
 xilinx/index.html                     |    1 +
 xilinx/virtex2/bram.html              |    1 +
 xilinx/virtex2/clb.html               |    1 +
 xilinx/virtex2/clock.html             |    5 +-
 xilinx/virtex2/corner.html            |    5 +-
 xilinx/virtex2/index.html             |    6 +
 xilinx/virtex2/interconnect.html      |    3 +-
 xilinx/virtex2/intro.html             |    3 +-
 xilinx/virtex2/io.html                | 6558 +++++++++++++++++++++++++
 xilinx/virtex2/structure.html         |    1 +
 14 files changed, 6689 insertions(+), 7 deletions(-)
 create mode 100644 _sources/xilinx/virtex2/io.rst.txt
 create mode 100644 xilinx/virtex2/io.html

diff --git a/_sources/xilinx/virtex2/index.rst.txt b/_sources/xilinx/virtex2/index.rst.txt
index 616032f0..0d1c4ff6 100644
--- a/_sources/xilinx/virtex2/index.rst.txt
+++ b/_sources/xilinx/virtex2/index.rst.txt
@@ -13,4 +13,5 @@ Xilinx Virtex 2 FPGAs
    clb
    bram
    clock
+   io
    corner
diff --git a/_sources/xilinx/virtex2/io.rst.txt b/_sources/xilinx/virtex2/io.rst.txt
new file mode 100644
index 00000000..e42b8b87
--- /dev/null
+++ b/_sources/xilinx/virtex2/io.rst.txt
@@ -0,0 +1,109 @@
+.. _virtex2-io:
+
+Input / Output — Virtex 2, Spartan 3
+####################################
+
+.. todo:: document
+
+
+I/O interface
+=============
+
+.. todo:: document
+
+
+``IOI`` — Virtex 2
+------------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc2v-IOI.html
+
+
+``IOI.CLK_B`` — Virtex 2
+------------------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc2v-IOI.CLK_B.html
+
+
+``IOI.CLK_T`` — Virtex 2
+------------------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc2v-IOI.CLK_T.html
+
+
+``IOI.S3``
+----------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-IOI.S3.html
+
+
+``IOI.S3E``
+-----------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-IOI.S3E.html
+
+
+``IOI.S3A.L``
+-------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-IOI.S3A.L.html
+
+
+``IOI.S3A.R``
+-------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-IOI.S3A.R.html
+
+
+``IOI.S3A.B``
+-------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-IOI.S3A.B.html
+
+
+``IOI.S3A.T``
+-------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-IOI.S3A.T.html
+
+
+``IOI.S3ADSP.L``
+----------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-IOI.S3ADSP.L.html
+
+
+``IOI.S3ADSP.R``
+----------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-IOI.S3ADSP.R.html
+
+
+``IOI.S3ADSP.B``
+----------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-IOI.S3ADSP.B.html
+
+
+``IOI.S3ADSP.T``
+----------------
+
+.. raw:: html
+   :file: ../gen-xilinx-tile-xc3s-IOI.S3ADSP.T.html
+
+
+I/O buffers
+===========
+
+.. todo:: document
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diff --git a/searchindex.js b/searchindex.js
index 8f23171e..915409ae 100644
--- a/searchindex.js
+++ b/searchindex.js
@@ -1 +1 @@
-Search.setIndex({"alltitles": {"AIM and FB inputs": [[14, "aim-and-fb-inputs"]], "BRAM (Virtex 2)": [[51, "bram-virtex-2"]], "BRAM.S3": [[51, "bram-s3"]], "BRAM.S3A": [[51, "bram-s3a"]], "BRAM.S3ADSP": [[51, "bram-s3adsp"]], "BRAM.S3E": [[51, "bram-s3e"]], "Backbone": [[42, "backbone"], [56, "backbone"]], "Bank configuration": [[14, "bank-configuration"]], "Bitsteam \u2014 interface tiles": [[47, "bitsteam-interface-tiles"]], "Bitstream": [[38, "bitstream"], [40, "bitstream"], [49, "bitstream"], [51, "bitstream"], [52, "bitstream"], [59, "bitstream"], [60, "bitstream"], [62, "bitstream"], [64, "bitstream"]], "Bitstream geometry": [[44, "bitstream-geometry"], [58, "bitstream-geometry"]], "Bitstream structure": [[1, "bitstream-structure"], [69, "bitstream-structure"]], "Bitstream structure \u2014 XC9500": [[15, "bitstream-structure-xc9500"]], "Bitstream structure \u2014 XC9500XL/XV": [[16, "bitstream-structure-xc9500xl-xv"]], "Bitstream \u2014 IOI tile": [[47, "bitstream-ioi-tile"]], "Bitstream \u2014 LLH tiles": [[42, "bitstream-llh-tiles"]], "Bitstream \u2014 LLV tiles": [[42, "bitstream-llv-tiles"]], "Bitstream \u2014 PowerPC hole tiles": [[56, "bitstream-powerpc-hole-tiles"]], "Bitstream \u2014 Series 7": [[63, "bitstream-series-7"], [66, "bitstream-series-7"], [67, "bitstream-series-7"]], "Bitstream \u2014 Spartan 6": [[63, "bitstream-spartan-6"]], "Bitstream \u2014 Virtex 5": [[63, "bitstream-virtex-5"], [66, "bitstream-virtex-5"]], "Bitstream \u2014 Virtex 6": [[63, "bitstream-virtex-6"], [66, "bitstream-virtex-6"], [67, "bitstream-virtex-6"]], "Bitstream \u2014 bottom tile": [[45, "bitstream-bottom-tile"]], "Bitstream \u2014 bottom tiles": [[39, "bitstream-bottom-tiles"], [53, "bitstream-bottom-tiles"]], "Bitstream \u2014 interconnect tiles": [[42, "bitstream-interconnect-tiles"], [56, "bitstream-interconnect-tiles"]], "Bitstream \u2014 interface tile": [[62, "bitstream-interface-tile"]], "Bitstream \u2014 interface tiles": [[42, "bitstream-interface-tiles"], [56, "bitstream-interface-tiles"]], "Bitstream \u2014 left side": [[48, "bitstream-left-side"]], "Bitstream \u2014 left tiles": [[39, "bitstream-left-tiles"]], "Bitstream \u2014 middle": [[48, "bitstream-middle"]], "Bitstream \u2014 normal tile": [[47, "bitstream-normal-tile"]], "Bitstream \u2014 right side": [[48, "bitstream-right-side"]], "Bitstream \u2014 right tiles": [[39, "bitstream-right-tiles"]], "Bitstream \u2014 terminator tiles": [[56, "bitstream-terminator-tiles"]], "Bitstream \u2014 top tile": [[45, "bitstream-top-tile"]], "Bitstream \u2014 top tiles": [[39, "bitstream-top-tiles"], [53, "bitstream-top-tiles"]], "Blank check \u2014 XC9500XL/XV": [[35, "blank-check-xc9500xl-xv"]], "Block RAM": [[59, "block-ram"]], "Block RAM \u2014 Virtex": [[48, "block-ram-virtex"]], "Block RAM \u2014 Virtex 2, Spartan 3": [[51, "block-ram-virtex-2-spartan-3"]], "Bond": [[17, "bond"], [70, "bond"]], "Boundary scan register": [[13, "boundary-scan-register"], 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"devices"], [79, "devices"]], "Dual-port 16\u00d7X RAM": [[38, "dual-port-16x-ram"], [52, "dual-port-16x-ram"]], "Dual-port 32\u00d7X RAM": [[52, "dual-port-32x-ram"]], "Dual-port 64\u00d71 RAM": [[52, "dual-port-641-ram"]], "ECC mode": [[59, "ecc-mode"]], "Entering and exiting ISP mode \u2014 XC9500": [[35, "entering-and-exiting-isp-mode-xc9500"]], "Entering and exiting ISP mode \u2014 XC9500XL/XV": [[35, "entering-and-exiting-isp-mode-xc9500xl-xv"]], "Erasing fuses \u2014 XC9500": [[35, "erasing-fuses-xc9500"]], "Erasing fuses \u2014 XC9500XL/XV": [[35, "erasing-fuses-xc9500xl-xv"]], "FB columns and rows": [[81, "fb-columns-and-rows"]], "FB global fuses": [[36, "fb-global-fuses"]], "FCLK networks": [[81, "fclk-networks"]], "FIFO mode": [[59, "fifo-mode"]], "Flip-flop": [[36, "flip-flop"]], "Frequency": [[35, "frequency"]], "Fuses \u2014 FB inputs": [[15, "fuses-fb-inputs"], [16, "fuses-fb-inputs"]], "Fuses \u2014 FBs": [[69, "fuses-fbs"]], "Fuses \u2014 IMUX bits": [[69, "fuses-imux-bits"]], "Fuses \u2014 UIM wire-AND": [[15, "fuses-uim-wire-and"]], "Fuses \u2014 global bits": [[69, "fuses-global-bits"]], "Fuses \u2014 input buffer enable": [[15, "fuses-input-buffer-enable"]], "Fuses \u2014 macrocells": [[15, "fuses-macrocells"], [16, "fuses-macrocells"], [69, "fuses-macrocells"]], "Fuses \u2014 per-FB bits and globals": [[15, "fuses-per-fb-bits-and-globals"], [16, "fuses-per-fb-bits-and-globals"]], "Fuses \u2014 product and sum terms": [[69, "fuses-product-and-sum-terms"]], "Fuses \u2014 product terms": [[15, "fuses-product-terms"], [16, "fuses-product-terms"]], "GCLKC": [[53, "gclkc"]], "GCLKC.B": [[53, "gclkc-b"]], "GCLKC.T": [[53, "gclkc-t"]], "GCLKH": [[39, "gclkh"], [53, "gclkh"]], "GCLKH.N": [[39, "gclkh-n"]], "GCLKH.S": [[39, "gclkh-s"]], "GCLKH.UNI": [[39, "gclkh-uni"]], "GCLKH.UNI.N": [[39, "gclkh-uni-n"]], "GCLKH.UNI.S": [[39, "gclkh-uni-s"]], "GCLKVM.S3": [[39, "gclkvm-s3"]], "GCLKVM.S3E": [[39, "gclkvm-s3e"]], "General interconnect": [[42, "general-interconnect"], [47, "general-interconnect"], [56, "general-interconnect"]], "General structure": [[44, "general-structure"], [58, "general-structure"]], "Global bits": [[2, "global-bits"], [3, "global-bits"], [4, "global-bits"], [5, "global-bits"], [6, "global-bits"], [7, "global-bits"], [8, "global-bits"], [9, "global-bits"], [71, "global-bits"], [72, "global-bits"], [73, "global-bits"], [74, "global-bits"], [75, "global-bits"], [76, "global-bits"]], "Global networks": [[14, "global-networks"]], "Global networks \u2014 XC9500": [[36, "global-networks-xc9500"]], "Global networks \u2014 XC9500XL/XV": [[36, "global-networks-xc9500xl-xv"]], "Horizontal clock spine": [[44, "horizontal-clock-spine"]], "I/O pins": [[2, "i-o-pins"], [3, "i-o-pins"], [4, "i-o-pins"], [5, "i-o-pins"], [6, "i-o-pins"], [7, "i-o-pins"], [8, "i-o-pins"], [9, "i-o-pins"], [18, "i-o-pins"], [19, "i-o-pins"], [20, "i-o-pins"], [21, "i-o-pins"], [22, "i-o-pins"], [23, "i-o-pins"], [24, "i-o-pins"], [25, "i-o-pins"], [26, "i-o-pins"], [27, "i-o-pins"], [28, "i-o-pins"], [29, "i-o-pins"], [30, "i-o-pins"], [31, "i-o-pins"], [71, "i-o-pins"], [72, "i-o-pins"], [73, "i-o-pins"], [74, "i-o-pins"], [75, "i-o-pins"], [76, "i-o-pins"]], "IDCODE": [[35, "idcode"], [80, "idcode"]], "IMUX bits": [[2, "imux-bits"], [3, "imux-bits"], [4, "imux-bits"], [5, "imux-bits"], [6, "imux-bits"], [7, "imux-bits"], [8, "imux-bits"], [9, "imux-bits"], [18, "imux-bits"], [19, "imux-bits"], [20, "imux-bits"], [21, "imux-bits"], [22, "imux-bits"], [23, "imux-bits"], [24, "imux-bits"], [25, "imux-bits"], [26, "imux-bits"], [27, "imux-bits"], [28, "imux-bits"], [29, "imux-bits"], [30, "imux-bits"], [31, "imux-bits"], [71, "imux-bits"], [72, "imux-bits"], [73, "imux-bits"], [74, "imux-bits"], [75, "imux-bits"], [76, "imux-bits"]], "INT.BRAM": [[56, "int-bram"]], "INT.BRAM.S3": [[42, "int-bram-s3"]], "INT.BRAM.S3A.03": [[42, "int-bram-s3a-03"]], "INT.BRAM.S3A.12": [[42, "int-bram-s3a-12"]], "INT.BRAM.S3ADSP": [[42, "int-bram-s3adsp"]], "INT.BRAM.S3E": [[42, "int-bram-s3e"]], "INT.CLB": [[42, "int-clb"], [56, "int-clb"]], "INT.CNR": [[56, "int-cnr"]], "INT.DCM": [[42, "int-dcm"]], "INT.DCM.S3E.DUMMY": [[42, "int-dcm-s3e-dummy"]], "INT.DCM.V2": [[56, "int-dcm-v2"]], "INT.DCM.V2P": [[56, "int-dcm-v2p"]], "INT.GT.CLKPAD": [[56, "int-gt-clkpad"]], "INT.IOI": [[56, "int-ioi"]], "INT.IOI.CLK_B": [[56, "int-ioi-clk-b"]], "INT.IOI.CLK_T": [[56, "int-ioi-clk-t"]], "INT.IOI.S3": [[42, "int-ioi-s3"]], "INT.IOI.S3A.LR": [[42, "int-ioi-s3a-lr"]], "INT.IOI.S3A.TB": [[42, "int-ioi-s3a-tb"]], "INT.IOI.S3E": [[42, "int-ioi-s3e"]], "INT.PPC": [[56, "int-ppc"]], "INTF": [[47, "intf"], [66, "intf"], [66, "id1"], [66, "id3"]], "INTF.BRAM": [[66, "intf-bram"]], "INTF.CMT": [[47, "intf-cmt"]], "INTF.CMT.IOI": [[47, "intf-cmt-ioi"]], "INTF.DELAY": [[66, "intf-delay"], [66, "id2"], [66, "id4"]], "INTF.DSP": [[42, "intf-dsp"]], "INTF.GT.B0": [[56, "intf-gt-b0"]], "INTF.GT.B123": [[56, "intf-gt-b123"]], "INTF.GT.BCLKPAD": [[56, "intf-gt-bclkpad"]], "INTF.GT.T0": [[56, "intf-gt-t0"]], "INTF.GT.T123": [[56, "intf-gt-t123"]], "INTF.GT.TCLKPAD": [[56, "intf-gt-tclkpad"]], "INTF.IOI": [[47, "intf-ioi"]], "INTF.PPC": [[56, "intf-ppc"]], "IO banks and IO buffers": [[44, "io-banks-and-io-buffers"], [58, "io-banks-and-io-buffers"]], "IR": [[13, "ir"], [35, "ir"], [80, "ir"]], "ISP DR registers \u2014 XC9500": [[35, "isp-dr-registers-xc9500"]], "ISP DR registers \u2014 XC9500XL/XV": [[35, "isp-dr-registers-xc9500xl-xv"]], "ISP instructions": [[13, "isp-instructions"], [80, "isp-instructions"]], "ISP instructions \u2014 XC9500": [[35, "isp-instructions-xc9500"]], "ISP instructions \u2014 XC9500XL/XV": [[35, "isp-instructions-xc9500xl-xv"]], "Input multiplexers": [[42, "input-multiplexers"], [56, "input-multiplexers"]], "Input/output buffer": [[14, "input-output-buffer"], [36, "input-output-buffer"], [81, "input-output-buffer"]], "Interconnect": [[62, "interconnect"]], "Interconnect \u2014 Virtex 5, Virtex 6, Series 7": [[66, "interconnect-virtex-5-virtex-6-series-7"]], "Introduction": [[12, "introduction"], [34, "introduction"], [43, "introduction"], [57, "introduction"], [79, "introduction"]], "JED bits": [[70, "jed-bits"]], "JED format mapping": [[15, "jed-format-mapping"], [16, "jed-format-mapping"]], "JED mapping": [[2, "jed-mapping"], [3, "jed-mapping"], [4, "jed-mapping"], [4, "id1"], [5, "jed-mapping"], [5, "id1"], [6, "jed-mapping"], [7, "jed-mapping"], [8, "jed-mapping"], [8, "id1"], [9, "jed-mapping"], [9, "id1"], [69, "jed-mapping"], [71, "jed-mapping"], [72, "jed-mapping"], [73, "jed-mapping"], [74, "jed-mapping"], [75, "jed-mapping"], [76, "jed-mapping"]], "JED mapping \u2014 MCs with IOBs": [[2, "jed-mapping-mcs-with-iobs"], [3, "jed-mapping-mcs-with-iobs"], [6, "jed-mapping-mcs-with-iobs"], [7, "jed-mapping-mcs-with-iobs"]], "JED mapping \u2014 MCs without IOBs": [[2, "jed-mapping-mcs-without-iobs"], [3, "jed-mapping-mcs-without-iobs"], [6, "jed-mapping-mcs-without-iobs"], [7, "jed-mapping-mcs-without-iobs"]], "JED mapping \u2014 macrocells with IOB": [[69, "jed-mapping-macrocells-with-iob"]], "JED mapping \u2014 macrocells without IOB": [[69, "jed-mapping-macrocells-without-iob"]], "JED structure": [[69, "jed-structure"]], "JTAG interface": [[13, "jtag-interface"], [35, "jtag-interface"], [80, "jtag-interface"]], "LL \u2014 Virtex 2": [[54, "ll-virtex-2"]], "LL.S3": [[54, "ll-s3"]], "LL.S3A": [[54, "ll-s3a"]], "LL.S3E": [[54, "ll-s3e"]], "LLH": [[42, "llh"]], "LLH.CLKB.S3A": [[42, "llh-clkb-s3a"]], "LLH.CLKT.S3A": [[42, "llh-clkt-s3a"]], "LLV.S3A": [[42, "llv-s3a"]], "LLV.S3E": [[42, "llv-s3e"]], "LR \u2014 Virtex 2": [[54, "lr-virtex-2"]], "LR.S3": [[54, "lr-s3"]], "LR.S3A": [[54, "lr-s3a"]], "LR.S3E": [[54, "lr-s3e"]], "LUT RAM": [[38, "lut-ram"], [52, "lut-ram"]], "LUTs": [[38, "luts"], [52, "luts"]], "Local control terms": [[81, "local-control-terms"]], "Long line splitters": [[42, "long-line-splitters"]], "Lower left": [[54, "lower-left"]], "Lower right": [[54, "lower-right"]], "MC bits": [[2, "mc-bits"], [3, "mc-bits"], [4, "mc-bits"], [5, "mc-bits"], [6, "mc-bits"], [7, "mc-bits"], [8, "mc-bits"], [9, "mc-bits"]], "Macrocell and IOB outputs": [[14, "macrocell-and-iob-outputs"], [81, "macrocell-and-iob-outputs"]], "Macrocell output \u2014 XC9500": [[36, "macrocell-output-xc9500"]], "Macrocell output \u2014 XC9500XL/XV": [[36, "macrocell-output-xc9500xl-xv"]], "Misc configuration": [[14, "misc-configuration"], [36, "misc-configuration"], [81, "misc-configuration"]], "Output multiplexers": [[52, "output-multiplexers"]], "Output multiplexers \u2014 Spartan 3": [[38, "output-multiplexers-spartan-3"]], "Output multiplexers \u2014 Virtex 4": [[38, "output-multiplexers-virtex-4"]], "Overview": [[14, "overview"], [36, "overview"], [81, "overview"]], "PCI logic": [[58, "pci-logic"]], "PPC.E": [[56, "ppc-e"]], "PPC.N": [[56, "ppc-n"]], "PPC.S": [[56, "ppc-s"]], "PPC.W": [[56, "ppc-w"]], "PT import/export": [[36, "pt-import-export"]], "Packages": [[12, "packages"], [34, "packages"], [79, "packages"]], "Part": [[17, "part"], [70, "part"]], "PowerPC holes": [[56, "powerpc-holes"], [58, "powerpc-holes"]], "Primary vertical clock spine": [[44, "primary-vertical-clock-spine"]], "Primitive outputs": [[42, "primitive-outputs"], [56, "primitive-outputs"]], "Product terms": [[14, "product-terms"], [36, "product-terms"], [81, "product-terms"]], "Programming fuses \u2014 XC9500": [[35, "programming-fuses-xc9500"]], "Programming fuses \u2014 XC9500XL/XV": [[35, "programming-fuses-xc9500xl-xv"]], "Programming sequence": [[13, "programming-sequence"], [35, "programming-sequence"], [80, "programming-sequence"]], "Project Combine": [[0, "project-combine"]], "Reading fuses \u2014 XC9500": [[35, "reading-fuses-xc9500"]], "Reading fuses \u2014 XC9500XL/XV": [[35, "reading-fuses-xc9500xl-xv"]], "Register": [[14, "register"], [81, "register"]], "Registers": [[38, "registers"], [52, "registers"]], "Secondary vertical clock spines": [[44, "secondary-vertical-clock-spines"]], "Shift registers": [[38, "shift-registers"], [52, "shift-registers"]], "Single-port 128\u00d71 RAM": [[52, "single-port-1281-ram"]], "Single-port 16\u00d7X RAM": [[38, "single-port-16x-ram"], [52, "single-port-16x-ram"]], "Single-port 32\u00d7X RAM": [[38, "single-port-32x-ram"], [52, "single-port-32x-ram"]], "Single-port 64\u00d71 RAM": [[38, "single-port-641-ram"]], "Single-port 64\u00d7X RAM": [[52, "single-port-64x-ram"]], "Spartan 3": [[38, "spartan-3"]], "Spartan 3A DCMs": [[44, "spartan-3a-dcms"]], "Spartan 3A DSP": [[40, "spartan-3a-dsp"]], "Spartan 3A and 3A DSP BRAM columns": [[44, "spartan-3a-and-3a-dsp-bram-columns"]], "Spartan 3E BRAM columns": [[44, "spartan-3e-bram-columns"]], "Spartan 3E DCMs": [[44, "spartan-3e-dcms"]], "Spartan 6": [[40, "spartan-6"]], "Speed": [[17, "speed"], [70, "speed"]], "Speed data": [[2, "speed-data"], [3, "speed-data"], [4, "speed-data"], [5, "speed-data"], [6, "speed-data"], [7, "speed-data"], [8, "speed-data"], [9, "speed-data"], [18, "speed-data"], [19, "speed-data"], [20, "speed-data"], [21, "speed-data"], [22, "speed-data"], [23, "speed-data"], [24, "speed-data"], [25, "speed-data"], [26, "speed-data"], [27, "speed-data"], [28, "speed-data"], [29, "speed-data"], [30, "speed-data"], [31, "speed-data"], [71, "speed-data"], [72, "speed-data"], [73, "speed-data"], [74, "speed-data"], [75, "speed-data"], [76, "speed-data"]], "Sum of products": [[52, "sum-of-products"]], "Sum term, LUT2": [[81, "sum-term-lut2"]], "Sum term, XOR gate": [[14, "sum-term-xor-gate"], [36, "sum-term-xor-gate"]], "TERM.E": [[56, "term-e"]], "TERM.N": [[56, "term-n"]], "TERM.S": [[56, "term-s"]], "TERM.W": [[56, "term-w"]], "Terminators": [[42, "terminators"], [56, "terminators"]], "The BRAM bel": [[51, "the-bram-bel"]], "The CLKC clock center tile": [[39, "the-clkc-clock-center-tile"]], "The CLKC_50A clock center tile": [[39, "the-clkc-50a-clock-center-tile"]], "The GCLKC clock spine distribution tiles": [[53, "the-gclkc-clock-spine-distribution-tiles"]], "The GCLKH clock row distribution tiles": [[39, "the-gclkh-clock-row-distribution-tiles"]], "The GCLKVC clock spine distribution tiles": [[39, "the-gclkvc-clock-spine-distribution-tiles"]], "The GCLKVM secondary clock center tiles": [[39, "the-gclkvm-secondary-clock-center-tiles"]], "The MULT bel \u2014 Spartan 3E and Spartan 3A": [[51, "the-mult-bel-spartan-3e-and-spartan-3a"]], "The MULT bel \u2014 Virtex 2 and Spartan 3": [[51, "the-mult-bel-virtex-2-and-spartan-3"]], "The clock row distribution tiles": [[53, "the-clock-row-distribution-tiles"]], "Tile": [[17, "tile"], [70, "tile"]], "Todo": [[1, "id1"], [12, "id1"], [13, "id1"], [13, "id2"], [13, "id3"], [13, "id4"], [14, "id1"], [14, "id2"], [14, "id3"], [14, "id4"], [14, "id5"], [14, "id6"], [14, "id7"], [14, "id8"], [14, "id9"], [14, "id10"], [35, "id1"], [35, "id2"], [36, "id1"], [36, "id2"], [38, "id1"], [39, "id1"], [39, "id2"], [39, "id3"], [39, "id4"], [39, "id5"], [39, "id6"], [39, "id7"], [39, "id8"], [39, "id9"], [39, "id10"], [40, "id1"], [41, "id1"], [43, "id1"], [44, "id1"], [46, "id1"], [50, "id1"], [51, "id1"], [51, "id2"], [51, "id3"], [51, "id4"], [52, "id1"], [52, "id2"], [52, "id3"], [53, "id1"], [53, "id2"], [53, "id3"], [53, "id4"], [53, "id5"], [54, "id1"], [54, "id2"], [54, "id3"], [54, "id4"], [54, "id5"], [55, "id1"], [56, "id1"], [57, "id1"], [58, "id1"], [59, "id1"], [59, "id2"], [59, "id3"], [61, "id1"], [65, "id1"], [68, "id1"], [80, "id1"], [80, "id2"], [80, "id3"], [81, "id1"], [81, "id2"]], "Top level": [[17, "top-level"], [70, "top-level"]], "Tristate buses and TBUFs": [[52, "tristate-buses-and-tbufs"]], "UIM IBUF bits": [[23, "uim-ibuf-bits"]], "UIM and FB inputs \u2014 XC9500": [[36, "uim-and-fb-inputs-xc9500"]], "UIM and FB inputs \u2014 XC9500XL/XV": [[36, "uim-and-fb-inputs-xc9500xl-xv"]], "UL \u2014 Virtex 2": [[54, "ul-virtex-2"]], "UL.S3": [[54, "ul-s3"]], "UL.S3A": [[54, "ul-s3a"]], "UL.S3E": [[54, "ul-s3e"]], "UR.S3": [[54, "ur-s3"]], "UR.S3A": [[54, "ur-s3a"]], "UR.S3E": [[54, "ur-s3e"]], "UR.V2": [[54, "ur-v2"]], "UR.V2P": [[54, "ur-v2p"]], "Universal control terms": [[81, "universal-control-terms"]], "Upper left": [[54, "upper-left"]], "Upper right": [[54, "upper-right"]], "Virtex 4": [[38, "virtex-4"]], "Wide multiplexers": [[38, "wide-multiplexers"], [52, "wide-multiplexers"]], "Write protection \u2014 XC9500": [[35, "write-protection-xc9500"]], "Write protection \u2014 XC9500XL/XV": [[35, "write-protection-xc9500xl-xv"]], "XC2C128, XA2C128": [[2, "xc2c128-xa2c128"]], "XC2C256, XA2C256": [[3, "xc2c256-xa2c256"]], "XC2C32": [[4, "xc2c32"]], "XC2C32A, XA2C32A": [[5, "xc2c32a-xa2c32a"]], "XC2C384, XA2C384": [[6, "xc2c384-xa2c384"]], "XC2C512": [[7, "xc2c512"]], "XC2C64": [[8, "xc2c64"]], "XC2C64A, XA2C64A": [[9, "xc2c64a-xa2c64a"]], "XC9500XL/XV bus keeper": [[36, "xc9500xl-xv-bus-keeper"]], "XC95108": [[18, "xc95108"]], "XC95144": [[19, "xc95144"]], "XC95144XL, XA95144XL": [[20, "xc95144xl-xa95144xl"]], "XC95144XV": [[21, "xc95144xv"]], "XC95216": [[22, "xc95216"]], "XC95288": [[23, "xc95288"]], "XC95288XL": [[24, "xc95288xl"]], "XC95288XV": [[25, "xc95288xv"]], "XC9536": [[26, "xc9536"]], "XC9536XL, XA9536XL": [[27, "xc9536xl-xa9536xl"]], "XC9536XV": [[28, "xc9536xv"]], "XC9572": [[29, "xc9572"]], "XC9572XL, XA9572XL": [[30, "xc9572xl-xa9572xl"]], "XC9572XV": [[31, "xc9572xv"]], "XCR3032XL": [[71, "xcr3032xl"]], "XCR3064XL": [[72, "xcr3064xl"]], "XCR3128XL": [[73, "xcr3128xl"]], "XCR3256XL": [[74, "xcr3256xl"]], "XCR3384XL": [[75, "xcr3384xl"]], "XCR3512XL": [[76, "xcr3512xl"]], "Xilinx Coolrunner II CPLDs": [[11, "xilinx-coolrunner-ii-cplds"]], "Xilinx FPGAs": [[37, "xilinx-fpgas"]], "Xilinx Spartan 3 FPGAs": [[41, "xilinx-spartan-3-fpgas"]], "Xilinx Spartan 6 FPGAs": [[46, "xilinx-spartan-6-fpgas"]], "Xilinx Virtex 2 FPGAs": [[55, "xilinx-virtex-2-fpgas"]], "Xilinx Virtex 4 FPGAs": [[61, "xilinx-virtex-4-fpgas"]], "Xilinx Virtex 5 FPGAs": [[65, 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63, "a5ffsrslice1": 63, "a5mux": 51, "a5q0": 63, "a5q0100": 63, "a6": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "a6lut": 63, "a6mux": 51, "a7": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "a7mux": 51, "a8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 72, 73, 74, 75, 76], "a8mux": 51, "a9": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 72, 73, 74, 75, 76], "a9mux": 51, "a_input": [64, 67], "a_q": 51, "aa1": [6, 7, 22, 23, 75, 76], "aa10": [6, 7, 75, 76], "aa11": [6, 7, 75, 76], "aa12": [6, 7, 75, 76], "aa13": [6, 7, 75, 76], "aa14": [6, 7, 75, 76], "aa15": [6, 7, 75, 76], "aa16": [6, 7, 75, 76], "aa17": [6, 7, 75, 76], "aa18": [6, 7, 75, 76], "aa19": [6, 7, 75, 76], "aa2": [6, 7, 22, 23, 75, 76], "aa20": [6, 7, 75, 76], "aa21": [6, 7, 75, 76], "aa22": [6, 7, 75, 76], "aa23": [22, 23], "aa24": [22, 23], "aa25": [22, 23], "aa26": [22, 23], "aa3": [6, 7, 22, 23, 75, 76], "aa4": [6, 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"almost": 44, "almost_empty_offset": 59, "almost_full_offset": 59, "almostempti": 59, "almostful": 59, "alon": 52, "along": 79, "alreadi": [35, 81], "also": [12, 14, 34, 36, 38, 42, 44, 51, 52, 56, 58, 59, 69, 70, 79, 81], "alt": [38, 52], "alt0": [38, 52, 63], "alt00010001": 62, "alt0010001": 62, "altdig": [38, 52], "altern": [38, 52], "alumode0inv": [64, 67], "alumode0invdsp0": 64, "alumode0invdsp1": 64, "alumode1inv": [64, 67], "alumode2_mux": 67, "alumode2inv": [64, 67], "alumode2invdsp0": 67, "alumode2invdsp1": 67, "alumode3_mux": 67, "alumode3inv": [64, 67], "alumode3invdsp0": [64, 67], "alumode3invdsp1": 67, "alumodereg": [64, 67], "alwai": [12, 14, 17, 35, 36, 38, 42, 44, 51, 52, 56, 58, 70, 81], "amount": [44, 58], "an": [12, 14, 15, 17, 34, 35, 36, 38, 42, 43, 44, 51, 56, 57, 58, 59, 69, 70, 79, 80, 81], "analog": [42, 56], "ani": [35, 36, 38, 42, 44, 56, 58, 81], "anoth": [38, 52, 56], "anyth": [35, 52], "anywai": 42, "aoutmux": 63, "aoutmuxslice1": 63, "appear": [35, 38], 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81], "clk_inv35": 16, "clk_mux": [2, 3, 4, 5, 6, 7, 8, 9, 36, 69, 81], "clk_mux3433": 16, "clk_mux3736": 15, "clka": 59, "clkainv": 48, "clkb": [44, 58, 59], "clkbinv": 48, "clkc": [41, 44, 58], "clkc_50a": [41, 44], "clkc_mux": 60, "clkdiv_delay_en": [2, 3, 6, 7], "clkdiv_div": [2, 3, 6, 7], "clkdiv_en": [2, 3, 6, 7], "clkfb011": 42, "clkin011": 42, "clkinv": [40, 49, 63, 64, 67], "clkinvdsp0": 67, "clkinvdsp1": 67, "clkinvslice0": [49, 63], "clkinvslice1": 63, "clkl": 44, "clkmux": [39, 53], "clkpad": [42, 58], "clkpad0000100000100": 56, "clkpad0001000000010000": 42, "clkpad1000100001000": 56, "clkpad1001000000100000": 42, "clkpad2001000000100": 56, "clkpad2001000001000000": 42, "clkpad3001000001000": 56, "clkpad3001000010000000": 42, "clkpad4010000000100": 56, "clkpad5010000001000": 56, "clkpad6100000000100": 56, "clkpad7100000001000": 56, "clkr": 44, "clkt": [44, 58], "clock": [11, 12, 34, 35, 36, 37, 38, 41, 42, 43, 46, 51, 52, 55, 57, 59, 70, 79, 81], "clock_invert_m": 64, "clock_invert_p": 64, "clock_invert_pdsp1": 64, "clockwis": [44, 58], "close": [44, 51], "closest": 44, "cmo": 14, "cnr": [44, 58], "code": 35, "col": [2, 3, 4, 5, 6, 7, 8, 9, 71, 72, 73, 74, 75, 76], "col_hi": [15, 16], "col_lo": [15, 16], "coloc": [44, 51], "column": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 35, 38, 39, 42, 51, 52, 53, 56, 58, 69, 70, 71, 72, 73, 74, 75, 76, 78, 80], "comb": 36, "comb0": 15, "comb1": 16, "combin": [36, 38, 42, 51, 52, 56, 81], "combination": 51, "combinatori": [14, 36, 81], "come": [12, 34, 36, 38, 44, 51, 58, 79, 81], "commerci": [17, 70], "commonli": 69, "compat": [12, 34, 79], "compens": 52, "complet": [12, 13, 16, 34, 35, 36, 69, 79], "complex": [15, 16], "comput": [51, 69], "concaten": [15, 16, 51, 59], "conceptu": 44, "config": [15, 16, 69], "configur": [11, 12, 15, 33, 34, 35, 37, 39, 41, 42, 43, 50, 55, 56, 57, 58, 65, 69, 78], "configuraton": [15, 16], "conjunct": 36, "connect": [35, 36, 38, 44, 51, 52, 56, 57, 59, 80, 81], "consid": 35, "consist": [35, 36, 51], "const": [13, 14, 35, 36, 38, 52, 80, 81], "constant": [36, 38, 52], "constraint": 12, "construct": 81, "consult": 15, "contain": [15, 17, 34, 38, 42, 43, 44, 51, 52, 56, 57, 58, 59, 80, 81], "content": [35, 38, 52], "contigu": [15, 16], "continu": 35, "control": [12, 14, 35, 36, 38, 43, 52, 57, 59], "convert": [15, 16], "coolrunn": [0, 12, 14], "coordin": [16, 17, 36, 44, 58, 69, 70, 81], "core": [12, 34, 36, 42, 56, 57, 58, 79, 81], "corner": [37, 42, 43, 44, 55, 56, 57, 58], "correct": 59, "correspond": [12, 14, 15, 16, 17, 34, 35, 36, 38, 39, 40, 42, 44, 51, 52, 53, 56, 58, 59, 70, 81], "could": 35, "count": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 38, 44, 51, 58, 71, 72, 73, 74, 75, 76], "cout": [38, 52], "coutmux": 63, "coutmuxslice1": 63, "cover": 81, "cp132": [2, 3, 12], "cp56": [4, 5, 8, 9, 12, 72, 79], "cpld": [0, 12, 34, 36, 79, 81], "crammod": 63, "creat": [42, 56, 58], "creg": [40, 60, 64, 67], "cregdsp": 40, "cregdsp0": [64, 67], "cregdsp1": 67, "cross": [44, 56], "cs144": [20, 21, 34, 73, 79], "cs280": [24, 25, 34, 74, 79], "cs48": [26, 27, 28, 30, 31, 34, 71, 72, 79], "cso2pin": 54, "ct": 14, "ct4111": [2, 3, 4, 5, 6, 7, 8, 9], "ct501": [2, 3, 4, 5, 6, 7, 8, 9], "ct601": [2, 3, 4, 5, 6, 7, 8, 9], "ct70001": [2, 3, 4, 5, 6, 7, 8, 9], "ctc": 14, "cte": 14, "ctlgo001": 42, "ctlmode011": 42, "ctlosc1001": 42, "ctlosc2001": 42, "ctlsel0011": 42, "ctlsel1101": 42, "ctlsel2100": 42, "ctr": 14, "ctrl0": 66, "ctrl00001": 66, "ctrl1": 66, "ctrl10010": 66, "ctrl2": 66, "ctrl3": 66, "curious": [12, 34], "current": [35, 38, 52], "cut": [43, 44], "cv100": [2, 12], "cv64": [5, 9, 12], "cx0": 63, "cx0100": 63, "cx1": 63, "cx10": 63, "cx1010": 63, "cy0": 49, "cy0111": 63, "cy0f": [38, 52], "cy0g": [38, 52], "cy1010": 63, "cy110": 63, "cycl": [35, 51, 59], "cyinit": [38, 49, 52, 63], "cyinitslice0": [38, 49, 63], "cyinitslice1": [38, 49, 63], "cyinitslice2": 38, "cyinitslice3": 38, "cyself": [38, 49, 52], "cyselfslice0": 49, "cyselfslice1": [38, 49], "cyselfslice3": 38, "cyselg": [38, 49, 52], "cyselgslice0": [49, 52], "cyselgslice1": [38, 49, 52], "cyselgslice3": 38, "d": [14, 36, 51, 59, 81], "d0_mux": 67, "d1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76, 81], "d10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 72, 73, 74, 75, 76], "d10_mux": 67, "d11": [3, 6, 7, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "d11_mux": 67, "d12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "d12_mux": 67, "d13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "d13_mux": 67, "d14": [2, 3, 6, 7, 22, 23, 24, 25, 74, 75, 76], "d14_mux": 67, "d15": [3, 6, 7, 22, 23, 24, 25, 74, 75, 76], "d15_mux": 67, "d16": [3, 6, 7, 22, 23, 24, 25, 74, 75, 76], "d16_mux": 67, "d17": [6, 7, 22, 23, 24, 25, 74, 75, 76], "d17_mux": 67, "d18": [6, 7, 22, 23, 24, 25, 74, 75, 76], "d18_mux": 67, "d19": [6, 7, 22, 23, 24, 25, 74, 75, 76], "d19_mux": 67, "d1_mux": 67, "d2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "d20": [6, 7, 22, 23, 24, 75, 76], "d20_mux": 67, "d21": [6, 7, 22, 23, 75, 76], "d21_mux": 67, "d22": [6, 7, 22, 23, 75, 76], "d22_mux": 67, "d23": [22, 23], "d23_mux": 67, "d24": [22, 23], "d24_mux": 67, "d25": [22, 23], "d26": [22, 23], "d2_mux": 67, "d3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "d3_mux": 67, "d4": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "d4_mux": 67, "d5": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "d5_mux": 67, "d5ffinit": 63, "d5ffinitslice0": 63, "d5ffmux": 63, "d5ffsr": 63, "d5ffsrinit": 63, "d5ffsrinitslice0": 63, "d5ffsrslice1": 63, "d5q0": 63, "d5q0100": 63, "d6": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "d6_mux": 67, "d6lut": 63, "d7": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 71, 72, 73, 74, 75, 76], "d7_mux": 67, "d8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 72, 73, 74, 75, 76], "d8_mux": 67, "d9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "d9_mux": 67, "data": [10, 12, 14, 17, 32, 35, 38, 40, 42, 44, 48, 51, 52, 56, 58, 59, 69, 70, 77, 81], "data0": [42, 56], "data00001000001": 56, "data00001000100": 56, "data00mux": 42, "data1": [42, 56], "data10": 42, "data10001000010": 56, "data10001001000": 56, "data101mux": 42, "data10mux": 42, "data11": 42, "data110mux": 42, "data11mux": 42, "data12": 42, "data13": 42, "data130mux": 42, "data131mux": 42, "data14": 42, "data140mux": 42, "data15": 42, "data16": 42, "data160mux": 42, "data17": 42, "data170mux": 42, "data171mux": 42, "data18": 42, "data180mux": 42, "data181mux": 42, "data19": 42, "data190mux": 42, "data2": [42, 56], "data20": 42, "data20001000100": 56, "data20001010000": 56, "data20mux": 42, "data21": 42, "data210mux": 42, "data21mux": 42, "data22": 42, "data220mux": 42, "data221mux": 42, "data23": 42, "data24": 42, "data240mux": 42, "data25": 42, "data250mux": 42, "data251mux": 42, "data26": 42, "data261mux": 42, "data27": 42, "data270mux": 42, "data28": 42, "data29": 42, "data290mux": 42, "data3": [42, 56], "data30": 42, "data30001001000": 56, "data30001100000": 56, "data300mux": 42, "data301mux": 42, "data30mux": 42, "data31": 42, "data4": [42, 56], "data40001000001": 56, "data40001000010": 56, "data40001000100": 56, "data5": [42, 56], "data50001000010": 56, "data50001000100": 56, "data50001001000": 56, "data50mux": 42, "data51mux": 42, "data6": [42, 56], "data60001000100": 56, "data60001001000": 56, "data60001010000": 56, "data60mux": 42, "data7": [42, 56], "data70001001000": 56, "data70001010000": 56, "data70001100000": 56, "data8": 42, "data80mux": 42, "data9": 42, "data90mux": 42, "data91mux": 42, "data_width_": 51, "data_width_a": 51, "data_width_b": 51, "databas": [11, 15, 16, 33, 35, 36, 69, 78, 80, 81], "datap": [51, 59], "datareg": 13, "datastream": [17, 70], "dbl": [39, 42, 47, 53, 56, 62, 66], "dbl0001010000": 66, "dbl0001100000": 66, "dbl0010010000": 66, "dbl0010100000": 66, "dbl0100010000": 66, "dbl0100100000": 66, "dbl1000010000": 66, "dbl1000100000": 66, "dci": [43, 56, 57], "dci_osc_sel": 54, "dcireset0": 54, "dcireset1": 54, "dcm": [43, 51, 55, 58], "dcm_out100": 39, "dcm_out_l0100": [39, 53], "dcm_out_l01000": 39, "dcm_out_r1000": [39, 53], "dcm_out_r10000": 39, "dcmclk": 56, "dcmclk0": 56, "dcmclk00001000001": 56, "dcmclk1": 56, "dcmclk10001000010": 56, "dcmclk2": 56, "dcmclk20001000001": 56, "dcmclk3": 56, "dcmclk30001000010": 56, "dcy0": 63, "dcy0slice0": 63, "dcy0slice1": 63, "dd1": 34, "ddel_a": 51, "ddel_a_default": 51, "ddel_b": 51, "ddel_b_default": 51, "ddr": [43, 57], "deal": [44, 56, 58], "decod": 59, "dedic": [12, 14, 34, 36, 38, 43, 44, 51, 52, 56, 57, 58, 59, 70, 79, 81], "def": [15, 16], "default": [17, 35, 55], "defin": 81, "del_clk_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "del_d_q_comb": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_d_q_latch": [2, 3, 4, 5, 6, 7, 8, 9, 71, 72, 73, 74, 75, 76], "del_exp_d": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_exp_exp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_d": [2, 3, 4, 5, 6, 7, 8, 9, 71, 72, 73, 74, 75, 76], "del_ibuf_fclk": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "del_ibuf_fo": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_fsr": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_ibuf_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "del_ibuf_plain": [2, 3, 4, 5, 6, 7, 8, 9], "del_ibuf_schmitt": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_ct": [2, 3, 4, 5, 6, 7, 8, 9], "del_imux_d_hp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_d_lp": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_fbn": [71, 72, 73, 74, 75, 76], "del_imux_or": [2, 3, 4, 5, 6, 7, 8, 9, 71, 72, 73, 74, 75, 76], "del_imux_pt": [2, 3, 4, 5, 6, 7, 8, 9, 71, 72, 73, 74, 75, 76], "del_imux_pt_c": [20, 21, 24, 25, 27, 28, 30, 31], "del_imux_pt_clk": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "del_imux_pt_o": [18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31], "del_imux_pt_sr": [20, 21, 24, 25, 27, 28, 30, 31], "del_mc_fo": [2, 3, 4, 5, 6, 7, 8, 9], "del_obuf_fast": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "del_obuf_o": [2, 3, 4, 5, 6, 7, 8, 9, 71, 72, 73, 74, 75, 76], "del_obuf_slow": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "del_pt_ut": [71, 72, 73, 74, 75, 76], "del_sr_q": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "del_uim_imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "delai": [14, 39], "depend": [17, 35, 36, 42, 44, 51, 56, 70, 80, 81], "deriv": [12, 34, 43, 57, 79, 81], "describ": [17, 35, 38, 39, 44, 51, 52, 53, 70], "design": [12, 36, 44, 79, 81], "destin": 36, "detail": [35, 44, 58, 59, 80], "determin": [12, 34, 35, 38, 52, 81], "devic": [11, 15, 16, 33, 35, 37, 38, 39, 41, 42, 51, 52, 53, 55, 56, 69, 78, 80], "devicebram": 51, "devicevalu": 39, "dff": [14, 36, 81], "dff0": 16, "dff00": [2, 3, 4, 5, 6, 7, 8, 9, 69], "dff1": 15, "dff_latch": 63, "dff_latchslice0": 63, "dffce": 81, "dffce11": [2, 3, 4, 5, 6, 7, 8, 9, 69], "dffinit": 63, "dffinitslice0": 63, "dffmux": 63, "dffmuxslice1": 63, "dffsr": 63, "dffsrinit": 63, "dffsrinitslice1": 63, "dffsrslice0": 63, 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7, 18, 19, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "p118": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "p119": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "p12": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "p120": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "p121": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "p122": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "p123": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "p124": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "p125": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "p126": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "p127": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "p128": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76], "p129": [2, 3, 6, 7, 18, 19, 20, 21, 22, 23, 24, 25, 73, 74, 75, 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"xa3s700a00": 51, "xa3s700a011": 51, "xa3s700alow": 39, "xa3sd1800a00": 51, "xa3sd1800a011": 51, "xa3sd1800alow": 39, "xa3sd3400a00": 51, "xa3sd3400a011": 51, "xa3sd3400alow": 39, "xa95144xl": [32, 33, 34], "xa9536xl": [32, 33, 34], "xa9572xl": [32, 33, 34], "xb": [38, 42, 52, 56], "xb00101": 38, "xbmux": [38, 52], "xbmuxslice0": 52, "xbmuxslice1": 52, "xc": [12, 34], "xc2c128": [10, 11, 12], "xc2c256": [10, 11, 12], "xc2c32": [10, 11, 12], "xc2c32a": [10, 11, 12], "xc2c384": [10, 11, 12], "xc2c512": [10, 11, 12], "xc2c64": [10, 11, 12], "xc2c64a": [10, 11, 12], "xc2v40": 58, "xc3s1000001": 51, "xc3s100001": 51, "xc3s1000l001": 51, "xc3s1000l01": 51, "xc3s100e": 44, "xc3s100e00": 51, "xc3s100e100": 51, "xc3s1200e00": 51, "xc3s1200e100": 51, "xc3s1400a00": 51, "xc3s1400a011": 51, "xc3s1400alow": 39, "xc3s1400an00": 51, "xc3s1400an011": 51, "xc3s1400anlow": 39, "xc3s1500001": 51, "xc3s150001": 51, "xc3s1500l001": 51, "xc3s1500l01": 51, "xc3s1600e00": 51, "xc3s1600e100": 51, "xc3s20000": 51, "xc3s200000": 51, "xc3s2000001": 51, "xc3s200001": 51, "xc3s200a00": 51, "xc3s200a011": 51, "xc3s200alow": 39, "xc3s200an00": 51, "xc3s200an011": 51, "xc3s200anlow": 39, "xc3s250e00": 51, "xc3s250e100": 51, "xc3s40000": 51, "xc3s400000": 51, "xc3s4000001": 51, "xc3s400001": 51, "xc3s4000l001": 51, "xc3s4000l01": 51, "xc3s400a00": 51, "xc3s400a011": 51, "xc3s400alow": 39, "xc3s400an00": 51, "xc3s400an011": 51, "xc3s400anlow": 39, "xc3s5000001": 51, "xc3s500001": 51, "xc3s50001": 51, "xc3s5001": 51, "xc3s500e00": 51, "xc3s500e100": 51, "xc3s50a": [39, 44], "xc3s50a00": 51, "xc3s50a011": 51, "xc3s50ame": 39, "xc3s50an00": 51, "xc3s50an011": 51, "xc3s50anm": 39, "xc3s700a00": 51, "xc3s700a011": 51, "xc3s700alow": 39, "xc3s700an00": 51, "xc3s700an011": 51, "xc3s700anlow": 39, "xc3sd1800a00": 51, "xc3sd1800a011": 51, "xc3sd1800alow": 39, "xc3sd3400a00": 51, "xc3sd3400a011": 51, "xc3sd3400alow": 39, "xc7200": 34, "xc7300": 34, "xc9500": [0, 12, 16, 17, 34], "xc9500xl": [0, 17, 34], "xc9500xv": [0, 16, 17, 34, 35, 36], "xc95108": [32, 33, 34, 36], "xc95144": [32, 33, 34, 36], "xc95144xl": [32, 33, 34], "xc95144xv": [32, 33, 34], "xc95216": [32, 33, 34, 36], "xc95288": [15, 17, 32, 33, 34, 36], "xc95288xl": [32, 33, 34], "xc95288xv": [32, 33, 34], "xc9536": [32, 33, 34, 36], "xc9536xl": [32, 33, 34], "xc9536xv": [32, 33, 34], "xc9572": [32, 33, 34, 36], "xc9572xl": [32, 33, 34], "xc9572xv": [32, 33, 34], "xc995288": 17, "xcr3032xl": [77, 78, 79, 81], "xcr3064xl": [77, 78, 79], "xcr3128xl": [77, 78, 79], "xcr3256xl": [77, 78, 79], "xcr3384xl": [77, 78, 79, 81], "xcr3512xl": [77, 78, 79, 81], "xilinx": [0, 12, 34, 38, 51, 52, 79, 80], "xl": 36, "xmux": 38, "xor": [11, 33, 81], "xor00": [2, 3, 4, 5, 6, 7, 8, 9], "xor0010": 63, "xor010": 63, "xor0110": 63, "xor1": [2, 3, 4, 5, 6, 7, 8, 9], "xor_mux": [2, 3, 4, 5, 6, 7, 8, 9], "xorci": [38, 52], "xpla": 79, "xpla2": 79, "xpla3": [0, 12, 69, 70, 79, 81], "xq": [38, 42, 52, 56], "xv": 33, "xx": [2, 6, 7, 15, 16, 26, 27, 28, 71, 72, 73, 74, 75, 76], "xxx": [6, 7, 20, 21, 29, 30, 31, 71, 72, 81], "xxxx": [2, 6, 8, 9, 18, 19, 22, 29, 69, 71, 72, 73, 74, 75, 76], "xxxxx": [3, 4, 5, 8, 9, 19, 20, 21, 22, 23, 24, 25, 69, 71, 72, 74, 75], "xxxxxx": [3, 4, 5, 8, 9, 23, 76], "xxxxxxx": [2, 3, 4, 5, 6, 7], "xxxxxxxx": [4, 5, 6, 7, 15, 16, 71, 75], "xxxxxxxxx": [3, 4, 5, 6, 8, 9, 15, 16], "xxxxxxxxxx": [3, 9], "xxxxxxxxxxxx": 2, "xxxxxxxxxxxxxxx": [2, 6, 7, 73, 74, 75, 76], "xxxxxxxxxxxxxxxx": [7, 8, 9], "xxxxxxxxxxxxxxxxx": 72, "xxxxxxxxxxxxxxxxxx": 23, "xxxxxxxxxxxxxxxxxxxxxxxxxxx": 73, "xxxxxxxxxxxxxxxxxxxxxxxxxxxx": 2, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": [2, 3, 4, 5, 6, 7, 8, 9], "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 74, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": [3, 71, 72], "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 75, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 6, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 76, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 7, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 73, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 74, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 76, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 76, "xxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxxx": 75, "xy": [38, 42, 52, 56], "y": [38, 42, 52, 56], "y0": 49, "y00000": 38, "y1": [6, 7, 22, 23, 24, 38, 52, 75, 76], "y10": [6, 7, 24, 75, 76], "y11": [6, 7, 24, 75, 76], "y12": [6, 7, 24, 75, 76], "y13": [6, 7, 24, 75, 76], "y14": [6, 7, 24, 75, 76], "y15": [6, 7, 24, 75, 76], "y16": [6, 7, 24, 75, 76], "y17": [6, 7, 24, 75, 76], "y18": [6, 7, 24, 75, 76], "y19": [6, 7, 24, 75, 76], "y2": [6, 7, 22, 23, 24, 75, 76], "y20": [6, 7, 24, 75, 76], "y21": [6, 7, 75, 76], "y22": [6, 7, 75, 76], "y23": [22, 23], "y24": [22, 23], "y25": [22, 23], "y26": [22, 23], "y3": [6, 7, 22, 23, 24, 75, 76], "y4": [6, 7, 22, 23, 24, 75, 76], "y5": [6, 7, 24, 75, 76], "y6": [6, 7, 24, 75, 76], "y7": [6, 7, 24, 75, 76], "y8": [6, 7, 24, 75, 76], "y9": [6, 7, 24, 75, 76], "yb": [38, 42, 52, 56], "yb00101": 38, "ybmux": [38, 49, 52], "ybmuxslice0": 49, "ybmuxslice1": 49, "ymux": 38, "you": 35, "your": 35, "yq": [38, 42, 52, 56], "z": 35, "zclk_div2": 54, "zero": 81, "zia": [14, 78, 80], "zia_gclk": [69, 81], "zia_gclk0_en": [71, 72, 73, 74, 75, 76], "zia_gclk1_en": [71, 72, 73, 74, 75, 76], "zia_gclk2_en": [71, 72, 73, 74, 75, 76], "zia_gclk3_en": [71, 72, 73, 74, 75, 76], "\u00b5": [17, 35]}, "titles": ["Project Combine", "Bitstream structure", "XC2C128, XA2C128", "XC2C256, XA2C256", "XC2C32", "XC2C32A, XA2C32A", "XC2C384, XA2C384", "XC2C512", "XC2C64", "XC2C64A, XA2C64A", "Database \u2014 devices", "Xilinx Coolrunner II CPLDs", "Introduction", "JTAG interface", "Device structure", "Bitstream structure \u2014 XC9500", "Bitstream structure \u2014 XC9500XL/XV", "Database schema", "XC95108", "XC95144", "XC95144XL, XA95144XL", "XC95144XV", "XC95216", "XC95288", "XC95288XL", "XC95288XV", "XC9536", "XC9536XL, XA9536XL", "XC9536XV", "XC9572", "XC9572XL, XA9572XL", "XC9572XV", "Database \u2014 devices", "Xilinx XC9500, XC9500XL, XC9500XV CPLDs", "Introduction", "JTAG interface", "Device structure", "Xilinx FPGAs", "Configurable Logic Block \u2014 Spartan 3, Virtex 4", "Clock interconnect", "DSP \u2014 Spartan 3A DSP, Spartan 6", "Xilinx Spartan 3 FPGAs", "General interconnect", "Introduction", "Device geometry", "Clock interconnect", "Xilinx Spartan 6 FPGAs", "General interconnect", "Block RAM \u2014 Virtex", "Configurable Logic Block \u2014 Virtex", "Xilinx Virtex, Virtex E, Spartan 2, Spartan 2E FPGAs", "Block RAM \u2014 Virtex 2, Spartan 3", "Configurable Logic Block", "Clock interconnect", "Corners \u2014 Virtex 2, Spartan 3", "Xilinx Virtex 2 FPGAs", "General interconnect", "Introduction", "Device geometry", "Block RAM", "DSP", "Xilinx Virtex 4 FPGAs", "Interconnect", "Configurable Logic Block \u2014 Virtex 5, Virtex 6, Series 7, Spartan 6", "DSP", "Xilinx Virtex 5 FPGAs", "Interconnect \u2014 Virtex 5, Virtex 6, Series 7", "DSP", "Xilinx Virtex 6 FPGAs", "Bitstream structure", "Database schema", "XCR3032XL", "XCR3064XL", "XCR3128XL", "XCR3256XL", "XCR3384XL", "XCR3512XL", "Database \u2014 devices", "Xilinx XPLA3 CPLDs", "Introduction", "JTAG interface", "Device structure"], "titleterms": {"": [39, 56], "03": 42, "1": [38, 52], "12": 42, "128": 52, "16": [38, 52], "2": [50, 51, 54, 55], "2e": 50, "3": [38, 41, 51, 54], "32": [38, 52], "3a": [40, 44, 51], "3e": [44, 51], "4": [38, 61], "5": [63, 65, 66], "6": [40, 46, 63, 66, 67, 68], "64": [38, 52], "7": [63, 66, 67], "AND": 15, "The": [39, 51, 53], "aim": 14, "attribut": 39, "b": 53, "b0": 56, "b123": 56, "backbon": [42, 56], "bank": [14, 44, 58], "bclkpad": 56, "bel": 51, "bit": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 69, 70, 71, 72, 73, 74, 75, 76], "bitsteam": 47, "bitstream": [1, 15, 16, 38, 39, 40, 42, 44, 45, 47, 48, 49, 51, 52, 53, 56, 58, 59, 60, 62, 63, 64, 66, 67, 69], "blank": 35, "block": [38, 48, 49, 51, 52, 59, 63], "bond": [17, 70], "bot": 53, "bottom": [39, 45, 53, 56], "boundari": [13, 35, 80], "bram": [42, 44, 51, 56, 66], "bu": [36, 53], "buffer": [14, 15, 36, 44, 58, 81], "buse": 52, "carri": [38, 52], "center": 39, "check": 35, "clb": [42, 56], "clbll": 63, "clblm": 63, "clexl": 63, "clexm": 63, "clk_b": 56, "clk_t": 56, "clkb": [39, 42, 53], "clkc": 39, "clkc_50a": 39, "clkl": 39, "clkpad": 56, "clkr": 39, "clkt": [39, 42, 53], "clock": [14, 39, 44, 45, 53, 56, 58], "cmt": 47, "cnr": 56, "column": [44, 81], "combin": 0, "configur": [14, 36, 38, 49, 52, 63, 81], "content": [0, 10, 11, 32, 33, 37, 41, 46, 50, 55, 61, 65, 68, 77, 78], "control": 81, "coolrunn": 11, "corner": 54, "cpld": [11, 33, 78], "data": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "databas": [10, 17, 32, 70, 77], "dcm": [42, 44, 53, 56], "dcmconn": 53, "default": [39, 51], "delai": 66, "devic": [10, 12, 14, 17, 32, 34, 36, 43, 44, 57, 58, 70, 77, 79, 81], "distribut": [39, 53], "divid": 14, "dr": 35, "dsp": [40, 42, 44, 60, 64, 67], "dual": [38, 52], "dummi": 42, "e": [50, 56], "ecc": 59, "enabl": 15, "enter": 35, "eras": 35, "exit": 35, "export": 36, "fb": [14, 15, 16, 36, 69, 81], "fclk": 81, "fifo": 59, "flip": 36, "flop": 36, "format": [15, 16], "fpga": [37, 41, 46, 50, 55, 61, 65, 68], "frequenc": 35, "fuse": [15, 16, 35, 36, 69], "gate": [14, 36], "gclkc": 53, "gclkh": [39, 53], "gclkvc": 39, "gclkvm": 39, "gener": [42, 44, 47, 56, 58], "geometri": [44, 58], "global": [2, 3, 4, 5, 6, 7, 8, 9, 14, 15, 16, 36, 69, 71, 72, 73, 74, 75, 76], "gt": 56, "hole": [56, 58], "horizont": 44, "i": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "ibuf": 23, "idcod": [35, 80], "ii": 11, "import": 36, "imux": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 69, 71, 72, 73, 74, 75, 76], "input": [14, 15, 16, 36, 42, 56, 81], "instruct": [13, 35, 80], "int": [42, 56], "interconnect": [39, 42, 45, 47, 53, 56, 62, 66], "interfac": [13, 35, 42, 47, 56, 62, 80], "intf": [42, 47, 56, 66], "introduct": [12, 34, 43, 57, 79], "io": [44, 58], "iob": [2, 3, 6, 7, 14, 69, 81], "ioi": [42, 47, 56], "ir": [13, 35, 80], "isp": [13, 35, 80], "jed": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 69, 70, 71, 72, 73, 74, 75, 76], "jtag": [13, 35, 80], "keeper": 36, "left": [39, 48, 54], "level": [17, 70], "line": 42, "ll": 54, "llh": 42, "llv": 42, "local": 81, "logic": [38, 49, 52, 58, 63], "long": 42, "lower": 54, "lr": [42, 54], "lut": [38, 52], "lut2": 81, "macrocel": [14, 15, 16, 36, 69, 81], "map": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 69, 71, 72, 73, 74, 75, 76], "mc": [2, 3, 4, 5, 6, 7, 8, 9], "middl": 48, "misc": [14, 36, 81], "mode": [35, 59], "mult": 51, "multiplex": [38, 42, 52, 56], "n": [39, 56], "network": [14, 36, 81], "normal": 47, "o": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76], "option": [39, 51], "output": [14, 36, 38, 42, 52, 53, 56, 81], "overview": [14, 36, 81], "packag": [12, 34, 79], "part": [17, 70], "pci": 58, "per": [15, 16], "pin": [2, 3, 4, 5, 6, 7, 8, 9, 12, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 34, 71, 72, 73, 74, 75, 76, 79], "port": [38, 52], "powerpc": [56, 58], "ppc": 56, "primari": 44, "primit": [42, 56], "product": [14, 15, 16, 36, 52, 69, 81], "program": [13, 35, 80], "project": 0, "protect": 35, "pt": 36, "pull": 36, "ram": [38, 48, 51, 52, 59], "read": 35, "regist": [13, 14, 35, 38, 52, 80, 81], "right": [39, 48, 54], "row": [39, 44, 53, 58, 81], "s3": [39, 42, 51, 54], "s3a": [39, 42, 51, 54], "s3adsp": [42, 51], "s3e": [39, 42, 51, 54], "scan": [13, 35, 80], "schema": [17, 70], "secondari": [39, 44], "sequenc": [13, 35, 80], "seri": [63, 66, 67], "shift": [38, 52], "side": 48, "singl": [38, 52], "sourc": [39, 53], "spartan": [38, 40, 41, 44, 46, 50, 51, 54, 63], "speed": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 70, 71, 72, 73, 74, 75, 76], "spine": [39, 44, 53, 56, 58], "splitter": 42, "structur": [1, 14, 15, 16, 36, 44, 58, 69, 81], "sum": [14, 36, 52, 69, 81], "t": 53, "t0": 56, "t123": 56, "tabl": [43, 57], "tb": 42, "tbuf": 52, "tclkpad": 56, "term": [14, 15, 16, 36, 56, 69, 81], "termin": [42, 56], "tile": [17, 39, 42, 45, 47, 53, 56, 62, 70], "todo": [1, 12, 13, 14, 35, 36, 38, 39, 40, 41, 43, 44, 46, 50, 51, 52, 53, 54, 55, 56, 57, 58, 59, 61, 65, 68, 80, 81], "top": [17, 39, 45, 53, 56, 70], "tristat": 52, "uim": [15, 23, 36], "ul": 54, "uni": 39, "univers": 81, "up": 36, "upper": 54, "ur": 54, "v2": [53, 54, 56], "v2p": [53, 54, 56], "v2px": 53, "valu": 51, "vertic": 44, "virtex": [38, 48, 49, 50, 51, 54, 55, 61, 63, 65, 66, 67, 68], "w": 56, "wide": [38, 52], "wire": 15, "without": [2, 3, 6, 7, 69], "write": 35, "x": [38, 52], "xa2c128": 2, "xa2c256": 3, "xa2c32a": 5, "xa2c384": 6, "xa2c64a": 9, "xa95144xl": 20, "xa9536xl": 27, "xa9572xl": 30, "xc2c128": 2, "xc2c256": 3, "xc2c32": 4, "xc2c32a": 5, "xc2c384": 6, "xc2c512": 7, "xc2c64": 8, "xc2c64a": 9, "xc9500": [15, 33, 35, 36], "xc9500xl": [16, 33, 35, 36], "xc9500xv": 33, "xc95108": 18, "xc95144": 19, "xc95144xl": 20, "xc95144xv": 21, "xc95216": 22, "xc95288": 23, "xc95288xl": 24, "xc95288xv": 25, "xc9536": 26, "xc9536xl": 27, "xc9536xv": 28, "xc9572": 29, "xc9572xl": 30, "xc9572xv": 31, "xcr3032xl": 71, "xcr3064xl": 72, "xcr3128xl": 73, "xcr3256xl": 74, "xcr3384xl": 75, "xcr3512xl": 76, "xilinx": [11, 33, 37, 41, 46, 50, 55, 61, 65, 68, 78], "xor": [14, 36], "xpla3": 78, "xv": [16, 35, 36], "zia": 81}})
\ No newline at end of file
+Search.setIndex({"alltitles": {"AIM and FB inputs": [[14, "aim-and-fb-inputs"]], "BRAM (Virtex 2)": [[51, "bram-virtex-2"]], "BRAM.S3": [[51, "bram-s3"]], "BRAM.S3A": [[51, "bram-s3a"]], "BRAM.S3ADSP": [[51, "bram-s3adsp"]], "BRAM.S3E": [[51, "bram-s3e"]], "Backbone": [[42, "backbone"], [56, "backbone"]], "Bank configuration": [[14, "bank-configuration"]], "Bitsteam \u2014 interface tiles": [[47, "bitsteam-interface-tiles"]], "Bitstream": [[38, "bitstream"], [40, "bitstream"], [49, "bitstream"], [51, "bitstream"], [52, "bitstream"], [60, "bitstream"], [61, "bitstream"], [63, "bitstream"], [65, "bitstream"]], "Bitstream geometry": [[44, "bitstream-geometry"], [59, "bitstream-geometry"]], "Bitstream structure": [[1, "bitstream-structure"], [70, "bitstream-structure"]], "Bitstream structure \u2014 XC9500": [[15, "bitstream-structure-xc9500"]], "Bitstream structure \u2014 XC9500XL/XV": [[16, "bitstream-structure-xc9500xl-xv"]], "Bitstream \u2014 IOI tile": [[47, "bitstream-ioi-tile"]], "Bitstream \u2014 LLH tiles": [[42, "bitstream-llh-tiles"]], "Bitstream \u2014 LLV tiles": [[42, "bitstream-llv-tiles"]], "Bitstream \u2014 PowerPC hole tiles": [[56, "bitstream-powerpc-hole-tiles"]], "Bitstream \u2014 Series 7": [[64, "bitstream-series-7"], [67, "bitstream-series-7"], [68, "bitstream-series-7"]], "Bitstream \u2014 Spartan 6": [[64, "bitstream-spartan-6"]], "Bitstream \u2014 Virtex 5": [[64, "bitstream-virtex-5"], [67, "bitstream-virtex-5"]], "Bitstream \u2014 Virtex 6": [[64, "bitstream-virtex-6"], [67, "bitstream-virtex-6"], [68, "bitstream-virtex-6"]], "Bitstream \u2014 bottom tile": [[45, "bitstream-bottom-tile"]], "Bitstream \u2014 bottom tiles": [[39, "bitstream-bottom-tiles"], [53, "bitstream-bottom-tiles"]], "Bitstream \u2014 interconnect tiles": [[42, "bitstream-interconnect-tiles"], [56, "bitstream-interconnect-tiles"]], "Bitstream \u2014 interface tile": [[63, "bitstream-interface-tile"]], "Bitstream \u2014 interface tiles": [[42, "bitstream-interface-tiles"], [56, "bitstream-interface-tiles"]], "Bitstream \u2014 left side": [[48, "bitstream-left-side"]], "Bitstream \u2014 left tiles": [[39, "bitstream-left-tiles"]], "Bitstream \u2014 middle": [[48, "bitstream-middle"]], "Bitstream \u2014 normal tile": [[47, "bitstream-normal-tile"]], "Bitstream \u2014 right side": [[48, "bitstream-right-side"]], "Bitstream \u2014 right tiles": [[39, "bitstream-right-tiles"]], "Bitstream \u2014 terminator tiles": [[56, "bitstream-terminator-tiles"]], "Bitstream \u2014 top tile": [[45, "bitstream-top-tile"]], "Bitstream \u2014 top tiles": [[39, "bitstream-top-tiles"], [53, "bitstream-top-tiles"]], "Blank check \u2014 XC9500XL/XV": [[35, "blank-check-xc9500xl-xv"]], "Block RAM": [[60, "block-ram"]], "Block RAM \u2014 Virtex": [[48, "block-ram-virtex"]], "Block RAM \u2014 Virtex 2, Spartan 3": [[51, "block-ram-virtex-2-spartan-3"]], "Bond": [[17, "bond"], [71, "bond"]], "Boundary scan register": [[13, "boundary-scan-register"], [35, "boundary-scan-register"], [81, "boundary-scan-register"]], "CLBLL": [[64, "clbll"], [64, "id1"], [64, "id3"]], "CLBLM": [[64, "clblm"], [64, "id2"], [64, "id4"]], "CLEXL": [[64, "clexl"]], "CLEXM": [[64, "clexm"]], "CLKB.S3": [[39, "clkb-s3"]], "CLKB.S3A": [[39, "clkb-s3a"]], "CLKB.S3E": [[39, "clkb-s3e"]], "CLKB.V2": [[53, "clkb-v2"]], "CLKB.V2P": [[53, "clkb-v2p"]], "CLKB.V2PX": [[53, "clkb-v2px"]], "CLKL.S3A": [[39, "clkl-s3a"]], "CLKL.S3E": [[39, "clkl-s3e"]], "CLKR.S3A": [[39, "clkr-s3a"]], "CLKR.S3E": [[39, "clkr-s3e"]], "CLKT.S3": [[39, "clkt-s3"]], "CLKT.S3A": [[39, "clkt-s3a"]], "CLKT.S3E": [[39, "clkt-s3e"]], "CLKT.V2": [[53, "clkt-v2"]], "CLKT.V2P": [[53, "clkt-v2p"]], "CLKT.V2PX": [[53, "clkt-v2px"]], "Carry logic": [[38, "carry-logic"], [52, "carry-logic"]], "Clock divider": [[14, "clock-divider"]], "Clock interconnect": [[39, "clock-interconnect"], [45, "clock-interconnect"], [53, "clock-interconnect"]], "Clock rows": [[44, "clock-rows"], [59, "clock-rows"]], "Clock source \u2014 left and right": [[39, "clock-source-left-and-right"]], "Clock source \u2014 spine bottom and top": [[39, "clock-source-spine-bottom-and-top"], [53, "clock-source-spine-bottom-and-top"]], "Clock spine": [[59, "clock-spine"]], "Clock spine top and bottom": [[56, "clock-spine-top-and-bottom"]], "Configurable Logic Block": [[52, "configurable-logic-block"]], "Configurable Logic Block \u2014 Spartan 3, Virtex 4": [[38, "configurable-logic-block-spartan-3-virtex-4"]], "Configurable Logic Block \u2014 Virtex": [[49, "configurable-logic-block-virtex"]], "Configurable Logic Block \u2014 Virtex 5, Virtex 6, Series 7, Spartan 6": [[64, "configurable-logic-block-virtex-5-virtex-6-series-7-spartan-6"]], "Configuration pull-ups": [[36, "configuration-pull-ups"]], "Contents:": [[0, null], [10, null], [11, null], [32, null], [33, null], [37, null], [41, null], [46, null], [50, null], [55, null], [62, null], [66, null], [69, null], [78, null], [79, null]], "Corners \u2014 Virtex 2, Spartan 3": [[54, "corners-virtex-2-spartan-3"]], "DCM output bus": [[53, "dcm-output-bus"]], "DCMCONN.BOT": [[53, "dcmconn-bot"]], "DCMCONN.TOP": [[53, "dcmconn-top"]], "DSP": [[61, "dsp"], [65, "dsp"], [68, "dsp"]], "DSP \u2014 Spartan 3A DSP, Spartan 6": [[40, "dsp-spartan-3a-dsp-spartan-6"]], "Database schema": [[17, "database-schema"], [71, "database-schema"]], "Database \u2014 devices": [[10, "database-devices"], [32, "database-devices"], [78, "database-devices"]], "Default option attributes": [[39, "default-option-attributes"]], "Default option values": [[51, "default-option-values"]], "Device": [[17, "device"], [71, "device"]], "Device geometry": [[44, "device-geometry"], [59, "device-geometry"]], "Device pins": [[12, "device-pins"], [34, "device-pins"], [80, "device-pins"]], "Device structure": [[14, "device-structure"], [36, "device-structure"], [82, "device-structure"]], "Device table": [[43, "device-table"], [57, "device-table"]], "Devices": [[12, "devices"], [34, "devices"], [80, "devices"]], "Dual-port 16\u00d7X RAM": [[38, "dual-port-16x-ram"], [52, "dual-port-16x-ram"]], "Dual-port 32\u00d7X RAM": [[52, "dual-port-32x-ram"]], "Dual-port 64\u00d71 RAM": [[52, "dual-port-641-ram"]], "ECC mode": [[60, "ecc-mode"]], "Entering and exiting ISP mode \u2014 XC9500": [[35, "entering-and-exiting-isp-mode-xc9500"]], "Entering and exiting ISP mode \u2014 XC9500XL/XV": [[35, "entering-and-exiting-isp-mode-xc9500xl-xv"]], "Erasing fuses \u2014 XC9500": [[35, "erasing-fuses-xc9500"]], "Erasing fuses \u2014 XC9500XL/XV": [[35, "erasing-fuses-xc9500xl-xv"]], "FB columns and rows": [[82, "fb-columns-and-rows"]], "FB global fuses": [[36, "fb-global-fuses"]], "FCLK networks": [[82, "fclk-networks"]], "FIFO mode": [[60, "fifo-mode"]], "Flip-flop": [[36, "flip-flop"]], "Frequency": [[35, "frequency"]], "Fuses \u2014 FB inputs": [[15, "fuses-fb-inputs"], [16, "fuses-fb-inputs"]], "Fuses \u2014 FBs": [[70, "fuses-fbs"]], "Fuses \u2014 IMUX bits": [[70, "fuses-imux-bits"]], "Fuses \u2014 UIM wire-AND": [[15, "fuses-uim-wire-and"]], "Fuses \u2014 global bits": [[70, "fuses-global-bits"]], "Fuses \u2014 input buffer enable": [[15, "fuses-input-buffer-enable"]], "Fuses \u2014 macrocells": [[15, "fuses-macrocells"], [16, "fuses-macrocells"], [70, "fuses-macrocells"]], "Fuses \u2014 per-FB bits and globals": [[15, "fuses-per-fb-bits-and-globals"], [16, "fuses-per-fb-bits-and-globals"]], "Fuses \u2014 product and sum terms": [[70, "fuses-product-and-sum-terms"]], "Fuses \u2014 product terms": [[15, "fuses-product-terms"], [16, "fuses-product-terms"]], "GCLKC": [[53, "gclkc"]], "GCLKC.B": [[53, "gclkc-b"]], "GCLKC.T": [[53, "gclkc-t"]], "GCLKH": [[39, "gclkh"], [53, "gclkh"]], "GCLKH.N": [[39, "gclkh-n"]], "GCLKH.S": [[39, "gclkh-s"]], "GCLKH.UNI": [[39, "gclkh-uni"]], "GCLKH.UNI.N": [[39, "gclkh-uni-n"]], "GCLKH.UNI.S": [[39, "gclkh-uni-s"]], "GCLKVM.S3": [[39, "gclkvm-s3"]], "GCLKVM.S3E": [[39, "gclkvm-s3e"]], "General interconnect": [[42, "general-interconnect"], [47, "general-interconnect"], [56, "general-interconnect"]], "General structure": [[44, "general-structure"], [59, "general-structure"]], "Global bits": [[2, "global-bits"], [3, "global-bits"], [4, "global-bits"], [5, "global-bits"], [6, "global-bits"], [7, "global-bits"], [8, "global-bits"], [9, "global-bits"], [72, "global-bits"], [73, "global-bits"], [74, "global-bits"], [75, "global-bits"], [76, "global-bits"], [77, "global-bits"]], "Global networks": [[14, "global-networks"]], "Global networks \u2014 XC9500": [[36, "global-networks-xc9500"]], "Global networks \u2014 XC9500XL/XV": [[36, "global-networks-xc9500xl-xv"]], "Horizontal clock spine": [[44, "horizontal-clock-spine"]], "I/O buffers": [[58, "i-o-buffers"]], "I/O interface": [[58, "i-o-interface"]], "I/O pins": [[2, "i-o-pins"], [3, "i-o-pins"], [4, "i-o-pins"], [5, "i-o-pins"], [6, "i-o-pins"], [7, "i-o-pins"], [8, "i-o-pins"], [9, "i-o-pins"], [18, "i-o-pins"], [19, "i-o-pins"], [20, "i-o-pins"], [21, "i-o-pins"], [22, "i-o-pins"], [23, "i-o-pins"], [24, "i-o-pins"], [25, "i-o-pins"], [26, "i-o-pins"], [27, "i-o-pins"], [28, "i-o-pins"], [29, "i-o-pins"], [30, "i-o-pins"], [31, "i-o-pins"], [72, "i-o-pins"], [73, "i-o-pins"], [74, "i-o-pins"], [75, "i-o-pins"], [76, "i-o-pins"], [77, "i-o-pins"]], "IDCODE": [[35, "idcode"], [81, "idcode"]], "IMUX bits": [[2, "imux-bits"], [3, "imux-bits"], [4, "imux-bits"], [5, "imux-bits"], [6, "imux-bits"], [7, "imux-bits"], [8, "imux-bits"], [9, "imux-bits"], [18, "imux-bits"], [19, "imux-bits"], [20, "imux-bits"], [21, "imux-bits"], [22, "imux-bits"], [23, "imux-bits"], [24, "imux-bits"], [25, "imux-bits"], [26, "imux-bits"], [27, "imux-bits"], [28, "imux-bits"], [29, "imux-bits"], [30, "imux-bits"], [31, "imux-bits"], [72, "imux-bits"], [73, "imux-bits"], [74, "imux-bits"], [75, "imux-bits"], [76, "imux-bits"], [77, "imux-bits"]], "INT.BRAM": [[56, "int-bram"]], "INT.BRAM.S3": [[42, "int-bram-s3"]], "INT.BRAM.S3A.03": [[42, "int-bram-s3a-03"]], "INT.BRAM.S3A.12": [[42, "int-bram-s3a-12"]], "INT.BRAM.S3ADSP": [[42, "int-bram-s3adsp"]], "INT.BRAM.S3E": [[42, "int-bram-s3e"]], "INT.CLB": [[42, "int-clb"], [56, "int-clb"]], "INT.CNR": [[56, "int-cnr"]], "INT.DCM": [[42, "int-dcm"]], "INT.DCM.S3E.DUMMY": [[42, "int-dcm-s3e-dummy"]], "INT.DCM.V2": [[56, "int-dcm-v2"]], "INT.DCM.V2P": [[56, "int-dcm-v2p"]], "INT.GT.CLKPAD": [[56, "int-gt-clkpad"]], "INT.IOI": [[56, "int-ioi"]], "INT.IOI.CLK_B": [[56, "int-ioi-clk-b"]], "INT.IOI.CLK_T": [[56, "int-ioi-clk-t"]], "INT.IOI.S3": [[42, "int-ioi-s3"]], "INT.IOI.S3A.LR": [[42, "int-ioi-s3a-lr"]], "INT.IOI.S3A.TB": [[42, "int-ioi-s3a-tb"]], "INT.IOI.S3E": [[42, "int-ioi-s3e"]], "INT.PPC": [[56, "int-ppc"]], "INTF": [[47, "intf"], [67, "intf"], [67, "id1"], [67, "id3"]], "INTF.BRAM": [[67, "intf-bram"]], "INTF.CMT": [[47, "intf-cmt"]], "INTF.CMT.IOI": [[47, "intf-cmt-ioi"]], "INTF.DELAY": [[67, "intf-delay"], [67, "id2"], [67, "id4"]], "INTF.DSP": [[42, "intf-dsp"]], "INTF.GT.B0": [[56, "intf-gt-b0"]], "INTF.GT.B123": [[56, "intf-gt-b123"]], "INTF.GT.BCLKPAD": [[56, "intf-gt-bclkpad"]], "INTF.GT.T0": [[56, "intf-gt-t0"]], "INTF.GT.T123": [[56, "intf-gt-t123"]], "INTF.GT.TCLKPAD": [[56, "intf-gt-tclkpad"]], "INTF.IOI": [[47, "intf-ioi"]], "INTF.PPC": [[56, "intf-ppc"]], "IO banks and IO buffers": [[44, "io-banks-and-io-buffers"], [59, "io-banks-and-io-buffers"]], "IOI \u2014 Virtex 2": [[58, "ioi-virtex-2"]], "IOI.CLK_B \u2014 Virtex 2": [[58, "ioi-clk-b-virtex-2"]], "IOI.CLK_T \u2014 Virtex 2": [[58, "ioi-clk-t-virtex-2"]], "IOI.S3": [[58, "ioi-s3"]], "IOI.S3A.B": [[58, "ioi-s3a-b"]], "IOI.S3A.L": [[58, "ioi-s3a-l"]], "IOI.S3A.R": [[58, "ioi-s3a-r"]], "IOI.S3A.T": [[58, "ioi-s3a-t"]], "IOI.S3ADSP.B": [[58, "ioi-s3adsp-b"]], "IOI.S3ADSP.L": [[58, "ioi-s3adsp-l"]], "IOI.S3ADSP.R": [[58, "ioi-s3adsp-r"]], "IOI.S3ADSP.T": [[58, "ioi-s3adsp-t"]], "IOI.S3E": [[58, "ioi-s3e"]], "IR": [[13, "ir"], [35, "ir"], [81, "ir"]], "ISP DR registers \u2014 XC9500": [[35, "isp-dr-registers-xc9500"]], "ISP DR registers \u2014 XC9500XL/XV": [[35, "isp-dr-registers-xc9500xl-xv"]], "ISP instructions": [[13, "isp-instructions"], [81, "isp-instructions"]], "ISP instructions \u2014 XC9500": [[35, "isp-instructions-xc9500"]], "ISP instructions \u2014 XC9500XL/XV": [[35, "isp-instructions-xc9500xl-xv"]], "Input / Output \u2014 Virtex 2, Spartan 3": [[58, "input-output-virtex-2-spartan-3"]], "Input multiplexers": [[42, "input-multiplexers"], [56, "input-multiplexers"]], "Input/output buffer": [[14, "input-output-buffer"], [36, "input-output-buffer"], [82, "input-output-buffer"]], "Interconnect": [[63, "interconnect"]], "Interconnect \u2014 Virtex 5, Virtex 6, Series 7": [[67, "interconnect-virtex-5-virtex-6-series-7"]], "Introduction": [[12, "introduction"], [34, "introduction"], [43, "introduction"], [57, "introduction"], [80, "introduction"]], "JED bits": [[71, "jed-bits"]], "JED format mapping": [[15, "jed-format-mapping"], [16, "jed-format-mapping"]], "JED mapping": [[2, "jed-mapping"], [3, "jed-mapping"], [4, "jed-mapping"], [4, "id1"], [5, "jed-mapping"], [5, "id1"], [6, "jed-mapping"], [7, "jed-mapping"], [8, "jed-mapping"], [8, "id1"], [9, "jed-mapping"], [9, "id1"], [70, "jed-mapping"], [72, "jed-mapping"], [73, "jed-mapping"], [74, "jed-mapping"], [75, "jed-mapping"], [76, "jed-mapping"], [77, "jed-mapping"]], "JED mapping \u2014 MCs with IOBs": [[2, "jed-mapping-mcs-with-iobs"], [3, "jed-mapping-mcs-with-iobs"], [6, "jed-mapping-mcs-with-iobs"], [7, "jed-mapping-mcs-with-iobs"]], "JED mapping \u2014 MCs without IOBs": [[2, "jed-mapping-mcs-without-iobs"], [3, "jed-mapping-mcs-without-iobs"], [6, "jed-mapping-mcs-without-iobs"], [7, "jed-mapping-mcs-without-iobs"]], "JED mapping \u2014 macrocells with IOB": [[70, "jed-mapping-macrocells-with-iob"]], "JED mapping \u2014 macrocells without IOB": [[70, "jed-mapping-macrocells-without-iob"]], "JED structure": [[70, "jed-structure"]], "JTAG interface": [[13, "jtag-interface"], [35, "jtag-interface"], [81, "jtag-interface"]], "LL \u2014 Virtex 2": [[54, "ll-virtex-2"]], "LL.S3": [[54, "ll-s3"]], "LL.S3A": [[54, "ll-s3a"]], "LL.S3E": [[54, "ll-s3e"]], "LLH": [[42, "llh"]], "LLH.CLKB.S3A": [[42, "llh-clkb-s3a"]], "LLH.CLKT.S3A": [[42, "llh-clkt-s3a"]], "LLV.S3A": [[42, "llv-s3a"]], "LLV.S3E": [[42, "llv-s3e"]], "LR \u2014 Virtex 2": [[54, "lr-virtex-2"]], "LR.S3": [[54, "lr-s3"]], "LR.S3A": [[54, "lr-s3a"]], "LR.S3E": [[54, "lr-s3e"]], "LUT RAM": [[38, "lut-ram"], [52, "lut-ram"]], "LUTs": [[38, "luts"], [52, "luts"]], "Local control terms": [[82, "local-control-terms"]], "Long line splitters": [[42, "long-line-splitters"]], "Lower left": [[54, "lower-left"]], "Lower right": [[54, "lower-right"]], "MC bits": [[2, "mc-bits"], [3, "mc-bits"], [4, "mc-bits"], [5, "mc-bits"], [6, "mc-bits"], [7, "mc-bits"], [8, "mc-bits"], [9, "mc-bits"]], "Macrocell and IOB outputs": [[14, "macrocell-and-iob-outputs"], [82, "macrocell-and-iob-outputs"]], "Macrocell output \u2014 XC9500": [[36, "macrocell-output-xc9500"]], "Macrocell output \u2014 XC9500XL/XV": [[36, "macrocell-output-xc9500xl-xv"]], "Misc configuration": [[14, "misc-configuration"], [36, "misc-configuration"], [82, "misc-configuration"]], "Output multiplexers": [[52, "output-multiplexers"]], "Output multiplexers \u2014 Spartan 3": [[38, "output-multiplexers-spartan-3"]], "Output multiplexers \u2014 Virtex 4": [[38, "output-multiplexers-virtex-4"]], "Overview": [[14, "overview"], [36, "overview"], [82, "overview"]], "PCI logic": [[59, "pci-logic"]], "PPC.E": [[56, "ppc-e"]], "PPC.N": [[56, "ppc-n"]], "PPC.S": [[56, "ppc-s"]], "PPC.W": [[56, "ppc-w"]], "PT import/export": [[36, "pt-import-export"]], "Packages": [[12, "packages"], [34, "packages"], [80, "packages"]], "Part": [[17, "part"], [71, "part"]], "PowerPC holes": [[56, "powerpc-holes"], [59, "powerpc-holes"]], "Primary vertical clock spine": [[44, "primary-vertical-clock-spine"]], "Primitive outputs": [[42, "primitive-outputs"], [56, "primitive-outputs"]], "Product terms": [[14, "product-terms"], [36, "product-terms"], [82, "product-terms"]], "Programming fuses \u2014 XC9500": [[35, "programming-fuses-xc9500"]], "Programming fuses \u2014 XC9500XL/XV": [[35, "programming-fuses-xc9500xl-xv"]], "Programming sequence": [[13, "programming-sequence"], [35, "programming-sequence"], [81, "programming-sequence"]], "Project Combine": [[0, "project-combine"]], "Reading fuses \u2014 XC9500": [[35, "reading-fuses-xc9500"]], "Reading fuses \u2014 XC9500XL/XV": [[35, "reading-fuses-xc9500xl-xv"]], "Register": [[14, "register"], [82, "register"]], "Registers": [[38, "registers"], [52, "registers"]], "Secondary vertical clock spines": [[44, "secondary-vertical-clock-spines"]], "Shift registers": [[38, "shift-registers"], [52, "shift-registers"]], "Single-port 128\u00d71 RAM": [[52, "single-port-1281-ram"]], "Single-port 16\u00d7X RAM": [[38, "single-port-16x-ram"], [52, "single-port-16x-ram"]], "Single-port 32\u00d7X RAM": [[38, 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74, 75, 76, 77], "c20": [6, 7, 22, 23, 24, 76, 77], "c21": [6, 7, 22, 23, 76, 77], "c22": [6, 7, 22, 23, 76, 77], "c23": [22, 23], "c24": [22, 23], "c25": [22, 23], "c26": [22, 23], "c3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 72, 73, 74, 75, 76, 77], "c4": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 72, 73, 74, 75, 76, 77], "c5": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 72, 73, 74, 75, 76, 77], "c5ffinit": 64, "c5ffinitslice0": 64, "c5ffmux": 64, "c5ffsr": 64, "c5ffsrinit": 64, "c5ffsrinitslice0": 64, "c5ffsrslice0": 64, "c5ffsrslice1": 64, "c5q0": 64, "c5q0100": 64, "c6": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 72, 73, 74, 75, 76, 77], "c6lut": 64, "c7": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 72, 73, 74, 75, 76, 77], "c8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76, 77], "c9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 74, 75, 76, 77], "calcul": [15, 16], "call": [36, 42, 44, 56, 59, 82], "came": [35, 56], "can": [12, 14, 17, 34, 35, 36, 38, 42, 43, 44, 51, 52, 56, 59, 60, 70, 71, 80, 81, 82], "cannot": [35, 38, 52, 60, 82], "capabl": [12, 34, 38, 57, 60], "captur": [38, 43, 52, 57, 81], "cardin": [42, 56], "care": 35, "carri": [41, 55], "carryin0": 40, "carryininv": [61, 65, 68], "carryininvdsp0": [65, 68], "carryininvdsp1": [65, 68], "carryinreg": [40, 61, 65, 68], "carryinregdsp": 40, "carryinregdsp0": 68, "carryinregdsp1": 68, "carryinsel": 40, "carryinsel0inv": 61, "carryinsel1inv": 61, "carryinsel2_mux": 68, "carryinseldsp": 40, "carryinselreg": [61, 65, 68], "carryinselregdsp0": 68, "carryinselregdsp1": 68, "carryoutreg": 40, "carryoutregdsp": 40, "cascad": [51, 56, 60], "cascade1": [40, 51, 61, 65, 68], "cascadein": 60, "cascadeout": 60, "case": [36, 56, 82], "cclk2pin": 54, "cclkpin": 54, "ccy0": 64, "ccy0slice0": 64, "ccy0slice1": 64, "cdi1mux": 64, "cdi1muxslice0": 64, "cdr": [2, 3, 6, 7], "cdrst": [12, 14], "ce": [14, 36, 38, 42, 51, 52, 56, 82], "ce0": [42, 56, 63], "ce00001000001": 56, "ce00mux": 42, "ce01": 63, "ce0int": [42, 56], "ce1": [42, 56, 63, 64], "ce10001000010": 56, "ce10mux": 42, "ce11": 63, "ce1int": [42, 56], "ce2": [42, 56, 63], "ce20": 42, "ce20001000001": 56, "ce20mux": 42, "ce21": 63, "ce2int": [42, 56], "ce3": [42, 56, 63], "ce30001000010": 56, "ce30mux": 42, "ce31": 63, "ce3int": [42, 56], "ce_mux": [36, 70, 82], "ce_mux3736": 16, "cea": 51, "cead_mux": 68, "ceainv": 40, "cealumode_mux": 68, "ceb": 51, "cebinv": 40, "cecarryininv": 40, "cecarryininvdsp": 40, "cecinv": 40, "ced_mux": 68, "cedinv": 40, "cedinvdsp": 40, "ceinmode_mux": 68, "ceinv": 49, "ceinvslice0": 49, "cell": [35, 81], "ceminv": 40, "center": 41, "ceopmodeinv": 40, "cep": 51, "cepinv": 40, "cepinvdsp": 40, "cff_latch": 64, "cff_latchslice0": 64, "cffinit": 64, "cffinitslice0": 64, "cffinitslice1": 64, "cffmux": 64, "cffmuxslice1": 64, "cffsr": 64, "cffsrinit": 64, "cffsrinitslice0": 64, "cffsrinitslice1": 64, "cffsrslice1": 64, "cfuse": [15, 16], "cgate111": 54, "cgate1111": 54, "chain": [36, 38, 51, 52, 60], "chanc": 51, "chang": [34, 35, 38, 43, 44], "charact": 82, "check": 70, "chip": [12, 34, 36, 80], "choic": [56, 82], "ci1": 64, "cin": [38, 52], "cin0": 49, "cin1": [38, 52, 64], "circuit": 35, "circuitri": [35, 36, 38, 44, 52], "cki0010": [39, 53], "cki010": 39, "ckil00010": 39, "ckir00100": 39, "clamp": [13, 35, 81], "classic": [36, 82], "clb": [38, 44, 52, 59], "clear": 35, "clk": [14, 36, 38, 39, 42, 44, 51, 52, 53, 56, 60, 82], "clk0": [39, 42, 47, 53, 56, 63, 67], "clk00": 47, "clk000": 67, "clk00001": 67, "clk00001000001": 56, "clk01": 63, "clk0int": [42, 56], "clk1": [39, 42, 47, 53, 56, 63, 67], "clk100": 67, "clk10001000010": 56, "clk10010": 67, "clk11": [47, 63], "clk1int": [42, 56], "clk2": [39, 42, 53, 56, 63], "clk20001000001": 56, "clk21": 63, "clk2int": [42, 56], "clk3": [39, 42, 53, 56, 63], "clk30001000010": 56, "clk30mux": 42, "clk31": 63, "clk3int": [42, 56], "clk4": 53, "clk5": 53, "clk6": 53, "clk7": 53, "clk_ddr": [2, 3, 4, 5, 6, 7, 8, 9], "clk_inv": [2, 3, 4, 5, 6, 7, 8, 9, 36, 70, 82], "clk_inv35": 16, "clk_mux": [2, 3, 4, 5, 6, 7, 8, 9, 36, 70, 82], "clk_mux3433": 16, "clk_mux3736": 15, "clka": 60, "clkainv": 48, "clkb": [44, 59, 60], "clkbinv": 48, "clkc": [41, 44, 59], "clkc_50a": [41, 44], "clkc_mux": 61, "clkdiv_delay_en": [2, 3, 6, 7], "clkdiv_div": [2, 3, 6, 7], "clkdiv_en": [2, 3, 6, 7], "clkfb011": 42, "clkin011": 42, "clkinv": [40, 49, 64, 65, 68], "clkinvdsp0": 68, "clkinvdsp1": 68, "clkinvslice0": [49, 64], "clkinvslice1": 64, "clkl": 44, "clkmux": [39, 53], "clkpad": [42, 59], "clkpad0000100000100": 56, "clkpad0001000000010000": 42, "clkpad1000100001000": 56, "clkpad1001000000100000": 42, "clkpad2001000000100": 56, "clkpad2001000001000000": 42, "clkpad3001000001000": 56, "clkpad3001000010000000": 42, "clkpad4010000000100": 56, "clkpad5010000001000": 56, "clkpad6100000000100": 56, "clkpad7100000001000": 56, "clkr": 44, "clkt": [44, 59], "clock": [11, 12, 34, 35, 36, 37, 38, 41, 42, 43, 46, 51, 52, 55, 57, 60, 71, 80, 82], "clock_invert_m": 65, "clock_invert_p": 65, "clock_invert_pdsp1": 65, "clockwis": [44, 59], "close": [44, 51], "closest": 44, "cmo": 14, "cnr": [44, 59], "code": 35, "col": [2, 3, 4, 5, 6, 7, 8, 9, 72, 73, 74, 75, 76, 77], "col_hi": [15, 16], "col_lo": [15, 16], "coloc": [44, 51], "column": [2, 3, 4, 5, 6, 7, 8, 9, 15, 16, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 35, 38, 39, 42, 51, 52, 53, 56, 59, 70, 71, 72, 73, 74, 75, 76, 77, 79, 81], "comb": 36, "comb0": 15, "comb1": 16, "combin": [36, 38, 42, 51, 52, 56, 82], "combination": 51, "combinatori": [14, 36, 82], "come": [12, 34, 36, 38, 44, 51, 59, 80, 82], "commerci": [17, 71], "commonli": 70, "compat": [12, 34, 80], "compens": 52, "complet": [12, 13, 16, 34, 35, 36, 70, 80], "complex": [15, 16], "comput": [51, 70], "concaten": [15, 16, 51, 60], "conceptu": 44, "config": [15, 16, 70], "configur": [11, 12, 15, 33, 34, 35, 37, 39, 41, 42, 43, 50, 55, 56, 57, 59, 66, 70, 79], "configuraton": [15, 16], "conjunct": 36, "connect": [35, 36, 38, 44, 51, 52, 56, 57, 60, 81, 82], "consid": 35, "consist": [35, 36, 51], "const": [13, 14, 35, 36, 38, 52, 81, 82], "constant": [36, 38, 52], "constraint": 12, "construct": 82, "consult": 15, "contain": [15, 17, 34, 38, 42, 43, 44, 51, 52, 56, 57, 59, 60, 81, 82], "content": [35, 38, 52], "contigu": [15, 16], "continu": 35, "control": [12, 14, 35, 36, 38, 43, 52, 57, 60], "convert": [15, 16], "coolrunn": [0, 12, 14], "coordin": [16, 17, 36, 44, 59, 70, 71, 82], "core": [12, 34, 36, 42, 56, 57, 59, 80, 82], "corner": [37, 42, 43, 44, 55, 56, 57, 59], "correct": 60, "correspond": [12, 14, 15, 16, 17, 34, 35, 36, 38, 39, 40, 42, 44, 51, 52, 53, 56, 59, 60, 71, 82], "could": 35, "count": [2, 3, 4, 5, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 38, 44, 51, 59, 72, 73, 74, 75, 76, 77], "cout": [38, 52], "coutmux": 64, "coutmuxslice1": 64, "cover": 82, "cp132": [2, 3, 12], "cp56": [4, 5, 8, 9, 12, 73, 80], "cpld": [0, 12, 34, 36, 80, 82], "crammod": 64, "creat": [42, 56, 59], "creg": [40, 61, 65, 68], "cregdsp": 40, "cregdsp0": [65, 68], "cregdsp1": 68, "cross": [44, 56], "cs144": [20, 21, 34, 74, 80], "cs280": [24, 25, 34, 75, 80], "cs48": [26, 27, 28, 30, 31, 34, 72, 73, 80], "cso2pin": 54, "ct": 14, "ct4111": [2, 3, 4, 5, 6, 7, 8, 9], "ct501": [2, 3, 4, 5, 6, 7, 8, 9], "ct601": [2, 3, 4, 5, 6, 7, 8, 9], "ct70001": [2, 3, 4, 5, 6, 7, 8, 9], "ctc": 14, "cte": 14, "ctlgo001": 42, "ctlmode011": 42, "ctlosc1001": 42, "ctlosc2001": 42, "ctlsel0011": 42, "ctlsel1101": 42, "ctlsel2100": 42, "ctr": 14, "ctrl0": 67, "ctrl00001": 67, "ctrl1": 67, "ctrl10010": 67, "ctrl2": 67, "ctrl3": 67, "curious": [12, 34], "current": [35, 38, 52], "cut": [43, 44], "cv100": [2, 12], "cv64": [5, 9, 12], "cx0": 64, "cx0100": 64, "cx1": 64, "cx10": 64, "cx1010": 64, "cy0": 49, "cy0111": 64, "cy0f": [38, 52], "cy0g": [38, 52], "cy1010": 64, "cy110": 64, "cycl": [35, 51, 60], "cyinit": [38, 49, 52, 64], "cyinitslice0": [38, 49, 64], "cyinitslice1": [38, 49, 64], "cyinitslice2": 38, "cyinitslice3": 38, "cyself": [38, 49, 52], "cyselfslice0": 49, "cyselfslice1": [38, 49], "cyselfslice3": 38, "cyselg": [38, 49, 52], "cyselgslice0": [49, 52], "cyselgslice1": [38, 49, 52], "cyselgslice3": 38, "d": [14, 36, 51, 60, 82], "d0_mux": 68, "d1": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 72, 73, 74, 75, 76, 77, 82], "d10": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76, 77], "d10_mux": 68, "d11": [3, 6, 7, 20, 21, 22, 23, 24, 25, 74, 75, 76, 77], "d11_mux": 68, "d12": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 74, 75, 76, 77], "d12_mux": 68, "d13": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 74, 75, 76, 77], "d13_mux": 68, "d14": [2, 3, 6, 7, 22, 23, 24, 25, 75, 76, 77], "d14_mux": 68, "d15": [3, 6, 7, 22, 23, 24, 25, 75, 76, 77], "d15_mux": 68, "d16": [3, 6, 7, 22, 23, 24, 25, 75, 76, 77], "d16_mux": 68, "d17": [6, 7, 22, 23, 24, 25, 75, 76, 77], "d17_mux": 68, "d18": [6, 7, 22, 23, 24, 25, 75, 76, 77], "d18_mux": 68, "d19": [6, 7, 22, 23, 24, 25, 75, 76, 77], "d19_mux": 68, "d1_mux": 68, "d2": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 72, 73, 74, 75, 76, 77], "d20": [6, 7, 22, 23, 24, 76, 77], "d20_mux": 68, "d21": [6, 7, 22, 23, 76, 77], "d21_mux": 68, "d22": [6, 7, 22, 23, 76, 77], "d22_mux": 68, "d23": [22, 23], "d23_mux": 68, "d24": [22, 23], "d24_mux": 68, "d25": [22, 23], "d26": [22, 23], "d2_mux": 68, "d3": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 72, 73, 74, 75, 76, 77], "d3_mux": 68, "d4": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 72, 73, 74, 75, 76, 77], "d4_mux": 68, "d5": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 74, 75, 76, 77], "d5_mux": 68, "d5ffinit": 64, "d5ffinitslice0": 64, "d5ffmux": 64, "d5ffsr": 64, "d5ffsrinit": 64, "d5ffsrinitslice0": 64, "d5ffsrslice1": 64, "d5q0": 64, "d5q0100": 64, "d6": [2, 3, 5, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 72, 73, 74, 75, 76, 77], "d6_mux": 68, "d6lut": 64, "d7": [2, 3, 6, 7, 9, 20, 21, 22, 23, 24, 25, 26, 27, 28, 30, 31, 72, 73, 74, 75, 76, 77], "d7_mux": 68, "d8": [2, 3, 4, 5, 6, 7, 8, 9, 20, 21, 22, 23, 24, 25, 73, 74, 75, 76, 77], "d8_mux": 68, "d9": [2, 3, 6, 7, 20, 21, 22, 23, 24, 25, 74, 75, 76, 77], "d9_mux": 68, "data": [10, 12, 14, 17, 32, 35, 38, 40, 42, 44, 48, 51, 52, 56, 59, 60, 70, 71, 78, 82], "data0": [42, 56], "data00001000001": 56, "data00001000100": 56, "data00mux": 42, "data1": [42, 56], "data10": 42, "data10001000010": 56, "data10001001000": 56, "data101mux": 42, "data10mux": 42, "data11": 42, "data110mux": 42, "data11mux": 42, "data12": 42, "data13": 42, "data130mux": 42, "data131mux": 42, "data14": 42, "data140mux": 42, "data15": 42, "data16": 42, "data160mux": 42, "data17": 42, "data170mux": 42, "data171mux": 42, "data18": 42, "data180mux": 42, "data181mux": 42, "data19": 42, "data190mux": 42, "data2": [42, 56], "data20": 42, "data20001000100": 56, "data20001010000": 56, "data20mux": 42, "data21": 42, "data210mux": 42, "data21mux": 42, "data22": 42, "data220mux": 42, "data221mux": 42, "data23": 42, "data24": 42, "data240mux": 42, "data25": 42, "data250mux": 42, "data251mux": 42, "data26": 42, "data261mux": 42, "data27": 42, "data270mux": 42, "data28": 42, "data29": 42, "data290mux": 42, "data3": [42, 56], "data30": 42, "data30001001000": 56, "data30001100000": 56, "data300mux": 42, "data301mux": 42, "data30mux": 42, "data31": 42, "data4": [42, 56], "data40001000001": 56, "data40001000010": 56, "data40001000100": 56, "data5": [42, 56], "data50001000010": 56, "data50001000100": 56, "data50001001000": 56, "data50mux": 42, "data51mux": 42, "data6": [42, 56], "data60001000100": 56, "data60001001000": 56, "data60001010000": 56, "data60mux": 42, "data7": [42, 56], "data70001001000": 56, "data70001010000": 56, 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18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 73, 74, 75, 76, 77], "p99": [2, 3, 6, 7, 8, 9, 18, 19, 20, 21, 22, 23, 24, 25, 29, 30, 31, 73, 74, 75, 76, 77], "p_d": 51, "packag": [11, 17, 33, 36, 43, 71, 79, 81], "pad": [2, 3, 4, 5, 6, 7, 8, 9, 12, 14, 15, 16, 17, 34, 36, 42, 56, 71, 80, 82], "pair": [17, 44, 52, 60, 71], "parallel": 16, "paramet": [2, 3, 4, 5, 6, 7, 8, 9, 17, 18, 19, 20, 21, 22, 23, 24, 25, 26, 27, 28, 29, 30, 31, 71, 72, 73, 74, 75, 76, 77], "pariti": [51, 60], "part": [2, 3, 4, 5, 6, 7, 8, 9, 12, 33, 34, 38, 44, 52, 60, 72, 73, 74, 75, 76, 77, 79, 81], "partial": [34, 51, 60, 81], "particip": 36, "particular": [17, 71], "particularli": 38, "pass": [35, 42, 44, 56], "passthrough": 56, "patdet1": 65, "path": [36, 51], "pattern": [59, 65, 68], "pattern0": [65, 68], "pc44": [4, 5, 8, 9, 12, 26, 27, 28, 29, 30, 31, 34, 72, 73, 80], "pc84": [18, 29, 34], "pci": [43, 44, 55, 56, 57], "pci000": 56, "pci100": 56, "pcice10": 58, "pcice_mux": 58, "pcilog": [44, 55, 56, 59], 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diff --git a/xilinx/index.html b/xilinx/index.html
index 97c72abe..39762939 100644
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@@ -62,6 +62,7 @@
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 <li class="toctree-l3"><a class="reference internal" href="bram.html">Block RAM — Virtex 2, Spartan 3</a></li>
 <li class="toctree-l3"><a class="reference internal" href="clock.html">Clock interconnect</a></li>
+<li class="toctree-l3"><a class="reference internal" href="io.html">Input / Output — Virtex 2, Spartan 3</a></li>
 <li class="toctree-l3"><a class="reference internal" href="corner.html">Corners — Virtex 2, Spartan 3</a></li>
 </ul>
 </li>
@@ -112,7 +113,7 @@
 <ul class="simple">
 <li><p><code class="docutils literal notranslate"><span class="pre">INT.CLB</span></code>, the interconnect tile associated with <a class="reference internal" href="clb.html#virtex2-clb"><span class="std std-ref">configurable logic blocks</span></a></p></li>
 <li><p><code class="docutils literal notranslate"><span class="pre">INT.BRAM</span></code>, the interconnect tile associated with <a class="reference internal" href="bram.html#virtex2-bram"><span class="std std-ref">block RAMs</span></a></p></li>
-<li><p><code class="docutils literal notranslate"><span class="pre">INT.{IOI|IOI.CLK_B|IOI.CLK_T}</span></code>, the interconnect tile associated with <span class="xref std std-ref">I/O tiles</span></p></li>
+<li><p><code class="docutils literal notranslate"><span class="pre">INT.{IOI|IOI.CLK_B|IOI.CLK_T}</span></code>, the interconnect tile associated with <a class="reference internal" href="io.html#virtex2-io"><span class="std std-ref">I/O tiles</span></a></p></li>
 <li><p><code class="docutils literal notranslate"><span class="pre">INT.DCM.{V2|V2P}</span></code>, the interconnect tiles associated with <span class="xref std std-ref">digital clock managers</span></p></li>
 <li><p><code class="docutils literal notranslate"><span class="pre">INT.CNR</span></code>, the interconnect tile associated with <a class="reference internal" href="corner.html#virtex2-corner"><span class="std std-ref">corner tiles</span></a></p></li>
 <li><p><code class="docutils literal notranslate"><span class="pre">INT.PPC</span></code>, the interconnect tile associated with <span class="xref std std-ref">PowerPC cores</span> and multi-gigabit transceivers</p></li>
diff --git a/xilinx/virtex2/intro.html b/xilinx/virtex2/intro.html
index 5c597931..6ec12302 100644
--- a/xilinx/virtex2/intro.html
+++ b/xilinx/virtex2/intro.html
@@ -59,6 +59,7 @@
 <li class="toctree-l3"><a class="reference internal" href="clb.html">Configurable Logic Block</a></li>
 <li class="toctree-l3"><a class="reference internal" href="bram.html">Block RAM — Virtex 2, Spartan 3</a></li>
 <li class="toctree-l3"><a class="reference internal" href="clock.html">Clock interconnect</a></li>
+<li class="toctree-l3"><a class="reference internal" href="io.html">Input / Output — Virtex 2, Spartan 3</a></li>
 <li class="toctree-l3"><a class="reference internal" href="corner.html">Corners — Virtex 2, Spartan 3</a></li>
 </ul>
 </li>
@@ -117,7 +118,7 @@
 <li><p>18×18 multiplier blocks</p></li>
 </ul>
 </li>
-<li><p>new <span class="xref std std-ref">input-output tiles</span>, with DDR register and DCI (digitally controlled impedance) support</p></li>
+<li><p>new <a class="reference internal" href="io.html#virtex2-io"><span class="std std-ref">input-output tiles</span></a>, with DDR register and DCI (digitally controlled impedance) support</p></li>
 <li><p>new <span class="xref std std-ref">digital clock managers</span>, a new version of the <span class="xref std std-ref">Virtex DLLs</span> with added frequency synthesis capability</p></li>
 <li><p><a class="reference internal" href="corner.html#virtex2-corner"><span class="std std-ref">corner tiles</span></a>, with various global bits of logic:</p>
 <ul>
diff --git a/xilinx/virtex2/io.html b/xilinx/virtex2/io.html
new file mode 100644
index 00000000..908244fa
--- /dev/null
+++ b/xilinx/virtex2/io.html
@@ -0,0 +1,6558 @@
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+<li class="toctree-l1"><a class="reference internal" href="../../xc9500/index.html">Xilinx XC9500, XC9500XL, XC9500XV CPLDs</a></li>
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+<li class="toctree-l3"><a class="reference internal" href="structure.html">Device geometry</a></li>
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+  <section id="input-output-virtex-2-spartan-3">
+<span id="virtex2-io"></span><h1>Input / Output — Virtex 2, Spartan 3<a class="headerlink" href="#input-output-virtex-2-spartan-3" title="Link to this heading"></a></h1>
+<div class="admonition-todo admonition" id="id1">
+<p class="admonition-title">Todo</p>
+<p>document</p>
+</div>
+<section id="i-o-interface">
+<h2>I/O interface<a class="headerlink" href="#i-o-interface" title="Link to this heading"></a></h2>
+<div class="admonition-todo admonition" id="id2">
+<p class="admonition-title">Todo</p>
+<p>document</p>
+</div>
+<section id="ioi-virtex-2">
+<h3><code class="docutils literal notranslate"><span class="pre">IOI</span></code> — Virtex 2<a class="headerlink" href="#ioi-virtex-2" title="Link to this heading"></a></h3>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:ICLK2INV" title="~IOI0:ICLK2INV">~IOI0:ICLK2INV</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:OFF1_SRVAL" title="~IOI0:OFF1_SRVAL">~IOI0:OFF1_SRVAL</a></td></tr>
+<tr><td>2</td>
+<td><a href="#bits-xc2v-IOI-IOI0:IFF1_SRVAL" title="~IOI0:IFF1_SRVAL">~IOI0:IFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI-IOI0:IFF_SR_EN" title="IOI0:IFF_SR_EN">IOI0:IFF_SR_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:REVINV" title="~IOI0:REVINV">~IOI0:REVINV</a></td></tr>
+<tr><td>3</td>
+<td><a href="#bits-xc2v-IOI-IOI0:TSBYPASS_MUX" title="IOI0:TSBYPASS_MUX">IOI0:TSBYPASS_MUX</a></td><td><a href="#bits-xc2v-IOI-IOI0:IFF_REV_EN" title="IOI0:IFF_REV_EN">IOI0:IFF_REV_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:OMUX" title="IOI0:OMUX[2]">IOI0:OMUX[2]</a></td></tr>
+<tr><td>4</td>
+<td><a href="#bits-xc2v-IOI-IOI0:I_DELAY_EN" title="IOI0:I_DELAY_EN">IOI0:I_DELAY_EN</a></td><td><a href="#bits-xc2v-IOI-IOI0:TFF_REV_EN" title="IOI0:TFF_REV_EN">IOI0:TFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI-IOI0:OFF_REV_EN" title="IOI0:OFF_REV_EN">IOI0:OFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI-IOI0:TCEINV" title="~IOI0:TCEINV">~IOI0:TCEINV</a></td></tr>
+<tr><td>5</td>
+<td><a href="#bits-xc2v-IOI-IOI0:TFF1_SRVAL" title="~IOI0:TFF1_SRVAL">~IOI0:TFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI-IOI0:TFF_SR_EN" title="IOI0:TFF_SR_EN">IOI0:TFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI-IOI0:OFF_SR_EN" title="IOI0:OFF_SR_EN">IOI0:OFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI-IOI0:OMUX" title="IOI0:OMUX[0]">IOI0:OMUX[0]</a></td></tr>
+<tr><td>6</td>
+<td><a href="#bits-xc2v-IOI-IOI0:I_TSBYPASS_EN" title="IOI0:I_TSBYPASS_EN">IOI0:I_TSBYPASS_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:ICEINV" title="~IOI0:ICEINV">~IOI0:ICEINV</a></td></tr>
+<tr><td>7</td>
+<td><a href="#bits-xc2v-IOI-IOI0:TMUX" title="IOI0:TMUX[0]">IOI0:TMUX[0]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:OFF1_LATCH" title="IOI0:OFF1_LATCH">IOI0:OFF1_LATCH</a></td></tr>
+<tr><td>8</td>
+<td><a href="#bits-xc2v-IOI-IOI0:TMUX" title="IOI0:TMUX[2]">IOI0:TMUX[2]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:ICLK1INV" title="~IOI0:ICLK1INV">~IOI0:ICLK1INV</a></td></tr>
+<tr><td>9</td>
+<td><a href="#bits-xc2v-IOI-IOI0:IFF_TSBYPASS_EN" title="IOI0:IFF_TSBYPASS_EN">IOI0:IFF_TSBYPASS_EN</a></td><td><a href="#bits-xc2v-IOI-IOI0:IFF1_INIT" title="~IOI0:IFF1_INIT">~IOI0:IFF1_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:OTCLK2INV" title="~IOI0:OTCLK2INV">~IOI0:OTCLK2INV</a></td></tr>
+<tr><td>10</td>
+<td><a href="#bits-xc2v-IOI-IOI0:OFF_SYNC" title="IOI0:OFF_SYNC">IOI0:OFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:OMUX" title="IOI0:OMUX[1]">IOI0:OMUX[1]</a></td></tr>
+<tr><td>11</td>
+<td><a href="#bits-xc2v-IOI-IOI0:IFF_DELAY_EN" title="IOI0:IFF_DELAY_EN">IOI0:IFF_DELAY_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:O1INV" title="IOI0:O1INV">IOI0:O1INV</a></td></tr>
+<tr><td>12</td>
+<td><a href="#bits-xc2v-IOI-IOI0:TFF_SYNC" title="IOI0:TFF_SYNC">IOI0:TFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:OMUX" title="IOI0:OMUX[3]">IOI0:OMUX[3]</a></td></tr>
+<tr><td>13</td>
+<td><a href="#bits-xc2v-IOI-IOI0:IFF_SYNC" title="IOI0:IFF_SYNC">IOI0:IFF_SYNC</a></td><td><a href="#bits-xc2v-IOI-IOI0:IFF2_INIT" title="~IOI0:IFF2_INIT">~IOI0:IFF2_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:O2INV" title="IOI0:O2INV">IOI0:O2INV</a></td></tr>
+<tr><td>14</td>
+<td><a href="#bits-xc2v-IOI-IOI0:TMUX" title="IOI0:TMUX[3]">IOI0:TMUX[3]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:OFF2_LATCH" title="IOI0:OFF2_LATCH">IOI0:OFF2_LATCH</a></td></tr>
+<tr><td>15</td>
+<td><a href="#bits-xc2v-IOI-IOI0:TMUX" title="IOI0:TMUX[1]">IOI0:TMUX[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:T1INV" title="IOI0:T1INV">IOI0:T1INV</a></td></tr>
+<tr><td>16</td>
+<td><a href="#bits-xc2v-IOI-IOI0:IFF_LATCH" title="IOI0:IFF_LATCH">IOI0:IFF_LATCH</a></td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>17</td>
+<td><a href="#bits-xc2v-IOI-IOI0:TFF2_LATCH" title="IOI0:TFF2_LATCH">IOI0:TFF2_LATCH</a></td><td><a href="#bits-xc2v-IOI-IOI0:TFF_INIT" title="~IOI0:TFF_INIT">~IOI0:TFF_INIT</a></td><td><a href="#bits-xc2v-IOI-IOI0:OFF_INIT" title="~IOI0:OFF_INIT">~IOI0:OFF_INIT</a></td><td><a href="#bits-xc2v-IOI-IOI0:T2INV" title="IOI0:T2INV">IOI0:T2INV</a></td></tr>
+<tr><td>18</td>
+<td><a href="#bits-xc2v-IOI-IOI1:TFF1_LATCH" title="IOI1:TFF1_LATCH">IOI1:TFF1_LATCH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:OFF2_SRVAL" title="~IOI0:OFF2_SRVAL">~IOI0:OFF2_SRVAL</a></td></tr>
+<tr><td>19</td>
+<td><a href="#bits-xc2v-IOI-IOI0:TFF2_SRVAL" title="~IOI0:TFF2_SRVAL">~IOI0:TFF2_SRVAL</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI0:OTCLK1INV" title="~IOI0:OTCLK1INV">~IOI0:OTCLK1INV</a></td></tr>
+<tr><td>20</td>
+<td><a href="#bits-xc2v-IOI-IOI0:IFF2_SRVAL" title="~IOI0:IFF2_SRVAL">~IOI0:IFF2_SRVAL</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:ICLK2INV" title="~IOI1:ICLK2INV">~IOI1:ICLK2INV</a></td></tr>
+<tr><td>21</td>
+<td><a href="#bits-xc2v-IOI-IOI1:IFF1_SRVAL" title="~IOI1:IFF1_SRVAL">~IOI1:IFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI-IOI1:IFF_SR_EN" title="IOI1:IFF_SR_EN">IOI1:IFF_SR_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:OFF1_SRVAL" title="~IOI1:OFF1_SRVAL">~IOI1:OFF1_SRVAL</a></td></tr>
+<tr><td>22</td>
+<td><a href="#bits-xc2v-IOI-IOI1:TFF1_SRVAL" title="~IOI1:TFF1_SRVAL">~IOI1:TFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI-IOI1:IFF_REV_EN" title="IOI1:IFF_REV_EN">IOI1:IFF_REV_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:REVINV" title="~IOI1:REVINV">~IOI1:REVINV</a></td></tr>
+<tr><td>23</td>
+<td><a href="#bits-xc2v-IOI-IOI1:TSBYPASS_MUX" title="IOI1:TSBYPASS_MUX">IOI1:TSBYPASS_MUX</a></td><td><a href="#bits-xc2v-IOI-IOI1:TFF_REV_EN" title="IOI1:TFF_REV_EN">IOI1:TFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI-IOI1:OFF_REV_EN" title="IOI1:OFF_REV_EN">IOI1:OFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI-IOI1:OMUX" title="IOI1:OMUX[2]">IOI1:OMUX[2]</a></td></tr>
+<tr><td>24</td>
+<td><a href="#bits-xc2v-IOI-IOI1:I_DELAY_EN" title="IOI1:I_DELAY_EN">IOI1:I_DELAY_EN</a></td><td><a href="#bits-xc2v-IOI-IOI1:TFF_SR_EN" title="IOI1:TFF_SR_EN">IOI1:TFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI-IOI1:OFF_SR_EN" title="IOI1:OFF_SR_EN">IOI1:OFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI-IOI1:TCEINV" title="~IOI1:TCEINV">~IOI1:TCEINV</a></td></tr>
+<tr><td>25</td>
+<td><a href="#bits-xc2v-IOI-IOI1:TMUX" title="IOI1:TMUX[0]">IOI1:TMUX[0]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:OMUX" title="IOI1:OMUX[0]">IOI1:OMUX[0]</a></td></tr>
+<tr><td>26</td>
+<td><a href="#bits-xc2v-IOI-IOI1:I_TSBYPASS_EN" title="IOI1:I_TSBYPASS_EN">IOI1:I_TSBYPASS_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:ICEINV" title="~IOI1:ICEINV">~IOI1:ICEINV</a></td></tr>
+<tr><td>27</td>
+<td><a href="#bits-xc2v-IOI-IOI1:TMUX" title="IOI1:TMUX[2]">IOI1:TMUX[2]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:OFF1_LATCH" title="IOI1:OFF1_LATCH">IOI1:OFF1_LATCH</a></td></tr>
+<tr><td>28</td>
+<td><a href="#bits-xc2v-IOI-IOI1:OFF_SYNC" title="IOI1:OFF_SYNC">IOI1:OFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:ICLK1INV" title="~IOI1:ICLK1INV">~IOI1:ICLK1INV</a></td></tr>
+<tr><td>29</td>
+<td><a href="#bits-xc2v-IOI-IOI1:IFF_TSBYPASS_EN" title="IOI1:IFF_TSBYPASS_EN">IOI1:IFF_TSBYPASS_EN</a></td><td><a href="#bits-xc2v-IOI-IOI1:IFF1_INIT" title="~IOI1:IFF1_INIT">~IOI1:IFF1_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:OTCLK2INV" title="~IOI1:OTCLK2INV">~IOI1:OTCLK2INV</a></td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc2v-IOI-IOI1:TFF_SYNC" title="IOI1:TFF_SYNC">IOI1:TFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:OMUX" title="IOI1:OMUX[1]">IOI1:OMUX[1]</a></td></tr>
+<tr><td>31</td>
+<td><a href="#bits-xc2v-IOI-IOI1:IFF_DELAY_EN" title="IOI1:IFF_DELAY_EN">IOI1:IFF_DELAY_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:O1INV" title="IOI1:O1INV">IOI1:O1INV</a></td></tr>
+<tr><td>32</td>
+<td><a href="#bits-xc2v-IOI-IOI1:IFF_SYNC" title="IOI1:IFF_SYNC">IOI1:IFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:OMUX" title="IOI1:OMUX[3]">IOI1:OMUX[3]</a></td></tr>
+<tr><td>33</td>
+<td><a href="#bits-xc2v-IOI-IOI1:TMUX" title="IOI1:TMUX[3]">IOI1:TMUX[3]</a></td><td><a href="#bits-xc2v-IOI-IOI1:IFF2_INIT" title="~IOI1:IFF2_INIT">~IOI1:IFF2_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:O2INV" title="IOI1:O2INV">IOI1:O2INV</a></td></tr>
+<tr><td>34</td>
+<td><a href="#bits-xc2v-IOI-IOI0:TFF1_LATCH" title="IOI0:TFF1_LATCH">IOI0:TFF1_LATCH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:OFF2_LATCH" title="IOI1:OFF2_LATCH">IOI1:OFF2_LATCH</a></td></tr>
+<tr><td>35</td>
+<td><a href="#bits-xc2v-IOI-IOI1:IFF_LATCH" title="IOI1:IFF_LATCH">IOI1:IFF_LATCH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:T1INV" title="IOI1:T1INV">IOI1:T1INV</a></td></tr>
+<tr><td>36</td>
+<td><a href="#bits-xc2v-IOI-IOI1:TMUX" title="IOI1:TMUX[1]">IOI1:TMUX[1]</a></td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>37</td>
+<td><a href="#bits-xc2v-IOI-IOI1:TFF2_LATCH" title="IOI1:TFF2_LATCH">IOI1:TFF2_LATCH</a></td><td><a href="#bits-xc2v-IOI-IOI1:TFF_INIT" title="~IOI1:TFF_INIT">~IOI1:TFF_INIT</a></td><td><a href="#bits-xc2v-IOI-IOI1:OFF_INIT" title="~IOI1:OFF_INIT">~IOI1:OFF_INIT</a></td><td><a href="#bits-xc2v-IOI-IOI1:T2INV" title="IOI1:T2INV">IOI1:T2INV</a></td></tr>
+<tr><td>38</td>
+<td><a href="#bits-xc2v-IOI-IOI1:TFF2_SRVAL" title="~IOI1:TFF2_SRVAL">~IOI1:TFF2_SRVAL</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:OFF2_SRVAL" title="~IOI1:OFF2_SRVAL">~IOI1:OFF2_SRVAL</a></td></tr>
+<tr><td>39</td>
+<td><a href="#bits-xc2v-IOI-IOI1:IFF2_SRVAL" title="~IOI1:IFF2_SRVAL">~IOI1:IFF2_SRVAL</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI1:OTCLK1INV" title="~IOI1:OTCLK1INV">~IOI1:OTCLK1INV</a></td></tr>
+<tr><td>40</td>
+<td><a href="#bits-xc2v-IOI-IOI2:IFF1_SRVAL" title="~IOI2:IFF1_SRVAL">~IOI2:IFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI-IOI2:IFF_SR_EN" title="IOI2:IFF_SR_EN">IOI2:IFF_SR_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:ICLK2INV" title="~IOI2:ICLK2INV">~IOI2:ICLK2INV</a></td></tr>
+<tr><td>41</td>
+<td><a href="#bits-xc2v-IOI-IOI2:TFF1_LATCH" title="IOI2:TFF1_LATCH">IOI2:TFF1_LATCH</a></td><td><a href="#bits-xc2v-IOI-IOI2:IFF_REV_EN" title="IOI2:IFF_REV_EN">IOI2:IFF_REV_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:OFF1_SRVAL" title="~IOI2:OFF1_SRVAL">~IOI2:OFF1_SRVAL</a></td></tr>
+<tr><td>42</td>
+<td><a href="#bits-xc2v-IOI-IOI2:TFF1_SRVAL" title="~IOI2:TFF1_SRVAL">~IOI2:TFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI-IOI2:TFF_REV_EN" title="IOI2:TFF_REV_EN">IOI2:TFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI-IOI2:OFF_REV_EN" title="IOI2:OFF_REV_EN">IOI2:OFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI-IOI2:REVINV" title="~IOI2:REVINV">~IOI2:REVINV</a></td></tr>
+<tr><td>43</td>
+<td><a href="#bits-xc2v-IOI-IOI2:TSBYPASS_MUX" title="IOI2:TSBYPASS_MUX">IOI2:TSBYPASS_MUX</a></td><td><a href="#bits-xc2v-IOI-IOI2:TFF_SR_EN" title="IOI2:TFF_SR_EN">IOI2:TFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI-IOI2:OFF_SR_EN" title="IOI2:OFF_SR_EN">IOI2:OFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI-IOI2:OMUX" title="IOI2:OMUX[2]">IOI2:OMUX[2]</a></td></tr>
+<tr><td>44</td>
+<td><a href="#bits-xc2v-IOI-IOI2:I_DELAY_EN" title="IOI2:I_DELAY_EN">IOI2:I_DELAY_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:TCEINV" title="~IOI2:TCEINV">~IOI2:TCEINV</a></td></tr>
+<tr><td>45</td>
+<td><a href="#bits-xc2v-IOI-IOI2:TMUX" title="IOI2:TMUX[0]">IOI2:TMUX[0]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:OMUX" title="IOI2:OMUX[0]">IOI2:OMUX[0]</a></td></tr>
+<tr><td>46</td>
+<td><a href="#bits-xc2v-IOI-IOI2:I_TSBYPASS_EN" title="IOI2:I_TSBYPASS_EN">IOI2:I_TSBYPASS_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:ICEINV" title="~IOI2:ICEINV">~IOI2:ICEINV</a></td></tr>
+<tr><td>47</td>
+<td><a href="#bits-xc2v-IOI-IOI2:TMUX" title="IOI2:TMUX[2]">IOI2:TMUX[2]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:OFF1_LATCH" title="IOI2:OFF1_LATCH">IOI2:OFF1_LATCH</a></td></tr>
+<tr><td>48</td>
+<td><a href="#bits-xc2v-IOI-IOI2:OFF_SYNC" title="IOI2:OFF_SYNC">IOI2:OFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:ICLK1INV" title="~IOI2:ICLK1INV">~IOI2:ICLK1INV</a></td></tr>
+<tr><td>49</td>
+<td><a href="#bits-xc2v-IOI-IOI2:IFF_TSBYPASS_EN" title="IOI2:IFF_TSBYPASS_EN">IOI2:IFF_TSBYPASS_EN</a></td><td><a href="#bits-xc2v-IOI-IOI2:IFF1_INIT" title="~IOI2:IFF1_INIT">~IOI2:IFF1_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:OTCLK2INV" title="~IOI2:OTCLK2INV">~IOI2:OTCLK2INV</a></td></tr>
+<tr><td>50</td>
+<td><a href="#bits-xc2v-IOI-IOI2:TFF_SYNC" title="IOI2:TFF_SYNC">IOI2:TFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:OMUX" title="IOI2:OMUX[1]">IOI2:OMUX[1]</a></td></tr>
+<tr><td>51</td>
+<td><a href="#bits-xc2v-IOI-IOI2:IFF_DELAY_EN" title="IOI2:IFF_DELAY_EN">IOI2:IFF_DELAY_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:O1INV" title="IOI2:O1INV">IOI2:O1INV</a></td></tr>
+<tr><td>52</td>
+<td><a href="#bits-xc2v-IOI-IOI2:IFF_SYNC" title="IOI2:IFF_SYNC">IOI2:IFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:OMUX" title="IOI2:OMUX[3]">IOI2:OMUX[3]</a></td></tr>
+<tr><td>53</td>
+<td><a href="#bits-xc2v-IOI-IOI2:TMUX" title="IOI2:TMUX[3]">IOI2:TMUX[3]</a></td><td><a href="#bits-xc2v-IOI-IOI2:IFF2_INIT" title="~IOI2:IFF2_INIT">~IOI2:IFF2_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:O2INV" title="IOI2:O2INV">IOI2:O2INV</a></td></tr>
+<tr><td>54</td>
+<td><a href="#bits-xc2v-IOI-IOI2:IFF_LATCH" title="IOI2:IFF_LATCH">IOI2:IFF_LATCH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:OFF2_LATCH" title="IOI2:OFF2_LATCH">IOI2:OFF2_LATCH</a></td></tr>
+<tr><td>55</td>
+<td><a href="#bits-xc2v-IOI-IOI2:TMUX" title="IOI2:TMUX[1]">IOI2:TMUX[1]</a></td><td><a href="#bits-xc2v-IOI-IOI2:TFF_INIT" title="~IOI2:TFF_INIT">~IOI2:TFF_INIT</a></td><td><a href="#bits-xc2v-IOI-IOI2:OFF_INIT" title="~IOI2:OFF_INIT">~IOI2:OFF_INIT</a></td><td><a href="#bits-xc2v-IOI-IOI2:T1INV" title="IOI2:T1INV">IOI2:T1INV</a></td></tr>
+<tr><td>56</td>
+<td><a href="#bits-xc2v-IOI-IOI2:TFF2_LATCH" title="IOI2:TFF2_LATCH">IOI2:TFF2_LATCH</a></td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>57</td>
+<td><a href="#bits-xc2v-IOI-IOI2:TFF2_SRVAL" title="~IOI2:TFF2_SRVAL">~IOI2:TFF2_SRVAL</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:T2INV" title="IOI2:T2INV">IOI2:T2INV</a></td></tr>
+<tr><td>58</td>
+<td><a href="#bits-xc2v-IOI-IOI2:IFF2_SRVAL" title="~IOI2:IFF2_SRVAL">~IOI2:IFF2_SRVAL</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:OFF2_SRVAL" title="~IOI2:OFF2_SRVAL">~IOI2:OFF2_SRVAL</a></td></tr>
+<tr><td>59</td>
+<td><a href="#bits-xc2v-IOI-IOI3:IFF1_SRVAL" title="~IOI3:IFF1_SRVAL">~IOI3:IFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI-IOI3:IFF_SR_EN" title="IOI3:IFF_SR_EN">IOI3:IFF_SR_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI2:OTCLK1INV" title="~IOI2:OTCLK1INV">~IOI2:OTCLK1INV</a></td></tr>
+<tr><td>60</td>
+<td><a href="#bits-xc2v-IOI-IOI3:TFF1_SRVAL" title="~IOI3:TFF1_SRVAL">~IOI3:TFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI-IOI3:IFF_REV_EN" title="IOI3:IFF_REV_EN">IOI3:IFF_REV_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:ICLK2INV" title="~IOI3:ICLK2INV">~IOI3:ICLK2INV</a></td></tr>
+<tr><td>61</td>
+<td><a href="#bits-xc2v-IOI-IOI3:TMUX" title="IOI3:TMUX[0]">IOI3:TMUX[0]</a></td><td><a href="#bits-xc2v-IOI-IOI3:TFF_REV_EN" title="IOI3:TFF_REV_EN">IOI3:TFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI-IOI3:OFF_REV_EN" title="IOI3:OFF_REV_EN">IOI3:OFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI-IOI3:OFF1_SRVAL" title="~IOI3:OFF1_SRVAL">~IOI3:OFF1_SRVAL</a></td></tr>
+<tr><td>62</td>
+<td><a href="#bits-xc2v-IOI-IOI3:TFF1_LATCH" title="IOI3:TFF1_LATCH">IOI3:TFF1_LATCH</a></td><td><a href="#bits-xc2v-IOI-IOI3:TFF_SR_EN" title="IOI3:TFF_SR_EN">IOI3:TFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI-IOI3:OFF_SR_EN" title="IOI3:OFF_SR_EN">IOI3:OFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI-IOI3:REVINV" title="~IOI3:REVINV">~IOI3:REVINV</a></td></tr>
+<tr><td>63</td>
+<td><a href="#bits-xc2v-IOI-IOI3:TSBYPASS_MUX" title="IOI3:TSBYPASS_MUX">IOI3:TSBYPASS_MUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:OMUX" title="IOI3:OMUX[2]">IOI3:OMUX[2]</a></td></tr>
+<tr><td>64</td>
+<td><a href="#bits-xc2v-IOI-IOI3:I_DELAY_EN" title="IOI3:I_DELAY_EN">IOI3:I_DELAY_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:TCEINV" title="~IOI3:TCEINV">~IOI3:TCEINV</a></td></tr>
+<tr><td>65</td>
+<td><a href="#bits-xc2v-IOI-IOI3:TMUX" title="IOI3:TMUX[2]">IOI3:TMUX[2]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:OMUX" title="IOI3:OMUX[0]">IOI3:OMUX[0]</a></td></tr>
+<tr><td>66</td>
+<td><a href="#bits-xc2v-IOI-IOI3:I_TSBYPASS_EN" title="IOI3:I_TSBYPASS_EN">IOI3:I_TSBYPASS_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:ICEINV" title="~IOI3:ICEINV">~IOI3:ICEINV</a></td></tr>
+<tr><td>67</td>
+<td><a href="#bits-xc2v-IOI-IOI3:OFF_SYNC" title="IOI3:OFF_SYNC">IOI3:OFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:OFF1_LATCH" title="IOI3:OFF1_LATCH">IOI3:OFF1_LATCH</a></td></tr>
+<tr><td>68</td>
+<td><a href="#bits-xc2v-IOI-IOI3:TFF_SYNC" title="IOI3:TFF_SYNC">IOI3:TFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:ICLK1INV" title="~IOI3:ICLK1INV">~IOI3:ICLK1INV</a></td></tr>
+<tr><td>69</td>
+<td><a href="#bits-xc2v-IOI-IOI3:IFF_TSBYPASS_EN" title="IOI3:IFF_TSBYPASS_EN">IOI3:IFF_TSBYPASS_EN</a></td><td><a href="#bits-xc2v-IOI-IOI3:IFF1_INIT" title="~IOI3:IFF1_INIT">~IOI3:IFF1_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:OTCLK2INV" title="~IOI3:OTCLK2INV">~IOI3:OTCLK2INV</a></td></tr>
+<tr><td>70</td>
+<td><a href="#bits-xc2v-IOI-IOI3:IFF_SYNC" title="IOI3:IFF_SYNC">IOI3:IFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:OMUX" title="IOI3:OMUX[1]">IOI3:OMUX[1]</a></td></tr>
+<tr><td>71</td>
+<td><a href="#bits-xc2v-IOI-IOI3:IFF_DELAY_EN" title="IOI3:IFF_DELAY_EN">IOI3:IFF_DELAY_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:O1INV" title="IOI3:O1INV">IOI3:O1INV</a></td></tr>
+<tr><td>72</td>
+<td><a href="#bits-xc2v-IOI-IOI3:TMUX" title="IOI3:TMUX[3]">IOI3:TMUX[3]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:OMUX" title="IOI3:OMUX[3]">IOI3:OMUX[3]</a></td></tr>
+<tr><td>73</td>
+<td><a href="#bits-xc2v-IOI-IOI3:IFF_LATCH" title="IOI3:IFF_LATCH">IOI3:IFF_LATCH</a></td><td><a href="#bits-xc2v-IOI-IOI3:IFF2_INIT" title="~IOI3:IFF2_INIT">~IOI3:IFF2_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:O2INV" title="IOI3:O2INV">IOI3:O2INV</a></td></tr>
+<tr><td>74</td>
+<td><a href="#bits-xc2v-IOI-IOI3:TMUX" title="IOI3:TMUX[1]">IOI3:TMUX[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:OFF2_LATCH" title="IOI3:OFF2_LATCH">IOI3:OFF2_LATCH</a></td></tr>
+<tr><td>75</td>
+<td><a href="#bits-xc2v-IOI-IOI3:TFF2_LATCH" title="IOI3:TFF2_LATCH">IOI3:TFF2_LATCH</a></td><td><a href="#bits-xc2v-IOI-IOI3:TFF_INIT" title="~IOI3:TFF_INIT">~IOI3:TFF_INIT</a></td><td><a href="#bits-xc2v-IOI-IOI3:OFF_INIT" title="~IOI3:OFF_INIT">~IOI3:OFF_INIT</a></td><td><a href="#bits-xc2v-IOI-IOI3:T1INV" title="IOI3:T1INV">IOI3:T1INV</a></td></tr>
+<tr><td>76</td>
+<td><a href="#bits-xc2v-IOI-IOI3:TFF2_SRVAL" title="~IOI3:TFF2_SRVAL">~IOI3:TFF2_SRVAL</a></td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>77</td>
+<td><a href="#bits-xc2v-IOI-IOI3:IFF2_SRVAL" title="~IOI3:IFF2_SRVAL">~IOI3:IFF2_SRVAL</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:T2INV" title="IOI3:T2INV">IOI3:T2INV</a></td></tr>
+<tr><td>78</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:OFF2_SRVAL" title="~IOI3:OFF2_SRVAL">~IOI3:OFF2_SRVAL</a></td></tr>
+<tr><td>79</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI-IOI3:OTCLK1INV" title="~IOI3:OTCLK1INV">~IOI3:OTCLK1INV</a></td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:IFF1_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI1:IFF1_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI2:IFF1_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI3:IFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_SRVAL</th><th>[0, 0, 2]</th></tr>
+<tr><th>IOI1:IFF1_SRVAL</th><th>[0, 0, 21]</th></tr>
+<tr><th>IOI2:IFF1_SRVAL</th><th>[0, 0, 40]</th></tr>
+<tr><th>IOI3:IFF1_SRVAL</th><th>[0, 0, 59]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:TSBYPASS_MUX"></div>
+<div id="bits-xc2v-IOI-IOI1:TSBYPASS_MUX"></div>
+<div id="bits-xc2v-IOI-IOI2:TSBYPASS_MUX"></div>
+<div id="bits-xc2v-IOI-IOI3:TSBYPASS_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TSBYPASS_MUX</th><th>[0, 0, 3]</th></tr>
+<tr><th>IOI1:TSBYPASS_MUX</th><th>[0, 0, 23]</th></tr>
+<tr><th>IOI2:TSBYPASS_MUX</th><th>[0, 0, 43]</th></tr>
+<tr><th>IOI3:TSBYPASS_MUX</th><th>[0, 0, 63]</th></tr>
+<tr><td>TMUX</td><td>0</td></tr>
+<tr><td>GND</td><td>1</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:I_DELAY_EN"></div>
+<div id="bits-xc2v-IOI-IOI1:I_DELAY_EN"></div>
+<div id="bits-xc2v-IOI-IOI2:I_DELAY_EN"></div>
+<div id="bits-xc2v-IOI-IOI3:I_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY_EN</th><th>[0, 0, 4]</th></tr>
+<tr><th>IOI1:I_DELAY_EN</th><th>[0, 0, 24]</th></tr>
+<tr><th>IOI2:I_DELAY_EN</th><th>[0, 0, 44]</th></tr>
+<tr><th>IOI3:I_DELAY_EN</th><th>[0, 0, 64]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:TFF1_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI1:TFF1_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI2:TFF1_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI3:TFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_SRVAL</th><th>[0, 0, 5]</th></tr>
+<tr><th>IOI1:TFF1_SRVAL</th><th>[0, 0, 22]</th></tr>
+<tr><th>IOI2:TFF1_SRVAL</th><th>[0, 0, 42]</th></tr>
+<tr><th>IOI3:TFF1_SRVAL</th><th>[0, 0, 60]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:I_TSBYPASS_EN"></div>
+<div id="bits-xc2v-IOI-IOI1:I_TSBYPASS_EN"></div>
+<div id="bits-xc2v-IOI-IOI2:I_TSBYPASS_EN"></div>
+<div id="bits-xc2v-IOI-IOI3:I_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_TSBYPASS_EN</th><th>[0, 0, 6]</th></tr>
+<tr><th>IOI1:I_TSBYPASS_EN</th><th>[0, 0, 26]</th></tr>
+<tr><th>IOI2:I_TSBYPASS_EN</th><th>[0, 0, 46]</th></tr>
+<tr><th>IOI3:I_TSBYPASS_EN</th><th>[0, 0, 66]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:TMUX"></div>
+<div id="bits-xc2v-IOI-IOI1:TMUX"></div>
+<div id="bits-xc2v-IOI-IOI2:TMUX"></div>
+<div id="bits-xc2v-IOI-IOI3:TMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TMUX</th><th>[0, 0, 14]</th><th>[0, 0, 8]</th><th>[0, 0, 15]</th><th>[0, 0, 7]</th></tr>
+<tr><th>IOI1:TMUX</th><th>[0, 0, 33]</th><th>[0, 0, 27]</th><th>[0, 0, 36]</th><th>[0, 0, 25]</th></tr>
+<tr><th>IOI2:TMUX</th><th>[0, 0, 53]</th><th>[0, 0, 47]</th><th>[0, 0, 55]</th><th>[0, 0, 45]</th></tr>
+<tr><th>IOI3:TMUX</th><th>[0, 0, 72]</th><th>[0, 0, 65]</th><th>[0, 0, 74]</th><th>[0, 0, 61]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>T1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>T2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>TFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>TFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>TFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc2v-IOI-IOI1:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc2v-IOI-IOI2:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc2v-IOI-IOI3:IFF_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_TSBYPASS_EN</th><th>[0, 0, 9]</th></tr>
+<tr><th>IOI1:IFF_TSBYPASS_EN</th><th>[0, 0, 29]</th></tr>
+<tr><th>IOI2:IFF_TSBYPASS_EN</th><th>[0, 0, 49]</th></tr>
+<tr><th>IOI3:IFF_TSBYPASS_EN</th><th>[0, 0, 69]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:OFF_SYNC"></div>
+<div id="bits-xc2v-IOI-IOI1:OFF_SYNC"></div>
+<div id="bits-xc2v-IOI-IOI2:OFF_SYNC"></div>
+<div id="bits-xc2v-IOI-IOI3:OFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SYNC</th><th>[0, 0, 10]</th></tr>
+<tr><th>IOI1:OFF_SYNC</th><th>[0, 0, 28]</th></tr>
+<tr><th>IOI2:OFF_SYNC</th><th>[0, 0, 48]</th></tr>
+<tr><th>IOI3:OFF_SYNC</th><th>[0, 0, 67]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:IFF_DELAY_EN"></div>
+<div id="bits-xc2v-IOI-IOI1:IFF_DELAY_EN"></div>
+<div id="bits-xc2v-IOI-IOI2:IFF_DELAY_EN"></div>
+<div id="bits-xc2v-IOI-IOI3:IFF_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY_EN</th><th>[0, 0, 11]</th></tr>
+<tr><th>IOI1:IFF_DELAY_EN</th><th>[0, 0, 31]</th></tr>
+<tr><th>IOI2:IFF_DELAY_EN</th><th>[0, 0, 51]</th></tr>
+<tr><th>IOI3:IFF_DELAY_EN</th><th>[0, 0, 71]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:TFF_SYNC"></div>
+<div id="bits-xc2v-IOI-IOI1:TFF_SYNC"></div>
+<div id="bits-xc2v-IOI-IOI2:TFF_SYNC"></div>
+<div id="bits-xc2v-IOI-IOI3:TFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SYNC</th><th>[0, 0, 12]</th></tr>
+<tr><th>IOI1:TFF_SYNC</th><th>[0, 0, 30]</th></tr>
+<tr><th>IOI2:TFF_SYNC</th><th>[0, 0, 50]</th></tr>
+<tr><th>IOI3:TFF_SYNC</th><th>[0, 0, 68]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:IFF_SYNC"></div>
+<div id="bits-xc2v-IOI-IOI1:IFF_SYNC"></div>
+<div id="bits-xc2v-IOI-IOI2:IFF_SYNC"></div>
+<div id="bits-xc2v-IOI-IOI3:IFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SYNC</th><th>[0, 0, 13]</th></tr>
+<tr><th>IOI1:IFF_SYNC</th><th>[0, 0, 32]</th></tr>
+<tr><th>IOI2:IFF_SYNC</th><th>[0, 0, 52]</th></tr>
+<tr><th>IOI3:IFF_SYNC</th><th>[0, 0, 70]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:IFF_LATCH"></div>
+<div id="bits-xc2v-IOI-IOI1:IFF_LATCH"></div>
+<div id="bits-xc2v-IOI-IOI2:IFF_LATCH"></div>
+<div id="bits-xc2v-IOI-IOI3:IFF_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_LATCH</th><th>[0, 0, 16]</th></tr>
+<tr><th>IOI1:IFF_LATCH</th><th>[0, 0, 35]</th></tr>
+<tr><th>IOI2:IFF_LATCH</th><th>[0, 0, 54]</th></tr>
+<tr><th>IOI3:IFF_LATCH</th><th>[0, 0, 73]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:TFF2_LATCH"></div>
+<div id="bits-xc2v-IOI-IOI1:TFF2_LATCH"></div>
+<div id="bits-xc2v-IOI-IOI2:TFF2_LATCH"></div>
+<div id="bits-xc2v-IOI-IOI3:TFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_LATCH</th><th>[0, 0, 17]</th></tr>
+<tr><th>IOI1:TFF2_LATCH</th><th>[0, 0, 37]</th></tr>
+<tr><th>IOI2:TFF2_LATCH</th><th>[0, 0, 56]</th></tr>
+<tr><th>IOI3:TFF2_LATCH</th><th>[0, 0, 75]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:TFF1_LATCH"></div>
+<div id="bits-xc2v-IOI-IOI1:TFF1_LATCH"></div>
+<div id="bits-xc2v-IOI-IOI2:TFF1_LATCH"></div>
+<div id="bits-xc2v-IOI-IOI3:TFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_LATCH</th><th>[0, 0, 34]</th></tr>
+<tr><th>IOI1:TFF1_LATCH</th><th>[0, 0, 18]</th></tr>
+<tr><th>IOI2:TFF1_LATCH</th><th>[0, 0, 41]</th></tr>
+<tr><th>IOI3:TFF1_LATCH</th><th>[0, 0, 62]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:TFF2_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI1:TFF2_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI2:TFF2_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI3:TFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_SRVAL</th><th>[0, 0, 19]</th></tr>
+<tr><th>IOI1:TFF2_SRVAL</th><th>[0, 0, 38]</th></tr>
+<tr><th>IOI2:TFF2_SRVAL</th><th>[0, 0, 57]</th></tr>
+<tr><th>IOI3:TFF2_SRVAL</th><th>[0, 0, 76]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:IFF2_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI1:IFF2_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI2:IFF2_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI3:IFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_SRVAL</th><th>[0, 0, 20]</th></tr>
+<tr><th>IOI1:IFF2_SRVAL</th><th>[0, 0, 39]</th></tr>
+<tr><th>IOI2:IFF2_SRVAL</th><th>[0, 0, 58]</th></tr>
+<tr><th>IOI3:IFF2_SRVAL</th><th>[0, 0, 77]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:IFF_SR_EN"></div>
+<div id="bits-xc2v-IOI-IOI1:IFF_SR_EN"></div>
+<div id="bits-xc2v-IOI-IOI2:IFF_SR_EN"></div>
+<div id="bits-xc2v-IOI-IOI3:IFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SR_EN</th><th>[0, 1, 2]</th></tr>
+<tr><th>IOI1:IFF_SR_EN</th><th>[0, 1, 21]</th></tr>
+<tr><th>IOI2:IFF_SR_EN</th><th>[0, 1, 40]</th></tr>
+<tr><th>IOI3:IFF_SR_EN</th><th>[0, 1, 59]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:IFF_REV_EN"></div>
+<div id="bits-xc2v-IOI-IOI1:IFF_REV_EN"></div>
+<div id="bits-xc2v-IOI-IOI2:IFF_REV_EN"></div>
+<div id="bits-xc2v-IOI-IOI3:IFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_REV_EN</th><th>[0, 1, 3]</th></tr>
+<tr><th>IOI1:IFF_REV_EN</th><th>[0, 1, 22]</th></tr>
+<tr><th>IOI2:IFF_REV_EN</th><th>[0, 1, 41]</th></tr>
+<tr><th>IOI3:IFF_REV_EN</th><th>[0, 1, 60]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:TFF_REV_EN"></div>
+<div id="bits-xc2v-IOI-IOI1:TFF_REV_EN"></div>
+<div id="bits-xc2v-IOI-IOI2:TFF_REV_EN"></div>
+<div id="bits-xc2v-IOI-IOI3:TFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_REV_EN</th><th>[0, 1, 4]</th></tr>
+<tr><th>IOI1:TFF_REV_EN</th><th>[0, 1, 23]</th></tr>
+<tr><th>IOI2:TFF_REV_EN</th><th>[0, 1, 42]</th></tr>
+<tr><th>IOI3:TFF_REV_EN</th><th>[0, 1, 61]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:TFF_SR_EN"></div>
+<div id="bits-xc2v-IOI-IOI1:TFF_SR_EN"></div>
+<div id="bits-xc2v-IOI-IOI2:TFF_SR_EN"></div>
+<div id="bits-xc2v-IOI-IOI3:TFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SR_EN</th><th>[0, 1, 5]</th></tr>
+<tr><th>IOI1:TFF_SR_EN</th><th>[0, 1, 24]</th></tr>
+<tr><th>IOI2:TFF_SR_EN</th><th>[0, 1, 43]</th></tr>
+<tr><th>IOI3:TFF_SR_EN</th><th>[0, 1, 62]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:IFF1_INIT"></div>
+<div id="bits-xc2v-IOI-IOI1:IFF1_INIT"></div>
+<div id="bits-xc2v-IOI-IOI2:IFF1_INIT"></div>
+<div id="bits-xc2v-IOI-IOI3:IFF1_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_INIT</th><th>[0, 1, 9]</th></tr>
+<tr><th>IOI1:IFF1_INIT</th><th>[0, 1, 29]</th></tr>
+<tr><th>IOI2:IFF1_INIT</th><th>[0, 1, 49]</th></tr>
+<tr><th>IOI3:IFF1_INIT</th><th>[0, 1, 69]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:IFF2_INIT"></div>
+<div id="bits-xc2v-IOI-IOI1:IFF2_INIT"></div>
+<div id="bits-xc2v-IOI-IOI2:IFF2_INIT"></div>
+<div id="bits-xc2v-IOI-IOI3:IFF2_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_INIT</th><th>[0, 1, 13]</th></tr>
+<tr><th>IOI1:IFF2_INIT</th><th>[0, 1, 33]</th></tr>
+<tr><th>IOI2:IFF2_INIT</th><th>[0, 1, 53]</th></tr>
+<tr><th>IOI3:IFF2_INIT</th><th>[0, 1, 73]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:TFF_INIT"></div>
+<div id="bits-xc2v-IOI-IOI1:TFF_INIT"></div>
+<div id="bits-xc2v-IOI-IOI2:TFF_INIT"></div>
+<div id="bits-xc2v-IOI-IOI3:TFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_INIT</th><th>[0, 1, 17]</th></tr>
+<tr><th>IOI1:TFF_INIT</th><th>[0, 1, 37]</th></tr>
+<tr><th>IOI2:TFF_INIT</th><th>[0, 1, 55]</th></tr>
+<tr><th>IOI3:TFF_INIT</th><th>[0, 1, 75]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:OFF_REV_EN"></div>
+<div id="bits-xc2v-IOI-IOI1:OFF_REV_EN"></div>
+<div id="bits-xc2v-IOI-IOI2:OFF_REV_EN"></div>
+<div id="bits-xc2v-IOI-IOI3:OFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_REV_EN</th><th>[0, 2, 4]</th></tr>
+<tr><th>IOI1:OFF_REV_EN</th><th>[0, 2, 23]</th></tr>
+<tr><th>IOI2:OFF_REV_EN</th><th>[0, 2, 42]</th></tr>
+<tr><th>IOI3:OFF_REV_EN</th><th>[0, 2, 61]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:OFF_SR_EN"></div>
+<div id="bits-xc2v-IOI-IOI1:OFF_SR_EN"></div>
+<div id="bits-xc2v-IOI-IOI2:OFF_SR_EN"></div>
+<div id="bits-xc2v-IOI-IOI3:OFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SR_EN</th><th>[0, 2, 5]</th></tr>
+<tr><th>IOI1:OFF_SR_EN</th><th>[0, 2, 24]</th></tr>
+<tr><th>IOI2:OFF_SR_EN</th><th>[0, 2, 43]</th></tr>
+<tr><th>IOI3:OFF_SR_EN</th><th>[0, 2, 62]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:OFF_INIT"></div>
+<div id="bits-xc2v-IOI-IOI1:OFF_INIT"></div>
+<div id="bits-xc2v-IOI-IOI2:OFF_INIT"></div>
+<div id="bits-xc2v-IOI-IOI3:OFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_INIT</th><th>[0, 2, 17]</th></tr>
+<tr><th>IOI1:OFF_INIT</th><th>[0, 2, 37]</th></tr>
+<tr><th>IOI2:OFF_INIT</th><th>[0, 2, 55]</th></tr>
+<tr><th>IOI3:OFF_INIT</th><th>[0, 2, 75]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:ICEINV"></div>
+<div id="bits-xc2v-IOI-IOI0:ICLK1INV"></div>
+<div id="bits-xc2v-IOI-IOI0:ICLK2INV"></div>
+<div id="bits-xc2v-IOI-IOI0:OTCLK1INV"></div>
+<div id="bits-xc2v-IOI-IOI0:OTCLK2INV"></div>
+<div id="bits-xc2v-IOI-IOI0:REVINV"></div>
+<div id="bits-xc2v-IOI-IOI0:TCEINV"></div>
+<div id="bits-xc2v-IOI-IOI1:ICEINV"></div>
+<div id="bits-xc2v-IOI-IOI1:ICLK1INV"></div>
+<div id="bits-xc2v-IOI-IOI1:ICLK2INV"></div>
+<div id="bits-xc2v-IOI-IOI1:OTCLK1INV"></div>
+<div id="bits-xc2v-IOI-IOI1:OTCLK2INV"></div>
+<div id="bits-xc2v-IOI-IOI1:REVINV"></div>
+<div id="bits-xc2v-IOI-IOI1:TCEINV"></div>
+<div id="bits-xc2v-IOI-IOI2:ICEINV"></div>
+<div id="bits-xc2v-IOI-IOI2:ICLK1INV"></div>
+<div id="bits-xc2v-IOI-IOI2:ICLK2INV"></div>
+<div id="bits-xc2v-IOI-IOI2:OTCLK1INV"></div>
+<div id="bits-xc2v-IOI-IOI2:OTCLK2INV"></div>
+<div id="bits-xc2v-IOI-IOI2:REVINV"></div>
+<div id="bits-xc2v-IOI-IOI2:TCEINV"></div>
+<div id="bits-xc2v-IOI-IOI3:ICEINV"></div>
+<div id="bits-xc2v-IOI-IOI3:ICLK1INV"></div>
+<div id="bits-xc2v-IOI-IOI3:ICLK2INV"></div>
+<div id="bits-xc2v-IOI-IOI3:OTCLK1INV"></div>
+<div id="bits-xc2v-IOI-IOI3:OTCLK2INV"></div>
+<div id="bits-xc2v-IOI-IOI3:REVINV"></div>
+<div id="bits-xc2v-IOI-IOI3:TCEINV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:ICEINV</th><th>[0, 3, 6]</th></tr>
+<tr><th>IOI0:ICLK1INV</th><th>[0, 3, 8]</th></tr>
+<tr><th>IOI0:ICLK2INV</th><th>[0, 3, 0]</th></tr>
+<tr><th>IOI0:OTCLK1INV</th><th>[0, 3, 19]</th></tr>
+<tr><th>IOI0:OTCLK2INV</th><th>[0, 3, 9]</th></tr>
+<tr><th>IOI0:REVINV</th><th>[0, 3, 2]</th></tr>
+<tr><th>IOI0:TCEINV</th><th>[0, 3, 4]</th></tr>
+<tr><th>IOI1:ICEINV</th><th>[0, 3, 26]</th></tr>
+<tr><th>IOI1:ICLK1INV</th><th>[0, 3, 28]</th></tr>
+<tr><th>IOI1:ICLK2INV</th><th>[0, 3, 20]</th></tr>
+<tr><th>IOI1:OTCLK1INV</th><th>[0, 3, 39]</th></tr>
+<tr><th>IOI1:OTCLK2INV</th><th>[0, 3, 29]</th></tr>
+<tr><th>IOI1:REVINV</th><th>[0, 3, 22]</th></tr>
+<tr><th>IOI1:TCEINV</th><th>[0, 3, 24]</th></tr>
+<tr><th>IOI2:ICEINV</th><th>[0, 3, 46]</th></tr>
+<tr><th>IOI2:ICLK1INV</th><th>[0, 3, 48]</th></tr>
+<tr><th>IOI2:ICLK2INV</th><th>[0, 3, 40]</th></tr>
+<tr><th>IOI2:OTCLK1INV</th><th>[0, 3, 59]</th></tr>
+<tr><th>IOI2:OTCLK2INV</th><th>[0, 3, 49]</th></tr>
+<tr><th>IOI2:REVINV</th><th>[0, 3, 42]</th></tr>
+<tr><th>IOI2:TCEINV</th><th>[0, 3, 44]</th></tr>
+<tr><th>IOI3:ICEINV</th><th>[0, 3, 66]</th></tr>
+<tr><th>IOI3:ICLK1INV</th><th>[0, 3, 68]</th></tr>
+<tr><th>IOI3:ICLK2INV</th><th>[0, 3, 60]</th></tr>
+<tr><th>IOI3:OTCLK1INV</th><th>[0, 3, 79]</th></tr>
+<tr><th>IOI3:OTCLK2INV</th><th>[0, 3, 69]</th></tr>
+<tr><th>IOI3:REVINV</th><th>[0, 3, 62]</th></tr>
+<tr><th>IOI3:TCEINV</th><th>[0, 3, 64]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:OFF1_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI1:OFF1_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI2:OFF1_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI3:OFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_SRVAL</th><th>[0, 3, 1]</th></tr>
+<tr><th>IOI1:OFF1_SRVAL</th><th>[0, 3, 21]</th></tr>
+<tr><th>IOI2:OFF1_SRVAL</th><th>[0, 3, 41]</th></tr>
+<tr><th>IOI3:OFF1_SRVAL</th><th>[0, 3, 61]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:OMUX"></div>
+<div id="bits-xc2v-IOI-IOI1:OMUX"></div>
+<div id="bits-xc2v-IOI-IOI2:OMUX"></div>
+<div id="bits-xc2v-IOI-IOI3:OMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OMUX</th><th>[0, 3, 12]</th><th>[0, 3, 3]</th><th>[0, 3, 10]</th><th>[0, 3, 5]</th></tr>
+<tr><th>IOI1:OMUX</th><th>[0, 3, 32]</th><th>[0, 3, 23]</th><th>[0, 3, 30]</th><th>[0, 3, 25]</th></tr>
+<tr><th>IOI2:OMUX</th><th>[0, 3, 52]</th><th>[0, 3, 43]</th><th>[0, 3, 50]</th><th>[0, 3, 45]</th></tr>
+<tr><th>IOI3:OMUX</th><th>[0, 3, 72]</th><th>[0, 3, 63]</th><th>[0, 3, 70]</th><th>[0, 3, 65]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>O1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>O2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:OFF1_LATCH"></div>
+<div id="bits-xc2v-IOI-IOI1:OFF1_LATCH"></div>
+<div id="bits-xc2v-IOI-IOI2:OFF1_LATCH"></div>
+<div id="bits-xc2v-IOI-IOI3:OFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_LATCH</th><th>[0, 3, 7]</th></tr>
+<tr><th>IOI1:OFF1_LATCH</th><th>[0, 3, 27]</th></tr>
+<tr><th>IOI2:OFF1_LATCH</th><th>[0, 3, 47]</th></tr>
+<tr><th>IOI3:OFF1_LATCH</th><th>[0, 3, 67]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:O1INV"></div>
+<div id="bits-xc2v-IOI-IOI0:O2INV"></div>
+<div id="bits-xc2v-IOI-IOI0:T1INV"></div>
+<div id="bits-xc2v-IOI-IOI0:T2INV"></div>
+<div id="bits-xc2v-IOI-IOI1:O1INV"></div>
+<div id="bits-xc2v-IOI-IOI1:O2INV"></div>
+<div id="bits-xc2v-IOI-IOI1:T1INV"></div>
+<div id="bits-xc2v-IOI-IOI1:T2INV"></div>
+<div id="bits-xc2v-IOI-IOI2:O1INV"></div>
+<div id="bits-xc2v-IOI-IOI2:O2INV"></div>
+<div id="bits-xc2v-IOI-IOI2:T1INV"></div>
+<div id="bits-xc2v-IOI-IOI2:T2INV"></div>
+<div id="bits-xc2v-IOI-IOI3:O1INV"></div>
+<div id="bits-xc2v-IOI-IOI3:O2INV"></div>
+<div id="bits-xc2v-IOI-IOI3:T1INV"></div>
+<div id="bits-xc2v-IOI-IOI3:T2INV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1INV</th><th>[0, 3, 11]</th></tr>
+<tr><th>IOI0:O2INV</th><th>[0, 3, 13]</th></tr>
+<tr><th>IOI0:T1INV</th><th>[0, 3, 15]</th></tr>
+<tr><th>IOI0:T2INV</th><th>[0, 3, 17]</th></tr>
+<tr><th>IOI1:O1INV</th><th>[0, 3, 31]</th></tr>
+<tr><th>IOI1:O2INV</th><th>[0, 3, 33]</th></tr>
+<tr><th>IOI1:T1INV</th><th>[0, 3, 35]</th></tr>
+<tr><th>IOI1:T2INV</th><th>[0, 3, 37]</th></tr>
+<tr><th>IOI2:O1INV</th><th>[0, 3, 51]</th></tr>
+<tr><th>IOI2:O2INV</th><th>[0, 3, 53]</th></tr>
+<tr><th>IOI2:T1INV</th><th>[0, 3, 55]</th></tr>
+<tr><th>IOI2:T2INV</th><th>[0, 3, 57]</th></tr>
+<tr><th>IOI3:O1INV</th><th>[0, 3, 71]</th></tr>
+<tr><th>IOI3:O2INV</th><th>[0, 3, 73]</th></tr>
+<tr><th>IOI3:T1INV</th><th>[0, 3, 75]</th></tr>
+<tr><th>IOI3:T2INV</th><th>[0, 3, 77]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:OFF2_LATCH"></div>
+<div id="bits-xc2v-IOI-IOI1:OFF2_LATCH"></div>
+<div id="bits-xc2v-IOI-IOI2:OFF2_LATCH"></div>
+<div id="bits-xc2v-IOI-IOI3:OFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_LATCH</th><th>[0, 3, 14]</th></tr>
+<tr><th>IOI1:OFF2_LATCH</th><th>[0, 3, 34]</th></tr>
+<tr><th>IOI2:OFF2_LATCH</th><th>[0, 3, 54]</th></tr>
+<tr><th>IOI3:OFF2_LATCH</th><th>[0, 3, 74]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI-IOI0:OFF2_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI1:OFF2_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI2:OFF2_SRVAL"></div>
+<div id="bits-xc2v-IOI-IOI3:OFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_SRVAL</th><th>[0, 3, 18]</th></tr>
+<tr><th>IOI1:OFF2_SRVAL</th><th>[0, 3, 38]</th></tr>
+<tr><th>IOI2:OFF2_SRVAL</th><th>[0, 3, 58]</th></tr>
+<tr><th>IOI3:OFF2_SRVAL</th><th>[0, 3, 78]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+</section>
+<section id="ioi-clk-b-virtex-2">
+<h3><code class="docutils literal notranslate"><span class="pre">IOI.CLK_B</span></code> — Virtex 2<a class="headerlink" href="#ioi-clk-b-virtex-2" title="Link to this heading"></a></h3>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:ICLK2INV" title="~IOI0:ICLK2INV">~IOI0:ICLK2INV</a></td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:OFF1_SRVAL" title="~IOI0:OFF1_SRVAL">~IOI0:OFF1_SRVAL</a></td></tr>
+<tr><td>2</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:IFF1_SRVAL" title="~IOI0:IFF1_SRVAL">~IOI0:IFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:IFF_SR_EN" title="IOI0:IFF_SR_EN">IOI0:IFF_SR_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:REVINV" title="~IOI0:REVINV">~IOI0:REVINV</a></td></tr>
+<tr><td>3</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:TSBYPASS_MUX" title="IOI0:TSBYPASS_MUX">IOI0:TSBYPASS_MUX</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:IFF_REV_EN" title="IOI0:IFF_REV_EN">IOI0:IFF_REV_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:OMUX" title="IOI0:OMUX[2]">IOI0:OMUX[2]</a></td></tr>
+<tr><td>4</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:I_DELAY_EN" title="IOI0:I_DELAY_EN">IOI0:I_DELAY_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:TFF_REV_EN" title="IOI0:TFF_REV_EN">IOI0:TFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:OFF_REV_EN" title="IOI0:OFF_REV_EN">IOI0:OFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:TCEINV" title="~IOI0:TCEINV">~IOI0:TCEINV</a></td></tr>
+<tr><td>5</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:TFF1_SRVAL" title="~IOI0:TFF1_SRVAL">~IOI0:TFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:TFF_SR_EN" title="IOI0:TFF_SR_EN">IOI0:TFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:OFF_SR_EN" title="IOI0:OFF_SR_EN">IOI0:OFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:OMUX" title="IOI0:OMUX[0]">IOI0:OMUX[0]</a></td></tr>
+<tr><td>6</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:I_TSBYPASS_EN" title="IOI0:I_TSBYPASS_EN">IOI0:I_TSBYPASS_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:ICEINV" title="~IOI0:ICEINV">~IOI0:ICEINV</a></td></tr>
+<tr><td>7</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:TMUX" title="IOI0:TMUX[0]">IOI0:TMUX[0]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:OFF1_LATCH" title="IOI0:OFF1_LATCH">IOI0:OFF1_LATCH</a></td></tr>
+<tr><td>8</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:TMUX" title="IOI0:TMUX[2]">IOI0:TMUX[2]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:ICLK1INV" title="~IOI0:ICLK1INV">~IOI0:ICLK1INV</a></td></tr>
+<tr><td>9</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:IFF_TSBYPASS_EN" title="IOI0:IFF_TSBYPASS_EN">IOI0:IFF_TSBYPASS_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:IFF1_INIT" title="~IOI0:IFF1_INIT">~IOI0:IFF1_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:OTCLK2INV" title="~IOI0:OTCLK2INV">~IOI0:OTCLK2INV</a></td></tr>
+<tr><td>10</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:OFF_SYNC" title="IOI0:OFF_SYNC">IOI0:OFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:OMUX" title="IOI0:OMUX[1]">IOI0:OMUX[1]</a></td></tr>
+<tr><td>11</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:IFF_DELAY_EN" title="IOI0:IFF_DELAY_EN">IOI0:IFF_DELAY_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:O1INV" title="IOI0:O1INV">IOI0:O1INV</a></td></tr>
+<tr><td>12</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:TFF_SYNC" title="IOI0:TFF_SYNC">IOI0:TFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:OMUX" title="IOI0:OMUX[3]">IOI0:OMUX[3]</a></td></tr>
+<tr><td>13</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:IFF_SYNC" title="IOI0:IFF_SYNC">IOI0:IFF_SYNC</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:IFF2_INIT" title="~IOI0:IFF2_INIT">~IOI0:IFF2_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:O2INV" title="IOI0:O2INV">IOI0:O2INV</a></td></tr>
+<tr><td>14</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:TMUX" title="IOI0:TMUX[3]">IOI0:TMUX[3]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:OFF2_LATCH" title="IOI0:OFF2_LATCH">IOI0:OFF2_LATCH</a></td></tr>
+<tr><td>15</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:TMUX" title="IOI0:TMUX[1]">IOI0:TMUX[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:T1INV" title="IOI0:T1INV">IOI0:T1INV</a></td></tr>
+<tr><td>16</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:IFF_LATCH" title="IOI0:IFF_LATCH">IOI0:IFF_LATCH</a></td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>17</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:TFF2_LATCH" title="IOI0:TFF2_LATCH">IOI0:TFF2_LATCH</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:TFF_INIT" title="~IOI0:TFF_INIT">~IOI0:TFF_INIT</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:OFF_INIT" title="~IOI0:OFF_INIT">~IOI0:OFF_INIT</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:T2INV" title="IOI0:T2INV">IOI0:T2INV</a></td></tr>
+<tr><td>18</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:TFF1_LATCH" title="IOI1:TFF1_LATCH">IOI1:TFF1_LATCH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:OFF2_SRVAL" title="~IOI0:OFF2_SRVAL">~IOI0:OFF2_SRVAL</a></td></tr>
+<tr><td>19</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:TFF2_SRVAL" title="~IOI0:TFF2_SRVAL">~IOI0:TFF2_SRVAL</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI0:OTCLK1INV" title="~IOI0:OTCLK1INV">~IOI0:OTCLK1INV</a></td></tr>
+<tr><td>20</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:IFF2_SRVAL" title="~IOI0:IFF2_SRVAL">~IOI0:IFF2_SRVAL</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:ICLK2INV" title="~IOI1:ICLK2INV">~IOI1:ICLK2INV</a></td></tr>
+<tr><td>21</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:IFF1_SRVAL" title="~IOI1:IFF1_SRVAL">~IOI1:IFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:IFF_SR_EN" title="IOI1:IFF_SR_EN">IOI1:IFF_SR_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:OFF1_SRVAL" title="~IOI1:OFF1_SRVAL">~IOI1:OFF1_SRVAL</a></td></tr>
+<tr><td>22</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:TFF1_SRVAL" title="~IOI1:TFF1_SRVAL">~IOI1:TFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:IFF_REV_EN" title="IOI1:IFF_REV_EN">IOI1:IFF_REV_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:REVINV" title="~IOI1:REVINV">~IOI1:REVINV</a></td></tr>
+<tr><td>23</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:TSBYPASS_MUX" title="IOI1:TSBYPASS_MUX">IOI1:TSBYPASS_MUX</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:TFF_REV_EN" title="IOI1:TFF_REV_EN">IOI1:TFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:OFF_REV_EN" title="IOI1:OFF_REV_EN">IOI1:OFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:OMUX" title="IOI1:OMUX[2]">IOI1:OMUX[2]</a></td></tr>
+<tr><td>24</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:I_DELAY_EN" title="IOI1:I_DELAY_EN">IOI1:I_DELAY_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:TFF_SR_EN" title="IOI1:TFF_SR_EN">IOI1:TFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:OFF_SR_EN" title="IOI1:OFF_SR_EN">IOI1:OFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:TCEINV" title="~IOI1:TCEINV">~IOI1:TCEINV</a></td></tr>
+<tr><td>25</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:TMUX" title="IOI1:TMUX[0]">IOI1:TMUX[0]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:OMUX" title="IOI1:OMUX[0]">IOI1:OMUX[0]</a></td></tr>
+<tr><td>26</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:I_TSBYPASS_EN" title="IOI1:I_TSBYPASS_EN">IOI1:I_TSBYPASS_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:ICEINV" title="~IOI1:ICEINV">~IOI1:ICEINV</a></td></tr>
+<tr><td>27</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:TMUX" title="IOI1:TMUX[2]">IOI1:TMUX[2]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:OFF1_LATCH" title="IOI1:OFF1_LATCH">IOI1:OFF1_LATCH</a></td></tr>
+<tr><td>28</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:OFF_SYNC" title="IOI1:OFF_SYNC">IOI1:OFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:ICLK1INV" title="~IOI1:ICLK1INV">~IOI1:ICLK1INV</a></td></tr>
+<tr><td>29</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:IFF_TSBYPASS_EN" title="IOI1:IFF_TSBYPASS_EN">IOI1:IFF_TSBYPASS_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:IFF1_INIT" title="~IOI1:IFF1_INIT">~IOI1:IFF1_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:OTCLK2INV" title="~IOI1:OTCLK2INV">~IOI1:OTCLK2INV</a></td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:TFF_SYNC" title="IOI1:TFF_SYNC">IOI1:TFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:OMUX" title="IOI1:OMUX[1]">IOI1:OMUX[1]</a></td></tr>
+<tr><td>31</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:IFF_DELAY_EN" title="IOI1:IFF_DELAY_EN">IOI1:IFF_DELAY_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:O1INV" title="IOI1:O1INV">IOI1:O1INV</a></td></tr>
+<tr><td>32</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:IFF_SYNC" title="IOI1:IFF_SYNC">IOI1:IFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:OMUX" title="IOI1:OMUX[3]">IOI1:OMUX[3]</a></td></tr>
+<tr><td>33</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:TMUX" title="IOI1:TMUX[3]">IOI1:TMUX[3]</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:IFF2_INIT" title="~IOI1:IFF2_INIT">~IOI1:IFF2_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:O2INV" title="IOI1:O2INV">IOI1:O2INV</a></td></tr>
+<tr><td>34</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI0:TFF1_LATCH" title="IOI0:TFF1_LATCH">IOI0:TFF1_LATCH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:OFF2_LATCH" title="IOI1:OFF2_LATCH">IOI1:OFF2_LATCH</a></td></tr>
+<tr><td>35</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:IFF_LATCH" title="IOI1:IFF_LATCH">IOI1:IFF_LATCH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:T1INV" title="IOI1:T1INV">IOI1:T1INV</a></td></tr>
+<tr><td>36</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:TMUX" title="IOI1:TMUX[1]">IOI1:TMUX[1]</a></td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>37</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:TFF2_LATCH" title="IOI1:TFF2_LATCH">IOI1:TFF2_LATCH</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:TFF_INIT" title="~IOI1:TFF_INIT">~IOI1:TFF_INIT</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:OFF_INIT" title="~IOI1:OFF_INIT">~IOI1:OFF_INIT</a></td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:T2INV" title="IOI1:T2INV">IOI1:T2INV</a></td></tr>
+<tr><td>38</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:TFF2_SRVAL" title="~IOI1:TFF2_SRVAL">~IOI1:TFF2_SRVAL</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:OFF2_SRVAL" title="~IOI1:OFF2_SRVAL">~IOI1:OFF2_SRVAL</a></td></tr>
+<tr><td>39</td>
+<td><a href="#bits-xc2v-IOI.CLK_B-IOI1:IFF2_SRVAL" title="~IOI1:IFF2_SRVAL">~IOI1:IFF2_SRVAL</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_B-IOI1:OTCLK1INV" title="~IOI1:OTCLK1INV">~IOI1:OTCLK1INV</a></td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:IFF1_SRVAL"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:IFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_SRVAL</th><th>[0, 0, 2]</th></tr>
+<tr><th>IOI1:IFF1_SRVAL</th><th>[0, 0, 21]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:TSBYPASS_MUX"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:TSBYPASS_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TSBYPASS_MUX</th><th>[0, 0, 3]</th></tr>
+<tr><th>IOI1:TSBYPASS_MUX</th><th>[0, 0, 23]</th></tr>
+<tr><td>TMUX</td><td>0</td></tr>
+<tr><td>GND</td><td>1</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:I_DELAY_EN"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:I_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY_EN</th><th>[0, 0, 4]</th></tr>
+<tr><th>IOI1:I_DELAY_EN</th><th>[0, 0, 24]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:TFF1_SRVAL"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:TFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_SRVAL</th><th>[0, 0, 5]</th></tr>
+<tr><th>IOI1:TFF1_SRVAL</th><th>[0, 0, 22]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:I_TSBYPASS_EN"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:I_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_TSBYPASS_EN</th><th>[0, 0, 6]</th></tr>
+<tr><th>IOI1:I_TSBYPASS_EN</th><th>[0, 0, 26]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:TMUX"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:TMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TMUX</th><th>[0, 0, 14]</th><th>[0, 0, 8]</th><th>[0, 0, 15]</th><th>[0, 0, 7]</th></tr>
+<tr><th>IOI1:TMUX</th><th>[0, 0, 33]</th><th>[0, 0, 27]</th><th>[0, 0, 36]</th><th>[0, 0, 25]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>T1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>T2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>TFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>TFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>TFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:IFF_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_TSBYPASS_EN</th><th>[0, 0, 9]</th></tr>
+<tr><th>IOI1:IFF_TSBYPASS_EN</th><th>[0, 0, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:OFF_SYNC"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:OFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SYNC</th><th>[0, 0, 10]</th></tr>
+<tr><th>IOI1:OFF_SYNC</th><th>[0, 0, 28]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:IFF_DELAY_EN"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:IFF_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY_EN</th><th>[0, 0, 11]</th></tr>
+<tr><th>IOI1:IFF_DELAY_EN</th><th>[0, 0, 31]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:TFF_SYNC"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:TFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SYNC</th><th>[0, 0, 12]</th></tr>
+<tr><th>IOI1:TFF_SYNC</th><th>[0, 0, 30]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:IFF_SYNC"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:IFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SYNC</th><th>[0, 0, 13]</th></tr>
+<tr><th>IOI1:IFF_SYNC</th><th>[0, 0, 32]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:IFF_LATCH"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:IFF_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_LATCH</th><th>[0, 0, 16]</th></tr>
+<tr><th>IOI1:IFF_LATCH</th><th>[0, 0, 35]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:TFF2_LATCH"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:TFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_LATCH</th><th>[0, 0, 17]</th></tr>
+<tr><th>IOI1:TFF2_LATCH</th><th>[0, 0, 37]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:TFF1_LATCH"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:TFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_LATCH</th><th>[0, 0, 34]</th></tr>
+<tr><th>IOI1:TFF1_LATCH</th><th>[0, 0, 18]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:TFF2_SRVAL"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:TFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_SRVAL</th><th>[0, 0, 19]</th></tr>
+<tr><th>IOI1:TFF2_SRVAL</th><th>[0, 0, 38]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:IFF2_SRVAL"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:IFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_SRVAL</th><th>[0, 0, 20]</th></tr>
+<tr><th>IOI1:IFF2_SRVAL</th><th>[0, 0, 39]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:IFF_SR_EN"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:IFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SR_EN</th><th>[0, 1, 2]</th></tr>
+<tr><th>IOI1:IFF_SR_EN</th><th>[0, 1, 21]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:IFF_REV_EN"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:IFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_REV_EN</th><th>[0, 1, 3]</th></tr>
+<tr><th>IOI1:IFF_REV_EN</th><th>[0, 1, 22]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:TFF_REV_EN"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:TFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_REV_EN</th><th>[0, 1, 4]</th></tr>
+<tr><th>IOI1:TFF_REV_EN</th><th>[0, 1, 23]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:TFF_SR_EN"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:TFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SR_EN</th><th>[0, 1, 5]</th></tr>
+<tr><th>IOI1:TFF_SR_EN</th><th>[0, 1, 24]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:IFF1_INIT"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:IFF1_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_INIT</th><th>[0, 1, 9]</th></tr>
+<tr><th>IOI1:IFF1_INIT</th><th>[0, 1, 29]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:IFF2_INIT"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:IFF2_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_INIT</th><th>[0, 1, 13]</th></tr>
+<tr><th>IOI1:IFF2_INIT</th><th>[0, 1, 33]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:TFF_INIT"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:TFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_INIT</th><th>[0, 1, 17]</th></tr>
+<tr><th>IOI1:TFF_INIT</th><th>[0, 1, 37]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:OFF_REV_EN"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:OFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_REV_EN</th><th>[0, 2, 4]</th></tr>
+<tr><th>IOI1:OFF_REV_EN</th><th>[0, 2, 23]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:OFF_SR_EN"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:OFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SR_EN</th><th>[0, 2, 5]</th></tr>
+<tr><th>IOI1:OFF_SR_EN</th><th>[0, 2, 24]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:OFF_INIT"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:OFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_INIT</th><th>[0, 2, 17]</th></tr>
+<tr><th>IOI1:OFF_INIT</th><th>[0, 2, 37]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:ICEINV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:ICLK1INV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:ICLK2INV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:OTCLK1INV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:OTCLK2INV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:REVINV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:TCEINV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:ICEINV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:ICLK1INV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:ICLK2INV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:OTCLK1INV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:OTCLK2INV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:REVINV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:TCEINV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:ICEINV</th><th>[0, 3, 6]</th></tr>
+<tr><th>IOI0:ICLK1INV</th><th>[0, 3, 8]</th></tr>
+<tr><th>IOI0:ICLK2INV</th><th>[0, 3, 0]</th></tr>
+<tr><th>IOI0:OTCLK1INV</th><th>[0, 3, 19]</th></tr>
+<tr><th>IOI0:OTCLK2INV</th><th>[0, 3, 9]</th></tr>
+<tr><th>IOI0:REVINV</th><th>[0, 3, 2]</th></tr>
+<tr><th>IOI0:TCEINV</th><th>[0, 3, 4]</th></tr>
+<tr><th>IOI1:ICEINV</th><th>[0, 3, 26]</th></tr>
+<tr><th>IOI1:ICLK1INV</th><th>[0, 3, 28]</th></tr>
+<tr><th>IOI1:ICLK2INV</th><th>[0, 3, 20]</th></tr>
+<tr><th>IOI1:OTCLK1INV</th><th>[0, 3, 39]</th></tr>
+<tr><th>IOI1:OTCLK2INV</th><th>[0, 3, 29]</th></tr>
+<tr><th>IOI1:REVINV</th><th>[0, 3, 22]</th></tr>
+<tr><th>IOI1:TCEINV</th><th>[0, 3, 24]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:OFF1_SRVAL"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:OFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_SRVAL</th><th>[0, 3, 1]</th></tr>
+<tr><th>IOI1:OFF1_SRVAL</th><th>[0, 3, 21]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:OMUX"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:OMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OMUX</th><th>[0, 3, 12]</th><th>[0, 3, 3]</th><th>[0, 3, 10]</th><th>[0, 3, 5]</th></tr>
+<tr><th>IOI1:OMUX</th><th>[0, 3, 32]</th><th>[0, 3, 23]</th><th>[0, 3, 30]</th><th>[0, 3, 25]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>O1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>O2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:OFF1_LATCH"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:OFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_LATCH</th><th>[0, 3, 7]</th></tr>
+<tr><th>IOI1:OFF1_LATCH</th><th>[0, 3, 27]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:O1INV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:O2INV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:T1INV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:T2INV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:O1INV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:O2INV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:T1INV"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:T2INV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1INV</th><th>[0, 3, 11]</th></tr>
+<tr><th>IOI0:O2INV</th><th>[0, 3, 13]</th></tr>
+<tr><th>IOI0:T1INV</th><th>[0, 3, 15]</th></tr>
+<tr><th>IOI0:T2INV</th><th>[0, 3, 17]</th></tr>
+<tr><th>IOI1:O1INV</th><th>[0, 3, 31]</th></tr>
+<tr><th>IOI1:O2INV</th><th>[0, 3, 33]</th></tr>
+<tr><th>IOI1:T1INV</th><th>[0, 3, 35]</th></tr>
+<tr><th>IOI1:T2INV</th><th>[0, 3, 37]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:OFF2_LATCH"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:OFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_LATCH</th><th>[0, 3, 14]</th></tr>
+<tr><th>IOI1:OFF2_LATCH</th><th>[0, 3, 34]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_B-IOI0:OFF2_SRVAL"></div>
+<div id="bits-xc2v-IOI.CLK_B-IOI1:OFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_SRVAL</th><th>[0, 3, 18]</th></tr>
+<tr><th>IOI1:OFF2_SRVAL</th><th>[0, 3, 38]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+</section>
+<section id="ioi-clk-t-virtex-2">
+<h3><code class="docutils literal notranslate"><span class="pre">IOI.CLK_T</span></code> — Virtex 2<a class="headerlink" href="#ioi-clk-t-virtex-2" title="Link to this heading"></a></h3>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>5</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>8</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>9</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>10</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>11</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>12</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>13</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>14</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>15</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>16</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>17</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>18</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>19</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>22</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>23</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>24</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>25</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>26</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>27</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>28</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>29</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>30</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>31</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>36</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>40</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:IFF1_SRVAL" title="~IOI2:IFF1_SRVAL">~IOI2:IFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:IFF_SR_EN" title="IOI2:IFF_SR_EN">IOI2:IFF_SR_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:ICLK2INV" title="~IOI2:ICLK2INV">~IOI2:ICLK2INV</a></td></tr>
+<tr><td>41</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:TFF1_LATCH" title="IOI2:TFF1_LATCH">IOI2:TFF1_LATCH</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:IFF_REV_EN" title="IOI2:IFF_REV_EN">IOI2:IFF_REV_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:OFF1_SRVAL" title="~IOI2:OFF1_SRVAL">~IOI2:OFF1_SRVAL</a></td></tr>
+<tr><td>42</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:TFF1_SRVAL" title="~IOI2:TFF1_SRVAL">~IOI2:TFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:TFF_REV_EN" title="IOI2:TFF_REV_EN">IOI2:TFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:OFF_REV_EN" title="IOI2:OFF_REV_EN">IOI2:OFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:REVINV" title="~IOI2:REVINV">~IOI2:REVINV</a></td></tr>
+<tr><td>43</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:TSBYPASS_MUX" title="IOI2:TSBYPASS_MUX">IOI2:TSBYPASS_MUX</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:TFF_SR_EN" title="IOI2:TFF_SR_EN">IOI2:TFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:OFF_SR_EN" title="IOI2:OFF_SR_EN">IOI2:OFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:OMUX" title="IOI2:OMUX[2]">IOI2:OMUX[2]</a></td></tr>
+<tr><td>44</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:I_DELAY_EN" title="IOI2:I_DELAY_EN">IOI2:I_DELAY_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:TCEINV" title="~IOI2:TCEINV">~IOI2:TCEINV</a></td></tr>
+<tr><td>45</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:TMUX" title="IOI2:TMUX[0]">IOI2:TMUX[0]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:OMUX" title="IOI2:OMUX[0]">IOI2:OMUX[0]</a></td></tr>
+<tr><td>46</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:I_TSBYPASS_EN" title="IOI2:I_TSBYPASS_EN">IOI2:I_TSBYPASS_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:ICEINV" title="~IOI2:ICEINV">~IOI2:ICEINV</a></td></tr>
+<tr><td>47</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:TMUX" title="IOI2:TMUX[2]">IOI2:TMUX[2]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:OFF1_LATCH" title="IOI2:OFF1_LATCH">IOI2:OFF1_LATCH</a></td></tr>
+<tr><td>48</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:OFF_SYNC" title="IOI2:OFF_SYNC">IOI2:OFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:ICLK1INV" title="~IOI2:ICLK1INV">~IOI2:ICLK1INV</a></td></tr>
+<tr><td>49</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:IFF_TSBYPASS_EN" title="IOI2:IFF_TSBYPASS_EN">IOI2:IFF_TSBYPASS_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:IFF1_INIT" title="~IOI2:IFF1_INIT">~IOI2:IFF1_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:OTCLK2INV" title="~IOI2:OTCLK2INV">~IOI2:OTCLK2INV</a></td></tr>
+<tr><td>50</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:TFF_SYNC" title="IOI2:TFF_SYNC">IOI2:TFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:OMUX" title="IOI2:OMUX[1]">IOI2:OMUX[1]</a></td></tr>
+<tr><td>51</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:IFF_DELAY_EN" title="IOI2:IFF_DELAY_EN">IOI2:IFF_DELAY_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:O1INV" title="IOI2:O1INV">IOI2:O1INV</a></td></tr>
+<tr><td>52</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:IFF_SYNC" title="IOI2:IFF_SYNC">IOI2:IFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:OMUX" title="IOI2:OMUX[3]">IOI2:OMUX[3]</a></td></tr>
+<tr><td>53</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:TMUX" title="IOI2:TMUX[3]">IOI2:TMUX[3]</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:IFF2_INIT" title="~IOI2:IFF2_INIT">~IOI2:IFF2_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:O2INV" title="IOI2:O2INV">IOI2:O2INV</a></td></tr>
+<tr><td>54</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:IFF_LATCH" title="IOI2:IFF_LATCH">IOI2:IFF_LATCH</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:OFF2_LATCH" title="IOI2:OFF2_LATCH">IOI2:OFF2_LATCH</a></td></tr>
+<tr><td>55</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:TMUX" title="IOI2:TMUX[1]">IOI2:TMUX[1]</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:TFF_INIT" title="~IOI2:TFF_INIT">~IOI2:TFF_INIT</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:OFF_INIT" title="~IOI2:OFF_INIT">~IOI2:OFF_INIT</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:T1INV" title="IOI2:T1INV">IOI2:T1INV</a></td></tr>
+<tr><td>56</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:TFF2_LATCH" title="IOI2:TFF2_LATCH">IOI2:TFF2_LATCH</a></td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>57</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:TFF2_SRVAL" title="~IOI2:TFF2_SRVAL">~IOI2:TFF2_SRVAL</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:T2INV" title="IOI2:T2INV">IOI2:T2INV</a></td></tr>
+<tr><td>58</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI2:IFF2_SRVAL" title="~IOI2:IFF2_SRVAL">~IOI2:IFF2_SRVAL</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:OFF2_SRVAL" title="~IOI2:OFF2_SRVAL">~IOI2:OFF2_SRVAL</a></td></tr>
+<tr><td>59</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:IFF1_SRVAL" title="~IOI3:IFF1_SRVAL">~IOI3:IFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:IFF_SR_EN" title="IOI3:IFF_SR_EN">IOI3:IFF_SR_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI2:OTCLK1INV" title="~IOI2:OTCLK1INV">~IOI2:OTCLK1INV</a></td></tr>
+<tr><td>60</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:TFF1_SRVAL" title="~IOI3:TFF1_SRVAL">~IOI3:TFF1_SRVAL</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:IFF_REV_EN" title="IOI3:IFF_REV_EN">IOI3:IFF_REV_EN</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:ICLK2INV" title="~IOI3:ICLK2INV">~IOI3:ICLK2INV</a></td></tr>
+<tr><td>61</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:TMUX" title="IOI3:TMUX[0]">IOI3:TMUX[0]</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:TFF_REV_EN" title="IOI3:TFF_REV_EN">IOI3:TFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:OFF_REV_EN" title="IOI3:OFF_REV_EN">IOI3:OFF_REV_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:OFF1_SRVAL" title="~IOI3:OFF1_SRVAL">~IOI3:OFF1_SRVAL</a></td></tr>
+<tr><td>62</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:TFF1_LATCH" title="IOI3:TFF1_LATCH">IOI3:TFF1_LATCH</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:TFF_SR_EN" title="IOI3:TFF_SR_EN">IOI3:TFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:OFF_SR_EN" title="IOI3:OFF_SR_EN">IOI3:OFF_SR_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:REVINV" title="~IOI3:REVINV">~IOI3:REVINV</a></td></tr>
+<tr><td>63</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:TSBYPASS_MUX" title="IOI3:TSBYPASS_MUX">IOI3:TSBYPASS_MUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:OMUX" title="IOI3:OMUX[2]">IOI3:OMUX[2]</a></td></tr>
+<tr><td>64</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:I_DELAY_EN" title="IOI3:I_DELAY_EN">IOI3:I_DELAY_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:TCEINV" title="~IOI3:TCEINV">~IOI3:TCEINV</a></td></tr>
+<tr><td>65</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:TMUX" title="IOI3:TMUX[2]">IOI3:TMUX[2]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:OMUX" title="IOI3:OMUX[0]">IOI3:OMUX[0]</a></td></tr>
+<tr><td>66</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:I_TSBYPASS_EN" title="IOI3:I_TSBYPASS_EN">IOI3:I_TSBYPASS_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:ICEINV" title="~IOI3:ICEINV">~IOI3:ICEINV</a></td></tr>
+<tr><td>67</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:OFF_SYNC" title="IOI3:OFF_SYNC">IOI3:OFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:OFF1_LATCH" title="IOI3:OFF1_LATCH">IOI3:OFF1_LATCH</a></td></tr>
+<tr><td>68</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:TFF_SYNC" title="IOI3:TFF_SYNC">IOI3:TFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:ICLK1INV" title="~IOI3:ICLK1INV">~IOI3:ICLK1INV</a></td></tr>
+<tr><td>69</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:IFF_TSBYPASS_EN" title="IOI3:IFF_TSBYPASS_EN">IOI3:IFF_TSBYPASS_EN</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:IFF1_INIT" title="~IOI3:IFF1_INIT">~IOI3:IFF1_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:OTCLK2INV" title="~IOI3:OTCLK2INV">~IOI3:OTCLK2INV</a></td></tr>
+<tr><td>70</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:IFF_SYNC" title="IOI3:IFF_SYNC">IOI3:IFF_SYNC</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:OMUX" title="IOI3:OMUX[1]">IOI3:OMUX[1]</a></td></tr>
+<tr><td>71</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:IFF_DELAY_EN" title="IOI3:IFF_DELAY_EN">IOI3:IFF_DELAY_EN</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:O1INV" title="IOI3:O1INV">IOI3:O1INV</a></td></tr>
+<tr><td>72</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:TMUX" title="IOI3:TMUX[3]">IOI3:TMUX[3]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:OMUX" title="IOI3:OMUX[3]">IOI3:OMUX[3]</a></td></tr>
+<tr><td>73</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:IFF_LATCH" title="IOI3:IFF_LATCH">IOI3:IFF_LATCH</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:IFF2_INIT" title="~IOI3:IFF2_INIT">~IOI3:IFF2_INIT</a></td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:O2INV" title="IOI3:O2INV">IOI3:O2INV</a></td></tr>
+<tr><td>74</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:TMUX" title="IOI3:TMUX[1]">IOI3:TMUX[1]</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:OFF2_LATCH" title="IOI3:OFF2_LATCH">IOI3:OFF2_LATCH</a></td></tr>
+<tr><td>75</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:TFF2_LATCH" title="IOI3:TFF2_LATCH">IOI3:TFF2_LATCH</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:TFF_INIT" title="~IOI3:TFF_INIT">~IOI3:TFF_INIT</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:OFF_INIT" title="~IOI3:OFF_INIT">~IOI3:OFF_INIT</a></td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:T1INV" title="IOI3:T1INV">IOI3:T1INV</a></td></tr>
+<tr><td>76</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:TFF2_SRVAL" title="~IOI3:TFF2_SRVAL">~IOI3:TFF2_SRVAL</a></td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>77</td>
+<td><a href="#bits-xc2v-IOI.CLK_T-IOI3:IFF2_SRVAL" title="~IOI3:IFF2_SRVAL">~IOI3:IFF2_SRVAL</a></td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:T2INV" title="IOI3:T2INV">IOI3:T2INV</a></td></tr>
+<tr><td>78</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:OFF2_SRVAL" title="~IOI3:OFF2_SRVAL">~IOI3:OFF2_SRVAL</a></td></tr>
+<tr><td>79</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc2v-IOI.CLK_T-IOI3:OTCLK1INV" title="~IOI3:OTCLK1INV">~IOI3:OTCLK1INV</a></td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:IFF1_SRVAL"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:IFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:IFF1_SRVAL</th><th>[0, 0, 40]</th></tr>
+<tr><th>IOI3:IFF1_SRVAL</th><th>[0, 0, 59]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:TFF1_LATCH"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:TFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:TFF1_LATCH</th><th>[0, 0, 41]</th></tr>
+<tr><th>IOI3:TFF1_LATCH</th><th>[0, 0, 62]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:TFF1_SRVAL"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:TFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:TFF1_SRVAL</th><th>[0, 0, 42]</th></tr>
+<tr><th>IOI3:TFF1_SRVAL</th><th>[0, 0, 60]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:TSBYPASS_MUX"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:TSBYPASS_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:TSBYPASS_MUX</th><th>[0, 0, 43]</th></tr>
+<tr><th>IOI3:TSBYPASS_MUX</th><th>[0, 0, 63]</th></tr>
+<tr><td>TMUX</td><td>0</td></tr>
+<tr><td>GND</td><td>1</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:I_DELAY_EN"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:I_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:I_DELAY_EN</th><th>[0, 0, 44]</th></tr>
+<tr><th>IOI3:I_DELAY_EN</th><th>[0, 0, 64]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:TMUX"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:TMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:TMUX</th><th>[0, 0, 53]</th><th>[0, 0, 47]</th><th>[0, 0, 55]</th><th>[0, 0, 45]</th></tr>
+<tr><th>IOI3:TMUX</th><th>[0, 0, 72]</th><th>[0, 0, 65]</th><th>[0, 0, 74]</th><th>[0, 0, 61]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>T1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>T2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>TFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>TFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>TFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:I_TSBYPASS_EN"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:I_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:I_TSBYPASS_EN</th><th>[0, 0, 46]</th></tr>
+<tr><th>IOI3:I_TSBYPASS_EN</th><th>[0, 0, 66]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:OFF_SYNC"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:OFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:OFF_SYNC</th><th>[0, 0, 48]</th></tr>
+<tr><th>IOI3:OFF_SYNC</th><th>[0, 0, 67]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:IFF_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:IFF_TSBYPASS_EN</th><th>[0, 0, 49]</th></tr>
+<tr><th>IOI3:IFF_TSBYPASS_EN</th><th>[0, 0, 69]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:TFF_SYNC"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:TFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:TFF_SYNC</th><th>[0, 0, 50]</th></tr>
+<tr><th>IOI3:TFF_SYNC</th><th>[0, 0, 68]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:IFF_DELAY_EN"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:IFF_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:IFF_DELAY_EN</th><th>[0, 0, 51]</th></tr>
+<tr><th>IOI3:IFF_DELAY_EN</th><th>[0, 0, 71]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:IFF_SYNC"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:IFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:IFF_SYNC</th><th>[0, 0, 52]</th></tr>
+<tr><th>IOI3:IFF_SYNC</th><th>[0, 0, 70]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:IFF_LATCH"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:IFF_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:IFF_LATCH</th><th>[0, 0, 54]</th></tr>
+<tr><th>IOI3:IFF_LATCH</th><th>[0, 0, 73]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:TFF2_LATCH"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:TFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:TFF2_LATCH</th><th>[0, 0, 56]</th></tr>
+<tr><th>IOI3:TFF2_LATCH</th><th>[0, 0, 75]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:TFF2_SRVAL"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:TFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:TFF2_SRVAL</th><th>[0, 0, 57]</th></tr>
+<tr><th>IOI3:TFF2_SRVAL</th><th>[0, 0, 76]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:IFF2_SRVAL"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:IFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:IFF2_SRVAL</th><th>[0, 0, 58]</th></tr>
+<tr><th>IOI3:IFF2_SRVAL</th><th>[0, 0, 77]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:IFF_SR_EN"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:IFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:IFF_SR_EN</th><th>[0, 1, 40]</th></tr>
+<tr><th>IOI3:IFF_SR_EN</th><th>[0, 1, 59]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:IFF_REV_EN"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:IFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:IFF_REV_EN</th><th>[0, 1, 41]</th></tr>
+<tr><th>IOI3:IFF_REV_EN</th><th>[0, 1, 60]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:TFF_REV_EN"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:TFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:TFF_REV_EN</th><th>[0, 1, 42]</th></tr>
+<tr><th>IOI3:TFF_REV_EN</th><th>[0, 1, 61]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:TFF_SR_EN"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:TFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:TFF_SR_EN</th><th>[0, 1, 43]</th></tr>
+<tr><th>IOI3:TFF_SR_EN</th><th>[0, 1, 62]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:IFF1_INIT"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:IFF1_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:IFF1_INIT</th><th>[0, 1, 49]</th></tr>
+<tr><th>IOI3:IFF1_INIT</th><th>[0, 1, 69]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:IFF2_INIT"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:IFF2_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:IFF2_INIT</th><th>[0, 1, 53]</th></tr>
+<tr><th>IOI3:IFF2_INIT</th><th>[0, 1, 73]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:TFF_INIT"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:TFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:TFF_INIT</th><th>[0, 1, 55]</th></tr>
+<tr><th>IOI3:TFF_INIT</th><th>[0, 1, 75]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:OFF_REV_EN"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:OFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:OFF_REV_EN</th><th>[0, 2, 42]</th></tr>
+<tr><th>IOI3:OFF_REV_EN</th><th>[0, 2, 61]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:OFF_SR_EN"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:OFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:OFF_SR_EN</th><th>[0, 2, 43]</th></tr>
+<tr><th>IOI3:OFF_SR_EN</th><th>[0, 2, 62]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:OFF_INIT"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:OFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:OFF_INIT</th><th>[0, 2, 55]</th></tr>
+<tr><th>IOI3:OFF_INIT</th><th>[0, 2, 75]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:ICEINV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:ICLK1INV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:ICLK2INV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:OTCLK1INV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:OTCLK2INV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:REVINV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:TCEINV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:ICEINV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:ICLK1INV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:ICLK2INV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:OTCLK1INV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:OTCLK2INV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:REVINV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:TCEINV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:ICEINV</th><th>[0, 3, 46]</th></tr>
+<tr><th>IOI2:ICLK1INV</th><th>[0, 3, 48]</th></tr>
+<tr><th>IOI2:ICLK2INV</th><th>[0, 3, 40]</th></tr>
+<tr><th>IOI2:OTCLK1INV</th><th>[0, 3, 59]</th></tr>
+<tr><th>IOI2:OTCLK2INV</th><th>[0, 3, 49]</th></tr>
+<tr><th>IOI2:REVINV</th><th>[0, 3, 42]</th></tr>
+<tr><th>IOI2:TCEINV</th><th>[0, 3, 44]</th></tr>
+<tr><th>IOI3:ICEINV</th><th>[0, 3, 66]</th></tr>
+<tr><th>IOI3:ICLK1INV</th><th>[0, 3, 68]</th></tr>
+<tr><th>IOI3:ICLK2INV</th><th>[0, 3, 60]</th></tr>
+<tr><th>IOI3:OTCLK1INV</th><th>[0, 3, 79]</th></tr>
+<tr><th>IOI3:OTCLK2INV</th><th>[0, 3, 69]</th></tr>
+<tr><th>IOI3:REVINV</th><th>[0, 3, 62]</th></tr>
+<tr><th>IOI3:TCEINV</th><th>[0, 3, 64]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:OFF1_SRVAL"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:OFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:OFF1_SRVAL</th><th>[0, 3, 41]</th></tr>
+<tr><th>IOI3:OFF1_SRVAL</th><th>[0, 3, 61]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:OMUX"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:OMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:OMUX</th><th>[0, 3, 52]</th><th>[0, 3, 43]</th><th>[0, 3, 50]</th><th>[0, 3, 45]</th></tr>
+<tr><th>IOI3:OMUX</th><th>[0, 3, 72]</th><th>[0, 3, 63]</th><th>[0, 3, 70]</th><th>[0, 3, 65]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>O1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>O2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:OFF1_LATCH"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:OFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:OFF1_LATCH</th><th>[0, 3, 47]</th></tr>
+<tr><th>IOI3:OFF1_LATCH</th><th>[0, 3, 67]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:O1INV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:O2INV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:T1INV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:T2INV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:O1INV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:O2INV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:T1INV"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:T2INV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:O1INV</th><th>[0, 3, 51]</th></tr>
+<tr><th>IOI2:O2INV</th><th>[0, 3, 53]</th></tr>
+<tr><th>IOI2:T1INV</th><th>[0, 3, 55]</th></tr>
+<tr><th>IOI2:T2INV</th><th>[0, 3, 57]</th></tr>
+<tr><th>IOI3:O1INV</th><th>[0, 3, 71]</th></tr>
+<tr><th>IOI3:O2INV</th><th>[0, 3, 73]</th></tr>
+<tr><th>IOI3:T1INV</th><th>[0, 3, 75]</th></tr>
+<tr><th>IOI3:T2INV</th><th>[0, 3, 77]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:OFF2_LATCH"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:OFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:OFF2_LATCH</th><th>[0, 3, 54]</th></tr>
+<tr><th>IOI3:OFF2_LATCH</th><th>[0, 3, 74]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc2v-IOI.CLK_T-IOI2:OFF2_SRVAL"></div>
+<div id="bits-xc2v-IOI.CLK_T-IOI3:OFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI2:OFF2_SRVAL</th><th>[0, 3, 58]</th></tr>
+<tr><th>IOI3:OFF2_SRVAL</th><th>[0, 3, 78]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+</section>
+<section id="ioi-s3">
+<h3><code class="docutils literal notranslate"><span class="pre">IOI.S3</span></code><a class="headerlink" href="#ioi-s3" title="Link to this heading"></a></h3>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI0:IFF_DELAY_EN" title="IOI0:IFF_DELAY_EN">IOI0:IFF_DELAY_EN</a></td></tr>
+<tr><td>2</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>3</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI0:TFF1_SRVAL" title="~IOI0:TFF1_SRVAL">~IOI0:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:OFF1_SRVAL" title="~IOI0:OFF1_SRVAL">~IOI0:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:IFF1_SRVAL" title="~IOI0:IFF1_SRVAL">~IOI0:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:IFF_TSBYPASS_EN" title="IOI0:IFF_TSBYPASS_EN">IOI0:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI0:TSBYPASS_MUX" title="IOI0:TSBYPASS_MUX">IOI0:TSBYPASS_MUX</a></td></tr>
+<tr><td>5</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI0:TFF2_SRVAL" title="~IOI0:TFF2_SRVAL">~IOI0:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:OFF2_SRVAL" title="~IOI0:OFF2_SRVAL">~IOI0:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI0:IFF1_INIT" title="~IOI0:IFF1_INIT">~IOI0:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:I_TSBYPASS_EN" title="IOI0:I_TSBYPASS_EN">IOI0:I_TSBYPASS_EN</a></td></tr>
+<tr><td>8</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI0:TFF_INIT" title="~IOI0:TFF_INIT">~IOI0:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:OFF_INIT" title="~IOI0:OFF_INIT">~IOI0:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:IFF_SYNC" title="IOI0:IFF_SYNC">IOI0:IFF_SYNC</a></td><td>-</td></tr>
+<tr><td>9</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI0:TFF_REV_EN" title="IOI0:TFF_REV_EN">IOI0:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:OFF_REV_EN" title="IOI0:OFF_REV_EN">IOI0:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:IFF_REV_EN" title="IOI0:IFF_REV_EN">IOI0:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>10</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI0:TFF_SR_EN" title="IOI0:TFF_SR_EN">IOI0:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:OFF_SR_EN" title="IOI0:OFF_SR_EN">IOI0:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:IFF_SR_EN" title="IOI0:IFF_SR_EN">IOI0:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:I_DELAY_EN" title="IOI0:I_DELAY_EN">IOI0:I_DELAY_EN</a></td></tr>
+<tr><td>11</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI0:T2INV" title="IOI0:T2INV">IOI0:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:O2INV" title="IOI0:O2INV">IOI0:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:IFF_LATCH" title="IOI0:IFF_LATCH">IOI0:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:REVINV" title="~IOI0:REVINV">~IOI0:REVINV</a></td></tr>
+<tr><td>12</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI0:T1INV" title="IOI0:T1INV">IOI0:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:O1INV" title="IOI0:O1INV">IOI0:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:IFF2_INIT" title="~IOI0:IFF2_INIT">~IOI0:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:ICLK2INV" title="~IOI0:ICLK2INV">~IOI0:ICLK2INV</a></td></tr>
+<tr><td>13</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI0:TFF_SYNC" title="IOI0:TFF_SYNC">IOI0:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:OFF_SYNC" title="IOI0:OFF_SYNC">IOI0:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI0:ICLK1INV" title="~IOI0:ICLK1INV">~IOI0:ICLK1INV</a></td></tr>
+<tr><td>14</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI0:TMUX" title="IOI0:TMUX[1]">IOI0:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:OMUX" title="IOI0:OMUX[1]">IOI0:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI0:ICEINV" title="~IOI0:ICEINV">~IOI0:ICEINV</a></td></tr>
+<tr><td>15</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI0:TMUX" title="IOI0:TMUX[3]">IOI0:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:OMUX" title="IOI0:OMUX[3]">IOI0:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI0:OTCLK2INV" title="~IOI0:OTCLK2INV">~IOI0:OTCLK2INV</a></td></tr>
+<tr><td>16</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI0:TMUX" title="IOI0:TMUX[0]">IOI0:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:OMUX" title="IOI0:OMUX[0]">IOI0:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:IFF2_SRVAL" title="~IOI0:IFF2_SRVAL">~IOI0:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:OTCLK1INV" title="~IOI0:OTCLK1INV">~IOI0:OTCLK1INV</a></td></tr>
+<tr><td>17</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI0:TFF1_LATCH" title="IOI0:TFF1_LATCH">IOI0:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:OFF1_LATCH" title="IOI0:OFF1_LATCH">IOI0:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI0:TCEINV" title="~IOI0:TCEINV">~IOI0:TCEINV</a></td></tr>
+<tr><td>18</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI0:TFF2_LATCH" title="IOI0:TFF2_LATCH">IOI0:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:OFF2_LATCH" title="IOI0:OFF2_LATCH">IOI0:OFF2_LATCH</a></td><td>-</td><td>-</td></tr>
+<tr><td>19</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI0:TMUX" title="IOI0:TMUX[2]">IOI0:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3-IOI0:OMUX" title="IOI0:OMUX[2]">IOI0:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI1:TMUX" title="IOI1:TMUX[2]">IOI1:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:OMUX" title="IOI1:OMUX[2]">IOI1:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI1:TFF2_LATCH" title="IOI1:TFF2_LATCH">IOI1:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:OFF2_LATCH" title="IOI1:OFF2_LATCH">IOI1:OFF2_LATCH</a></td><td>-</td><td>-</td></tr>
+<tr><td>22</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI1:TFF1_LATCH" title="IOI1:TFF1_LATCH">IOI1:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:OFF1_LATCH" title="IOI1:OFF1_LATCH">IOI1:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI1:TCEINV" title="~IOI1:TCEINV">~IOI1:TCEINV</a></td></tr>
+<tr><td>23</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI1:TMUX" title="IOI1:TMUX[0]">IOI1:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:OMUX" title="IOI1:OMUX[0]">IOI1:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:IFF2_SRVAL" title="~IOI1:IFF2_SRVAL">~IOI1:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:OTCLK1INV" title="~IOI1:OTCLK1INV">~IOI1:OTCLK1INV</a></td></tr>
+<tr><td>24</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI1:TMUX" title="IOI1:TMUX[3]">IOI1:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:OMUX" title="IOI1:OMUX[3]">IOI1:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI1:OTCLK2INV" title="~IOI1:OTCLK2INV">~IOI1:OTCLK2INV</a></td></tr>
+<tr><td>25</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI1:TMUX" title="IOI1:TMUX[1]">IOI1:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:OMUX" title="IOI1:OMUX[1]">IOI1:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI1:ICEINV" title="~IOI1:ICEINV">~IOI1:ICEINV</a></td></tr>
+<tr><td>26</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI1:TFF_SYNC" title="IOI1:TFF_SYNC">IOI1:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:OFF_SYNC" title="IOI1:OFF_SYNC">IOI1:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI1:ICLK1INV" title="~IOI1:ICLK1INV">~IOI1:ICLK1INV</a></td></tr>
+<tr><td>27</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI1:T1INV" title="IOI1:T1INV">IOI1:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:O1INV" title="IOI1:O1INV">IOI1:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:IFF2_INIT" title="~IOI1:IFF2_INIT">~IOI1:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:ICLK2INV" title="~IOI1:ICLK2INV">~IOI1:ICLK2INV</a></td></tr>
+<tr><td>28</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI1:T2INV" title="IOI1:T2INV">IOI1:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:O2INV" title="IOI1:O2INV">IOI1:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:IFF_LATCH" title="IOI1:IFF_LATCH">IOI1:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:REVINV" title="~IOI1:REVINV">~IOI1:REVINV</a></td></tr>
+<tr><td>29</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI1:TFF_SR_EN" title="IOI1:TFF_SR_EN">IOI1:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:OFF_SR_EN" title="IOI1:OFF_SR_EN">IOI1:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:IFF_SR_EN" title="IOI1:IFF_SR_EN">IOI1:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:I_DELAY_EN" title="IOI1:I_DELAY_EN">IOI1:I_DELAY_EN</a></td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI1:TFF_REV_EN" title="IOI1:TFF_REV_EN">IOI1:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:OFF_REV_EN" title="IOI1:OFF_REV_EN">IOI1:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:IFF_REV_EN" title="IOI1:IFF_REV_EN">IOI1:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>31</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI1:TFF_INIT" title="~IOI1:TFF_INIT">~IOI1:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:OFF_INIT" title="~IOI1:OFF_INIT">~IOI1:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:IFF_SYNC" title="IOI1:IFF_SYNC">IOI1:IFF_SYNC</a></td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI1:IFF1_INIT" title="~IOI1:IFF1_INIT">~IOI1:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:I_TSBYPASS_EN" title="IOI1:I_TSBYPASS_EN">IOI1:I_TSBYPASS_EN</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI1:TFF2_SRVAL" title="~IOI1:TFF2_SRVAL">~IOI1:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:OFF2_SRVAL" title="~IOI1:OFF2_SRVAL">~IOI1:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI1:TSBYPASS_MUX" title="IOI1:TSBYPASS_MUX">IOI1:TSBYPASS_MUX</a></td></tr>
+<tr><td>36</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI1:TFF1_SRVAL" title="~IOI1:TFF1_SRVAL">~IOI1:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:OFF1_SRVAL" title="~IOI1:OFF1_SRVAL">~IOI1:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:IFF1_SRVAL" title="~IOI1:IFF1_SRVAL">~IOI1:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3-IOI1:IFF_TSBYPASS_EN" title="IOI1:IFF_TSBYPASS_EN">IOI1:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>37</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI1:IFF_DELAY_EN" title="IOI1:IFF_DELAY_EN">IOI1:IFF_DELAY_EN</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI2:IFF_DELAY_EN" title="IOI2:IFF_DELAY_EN">IOI2:IFF_DELAY_EN</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>43</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI2:TFF1_SRVAL" title="~IOI2:TFF1_SRVAL">~IOI2:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:OFF1_SRVAL" title="~IOI2:OFF1_SRVAL">~IOI2:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:IFF1_SRVAL" title="~IOI2:IFF1_SRVAL">~IOI2:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:IFF_TSBYPASS_EN" title="IOI2:IFF_TSBYPASS_EN">IOI2:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI2:TSBYPASS_MUX" title="IOI2:TSBYPASS_MUX">IOI2:TSBYPASS_MUX</a></td></tr>
+<tr><td>45</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI2:TFF2_SRVAL" title="~IOI2:TFF2_SRVAL">~IOI2:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:OFF2_SRVAL" title="~IOI2:OFF2_SRVAL">~IOI2:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI2:IFF1_INIT" title="~IOI2:IFF1_INIT">~IOI2:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:I_TSBYPASS_EN" title="IOI2:I_TSBYPASS_EN">IOI2:I_TSBYPASS_EN</a></td></tr>
+<tr><td>48</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI2:TFF_INIT" title="~IOI2:TFF_INIT">~IOI2:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:OFF_INIT" title="~IOI2:OFF_INIT">~IOI2:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:IFF_SYNC" title="IOI2:IFF_SYNC">IOI2:IFF_SYNC</a></td><td>-</td></tr>
+<tr><td>49</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI2:TFF_REV_EN" title="IOI2:TFF_REV_EN">IOI2:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:OFF_REV_EN" title="IOI2:OFF_REV_EN">IOI2:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:IFF_REV_EN" title="IOI2:IFF_REV_EN">IOI2:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>50</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI2:TFF_SR_EN" title="IOI2:TFF_SR_EN">IOI2:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:OFF_SR_EN" title="IOI2:OFF_SR_EN">IOI2:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:IFF_SR_EN" title="IOI2:IFF_SR_EN">IOI2:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:I_DELAY_EN" title="IOI2:I_DELAY_EN">IOI2:I_DELAY_EN</a></td></tr>
+<tr><td>51</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI2:T2INV" title="IOI2:T2INV">IOI2:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:O2INV" title="IOI2:O2INV">IOI2:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:IFF_LATCH" title="IOI2:IFF_LATCH">IOI2:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:REVINV" title="~IOI2:REVINV">~IOI2:REVINV</a></td></tr>
+<tr><td>52</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI2:T1INV" title="IOI2:T1INV">IOI2:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:O1INV" title="IOI2:O1INV">IOI2:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:IFF2_INIT" title="~IOI2:IFF2_INIT">~IOI2:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:ICLK2INV" title="~IOI2:ICLK2INV">~IOI2:ICLK2INV</a></td></tr>
+<tr><td>53</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI2:TFF_SYNC" title="IOI2:TFF_SYNC">IOI2:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:OFF_SYNC" title="IOI2:OFF_SYNC">IOI2:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI2:ICLK1INV" title="~IOI2:ICLK1INV">~IOI2:ICLK1INV</a></td></tr>
+<tr><td>54</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI2:TMUX" title="IOI2:TMUX[1]">IOI2:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:OMUX" title="IOI2:OMUX[1]">IOI2:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI2:ICEINV" title="~IOI2:ICEINV">~IOI2:ICEINV</a></td></tr>
+<tr><td>55</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI2:TMUX" title="IOI2:TMUX[3]">IOI2:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:OMUX" title="IOI2:OMUX[3]">IOI2:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI2:OTCLK2INV" title="~IOI2:OTCLK2INV">~IOI2:OTCLK2INV</a></td></tr>
+<tr><td>56</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI2:TMUX" title="IOI2:TMUX[0]">IOI2:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:OMUX" title="IOI2:OMUX[0]">IOI2:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:IFF2_SRVAL" title="~IOI2:IFF2_SRVAL">~IOI2:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:OTCLK1INV" title="~IOI2:OTCLK1INV">~IOI2:OTCLK1INV</a></td></tr>
+<tr><td>57</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI2:TFF1_LATCH" title="IOI2:TFF1_LATCH">IOI2:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:OFF1_LATCH" title="IOI2:OFF1_LATCH">IOI2:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3-IOI2:TCEINV" title="~IOI2:TCEINV">~IOI2:TCEINV</a></td></tr>
+<tr><td>58</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI2:TFF2_LATCH" title="IOI2:TFF2_LATCH">IOI2:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:OFF2_LATCH" title="IOI2:OFF2_LATCH">IOI2:OFF2_LATCH</a></td><td>-</td><td>-</td></tr>
+<tr><td>59</td>
+<td><a href="#bits-xc3s-IOI.S3-IOI2:TMUX" title="IOI2:TMUX[2]">IOI2:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3-IOI2:OMUX" title="IOI2:OMUX[2]">IOI2:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:TFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_SRVAL</th><th>[0, 0, 3]</th></tr>
+<tr><th>IOI1:TFF1_SRVAL</th><th>[0, 0, 36]</th></tr>
+<tr><th>IOI2:TFF1_SRVAL</th><th>[0, 0, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:TFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_SRVAL</th><th>[0, 0, 5]</th></tr>
+<tr><th>IOI1:TFF2_SRVAL</th><th>[0, 0, 34]</th></tr>
+<tr><th>IOI2:TFF2_SRVAL</th><th>[0, 0, 45]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:TFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_INIT</th><th>[0, 0, 8]</th></tr>
+<tr><th>IOI1:TFF_INIT</th><th>[0, 0, 31]</th></tr>
+<tr><th>IOI2:TFF_INIT</th><th>[0, 0, 48]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:TFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_REV_EN</th><th>[0, 0, 9]</th></tr>
+<tr><th>IOI1:TFF_REV_EN</th><th>[0, 0, 30]</th></tr>
+<tr><th>IOI2:TFF_REV_EN</th><th>[0, 0, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:TFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SR_EN</th><th>[0, 0, 10]</th></tr>
+<tr><th>IOI1:TFF_SR_EN</th><th>[0, 0, 29]</th></tr>
+<tr><th>IOI2:TFF_SR_EN</th><th>[0, 0, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:O1INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI0:O2INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI0:T1INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI0:T2INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:O1INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:O2INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:T1INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:T2INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:O1INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:O2INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:T1INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:T2INV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1INV</th><th>[0, 1, 12]</th></tr>
+<tr><th>IOI0:O2INV</th><th>[0, 1, 11]</th></tr>
+<tr><th>IOI0:T1INV</th><th>[0, 0, 12]</th></tr>
+<tr><th>IOI0:T2INV</th><th>[0, 0, 11]</th></tr>
+<tr><th>IOI1:O1INV</th><th>[0, 1, 27]</th></tr>
+<tr><th>IOI1:O2INV</th><th>[0, 1, 28]</th></tr>
+<tr><th>IOI1:T1INV</th><th>[0, 0, 27]</th></tr>
+<tr><th>IOI1:T2INV</th><th>[0, 0, 28]</th></tr>
+<tr><th>IOI2:O1INV</th><th>[0, 1, 52]</th></tr>
+<tr><th>IOI2:O2INV</th><th>[0, 1, 51]</th></tr>
+<tr><th>IOI2:T1INV</th><th>[0, 0, 52]</th></tr>
+<tr><th>IOI2:T2INV</th><th>[0, 0, 51]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:TFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SYNC</th><th>[0, 0, 13]</th></tr>
+<tr><th>IOI1:TFF_SYNC</th><th>[0, 0, 26]</th></tr>
+<tr><th>IOI2:TFF_SYNC</th><th>[0, 0, 53]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:TMUX"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:TMUX"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:TMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TMUX</th><th>[0, 0, 15]</th><th>[0, 0, 19]</th><th>[0, 0, 14]</th><th>[0, 0, 16]</th></tr>
+<tr><th>IOI1:TMUX</th><th>[0, 0, 24]</th><th>[0, 0, 20]</th><th>[0, 0, 25]</th><th>[0, 0, 23]</th></tr>
+<tr><th>IOI2:TMUX</th><th>[0, 0, 55]</th><th>[0, 0, 59]</th><th>[0, 0, 54]</th><th>[0, 0, 56]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>T1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>T2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>TFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>TFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>TFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:TFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_LATCH</th><th>[0, 0, 17]</th></tr>
+<tr><th>IOI1:TFF1_LATCH</th><th>[0, 0, 22]</th></tr>
+<tr><th>IOI2:TFF1_LATCH</th><th>[0, 0, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:TFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_LATCH</th><th>[0, 0, 18]</th></tr>
+<tr><th>IOI1:TFF2_LATCH</th><th>[0, 0, 21]</th></tr>
+<tr><th>IOI2:TFF2_LATCH</th><th>[0, 0, 58]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:OFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_SRVAL</th><th>[0, 1, 3]</th></tr>
+<tr><th>IOI1:OFF1_SRVAL</th><th>[0, 1, 36]</th></tr>
+<tr><th>IOI2:OFF1_SRVAL</th><th>[0, 1, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:OFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_SRVAL</th><th>[0, 1, 5]</th></tr>
+<tr><th>IOI1:OFF2_SRVAL</th><th>[0, 1, 34]</th></tr>
+<tr><th>IOI2:OFF2_SRVAL</th><th>[0, 1, 45]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:OFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_INIT</th><th>[0, 1, 8]</th></tr>
+<tr><th>IOI1:OFF_INIT</th><th>[0, 1, 31]</th></tr>
+<tr><th>IOI2:OFF_INIT</th><th>[0, 1, 48]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:OFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_REV_EN</th><th>[0, 1, 9]</th></tr>
+<tr><th>IOI1:OFF_REV_EN</th><th>[0, 1, 30]</th></tr>
+<tr><th>IOI2:OFF_REV_EN</th><th>[0, 1, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:OFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SR_EN</th><th>[0, 1, 10]</th></tr>
+<tr><th>IOI1:OFF_SR_EN</th><th>[0, 1, 29]</th></tr>
+<tr><th>IOI2:OFF_SR_EN</th><th>[0, 1, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:OFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SYNC</th><th>[0, 1, 13]</th></tr>
+<tr><th>IOI1:OFF_SYNC</th><th>[0, 1, 26]</th></tr>
+<tr><th>IOI2:OFF_SYNC</th><th>[0, 1, 53]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:OMUX"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:OMUX"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:OMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OMUX</th><th>[0, 1, 15]</th><th>[0, 1, 19]</th><th>[0, 1, 14]</th><th>[0, 1, 16]</th></tr>
+<tr><th>IOI1:OMUX</th><th>[0, 1, 24]</th><th>[0, 1, 20]</th><th>[0, 1, 25]</th><th>[0, 1, 23]</th></tr>
+<tr><th>IOI2:OMUX</th><th>[0, 1, 55]</th><th>[0, 1, 59]</th><th>[0, 1, 54]</th><th>[0, 1, 56]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>O1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>O2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:OFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_LATCH</th><th>[0, 1, 17]</th></tr>
+<tr><th>IOI1:OFF1_LATCH</th><th>[0, 1, 22]</th></tr>
+<tr><th>IOI2:OFF1_LATCH</th><th>[0, 1, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:OFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_LATCH</th><th>[0, 1, 18]</th></tr>
+<tr><th>IOI1:OFF2_LATCH</th><th>[0, 1, 21]</th></tr>
+<tr><th>IOI2:OFF2_LATCH</th><th>[0, 1, 58]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:IFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_SRVAL</th><th>[0, 2, 3]</th></tr>
+<tr><th>IOI1:IFF1_SRVAL</th><th>[0, 2, 36]</th></tr>
+<tr><th>IOI2:IFF1_SRVAL</th><th>[0, 2, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:IFF1_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_INIT</th><th>[0, 2, 7]</th></tr>
+<tr><th>IOI1:IFF1_INIT</th><th>[0, 2, 32]</th></tr>
+<tr><th>IOI2:IFF1_INIT</th><th>[0, 2, 47]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:IFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SYNC</th><th>[0, 2, 8]</th></tr>
+<tr><th>IOI1:IFF_SYNC</th><th>[0, 2, 31]</th></tr>
+<tr><th>IOI2:IFF_SYNC</th><th>[0, 2, 48]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:IFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_REV_EN</th><th>[0, 2, 9]</th></tr>
+<tr><th>IOI1:IFF_REV_EN</th><th>[0, 2, 30]</th></tr>
+<tr><th>IOI2:IFF_REV_EN</th><th>[0, 2, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:IFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SR_EN</th><th>[0, 2, 10]</th></tr>
+<tr><th>IOI1:IFF_SR_EN</th><th>[0, 2, 29]</th></tr>
+<tr><th>IOI2:IFF_SR_EN</th><th>[0, 2, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:IFF_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_LATCH</th><th>[0, 2, 11]</th></tr>
+<tr><th>IOI1:IFF_LATCH</th><th>[0, 2, 28]</th></tr>
+<tr><th>IOI2:IFF_LATCH</th><th>[0, 2, 51]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:IFF2_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_INIT</th><th>[0, 2, 12]</th></tr>
+<tr><th>IOI1:IFF2_INIT</th><th>[0, 2, 27]</th></tr>
+<tr><th>IOI2:IFF2_INIT</th><th>[0, 2, 52]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:IFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_SRVAL</th><th>[0, 2, 16]</th></tr>
+<tr><th>IOI1:IFF2_SRVAL</th><th>[0, 2, 23]</th></tr>
+<tr><th>IOI2:IFF2_SRVAL</th><th>[0, 2, 56]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:IFF_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY_EN</th><th>[0, 3, 1]</th></tr>
+<tr><th>IOI1:IFF_DELAY_EN</th><th>[0, 3, 38]</th></tr>
+<tr><th>IOI2:IFF_DELAY_EN</th><th>[0, 3, 41]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:IFF_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_TSBYPASS_EN</th><th>[0, 3, 3]</th></tr>
+<tr><th>IOI1:IFF_TSBYPASS_EN</th><th>[0, 3, 36]</th></tr>
+<tr><th>IOI2:IFF_TSBYPASS_EN</th><th>[0, 3, 43]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:TSBYPASS_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TSBYPASS_MUX</th><th>[0, 3, 4]</th></tr>
+<tr><th>IOI1:TSBYPASS_MUX</th><th>[0, 3, 35]</th></tr>
+<tr><th>IOI2:TSBYPASS_MUX</th><th>[0, 3, 44]</th></tr>
+<tr><td>TMUX</td><td>0</td></tr>
+<tr><td>GND</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:I_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_TSBYPASS_EN</th><th>[0, 3, 7]</th></tr>
+<tr><th>IOI1:I_TSBYPASS_EN</th><th>[0, 3, 32]</th></tr>
+<tr><th>IOI2:I_TSBYPASS_EN</th><th>[0, 3, 47]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:I_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY_EN</th><th>[0, 3, 10]</th></tr>
+<tr><th>IOI1:I_DELAY_EN</th><th>[0, 3, 29]</th></tr>
+<tr><th>IOI2:I_DELAY_EN</th><th>[0, 3, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3-IOI0:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3-IOI0:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI0:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI0:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI0:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI0:REVINV"></div>
+<div id="bits-xc3s-IOI.S3-IOI0:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:REVINV"></div>
+<div id="bits-xc3s-IOI.S3-IOI1:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:REVINV"></div>
+<div id="bits-xc3s-IOI.S3-IOI2:TCEINV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:ICEINV</th><th>[0, 3, 14]</th></tr>
+<tr><th>IOI0:ICLK1INV</th><th>[0, 3, 13]</th></tr>
+<tr><th>IOI0:ICLK2INV</th><th>[0, 3, 12]</th></tr>
+<tr><th>IOI0:OTCLK1INV</th><th>[0, 3, 16]</th></tr>
+<tr><th>IOI0:OTCLK2INV</th><th>[0, 3, 15]</th></tr>
+<tr><th>IOI0:REVINV</th><th>[0, 3, 11]</th></tr>
+<tr><th>IOI0:TCEINV</th><th>[0, 3, 17]</th></tr>
+<tr><th>IOI1:ICEINV</th><th>[0, 3, 25]</th></tr>
+<tr><th>IOI1:ICLK1INV</th><th>[0, 3, 26]</th></tr>
+<tr><th>IOI1:ICLK2INV</th><th>[0, 3, 27]</th></tr>
+<tr><th>IOI1:OTCLK1INV</th><th>[0, 3, 23]</th></tr>
+<tr><th>IOI1:OTCLK2INV</th><th>[0, 3, 24]</th></tr>
+<tr><th>IOI1:REVINV</th><th>[0, 3, 28]</th></tr>
+<tr><th>IOI1:TCEINV</th><th>[0, 3, 22]</th></tr>
+<tr><th>IOI2:ICEINV</th><th>[0, 3, 54]</th></tr>
+<tr><th>IOI2:ICLK1INV</th><th>[0, 3, 53]</th></tr>
+<tr><th>IOI2:ICLK2INV</th><th>[0, 3, 52]</th></tr>
+<tr><th>IOI2:OTCLK1INV</th><th>[0, 3, 56]</th></tr>
+<tr><th>IOI2:OTCLK2INV</th><th>[0, 3, 55]</th></tr>
+<tr><th>IOI2:REVINV</th><th>[0, 3, 51]</th></tr>
+<tr><th>IOI2:TCEINV</th><th>[0, 3, 57]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+</section>
+<section id="ioi-s3e">
+<h3><code class="docutils literal notranslate"><span class="pre">IOI.S3E</span></code><a class="headerlink" href="#ioi-s3e" title="Link to this heading"></a></h3>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[0]">IOI0:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[1]">IOI0:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI0:IFF_DELAY_EN" title="IOI0:IFF_DELAY_EN">IOI0:IFF_DELAY_EN</a></td></tr>
+<tr><td>2</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI1:O2_DDRMUX" title="IOI1:O2_DDRMUX">IOI1:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[1]">IOI1:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>3</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI0:TFF1_SRVAL" title="~IOI0:TFF1_SRVAL">~IOI0:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:OFF1_SRVAL" title="~IOI0:OFF1_SRVAL">~IOI0:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:IFF1_SRVAL" title="~IOI0:IFF1_SRVAL">~IOI0:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:IFF_TSBYPASS_EN" title="IOI0:IFF_TSBYPASS_EN">IOI0:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI1:O1_DDRMUX" title="IOI1:O1_DDRMUX">IOI1:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI0:TSBYPASS_MUX" title="IOI0:TSBYPASS_MUX">IOI0:TSBYPASS_MUX</a></td></tr>
+<tr><td>5</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI0:TFF2_SRVAL" title="~IOI0:TFF2_SRVAL">~IOI0:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:OFF2_SRVAL" title="~IOI0:OFF2_SRVAL">~IOI0:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI0:IFF1_INIT" title="~IOI0:IFF1_INIT">~IOI0:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:I_TSBYPASS_EN" title="IOI0:I_TSBYPASS_EN">IOI0:I_TSBYPASS_EN</a></td></tr>
+<tr><td>8</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI0:TFF_INIT" title="~IOI0:TFF_INIT">~IOI0:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:OFF_INIT" title="~IOI0:OFF_INIT">~IOI0:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:IFF_SYNC" title="IOI0:IFF_SYNC">IOI0:IFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[0]">IOI0:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>9</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI0:TFF_REV_EN" title="IOI0:TFF_REV_EN">IOI0:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:OFF_REV_EN" title="IOI0:OFF_REV_EN">IOI0:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:IFF_REV_EN" title="IOI0:IFF_REV_EN">IOI0:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>10</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI0:TFF_SR_EN" title="IOI0:TFF_SR_EN">IOI0:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:OFF_SR_EN" title="IOI0:OFF_SR_EN">IOI0:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:IFF_SR_EN" title="IOI0:IFF_SR_EN">IOI0:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:I_DELAY_EN" title="IOI0:I_DELAY_EN">IOI0:I_DELAY_EN</a></td></tr>
+<tr><td>11</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI0:T2INV" title="IOI0:T2INV">IOI0:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:O2INV" title="IOI0:O2INV">IOI0:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:IFF_LATCH" title="IOI0:IFF_LATCH">IOI0:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:REVINV" title="~IOI0:REVINV">~IOI0:REVINV</a></td></tr>
+<tr><td>12</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI0:T1INV" title="IOI0:T1INV">IOI0:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:O1INV" title="IOI0:O1INV">IOI0:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:IFF2_INIT" title="~IOI0:IFF2_INIT">~IOI0:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:ICLK2INV" title="~IOI0:ICLK2INV">~IOI0:ICLK2INV</a></td></tr>
+<tr><td>13</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI0:TFF_SYNC" title="IOI0:TFF_SYNC">IOI0:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:OFF_SYNC" title="IOI0:OFF_SYNC">IOI0:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI0:ICLK1INV" title="~IOI0:ICLK1INV">~IOI0:ICLK1INV</a></td></tr>
+<tr><td>14</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI0:TMUX" title="IOI0:TMUX[1]">IOI0:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:OMUX" title="IOI0:OMUX[1]">IOI0:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI0:ICEINV" title="~IOI0:ICEINV">~IOI0:ICEINV</a></td></tr>
+<tr><td>15</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI0:TMUX" title="IOI0:TMUX[3]">IOI0:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:OMUX" title="IOI0:OMUX[3]">IOI0:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI0:OTCLK2INV" title="~IOI0:OTCLK2INV">~IOI0:OTCLK2INV</a></td></tr>
+<tr><td>16</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI0:TMUX" title="IOI0:TMUX[0]">IOI0:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:OMUX" title="IOI0:OMUX[0]">IOI0:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:IFF2_SRVAL" title="~IOI0:IFF2_SRVAL">~IOI0:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:OTCLK1INV" title="~IOI0:OTCLK1INV">~IOI0:OTCLK1INV</a></td></tr>
+<tr><td>17</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI0:TFF1_LATCH" title="IOI0:TFF1_LATCH">IOI0:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:OFF1_LATCH" title="IOI0:OFF1_LATCH">IOI0:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI0:TCEINV" title="~IOI0:TCEINV">~IOI0:TCEINV</a></td></tr>
+<tr><td>18</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI0:TFF2_LATCH" title="IOI0:TFF2_LATCH">IOI0:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:OFF2_LATCH" title="IOI0:OFF2_LATCH">IOI0:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[2]">IOI1:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>19</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI0:TMUX" title="IOI0:TMUX[2]">IOI0:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI0:OMUX" title="IOI0:OMUX[2]">IOI0:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI1:TMUX" title="IOI1:TMUX[2]">IOI1:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:OMUX" title="IOI1:OMUX[2]">IOI1:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI1:TFF2_LATCH" title="IOI1:TFF2_LATCH">IOI1:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:OFF2_LATCH" title="IOI1:OFF2_LATCH">IOI1:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[2]">IOI0:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>22</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI1:TFF1_LATCH" title="IOI1:TFF1_LATCH">IOI1:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:OFF1_LATCH" title="IOI1:OFF1_LATCH">IOI1:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI1:TCEINV" title="~IOI1:TCEINV">~IOI1:TCEINV</a></td></tr>
+<tr><td>23</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI1:TMUX" title="IOI1:TMUX[0]">IOI1:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:OMUX" title="IOI1:OMUX[0]">IOI1:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:IFF2_SRVAL" title="~IOI1:IFF2_SRVAL">~IOI1:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:OTCLK1INV" title="~IOI1:OTCLK1INV">~IOI1:OTCLK1INV</a></td></tr>
+<tr><td>24</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI1:TMUX" title="IOI1:TMUX[3]">IOI1:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:OMUX" title="IOI1:OMUX[3]">IOI1:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI1:OTCLK2INV" title="~IOI1:OTCLK2INV">~IOI1:OTCLK2INV</a></td></tr>
+<tr><td>25</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI1:TMUX" title="IOI1:TMUX[1]">IOI1:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:OMUX" title="IOI1:OMUX[1]">IOI1:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI1:ICEINV" title="~IOI1:ICEINV">~IOI1:ICEINV</a></td></tr>
+<tr><td>26</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI1:TFF_SYNC" title="IOI1:TFF_SYNC">IOI1:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:OFF_SYNC" title="IOI1:OFF_SYNC">IOI1:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI1:ICLK1INV" title="~IOI1:ICLK1INV">~IOI1:ICLK1INV</a></td></tr>
+<tr><td>27</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI1:T1INV" title="IOI1:T1INV">IOI1:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:O1INV" title="IOI1:O1INV">IOI1:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:IFF2_INIT" title="~IOI1:IFF2_INIT">~IOI1:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:ICLK2INV" title="~IOI1:ICLK2INV">~IOI1:ICLK2INV</a></td></tr>
+<tr><td>28</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI1:T2INV" title="IOI1:T2INV">IOI1:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:O2INV" title="IOI1:O2INV">IOI1:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:IFF_LATCH" title="IOI1:IFF_LATCH">IOI1:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:REVINV" title="~IOI1:REVINV">~IOI1:REVINV</a></td></tr>
+<tr><td>29</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI1:TFF_SR_EN" title="IOI1:TFF_SR_EN">IOI1:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:OFF_SR_EN" title="IOI1:OFF_SR_EN">IOI1:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:IFF_SR_EN" title="IOI1:IFF_SR_EN">IOI1:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:I_DELAY_EN" title="IOI1:I_DELAY_EN">IOI1:I_DELAY_EN</a></td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI1:TFF_REV_EN" title="IOI1:TFF_REV_EN">IOI1:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:OFF_REV_EN" title="IOI1:OFF_REV_EN">IOI1:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:IFF_REV_EN" title="IOI1:IFF_REV_EN">IOI1:IFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[0]">IOI1:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>31</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI1:TFF_INIT" title="~IOI1:TFF_INIT">~IOI1:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:OFF_INIT" title="~IOI1:OFF_INIT">~IOI1:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:IFF_SYNC" title="IOI1:IFF_SYNC">IOI1:IFF_SYNC</a></td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI1:IFF1_INIT" title="~IOI1:IFF1_INIT">~IOI1:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:I_TSBYPASS_EN" title="IOI1:I_TSBYPASS_EN">IOI1:I_TSBYPASS_EN</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI1:TFF2_SRVAL" title="~IOI1:TFF2_SRVAL">~IOI1:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:OFF2_SRVAL" title="~IOI1:OFF2_SRVAL">~IOI1:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI0:O1_DDRMUX" title="IOI0:O1_DDRMUX">IOI0:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI1:TSBYPASS_MUX" title="IOI1:TSBYPASS_MUX">IOI1:TSBYPASS_MUX</a></td></tr>
+<tr><td>36</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI1:TFF1_SRVAL" title="~IOI1:TFF1_SRVAL">~IOI1:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:OFF1_SRVAL" title="~IOI1:OFF1_SRVAL">~IOI1:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:IFF1_SRVAL" title="~IOI1:IFF1_SRVAL">~IOI1:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:IFF_TSBYPASS_EN" title="IOI1:IFF_TSBYPASS_EN">IOI1:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>37</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI0:O2_DDRMUX" title="IOI0:O2_DDRMUX">IOI0:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[1]">IOI0:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI1:IFF_DELAY_EN" title="IOI1:IFF_DELAY_EN">IOI1:IFF_DELAY_EN</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[0]">IOI1:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[1]">IOI1:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI2:PCICE_MUX" title="IOI2:PCICE_MUX[0]">IOI2:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:PCICE_MUX" title="IOI2:PCICE_MUX[1]">IOI2:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI2:IFF_DELAY_EN" title="IOI2:IFF_DELAY_EN">IOI2:IFF_DELAY_EN</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI2:IDDRIN_MUX" title="IOI2:IDDRIN_MUX[1]">IOI2:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>43</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI2:TFF1_SRVAL" title="~IOI2:TFF1_SRVAL">~IOI2:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:OFF1_SRVAL" title="~IOI2:OFF1_SRVAL">~IOI2:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:IFF1_SRVAL" title="~IOI2:IFF1_SRVAL">~IOI2:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:IFF_TSBYPASS_EN" title="IOI2:IFF_TSBYPASS_EN">IOI2:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI2:TSBYPASS_MUX" title="IOI2:TSBYPASS_MUX">IOI2:TSBYPASS_MUX</a></td></tr>
+<tr><td>45</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI2:TFF2_SRVAL" title="~IOI2:TFF2_SRVAL">~IOI2:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:OFF2_SRVAL" title="~IOI2:OFF2_SRVAL">~IOI2:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI2:IFF1_INIT" title="~IOI2:IFF1_INIT">~IOI2:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:I_TSBYPASS_EN" title="IOI2:I_TSBYPASS_EN">IOI2:I_TSBYPASS_EN</a></td></tr>
+<tr><td>48</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI2:TFF_INIT" title="~IOI2:TFF_INIT">~IOI2:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:OFF_INIT" title="~IOI2:OFF_INIT">~IOI2:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:IFF_SYNC" title="IOI2:IFF_SYNC">IOI2:IFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:IDDRIN_MUX" title="IOI2:IDDRIN_MUX[0]">IOI2:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>49</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI2:TFF_REV_EN" title="IOI2:TFF_REV_EN">IOI2:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:OFF_REV_EN" title="IOI2:OFF_REV_EN">IOI2:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:IFF_REV_EN" title="IOI2:IFF_REV_EN">IOI2:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>50</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI2:TFF_SR_EN" title="IOI2:TFF_SR_EN">IOI2:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:OFF_SR_EN" title="IOI2:OFF_SR_EN">IOI2:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:IFF_SR_EN" title="IOI2:IFF_SR_EN">IOI2:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:I_DELAY_EN" title="IOI2:I_DELAY_EN">IOI2:I_DELAY_EN</a></td></tr>
+<tr><td>51</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI2:T2INV" title="IOI2:T2INV">IOI2:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:O2INV" title="IOI2:O2INV">IOI2:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:IFF_LATCH" title="IOI2:IFF_LATCH">IOI2:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:REVINV" title="~IOI2:REVINV">~IOI2:REVINV</a></td></tr>
+<tr><td>52</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI2:T1INV" title="IOI2:T1INV">IOI2:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:O1INV" title="IOI2:O1INV">IOI2:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:IFF2_INIT" title="~IOI2:IFF2_INIT">~IOI2:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:ICLK2INV" title="~IOI2:ICLK2INV">~IOI2:ICLK2INV</a></td></tr>
+<tr><td>53</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI2:TFF_SYNC" title="IOI2:TFF_SYNC">IOI2:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:OFF_SYNC" title="IOI2:OFF_SYNC">IOI2:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI2:ICLK1INV" title="~IOI2:ICLK1INV">~IOI2:ICLK1INV</a></td></tr>
+<tr><td>54</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI2:TMUX" title="IOI2:TMUX[1]">IOI2:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:OMUX" title="IOI2:OMUX[1]">IOI2:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI2:ICEINV" title="~IOI2:ICEINV">~IOI2:ICEINV</a></td></tr>
+<tr><td>55</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI2:TMUX" title="IOI2:TMUX[3]">IOI2:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:OMUX" title="IOI2:OMUX[3]">IOI2:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI2:OTCLK2INV" title="~IOI2:OTCLK2INV">~IOI2:OTCLK2INV</a></td></tr>
+<tr><td>56</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI2:TMUX" title="IOI2:TMUX[0]">IOI2:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:OMUX" title="IOI2:OMUX[0]">IOI2:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:IFF2_SRVAL" title="~IOI2:IFF2_SRVAL">~IOI2:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:OTCLK1INV" title="~IOI2:OTCLK1INV">~IOI2:OTCLK1INV</a></td></tr>
+<tr><td>57</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI2:TFF1_LATCH" title="IOI2:TFF1_LATCH">IOI2:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:OFF1_LATCH" title="IOI2:OFF1_LATCH">IOI2:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI2:TCEINV" title="~IOI2:TCEINV">~IOI2:TCEINV</a></td></tr>
+<tr><td>58</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI2:TFF2_LATCH" title="IOI2:TFF2_LATCH">IOI2:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:OFF2_LATCH" title="IOI2:OFF2_LATCH">IOI2:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3E-IOI2:IDDRIN_MUX" title="IOI2:IDDRIN_MUX[2]">IOI2:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>59</td>
+<td><a href="#bits-xc3s-IOI.S3E-IOI2:TMUX" title="IOI2:TMUX[2]">IOI2:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3E-IOI2:OMUX" title="IOI2:OMUX[2]">IOI2:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:O2_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:O2_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O2_DDRMUX</th><th>[0, 0, 37]</th></tr>
+<tr><th>IOI1:O2_DDRMUX</th><th>[0, 0, 2]</th></tr>
+<tr><td>O2</td><td>0</td></tr>
+<tr><td>ODDRIN2</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:TFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_SRVAL</th><th>[0, 0, 3]</th></tr>
+<tr><th>IOI1:TFF1_SRVAL</th><th>[0, 0, 36]</th></tr>
+<tr><th>IOI2:TFF1_SRVAL</th><th>[0, 0, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:TFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_SRVAL</th><th>[0, 0, 5]</th></tr>
+<tr><th>IOI1:TFF2_SRVAL</th><th>[0, 0, 34]</th></tr>
+<tr><th>IOI2:TFF2_SRVAL</th><th>[0, 0, 45]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:TFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_INIT</th><th>[0, 0, 8]</th></tr>
+<tr><th>IOI1:TFF_INIT</th><th>[0, 0, 31]</th></tr>
+<tr><th>IOI2:TFF_INIT</th><th>[0, 0, 48]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:TFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_REV_EN</th><th>[0, 0, 9]</th></tr>
+<tr><th>IOI1:TFF_REV_EN</th><th>[0, 0, 30]</th></tr>
+<tr><th>IOI2:TFF_REV_EN</th><th>[0, 0, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:TFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SR_EN</th><th>[0, 0, 10]</th></tr>
+<tr><th>IOI1:TFF_SR_EN</th><th>[0, 0, 29]</th></tr>
+<tr><th>IOI2:TFF_SR_EN</th><th>[0, 0, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:O1INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI0:O2INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI0:T1INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI0:T2INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:O1INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:O2INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:T1INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:T2INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:O1INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:O2INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:T1INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:T2INV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1INV</th><th>[0, 1, 12]</th></tr>
+<tr><th>IOI0:O2INV</th><th>[0, 1, 11]</th></tr>
+<tr><th>IOI0:T1INV</th><th>[0, 0, 12]</th></tr>
+<tr><th>IOI0:T2INV</th><th>[0, 0, 11]</th></tr>
+<tr><th>IOI1:O1INV</th><th>[0, 1, 27]</th></tr>
+<tr><th>IOI1:O2INV</th><th>[0, 1, 28]</th></tr>
+<tr><th>IOI1:T1INV</th><th>[0, 0, 27]</th></tr>
+<tr><th>IOI1:T2INV</th><th>[0, 0, 28]</th></tr>
+<tr><th>IOI2:O1INV</th><th>[0, 1, 52]</th></tr>
+<tr><th>IOI2:O2INV</th><th>[0, 1, 51]</th></tr>
+<tr><th>IOI2:T1INV</th><th>[0, 0, 52]</th></tr>
+<tr><th>IOI2:T2INV</th><th>[0, 0, 51]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:TFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SYNC</th><th>[0, 0, 13]</th></tr>
+<tr><th>IOI1:TFF_SYNC</th><th>[0, 0, 26]</th></tr>
+<tr><th>IOI2:TFF_SYNC</th><th>[0, 0, 53]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:TMUX"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:TMUX"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:TMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TMUX</th><th>[0, 0, 15]</th><th>[0, 0, 19]</th><th>[0, 0, 14]</th><th>[0, 0, 16]</th></tr>
+<tr><th>IOI1:TMUX</th><th>[0, 0, 24]</th><th>[0, 0, 20]</th><th>[0, 0, 25]</th><th>[0, 0, 23]</th></tr>
+<tr><th>IOI2:TMUX</th><th>[0, 0, 55]</th><th>[0, 0, 59]</th><th>[0, 0, 54]</th><th>[0, 0, 56]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>T1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>T2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>TFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>TFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>TFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:TFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_LATCH</th><th>[0, 0, 17]</th></tr>
+<tr><th>IOI1:TFF1_LATCH</th><th>[0, 0, 22]</th></tr>
+<tr><th>IOI2:TFF1_LATCH</th><th>[0, 0, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:TFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_LATCH</th><th>[0, 0, 18]</th></tr>
+<tr><th>IOI1:TFF2_LATCH</th><th>[0, 0, 21]</th></tr>
+<tr><th>IOI2:TFF2_LATCH</th><th>[0, 0, 58]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:PCICE_MUX"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:PCICE_MUX"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:PCICE_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:PCICE_MUX</th><th>[0, 2, 0]</th><th>[0, 1, 0]</th></tr>
+<tr><th>IOI1:PCICE_MUX</th><th>[0, 2, 39]</th><th>[0, 1, 39]</th></tr>
+<tr><th>IOI2:PCICE_MUX</th><th>[0, 2, 40]</th><th>[0, 1, 40]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td></tr>
+<tr><td>OCE</td><td>0</td><td>1</td></tr>
+<tr><td>PCICE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:OFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_SRVAL</th><th>[0, 1, 3]</th></tr>
+<tr><th>IOI1:OFF1_SRVAL</th><th>[0, 1, 36]</th></tr>
+<tr><th>IOI2:OFF1_SRVAL</th><th>[0, 1, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:O1_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:O1_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1_DDRMUX</th><th>[0, 1, 35]</th></tr>
+<tr><th>IOI1:O1_DDRMUX</th><th>[0, 1, 4]</th></tr>
+<tr><td>O1</td><td>0</td></tr>
+<tr><td>ODDRIN1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:OFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_SRVAL</th><th>[0, 1, 5]</th></tr>
+<tr><th>IOI1:OFF2_SRVAL</th><th>[0, 1, 34]</th></tr>
+<tr><th>IOI2:OFF2_SRVAL</th><th>[0, 1, 45]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:OFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_INIT</th><th>[0, 1, 8]</th></tr>
+<tr><th>IOI1:OFF_INIT</th><th>[0, 1, 31]</th></tr>
+<tr><th>IOI2:OFF_INIT</th><th>[0, 1, 48]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:OFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_REV_EN</th><th>[0, 1, 9]</th></tr>
+<tr><th>IOI1:OFF_REV_EN</th><th>[0, 1, 30]</th></tr>
+<tr><th>IOI2:OFF_REV_EN</th><th>[0, 1, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:OFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SR_EN</th><th>[0, 1, 10]</th></tr>
+<tr><th>IOI1:OFF_SR_EN</th><th>[0, 1, 29]</th></tr>
+<tr><th>IOI2:OFF_SR_EN</th><th>[0, 1, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:OFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SYNC</th><th>[0, 1, 13]</th></tr>
+<tr><th>IOI1:OFF_SYNC</th><th>[0, 1, 26]</th></tr>
+<tr><th>IOI2:OFF_SYNC</th><th>[0, 1, 53]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:OMUX"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:OMUX"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:OMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OMUX</th><th>[0, 1, 15]</th><th>[0, 1, 19]</th><th>[0, 1, 14]</th><th>[0, 1, 16]</th></tr>
+<tr><th>IOI1:OMUX</th><th>[0, 1, 24]</th><th>[0, 1, 20]</th><th>[0, 1, 25]</th><th>[0, 1, 23]</th></tr>
+<tr><th>IOI2:OMUX</th><th>[0, 1, 55]</th><th>[0, 1, 59]</th><th>[0, 1, 54]</th><th>[0, 1, 56]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>O1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>O2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:OFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_LATCH</th><th>[0, 1, 17]</th></tr>
+<tr><th>IOI1:OFF1_LATCH</th><th>[0, 1, 22]</th></tr>
+<tr><th>IOI2:OFF1_LATCH</th><th>[0, 1, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:OFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_LATCH</th><th>[0, 1, 18]</th></tr>
+<tr><th>IOI1:OFF2_LATCH</th><th>[0, 1, 21]</th></tr>
+<tr><th>IOI2:OFF2_LATCH</th><th>[0, 1, 58]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:IFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_SRVAL</th><th>[0, 2, 3]</th></tr>
+<tr><th>IOI1:IFF1_SRVAL</th><th>[0, 2, 36]</th></tr>
+<tr><th>IOI2:IFF1_SRVAL</th><th>[0, 2, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:IFF1_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_INIT</th><th>[0, 2, 7]</th></tr>
+<tr><th>IOI1:IFF1_INIT</th><th>[0, 2, 32]</th></tr>
+<tr><th>IOI2:IFF1_INIT</th><th>[0, 2, 47]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:IFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SYNC</th><th>[0, 2, 8]</th></tr>
+<tr><th>IOI1:IFF_SYNC</th><th>[0, 2, 31]</th></tr>
+<tr><th>IOI2:IFF_SYNC</th><th>[0, 2, 48]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:IFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_REV_EN</th><th>[0, 2, 9]</th></tr>
+<tr><th>IOI1:IFF_REV_EN</th><th>[0, 2, 30]</th></tr>
+<tr><th>IOI2:IFF_REV_EN</th><th>[0, 2, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:IFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SR_EN</th><th>[0, 2, 10]</th></tr>
+<tr><th>IOI1:IFF_SR_EN</th><th>[0, 2, 29]</th></tr>
+<tr><th>IOI2:IFF_SR_EN</th><th>[0, 2, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:IFF_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_LATCH</th><th>[0, 2, 11]</th></tr>
+<tr><th>IOI1:IFF_LATCH</th><th>[0, 2, 28]</th></tr>
+<tr><th>IOI2:IFF_LATCH</th><th>[0, 2, 51]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:IFF2_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_INIT</th><th>[0, 2, 12]</th></tr>
+<tr><th>IOI1:IFF2_INIT</th><th>[0, 2, 27]</th></tr>
+<tr><th>IOI2:IFF2_INIT</th><th>[0, 2, 52]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:IFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_SRVAL</th><th>[0, 2, 16]</th></tr>
+<tr><th>IOI1:IFF2_SRVAL</th><th>[0, 2, 23]</th></tr>
+<tr><th>IOI2:IFF2_SRVAL</th><th>[0, 2, 56]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:IFF_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY_EN</th><th>[0, 3, 1]</th></tr>
+<tr><th>IOI1:IFF_DELAY_EN</th><th>[0, 3, 38]</th></tr>
+<tr><th>IOI2:IFF_DELAY_EN</th><th>[0, 3, 41]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:IFF_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_TSBYPASS_EN</th><th>[0, 3, 3]</th></tr>
+<tr><th>IOI1:IFF_TSBYPASS_EN</th><th>[0, 3, 36]</th></tr>
+<tr><th>IOI2:IFF_TSBYPASS_EN</th><th>[0, 3, 43]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:TSBYPASS_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TSBYPASS_MUX</th><th>[0, 3, 4]</th></tr>
+<tr><th>IOI1:TSBYPASS_MUX</th><th>[0, 3, 35]</th></tr>
+<tr><th>IOI2:TSBYPASS_MUX</th><th>[0, 3, 44]</th></tr>
+<tr><td>TMUX</td><td>0</td></tr>
+<tr><td>GND</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:I_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_TSBYPASS_EN</th><th>[0, 3, 7]</th></tr>
+<tr><th>IOI1:I_TSBYPASS_EN</th><th>[0, 3, 32]</th></tr>
+<tr><th>IOI2:I_TSBYPASS_EN</th><th>[0, 3, 47]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:IDDRIN_MUX"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:IDDRIN_MUX"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:IDDRIN_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IDDRIN_MUX</th><th>[0, 3, 21]</th><th>[0, 3, 37]</th><th>[0, 3, 8]</th></tr>
+<tr><th>IOI1:IDDRIN_MUX</th><th>[0, 3, 18]</th><th>[0, 3, 2]</th><th>[0, 3, 30]</th></tr>
+<tr><th>IOI2:IDDRIN_MUX</th><th>[0, 3, 58]</th><th>[0, 3, 42]</th><th>[0, 3, 48]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>IFFDMUX</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>IDDRIN1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>IDDRIN2</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:I_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY_EN</th><th>[0, 3, 10]</th></tr>
+<tr><th>IOI1:I_DELAY_EN</th><th>[0, 3, 29]</th></tr>
+<tr><th>IOI2:I_DELAY_EN</th><th>[0, 3, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3E-IOI0:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI0:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI0:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI0:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI0:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI0:REVINV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI0:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:REVINV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI1:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:REVINV"></div>
+<div id="bits-xc3s-IOI.S3E-IOI2:TCEINV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:ICEINV</th><th>[0, 3, 14]</th></tr>
+<tr><th>IOI0:ICLK1INV</th><th>[0, 3, 13]</th></tr>
+<tr><th>IOI0:ICLK2INV</th><th>[0, 3, 12]</th></tr>
+<tr><th>IOI0:OTCLK1INV</th><th>[0, 3, 16]</th></tr>
+<tr><th>IOI0:OTCLK2INV</th><th>[0, 3, 15]</th></tr>
+<tr><th>IOI0:REVINV</th><th>[0, 3, 11]</th></tr>
+<tr><th>IOI0:TCEINV</th><th>[0, 3, 17]</th></tr>
+<tr><th>IOI1:ICEINV</th><th>[0, 3, 25]</th></tr>
+<tr><th>IOI1:ICLK1INV</th><th>[0, 3, 26]</th></tr>
+<tr><th>IOI1:ICLK2INV</th><th>[0, 3, 27]</th></tr>
+<tr><th>IOI1:OTCLK1INV</th><th>[0, 3, 23]</th></tr>
+<tr><th>IOI1:OTCLK2INV</th><th>[0, 3, 24]</th></tr>
+<tr><th>IOI1:REVINV</th><th>[0, 3, 28]</th></tr>
+<tr><th>IOI1:TCEINV</th><th>[0, 3, 22]</th></tr>
+<tr><th>IOI2:ICEINV</th><th>[0, 3, 54]</th></tr>
+<tr><th>IOI2:ICLK1INV</th><th>[0, 3, 53]</th></tr>
+<tr><th>IOI2:ICLK2INV</th><th>[0, 3, 52]</th></tr>
+<tr><th>IOI2:OTCLK1INV</th><th>[0, 3, 56]</th></tr>
+<tr><th>IOI2:OTCLK2INV</th><th>[0, 3, 55]</th></tr>
+<tr><th>IOI2:REVINV</th><th>[0, 3, 51]</th></tr>
+<tr><th>IOI2:TCEINV</th><th>[0, 3, 57]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+</section>
+<section id="ioi-s3a-l">
+<h3><code class="docutils literal notranslate"><span class="pre">IOI.S3A.L</span></code><a class="headerlink" href="#ioi-s3a-l" title="Link to this heading"></a></h3>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[0]">IOI0:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[1]">IOI0:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:IFF_DELAY_EN" title="IOI0:IFF_DELAY_EN">IOI0:IFF_DELAY_EN</a></td></tr>
+<tr><td>2</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI1:O2_DDRMUX" title="IOI1:O2_DDRMUX">IOI1:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[1]">IOI1:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>3</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI0:TFF1_SRVAL" title="~IOI0:TFF1_SRVAL">~IOI0:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:OFF1_SRVAL" title="~IOI0:OFF1_SRVAL">~IOI0:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:IFF1_SRVAL" title="~IOI0:IFF1_SRVAL">~IOI0:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:IFF_TSBYPASS_EN" title="IOI0:IFF_TSBYPASS_EN">IOI0:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:O1_DDRMUX" title="IOI1:O1_DDRMUX">IOI1:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:TSBYPASS_MUX" title="IOI0:TSBYPASS_MUX">IOI0:TSBYPASS_MUX</a></td></tr>
+<tr><td>5</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI0:TFF2_SRVAL" title="~IOI0:TFF2_SRVAL">~IOI0:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:OFF2_SRVAL" title="~IOI0:OFF2_SRVAL">~IOI0:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:IFF1_INIT" title="~IOI0:IFF1_INIT">~IOI0:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:I_TSBYPASS_EN" title="IOI0:I_TSBYPASS_EN">IOI0:I_TSBYPASS_EN</a></td></tr>
+<tr><td>8</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI0:TFF_INIT" title="~IOI0:TFF_INIT">~IOI0:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:OFF_INIT" title="~IOI0:OFF_INIT">~IOI0:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:IFF_SYNC" title="IOI0:IFF_SYNC">IOI0:IFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[0]">IOI0:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>9</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI0:TFF_REV_EN" title="IOI0:TFF_REV_EN">IOI0:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:OFF_REV_EN" title="IOI0:OFF_REV_EN">IOI0:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:IFF_REV_EN" title="IOI0:IFF_REV_EN">IOI0:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>10</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI0:TFF_SR_EN" title="IOI0:TFF_SR_EN">IOI0:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:OFF_SR_EN" title="IOI0:OFF_SR_EN">IOI0:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:IFF_SR_EN" title="IOI0:IFF_SR_EN">IOI0:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:I_DELAY_EN" title="IOI0:I_DELAY_EN">IOI0:I_DELAY_EN</a></td></tr>
+<tr><td>11</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI0:T2INV" title="IOI0:T2INV">IOI0:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:O2INV" title="IOI0:O2INV">IOI0:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:IFF_LATCH" title="IOI0:IFF_LATCH">IOI0:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:REVINV" title="~IOI0:REVINV">~IOI0:REVINV</a></td></tr>
+<tr><td>12</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI0:T1INV" title="IOI0:T1INV">IOI0:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:O1INV" title="IOI0:O1INV">IOI0:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:IFF2_INIT" title="~IOI0:IFF2_INIT">~IOI0:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:ICLK2INV" title="~IOI0:ICLK2INV">~IOI0:ICLK2INV</a></td></tr>
+<tr><td>13</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI0:TFF_SYNC" title="IOI0:TFF_SYNC">IOI0:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:OFF_SYNC" title="IOI0:OFF_SYNC">IOI0:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:ICLK1INV" title="~IOI0:ICLK1INV">~IOI0:ICLK1INV</a></td></tr>
+<tr><td>14</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI0:TMUX" title="IOI0:TMUX[1]">IOI0:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:OMUX" title="IOI0:OMUX[1]">IOI0:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:ICEINV" title="~IOI0:ICEINV">~IOI0:ICEINV</a></td></tr>
+<tr><td>15</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI0:TMUX" title="IOI0:TMUX[3]">IOI0:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:OMUX" title="IOI0:OMUX[3]">IOI0:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:OTCLK2INV" title="~IOI0:OTCLK2INV">~IOI0:OTCLK2INV</a></td></tr>
+<tr><td>16</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI0:TMUX" title="IOI0:TMUX[0]">IOI0:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:OMUX" title="IOI0:OMUX[0]">IOI0:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:IFF2_SRVAL" title="~IOI0:IFF2_SRVAL">~IOI0:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:OTCLK1INV" title="~IOI0:OTCLK1INV">~IOI0:OTCLK1INV</a></td></tr>
+<tr><td>17</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI0:TFF1_LATCH" title="IOI0:TFF1_LATCH">IOI0:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:OFF1_LATCH" title="IOI0:OFF1_LATCH">IOI0:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:TCEINV" title="~IOI0:TCEINV">~IOI0:TCEINV</a></td></tr>
+<tr><td>18</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI0:TFF2_LATCH" title="IOI0:TFF2_LATCH">IOI0:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:OFF2_LATCH" title="IOI0:OFF2_LATCH">IOI0:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[2]">IOI1:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>19</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI0:TMUX" title="IOI0:TMUX[2]">IOI0:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:OMUX" title="IOI0:OMUX[2]">IOI0:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI1:TMUX" title="IOI1:TMUX[2]">IOI1:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:OMUX" title="IOI1:OMUX[2]">IOI1:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI1:TFF2_LATCH" title="IOI1:TFF2_LATCH">IOI1:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:OFF2_LATCH" title="IOI1:OFF2_LATCH">IOI1:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[2]">IOI0:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>22</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI1:TFF1_LATCH" title="IOI1:TFF1_LATCH">IOI1:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:OFF1_LATCH" title="IOI1:OFF1_LATCH">IOI1:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:TCEINV" title="~IOI1:TCEINV">~IOI1:TCEINV</a></td></tr>
+<tr><td>23</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI1:TMUX" title="IOI1:TMUX[0]">IOI1:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:OMUX" title="IOI1:OMUX[0]">IOI1:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:IFF2_SRVAL" title="~IOI1:IFF2_SRVAL">~IOI1:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:OTCLK1INV" title="~IOI1:OTCLK1INV">~IOI1:OTCLK1INV</a></td></tr>
+<tr><td>24</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI1:TMUX" title="IOI1:TMUX[3]">IOI1:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:OMUX" title="IOI1:OMUX[3]">IOI1:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:OTCLK2INV" title="~IOI1:OTCLK2INV">~IOI1:OTCLK2INV</a></td></tr>
+<tr><td>25</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI1:TMUX" title="IOI1:TMUX[1]">IOI1:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:OMUX" title="IOI1:OMUX[1]">IOI1:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:ICEINV" title="~IOI1:ICEINV">~IOI1:ICEINV</a></td></tr>
+<tr><td>26</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI1:TFF_SYNC" title="IOI1:TFF_SYNC">IOI1:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:OFF_SYNC" title="IOI1:OFF_SYNC">IOI1:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:ICLK1INV" title="~IOI1:ICLK1INV">~IOI1:ICLK1INV</a></td></tr>
+<tr><td>27</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI1:T1INV" title="IOI1:T1INV">IOI1:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:O1INV" title="IOI1:O1INV">IOI1:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:IFF2_INIT" title="~IOI1:IFF2_INIT">~IOI1:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:ICLK2INV" title="~IOI1:ICLK2INV">~IOI1:ICLK2INV</a></td></tr>
+<tr><td>28</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI1:T2INV" title="IOI1:T2INV">IOI1:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:O2INV" title="IOI1:O2INV">IOI1:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:IFF_LATCH" title="IOI1:IFF_LATCH">IOI1:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:REVINV" title="~IOI1:REVINV">~IOI1:REVINV</a></td></tr>
+<tr><td>29</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI1:TFF_SR_EN" title="IOI1:TFF_SR_EN">IOI1:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:OFF_SR_EN" title="IOI1:OFF_SR_EN">IOI1:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:IFF_SR_EN" title="IOI1:IFF_SR_EN">IOI1:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:I_DELAY_EN" title="IOI1:I_DELAY_EN">IOI1:I_DELAY_EN</a></td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI1:TFF_REV_EN" title="IOI1:TFF_REV_EN">IOI1:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:OFF_REV_EN" title="IOI1:OFF_REV_EN">IOI1:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:IFF_REV_EN" title="IOI1:IFF_REV_EN">IOI1:IFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[0]">IOI1:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>31</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI1:TFF_INIT" title="~IOI1:TFF_INIT">~IOI1:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:OFF_INIT" title="~IOI1:OFF_INIT">~IOI1:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:IFF_SYNC" title="IOI1:IFF_SYNC">IOI1:IFF_SYNC</a></td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:IFF1_INIT" title="~IOI1:IFF1_INIT">~IOI1:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:I_TSBYPASS_EN" title="IOI1:I_TSBYPASS_EN">IOI1:I_TSBYPASS_EN</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI1:TFF2_SRVAL" title="~IOI1:TFF2_SRVAL">~IOI1:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:OFF2_SRVAL" title="~IOI1:OFF2_SRVAL">~IOI1:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:O1_DDRMUX" title="IOI0:O1_DDRMUX">IOI0:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:TSBYPASS_MUX" title="IOI1:TSBYPASS_MUX">IOI1:TSBYPASS_MUX</a></td></tr>
+<tr><td>36</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI1:TFF1_SRVAL" title="~IOI1:TFF1_SRVAL">~IOI1:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:OFF1_SRVAL" title="~IOI1:OFF1_SRVAL">~IOI1:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:IFF1_SRVAL" title="~IOI1:IFF1_SRVAL">~IOI1:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:IFF_TSBYPASS_EN" title="IOI1:IFF_TSBYPASS_EN">IOI1:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>37</td>
+<td><a href="#bits-xc3s-IOI.S3A.L-IOI0:O2_DDRMUX" title="IOI0:O2_DDRMUX">IOI0:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[1]">IOI0:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:IFF_DELAY_EN" title="IOI1:IFF_DELAY_EN">IOI1:IFF_DELAY_EN</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[0]">IOI1:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[1]">IOI1:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:DELAY_COMMON" title="~IOI0:DELAY_COMMON">~IOI0:DELAY_COMMON</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:DELAY_COMMON" title="~IOI1:DELAY_COMMON">~IOI1:DELAY_COMMON</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:IFF_DELAY" title="~IOI1:IFF_DELAY[0]">~IOI1:IFF_DELAY[0]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:DELAY_VARIABLE" title="IOI0:DELAY_VARIABLE">IOI0:DELAY_VARIABLE</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:I_DELAY" title="~IOI0:I_DELAY[1]">~IOI0:I_DELAY[1]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:I_DELAY" title="~IOI0:I_DELAY[2]">~IOI0:I_DELAY[2]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:IFF_DELAY" title="~IOI0:IFF_DELAY[0]">~IOI0:IFF_DELAY[0]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:I_DELAY" title="~IOI0:I_DELAY[0]">~IOI0:I_DELAY[0]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI0:IFF_DELAY" title="~IOI0:IFF_DELAY[1]">~IOI0:IFF_DELAY[1]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:I_DELAY" title="~IOI1:I_DELAY[0]">~IOI1:I_DELAY[0]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:I_DELAY" title="~IOI1:I_DELAY[1]">~IOI1:I_DELAY[1]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:I_DELAY" title="~IOI1:I_DELAY[2]">~IOI1:I_DELAY[2]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:DELAY_VARIABLE" title="IOI1:DELAY_VARIABLE">IOI1:DELAY_VARIABLE</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.L-IOI1:IFF_DELAY" title="~IOI1:IFF_DELAY[1]">~IOI1:IFF_DELAY[1]</a></td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:O2_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:O2_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O2_DDRMUX</th><th>[0, 0, 37]</th></tr>
+<tr><th>IOI1:O2_DDRMUX</th><th>[0, 0, 2]</th></tr>
+<tr><td>O2</td><td>0</td></tr>
+<tr><td>ODDRIN2</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:TFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_SRVAL</th><th>[0, 0, 3]</th></tr>
+<tr><th>IOI1:TFF1_SRVAL</th><th>[0, 0, 36]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:TFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_SRVAL</th><th>[0, 0, 5]</th></tr>
+<tr><th>IOI1:TFF2_SRVAL</th><th>[0, 0, 34]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:TFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_INIT</th><th>[0, 0, 8]</th></tr>
+<tr><th>IOI1:TFF_INIT</th><th>[0, 0, 31]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:TFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_REV_EN</th><th>[0, 0, 9]</th></tr>
+<tr><th>IOI1:TFF_REV_EN</th><th>[0, 0, 30]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:TFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SR_EN</th><th>[0, 0, 10]</th></tr>
+<tr><th>IOI1:TFF_SR_EN</th><th>[0, 0, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:O1INV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:O2INV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:T1INV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:T2INV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:O1INV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:O2INV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:T1INV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:T2INV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1INV</th><th>[0, 1, 12]</th></tr>
+<tr><th>IOI0:O2INV</th><th>[0, 1, 11]</th></tr>
+<tr><th>IOI0:T1INV</th><th>[0, 0, 12]</th></tr>
+<tr><th>IOI0:T2INV</th><th>[0, 0, 11]</th></tr>
+<tr><th>IOI1:O1INV</th><th>[0, 1, 27]</th></tr>
+<tr><th>IOI1:O2INV</th><th>[0, 1, 28]</th></tr>
+<tr><th>IOI1:T1INV</th><th>[0, 0, 27]</th></tr>
+<tr><th>IOI1:T2INV</th><th>[0, 0, 28]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:TFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SYNC</th><th>[0, 0, 13]</th></tr>
+<tr><th>IOI1:TFF_SYNC</th><th>[0, 0, 26]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:TMUX"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:TMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TMUX</th><th>[0, 0, 15]</th><th>[0, 0, 19]</th><th>[0, 0, 14]</th><th>[0, 0, 16]</th></tr>
+<tr><th>IOI1:TMUX</th><th>[0, 0, 24]</th><th>[0, 0, 20]</th><th>[0, 0, 25]</th><th>[0, 0, 23]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>T1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>T2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>TFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>TFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>TFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:TFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_LATCH</th><th>[0, 0, 17]</th></tr>
+<tr><th>IOI1:TFF1_LATCH</th><th>[0, 0, 22]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:TFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_LATCH</th><th>[0, 0, 18]</th></tr>
+<tr><th>IOI1:TFF2_LATCH</th><th>[0, 0, 21]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:PCICE_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:PCICE_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:PCICE_MUX</th><th>[0, 2, 0]</th><th>[0, 1, 0]</th></tr>
+<tr><th>IOI1:PCICE_MUX</th><th>[0, 2, 39]</th><th>[0, 1, 39]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td></tr>
+<tr><td>OCE</td><td>0</td><td>1</td></tr>
+<tr><td>PCICE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:OFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_SRVAL</th><th>[0, 1, 3]</th></tr>
+<tr><th>IOI1:OFF1_SRVAL</th><th>[0, 1, 36]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:O1_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:O1_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1_DDRMUX</th><th>[0, 1, 35]</th></tr>
+<tr><th>IOI1:O1_DDRMUX</th><th>[0, 1, 4]</th></tr>
+<tr><td>O1</td><td>0</td></tr>
+<tr><td>ODDRIN1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:OFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_SRVAL</th><th>[0, 1, 5]</th></tr>
+<tr><th>IOI1:OFF2_SRVAL</th><th>[0, 1, 34]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:OFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_INIT</th><th>[0, 1, 8]</th></tr>
+<tr><th>IOI1:OFF_INIT</th><th>[0, 1, 31]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:OFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_REV_EN</th><th>[0, 1, 9]</th></tr>
+<tr><th>IOI1:OFF_REV_EN</th><th>[0, 1, 30]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:OFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SR_EN</th><th>[0, 1, 10]</th></tr>
+<tr><th>IOI1:OFF_SR_EN</th><th>[0, 1, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:OFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SYNC</th><th>[0, 1, 13]</th></tr>
+<tr><th>IOI1:OFF_SYNC</th><th>[0, 1, 26]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:OMUX"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:OMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OMUX</th><th>[0, 1, 15]</th><th>[0, 1, 19]</th><th>[0, 1, 14]</th><th>[0, 1, 16]</th></tr>
+<tr><th>IOI1:OMUX</th><th>[0, 1, 24]</th><th>[0, 1, 20]</th><th>[0, 1, 25]</th><th>[0, 1, 23]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>O1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>O2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:OFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_LATCH</th><th>[0, 1, 17]</th></tr>
+<tr><th>IOI1:OFF1_LATCH</th><th>[0, 1, 22]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:OFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_LATCH</th><th>[0, 1, 18]</th></tr>
+<tr><th>IOI1:OFF2_LATCH</th><th>[0, 1, 21]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:IFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_SRVAL</th><th>[0, 2, 3]</th></tr>
+<tr><th>IOI1:IFF1_SRVAL</th><th>[0, 2, 36]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:IFF1_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_INIT</th><th>[0, 2, 7]</th></tr>
+<tr><th>IOI1:IFF1_INIT</th><th>[0, 2, 32]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:IFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SYNC</th><th>[0, 2, 8]</th></tr>
+<tr><th>IOI1:IFF_SYNC</th><th>[0, 2, 31]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:IFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_REV_EN</th><th>[0, 2, 9]</th></tr>
+<tr><th>IOI1:IFF_REV_EN</th><th>[0, 2, 30]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:IFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SR_EN</th><th>[0, 2, 10]</th></tr>
+<tr><th>IOI1:IFF_SR_EN</th><th>[0, 2, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:IFF_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_LATCH</th><th>[0, 2, 11]</th></tr>
+<tr><th>IOI1:IFF_LATCH</th><th>[0, 2, 28]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:IFF2_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_INIT</th><th>[0, 2, 12]</th></tr>
+<tr><th>IOI1:IFF2_INIT</th><th>[0, 2, 27]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:IFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_SRVAL</th><th>[0, 2, 16]</th></tr>
+<tr><th>IOI1:IFF2_SRVAL</th><th>[0, 2, 23]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:IFF_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY_EN</th><th>[0, 3, 1]</th></tr>
+<tr><th>IOI1:IFF_DELAY_EN</th><th>[0, 3, 38]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:IFF_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_TSBYPASS_EN</th><th>[0, 3, 3]</th></tr>
+<tr><th>IOI1:IFF_TSBYPASS_EN</th><th>[0, 3, 36]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:TSBYPASS_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TSBYPASS_MUX</th><th>[0, 3, 4]</th></tr>
+<tr><th>IOI1:TSBYPASS_MUX</th><th>[0, 3, 35]</th></tr>
+<tr><td>TMUX</td><td>0</td></tr>
+<tr><td>GND</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:I_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_TSBYPASS_EN</th><th>[0, 3, 7]</th></tr>
+<tr><th>IOI1:I_TSBYPASS_EN</th><th>[0, 3, 32]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:IDDRIN_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:IDDRIN_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IDDRIN_MUX</th><th>[0, 3, 21]</th><th>[0, 3, 37]</th><th>[0, 3, 8]</th></tr>
+<tr><th>IOI1:IDDRIN_MUX</th><th>[0, 3, 18]</th><th>[0, 3, 2]</th><th>[0, 3, 30]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>IFFDMUX</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>IDDRIN1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>IDDRIN2</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:I_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY_EN</th><th>[0, 3, 10]</th></tr>
+<tr><th>IOI1:I_DELAY_EN</th><th>[0, 3, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:REVINV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:REVINV"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:TCEINV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:ICEINV</th><th>[0, 3, 14]</th></tr>
+<tr><th>IOI0:ICLK1INV</th><th>[0, 3, 13]</th></tr>
+<tr><th>IOI0:ICLK2INV</th><th>[0, 3, 12]</th></tr>
+<tr><th>IOI0:OTCLK1INV</th><th>[0, 3, 16]</th></tr>
+<tr><th>IOI0:OTCLK2INV</th><th>[0, 3, 15]</th></tr>
+<tr><th>IOI0:REVINV</th><th>[0, 3, 11]</th></tr>
+<tr><th>IOI0:TCEINV</th><th>[0, 3, 17]</th></tr>
+<tr><th>IOI1:ICEINV</th><th>[0, 3, 25]</th></tr>
+<tr><th>IOI1:ICLK1INV</th><th>[0, 3, 26]</th></tr>
+<tr><th>IOI1:ICLK2INV</th><th>[0, 3, 27]</th></tr>
+<tr><th>IOI1:OTCLK1INV</th><th>[0, 3, 23]</th></tr>
+<tr><th>IOI1:OTCLK2INV</th><th>[0, 3, 24]</th></tr>
+<tr><th>IOI1:REVINV</th><th>[0, 3, 28]</th></tr>
+<tr><th>IOI1:TCEINV</th><th>[0, 3, 22]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:DELAY_COMMON"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:DELAY_COMMON"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:DELAY_COMMON</th><th>[0, 3, 41]</th></tr>
+<tr><th>IOI1:DELAY_COMMON</th><th>[0, 3, 42]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:IFF_DELAY"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:IFF_DELAY"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY</th><th>[0, 3, 53]</th><th>[0, 3, 51]</th></tr>
+<tr><th>IOI1:IFF_DELAY</th><th>[0, 3, 58]</th><th>[0, 3, 47]</th></tr>
+<tr><td>Inverted</td><td>~[1]</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:DELAY_VARIABLE"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:DELAY_VARIABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:DELAY_VARIABLE</th><th>[0, 3, 48]</th></tr>
+<tr><th>IOI1:DELAY_VARIABLE</th><th>[0, 3, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.L-IOI0:I_DELAY"></div>
+<div id="bits-xc3s-IOI.S3A.L-IOI1:I_DELAY"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY</th><th>[0, 3, 50]</th><th>[0, 3, 49]</th><th>[0, 3, 52]</th></tr>
+<tr><th>IOI1:I_DELAY</th><th>[0, 3, 56]</th><th>[0, 3, 55]</th><th>[0, 3, 54]</th></tr>
+<tr><td>Inverted</td><td>~[2]</td><td>~[1]</td><td>~[0]</td></tr>
+</table>
+</section>
+<section id="ioi-s3a-r">
+<h3><code class="docutils literal notranslate"><span class="pre">IOI.S3A.R</span></code><a class="headerlink" href="#ioi-s3a-r" title="Link to this heading"></a></h3>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[0]">IOI0:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[1]">IOI0:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:IFF_DELAY_EN" title="IOI0:IFF_DELAY_EN">IOI0:IFF_DELAY_EN</a></td></tr>
+<tr><td>2</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI1:O2_DDRMUX" title="IOI1:O2_DDRMUX">IOI1:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[1]">IOI1:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>3</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI0:TFF1_SRVAL" title="~IOI0:TFF1_SRVAL">~IOI0:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:OFF1_SRVAL" title="~IOI0:OFF1_SRVAL">~IOI0:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:IFF1_SRVAL" title="~IOI0:IFF1_SRVAL">~IOI0:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:IFF_TSBYPASS_EN" title="IOI0:IFF_TSBYPASS_EN">IOI0:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:O1_DDRMUX" title="IOI1:O1_DDRMUX">IOI1:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:TSBYPASS_MUX" title="IOI0:TSBYPASS_MUX">IOI0:TSBYPASS_MUX</a></td></tr>
+<tr><td>5</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI0:TFF2_SRVAL" title="~IOI0:TFF2_SRVAL">~IOI0:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:OFF2_SRVAL" title="~IOI0:OFF2_SRVAL">~IOI0:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:IFF1_INIT" title="~IOI0:IFF1_INIT">~IOI0:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:I_TSBYPASS_EN" title="IOI0:I_TSBYPASS_EN">IOI0:I_TSBYPASS_EN</a></td></tr>
+<tr><td>8</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI0:TFF_INIT" title="~IOI0:TFF_INIT">~IOI0:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:OFF_INIT" title="~IOI0:OFF_INIT">~IOI0:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:IFF_SYNC" title="IOI0:IFF_SYNC">IOI0:IFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[0]">IOI0:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>9</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI0:TFF_REV_EN" title="IOI0:TFF_REV_EN">IOI0:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:OFF_REV_EN" title="IOI0:OFF_REV_EN">IOI0:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:IFF_REV_EN" title="IOI0:IFF_REV_EN">IOI0:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>10</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI0:TFF_SR_EN" title="IOI0:TFF_SR_EN">IOI0:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:OFF_SR_EN" title="IOI0:OFF_SR_EN">IOI0:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:IFF_SR_EN" title="IOI0:IFF_SR_EN">IOI0:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:I_DELAY_EN" title="IOI0:I_DELAY_EN">IOI0:I_DELAY_EN</a></td></tr>
+<tr><td>11</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI0:T2INV" title="IOI0:T2INV">IOI0:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:O2INV" title="IOI0:O2INV">IOI0:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:IFF_LATCH" title="IOI0:IFF_LATCH">IOI0:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:REVINV" title="~IOI0:REVINV">~IOI0:REVINV</a></td></tr>
+<tr><td>12</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI0:T1INV" title="IOI0:T1INV">IOI0:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:O1INV" title="IOI0:O1INV">IOI0:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:IFF2_INIT" title="~IOI0:IFF2_INIT">~IOI0:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:ICLK2INV" title="~IOI0:ICLK2INV">~IOI0:ICLK2INV</a></td></tr>
+<tr><td>13</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI0:TFF_SYNC" title="IOI0:TFF_SYNC">IOI0:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:OFF_SYNC" title="IOI0:OFF_SYNC">IOI0:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:ICLK1INV" title="~IOI0:ICLK1INV">~IOI0:ICLK1INV</a></td></tr>
+<tr><td>14</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI0:TMUX" title="IOI0:TMUX[1]">IOI0:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:OMUX" title="IOI0:OMUX[1]">IOI0:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:ICEINV" title="~IOI0:ICEINV">~IOI0:ICEINV</a></td></tr>
+<tr><td>15</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI0:TMUX" title="IOI0:TMUX[3]">IOI0:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:OMUX" title="IOI0:OMUX[3]">IOI0:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:OTCLK2INV" title="~IOI0:OTCLK2INV">~IOI0:OTCLK2INV</a></td></tr>
+<tr><td>16</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI0:TMUX" title="IOI0:TMUX[0]">IOI0:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:OMUX" title="IOI0:OMUX[0]">IOI0:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:IFF2_SRVAL" title="~IOI0:IFF2_SRVAL">~IOI0:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:OTCLK1INV" title="~IOI0:OTCLK1INV">~IOI0:OTCLK1INV</a></td></tr>
+<tr><td>17</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI0:TFF1_LATCH" title="IOI0:TFF1_LATCH">IOI0:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:OFF1_LATCH" title="IOI0:OFF1_LATCH">IOI0:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:TCEINV" title="~IOI0:TCEINV">~IOI0:TCEINV</a></td></tr>
+<tr><td>18</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI0:TFF2_LATCH" title="IOI0:TFF2_LATCH">IOI0:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:OFF2_LATCH" title="IOI0:OFF2_LATCH">IOI0:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[2]">IOI1:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>19</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI0:TMUX" title="IOI0:TMUX[2]">IOI0:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:OMUX" title="IOI0:OMUX[2]">IOI0:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI1:TMUX" title="IOI1:TMUX[2]">IOI1:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:OMUX" title="IOI1:OMUX[2]">IOI1:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI1:TFF2_LATCH" title="IOI1:TFF2_LATCH">IOI1:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:OFF2_LATCH" title="IOI1:OFF2_LATCH">IOI1:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[2]">IOI0:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>22</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI1:TFF1_LATCH" title="IOI1:TFF1_LATCH">IOI1:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:OFF1_LATCH" title="IOI1:OFF1_LATCH">IOI1:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:TCEINV" title="~IOI1:TCEINV">~IOI1:TCEINV</a></td></tr>
+<tr><td>23</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI1:TMUX" title="IOI1:TMUX[0]">IOI1:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:OMUX" title="IOI1:OMUX[0]">IOI1:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:IFF2_SRVAL" title="~IOI1:IFF2_SRVAL">~IOI1:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:OTCLK1INV" title="~IOI1:OTCLK1INV">~IOI1:OTCLK1INV</a></td></tr>
+<tr><td>24</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI1:TMUX" title="IOI1:TMUX[3]">IOI1:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:OMUX" title="IOI1:OMUX[3]">IOI1:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:OTCLK2INV" title="~IOI1:OTCLK2INV">~IOI1:OTCLK2INV</a></td></tr>
+<tr><td>25</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI1:TMUX" title="IOI1:TMUX[1]">IOI1:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:OMUX" title="IOI1:OMUX[1]">IOI1:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:ICEINV" title="~IOI1:ICEINV">~IOI1:ICEINV</a></td></tr>
+<tr><td>26</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI1:TFF_SYNC" title="IOI1:TFF_SYNC">IOI1:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:OFF_SYNC" title="IOI1:OFF_SYNC">IOI1:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:ICLK1INV" title="~IOI1:ICLK1INV">~IOI1:ICLK1INV</a></td></tr>
+<tr><td>27</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI1:T1INV" title="IOI1:T1INV">IOI1:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:O1INV" title="IOI1:O1INV">IOI1:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:IFF2_INIT" title="~IOI1:IFF2_INIT">~IOI1:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:ICLK2INV" title="~IOI1:ICLK2INV">~IOI1:ICLK2INV</a></td></tr>
+<tr><td>28</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI1:T2INV" title="IOI1:T2INV">IOI1:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:O2INV" title="IOI1:O2INV">IOI1:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:IFF_LATCH" title="IOI1:IFF_LATCH">IOI1:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:REVINV" title="~IOI1:REVINV">~IOI1:REVINV</a></td></tr>
+<tr><td>29</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI1:TFF_SR_EN" title="IOI1:TFF_SR_EN">IOI1:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:OFF_SR_EN" title="IOI1:OFF_SR_EN">IOI1:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:IFF_SR_EN" title="IOI1:IFF_SR_EN">IOI1:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:I_DELAY_EN" title="IOI1:I_DELAY_EN">IOI1:I_DELAY_EN</a></td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI1:TFF_REV_EN" title="IOI1:TFF_REV_EN">IOI1:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:OFF_REV_EN" title="IOI1:OFF_REV_EN">IOI1:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:IFF_REV_EN" title="IOI1:IFF_REV_EN">IOI1:IFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[0]">IOI1:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>31</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI1:TFF_INIT" title="~IOI1:TFF_INIT">~IOI1:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:OFF_INIT" title="~IOI1:OFF_INIT">~IOI1:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:IFF_SYNC" title="IOI1:IFF_SYNC">IOI1:IFF_SYNC</a></td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:IFF1_INIT" title="~IOI1:IFF1_INIT">~IOI1:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:I_TSBYPASS_EN" title="IOI1:I_TSBYPASS_EN">IOI1:I_TSBYPASS_EN</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI1:TFF2_SRVAL" title="~IOI1:TFF2_SRVAL">~IOI1:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:OFF2_SRVAL" title="~IOI1:OFF2_SRVAL">~IOI1:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:O1_DDRMUX" title="IOI0:O1_DDRMUX">IOI0:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:TSBYPASS_MUX" title="IOI1:TSBYPASS_MUX">IOI1:TSBYPASS_MUX</a></td></tr>
+<tr><td>36</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI1:TFF1_SRVAL" title="~IOI1:TFF1_SRVAL">~IOI1:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:OFF1_SRVAL" title="~IOI1:OFF1_SRVAL">~IOI1:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:IFF1_SRVAL" title="~IOI1:IFF1_SRVAL">~IOI1:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:IFF_TSBYPASS_EN" title="IOI1:IFF_TSBYPASS_EN">IOI1:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>37</td>
+<td><a href="#bits-xc3s-IOI.S3A.R-IOI0:O2_DDRMUX" title="IOI0:O2_DDRMUX">IOI0:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[1]">IOI0:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:IFF_DELAY_EN" title="IOI1:IFF_DELAY_EN">IOI1:IFF_DELAY_EN</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[0]">IOI1:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[1]">IOI1:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:DELAY_COMMON" title="~IOI0:DELAY_COMMON">~IOI0:DELAY_COMMON</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:DELAY_COMMON" title="~IOI1:DELAY_COMMON">~IOI1:DELAY_COMMON</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:IFF_DELAY" title="~IOI1:IFF_DELAY[0]">~IOI1:IFF_DELAY[0]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:DELAY_VARIABLE" title="IOI0:DELAY_VARIABLE">IOI0:DELAY_VARIABLE</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:I_DELAY" title="~IOI0:I_DELAY[1]">~IOI0:I_DELAY[1]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:I_DELAY" title="~IOI0:I_DELAY[2]">~IOI0:I_DELAY[2]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:IFF_DELAY" title="~IOI0:IFF_DELAY[0]">~IOI0:IFF_DELAY[0]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:I_DELAY" title="~IOI0:I_DELAY[0]">~IOI0:I_DELAY[0]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI0:IFF_DELAY" title="~IOI0:IFF_DELAY[1]">~IOI0:IFF_DELAY[1]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:I_DELAY" title="~IOI1:I_DELAY[0]">~IOI1:I_DELAY[0]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:I_DELAY" title="~IOI1:I_DELAY[1]">~IOI1:I_DELAY[1]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:I_DELAY" title="~IOI1:I_DELAY[2]">~IOI1:I_DELAY[2]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:DELAY_VARIABLE" title="IOI1:DELAY_VARIABLE">IOI1:DELAY_VARIABLE</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.R-IOI1:IFF_DELAY" title="~IOI1:IFF_DELAY[1]">~IOI1:IFF_DELAY[1]</a></td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:O2_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:O2_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O2_DDRMUX</th><th>[0, 0, 37]</th></tr>
+<tr><th>IOI1:O2_DDRMUX</th><th>[0, 0, 2]</th></tr>
+<tr><td>O2</td><td>0</td></tr>
+<tr><td>ODDRIN2</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:TFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_SRVAL</th><th>[0, 0, 3]</th></tr>
+<tr><th>IOI1:TFF1_SRVAL</th><th>[0, 0, 36]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:TFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_SRVAL</th><th>[0, 0, 5]</th></tr>
+<tr><th>IOI1:TFF2_SRVAL</th><th>[0, 0, 34]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:TFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_INIT</th><th>[0, 0, 8]</th></tr>
+<tr><th>IOI1:TFF_INIT</th><th>[0, 0, 31]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:TFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_REV_EN</th><th>[0, 0, 9]</th></tr>
+<tr><th>IOI1:TFF_REV_EN</th><th>[0, 0, 30]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:TFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SR_EN</th><th>[0, 0, 10]</th></tr>
+<tr><th>IOI1:TFF_SR_EN</th><th>[0, 0, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:O1INV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:O2INV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:T1INV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:T2INV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:O1INV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:O2INV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:T1INV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:T2INV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1INV</th><th>[0, 1, 12]</th></tr>
+<tr><th>IOI0:O2INV</th><th>[0, 1, 11]</th></tr>
+<tr><th>IOI0:T1INV</th><th>[0, 0, 12]</th></tr>
+<tr><th>IOI0:T2INV</th><th>[0, 0, 11]</th></tr>
+<tr><th>IOI1:O1INV</th><th>[0, 1, 27]</th></tr>
+<tr><th>IOI1:O2INV</th><th>[0, 1, 28]</th></tr>
+<tr><th>IOI1:T1INV</th><th>[0, 0, 27]</th></tr>
+<tr><th>IOI1:T2INV</th><th>[0, 0, 28]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:TFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SYNC</th><th>[0, 0, 13]</th></tr>
+<tr><th>IOI1:TFF_SYNC</th><th>[0, 0, 26]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:TMUX"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:TMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TMUX</th><th>[0, 0, 15]</th><th>[0, 0, 19]</th><th>[0, 0, 14]</th><th>[0, 0, 16]</th></tr>
+<tr><th>IOI1:TMUX</th><th>[0, 0, 24]</th><th>[0, 0, 20]</th><th>[0, 0, 25]</th><th>[0, 0, 23]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>T1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>T2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>TFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>TFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>TFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:TFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_LATCH</th><th>[0, 0, 17]</th></tr>
+<tr><th>IOI1:TFF1_LATCH</th><th>[0, 0, 22]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:TFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_LATCH</th><th>[0, 0, 18]</th></tr>
+<tr><th>IOI1:TFF2_LATCH</th><th>[0, 0, 21]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:PCICE_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:PCICE_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:PCICE_MUX</th><th>[0, 2, 0]</th><th>[0, 1, 0]</th></tr>
+<tr><th>IOI1:PCICE_MUX</th><th>[0, 2, 39]</th><th>[0, 1, 39]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td></tr>
+<tr><td>OCE</td><td>0</td><td>1</td></tr>
+<tr><td>PCICE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:OFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_SRVAL</th><th>[0, 1, 3]</th></tr>
+<tr><th>IOI1:OFF1_SRVAL</th><th>[0, 1, 36]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:O1_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:O1_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1_DDRMUX</th><th>[0, 1, 35]</th></tr>
+<tr><th>IOI1:O1_DDRMUX</th><th>[0, 1, 4]</th></tr>
+<tr><td>O1</td><td>0</td></tr>
+<tr><td>ODDRIN1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:OFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_SRVAL</th><th>[0, 1, 5]</th></tr>
+<tr><th>IOI1:OFF2_SRVAL</th><th>[0, 1, 34]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:OFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_INIT</th><th>[0, 1, 8]</th></tr>
+<tr><th>IOI1:OFF_INIT</th><th>[0, 1, 31]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:OFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_REV_EN</th><th>[0, 1, 9]</th></tr>
+<tr><th>IOI1:OFF_REV_EN</th><th>[0, 1, 30]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:OFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SR_EN</th><th>[0, 1, 10]</th></tr>
+<tr><th>IOI1:OFF_SR_EN</th><th>[0, 1, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:OFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SYNC</th><th>[0, 1, 13]</th></tr>
+<tr><th>IOI1:OFF_SYNC</th><th>[0, 1, 26]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:OMUX"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:OMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OMUX</th><th>[0, 1, 15]</th><th>[0, 1, 19]</th><th>[0, 1, 14]</th><th>[0, 1, 16]</th></tr>
+<tr><th>IOI1:OMUX</th><th>[0, 1, 24]</th><th>[0, 1, 20]</th><th>[0, 1, 25]</th><th>[0, 1, 23]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>O1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>O2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:OFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_LATCH</th><th>[0, 1, 17]</th></tr>
+<tr><th>IOI1:OFF1_LATCH</th><th>[0, 1, 22]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:OFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_LATCH</th><th>[0, 1, 18]</th></tr>
+<tr><th>IOI1:OFF2_LATCH</th><th>[0, 1, 21]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:IFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_SRVAL</th><th>[0, 2, 3]</th></tr>
+<tr><th>IOI1:IFF1_SRVAL</th><th>[0, 2, 36]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:IFF1_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_INIT</th><th>[0, 2, 7]</th></tr>
+<tr><th>IOI1:IFF1_INIT</th><th>[0, 2, 32]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:IFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SYNC</th><th>[0, 2, 8]</th></tr>
+<tr><th>IOI1:IFF_SYNC</th><th>[0, 2, 31]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:IFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_REV_EN</th><th>[0, 2, 9]</th></tr>
+<tr><th>IOI1:IFF_REV_EN</th><th>[0, 2, 30]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:IFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SR_EN</th><th>[0, 2, 10]</th></tr>
+<tr><th>IOI1:IFF_SR_EN</th><th>[0, 2, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:IFF_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_LATCH</th><th>[0, 2, 11]</th></tr>
+<tr><th>IOI1:IFF_LATCH</th><th>[0, 2, 28]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:IFF2_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_INIT</th><th>[0, 2, 12]</th></tr>
+<tr><th>IOI1:IFF2_INIT</th><th>[0, 2, 27]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:IFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_SRVAL</th><th>[0, 2, 16]</th></tr>
+<tr><th>IOI1:IFF2_SRVAL</th><th>[0, 2, 23]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:IFF_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY_EN</th><th>[0, 3, 1]</th></tr>
+<tr><th>IOI1:IFF_DELAY_EN</th><th>[0, 3, 38]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:IFF_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_TSBYPASS_EN</th><th>[0, 3, 3]</th></tr>
+<tr><th>IOI1:IFF_TSBYPASS_EN</th><th>[0, 3, 36]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:TSBYPASS_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TSBYPASS_MUX</th><th>[0, 3, 4]</th></tr>
+<tr><th>IOI1:TSBYPASS_MUX</th><th>[0, 3, 35]</th></tr>
+<tr><td>TMUX</td><td>0</td></tr>
+<tr><td>GND</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:I_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_TSBYPASS_EN</th><th>[0, 3, 7]</th></tr>
+<tr><th>IOI1:I_TSBYPASS_EN</th><th>[0, 3, 32]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:IDDRIN_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:IDDRIN_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IDDRIN_MUX</th><th>[0, 3, 21]</th><th>[0, 3, 37]</th><th>[0, 3, 8]</th></tr>
+<tr><th>IOI1:IDDRIN_MUX</th><th>[0, 3, 18]</th><th>[0, 3, 2]</th><th>[0, 3, 30]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>IFFDMUX</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>IDDRIN1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>IDDRIN2</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:I_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY_EN</th><th>[0, 3, 10]</th></tr>
+<tr><th>IOI1:I_DELAY_EN</th><th>[0, 3, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:REVINV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:REVINV"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:TCEINV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:ICEINV</th><th>[0, 3, 14]</th></tr>
+<tr><th>IOI0:ICLK1INV</th><th>[0, 3, 13]</th></tr>
+<tr><th>IOI0:ICLK2INV</th><th>[0, 3, 12]</th></tr>
+<tr><th>IOI0:OTCLK1INV</th><th>[0, 3, 16]</th></tr>
+<tr><th>IOI0:OTCLK2INV</th><th>[0, 3, 15]</th></tr>
+<tr><th>IOI0:REVINV</th><th>[0, 3, 11]</th></tr>
+<tr><th>IOI0:TCEINV</th><th>[0, 3, 17]</th></tr>
+<tr><th>IOI1:ICEINV</th><th>[0, 3, 25]</th></tr>
+<tr><th>IOI1:ICLK1INV</th><th>[0, 3, 26]</th></tr>
+<tr><th>IOI1:ICLK2INV</th><th>[0, 3, 27]</th></tr>
+<tr><th>IOI1:OTCLK1INV</th><th>[0, 3, 23]</th></tr>
+<tr><th>IOI1:OTCLK2INV</th><th>[0, 3, 24]</th></tr>
+<tr><th>IOI1:REVINV</th><th>[0, 3, 28]</th></tr>
+<tr><th>IOI1:TCEINV</th><th>[0, 3, 22]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:DELAY_COMMON"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:DELAY_COMMON"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:DELAY_COMMON</th><th>[0, 3, 41]</th></tr>
+<tr><th>IOI1:DELAY_COMMON</th><th>[0, 3, 42]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:IFF_DELAY"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:IFF_DELAY"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY</th><th>[0, 3, 53]</th><th>[0, 3, 51]</th></tr>
+<tr><th>IOI1:IFF_DELAY</th><th>[0, 3, 58]</th><th>[0, 3, 47]</th></tr>
+<tr><td>Inverted</td><td>~[1]</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:DELAY_VARIABLE"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:DELAY_VARIABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:DELAY_VARIABLE</th><th>[0, 3, 48]</th></tr>
+<tr><th>IOI1:DELAY_VARIABLE</th><th>[0, 3, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.R-IOI0:I_DELAY"></div>
+<div id="bits-xc3s-IOI.S3A.R-IOI1:I_DELAY"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY</th><th>[0, 3, 50]</th><th>[0, 3, 49]</th><th>[0, 3, 52]</th></tr>
+<tr><th>IOI1:I_DELAY</th><th>[0, 3, 56]</th><th>[0, 3, 55]</th><th>[0, 3, 54]</th></tr>
+<tr><td>Inverted</td><td>~[2]</td><td>~[1]</td><td>~[0]</td></tr>
+</table>
+</section>
+<section id="ioi-s3a-b">
+<h3><code class="docutils literal notranslate"><span class="pre">IOI.S3A.B</span></code><a class="headerlink" href="#ioi-s3a-b" title="Link to this heading"></a></h3>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[0]">IOI0:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[1]">IOI0:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:IFF_DELAY_EN" title="IOI0:IFF_DELAY_EN">IOI0:IFF_DELAY_EN</a></td></tr>
+<tr><td>2</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI1:O2_DDRMUX" title="IOI1:O2_DDRMUX">IOI1:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[1]">IOI1:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>3</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI0:TFF1_SRVAL" title="~IOI0:TFF1_SRVAL">~IOI0:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:OFF1_SRVAL" title="~IOI0:OFF1_SRVAL">~IOI0:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:IFF1_SRVAL" title="~IOI0:IFF1_SRVAL">~IOI0:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:IFF_TSBYPASS_EN" title="IOI0:IFF_TSBYPASS_EN">IOI0:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:O1_DDRMUX" title="IOI1:O1_DDRMUX">IOI1:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:TSBYPASS_MUX" title="IOI0:TSBYPASS_MUX">IOI0:TSBYPASS_MUX</a></td></tr>
+<tr><td>5</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI0:TFF2_SRVAL" title="~IOI0:TFF2_SRVAL">~IOI0:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:OFF2_SRVAL" title="~IOI0:OFF2_SRVAL">~IOI0:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:IFF1_INIT" title="~IOI0:IFF1_INIT">~IOI0:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:I_TSBYPASS_EN" title="IOI0:I_TSBYPASS_EN">IOI0:I_TSBYPASS_EN</a></td></tr>
+<tr><td>8</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI0:TFF_INIT" title="~IOI0:TFF_INIT">~IOI0:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:OFF_INIT" title="~IOI0:OFF_INIT">~IOI0:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:IFF_SYNC" title="IOI0:IFF_SYNC">IOI0:IFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[0]">IOI0:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>9</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI0:TFF_REV_EN" title="IOI0:TFF_REV_EN">IOI0:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:OFF_REV_EN" title="IOI0:OFF_REV_EN">IOI0:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:IFF_REV_EN" title="IOI0:IFF_REV_EN">IOI0:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>10</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI0:TFF_SR_EN" title="IOI0:TFF_SR_EN">IOI0:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:OFF_SR_EN" title="IOI0:OFF_SR_EN">IOI0:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:IFF_SR_EN" title="IOI0:IFF_SR_EN">IOI0:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:I_DELAY_EN" title="IOI0:I_DELAY_EN">IOI0:I_DELAY_EN</a></td></tr>
+<tr><td>11</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI0:T2INV" title="IOI0:T2INV">IOI0:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:O2INV" title="IOI0:O2INV">IOI0:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:IFF_LATCH" title="IOI0:IFF_LATCH">IOI0:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:REVINV" title="~IOI0:REVINV">~IOI0:REVINV</a></td></tr>
+<tr><td>12</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI0:T1INV" title="IOI0:T1INV">IOI0:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:O1INV" title="IOI0:O1INV">IOI0:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:IFF2_INIT" title="~IOI0:IFF2_INIT">~IOI0:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:ICLK2INV" title="~IOI0:ICLK2INV">~IOI0:ICLK2INV</a></td></tr>
+<tr><td>13</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI0:TFF_SYNC" title="IOI0:TFF_SYNC">IOI0:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:OFF_SYNC" title="IOI0:OFF_SYNC">IOI0:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:ICLK1INV" title="~IOI0:ICLK1INV">~IOI0:ICLK1INV</a></td></tr>
+<tr><td>14</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI0:TMUX" title="IOI0:TMUX[1]">IOI0:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:OMUX" title="IOI0:OMUX[1]">IOI0:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:ICEINV" title="~IOI0:ICEINV">~IOI0:ICEINV</a></td></tr>
+<tr><td>15</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI0:TMUX" title="IOI0:TMUX[3]">IOI0:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:OMUX" title="IOI0:OMUX[3]">IOI0:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:OTCLK2INV" title="~IOI0:OTCLK2INV">~IOI0:OTCLK2INV</a></td></tr>
+<tr><td>16</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI0:TMUX" title="IOI0:TMUX[0]">IOI0:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:OMUX" title="IOI0:OMUX[0]">IOI0:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:IFF2_SRVAL" title="~IOI0:IFF2_SRVAL">~IOI0:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:OTCLK1INV" title="~IOI0:OTCLK1INV">~IOI0:OTCLK1INV</a></td></tr>
+<tr><td>17</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI0:TFF1_LATCH" title="IOI0:TFF1_LATCH">IOI0:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:OFF1_LATCH" title="IOI0:OFF1_LATCH">IOI0:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:TCEINV" title="~IOI0:TCEINV">~IOI0:TCEINV</a></td></tr>
+<tr><td>18</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI0:TFF2_LATCH" title="IOI0:TFF2_LATCH">IOI0:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:OFF2_LATCH" title="IOI0:OFF2_LATCH">IOI0:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[2]">IOI1:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>19</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI0:TMUX" title="IOI0:TMUX[2]">IOI0:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:OMUX" title="IOI0:OMUX[2]">IOI0:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI1:TMUX" title="IOI1:TMUX[2]">IOI1:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:OMUX" title="IOI1:OMUX[2]">IOI1:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI1:TFF2_LATCH" title="IOI1:TFF2_LATCH">IOI1:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:OFF2_LATCH" title="IOI1:OFF2_LATCH">IOI1:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[2]">IOI0:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>22</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI1:TFF1_LATCH" title="IOI1:TFF1_LATCH">IOI1:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:OFF1_LATCH" title="IOI1:OFF1_LATCH">IOI1:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:TCEINV" title="~IOI1:TCEINV">~IOI1:TCEINV</a></td></tr>
+<tr><td>23</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI1:TMUX" title="IOI1:TMUX[0]">IOI1:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:OMUX" title="IOI1:OMUX[0]">IOI1:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:IFF2_SRVAL" title="~IOI1:IFF2_SRVAL">~IOI1:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:OTCLK1INV" title="~IOI1:OTCLK1INV">~IOI1:OTCLK1INV</a></td></tr>
+<tr><td>24</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI1:TMUX" title="IOI1:TMUX[3]">IOI1:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:OMUX" title="IOI1:OMUX[3]">IOI1:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:OTCLK2INV" title="~IOI1:OTCLK2INV">~IOI1:OTCLK2INV</a></td></tr>
+<tr><td>25</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI1:TMUX" title="IOI1:TMUX[1]">IOI1:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:OMUX" title="IOI1:OMUX[1]">IOI1:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:ICEINV" title="~IOI1:ICEINV">~IOI1:ICEINV</a></td></tr>
+<tr><td>26</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI1:TFF_SYNC" title="IOI1:TFF_SYNC">IOI1:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:OFF_SYNC" title="IOI1:OFF_SYNC">IOI1:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:ICLK1INV" title="~IOI1:ICLK1INV">~IOI1:ICLK1INV</a></td></tr>
+<tr><td>27</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI1:T1INV" title="IOI1:T1INV">IOI1:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:O1INV" title="IOI1:O1INV">IOI1:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:IFF2_INIT" title="~IOI1:IFF2_INIT">~IOI1:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:ICLK2INV" title="~IOI1:ICLK2INV">~IOI1:ICLK2INV</a></td></tr>
+<tr><td>28</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI1:T2INV" title="IOI1:T2INV">IOI1:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:O2INV" title="IOI1:O2INV">IOI1:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:IFF_LATCH" title="IOI1:IFF_LATCH">IOI1:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:REVINV" title="~IOI1:REVINV">~IOI1:REVINV</a></td></tr>
+<tr><td>29</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI1:TFF_SR_EN" title="IOI1:TFF_SR_EN">IOI1:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:OFF_SR_EN" title="IOI1:OFF_SR_EN">IOI1:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:IFF_SR_EN" title="IOI1:IFF_SR_EN">IOI1:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:I_DELAY_EN" title="IOI1:I_DELAY_EN">IOI1:I_DELAY_EN</a></td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI1:TFF_REV_EN" title="IOI1:TFF_REV_EN">IOI1:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:OFF_REV_EN" title="IOI1:OFF_REV_EN">IOI1:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:IFF_REV_EN" title="IOI1:IFF_REV_EN">IOI1:IFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[0]">IOI1:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>31</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI1:TFF_INIT" title="~IOI1:TFF_INIT">~IOI1:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:OFF_INIT" title="~IOI1:OFF_INIT">~IOI1:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:IFF_SYNC" title="IOI1:IFF_SYNC">IOI1:IFF_SYNC</a></td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:IFF1_INIT" title="~IOI1:IFF1_INIT">~IOI1:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:I_TSBYPASS_EN" title="IOI1:I_TSBYPASS_EN">IOI1:I_TSBYPASS_EN</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI1:TFF2_SRVAL" title="~IOI1:TFF2_SRVAL">~IOI1:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:OFF2_SRVAL" title="~IOI1:OFF2_SRVAL">~IOI1:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:O1_DDRMUX" title="IOI0:O1_DDRMUX">IOI0:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:TSBYPASS_MUX" title="IOI1:TSBYPASS_MUX">IOI1:TSBYPASS_MUX</a></td></tr>
+<tr><td>36</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI1:TFF1_SRVAL" title="~IOI1:TFF1_SRVAL">~IOI1:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:OFF1_SRVAL" title="~IOI1:OFF1_SRVAL">~IOI1:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:IFF1_SRVAL" title="~IOI1:IFF1_SRVAL">~IOI1:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:IFF_TSBYPASS_EN" title="IOI1:IFF_TSBYPASS_EN">IOI1:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>37</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI0:O2_DDRMUX" title="IOI0:O2_DDRMUX">IOI0:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[1]">IOI0:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:IFF_DELAY_EN" title="IOI1:IFF_DELAY_EN">IOI1:IFF_DELAY_EN</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[0]">IOI1:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[1]">IOI1:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:PCICE_MUX" title="IOI2:PCICE_MUX[0]">IOI2:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:PCICE_MUX" title="IOI2:PCICE_MUX[1]">IOI2:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:IFF_DELAY_EN" title="IOI2:IFF_DELAY_EN">IOI2:IFF_DELAY_EN</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:IDDRIN_MUX" title="IOI2:IDDRIN_MUX[1]">IOI2:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>43</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI2:TFF1_SRVAL" title="~IOI2:TFF1_SRVAL">~IOI2:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:OFF1_SRVAL" title="~IOI2:OFF1_SRVAL">~IOI2:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:IFF1_SRVAL" title="~IOI2:IFF1_SRVAL">~IOI2:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:IFF_TSBYPASS_EN" title="IOI2:IFF_TSBYPASS_EN">IOI2:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:TSBYPASS_MUX" title="IOI2:TSBYPASS_MUX">IOI2:TSBYPASS_MUX</a></td></tr>
+<tr><td>45</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI2:TFF2_SRVAL" title="~IOI2:TFF2_SRVAL">~IOI2:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:OFF2_SRVAL" title="~IOI2:OFF2_SRVAL">~IOI2:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:IFF1_INIT" title="~IOI2:IFF1_INIT">~IOI2:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:I_TSBYPASS_EN" title="IOI2:I_TSBYPASS_EN">IOI2:I_TSBYPASS_EN</a></td></tr>
+<tr><td>48</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI2:TFF_INIT" title="~IOI2:TFF_INIT">~IOI2:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:OFF_INIT" title="~IOI2:OFF_INIT">~IOI2:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:IFF_SYNC" title="IOI2:IFF_SYNC">IOI2:IFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:IDDRIN_MUX" title="IOI2:IDDRIN_MUX[0]">IOI2:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>49</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI2:TFF_REV_EN" title="IOI2:TFF_REV_EN">IOI2:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:OFF_REV_EN" title="IOI2:OFF_REV_EN">IOI2:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:IFF_REV_EN" title="IOI2:IFF_REV_EN">IOI2:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>50</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI2:TFF_SR_EN" title="IOI2:TFF_SR_EN">IOI2:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:OFF_SR_EN" title="IOI2:OFF_SR_EN">IOI2:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:IFF_SR_EN" title="IOI2:IFF_SR_EN">IOI2:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:I_DELAY_EN" title="IOI2:I_DELAY_EN">IOI2:I_DELAY_EN</a></td></tr>
+<tr><td>51</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI2:T2INV" title="IOI2:T2INV">IOI2:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:O2INV" title="IOI2:O2INV">IOI2:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:IFF_LATCH" title="IOI2:IFF_LATCH">IOI2:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:REVINV" title="~IOI2:REVINV">~IOI2:REVINV</a></td></tr>
+<tr><td>52</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI2:T1INV" title="IOI2:T1INV">IOI2:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:O1INV" title="IOI2:O1INV">IOI2:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:IFF2_INIT" title="~IOI2:IFF2_INIT">~IOI2:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:ICLK2INV" title="~IOI2:ICLK2INV">~IOI2:ICLK2INV</a></td></tr>
+<tr><td>53</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI2:TFF_SYNC" title="IOI2:TFF_SYNC">IOI2:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:OFF_SYNC" title="IOI2:OFF_SYNC">IOI2:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:ICLK1INV" title="~IOI2:ICLK1INV">~IOI2:ICLK1INV</a></td></tr>
+<tr><td>54</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI2:TMUX" title="IOI2:TMUX[1]">IOI2:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:OMUX" title="IOI2:OMUX[1]">IOI2:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:ICEINV" title="~IOI2:ICEINV">~IOI2:ICEINV</a></td></tr>
+<tr><td>55</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI2:TMUX" title="IOI2:TMUX[3]">IOI2:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:OMUX" title="IOI2:OMUX[3]">IOI2:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:OTCLK2INV" title="~IOI2:OTCLK2INV">~IOI2:OTCLK2INV</a></td></tr>
+<tr><td>56</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI2:TMUX" title="IOI2:TMUX[0]">IOI2:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:OMUX" title="IOI2:OMUX[0]">IOI2:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:IFF2_SRVAL" title="~IOI2:IFF2_SRVAL">~IOI2:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:OTCLK1INV" title="~IOI2:OTCLK1INV">~IOI2:OTCLK1INV</a></td></tr>
+<tr><td>57</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI2:TFF1_LATCH" title="IOI2:TFF1_LATCH">IOI2:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:OFF1_LATCH" title="IOI2:OFF1_LATCH">IOI2:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:TCEINV" title="~IOI2:TCEINV">~IOI2:TCEINV</a></td></tr>
+<tr><td>58</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI2:TFF2_LATCH" title="IOI2:TFF2_LATCH">IOI2:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:OFF2_LATCH" title="IOI2:OFF2_LATCH">IOI2:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:IDDRIN_MUX" title="IOI2:IDDRIN_MUX[2]">IOI2:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>59</td>
+<td><a href="#bits-xc3s-IOI.S3A.B-IOI2:TMUX" title="IOI2:TMUX[2]">IOI2:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3A.B-IOI2:OMUX" title="IOI2:OMUX[2]">IOI2:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:O2_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:O2_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O2_DDRMUX</th><th>[0, 0, 37]</th></tr>
+<tr><th>IOI1:O2_DDRMUX</th><th>[0, 0, 2]</th></tr>
+<tr><td>O2</td><td>0</td></tr>
+<tr><td>ODDRIN2</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:TFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_SRVAL</th><th>[0, 0, 3]</th></tr>
+<tr><th>IOI1:TFF1_SRVAL</th><th>[0, 0, 36]</th></tr>
+<tr><th>IOI2:TFF1_SRVAL</th><th>[0, 0, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:TFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_SRVAL</th><th>[0, 0, 5]</th></tr>
+<tr><th>IOI1:TFF2_SRVAL</th><th>[0, 0, 34]</th></tr>
+<tr><th>IOI2:TFF2_SRVAL</th><th>[0, 0, 45]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:TFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_INIT</th><th>[0, 0, 8]</th></tr>
+<tr><th>IOI1:TFF_INIT</th><th>[0, 0, 31]</th></tr>
+<tr><th>IOI2:TFF_INIT</th><th>[0, 0, 48]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:TFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_REV_EN</th><th>[0, 0, 9]</th></tr>
+<tr><th>IOI1:TFF_REV_EN</th><th>[0, 0, 30]</th></tr>
+<tr><th>IOI2:TFF_REV_EN</th><th>[0, 0, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:TFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SR_EN</th><th>[0, 0, 10]</th></tr>
+<tr><th>IOI1:TFF_SR_EN</th><th>[0, 0, 29]</th></tr>
+<tr><th>IOI2:TFF_SR_EN</th><th>[0, 0, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:O1INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:O2INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:T1INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:T2INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:O1INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:O2INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:T1INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:T2INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:O1INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:O2INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:T1INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:T2INV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1INV</th><th>[0, 1, 12]</th></tr>
+<tr><th>IOI0:O2INV</th><th>[0, 1, 11]</th></tr>
+<tr><th>IOI0:T1INV</th><th>[0, 0, 12]</th></tr>
+<tr><th>IOI0:T2INV</th><th>[0, 0, 11]</th></tr>
+<tr><th>IOI1:O1INV</th><th>[0, 1, 27]</th></tr>
+<tr><th>IOI1:O2INV</th><th>[0, 1, 28]</th></tr>
+<tr><th>IOI1:T1INV</th><th>[0, 0, 27]</th></tr>
+<tr><th>IOI1:T2INV</th><th>[0, 0, 28]</th></tr>
+<tr><th>IOI2:O1INV</th><th>[0, 1, 52]</th></tr>
+<tr><th>IOI2:O2INV</th><th>[0, 1, 51]</th></tr>
+<tr><th>IOI2:T1INV</th><th>[0, 0, 52]</th></tr>
+<tr><th>IOI2:T2INV</th><th>[0, 0, 51]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:TFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SYNC</th><th>[0, 0, 13]</th></tr>
+<tr><th>IOI1:TFF_SYNC</th><th>[0, 0, 26]</th></tr>
+<tr><th>IOI2:TFF_SYNC</th><th>[0, 0, 53]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:TMUX"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:TMUX"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:TMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TMUX</th><th>[0, 0, 15]</th><th>[0, 0, 19]</th><th>[0, 0, 14]</th><th>[0, 0, 16]</th></tr>
+<tr><th>IOI1:TMUX</th><th>[0, 0, 24]</th><th>[0, 0, 20]</th><th>[0, 0, 25]</th><th>[0, 0, 23]</th></tr>
+<tr><th>IOI2:TMUX</th><th>[0, 0, 55]</th><th>[0, 0, 59]</th><th>[0, 0, 54]</th><th>[0, 0, 56]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>T1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>T2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>TFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>TFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>TFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:TFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_LATCH</th><th>[0, 0, 17]</th></tr>
+<tr><th>IOI1:TFF1_LATCH</th><th>[0, 0, 22]</th></tr>
+<tr><th>IOI2:TFF1_LATCH</th><th>[0, 0, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:TFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_LATCH</th><th>[0, 0, 18]</th></tr>
+<tr><th>IOI1:TFF2_LATCH</th><th>[0, 0, 21]</th></tr>
+<tr><th>IOI2:TFF2_LATCH</th><th>[0, 0, 58]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:PCICE_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:PCICE_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:PCICE_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:PCICE_MUX</th><th>[0, 2, 0]</th><th>[0, 1, 0]</th></tr>
+<tr><th>IOI1:PCICE_MUX</th><th>[0, 2, 39]</th><th>[0, 1, 39]</th></tr>
+<tr><th>IOI2:PCICE_MUX</th><th>[0, 2, 40]</th><th>[0, 1, 40]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td></tr>
+<tr><td>OCE</td><td>0</td><td>1</td></tr>
+<tr><td>PCICE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:OFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_SRVAL</th><th>[0, 1, 3]</th></tr>
+<tr><th>IOI1:OFF1_SRVAL</th><th>[0, 1, 36]</th></tr>
+<tr><th>IOI2:OFF1_SRVAL</th><th>[0, 1, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:O1_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:O1_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1_DDRMUX</th><th>[0, 1, 35]</th></tr>
+<tr><th>IOI1:O1_DDRMUX</th><th>[0, 1, 4]</th></tr>
+<tr><td>O1</td><td>0</td></tr>
+<tr><td>ODDRIN1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:OFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_SRVAL</th><th>[0, 1, 5]</th></tr>
+<tr><th>IOI1:OFF2_SRVAL</th><th>[0, 1, 34]</th></tr>
+<tr><th>IOI2:OFF2_SRVAL</th><th>[0, 1, 45]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:OFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_INIT</th><th>[0, 1, 8]</th></tr>
+<tr><th>IOI1:OFF_INIT</th><th>[0, 1, 31]</th></tr>
+<tr><th>IOI2:OFF_INIT</th><th>[0, 1, 48]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:OFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_REV_EN</th><th>[0, 1, 9]</th></tr>
+<tr><th>IOI1:OFF_REV_EN</th><th>[0, 1, 30]</th></tr>
+<tr><th>IOI2:OFF_REV_EN</th><th>[0, 1, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:OFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SR_EN</th><th>[0, 1, 10]</th></tr>
+<tr><th>IOI1:OFF_SR_EN</th><th>[0, 1, 29]</th></tr>
+<tr><th>IOI2:OFF_SR_EN</th><th>[0, 1, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:OFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SYNC</th><th>[0, 1, 13]</th></tr>
+<tr><th>IOI1:OFF_SYNC</th><th>[0, 1, 26]</th></tr>
+<tr><th>IOI2:OFF_SYNC</th><th>[0, 1, 53]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:OMUX"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:OMUX"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:OMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OMUX</th><th>[0, 1, 15]</th><th>[0, 1, 19]</th><th>[0, 1, 14]</th><th>[0, 1, 16]</th></tr>
+<tr><th>IOI1:OMUX</th><th>[0, 1, 24]</th><th>[0, 1, 20]</th><th>[0, 1, 25]</th><th>[0, 1, 23]</th></tr>
+<tr><th>IOI2:OMUX</th><th>[0, 1, 55]</th><th>[0, 1, 59]</th><th>[0, 1, 54]</th><th>[0, 1, 56]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>O1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>O2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:OFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_LATCH</th><th>[0, 1, 17]</th></tr>
+<tr><th>IOI1:OFF1_LATCH</th><th>[0, 1, 22]</th></tr>
+<tr><th>IOI2:OFF1_LATCH</th><th>[0, 1, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:OFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_LATCH</th><th>[0, 1, 18]</th></tr>
+<tr><th>IOI1:OFF2_LATCH</th><th>[0, 1, 21]</th></tr>
+<tr><th>IOI2:OFF2_LATCH</th><th>[0, 1, 58]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:IFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_SRVAL</th><th>[0, 2, 3]</th></tr>
+<tr><th>IOI1:IFF1_SRVAL</th><th>[0, 2, 36]</th></tr>
+<tr><th>IOI2:IFF1_SRVAL</th><th>[0, 2, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:IFF1_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_INIT</th><th>[0, 2, 7]</th></tr>
+<tr><th>IOI1:IFF1_INIT</th><th>[0, 2, 32]</th></tr>
+<tr><th>IOI2:IFF1_INIT</th><th>[0, 2, 47]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:IFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SYNC</th><th>[0, 2, 8]</th></tr>
+<tr><th>IOI1:IFF_SYNC</th><th>[0, 2, 31]</th></tr>
+<tr><th>IOI2:IFF_SYNC</th><th>[0, 2, 48]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:IFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_REV_EN</th><th>[0, 2, 9]</th></tr>
+<tr><th>IOI1:IFF_REV_EN</th><th>[0, 2, 30]</th></tr>
+<tr><th>IOI2:IFF_REV_EN</th><th>[0, 2, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:IFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SR_EN</th><th>[0, 2, 10]</th></tr>
+<tr><th>IOI1:IFF_SR_EN</th><th>[0, 2, 29]</th></tr>
+<tr><th>IOI2:IFF_SR_EN</th><th>[0, 2, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:IFF_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_LATCH</th><th>[0, 2, 11]</th></tr>
+<tr><th>IOI1:IFF_LATCH</th><th>[0, 2, 28]</th></tr>
+<tr><th>IOI2:IFF_LATCH</th><th>[0, 2, 51]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:IFF2_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_INIT</th><th>[0, 2, 12]</th></tr>
+<tr><th>IOI1:IFF2_INIT</th><th>[0, 2, 27]</th></tr>
+<tr><th>IOI2:IFF2_INIT</th><th>[0, 2, 52]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:IFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_SRVAL</th><th>[0, 2, 16]</th></tr>
+<tr><th>IOI1:IFF2_SRVAL</th><th>[0, 2, 23]</th></tr>
+<tr><th>IOI2:IFF2_SRVAL</th><th>[0, 2, 56]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:IFF_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY_EN</th><th>[0, 3, 1]</th></tr>
+<tr><th>IOI1:IFF_DELAY_EN</th><th>[0, 3, 38]</th></tr>
+<tr><th>IOI2:IFF_DELAY_EN</th><th>[0, 3, 41]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:IFF_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_TSBYPASS_EN</th><th>[0, 3, 3]</th></tr>
+<tr><th>IOI1:IFF_TSBYPASS_EN</th><th>[0, 3, 36]</th></tr>
+<tr><th>IOI2:IFF_TSBYPASS_EN</th><th>[0, 3, 43]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:TSBYPASS_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TSBYPASS_MUX</th><th>[0, 3, 4]</th></tr>
+<tr><th>IOI1:TSBYPASS_MUX</th><th>[0, 3, 35]</th></tr>
+<tr><th>IOI2:TSBYPASS_MUX</th><th>[0, 3, 44]</th></tr>
+<tr><td>TMUX</td><td>0</td></tr>
+<tr><td>GND</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:I_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_TSBYPASS_EN</th><th>[0, 3, 7]</th></tr>
+<tr><th>IOI1:I_TSBYPASS_EN</th><th>[0, 3, 32]</th></tr>
+<tr><th>IOI2:I_TSBYPASS_EN</th><th>[0, 3, 47]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:IDDRIN_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:IDDRIN_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:IDDRIN_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IDDRIN_MUX</th><th>[0, 3, 21]</th><th>[0, 3, 37]</th><th>[0, 3, 8]</th></tr>
+<tr><th>IOI1:IDDRIN_MUX</th><th>[0, 3, 18]</th><th>[0, 3, 2]</th><th>[0, 3, 30]</th></tr>
+<tr><th>IOI2:IDDRIN_MUX</th><th>[0, 3, 58]</th><th>[0, 3, 42]</th><th>[0, 3, 48]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>IFFDMUX</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>IDDRIN1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>IDDRIN2</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:I_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY_EN</th><th>[0, 3, 10]</th></tr>
+<tr><th>IOI1:I_DELAY_EN</th><th>[0, 3, 29]</th></tr>
+<tr><th>IOI2:I_DELAY_EN</th><th>[0, 3, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:REVINV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI0:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:REVINV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI1:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:REVINV"></div>
+<div id="bits-xc3s-IOI.S3A.B-IOI2:TCEINV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:ICEINV</th><th>[0, 3, 14]</th></tr>
+<tr><th>IOI0:ICLK1INV</th><th>[0, 3, 13]</th></tr>
+<tr><th>IOI0:ICLK2INV</th><th>[0, 3, 12]</th></tr>
+<tr><th>IOI0:OTCLK1INV</th><th>[0, 3, 16]</th></tr>
+<tr><th>IOI0:OTCLK2INV</th><th>[0, 3, 15]</th></tr>
+<tr><th>IOI0:REVINV</th><th>[0, 3, 11]</th></tr>
+<tr><th>IOI0:TCEINV</th><th>[0, 3, 17]</th></tr>
+<tr><th>IOI1:ICEINV</th><th>[0, 3, 25]</th></tr>
+<tr><th>IOI1:ICLK1INV</th><th>[0, 3, 26]</th></tr>
+<tr><th>IOI1:ICLK2INV</th><th>[0, 3, 27]</th></tr>
+<tr><th>IOI1:OTCLK1INV</th><th>[0, 3, 23]</th></tr>
+<tr><th>IOI1:OTCLK2INV</th><th>[0, 3, 24]</th></tr>
+<tr><th>IOI1:REVINV</th><th>[0, 3, 28]</th></tr>
+<tr><th>IOI1:TCEINV</th><th>[0, 3, 22]</th></tr>
+<tr><th>IOI2:ICEINV</th><th>[0, 3, 54]</th></tr>
+<tr><th>IOI2:ICLK1INV</th><th>[0, 3, 53]</th></tr>
+<tr><th>IOI2:ICLK2INV</th><th>[0, 3, 52]</th></tr>
+<tr><th>IOI2:OTCLK1INV</th><th>[0, 3, 56]</th></tr>
+<tr><th>IOI2:OTCLK2INV</th><th>[0, 3, 55]</th></tr>
+<tr><th>IOI2:REVINV</th><th>[0, 3, 51]</th></tr>
+<tr><th>IOI2:TCEINV</th><th>[0, 3, 57]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+</section>
+<section id="ioi-s3a-t">
+<h3><code class="docutils literal notranslate"><span class="pre">IOI.S3A.T</span></code><a class="headerlink" href="#ioi-s3a-t" title="Link to this heading"></a></h3>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[0]">IOI0:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[1]">IOI0:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:IFF_DELAY_EN" title="IOI0:IFF_DELAY_EN">IOI0:IFF_DELAY_EN</a></td></tr>
+<tr><td>2</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI1:O2_DDRMUX" title="IOI1:O2_DDRMUX">IOI1:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[1]">IOI1:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>3</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI0:TFF1_SRVAL" title="~IOI0:TFF1_SRVAL">~IOI0:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:OFF1_SRVAL" title="~IOI0:OFF1_SRVAL">~IOI0:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:IFF1_SRVAL" title="~IOI0:IFF1_SRVAL">~IOI0:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:IFF_TSBYPASS_EN" title="IOI0:IFF_TSBYPASS_EN">IOI0:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:O1_DDRMUX" title="IOI1:O1_DDRMUX">IOI1:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:TSBYPASS_MUX" title="IOI0:TSBYPASS_MUX">IOI0:TSBYPASS_MUX</a></td></tr>
+<tr><td>5</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI0:TFF2_SRVAL" title="~IOI0:TFF2_SRVAL">~IOI0:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:OFF2_SRVAL" title="~IOI0:OFF2_SRVAL">~IOI0:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:IFF1_INIT" title="~IOI0:IFF1_INIT">~IOI0:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:I_TSBYPASS_EN" title="IOI0:I_TSBYPASS_EN">IOI0:I_TSBYPASS_EN</a></td></tr>
+<tr><td>8</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI0:TFF_INIT" title="~IOI0:TFF_INIT">~IOI0:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:OFF_INIT" title="~IOI0:OFF_INIT">~IOI0:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:IFF_SYNC" title="IOI0:IFF_SYNC">IOI0:IFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[0]">IOI0:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>9</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI0:TFF_REV_EN" title="IOI0:TFF_REV_EN">IOI0:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:OFF_REV_EN" title="IOI0:OFF_REV_EN">IOI0:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:IFF_REV_EN" title="IOI0:IFF_REV_EN">IOI0:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>10</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI0:TFF_SR_EN" title="IOI0:TFF_SR_EN">IOI0:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:OFF_SR_EN" title="IOI0:OFF_SR_EN">IOI0:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:IFF_SR_EN" title="IOI0:IFF_SR_EN">IOI0:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:I_DELAY_EN" title="IOI0:I_DELAY_EN">IOI0:I_DELAY_EN</a></td></tr>
+<tr><td>11</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI0:T2INV" title="IOI0:T2INV">IOI0:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:O2INV" title="IOI0:O2INV">IOI0:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:IFF_LATCH" title="IOI0:IFF_LATCH">IOI0:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:REVINV" title="~IOI0:REVINV">~IOI0:REVINV</a></td></tr>
+<tr><td>12</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI0:T1INV" title="IOI0:T1INV">IOI0:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:O1INV" title="IOI0:O1INV">IOI0:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:IFF2_INIT" title="~IOI0:IFF2_INIT">~IOI0:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:ICLK2INV" title="~IOI0:ICLK2INV">~IOI0:ICLK2INV</a></td></tr>
+<tr><td>13</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI0:TFF_SYNC" title="IOI0:TFF_SYNC">IOI0:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:OFF_SYNC" title="IOI0:OFF_SYNC">IOI0:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:ICLK1INV" title="~IOI0:ICLK1INV">~IOI0:ICLK1INV</a></td></tr>
+<tr><td>14</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI0:TMUX" title="IOI0:TMUX[1]">IOI0:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:OMUX" title="IOI0:OMUX[1]">IOI0:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:ICEINV" title="~IOI0:ICEINV">~IOI0:ICEINV</a></td></tr>
+<tr><td>15</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI0:TMUX" title="IOI0:TMUX[3]">IOI0:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:OMUX" title="IOI0:OMUX[3]">IOI0:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:OTCLK2INV" title="~IOI0:OTCLK2INV">~IOI0:OTCLK2INV</a></td></tr>
+<tr><td>16</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI0:TMUX" title="IOI0:TMUX[0]">IOI0:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:OMUX" title="IOI0:OMUX[0]">IOI0:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:IFF2_SRVAL" title="~IOI0:IFF2_SRVAL">~IOI0:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:OTCLK1INV" title="~IOI0:OTCLK1INV">~IOI0:OTCLK1INV</a></td></tr>
+<tr><td>17</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI0:TFF1_LATCH" title="IOI0:TFF1_LATCH">IOI0:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:OFF1_LATCH" title="IOI0:OFF1_LATCH">IOI0:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:TCEINV" title="~IOI0:TCEINV">~IOI0:TCEINV</a></td></tr>
+<tr><td>18</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI0:TFF2_LATCH" title="IOI0:TFF2_LATCH">IOI0:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:OFF2_LATCH" title="IOI0:OFF2_LATCH">IOI0:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[2]">IOI1:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>19</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI0:TMUX" title="IOI0:TMUX[2]">IOI0:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:OMUX" title="IOI0:OMUX[2]">IOI0:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI1:TMUX" title="IOI1:TMUX[2]">IOI1:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:OMUX" title="IOI1:OMUX[2]">IOI1:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI1:TFF2_LATCH" title="IOI1:TFF2_LATCH">IOI1:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:OFF2_LATCH" title="IOI1:OFF2_LATCH">IOI1:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[2]">IOI0:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>22</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI1:TFF1_LATCH" title="IOI1:TFF1_LATCH">IOI1:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:OFF1_LATCH" title="IOI1:OFF1_LATCH">IOI1:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:TCEINV" title="~IOI1:TCEINV">~IOI1:TCEINV</a></td></tr>
+<tr><td>23</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI1:TMUX" title="IOI1:TMUX[0]">IOI1:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:OMUX" title="IOI1:OMUX[0]">IOI1:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:IFF2_SRVAL" title="~IOI1:IFF2_SRVAL">~IOI1:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:OTCLK1INV" title="~IOI1:OTCLK1INV">~IOI1:OTCLK1INV</a></td></tr>
+<tr><td>24</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI1:TMUX" title="IOI1:TMUX[3]">IOI1:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:OMUX" title="IOI1:OMUX[3]">IOI1:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:OTCLK2INV" title="~IOI1:OTCLK2INV">~IOI1:OTCLK2INV</a></td></tr>
+<tr><td>25</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI1:TMUX" title="IOI1:TMUX[1]">IOI1:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:OMUX" title="IOI1:OMUX[1]">IOI1:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:ICEINV" title="~IOI1:ICEINV">~IOI1:ICEINV</a></td></tr>
+<tr><td>26</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI1:TFF_SYNC" title="IOI1:TFF_SYNC">IOI1:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:OFF_SYNC" title="IOI1:OFF_SYNC">IOI1:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:ICLK1INV" title="~IOI1:ICLK1INV">~IOI1:ICLK1INV</a></td></tr>
+<tr><td>27</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI1:T1INV" title="IOI1:T1INV">IOI1:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:O1INV" title="IOI1:O1INV">IOI1:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:IFF2_INIT" title="~IOI1:IFF2_INIT">~IOI1:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:ICLK2INV" title="~IOI1:ICLK2INV">~IOI1:ICLK2INV</a></td></tr>
+<tr><td>28</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI1:T2INV" title="IOI1:T2INV">IOI1:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:O2INV" title="IOI1:O2INV">IOI1:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:IFF_LATCH" title="IOI1:IFF_LATCH">IOI1:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:REVINV" title="~IOI1:REVINV">~IOI1:REVINV</a></td></tr>
+<tr><td>29</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI1:TFF_SR_EN" title="IOI1:TFF_SR_EN">IOI1:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:OFF_SR_EN" title="IOI1:OFF_SR_EN">IOI1:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:IFF_SR_EN" title="IOI1:IFF_SR_EN">IOI1:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:I_DELAY_EN" title="IOI1:I_DELAY_EN">IOI1:I_DELAY_EN</a></td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI1:TFF_REV_EN" title="IOI1:TFF_REV_EN">IOI1:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:OFF_REV_EN" title="IOI1:OFF_REV_EN">IOI1:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:IFF_REV_EN" title="IOI1:IFF_REV_EN">IOI1:IFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[0]">IOI1:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>31</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI1:TFF_INIT" title="~IOI1:TFF_INIT">~IOI1:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:OFF_INIT" title="~IOI1:OFF_INIT">~IOI1:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:IFF_SYNC" title="IOI1:IFF_SYNC">IOI1:IFF_SYNC</a></td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:IFF1_INIT" title="~IOI1:IFF1_INIT">~IOI1:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:I_TSBYPASS_EN" title="IOI1:I_TSBYPASS_EN">IOI1:I_TSBYPASS_EN</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI1:TFF2_SRVAL" title="~IOI1:TFF2_SRVAL">~IOI1:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:OFF2_SRVAL" title="~IOI1:OFF2_SRVAL">~IOI1:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:O1_DDRMUX" title="IOI0:O1_DDRMUX">IOI0:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:TSBYPASS_MUX" title="IOI1:TSBYPASS_MUX">IOI1:TSBYPASS_MUX</a></td></tr>
+<tr><td>36</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI1:TFF1_SRVAL" title="~IOI1:TFF1_SRVAL">~IOI1:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:OFF1_SRVAL" title="~IOI1:OFF1_SRVAL">~IOI1:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:IFF1_SRVAL" title="~IOI1:IFF1_SRVAL">~IOI1:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:IFF_TSBYPASS_EN" title="IOI1:IFF_TSBYPASS_EN">IOI1:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>37</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI0:O2_DDRMUX" title="IOI0:O2_DDRMUX">IOI0:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[1]">IOI0:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:IFF_DELAY_EN" title="IOI1:IFF_DELAY_EN">IOI1:IFF_DELAY_EN</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[0]">IOI1:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[1]">IOI1:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:PCICE_MUX" title="IOI2:PCICE_MUX[0]">IOI2:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:PCICE_MUX" title="IOI2:PCICE_MUX[1]">IOI2:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:IFF_DELAY_EN" title="IOI2:IFF_DELAY_EN">IOI2:IFF_DELAY_EN</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:IDDRIN_MUX" title="IOI2:IDDRIN_MUX[1]">IOI2:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>43</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI2:TFF1_SRVAL" title="~IOI2:TFF1_SRVAL">~IOI2:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:OFF1_SRVAL" title="~IOI2:OFF1_SRVAL">~IOI2:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:IFF1_SRVAL" title="~IOI2:IFF1_SRVAL">~IOI2:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:IFF_TSBYPASS_EN" title="IOI2:IFF_TSBYPASS_EN">IOI2:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:TSBYPASS_MUX" title="IOI2:TSBYPASS_MUX">IOI2:TSBYPASS_MUX</a></td></tr>
+<tr><td>45</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI2:TFF2_SRVAL" title="~IOI2:TFF2_SRVAL">~IOI2:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:OFF2_SRVAL" title="~IOI2:OFF2_SRVAL">~IOI2:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:IFF1_INIT" title="~IOI2:IFF1_INIT">~IOI2:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:I_TSBYPASS_EN" title="IOI2:I_TSBYPASS_EN">IOI2:I_TSBYPASS_EN</a></td></tr>
+<tr><td>48</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI2:TFF_INIT" title="~IOI2:TFF_INIT">~IOI2:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:OFF_INIT" title="~IOI2:OFF_INIT">~IOI2:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:IFF_SYNC" title="IOI2:IFF_SYNC">IOI2:IFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:IDDRIN_MUX" title="IOI2:IDDRIN_MUX[0]">IOI2:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>49</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI2:TFF_REV_EN" title="IOI2:TFF_REV_EN">IOI2:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:OFF_REV_EN" title="IOI2:OFF_REV_EN">IOI2:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:IFF_REV_EN" title="IOI2:IFF_REV_EN">IOI2:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>50</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI2:TFF_SR_EN" title="IOI2:TFF_SR_EN">IOI2:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:OFF_SR_EN" title="IOI2:OFF_SR_EN">IOI2:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:IFF_SR_EN" title="IOI2:IFF_SR_EN">IOI2:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:I_DELAY_EN" title="IOI2:I_DELAY_EN">IOI2:I_DELAY_EN</a></td></tr>
+<tr><td>51</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI2:T2INV" title="IOI2:T2INV">IOI2:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:O2INV" title="IOI2:O2INV">IOI2:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:IFF_LATCH" title="IOI2:IFF_LATCH">IOI2:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:REVINV" title="~IOI2:REVINV">~IOI2:REVINV</a></td></tr>
+<tr><td>52</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI2:T1INV" title="IOI2:T1INV">IOI2:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:O1INV" title="IOI2:O1INV">IOI2:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:IFF2_INIT" title="~IOI2:IFF2_INIT">~IOI2:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:ICLK2INV" title="~IOI2:ICLK2INV">~IOI2:ICLK2INV</a></td></tr>
+<tr><td>53</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI2:TFF_SYNC" title="IOI2:TFF_SYNC">IOI2:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:OFF_SYNC" title="IOI2:OFF_SYNC">IOI2:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:ICLK1INV" title="~IOI2:ICLK1INV">~IOI2:ICLK1INV</a></td></tr>
+<tr><td>54</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI2:TMUX" title="IOI2:TMUX[1]">IOI2:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:OMUX" title="IOI2:OMUX[1]">IOI2:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:ICEINV" title="~IOI2:ICEINV">~IOI2:ICEINV</a></td></tr>
+<tr><td>55</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI2:TMUX" title="IOI2:TMUX[3]">IOI2:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:OMUX" title="IOI2:OMUX[3]">IOI2:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:OTCLK2INV" title="~IOI2:OTCLK2INV">~IOI2:OTCLK2INV</a></td></tr>
+<tr><td>56</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI2:TMUX" title="IOI2:TMUX[0]">IOI2:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:OMUX" title="IOI2:OMUX[0]">IOI2:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:IFF2_SRVAL" title="~IOI2:IFF2_SRVAL">~IOI2:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:OTCLK1INV" title="~IOI2:OTCLK1INV">~IOI2:OTCLK1INV</a></td></tr>
+<tr><td>57</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI2:TFF1_LATCH" title="IOI2:TFF1_LATCH">IOI2:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:OFF1_LATCH" title="IOI2:OFF1_LATCH">IOI2:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:TCEINV" title="~IOI2:TCEINV">~IOI2:TCEINV</a></td></tr>
+<tr><td>58</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI2:TFF2_LATCH" title="IOI2:TFF2_LATCH">IOI2:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:OFF2_LATCH" title="IOI2:OFF2_LATCH">IOI2:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:IDDRIN_MUX" title="IOI2:IDDRIN_MUX[2]">IOI2:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>59</td>
+<td><a href="#bits-xc3s-IOI.S3A.T-IOI2:TMUX" title="IOI2:TMUX[2]">IOI2:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3A.T-IOI2:OMUX" title="IOI2:OMUX[2]">IOI2:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:O2_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:O2_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O2_DDRMUX</th><th>[0, 0, 37]</th></tr>
+<tr><th>IOI1:O2_DDRMUX</th><th>[0, 0, 2]</th></tr>
+<tr><td>O2</td><td>0</td></tr>
+<tr><td>ODDRIN2</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:TFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_SRVAL</th><th>[0, 0, 3]</th></tr>
+<tr><th>IOI1:TFF1_SRVAL</th><th>[0, 0, 36]</th></tr>
+<tr><th>IOI2:TFF1_SRVAL</th><th>[0, 0, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:TFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_SRVAL</th><th>[0, 0, 5]</th></tr>
+<tr><th>IOI1:TFF2_SRVAL</th><th>[0, 0, 34]</th></tr>
+<tr><th>IOI2:TFF2_SRVAL</th><th>[0, 0, 45]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:TFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_INIT</th><th>[0, 0, 8]</th></tr>
+<tr><th>IOI1:TFF_INIT</th><th>[0, 0, 31]</th></tr>
+<tr><th>IOI2:TFF_INIT</th><th>[0, 0, 48]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:TFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_REV_EN</th><th>[0, 0, 9]</th></tr>
+<tr><th>IOI1:TFF_REV_EN</th><th>[0, 0, 30]</th></tr>
+<tr><th>IOI2:TFF_REV_EN</th><th>[0, 0, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:TFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SR_EN</th><th>[0, 0, 10]</th></tr>
+<tr><th>IOI1:TFF_SR_EN</th><th>[0, 0, 29]</th></tr>
+<tr><th>IOI2:TFF_SR_EN</th><th>[0, 0, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:O1INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:O2INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:T1INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:T2INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:O1INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:O2INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:T1INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:T2INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:O1INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:O2INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:T1INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:T2INV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1INV</th><th>[0, 1, 12]</th></tr>
+<tr><th>IOI0:O2INV</th><th>[0, 1, 11]</th></tr>
+<tr><th>IOI0:T1INV</th><th>[0, 0, 12]</th></tr>
+<tr><th>IOI0:T2INV</th><th>[0, 0, 11]</th></tr>
+<tr><th>IOI1:O1INV</th><th>[0, 1, 27]</th></tr>
+<tr><th>IOI1:O2INV</th><th>[0, 1, 28]</th></tr>
+<tr><th>IOI1:T1INV</th><th>[0, 0, 27]</th></tr>
+<tr><th>IOI1:T2INV</th><th>[0, 0, 28]</th></tr>
+<tr><th>IOI2:O1INV</th><th>[0, 1, 52]</th></tr>
+<tr><th>IOI2:O2INV</th><th>[0, 1, 51]</th></tr>
+<tr><th>IOI2:T1INV</th><th>[0, 0, 52]</th></tr>
+<tr><th>IOI2:T2INV</th><th>[0, 0, 51]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:TFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SYNC</th><th>[0, 0, 13]</th></tr>
+<tr><th>IOI1:TFF_SYNC</th><th>[0, 0, 26]</th></tr>
+<tr><th>IOI2:TFF_SYNC</th><th>[0, 0, 53]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:TMUX"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:TMUX"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:TMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TMUX</th><th>[0, 0, 15]</th><th>[0, 0, 19]</th><th>[0, 0, 14]</th><th>[0, 0, 16]</th></tr>
+<tr><th>IOI1:TMUX</th><th>[0, 0, 24]</th><th>[0, 0, 20]</th><th>[0, 0, 25]</th><th>[0, 0, 23]</th></tr>
+<tr><th>IOI2:TMUX</th><th>[0, 0, 55]</th><th>[0, 0, 59]</th><th>[0, 0, 54]</th><th>[0, 0, 56]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>T1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>T2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>TFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>TFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>TFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:TFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_LATCH</th><th>[0, 0, 17]</th></tr>
+<tr><th>IOI1:TFF1_LATCH</th><th>[0, 0, 22]</th></tr>
+<tr><th>IOI2:TFF1_LATCH</th><th>[0, 0, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:TFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_LATCH</th><th>[0, 0, 18]</th></tr>
+<tr><th>IOI1:TFF2_LATCH</th><th>[0, 0, 21]</th></tr>
+<tr><th>IOI2:TFF2_LATCH</th><th>[0, 0, 58]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:PCICE_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:PCICE_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:PCICE_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:PCICE_MUX</th><th>[0, 2, 0]</th><th>[0, 1, 0]</th></tr>
+<tr><th>IOI1:PCICE_MUX</th><th>[0, 2, 39]</th><th>[0, 1, 39]</th></tr>
+<tr><th>IOI2:PCICE_MUX</th><th>[0, 2, 40]</th><th>[0, 1, 40]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td></tr>
+<tr><td>OCE</td><td>0</td><td>1</td></tr>
+<tr><td>PCICE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:OFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_SRVAL</th><th>[0, 1, 3]</th></tr>
+<tr><th>IOI1:OFF1_SRVAL</th><th>[0, 1, 36]</th></tr>
+<tr><th>IOI2:OFF1_SRVAL</th><th>[0, 1, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:O1_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:O1_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1_DDRMUX</th><th>[0, 1, 35]</th></tr>
+<tr><th>IOI1:O1_DDRMUX</th><th>[0, 1, 4]</th></tr>
+<tr><td>O1</td><td>0</td></tr>
+<tr><td>ODDRIN1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:OFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_SRVAL</th><th>[0, 1, 5]</th></tr>
+<tr><th>IOI1:OFF2_SRVAL</th><th>[0, 1, 34]</th></tr>
+<tr><th>IOI2:OFF2_SRVAL</th><th>[0, 1, 45]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:OFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_INIT</th><th>[0, 1, 8]</th></tr>
+<tr><th>IOI1:OFF_INIT</th><th>[0, 1, 31]</th></tr>
+<tr><th>IOI2:OFF_INIT</th><th>[0, 1, 48]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:OFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_REV_EN</th><th>[0, 1, 9]</th></tr>
+<tr><th>IOI1:OFF_REV_EN</th><th>[0, 1, 30]</th></tr>
+<tr><th>IOI2:OFF_REV_EN</th><th>[0, 1, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:OFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SR_EN</th><th>[0, 1, 10]</th></tr>
+<tr><th>IOI1:OFF_SR_EN</th><th>[0, 1, 29]</th></tr>
+<tr><th>IOI2:OFF_SR_EN</th><th>[0, 1, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:OFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SYNC</th><th>[0, 1, 13]</th></tr>
+<tr><th>IOI1:OFF_SYNC</th><th>[0, 1, 26]</th></tr>
+<tr><th>IOI2:OFF_SYNC</th><th>[0, 1, 53]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:OMUX"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:OMUX"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:OMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OMUX</th><th>[0, 1, 15]</th><th>[0, 1, 19]</th><th>[0, 1, 14]</th><th>[0, 1, 16]</th></tr>
+<tr><th>IOI1:OMUX</th><th>[0, 1, 24]</th><th>[0, 1, 20]</th><th>[0, 1, 25]</th><th>[0, 1, 23]</th></tr>
+<tr><th>IOI2:OMUX</th><th>[0, 1, 55]</th><th>[0, 1, 59]</th><th>[0, 1, 54]</th><th>[0, 1, 56]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>O1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>O2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:OFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_LATCH</th><th>[0, 1, 17]</th></tr>
+<tr><th>IOI1:OFF1_LATCH</th><th>[0, 1, 22]</th></tr>
+<tr><th>IOI2:OFF1_LATCH</th><th>[0, 1, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:OFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_LATCH</th><th>[0, 1, 18]</th></tr>
+<tr><th>IOI1:OFF2_LATCH</th><th>[0, 1, 21]</th></tr>
+<tr><th>IOI2:OFF2_LATCH</th><th>[0, 1, 58]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:IFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_SRVAL</th><th>[0, 2, 3]</th></tr>
+<tr><th>IOI1:IFF1_SRVAL</th><th>[0, 2, 36]</th></tr>
+<tr><th>IOI2:IFF1_SRVAL</th><th>[0, 2, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:IFF1_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_INIT</th><th>[0, 2, 7]</th></tr>
+<tr><th>IOI1:IFF1_INIT</th><th>[0, 2, 32]</th></tr>
+<tr><th>IOI2:IFF1_INIT</th><th>[0, 2, 47]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:IFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SYNC</th><th>[0, 2, 8]</th></tr>
+<tr><th>IOI1:IFF_SYNC</th><th>[0, 2, 31]</th></tr>
+<tr><th>IOI2:IFF_SYNC</th><th>[0, 2, 48]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:IFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_REV_EN</th><th>[0, 2, 9]</th></tr>
+<tr><th>IOI1:IFF_REV_EN</th><th>[0, 2, 30]</th></tr>
+<tr><th>IOI2:IFF_REV_EN</th><th>[0, 2, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:IFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SR_EN</th><th>[0, 2, 10]</th></tr>
+<tr><th>IOI1:IFF_SR_EN</th><th>[0, 2, 29]</th></tr>
+<tr><th>IOI2:IFF_SR_EN</th><th>[0, 2, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:IFF_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_LATCH</th><th>[0, 2, 11]</th></tr>
+<tr><th>IOI1:IFF_LATCH</th><th>[0, 2, 28]</th></tr>
+<tr><th>IOI2:IFF_LATCH</th><th>[0, 2, 51]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:IFF2_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_INIT</th><th>[0, 2, 12]</th></tr>
+<tr><th>IOI1:IFF2_INIT</th><th>[0, 2, 27]</th></tr>
+<tr><th>IOI2:IFF2_INIT</th><th>[0, 2, 52]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:IFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_SRVAL</th><th>[0, 2, 16]</th></tr>
+<tr><th>IOI1:IFF2_SRVAL</th><th>[0, 2, 23]</th></tr>
+<tr><th>IOI2:IFF2_SRVAL</th><th>[0, 2, 56]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:IFF_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY_EN</th><th>[0, 3, 1]</th></tr>
+<tr><th>IOI1:IFF_DELAY_EN</th><th>[0, 3, 38]</th></tr>
+<tr><th>IOI2:IFF_DELAY_EN</th><th>[0, 3, 41]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:IFF_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_TSBYPASS_EN</th><th>[0, 3, 3]</th></tr>
+<tr><th>IOI1:IFF_TSBYPASS_EN</th><th>[0, 3, 36]</th></tr>
+<tr><th>IOI2:IFF_TSBYPASS_EN</th><th>[0, 3, 43]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:TSBYPASS_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TSBYPASS_MUX</th><th>[0, 3, 4]</th></tr>
+<tr><th>IOI1:TSBYPASS_MUX</th><th>[0, 3, 35]</th></tr>
+<tr><th>IOI2:TSBYPASS_MUX</th><th>[0, 3, 44]</th></tr>
+<tr><td>TMUX</td><td>0</td></tr>
+<tr><td>GND</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:I_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_TSBYPASS_EN</th><th>[0, 3, 7]</th></tr>
+<tr><th>IOI1:I_TSBYPASS_EN</th><th>[0, 3, 32]</th></tr>
+<tr><th>IOI2:I_TSBYPASS_EN</th><th>[0, 3, 47]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:IDDRIN_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:IDDRIN_MUX"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:IDDRIN_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IDDRIN_MUX</th><th>[0, 3, 21]</th><th>[0, 3, 37]</th><th>[0, 3, 8]</th></tr>
+<tr><th>IOI1:IDDRIN_MUX</th><th>[0, 3, 18]</th><th>[0, 3, 2]</th><th>[0, 3, 30]</th></tr>
+<tr><th>IOI2:IDDRIN_MUX</th><th>[0, 3, 58]</th><th>[0, 3, 42]</th><th>[0, 3, 48]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>IFFDMUX</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>IDDRIN1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>IDDRIN2</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:I_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY_EN</th><th>[0, 3, 10]</th></tr>
+<tr><th>IOI1:I_DELAY_EN</th><th>[0, 3, 29]</th></tr>
+<tr><th>IOI2:I_DELAY_EN</th><th>[0, 3, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:REVINV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI0:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:REVINV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI1:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:REVINV"></div>
+<div id="bits-xc3s-IOI.S3A.T-IOI2:TCEINV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:ICEINV</th><th>[0, 3, 14]</th></tr>
+<tr><th>IOI0:ICLK1INV</th><th>[0, 3, 13]</th></tr>
+<tr><th>IOI0:ICLK2INV</th><th>[0, 3, 12]</th></tr>
+<tr><th>IOI0:OTCLK1INV</th><th>[0, 3, 16]</th></tr>
+<tr><th>IOI0:OTCLK2INV</th><th>[0, 3, 15]</th></tr>
+<tr><th>IOI0:REVINV</th><th>[0, 3, 11]</th></tr>
+<tr><th>IOI0:TCEINV</th><th>[0, 3, 17]</th></tr>
+<tr><th>IOI1:ICEINV</th><th>[0, 3, 25]</th></tr>
+<tr><th>IOI1:ICLK1INV</th><th>[0, 3, 26]</th></tr>
+<tr><th>IOI1:ICLK2INV</th><th>[0, 3, 27]</th></tr>
+<tr><th>IOI1:OTCLK1INV</th><th>[0, 3, 23]</th></tr>
+<tr><th>IOI1:OTCLK2INV</th><th>[0, 3, 24]</th></tr>
+<tr><th>IOI1:REVINV</th><th>[0, 3, 28]</th></tr>
+<tr><th>IOI1:TCEINV</th><th>[0, 3, 22]</th></tr>
+<tr><th>IOI2:ICEINV</th><th>[0, 3, 54]</th></tr>
+<tr><th>IOI2:ICLK1INV</th><th>[0, 3, 53]</th></tr>
+<tr><th>IOI2:ICLK2INV</th><th>[0, 3, 52]</th></tr>
+<tr><th>IOI2:OTCLK1INV</th><th>[0, 3, 56]</th></tr>
+<tr><th>IOI2:OTCLK2INV</th><th>[0, 3, 55]</th></tr>
+<tr><th>IOI2:REVINV</th><th>[0, 3, 51]</th></tr>
+<tr><th>IOI2:TCEINV</th><th>[0, 3, 57]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+</section>
+<section id="ioi-s3adsp-l">
+<h3><code class="docutils literal notranslate"><span class="pre">IOI.S3ADSP.L</span></code><a class="headerlink" href="#ioi-s3adsp-l" title="Link to this heading"></a></h3>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[0]">IOI0:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[1]">IOI0:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:IFF_DELAY_EN" title="IOI0:IFF_DELAY_EN">IOI0:IFF_DELAY_EN</a></td></tr>
+<tr><td>2</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:O2_DDRMUX" title="IOI1:O2_DDRMUX">IOI1:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[1]">IOI1:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>3</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:TFF1_SRVAL" title="~IOI0:TFF1_SRVAL">~IOI0:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:OFF1_SRVAL" title="~IOI0:OFF1_SRVAL">~IOI0:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:IFF1_SRVAL" title="~IOI0:IFF1_SRVAL">~IOI0:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:IFF_TSBYPASS_EN" title="IOI0:IFF_TSBYPASS_EN">IOI0:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:O1_DDRMUX" title="IOI1:O1_DDRMUX">IOI1:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:TSBYPASS_MUX" title="IOI0:TSBYPASS_MUX">IOI0:TSBYPASS_MUX</a></td></tr>
+<tr><td>5</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:TFF2_SRVAL" title="~IOI0:TFF2_SRVAL">~IOI0:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:OFF2_SRVAL" title="~IOI0:OFF2_SRVAL">~IOI0:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:IFF1_INIT" title="~IOI0:IFF1_INIT">~IOI0:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:I_TSBYPASS_EN" title="IOI0:I_TSBYPASS_EN">IOI0:I_TSBYPASS_EN</a></td></tr>
+<tr><td>8</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:TFF_INIT" title="~IOI0:TFF_INIT">~IOI0:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:OFF_INIT" title="~IOI0:OFF_INIT">~IOI0:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:IFF_SYNC" title="IOI0:IFF_SYNC">IOI0:IFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[0]">IOI0:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>9</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:TFF_REV_EN" title="IOI0:TFF_REV_EN">IOI0:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:OFF_REV_EN" title="IOI0:OFF_REV_EN">IOI0:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:IFF_REV_EN" title="IOI0:IFF_REV_EN">IOI0:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>10</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:TFF_SR_EN" title="IOI0:TFF_SR_EN">IOI0:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:OFF_SR_EN" title="IOI0:OFF_SR_EN">IOI0:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:IFF_SR_EN" title="IOI0:IFF_SR_EN">IOI0:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:I_DELAY_EN" title="IOI0:I_DELAY_EN">IOI0:I_DELAY_EN</a></td></tr>
+<tr><td>11</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:T2INV" title="IOI0:T2INV">IOI0:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:O2INV" title="IOI0:O2INV">IOI0:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:IFF_LATCH" title="IOI0:IFF_LATCH">IOI0:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:REVINV" title="~IOI0:REVINV">~IOI0:REVINV</a></td></tr>
+<tr><td>12</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:T1INV" title="IOI0:T1INV">IOI0:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:O1INV" title="IOI0:O1INV">IOI0:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:IFF2_INIT" title="~IOI0:IFF2_INIT">~IOI0:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:ICLK2INV" title="~IOI0:ICLK2INV">~IOI0:ICLK2INV</a></td></tr>
+<tr><td>13</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:TFF_SYNC" title="IOI0:TFF_SYNC">IOI0:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:OFF_SYNC" title="IOI0:OFF_SYNC">IOI0:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:ICLK1INV" title="~IOI0:ICLK1INV">~IOI0:ICLK1INV</a></td></tr>
+<tr><td>14</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:TMUX" title="IOI0:TMUX[1]">IOI0:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:OMUX" title="IOI0:OMUX[1]">IOI0:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:ICEINV" title="~IOI0:ICEINV">~IOI0:ICEINV</a></td></tr>
+<tr><td>15</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:TMUX" title="IOI0:TMUX[3]">IOI0:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:OMUX" title="IOI0:OMUX[3]">IOI0:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:OTCLK2INV" title="~IOI0:OTCLK2INV">~IOI0:OTCLK2INV</a></td></tr>
+<tr><td>16</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:TMUX" title="IOI0:TMUX[0]">IOI0:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:OMUX" title="IOI0:OMUX[0]">IOI0:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:IFF2_SRVAL" title="~IOI0:IFF2_SRVAL">~IOI0:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:OTCLK1INV" title="~IOI0:OTCLK1INV">~IOI0:OTCLK1INV</a></td></tr>
+<tr><td>17</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:TFF1_LATCH" title="IOI0:TFF1_LATCH">IOI0:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:OFF1_LATCH" title="IOI0:OFF1_LATCH">IOI0:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:TCEINV" title="~IOI0:TCEINV">~IOI0:TCEINV</a></td></tr>
+<tr><td>18</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:TFF2_LATCH" title="IOI0:TFF2_LATCH">IOI0:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:OFF2_LATCH" title="IOI0:OFF2_LATCH">IOI0:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[2]">IOI1:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>19</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:TMUX" title="IOI0:TMUX[2]">IOI0:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:OMUX" title="IOI0:OMUX[2]">IOI0:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:TMUX" title="IOI1:TMUX[2]">IOI1:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:OMUX" title="IOI1:OMUX[2]">IOI1:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:TFF2_LATCH" title="IOI1:TFF2_LATCH">IOI1:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:OFF2_LATCH" title="IOI1:OFF2_LATCH">IOI1:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[2]">IOI0:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>22</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:TFF1_LATCH" title="IOI1:TFF1_LATCH">IOI1:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:OFF1_LATCH" title="IOI1:OFF1_LATCH">IOI1:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:TCEINV" title="~IOI1:TCEINV">~IOI1:TCEINV</a></td></tr>
+<tr><td>23</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:TMUX" title="IOI1:TMUX[0]">IOI1:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:OMUX" title="IOI1:OMUX[0]">IOI1:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:IFF2_SRVAL" title="~IOI1:IFF2_SRVAL">~IOI1:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:OTCLK1INV" title="~IOI1:OTCLK1INV">~IOI1:OTCLK1INV</a></td></tr>
+<tr><td>24</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:TMUX" title="IOI1:TMUX[3]">IOI1:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:OMUX" title="IOI1:OMUX[3]">IOI1:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:OTCLK2INV" title="~IOI1:OTCLK2INV">~IOI1:OTCLK2INV</a></td></tr>
+<tr><td>25</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:TMUX" title="IOI1:TMUX[1]">IOI1:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:OMUX" title="IOI1:OMUX[1]">IOI1:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:ICEINV" title="~IOI1:ICEINV">~IOI1:ICEINV</a></td></tr>
+<tr><td>26</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:TFF_SYNC" title="IOI1:TFF_SYNC">IOI1:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:OFF_SYNC" title="IOI1:OFF_SYNC">IOI1:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:ICLK1INV" title="~IOI1:ICLK1INV">~IOI1:ICLK1INV</a></td></tr>
+<tr><td>27</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:T1INV" title="IOI1:T1INV">IOI1:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:O1INV" title="IOI1:O1INV">IOI1:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:IFF2_INIT" title="~IOI1:IFF2_INIT">~IOI1:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:ICLK2INV" title="~IOI1:ICLK2INV">~IOI1:ICLK2INV</a></td></tr>
+<tr><td>28</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:T2INV" title="IOI1:T2INV">IOI1:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:O2INV" title="IOI1:O2INV">IOI1:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:IFF_LATCH" title="IOI1:IFF_LATCH">IOI1:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:REVINV" title="~IOI1:REVINV">~IOI1:REVINV</a></td></tr>
+<tr><td>29</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:TFF_SR_EN" title="IOI1:TFF_SR_EN">IOI1:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:OFF_SR_EN" title="IOI1:OFF_SR_EN">IOI1:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:IFF_SR_EN" title="IOI1:IFF_SR_EN">IOI1:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:I_DELAY_EN" title="IOI1:I_DELAY_EN">IOI1:I_DELAY_EN</a></td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:TFF_REV_EN" title="IOI1:TFF_REV_EN">IOI1:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:OFF_REV_EN" title="IOI1:OFF_REV_EN">IOI1:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:IFF_REV_EN" title="IOI1:IFF_REV_EN">IOI1:IFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[0]">IOI1:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>31</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:TFF_INIT" title="~IOI1:TFF_INIT">~IOI1:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:OFF_INIT" title="~IOI1:OFF_INIT">~IOI1:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:IFF_SYNC" title="IOI1:IFF_SYNC">IOI1:IFF_SYNC</a></td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:IFF1_INIT" title="~IOI1:IFF1_INIT">~IOI1:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:I_TSBYPASS_EN" title="IOI1:I_TSBYPASS_EN">IOI1:I_TSBYPASS_EN</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:TFF2_SRVAL" title="~IOI1:TFF2_SRVAL">~IOI1:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:OFF2_SRVAL" title="~IOI1:OFF2_SRVAL">~IOI1:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:O1_DDRMUX" title="IOI0:O1_DDRMUX">IOI0:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:TSBYPASS_MUX" title="IOI1:TSBYPASS_MUX">IOI1:TSBYPASS_MUX</a></td></tr>
+<tr><td>36</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:TFF1_SRVAL" title="~IOI1:TFF1_SRVAL">~IOI1:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:OFF1_SRVAL" title="~IOI1:OFF1_SRVAL">~IOI1:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:IFF1_SRVAL" title="~IOI1:IFF1_SRVAL">~IOI1:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:IFF_TSBYPASS_EN" title="IOI1:IFF_TSBYPASS_EN">IOI1:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>37</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:O2_DDRMUX" title="IOI0:O2_DDRMUX">IOI0:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[1]">IOI0:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:IFF_DELAY_EN" title="IOI1:IFF_DELAY_EN">IOI1:IFF_DELAY_EN</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[0]">IOI1:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[1]">IOI1:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:DELAY_COMMON" title="~IOI0:DELAY_COMMON">~IOI0:DELAY_COMMON</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:DELAY_COMMON" title="~IOI1:DELAY_COMMON">~IOI1:DELAY_COMMON</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:IFF_DELAY" title="~IOI1:IFF_DELAY[0]">~IOI1:IFF_DELAY[0]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:DELAY_VARIABLE" title="IOI0:DELAY_VARIABLE">IOI0:DELAY_VARIABLE</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:I_DELAY" title="~IOI0:I_DELAY[1]">~IOI0:I_DELAY[1]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:I_DELAY" title="~IOI0:I_DELAY[2]">~IOI0:I_DELAY[2]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:IFF_DELAY" title="~IOI0:IFF_DELAY[0]">~IOI0:IFF_DELAY[0]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:I_DELAY" title="~IOI0:I_DELAY[0]">~IOI0:I_DELAY[0]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI0:IFF_DELAY" title="~IOI0:IFF_DELAY[1]">~IOI0:IFF_DELAY[1]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:I_DELAY" title="~IOI1:I_DELAY[0]">~IOI1:I_DELAY[0]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:I_DELAY" title="~IOI1:I_DELAY[1]">~IOI1:I_DELAY[1]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:I_DELAY" title="~IOI1:I_DELAY[2]">~IOI1:I_DELAY[2]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:DELAY_VARIABLE" title="IOI1:DELAY_VARIABLE">IOI1:DELAY_VARIABLE</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.L-IOI1:IFF_DELAY" title="~IOI1:IFF_DELAY[1]">~IOI1:IFF_DELAY[1]</a></td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:O2_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:O2_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O2_DDRMUX</th><th>[0, 0, 37]</th></tr>
+<tr><th>IOI1:O2_DDRMUX</th><th>[0, 0, 2]</th></tr>
+<tr><td>O2</td><td>0</td></tr>
+<tr><td>ODDRIN2</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:TFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_SRVAL</th><th>[0, 0, 3]</th></tr>
+<tr><th>IOI1:TFF1_SRVAL</th><th>[0, 0, 36]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:TFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_SRVAL</th><th>[0, 0, 5]</th></tr>
+<tr><th>IOI1:TFF2_SRVAL</th><th>[0, 0, 34]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:TFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_INIT</th><th>[0, 0, 8]</th></tr>
+<tr><th>IOI1:TFF_INIT</th><th>[0, 0, 31]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:TFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_REV_EN</th><th>[0, 0, 9]</th></tr>
+<tr><th>IOI1:TFF_REV_EN</th><th>[0, 0, 30]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:TFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SR_EN</th><th>[0, 0, 10]</th></tr>
+<tr><th>IOI1:TFF_SR_EN</th><th>[0, 0, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:O1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:O2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:T1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:T2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:O1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:O2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:T1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:T2INV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1INV</th><th>[0, 1, 12]</th></tr>
+<tr><th>IOI0:O2INV</th><th>[0, 1, 11]</th></tr>
+<tr><th>IOI0:T1INV</th><th>[0, 0, 12]</th></tr>
+<tr><th>IOI0:T2INV</th><th>[0, 0, 11]</th></tr>
+<tr><th>IOI1:O1INV</th><th>[0, 1, 27]</th></tr>
+<tr><th>IOI1:O2INV</th><th>[0, 1, 28]</th></tr>
+<tr><th>IOI1:T1INV</th><th>[0, 0, 27]</th></tr>
+<tr><th>IOI1:T2INV</th><th>[0, 0, 28]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:TFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SYNC</th><th>[0, 0, 13]</th></tr>
+<tr><th>IOI1:TFF_SYNC</th><th>[0, 0, 26]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:TMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:TMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TMUX</th><th>[0, 0, 15]</th><th>[0, 0, 19]</th><th>[0, 0, 14]</th><th>[0, 0, 16]</th></tr>
+<tr><th>IOI1:TMUX</th><th>[0, 0, 24]</th><th>[0, 0, 20]</th><th>[0, 0, 25]</th><th>[0, 0, 23]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>T1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>T2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>TFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>TFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>TFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:TFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_LATCH</th><th>[0, 0, 17]</th></tr>
+<tr><th>IOI1:TFF1_LATCH</th><th>[0, 0, 22]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:TFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_LATCH</th><th>[0, 0, 18]</th></tr>
+<tr><th>IOI1:TFF2_LATCH</th><th>[0, 0, 21]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:PCICE_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:PCICE_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:PCICE_MUX</th><th>[0, 2, 0]</th><th>[0, 1, 0]</th></tr>
+<tr><th>IOI1:PCICE_MUX</th><th>[0, 2, 39]</th><th>[0, 1, 39]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td></tr>
+<tr><td>OCE</td><td>0</td><td>1</td></tr>
+<tr><td>PCICE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:OFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_SRVAL</th><th>[0, 1, 3]</th></tr>
+<tr><th>IOI1:OFF1_SRVAL</th><th>[0, 1, 36]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:O1_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:O1_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1_DDRMUX</th><th>[0, 1, 35]</th></tr>
+<tr><th>IOI1:O1_DDRMUX</th><th>[0, 1, 4]</th></tr>
+<tr><td>O1</td><td>0</td></tr>
+<tr><td>ODDRIN1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:OFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_SRVAL</th><th>[0, 1, 5]</th></tr>
+<tr><th>IOI1:OFF2_SRVAL</th><th>[0, 1, 34]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:OFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_INIT</th><th>[0, 1, 8]</th></tr>
+<tr><th>IOI1:OFF_INIT</th><th>[0, 1, 31]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:OFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_REV_EN</th><th>[0, 1, 9]</th></tr>
+<tr><th>IOI1:OFF_REV_EN</th><th>[0, 1, 30]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:OFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SR_EN</th><th>[0, 1, 10]</th></tr>
+<tr><th>IOI1:OFF_SR_EN</th><th>[0, 1, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:OFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SYNC</th><th>[0, 1, 13]</th></tr>
+<tr><th>IOI1:OFF_SYNC</th><th>[0, 1, 26]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:OMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:OMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OMUX</th><th>[0, 1, 15]</th><th>[0, 1, 19]</th><th>[0, 1, 14]</th><th>[0, 1, 16]</th></tr>
+<tr><th>IOI1:OMUX</th><th>[0, 1, 24]</th><th>[0, 1, 20]</th><th>[0, 1, 25]</th><th>[0, 1, 23]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>O1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>O2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:OFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_LATCH</th><th>[0, 1, 17]</th></tr>
+<tr><th>IOI1:OFF1_LATCH</th><th>[0, 1, 22]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:OFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_LATCH</th><th>[0, 1, 18]</th></tr>
+<tr><th>IOI1:OFF2_LATCH</th><th>[0, 1, 21]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:IFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_SRVAL</th><th>[0, 2, 3]</th></tr>
+<tr><th>IOI1:IFF1_SRVAL</th><th>[0, 2, 36]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:IFF1_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_INIT</th><th>[0, 2, 7]</th></tr>
+<tr><th>IOI1:IFF1_INIT</th><th>[0, 2, 32]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:IFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SYNC</th><th>[0, 2, 8]</th></tr>
+<tr><th>IOI1:IFF_SYNC</th><th>[0, 2, 31]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:IFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_REV_EN</th><th>[0, 2, 9]</th></tr>
+<tr><th>IOI1:IFF_REV_EN</th><th>[0, 2, 30]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:IFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SR_EN</th><th>[0, 2, 10]</th></tr>
+<tr><th>IOI1:IFF_SR_EN</th><th>[0, 2, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:IFF_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_LATCH</th><th>[0, 2, 11]</th></tr>
+<tr><th>IOI1:IFF_LATCH</th><th>[0, 2, 28]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:IFF2_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_INIT</th><th>[0, 2, 12]</th></tr>
+<tr><th>IOI1:IFF2_INIT</th><th>[0, 2, 27]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:IFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_SRVAL</th><th>[0, 2, 16]</th></tr>
+<tr><th>IOI1:IFF2_SRVAL</th><th>[0, 2, 23]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:IFF_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY_EN</th><th>[0, 3, 1]</th></tr>
+<tr><th>IOI1:IFF_DELAY_EN</th><th>[0, 3, 38]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:IFF_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_TSBYPASS_EN</th><th>[0, 3, 3]</th></tr>
+<tr><th>IOI1:IFF_TSBYPASS_EN</th><th>[0, 3, 36]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:TSBYPASS_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TSBYPASS_MUX</th><th>[0, 3, 4]</th></tr>
+<tr><th>IOI1:TSBYPASS_MUX</th><th>[0, 3, 35]</th></tr>
+<tr><td>TMUX</td><td>0</td></tr>
+<tr><td>GND</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:I_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_TSBYPASS_EN</th><th>[0, 3, 7]</th></tr>
+<tr><th>IOI1:I_TSBYPASS_EN</th><th>[0, 3, 32]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:IDDRIN_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:IDDRIN_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IDDRIN_MUX</th><th>[0, 3, 21]</th><th>[0, 3, 37]</th><th>[0, 3, 8]</th></tr>
+<tr><th>IOI1:IDDRIN_MUX</th><th>[0, 3, 18]</th><th>[0, 3, 2]</th><th>[0, 3, 30]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>IFFDMUX</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>IDDRIN1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>IDDRIN2</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:I_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY_EN</th><th>[0, 3, 10]</th></tr>
+<tr><th>IOI1:I_DELAY_EN</th><th>[0, 3, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:REVINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:REVINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:TCEINV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:ICEINV</th><th>[0, 3, 14]</th></tr>
+<tr><th>IOI0:ICLK1INV</th><th>[0, 3, 13]</th></tr>
+<tr><th>IOI0:ICLK2INV</th><th>[0, 3, 12]</th></tr>
+<tr><th>IOI0:OTCLK1INV</th><th>[0, 3, 16]</th></tr>
+<tr><th>IOI0:OTCLK2INV</th><th>[0, 3, 15]</th></tr>
+<tr><th>IOI0:REVINV</th><th>[0, 3, 11]</th></tr>
+<tr><th>IOI0:TCEINV</th><th>[0, 3, 17]</th></tr>
+<tr><th>IOI1:ICEINV</th><th>[0, 3, 25]</th></tr>
+<tr><th>IOI1:ICLK1INV</th><th>[0, 3, 26]</th></tr>
+<tr><th>IOI1:ICLK2INV</th><th>[0, 3, 27]</th></tr>
+<tr><th>IOI1:OTCLK1INV</th><th>[0, 3, 23]</th></tr>
+<tr><th>IOI1:OTCLK2INV</th><th>[0, 3, 24]</th></tr>
+<tr><th>IOI1:REVINV</th><th>[0, 3, 28]</th></tr>
+<tr><th>IOI1:TCEINV</th><th>[0, 3, 22]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:DELAY_COMMON"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:DELAY_COMMON"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:DELAY_COMMON</th><th>[0, 3, 41]</th></tr>
+<tr><th>IOI1:DELAY_COMMON</th><th>[0, 3, 42]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:IFF_DELAY"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:IFF_DELAY"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY</th><th>[0, 3, 53]</th><th>[0, 3, 51]</th></tr>
+<tr><th>IOI1:IFF_DELAY</th><th>[0, 3, 58]</th><th>[0, 3, 47]</th></tr>
+<tr><td>Inverted</td><td>~[1]</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:DELAY_VARIABLE"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:DELAY_VARIABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:DELAY_VARIABLE</th><th>[0, 3, 48]</th></tr>
+<tr><th>IOI1:DELAY_VARIABLE</th><th>[0, 3, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI0:I_DELAY"></div>
+<div id="bits-xc3s-IOI.S3ADSP.L-IOI1:I_DELAY"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY</th><th>[0, 3, 50]</th><th>[0, 3, 49]</th><th>[0, 3, 52]</th></tr>
+<tr><th>IOI1:I_DELAY</th><th>[0, 3, 56]</th><th>[0, 3, 55]</th><th>[0, 3, 54]</th></tr>
+<tr><td>Inverted</td><td>~[2]</td><td>~[1]</td><td>~[0]</td></tr>
+</table>
+</section>
+<section id="ioi-s3adsp-r">
+<h3><code class="docutils literal notranslate"><span class="pre">IOI.S3ADSP.R</span></code><a class="headerlink" href="#ioi-s3adsp-r" title="Link to this heading"></a></h3>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[0]">IOI0:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[1]">IOI0:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:IFF_DELAY_EN" title="IOI0:IFF_DELAY_EN">IOI0:IFF_DELAY_EN</a></td></tr>
+<tr><td>2</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:O2_DDRMUX" title="IOI1:O2_DDRMUX">IOI1:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[1]">IOI1:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>3</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:TFF1_SRVAL" title="~IOI0:TFF1_SRVAL">~IOI0:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:OFF1_SRVAL" title="~IOI0:OFF1_SRVAL">~IOI0:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:IFF1_SRVAL" title="~IOI0:IFF1_SRVAL">~IOI0:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:IFF_TSBYPASS_EN" title="IOI0:IFF_TSBYPASS_EN">IOI0:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:O1_DDRMUX" title="IOI1:O1_DDRMUX">IOI1:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:TSBYPASS_MUX" title="IOI0:TSBYPASS_MUX">IOI0:TSBYPASS_MUX</a></td></tr>
+<tr><td>5</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:TFF2_SRVAL" title="~IOI0:TFF2_SRVAL">~IOI0:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:OFF2_SRVAL" title="~IOI0:OFF2_SRVAL">~IOI0:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:IFF1_INIT" title="~IOI0:IFF1_INIT">~IOI0:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:I_TSBYPASS_EN" title="IOI0:I_TSBYPASS_EN">IOI0:I_TSBYPASS_EN</a></td></tr>
+<tr><td>8</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:TFF_INIT" title="~IOI0:TFF_INIT">~IOI0:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:OFF_INIT" title="~IOI0:OFF_INIT">~IOI0:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:IFF_SYNC" title="IOI0:IFF_SYNC">IOI0:IFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[0]">IOI0:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>9</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:TFF_REV_EN" title="IOI0:TFF_REV_EN">IOI0:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:OFF_REV_EN" title="IOI0:OFF_REV_EN">IOI0:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:IFF_REV_EN" title="IOI0:IFF_REV_EN">IOI0:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>10</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:TFF_SR_EN" title="IOI0:TFF_SR_EN">IOI0:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:OFF_SR_EN" title="IOI0:OFF_SR_EN">IOI0:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:IFF_SR_EN" title="IOI0:IFF_SR_EN">IOI0:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:I_DELAY_EN" title="IOI0:I_DELAY_EN">IOI0:I_DELAY_EN</a></td></tr>
+<tr><td>11</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:T2INV" title="IOI0:T2INV">IOI0:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:O2INV" title="IOI0:O2INV">IOI0:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:IFF_LATCH" title="IOI0:IFF_LATCH">IOI0:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:REVINV" title="~IOI0:REVINV">~IOI0:REVINV</a></td></tr>
+<tr><td>12</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:T1INV" title="IOI0:T1INV">IOI0:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:O1INV" title="IOI0:O1INV">IOI0:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:IFF2_INIT" title="~IOI0:IFF2_INIT">~IOI0:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:ICLK2INV" title="~IOI0:ICLK2INV">~IOI0:ICLK2INV</a></td></tr>
+<tr><td>13</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:TFF_SYNC" title="IOI0:TFF_SYNC">IOI0:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:OFF_SYNC" title="IOI0:OFF_SYNC">IOI0:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:ICLK1INV" title="~IOI0:ICLK1INV">~IOI0:ICLK1INV</a></td></tr>
+<tr><td>14</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:TMUX" title="IOI0:TMUX[1]">IOI0:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:OMUX" title="IOI0:OMUX[1]">IOI0:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:ICEINV" title="~IOI0:ICEINV">~IOI0:ICEINV</a></td></tr>
+<tr><td>15</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:TMUX" title="IOI0:TMUX[3]">IOI0:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:OMUX" title="IOI0:OMUX[3]">IOI0:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:OTCLK2INV" title="~IOI0:OTCLK2INV">~IOI0:OTCLK2INV</a></td></tr>
+<tr><td>16</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:TMUX" title="IOI0:TMUX[0]">IOI0:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:OMUX" title="IOI0:OMUX[0]">IOI0:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:IFF2_SRVAL" title="~IOI0:IFF2_SRVAL">~IOI0:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:OTCLK1INV" title="~IOI0:OTCLK1INV">~IOI0:OTCLK1INV</a></td></tr>
+<tr><td>17</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:TFF1_LATCH" title="IOI0:TFF1_LATCH">IOI0:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:OFF1_LATCH" title="IOI0:OFF1_LATCH">IOI0:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:TCEINV" title="~IOI0:TCEINV">~IOI0:TCEINV</a></td></tr>
+<tr><td>18</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:TFF2_LATCH" title="IOI0:TFF2_LATCH">IOI0:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:OFF2_LATCH" title="IOI0:OFF2_LATCH">IOI0:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[2]">IOI1:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>19</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:TMUX" title="IOI0:TMUX[2]">IOI0:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:OMUX" title="IOI0:OMUX[2]">IOI0:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:TMUX" title="IOI1:TMUX[2]">IOI1:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:OMUX" title="IOI1:OMUX[2]">IOI1:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:TFF2_LATCH" title="IOI1:TFF2_LATCH">IOI1:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:OFF2_LATCH" title="IOI1:OFF2_LATCH">IOI1:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[2]">IOI0:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>22</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:TFF1_LATCH" title="IOI1:TFF1_LATCH">IOI1:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:OFF1_LATCH" title="IOI1:OFF1_LATCH">IOI1:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:TCEINV" title="~IOI1:TCEINV">~IOI1:TCEINV</a></td></tr>
+<tr><td>23</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:TMUX" title="IOI1:TMUX[0]">IOI1:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:OMUX" title="IOI1:OMUX[0]">IOI1:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:IFF2_SRVAL" title="~IOI1:IFF2_SRVAL">~IOI1:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:OTCLK1INV" title="~IOI1:OTCLK1INV">~IOI1:OTCLK1INV</a></td></tr>
+<tr><td>24</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:TMUX" title="IOI1:TMUX[3]">IOI1:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:OMUX" title="IOI1:OMUX[3]">IOI1:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:OTCLK2INV" title="~IOI1:OTCLK2INV">~IOI1:OTCLK2INV</a></td></tr>
+<tr><td>25</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:TMUX" title="IOI1:TMUX[1]">IOI1:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:OMUX" title="IOI1:OMUX[1]">IOI1:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:ICEINV" title="~IOI1:ICEINV">~IOI1:ICEINV</a></td></tr>
+<tr><td>26</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:TFF_SYNC" title="IOI1:TFF_SYNC">IOI1:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:OFF_SYNC" title="IOI1:OFF_SYNC">IOI1:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:ICLK1INV" title="~IOI1:ICLK1INV">~IOI1:ICLK1INV</a></td></tr>
+<tr><td>27</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:T1INV" title="IOI1:T1INV">IOI1:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:O1INV" title="IOI1:O1INV">IOI1:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:IFF2_INIT" title="~IOI1:IFF2_INIT">~IOI1:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:ICLK2INV" title="~IOI1:ICLK2INV">~IOI1:ICLK2INV</a></td></tr>
+<tr><td>28</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:T2INV" title="IOI1:T2INV">IOI1:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:O2INV" title="IOI1:O2INV">IOI1:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:IFF_LATCH" title="IOI1:IFF_LATCH">IOI1:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:REVINV" title="~IOI1:REVINV">~IOI1:REVINV</a></td></tr>
+<tr><td>29</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:TFF_SR_EN" title="IOI1:TFF_SR_EN">IOI1:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:OFF_SR_EN" title="IOI1:OFF_SR_EN">IOI1:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:IFF_SR_EN" title="IOI1:IFF_SR_EN">IOI1:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:I_DELAY_EN" title="IOI1:I_DELAY_EN">IOI1:I_DELAY_EN</a></td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:TFF_REV_EN" title="IOI1:TFF_REV_EN">IOI1:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:OFF_REV_EN" title="IOI1:OFF_REV_EN">IOI1:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:IFF_REV_EN" title="IOI1:IFF_REV_EN">IOI1:IFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[0]">IOI1:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>31</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:TFF_INIT" title="~IOI1:TFF_INIT">~IOI1:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:OFF_INIT" title="~IOI1:OFF_INIT">~IOI1:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:IFF_SYNC" title="IOI1:IFF_SYNC">IOI1:IFF_SYNC</a></td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:IFF1_INIT" title="~IOI1:IFF1_INIT">~IOI1:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:I_TSBYPASS_EN" title="IOI1:I_TSBYPASS_EN">IOI1:I_TSBYPASS_EN</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:TFF2_SRVAL" title="~IOI1:TFF2_SRVAL">~IOI1:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:OFF2_SRVAL" title="~IOI1:OFF2_SRVAL">~IOI1:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:O1_DDRMUX" title="IOI0:O1_DDRMUX">IOI0:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:TSBYPASS_MUX" title="IOI1:TSBYPASS_MUX">IOI1:TSBYPASS_MUX</a></td></tr>
+<tr><td>36</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:TFF1_SRVAL" title="~IOI1:TFF1_SRVAL">~IOI1:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:OFF1_SRVAL" title="~IOI1:OFF1_SRVAL">~IOI1:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:IFF1_SRVAL" title="~IOI1:IFF1_SRVAL">~IOI1:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:IFF_TSBYPASS_EN" title="IOI1:IFF_TSBYPASS_EN">IOI1:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>37</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:O2_DDRMUX" title="IOI0:O2_DDRMUX">IOI0:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[1]">IOI0:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:IFF_DELAY_EN" title="IOI1:IFF_DELAY_EN">IOI1:IFF_DELAY_EN</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[0]">IOI1:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[1]">IOI1:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:DELAY_COMMON" title="~IOI0:DELAY_COMMON">~IOI0:DELAY_COMMON</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:DELAY_COMMON" title="~IOI1:DELAY_COMMON">~IOI1:DELAY_COMMON</a></td></tr>
+<tr><td>43</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>45</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:IFF_DELAY" title="~IOI1:IFF_DELAY[0]">~IOI1:IFF_DELAY[0]</a></td></tr>
+<tr><td>48</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:DELAY_VARIABLE" title="IOI0:DELAY_VARIABLE">IOI0:DELAY_VARIABLE</a></td></tr>
+<tr><td>49</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:I_DELAY" title="~IOI0:I_DELAY[1]">~IOI0:I_DELAY[1]</a></td></tr>
+<tr><td>50</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:I_DELAY" title="~IOI0:I_DELAY[2]">~IOI0:I_DELAY[2]</a></td></tr>
+<tr><td>51</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:IFF_DELAY" title="~IOI0:IFF_DELAY[0]">~IOI0:IFF_DELAY[0]</a></td></tr>
+<tr><td>52</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:I_DELAY" title="~IOI0:I_DELAY[0]">~IOI0:I_DELAY[0]</a></td></tr>
+<tr><td>53</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI0:IFF_DELAY" title="~IOI0:IFF_DELAY[1]">~IOI0:IFF_DELAY[1]</a></td></tr>
+<tr><td>54</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:I_DELAY" title="~IOI1:I_DELAY[0]">~IOI1:I_DELAY[0]</a></td></tr>
+<tr><td>55</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:I_DELAY" title="~IOI1:I_DELAY[1]">~IOI1:I_DELAY[1]</a></td></tr>
+<tr><td>56</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:I_DELAY" title="~IOI1:I_DELAY[2]">~IOI1:I_DELAY[2]</a></td></tr>
+<tr><td>57</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:DELAY_VARIABLE" title="IOI1:DELAY_VARIABLE">IOI1:DELAY_VARIABLE</a></td></tr>
+<tr><td>58</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.R-IOI1:IFF_DELAY" title="~IOI1:IFF_DELAY[1]">~IOI1:IFF_DELAY[1]</a></td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:O2_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:O2_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O2_DDRMUX</th><th>[0, 0, 37]</th></tr>
+<tr><th>IOI1:O2_DDRMUX</th><th>[0, 0, 2]</th></tr>
+<tr><td>O2</td><td>0</td></tr>
+<tr><td>ODDRIN2</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:TFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_SRVAL</th><th>[0, 0, 3]</th></tr>
+<tr><th>IOI1:TFF1_SRVAL</th><th>[0, 0, 36]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:TFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_SRVAL</th><th>[0, 0, 5]</th></tr>
+<tr><th>IOI1:TFF2_SRVAL</th><th>[0, 0, 34]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:TFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_INIT</th><th>[0, 0, 8]</th></tr>
+<tr><th>IOI1:TFF_INIT</th><th>[0, 0, 31]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:TFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_REV_EN</th><th>[0, 0, 9]</th></tr>
+<tr><th>IOI1:TFF_REV_EN</th><th>[0, 0, 30]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:TFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SR_EN</th><th>[0, 0, 10]</th></tr>
+<tr><th>IOI1:TFF_SR_EN</th><th>[0, 0, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:O1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:O2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:T1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:T2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:O1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:O2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:T1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:T2INV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1INV</th><th>[0, 1, 12]</th></tr>
+<tr><th>IOI0:O2INV</th><th>[0, 1, 11]</th></tr>
+<tr><th>IOI0:T1INV</th><th>[0, 0, 12]</th></tr>
+<tr><th>IOI0:T2INV</th><th>[0, 0, 11]</th></tr>
+<tr><th>IOI1:O1INV</th><th>[0, 1, 27]</th></tr>
+<tr><th>IOI1:O2INV</th><th>[0, 1, 28]</th></tr>
+<tr><th>IOI1:T1INV</th><th>[0, 0, 27]</th></tr>
+<tr><th>IOI1:T2INV</th><th>[0, 0, 28]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:TFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SYNC</th><th>[0, 0, 13]</th></tr>
+<tr><th>IOI1:TFF_SYNC</th><th>[0, 0, 26]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:TMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:TMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TMUX</th><th>[0, 0, 15]</th><th>[0, 0, 19]</th><th>[0, 0, 14]</th><th>[0, 0, 16]</th></tr>
+<tr><th>IOI1:TMUX</th><th>[0, 0, 24]</th><th>[0, 0, 20]</th><th>[0, 0, 25]</th><th>[0, 0, 23]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>T1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>T2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>TFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>TFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>TFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:TFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_LATCH</th><th>[0, 0, 17]</th></tr>
+<tr><th>IOI1:TFF1_LATCH</th><th>[0, 0, 22]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:TFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_LATCH</th><th>[0, 0, 18]</th></tr>
+<tr><th>IOI1:TFF2_LATCH</th><th>[0, 0, 21]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:PCICE_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:PCICE_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:PCICE_MUX</th><th>[0, 2, 0]</th><th>[0, 1, 0]</th></tr>
+<tr><th>IOI1:PCICE_MUX</th><th>[0, 2, 39]</th><th>[0, 1, 39]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td></tr>
+<tr><td>OCE</td><td>0</td><td>1</td></tr>
+<tr><td>PCICE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:OFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_SRVAL</th><th>[0, 1, 3]</th></tr>
+<tr><th>IOI1:OFF1_SRVAL</th><th>[0, 1, 36]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:O1_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:O1_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1_DDRMUX</th><th>[0, 1, 35]</th></tr>
+<tr><th>IOI1:O1_DDRMUX</th><th>[0, 1, 4]</th></tr>
+<tr><td>O1</td><td>0</td></tr>
+<tr><td>ODDRIN1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:OFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_SRVAL</th><th>[0, 1, 5]</th></tr>
+<tr><th>IOI1:OFF2_SRVAL</th><th>[0, 1, 34]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:OFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_INIT</th><th>[0, 1, 8]</th></tr>
+<tr><th>IOI1:OFF_INIT</th><th>[0, 1, 31]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:OFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_REV_EN</th><th>[0, 1, 9]</th></tr>
+<tr><th>IOI1:OFF_REV_EN</th><th>[0, 1, 30]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:OFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SR_EN</th><th>[0, 1, 10]</th></tr>
+<tr><th>IOI1:OFF_SR_EN</th><th>[0, 1, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:OFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SYNC</th><th>[0, 1, 13]</th></tr>
+<tr><th>IOI1:OFF_SYNC</th><th>[0, 1, 26]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:OMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:OMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OMUX</th><th>[0, 1, 15]</th><th>[0, 1, 19]</th><th>[0, 1, 14]</th><th>[0, 1, 16]</th></tr>
+<tr><th>IOI1:OMUX</th><th>[0, 1, 24]</th><th>[0, 1, 20]</th><th>[0, 1, 25]</th><th>[0, 1, 23]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>O1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>O2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:OFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_LATCH</th><th>[0, 1, 17]</th></tr>
+<tr><th>IOI1:OFF1_LATCH</th><th>[0, 1, 22]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:OFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_LATCH</th><th>[0, 1, 18]</th></tr>
+<tr><th>IOI1:OFF2_LATCH</th><th>[0, 1, 21]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:IFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_SRVAL</th><th>[0, 2, 3]</th></tr>
+<tr><th>IOI1:IFF1_SRVAL</th><th>[0, 2, 36]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:IFF1_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_INIT</th><th>[0, 2, 7]</th></tr>
+<tr><th>IOI1:IFF1_INIT</th><th>[0, 2, 32]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:IFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SYNC</th><th>[0, 2, 8]</th></tr>
+<tr><th>IOI1:IFF_SYNC</th><th>[0, 2, 31]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:IFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_REV_EN</th><th>[0, 2, 9]</th></tr>
+<tr><th>IOI1:IFF_REV_EN</th><th>[0, 2, 30]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:IFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SR_EN</th><th>[0, 2, 10]</th></tr>
+<tr><th>IOI1:IFF_SR_EN</th><th>[0, 2, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:IFF_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_LATCH</th><th>[0, 2, 11]</th></tr>
+<tr><th>IOI1:IFF_LATCH</th><th>[0, 2, 28]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:IFF2_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_INIT</th><th>[0, 2, 12]</th></tr>
+<tr><th>IOI1:IFF2_INIT</th><th>[0, 2, 27]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:IFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_SRVAL</th><th>[0, 2, 16]</th></tr>
+<tr><th>IOI1:IFF2_SRVAL</th><th>[0, 2, 23]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:IFF_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY_EN</th><th>[0, 3, 1]</th></tr>
+<tr><th>IOI1:IFF_DELAY_EN</th><th>[0, 3, 38]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:IFF_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_TSBYPASS_EN</th><th>[0, 3, 3]</th></tr>
+<tr><th>IOI1:IFF_TSBYPASS_EN</th><th>[0, 3, 36]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:TSBYPASS_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TSBYPASS_MUX</th><th>[0, 3, 4]</th></tr>
+<tr><th>IOI1:TSBYPASS_MUX</th><th>[0, 3, 35]</th></tr>
+<tr><td>TMUX</td><td>0</td></tr>
+<tr><td>GND</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:I_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_TSBYPASS_EN</th><th>[0, 3, 7]</th></tr>
+<tr><th>IOI1:I_TSBYPASS_EN</th><th>[0, 3, 32]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:IDDRIN_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:IDDRIN_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IDDRIN_MUX</th><th>[0, 3, 21]</th><th>[0, 3, 37]</th><th>[0, 3, 8]</th></tr>
+<tr><th>IOI1:IDDRIN_MUX</th><th>[0, 3, 18]</th><th>[0, 3, 2]</th><th>[0, 3, 30]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>IFFDMUX</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>IDDRIN1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>IDDRIN2</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:I_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY_EN</th><th>[0, 3, 10]</th></tr>
+<tr><th>IOI1:I_DELAY_EN</th><th>[0, 3, 29]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:REVINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:REVINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:TCEINV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:ICEINV</th><th>[0, 3, 14]</th></tr>
+<tr><th>IOI0:ICLK1INV</th><th>[0, 3, 13]</th></tr>
+<tr><th>IOI0:ICLK2INV</th><th>[0, 3, 12]</th></tr>
+<tr><th>IOI0:OTCLK1INV</th><th>[0, 3, 16]</th></tr>
+<tr><th>IOI0:OTCLK2INV</th><th>[0, 3, 15]</th></tr>
+<tr><th>IOI0:REVINV</th><th>[0, 3, 11]</th></tr>
+<tr><th>IOI0:TCEINV</th><th>[0, 3, 17]</th></tr>
+<tr><th>IOI1:ICEINV</th><th>[0, 3, 25]</th></tr>
+<tr><th>IOI1:ICLK1INV</th><th>[0, 3, 26]</th></tr>
+<tr><th>IOI1:ICLK2INV</th><th>[0, 3, 27]</th></tr>
+<tr><th>IOI1:OTCLK1INV</th><th>[0, 3, 23]</th></tr>
+<tr><th>IOI1:OTCLK2INV</th><th>[0, 3, 24]</th></tr>
+<tr><th>IOI1:REVINV</th><th>[0, 3, 28]</th></tr>
+<tr><th>IOI1:TCEINV</th><th>[0, 3, 22]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:DELAY_COMMON"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:DELAY_COMMON"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:DELAY_COMMON</th><th>[0, 3, 41]</th></tr>
+<tr><th>IOI1:DELAY_COMMON</th><th>[0, 3, 42]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:IFF_DELAY"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:IFF_DELAY"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY</th><th>[0, 3, 53]</th><th>[0, 3, 51]</th></tr>
+<tr><th>IOI1:IFF_DELAY</th><th>[0, 3, 58]</th><th>[0, 3, 47]</th></tr>
+<tr><td>Inverted</td><td>~[1]</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:DELAY_VARIABLE"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:DELAY_VARIABLE"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:DELAY_VARIABLE</th><th>[0, 3, 48]</th></tr>
+<tr><th>IOI1:DELAY_VARIABLE</th><th>[0, 3, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI0:I_DELAY"></div>
+<div id="bits-xc3s-IOI.S3ADSP.R-IOI1:I_DELAY"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY</th><th>[0, 3, 50]</th><th>[0, 3, 49]</th><th>[0, 3, 52]</th></tr>
+<tr><th>IOI1:I_DELAY</th><th>[0, 3, 56]</th><th>[0, 3, 55]</th><th>[0, 3, 54]</th></tr>
+<tr><td>Inverted</td><td>~[2]</td><td>~[1]</td><td>~[0]</td></tr>
+</table>
+</section>
+<section id="ioi-s3adsp-b">
+<h3><code class="docutils literal notranslate"><span class="pre">IOI.S3ADSP.B</span></code><a class="headerlink" href="#ioi-s3adsp-b" title="Link to this heading"></a></h3>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[0]">IOI0:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[1]">IOI0:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:IFF_DELAY_EN" title="IOI0:IFF_DELAY_EN">IOI0:IFF_DELAY_EN</a></td></tr>
+<tr><td>2</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:O2_DDRMUX" title="IOI1:O2_DDRMUX">IOI1:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[1]">IOI1:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>3</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:TFF1_SRVAL" title="~IOI0:TFF1_SRVAL">~IOI0:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:OFF1_SRVAL" title="~IOI0:OFF1_SRVAL">~IOI0:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:IFF1_SRVAL" title="~IOI0:IFF1_SRVAL">~IOI0:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:IFF_TSBYPASS_EN" title="IOI0:IFF_TSBYPASS_EN">IOI0:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:O1_DDRMUX" title="IOI1:O1_DDRMUX">IOI1:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:TSBYPASS_MUX" title="IOI0:TSBYPASS_MUX">IOI0:TSBYPASS_MUX</a></td></tr>
+<tr><td>5</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:TFF2_SRVAL" title="~IOI0:TFF2_SRVAL">~IOI0:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:OFF2_SRVAL" title="~IOI0:OFF2_SRVAL">~IOI0:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:IFF1_INIT" title="~IOI0:IFF1_INIT">~IOI0:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:I_TSBYPASS_EN" title="IOI0:I_TSBYPASS_EN">IOI0:I_TSBYPASS_EN</a></td></tr>
+<tr><td>8</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:TFF_INIT" title="~IOI0:TFF_INIT">~IOI0:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:OFF_INIT" title="~IOI0:OFF_INIT">~IOI0:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:IFF_SYNC" title="IOI0:IFF_SYNC">IOI0:IFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[0]">IOI0:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>9</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:TFF_REV_EN" title="IOI0:TFF_REV_EN">IOI0:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:OFF_REV_EN" title="IOI0:OFF_REV_EN">IOI0:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:IFF_REV_EN" title="IOI0:IFF_REV_EN">IOI0:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>10</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:TFF_SR_EN" title="IOI0:TFF_SR_EN">IOI0:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:OFF_SR_EN" title="IOI0:OFF_SR_EN">IOI0:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:IFF_SR_EN" title="IOI0:IFF_SR_EN">IOI0:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:I_DELAY_EN" title="IOI0:I_DELAY_EN">IOI0:I_DELAY_EN</a></td></tr>
+<tr><td>11</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:T2INV" title="IOI0:T2INV">IOI0:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:O2INV" title="IOI0:O2INV">IOI0:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:IFF_LATCH" title="IOI0:IFF_LATCH">IOI0:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:REVINV" title="~IOI0:REVINV">~IOI0:REVINV</a></td></tr>
+<tr><td>12</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:T1INV" title="IOI0:T1INV">IOI0:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:O1INV" title="IOI0:O1INV">IOI0:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:IFF2_INIT" title="~IOI0:IFF2_INIT">~IOI0:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:ICLK2INV" title="~IOI0:ICLK2INV">~IOI0:ICLK2INV</a></td></tr>
+<tr><td>13</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:TFF_SYNC" title="IOI0:TFF_SYNC">IOI0:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:OFF_SYNC" title="IOI0:OFF_SYNC">IOI0:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:ICLK1INV" title="~IOI0:ICLK1INV">~IOI0:ICLK1INV</a></td></tr>
+<tr><td>14</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:TMUX" title="IOI0:TMUX[1]">IOI0:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:OMUX" title="IOI0:OMUX[1]">IOI0:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:ICEINV" title="~IOI0:ICEINV">~IOI0:ICEINV</a></td></tr>
+<tr><td>15</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:TMUX" title="IOI0:TMUX[3]">IOI0:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:OMUX" title="IOI0:OMUX[3]">IOI0:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:OTCLK2INV" title="~IOI0:OTCLK2INV">~IOI0:OTCLK2INV</a></td></tr>
+<tr><td>16</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:TMUX" title="IOI0:TMUX[0]">IOI0:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:OMUX" title="IOI0:OMUX[0]">IOI0:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:IFF2_SRVAL" title="~IOI0:IFF2_SRVAL">~IOI0:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:OTCLK1INV" title="~IOI0:OTCLK1INV">~IOI0:OTCLK1INV</a></td></tr>
+<tr><td>17</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:TFF1_LATCH" title="IOI0:TFF1_LATCH">IOI0:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:OFF1_LATCH" title="IOI0:OFF1_LATCH">IOI0:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:TCEINV" title="~IOI0:TCEINV">~IOI0:TCEINV</a></td></tr>
+<tr><td>18</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:TFF2_LATCH" title="IOI0:TFF2_LATCH">IOI0:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:OFF2_LATCH" title="IOI0:OFF2_LATCH">IOI0:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[2]">IOI1:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>19</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:TMUX" title="IOI0:TMUX[2]">IOI0:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:OMUX" title="IOI0:OMUX[2]">IOI0:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:TMUX" title="IOI1:TMUX[2]">IOI1:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:OMUX" title="IOI1:OMUX[2]">IOI1:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:TFF2_LATCH" title="IOI1:TFF2_LATCH">IOI1:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:OFF2_LATCH" title="IOI1:OFF2_LATCH">IOI1:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[2]">IOI0:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>22</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:TFF1_LATCH" title="IOI1:TFF1_LATCH">IOI1:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:OFF1_LATCH" title="IOI1:OFF1_LATCH">IOI1:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:TCEINV" title="~IOI1:TCEINV">~IOI1:TCEINV</a></td></tr>
+<tr><td>23</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:TMUX" title="IOI1:TMUX[0]">IOI1:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:OMUX" title="IOI1:OMUX[0]">IOI1:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:IFF2_SRVAL" title="~IOI1:IFF2_SRVAL">~IOI1:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:OTCLK1INV" title="~IOI1:OTCLK1INV">~IOI1:OTCLK1INV</a></td></tr>
+<tr><td>24</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:TMUX" title="IOI1:TMUX[3]">IOI1:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:OMUX" title="IOI1:OMUX[3]">IOI1:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:OTCLK2INV" title="~IOI1:OTCLK2INV">~IOI1:OTCLK2INV</a></td></tr>
+<tr><td>25</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:TMUX" title="IOI1:TMUX[1]">IOI1:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:OMUX" title="IOI1:OMUX[1]">IOI1:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:ICEINV" title="~IOI1:ICEINV">~IOI1:ICEINV</a></td></tr>
+<tr><td>26</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:TFF_SYNC" title="IOI1:TFF_SYNC">IOI1:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:OFF_SYNC" title="IOI1:OFF_SYNC">IOI1:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:ICLK1INV" title="~IOI1:ICLK1INV">~IOI1:ICLK1INV</a></td></tr>
+<tr><td>27</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:T1INV" title="IOI1:T1INV">IOI1:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:O1INV" title="IOI1:O1INV">IOI1:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:IFF2_INIT" title="~IOI1:IFF2_INIT">~IOI1:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:ICLK2INV" title="~IOI1:ICLK2INV">~IOI1:ICLK2INV</a></td></tr>
+<tr><td>28</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:T2INV" title="IOI1:T2INV">IOI1:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:O2INV" title="IOI1:O2INV">IOI1:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:IFF_LATCH" title="IOI1:IFF_LATCH">IOI1:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:REVINV" title="~IOI1:REVINV">~IOI1:REVINV</a></td></tr>
+<tr><td>29</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:TFF_SR_EN" title="IOI1:TFF_SR_EN">IOI1:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:OFF_SR_EN" title="IOI1:OFF_SR_EN">IOI1:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:IFF_SR_EN" title="IOI1:IFF_SR_EN">IOI1:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:I_DELAY_EN" title="IOI1:I_DELAY_EN">IOI1:I_DELAY_EN</a></td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:TFF_REV_EN" title="IOI1:TFF_REV_EN">IOI1:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:OFF_REV_EN" title="IOI1:OFF_REV_EN">IOI1:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:IFF_REV_EN" title="IOI1:IFF_REV_EN">IOI1:IFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[0]">IOI1:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>31</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:TFF_INIT" title="~IOI1:TFF_INIT">~IOI1:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:OFF_INIT" title="~IOI1:OFF_INIT">~IOI1:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:IFF_SYNC" title="IOI1:IFF_SYNC">IOI1:IFF_SYNC</a></td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:IFF1_INIT" title="~IOI1:IFF1_INIT">~IOI1:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:I_TSBYPASS_EN" title="IOI1:I_TSBYPASS_EN">IOI1:I_TSBYPASS_EN</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:TFF2_SRVAL" title="~IOI1:TFF2_SRVAL">~IOI1:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:OFF2_SRVAL" title="~IOI1:OFF2_SRVAL">~IOI1:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:O1_DDRMUX" title="IOI0:O1_DDRMUX">IOI0:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:TSBYPASS_MUX" title="IOI1:TSBYPASS_MUX">IOI1:TSBYPASS_MUX</a></td></tr>
+<tr><td>36</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:TFF1_SRVAL" title="~IOI1:TFF1_SRVAL">~IOI1:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:OFF1_SRVAL" title="~IOI1:OFF1_SRVAL">~IOI1:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:IFF1_SRVAL" title="~IOI1:IFF1_SRVAL">~IOI1:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:IFF_TSBYPASS_EN" title="IOI1:IFF_TSBYPASS_EN">IOI1:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>37</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:O2_DDRMUX" title="IOI0:O2_DDRMUX">IOI0:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[1]">IOI0:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:IFF_DELAY_EN" title="IOI1:IFF_DELAY_EN">IOI1:IFF_DELAY_EN</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[0]">IOI1:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[1]">IOI1:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:PCICE_MUX" title="IOI2:PCICE_MUX[0]">IOI2:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:PCICE_MUX" title="IOI2:PCICE_MUX[1]">IOI2:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:IFF_DELAY_EN" title="IOI2:IFF_DELAY_EN">IOI2:IFF_DELAY_EN</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:IDDRIN_MUX" title="IOI2:IDDRIN_MUX[1]">IOI2:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>43</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:TFF1_SRVAL" title="~IOI2:TFF1_SRVAL">~IOI2:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:OFF1_SRVAL" title="~IOI2:OFF1_SRVAL">~IOI2:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:IFF1_SRVAL" title="~IOI2:IFF1_SRVAL">~IOI2:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:IFF_TSBYPASS_EN" title="IOI2:IFF_TSBYPASS_EN">IOI2:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:TSBYPASS_MUX" title="IOI2:TSBYPASS_MUX">IOI2:TSBYPASS_MUX</a></td></tr>
+<tr><td>45</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:TFF2_SRVAL" title="~IOI2:TFF2_SRVAL">~IOI2:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:OFF2_SRVAL" title="~IOI2:OFF2_SRVAL">~IOI2:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:IFF1_INIT" title="~IOI2:IFF1_INIT">~IOI2:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:I_TSBYPASS_EN" title="IOI2:I_TSBYPASS_EN">IOI2:I_TSBYPASS_EN</a></td></tr>
+<tr><td>48</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:TFF_INIT" title="~IOI2:TFF_INIT">~IOI2:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:OFF_INIT" title="~IOI2:OFF_INIT">~IOI2:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:IFF_SYNC" title="IOI2:IFF_SYNC">IOI2:IFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:IDDRIN_MUX" title="IOI2:IDDRIN_MUX[0]">IOI2:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>49</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:TFF_REV_EN" title="IOI2:TFF_REV_EN">IOI2:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:OFF_REV_EN" title="IOI2:OFF_REV_EN">IOI2:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:IFF_REV_EN" title="IOI2:IFF_REV_EN">IOI2:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>50</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:TFF_SR_EN" title="IOI2:TFF_SR_EN">IOI2:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:OFF_SR_EN" title="IOI2:OFF_SR_EN">IOI2:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:IFF_SR_EN" title="IOI2:IFF_SR_EN">IOI2:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:I_DELAY_EN" title="IOI2:I_DELAY_EN">IOI2:I_DELAY_EN</a></td></tr>
+<tr><td>51</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:T2INV" title="IOI2:T2INV">IOI2:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:O2INV" title="IOI2:O2INV">IOI2:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:IFF_LATCH" title="IOI2:IFF_LATCH">IOI2:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:REVINV" title="~IOI2:REVINV">~IOI2:REVINV</a></td></tr>
+<tr><td>52</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:T1INV" title="IOI2:T1INV">IOI2:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:O1INV" title="IOI2:O1INV">IOI2:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:IFF2_INIT" title="~IOI2:IFF2_INIT">~IOI2:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:ICLK2INV" title="~IOI2:ICLK2INV">~IOI2:ICLK2INV</a></td></tr>
+<tr><td>53</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:TFF_SYNC" title="IOI2:TFF_SYNC">IOI2:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:OFF_SYNC" title="IOI2:OFF_SYNC">IOI2:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:ICLK1INV" title="~IOI2:ICLK1INV">~IOI2:ICLK1INV</a></td></tr>
+<tr><td>54</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:TMUX" title="IOI2:TMUX[1]">IOI2:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:OMUX" title="IOI2:OMUX[1]">IOI2:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:ICEINV" title="~IOI2:ICEINV">~IOI2:ICEINV</a></td></tr>
+<tr><td>55</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:TMUX" title="IOI2:TMUX[3]">IOI2:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:OMUX" title="IOI2:OMUX[3]">IOI2:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:OTCLK2INV" title="~IOI2:OTCLK2INV">~IOI2:OTCLK2INV</a></td></tr>
+<tr><td>56</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:TMUX" title="IOI2:TMUX[0]">IOI2:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:OMUX" title="IOI2:OMUX[0]">IOI2:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:IFF2_SRVAL" title="~IOI2:IFF2_SRVAL">~IOI2:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:OTCLK1INV" title="~IOI2:OTCLK1INV">~IOI2:OTCLK1INV</a></td></tr>
+<tr><td>57</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:TFF1_LATCH" title="IOI2:TFF1_LATCH">IOI2:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:OFF1_LATCH" title="IOI2:OFF1_LATCH">IOI2:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:TCEINV" title="~IOI2:TCEINV">~IOI2:TCEINV</a></td></tr>
+<tr><td>58</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:TFF2_LATCH" title="IOI2:TFF2_LATCH">IOI2:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:OFF2_LATCH" title="IOI2:OFF2_LATCH">IOI2:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:IDDRIN_MUX" title="IOI2:IDDRIN_MUX[2]">IOI2:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>59</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:TMUX" title="IOI2:TMUX[2]">IOI2:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.B-IOI2:OMUX" title="IOI2:OMUX[2]">IOI2:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:O2_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:O2_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O2_DDRMUX</th><th>[0, 0, 37]</th></tr>
+<tr><th>IOI1:O2_DDRMUX</th><th>[0, 0, 2]</th></tr>
+<tr><td>O2</td><td>0</td></tr>
+<tr><td>ODDRIN2</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:TFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_SRVAL</th><th>[0, 0, 3]</th></tr>
+<tr><th>IOI1:TFF1_SRVAL</th><th>[0, 0, 36]</th></tr>
+<tr><th>IOI2:TFF1_SRVAL</th><th>[0, 0, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:TFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_SRVAL</th><th>[0, 0, 5]</th></tr>
+<tr><th>IOI1:TFF2_SRVAL</th><th>[0, 0, 34]</th></tr>
+<tr><th>IOI2:TFF2_SRVAL</th><th>[0, 0, 45]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:TFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_INIT</th><th>[0, 0, 8]</th></tr>
+<tr><th>IOI1:TFF_INIT</th><th>[0, 0, 31]</th></tr>
+<tr><th>IOI2:TFF_INIT</th><th>[0, 0, 48]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:TFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_REV_EN</th><th>[0, 0, 9]</th></tr>
+<tr><th>IOI1:TFF_REV_EN</th><th>[0, 0, 30]</th></tr>
+<tr><th>IOI2:TFF_REV_EN</th><th>[0, 0, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:TFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SR_EN</th><th>[0, 0, 10]</th></tr>
+<tr><th>IOI1:TFF_SR_EN</th><th>[0, 0, 29]</th></tr>
+<tr><th>IOI2:TFF_SR_EN</th><th>[0, 0, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:O1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:O2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:T1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:T2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:O1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:O2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:T1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:T2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:O1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:O2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:T1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:T2INV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1INV</th><th>[0, 1, 12]</th></tr>
+<tr><th>IOI0:O2INV</th><th>[0, 1, 11]</th></tr>
+<tr><th>IOI0:T1INV</th><th>[0, 0, 12]</th></tr>
+<tr><th>IOI0:T2INV</th><th>[0, 0, 11]</th></tr>
+<tr><th>IOI1:O1INV</th><th>[0, 1, 27]</th></tr>
+<tr><th>IOI1:O2INV</th><th>[0, 1, 28]</th></tr>
+<tr><th>IOI1:T1INV</th><th>[0, 0, 27]</th></tr>
+<tr><th>IOI1:T2INV</th><th>[0, 0, 28]</th></tr>
+<tr><th>IOI2:O1INV</th><th>[0, 1, 52]</th></tr>
+<tr><th>IOI2:O2INV</th><th>[0, 1, 51]</th></tr>
+<tr><th>IOI2:T1INV</th><th>[0, 0, 52]</th></tr>
+<tr><th>IOI2:T2INV</th><th>[0, 0, 51]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:TFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SYNC</th><th>[0, 0, 13]</th></tr>
+<tr><th>IOI1:TFF_SYNC</th><th>[0, 0, 26]</th></tr>
+<tr><th>IOI2:TFF_SYNC</th><th>[0, 0, 53]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:TMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:TMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:TMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TMUX</th><th>[0, 0, 15]</th><th>[0, 0, 19]</th><th>[0, 0, 14]</th><th>[0, 0, 16]</th></tr>
+<tr><th>IOI1:TMUX</th><th>[0, 0, 24]</th><th>[0, 0, 20]</th><th>[0, 0, 25]</th><th>[0, 0, 23]</th></tr>
+<tr><th>IOI2:TMUX</th><th>[0, 0, 55]</th><th>[0, 0, 59]</th><th>[0, 0, 54]</th><th>[0, 0, 56]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>T1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>T2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>TFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>TFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>TFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:TFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_LATCH</th><th>[0, 0, 17]</th></tr>
+<tr><th>IOI1:TFF1_LATCH</th><th>[0, 0, 22]</th></tr>
+<tr><th>IOI2:TFF1_LATCH</th><th>[0, 0, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:TFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_LATCH</th><th>[0, 0, 18]</th></tr>
+<tr><th>IOI1:TFF2_LATCH</th><th>[0, 0, 21]</th></tr>
+<tr><th>IOI2:TFF2_LATCH</th><th>[0, 0, 58]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:PCICE_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:PCICE_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:PCICE_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:PCICE_MUX</th><th>[0, 2, 0]</th><th>[0, 1, 0]</th></tr>
+<tr><th>IOI1:PCICE_MUX</th><th>[0, 2, 39]</th><th>[0, 1, 39]</th></tr>
+<tr><th>IOI2:PCICE_MUX</th><th>[0, 2, 40]</th><th>[0, 1, 40]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td></tr>
+<tr><td>OCE</td><td>0</td><td>1</td></tr>
+<tr><td>PCICE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:OFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_SRVAL</th><th>[0, 1, 3]</th></tr>
+<tr><th>IOI1:OFF1_SRVAL</th><th>[0, 1, 36]</th></tr>
+<tr><th>IOI2:OFF1_SRVAL</th><th>[0, 1, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:O1_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:O1_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1_DDRMUX</th><th>[0, 1, 35]</th></tr>
+<tr><th>IOI1:O1_DDRMUX</th><th>[0, 1, 4]</th></tr>
+<tr><td>O1</td><td>0</td></tr>
+<tr><td>ODDRIN1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:OFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_SRVAL</th><th>[0, 1, 5]</th></tr>
+<tr><th>IOI1:OFF2_SRVAL</th><th>[0, 1, 34]</th></tr>
+<tr><th>IOI2:OFF2_SRVAL</th><th>[0, 1, 45]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:OFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_INIT</th><th>[0, 1, 8]</th></tr>
+<tr><th>IOI1:OFF_INIT</th><th>[0, 1, 31]</th></tr>
+<tr><th>IOI2:OFF_INIT</th><th>[0, 1, 48]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:OFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_REV_EN</th><th>[0, 1, 9]</th></tr>
+<tr><th>IOI1:OFF_REV_EN</th><th>[0, 1, 30]</th></tr>
+<tr><th>IOI2:OFF_REV_EN</th><th>[0, 1, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:OFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SR_EN</th><th>[0, 1, 10]</th></tr>
+<tr><th>IOI1:OFF_SR_EN</th><th>[0, 1, 29]</th></tr>
+<tr><th>IOI2:OFF_SR_EN</th><th>[0, 1, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:OFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SYNC</th><th>[0, 1, 13]</th></tr>
+<tr><th>IOI1:OFF_SYNC</th><th>[0, 1, 26]</th></tr>
+<tr><th>IOI2:OFF_SYNC</th><th>[0, 1, 53]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:OMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:OMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:OMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OMUX</th><th>[0, 1, 15]</th><th>[0, 1, 19]</th><th>[0, 1, 14]</th><th>[0, 1, 16]</th></tr>
+<tr><th>IOI1:OMUX</th><th>[0, 1, 24]</th><th>[0, 1, 20]</th><th>[0, 1, 25]</th><th>[0, 1, 23]</th></tr>
+<tr><th>IOI2:OMUX</th><th>[0, 1, 55]</th><th>[0, 1, 59]</th><th>[0, 1, 54]</th><th>[0, 1, 56]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>O1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>O2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:OFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_LATCH</th><th>[0, 1, 17]</th></tr>
+<tr><th>IOI1:OFF1_LATCH</th><th>[0, 1, 22]</th></tr>
+<tr><th>IOI2:OFF1_LATCH</th><th>[0, 1, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:OFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_LATCH</th><th>[0, 1, 18]</th></tr>
+<tr><th>IOI1:OFF2_LATCH</th><th>[0, 1, 21]</th></tr>
+<tr><th>IOI2:OFF2_LATCH</th><th>[0, 1, 58]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:IFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_SRVAL</th><th>[0, 2, 3]</th></tr>
+<tr><th>IOI1:IFF1_SRVAL</th><th>[0, 2, 36]</th></tr>
+<tr><th>IOI2:IFF1_SRVAL</th><th>[0, 2, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:IFF1_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_INIT</th><th>[0, 2, 7]</th></tr>
+<tr><th>IOI1:IFF1_INIT</th><th>[0, 2, 32]</th></tr>
+<tr><th>IOI2:IFF1_INIT</th><th>[0, 2, 47]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:IFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SYNC</th><th>[0, 2, 8]</th></tr>
+<tr><th>IOI1:IFF_SYNC</th><th>[0, 2, 31]</th></tr>
+<tr><th>IOI2:IFF_SYNC</th><th>[0, 2, 48]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:IFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_REV_EN</th><th>[0, 2, 9]</th></tr>
+<tr><th>IOI1:IFF_REV_EN</th><th>[0, 2, 30]</th></tr>
+<tr><th>IOI2:IFF_REV_EN</th><th>[0, 2, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:IFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SR_EN</th><th>[0, 2, 10]</th></tr>
+<tr><th>IOI1:IFF_SR_EN</th><th>[0, 2, 29]</th></tr>
+<tr><th>IOI2:IFF_SR_EN</th><th>[0, 2, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:IFF_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_LATCH</th><th>[0, 2, 11]</th></tr>
+<tr><th>IOI1:IFF_LATCH</th><th>[0, 2, 28]</th></tr>
+<tr><th>IOI2:IFF_LATCH</th><th>[0, 2, 51]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:IFF2_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_INIT</th><th>[0, 2, 12]</th></tr>
+<tr><th>IOI1:IFF2_INIT</th><th>[0, 2, 27]</th></tr>
+<tr><th>IOI2:IFF2_INIT</th><th>[0, 2, 52]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:IFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_SRVAL</th><th>[0, 2, 16]</th></tr>
+<tr><th>IOI1:IFF2_SRVAL</th><th>[0, 2, 23]</th></tr>
+<tr><th>IOI2:IFF2_SRVAL</th><th>[0, 2, 56]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:IFF_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY_EN</th><th>[0, 3, 1]</th></tr>
+<tr><th>IOI1:IFF_DELAY_EN</th><th>[0, 3, 38]</th></tr>
+<tr><th>IOI2:IFF_DELAY_EN</th><th>[0, 3, 41]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:IFF_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_TSBYPASS_EN</th><th>[0, 3, 3]</th></tr>
+<tr><th>IOI1:IFF_TSBYPASS_EN</th><th>[0, 3, 36]</th></tr>
+<tr><th>IOI2:IFF_TSBYPASS_EN</th><th>[0, 3, 43]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:TSBYPASS_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TSBYPASS_MUX</th><th>[0, 3, 4]</th></tr>
+<tr><th>IOI1:TSBYPASS_MUX</th><th>[0, 3, 35]</th></tr>
+<tr><th>IOI2:TSBYPASS_MUX</th><th>[0, 3, 44]</th></tr>
+<tr><td>TMUX</td><td>0</td></tr>
+<tr><td>GND</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:I_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_TSBYPASS_EN</th><th>[0, 3, 7]</th></tr>
+<tr><th>IOI1:I_TSBYPASS_EN</th><th>[0, 3, 32]</th></tr>
+<tr><th>IOI2:I_TSBYPASS_EN</th><th>[0, 3, 47]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:IDDRIN_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:IDDRIN_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:IDDRIN_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IDDRIN_MUX</th><th>[0, 3, 21]</th><th>[0, 3, 37]</th><th>[0, 3, 8]</th></tr>
+<tr><th>IOI1:IDDRIN_MUX</th><th>[0, 3, 18]</th><th>[0, 3, 2]</th><th>[0, 3, 30]</th></tr>
+<tr><th>IOI2:IDDRIN_MUX</th><th>[0, 3, 58]</th><th>[0, 3, 42]</th><th>[0, 3, 48]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>IFFDMUX</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>IDDRIN1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>IDDRIN2</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:I_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY_EN</th><th>[0, 3, 10]</th></tr>
+<tr><th>IOI1:I_DELAY_EN</th><th>[0, 3, 29]</th></tr>
+<tr><th>IOI2:I_DELAY_EN</th><th>[0, 3, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:REVINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI0:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:REVINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI1:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:REVINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.B-IOI2:TCEINV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:ICEINV</th><th>[0, 3, 14]</th></tr>
+<tr><th>IOI0:ICLK1INV</th><th>[0, 3, 13]</th></tr>
+<tr><th>IOI0:ICLK2INV</th><th>[0, 3, 12]</th></tr>
+<tr><th>IOI0:OTCLK1INV</th><th>[0, 3, 16]</th></tr>
+<tr><th>IOI0:OTCLK2INV</th><th>[0, 3, 15]</th></tr>
+<tr><th>IOI0:REVINV</th><th>[0, 3, 11]</th></tr>
+<tr><th>IOI0:TCEINV</th><th>[0, 3, 17]</th></tr>
+<tr><th>IOI1:ICEINV</th><th>[0, 3, 25]</th></tr>
+<tr><th>IOI1:ICLK1INV</th><th>[0, 3, 26]</th></tr>
+<tr><th>IOI1:ICLK2INV</th><th>[0, 3, 27]</th></tr>
+<tr><th>IOI1:OTCLK1INV</th><th>[0, 3, 23]</th></tr>
+<tr><th>IOI1:OTCLK2INV</th><th>[0, 3, 24]</th></tr>
+<tr><th>IOI1:REVINV</th><th>[0, 3, 28]</th></tr>
+<tr><th>IOI1:TCEINV</th><th>[0, 3, 22]</th></tr>
+<tr><th>IOI2:ICEINV</th><th>[0, 3, 54]</th></tr>
+<tr><th>IOI2:ICLK1INV</th><th>[0, 3, 53]</th></tr>
+<tr><th>IOI2:ICLK2INV</th><th>[0, 3, 52]</th></tr>
+<tr><th>IOI2:OTCLK1INV</th><th>[0, 3, 56]</th></tr>
+<tr><th>IOI2:OTCLK2INV</th><th>[0, 3, 55]</th></tr>
+<tr><th>IOI2:REVINV</th><th>[0, 3, 51]</th></tr>
+<tr><th>IOI2:TCEINV</th><th>[0, 3, 57]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+</section>
+<section id="ioi-s3adsp-t">
+<h3><code class="docutils literal notranslate"><span class="pre">IOI.S3ADSP.T</span></code><a class="headerlink" href="#ioi-s3adsp-t" title="Link to this heading"></a></h3>
+<table class="docutils align-default prjcombine-tile">
+<tr><th rowspan="2">Row</th><th colspan="4">Column</th></tr><tr><th>0</th><th>1</th><th>2</th><th>3</th></tr>
+<tr><td>0</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[0]">IOI0:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:PCICE_MUX" title="IOI0:PCICE_MUX[1]">IOI0:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>1</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:IFF_DELAY_EN" title="IOI0:IFF_DELAY_EN">IOI0:IFF_DELAY_EN</a></td></tr>
+<tr><td>2</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:O2_DDRMUX" title="IOI1:O2_DDRMUX">IOI1:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[1]">IOI1:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>3</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:TFF1_SRVAL" title="~IOI0:TFF1_SRVAL">~IOI0:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:OFF1_SRVAL" title="~IOI0:OFF1_SRVAL">~IOI0:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:IFF1_SRVAL" title="~IOI0:IFF1_SRVAL">~IOI0:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:IFF_TSBYPASS_EN" title="IOI0:IFF_TSBYPASS_EN">IOI0:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>4</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:O1_DDRMUX" title="IOI1:O1_DDRMUX">IOI1:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:TSBYPASS_MUX" title="IOI0:TSBYPASS_MUX">IOI0:TSBYPASS_MUX</a></td></tr>
+<tr><td>5</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:TFF2_SRVAL" title="~IOI0:TFF2_SRVAL">~IOI0:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:OFF2_SRVAL" title="~IOI0:OFF2_SRVAL">~IOI0:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>6</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>7</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:IFF1_INIT" title="~IOI0:IFF1_INIT">~IOI0:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:I_TSBYPASS_EN" title="IOI0:I_TSBYPASS_EN">IOI0:I_TSBYPASS_EN</a></td></tr>
+<tr><td>8</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:TFF_INIT" title="~IOI0:TFF_INIT">~IOI0:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:OFF_INIT" title="~IOI0:OFF_INIT">~IOI0:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:IFF_SYNC" title="IOI0:IFF_SYNC">IOI0:IFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[0]">IOI0:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>9</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:TFF_REV_EN" title="IOI0:TFF_REV_EN">IOI0:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:OFF_REV_EN" title="IOI0:OFF_REV_EN">IOI0:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:IFF_REV_EN" title="IOI0:IFF_REV_EN">IOI0:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>10</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:TFF_SR_EN" title="IOI0:TFF_SR_EN">IOI0:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:OFF_SR_EN" title="IOI0:OFF_SR_EN">IOI0:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:IFF_SR_EN" title="IOI0:IFF_SR_EN">IOI0:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:I_DELAY_EN" title="IOI0:I_DELAY_EN">IOI0:I_DELAY_EN</a></td></tr>
+<tr><td>11</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:T2INV" title="IOI0:T2INV">IOI0:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:O2INV" title="IOI0:O2INV">IOI0:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:IFF_LATCH" title="IOI0:IFF_LATCH">IOI0:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:REVINV" title="~IOI0:REVINV">~IOI0:REVINV</a></td></tr>
+<tr><td>12</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:T1INV" title="IOI0:T1INV">IOI0:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:O1INV" title="IOI0:O1INV">IOI0:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:IFF2_INIT" title="~IOI0:IFF2_INIT">~IOI0:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:ICLK2INV" title="~IOI0:ICLK2INV">~IOI0:ICLK2INV</a></td></tr>
+<tr><td>13</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:TFF_SYNC" title="IOI0:TFF_SYNC">IOI0:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:OFF_SYNC" title="IOI0:OFF_SYNC">IOI0:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:ICLK1INV" title="~IOI0:ICLK1INV">~IOI0:ICLK1INV</a></td></tr>
+<tr><td>14</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:TMUX" title="IOI0:TMUX[1]">IOI0:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:OMUX" title="IOI0:OMUX[1]">IOI0:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:ICEINV" title="~IOI0:ICEINV">~IOI0:ICEINV</a></td></tr>
+<tr><td>15</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:TMUX" title="IOI0:TMUX[3]">IOI0:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:OMUX" title="IOI0:OMUX[3]">IOI0:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:OTCLK2INV" title="~IOI0:OTCLK2INV">~IOI0:OTCLK2INV</a></td></tr>
+<tr><td>16</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:TMUX" title="IOI0:TMUX[0]">IOI0:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:OMUX" title="IOI0:OMUX[0]">IOI0:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:IFF2_SRVAL" title="~IOI0:IFF2_SRVAL">~IOI0:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:OTCLK1INV" title="~IOI0:OTCLK1INV">~IOI0:OTCLK1INV</a></td></tr>
+<tr><td>17</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:TFF1_LATCH" title="IOI0:TFF1_LATCH">IOI0:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:OFF1_LATCH" title="IOI0:OFF1_LATCH">IOI0:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:TCEINV" title="~IOI0:TCEINV">~IOI0:TCEINV</a></td></tr>
+<tr><td>18</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:TFF2_LATCH" title="IOI0:TFF2_LATCH">IOI0:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:OFF2_LATCH" title="IOI0:OFF2_LATCH">IOI0:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[2]">IOI1:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>19</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:TMUX" title="IOI0:TMUX[2]">IOI0:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:OMUX" title="IOI0:OMUX[2]">IOI0:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>20</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:TMUX" title="IOI1:TMUX[2]">IOI1:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:OMUX" title="IOI1:OMUX[2]">IOI1:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+<tr><td>21</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:TFF2_LATCH" title="IOI1:TFF2_LATCH">IOI1:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:OFF2_LATCH" title="IOI1:OFF2_LATCH">IOI1:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[2]">IOI0:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>22</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:TFF1_LATCH" title="IOI1:TFF1_LATCH">IOI1:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:OFF1_LATCH" title="IOI1:OFF1_LATCH">IOI1:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:TCEINV" title="~IOI1:TCEINV">~IOI1:TCEINV</a></td></tr>
+<tr><td>23</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:TMUX" title="IOI1:TMUX[0]">IOI1:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:OMUX" title="IOI1:OMUX[0]">IOI1:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:IFF2_SRVAL" title="~IOI1:IFF2_SRVAL">~IOI1:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:OTCLK1INV" title="~IOI1:OTCLK1INV">~IOI1:OTCLK1INV</a></td></tr>
+<tr><td>24</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:TMUX" title="IOI1:TMUX[3]">IOI1:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:OMUX" title="IOI1:OMUX[3]">IOI1:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:OTCLK2INV" title="~IOI1:OTCLK2INV">~IOI1:OTCLK2INV</a></td></tr>
+<tr><td>25</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:TMUX" title="IOI1:TMUX[1]">IOI1:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:OMUX" title="IOI1:OMUX[1]">IOI1:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:ICEINV" title="~IOI1:ICEINV">~IOI1:ICEINV</a></td></tr>
+<tr><td>26</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:TFF_SYNC" title="IOI1:TFF_SYNC">IOI1:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:OFF_SYNC" title="IOI1:OFF_SYNC">IOI1:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:ICLK1INV" title="~IOI1:ICLK1INV">~IOI1:ICLK1INV</a></td></tr>
+<tr><td>27</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:T1INV" title="IOI1:T1INV">IOI1:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:O1INV" title="IOI1:O1INV">IOI1:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:IFF2_INIT" title="~IOI1:IFF2_INIT">~IOI1:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:ICLK2INV" title="~IOI1:ICLK2INV">~IOI1:ICLK2INV</a></td></tr>
+<tr><td>28</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:T2INV" title="IOI1:T2INV">IOI1:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:O2INV" title="IOI1:O2INV">IOI1:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:IFF_LATCH" title="IOI1:IFF_LATCH">IOI1:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:REVINV" title="~IOI1:REVINV">~IOI1:REVINV</a></td></tr>
+<tr><td>29</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:TFF_SR_EN" title="IOI1:TFF_SR_EN">IOI1:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:OFF_SR_EN" title="IOI1:OFF_SR_EN">IOI1:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:IFF_SR_EN" title="IOI1:IFF_SR_EN">IOI1:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:I_DELAY_EN" title="IOI1:I_DELAY_EN">IOI1:I_DELAY_EN</a></td></tr>
+<tr><td>30</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:TFF_REV_EN" title="IOI1:TFF_REV_EN">IOI1:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:OFF_REV_EN" title="IOI1:OFF_REV_EN">IOI1:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:IFF_REV_EN" title="IOI1:IFF_REV_EN">IOI1:IFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:IDDRIN_MUX" title="IOI1:IDDRIN_MUX[0]">IOI1:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>31</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:TFF_INIT" title="~IOI1:TFF_INIT">~IOI1:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:OFF_INIT" title="~IOI1:OFF_INIT">~IOI1:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:IFF_SYNC" title="IOI1:IFF_SYNC">IOI1:IFF_SYNC</a></td><td>-</td></tr>
+<tr><td>32</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:IFF1_INIT" title="~IOI1:IFF1_INIT">~IOI1:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:I_TSBYPASS_EN" title="IOI1:I_TSBYPASS_EN">IOI1:I_TSBYPASS_EN</a></td></tr>
+<tr><td>33</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>34</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:TFF2_SRVAL" title="~IOI1:TFF2_SRVAL">~IOI1:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:OFF2_SRVAL" title="~IOI1:OFF2_SRVAL">~IOI1:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>35</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:O1_DDRMUX" title="IOI0:O1_DDRMUX">IOI0:O1_DDRMUX</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:TSBYPASS_MUX" title="IOI1:TSBYPASS_MUX">IOI1:TSBYPASS_MUX</a></td></tr>
+<tr><td>36</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:TFF1_SRVAL" title="~IOI1:TFF1_SRVAL">~IOI1:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:OFF1_SRVAL" title="~IOI1:OFF1_SRVAL">~IOI1:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:IFF1_SRVAL" title="~IOI1:IFF1_SRVAL">~IOI1:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:IFF_TSBYPASS_EN" title="IOI1:IFF_TSBYPASS_EN">IOI1:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>37</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:O2_DDRMUX" title="IOI0:O2_DDRMUX">IOI0:O2_DDRMUX</a></td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI0:IDDRIN_MUX" title="IOI0:IDDRIN_MUX[1]">IOI0:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>38</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:IFF_DELAY_EN" title="IOI1:IFF_DELAY_EN">IOI1:IFF_DELAY_EN</a></td></tr>
+<tr><td>39</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[0]">IOI1:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI1:PCICE_MUX" title="IOI1:PCICE_MUX[1]">IOI1:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>40</td>
+<td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:PCICE_MUX" title="IOI2:PCICE_MUX[0]">IOI2:PCICE_MUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:PCICE_MUX" title="IOI2:PCICE_MUX[1]">IOI2:PCICE_MUX[1]</a></td><td>-</td></tr>
+<tr><td>41</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:IFF_DELAY_EN" title="IOI2:IFF_DELAY_EN">IOI2:IFF_DELAY_EN</a></td></tr>
+<tr><td>42</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:IDDRIN_MUX" title="IOI2:IDDRIN_MUX[1]">IOI2:IDDRIN_MUX[1]</a></td></tr>
+<tr><td>43</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:TFF1_SRVAL" title="~IOI2:TFF1_SRVAL">~IOI2:TFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:OFF1_SRVAL" title="~IOI2:OFF1_SRVAL">~IOI2:OFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:IFF1_SRVAL" title="~IOI2:IFF1_SRVAL">~IOI2:IFF1_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:IFF_TSBYPASS_EN" title="IOI2:IFF_TSBYPASS_EN">IOI2:IFF_TSBYPASS_EN</a></td></tr>
+<tr><td>44</td>
+<td>-</td><td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:TSBYPASS_MUX" title="IOI2:TSBYPASS_MUX">IOI2:TSBYPASS_MUX</a></td></tr>
+<tr><td>45</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:TFF2_SRVAL" title="~IOI2:TFF2_SRVAL">~IOI2:TFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:OFF2_SRVAL" title="~IOI2:OFF2_SRVAL">~IOI2:OFF2_SRVAL</a></td><td>-</td><td>-</td></tr>
+<tr><td>46</td>
+<td>-</td><td>-</td><td>-</td><td>-</td></tr>
+<tr><td>47</td>
+<td>-</td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:IFF1_INIT" title="~IOI2:IFF1_INIT">~IOI2:IFF1_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:I_TSBYPASS_EN" title="IOI2:I_TSBYPASS_EN">IOI2:I_TSBYPASS_EN</a></td></tr>
+<tr><td>48</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:TFF_INIT" title="~IOI2:TFF_INIT">~IOI2:TFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:OFF_INIT" title="~IOI2:OFF_INIT">~IOI2:OFF_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:IFF_SYNC" title="IOI2:IFF_SYNC">IOI2:IFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:IDDRIN_MUX" title="IOI2:IDDRIN_MUX[0]">IOI2:IDDRIN_MUX[0]</a></td></tr>
+<tr><td>49</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:TFF_REV_EN" title="IOI2:TFF_REV_EN">IOI2:TFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:OFF_REV_EN" title="IOI2:OFF_REV_EN">IOI2:OFF_REV_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:IFF_REV_EN" title="IOI2:IFF_REV_EN">IOI2:IFF_REV_EN</a></td><td>-</td></tr>
+<tr><td>50</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:TFF_SR_EN" title="IOI2:TFF_SR_EN">IOI2:TFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:OFF_SR_EN" title="IOI2:OFF_SR_EN">IOI2:OFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:IFF_SR_EN" title="IOI2:IFF_SR_EN">IOI2:IFF_SR_EN</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:I_DELAY_EN" title="IOI2:I_DELAY_EN">IOI2:I_DELAY_EN</a></td></tr>
+<tr><td>51</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:T2INV" title="IOI2:T2INV">IOI2:T2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:O2INV" title="IOI2:O2INV">IOI2:O2INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:IFF_LATCH" title="IOI2:IFF_LATCH">IOI2:IFF_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:REVINV" title="~IOI2:REVINV">~IOI2:REVINV</a></td></tr>
+<tr><td>52</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:T1INV" title="IOI2:T1INV">IOI2:T1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:O1INV" title="IOI2:O1INV">IOI2:O1INV</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:IFF2_INIT" title="~IOI2:IFF2_INIT">~IOI2:IFF2_INIT</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:ICLK2INV" title="~IOI2:ICLK2INV">~IOI2:ICLK2INV</a></td></tr>
+<tr><td>53</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:TFF_SYNC" title="IOI2:TFF_SYNC">IOI2:TFF_SYNC</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:OFF_SYNC" title="IOI2:OFF_SYNC">IOI2:OFF_SYNC</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:ICLK1INV" title="~IOI2:ICLK1INV">~IOI2:ICLK1INV</a></td></tr>
+<tr><td>54</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:TMUX" title="IOI2:TMUX[1]">IOI2:TMUX[1]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:OMUX" title="IOI2:OMUX[1]">IOI2:OMUX[1]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:ICEINV" title="~IOI2:ICEINV">~IOI2:ICEINV</a></td></tr>
+<tr><td>55</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:TMUX" title="IOI2:TMUX[3]">IOI2:TMUX[3]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:OMUX" title="IOI2:OMUX[3]">IOI2:OMUX[3]</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:OTCLK2INV" title="~IOI2:OTCLK2INV">~IOI2:OTCLK2INV</a></td></tr>
+<tr><td>56</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:TMUX" title="IOI2:TMUX[0]">IOI2:TMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:OMUX" title="IOI2:OMUX[0]">IOI2:OMUX[0]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:IFF2_SRVAL" title="~IOI2:IFF2_SRVAL">~IOI2:IFF2_SRVAL</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:OTCLK1INV" title="~IOI2:OTCLK1INV">~IOI2:OTCLK1INV</a></td></tr>
+<tr><td>57</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:TFF1_LATCH" title="IOI2:TFF1_LATCH">IOI2:TFF1_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:OFF1_LATCH" title="IOI2:OFF1_LATCH">IOI2:OFF1_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:TCEINV" title="~IOI2:TCEINV">~IOI2:TCEINV</a></td></tr>
+<tr><td>58</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:TFF2_LATCH" title="IOI2:TFF2_LATCH">IOI2:TFF2_LATCH</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:OFF2_LATCH" title="IOI2:OFF2_LATCH">IOI2:OFF2_LATCH</a></td><td>-</td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:IDDRIN_MUX" title="IOI2:IDDRIN_MUX[2]">IOI2:IDDRIN_MUX[2]</a></td></tr>
+<tr><td>59</td>
+<td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:TMUX" title="IOI2:TMUX[2]">IOI2:TMUX[2]</a></td><td><a href="#bits-xc3s-IOI.S3ADSP.T-IOI2:OMUX" title="IOI2:OMUX[2]">IOI2:OMUX[2]</a></td><td>-</td><td>-</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:O2_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:O2_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O2_DDRMUX</th><th>[0, 0, 37]</th></tr>
+<tr><th>IOI1:O2_DDRMUX</th><th>[0, 0, 2]</th></tr>
+<tr><td>O2</td><td>0</td></tr>
+<tr><td>ODDRIN2</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:TFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:TFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_SRVAL</th><th>[0, 0, 3]</th></tr>
+<tr><th>IOI1:TFF1_SRVAL</th><th>[0, 0, 36]</th></tr>
+<tr><th>IOI2:TFF1_SRVAL</th><th>[0, 0, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:TFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:TFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_SRVAL</th><th>[0, 0, 5]</th></tr>
+<tr><th>IOI1:TFF2_SRVAL</th><th>[0, 0, 34]</th></tr>
+<tr><th>IOI2:TFF2_SRVAL</th><th>[0, 0, 45]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:TFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:TFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_INIT</th><th>[0, 0, 8]</th></tr>
+<tr><th>IOI1:TFF_INIT</th><th>[0, 0, 31]</th></tr>
+<tr><th>IOI2:TFF_INIT</th><th>[0, 0, 48]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:TFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:TFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_REV_EN</th><th>[0, 0, 9]</th></tr>
+<tr><th>IOI1:TFF_REV_EN</th><th>[0, 0, 30]</th></tr>
+<tr><th>IOI2:TFF_REV_EN</th><th>[0, 0, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:TFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:TFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SR_EN</th><th>[0, 0, 10]</th></tr>
+<tr><th>IOI1:TFF_SR_EN</th><th>[0, 0, 29]</th></tr>
+<tr><th>IOI2:TFF_SR_EN</th><th>[0, 0, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:O1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:O2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:T1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:T2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:O1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:O2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:T1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:T2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:O1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:O2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:T1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:T2INV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1INV</th><th>[0, 1, 12]</th></tr>
+<tr><th>IOI0:O2INV</th><th>[0, 1, 11]</th></tr>
+<tr><th>IOI0:T1INV</th><th>[0, 0, 12]</th></tr>
+<tr><th>IOI0:T2INV</th><th>[0, 0, 11]</th></tr>
+<tr><th>IOI1:O1INV</th><th>[0, 1, 27]</th></tr>
+<tr><th>IOI1:O2INV</th><th>[0, 1, 28]</th></tr>
+<tr><th>IOI1:T1INV</th><th>[0, 0, 27]</th></tr>
+<tr><th>IOI1:T2INV</th><th>[0, 0, 28]</th></tr>
+<tr><th>IOI2:O1INV</th><th>[0, 1, 52]</th></tr>
+<tr><th>IOI2:O2INV</th><th>[0, 1, 51]</th></tr>
+<tr><th>IOI2:T1INV</th><th>[0, 0, 52]</th></tr>
+<tr><th>IOI2:T2INV</th><th>[0, 0, 51]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:TFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:TFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF_SYNC</th><th>[0, 0, 13]</th></tr>
+<tr><th>IOI1:TFF_SYNC</th><th>[0, 0, 26]</th></tr>
+<tr><th>IOI2:TFF_SYNC</th><th>[0, 0, 53]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:TMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:TMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:TMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TMUX</th><th>[0, 0, 15]</th><th>[0, 0, 19]</th><th>[0, 0, 14]</th><th>[0, 0, 16]</th></tr>
+<tr><th>IOI1:TMUX</th><th>[0, 0, 24]</th><th>[0, 0, 20]</th><th>[0, 0, 25]</th><th>[0, 0, 23]</th></tr>
+<tr><th>IOI2:TMUX</th><th>[0, 0, 55]</th><th>[0, 0, 59]</th><th>[0, 0, 54]</th><th>[0, 0, 56]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>T1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>T2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>TFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>TFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>TFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:TFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:TFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF1_LATCH</th><th>[0, 0, 17]</th></tr>
+<tr><th>IOI1:TFF1_LATCH</th><th>[0, 0, 22]</th></tr>
+<tr><th>IOI2:TFF1_LATCH</th><th>[0, 0, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:TFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:TFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TFF2_LATCH</th><th>[0, 0, 18]</th></tr>
+<tr><th>IOI1:TFF2_LATCH</th><th>[0, 0, 21]</th></tr>
+<tr><th>IOI2:TFF2_LATCH</th><th>[0, 0, 58]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:PCICE_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:PCICE_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:PCICE_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:PCICE_MUX</th><th>[0, 2, 0]</th><th>[0, 1, 0]</th></tr>
+<tr><th>IOI1:PCICE_MUX</th><th>[0, 2, 39]</th><th>[0, 1, 39]</th></tr>
+<tr><th>IOI2:PCICE_MUX</th><th>[0, 2, 40]</th><th>[0, 1, 40]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td></tr>
+<tr><td>OCE</td><td>0</td><td>1</td></tr>
+<tr><td>PCICE</td><td>1</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:OFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:OFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_SRVAL</th><th>[0, 1, 3]</th></tr>
+<tr><th>IOI1:OFF1_SRVAL</th><th>[0, 1, 36]</th></tr>
+<tr><th>IOI2:OFF1_SRVAL</th><th>[0, 1, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:O1_DDRMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:O1_DDRMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:O1_DDRMUX</th><th>[0, 1, 35]</th></tr>
+<tr><th>IOI1:O1_DDRMUX</th><th>[0, 1, 4]</th></tr>
+<tr><td>O1</td><td>0</td></tr>
+<tr><td>ODDRIN1</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:OFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:OFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_SRVAL</th><th>[0, 1, 5]</th></tr>
+<tr><th>IOI1:OFF2_SRVAL</th><th>[0, 1, 34]</th></tr>
+<tr><th>IOI2:OFF2_SRVAL</th><th>[0, 1, 45]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:OFF_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:OFF_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_INIT</th><th>[0, 1, 8]</th></tr>
+<tr><th>IOI1:OFF_INIT</th><th>[0, 1, 31]</th></tr>
+<tr><th>IOI2:OFF_INIT</th><th>[0, 1, 48]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:OFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:OFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_REV_EN</th><th>[0, 1, 9]</th></tr>
+<tr><th>IOI1:OFF_REV_EN</th><th>[0, 1, 30]</th></tr>
+<tr><th>IOI2:OFF_REV_EN</th><th>[0, 1, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:OFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:OFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SR_EN</th><th>[0, 1, 10]</th></tr>
+<tr><th>IOI1:OFF_SR_EN</th><th>[0, 1, 29]</th></tr>
+<tr><th>IOI2:OFF_SR_EN</th><th>[0, 1, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:OFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:OFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF_SYNC</th><th>[0, 1, 13]</th></tr>
+<tr><th>IOI1:OFF_SYNC</th><th>[0, 1, 26]</th></tr>
+<tr><th>IOI2:OFF_SYNC</th><th>[0, 1, 53]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:OMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:OMUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:OMUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OMUX</th><th>[0, 1, 15]</th><th>[0, 1, 19]</th><th>[0, 1, 14]</th><th>[0, 1, 16]</th></tr>
+<tr><th>IOI1:OMUX</th><th>[0, 1, 24]</th><th>[0, 1, 20]</th><th>[0, 1, 25]</th><th>[0, 1, 23]</th></tr>
+<tr><th>IOI2:OMUX</th><th>[0, 1, 55]</th><th>[0, 1, 59]</th><th>[0, 1, 54]</th><th>[0, 1, 56]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>O1</td><td>0</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>O2</td><td>0</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>OFF1</td><td>0</td><td>1</td><td>0</td><td>0</td></tr>
+<tr><td>OFF2</td><td>1</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>OFFDDR</td><td>1</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:OFF1_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:OFF1_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF1_LATCH</th><th>[0, 1, 17]</th></tr>
+<tr><th>IOI1:OFF1_LATCH</th><th>[0, 1, 22]</th></tr>
+<tr><th>IOI2:OFF1_LATCH</th><th>[0, 1, 57]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:OFF2_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:OFF2_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:OFF2_LATCH</th><th>[0, 1, 18]</th></tr>
+<tr><th>IOI1:OFF2_LATCH</th><th>[0, 1, 21]</th></tr>
+<tr><th>IOI2:OFF2_LATCH</th><th>[0, 1, 58]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:IFF1_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:IFF1_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_SRVAL</th><th>[0, 2, 3]</th></tr>
+<tr><th>IOI1:IFF1_SRVAL</th><th>[0, 2, 36]</th></tr>
+<tr><th>IOI2:IFF1_SRVAL</th><th>[0, 2, 43]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:IFF1_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:IFF1_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF1_INIT</th><th>[0, 2, 7]</th></tr>
+<tr><th>IOI1:IFF1_INIT</th><th>[0, 2, 32]</th></tr>
+<tr><th>IOI2:IFF1_INIT</th><th>[0, 2, 47]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:IFF_SYNC"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:IFF_SYNC"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SYNC</th><th>[0, 2, 8]</th></tr>
+<tr><th>IOI1:IFF_SYNC</th><th>[0, 2, 31]</th></tr>
+<tr><th>IOI2:IFF_SYNC</th><th>[0, 2, 48]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:IFF_REV_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:IFF_REV_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_REV_EN</th><th>[0, 2, 9]</th></tr>
+<tr><th>IOI1:IFF_REV_EN</th><th>[0, 2, 30]</th></tr>
+<tr><th>IOI2:IFF_REV_EN</th><th>[0, 2, 49]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:IFF_SR_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:IFF_SR_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_SR_EN</th><th>[0, 2, 10]</th></tr>
+<tr><th>IOI1:IFF_SR_EN</th><th>[0, 2, 29]</th></tr>
+<tr><th>IOI2:IFF_SR_EN</th><th>[0, 2, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:IFF_LATCH"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:IFF_LATCH"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_LATCH</th><th>[0, 2, 11]</th></tr>
+<tr><th>IOI1:IFF_LATCH</th><th>[0, 2, 28]</th></tr>
+<tr><th>IOI2:IFF_LATCH</th><th>[0, 2, 51]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:IFF2_INIT"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:IFF2_INIT"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_INIT</th><th>[0, 2, 12]</th></tr>
+<tr><th>IOI1:IFF2_INIT</th><th>[0, 2, 27]</th></tr>
+<tr><th>IOI2:IFF2_INIT</th><th>[0, 2, 52]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:IFF2_SRVAL"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:IFF2_SRVAL"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF2_SRVAL</th><th>[0, 2, 16]</th></tr>
+<tr><th>IOI1:IFF2_SRVAL</th><th>[0, 2, 23]</th></tr>
+<tr><th>IOI2:IFF2_SRVAL</th><th>[0, 2, 56]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:IFF_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:IFF_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_DELAY_EN</th><th>[0, 3, 1]</th></tr>
+<tr><th>IOI1:IFF_DELAY_EN</th><th>[0, 3, 38]</th></tr>
+<tr><th>IOI2:IFF_DELAY_EN</th><th>[0, 3, 41]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:IFF_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:IFF_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IFF_TSBYPASS_EN</th><th>[0, 3, 3]</th></tr>
+<tr><th>IOI1:IFF_TSBYPASS_EN</th><th>[0, 3, 36]</th></tr>
+<tr><th>IOI2:IFF_TSBYPASS_EN</th><th>[0, 3, 43]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:TSBYPASS_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:TSBYPASS_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:TSBYPASS_MUX</th><th>[0, 3, 4]</th></tr>
+<tr><th>IOI1:TSBYPASS_MUX</th><th>[0, 3, 35]</th></tr>
+<tr><th>IOI2:TSBYPASS_MUX</th><th>[0, 3, 44]</th></tr>
+<tr><td>TMUX</td><td>0</td></tr>
+<tr><td>GND</td><td>1</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:I_TSBYPASS_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:I_TSBYPASS_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_TSBYPASS_EN</th><th>[0, 3, 7]</th></tr>
+<tr><th>IOI1:I_TSBYPASS_EN</th><th>[0, 3, 32]</th></tr>
+<tr><th>IOI2:I_TSBYPASS_EN</th><th>[0, 3, 47]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:IDDRIN_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:IDDRIN_MUX"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:IDDRIN_MUX"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:IDDRIN_MUX</th><th>[0, 3, 21]</th><th>[0, 3, 37]</th><th>[0, 3, 8]</th></tr>
+<tr><th>IOI1:IDDRIN_MUX</th><th>[0, 3, 18]</th><th>[0, 3, 2]</th><th>[0, 3, 30]</th></tr>
+<tr><th>IOI2:IDDRIN_MUX</th><th>[0, 3, 58]</th><th>[0, 3, 42]</th><th>[0, 3, 48]</th></tr>
+<tr><td>NONE</td><td>0</td><td>0</td><td>0</td></tr>
+<tr><td>IFFDMUX</td><td>0</td><td>0</td><td>1</td></tr>
+<tr><td>IDDRIN1</td><td>0</td><td>1</td><td>0</td></tr>
+<tr><td>IDDRIN2</td><td>1</td><td>0</td><td>0</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:I_DELAY_EN"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:I_DELAY_EN"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:I_DELAY_EN</th><th>[0, 3, 10]</th></tr>
+<tr><th>IOI1:I_DELAY_EN</th><th>[0, 3, 29]</th></tr>
+<tr><th>IOI2:I_DELAY_EN</th><th>[0, 3, 50]</th></tr>
+<tr><td>Non-inverted</td><td>[0]</td></tr>
+</table>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:REVINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI0:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:REVINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI1:TCEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:ICEINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:ICLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:ICLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:OTCLK1INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:OTCLK2INV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:REVINV"></div>
+<div id="bits-xc3s-IOI.S3ADSP.T-IOI2:TCEINV"></div>
+<table class="docutils align-default prjcombine-enum">
+<tr><th>IOI0:ICEINV</th><th>[0, 3, 14]</th></tr>
+<tr><th>IOI0:ICLK1INV</th><th>[0, 3, 13]</th></tr>
+<tr><th>IOI0:ICLK2INV</th><th>[0, 3, 12]</th></tr>
+<tr><th>IOI0:OTCLK1INV</th><th>[0, 3, 16]</th></tr>
+<tr><th>IOI0:OTCLK2INV</th><th>[0, 3, 15]</th></tr>
+<tr><th>IOI0:REVINV</th><th>[0, 3, 11]</th></tr>
+<tr><th>IOI0:TCEINV</th><th>[0, 3, 17]</th></tr>
+<tr><th>IOI1:ICEINV</th><th>[0, 3, 25]</th></tr>
+<tr><th>IOI1:ICLK1INV</th><th>[0, 3, 26]</th></tr>
+<tr><th>IOI1:ICLK2INV</th><th>[0, 3, 27]</th></tr>
+<tr><th>IOI1:OTCLK1INV</th><th>[0, 3, 23]</th></tr>
+<tr><th>IOI1:OTCLK2INV</th><th>[0, 3, 24]</th></tr>
+<tr><th>IOI1:REVINV</th><th>[0, 3, 28]</th></tr>
+<tr><th>IOI1:TCEINV</th><th>[0, 3, 22]</th></tr>
+<tr><th>IOI2:ICEINV</th><th>[0, 3, 54]</th></tr>
+<tr><th>IOI2:ICLK1INV</th><th>[0, 3, 53]</th></tr>
+<tr><th>IOI2:ICLK2INV</th><th>[0, 3, 52]</th></tr>
+<tr><th>IOI2:OTCLK1INV</th><th>[0, 3, 56]</th></tr>
+<tr><th>IOI2:OTCLK2INV</th><th>[0, 3, 55]</th></tr>
+<tr><th>IOI2:REVINV</th><th>[0, 3, 51]</th></tr>
+<tr><th>IOI2:TCEINV</th><th>[0, 3, 57]</th></tr>
+<tr><td>Inverted</td><td>~[0]</td></tr>
+</table>
+</section>
+</section>
+<section id="i-o-buffers">
+<h2>I/O buffers<a class="headerlink" href="#i-o-buffers" title="Link to this heading"></a></h2>
+<div class="admonition-todo admonition" id="id3">
+<p class="admonition-title">Todo</p>
+<p>document</p>
+</div>
+</section>
+</section>
+
+
+           </div>
+          </div>
+          <footer><div class="rst-footer-buttons" role="navigation" aria-label="Footer">
+        <a href="clock.html" class="btn btn-neutral float-left" title="Clock interconnect" accesskey="p" rel="prev"><span class="fa fa-arrow-circle-left" aria-hidden="true"></span> Previous</a>
+        <a href="corner.html" class="btn btn-neutral float-right" title="Corners — Virtex 2, Spartan 3" accesskey="n" rel="next">Next <span class="fa fa-arrow-circle-right" aria-hidden="true"></span></a>
+    </div>
+
+  <hr/>
+
+  <div role="contentinfo">
+    <p>&#169; Copyright 2023, Wanda.</p>
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diff --git a/xilinx/virtex2/structure.html b/xilinx/virtex2/structure.html
index 591f7b3f..369f84c5 100644
--- a/xilinx/virtex2/structure.html
+++ b/xilinx/virtex2/structure.html
@@ -64,6 +64,7 @@
 <li class="toctree-l3"><a class="reference internal" href="clb.html">Configurable Logic Block</a></li>
 <li class="toctree-l3"><a class="reference internal" href="bram.html">Block RAM — Virtex 2, Spartan 3</a></li>
 <li class="toctree-l3"><a class="reference internal" href="clock.html">Clock interconnect</a></li>
+<li class="toctree-l3"><a class="reference internal" href="io.html">Input / Output — Virtex 2, Spartan 3</a></li>
 <li class="toctree-l3"><a class="reference internal" href="corner.html">Corners — Virtex 2, Spartan 3</a></li>
 </ul>
 </li>