diff --git a/databases/xcexf-tiledb.json b/databases/xcexf-tiledb.json
new file mode 100644
index 00000000..cb03ea0a
--- /dev/null
+++ b/databases/xcexf-tiledb.json
@@ -0,0 +1 @@
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alse],"OMUX12.NE":[false,true,false,false,false,false],"OMUX4":[true,false,false,false,false,false],"OMUX6":[false,true,false,false,true,false],"OUT.FAN3":[true,false,false,false,true,false]}},"INT:MUX.DBL.E3.0":{"bits":[[0,13,29],[0,13,31],[0,15,30],[0,13,30],[0,15,29],[0,15,28]],"values":{"DBL.E3.2":[true,false,false,false,false,true],"DBL.E5.2":[true,false,false,false,true,true],"DBL.N2.2":[false,false,true,false,false,true],"DBL.N3.1":[false,false,true,false,true,true],"DBL.S3.1":[false,true,false,false,false,true],"DBL.S5.2":[false,true,false,false,true,true],"HEX.E3.6":[false,true,false,false,false,false],"HEX.N3.3":[false,false,false,true,false,true],"HEX.N3.6":[false,false,true,false,false,false],"HEX.S3.3":[false,false,false,true,true,true],"HEX.S4.6":[false,true,false,false,true,false],"HEX.W3.6":[false,false,true,false,true,false],"NONE":[false,false,false,false,false,false],"OMUX3.SE":[true,false,false,false,true,false],"OMUX8.EN":[true,false,false,false,false,false],"OUT.FAN2":[false,false,false,true,true,false],"OUT.FAN4":[false,false,false,true,false,false]}},"INT:MUX.DBL.E4.0":{"bits":[[0,13,37],[0,13,38],[0,13,39],[0,15,38],[0,15,37],[0,15,36]],"values":{"DBL.E4.2":[true,false,false,false,false,true],"DBL.E6.2":[true,false,false,false,true,true],"DBL.N3.2":[false,false,true,false,false,true],"DBL.N4.1":[false,false,true,false,true,true],"DBL.S4.1":[false,true,false,false,true,true],"DBL.S6.2":[false,true,false,false,false,true],"HEX.E4.6":[false,false,true,false,false,false],"HEX.N4.3":[false,false,false,true,false,true],"HEX.N4.6":[false,false,false,true,false,false],"HEX.S4.3":[false,false,false,true,true,true],"HEX.S5.6":[false,false,true,false,true,false],"HEX.W4.6":[false,false,false,true,true,false],"NONE":[false,false,false,false,false,false],"OMUX7.E":[true,false,false,false,false,false],"OMUX8.E":[true,false,false,false,true,false],"OUT.FAN5":[false,true,false,false,false,false],"OUT.FAN6":[false,true,false,false,true,false]}},"INT:MUX.DBL.E5.0":{"bits":[[0,13,45],[0,13,47],[0,15,46],[0,13,46],[0,15,45],[0,15,44]],"values":{"DBL.E5.2":[true,false,false,false,false,true],"DBL.E7.2":[true,false,false,false,true,true],"DBL.N4.2":[false,false,true,false,false,true],"DBL.N5.1":[false,false,true,false,true,true],"DBL.S5.1":[false,true,false,false,false,true],"DBL.S7.2":[false,true,false,false,true,true],"HEX.E5.6":[false,true,false,false,false,false],"HEX.N5.3":[false,false,false,true,false,true],"HEX.N5.6":[false,false,true,false,false,false],"HEX.S5.3":[false,false,false,true,true,true],"HEX.S6.6":[false,true,false,false,true,false],"HEX.W5.6":[false,false,true,false,true,false],"NONE":[false,false,false,false,false,false],"OMUX12.NE":[true,false,false,false,false,false],"OMUX7.ES":[true,false,false,false,true,false],"OUT.FAN1":[false,false,false,true,false,false],"OUT.FAN7":[false,false,false,true,true,false]}},"INT:MUX.DBL.E6.0":{"bits":[[0,13,53],[0,13,54],[0,13,55],[0,15,54],[0,15,53],[0,15,52]],"values":{"DBL.E0.3":[true,false,false,false,true,true],"DBL.E6.2":[true,false,false,false,false,true],"DBL.N5.2":[false,false,true,false,false,true],"DBL.N6.1":[false,false,true,false,true,true],"DBL.S0.3":[false,true,false,false,false,true],"DBL.S6.1":[false,true,false,false,true,true],"HEX.E6.6":[false,false,true,false,false,false],"HEX.N6.3":[false,false,false,true,false,true],"HEX.N6.6":[false,false,false,true,false,false],"HEX.S6.3":[false,false,false,true,true,true],"HEX.S7.6":[false,false,true,false,true,false],"HEX.W6.6":[false,false,false,true,true,false],"NONE":[false,false,false,false,false,false],"OMUX11":[false,true,false,false,true,false],"OMUX3.SE":[true,false,false,false,true,false],"OMUX9":[true,false,false,false,false,false],"OUT.FAN0":[false,true,false,false,false,false]}},"INT:MUX.DBL.E7.0":{"bits":[[0,13,62],[0,13,61],[0,13,63],[0,15,62],[0,15,61],[0,15,60]],"values":{"DBL.E1.3":[false,true,false,false,true,true],"DBL.E7.2":[false,true,false,false,false,true],"DBL.N6.2":[false,false,false,true,false,true],"DBL.N7.1":[false,false,false,true,true,true],"DBL.S1.3":[false,false,true,false,true,true],"DBL.S7.1":[false,false,true,false,false,true],"HEX.E7.6":[false,false,true,false,false,false],"HEX.N7.3":[true,false,false,false,false,true],"HEX.N7.6":[false,false,false,true,false,false],"HEX.S0.7":[false,false,true,false,true,false],"HEX.S7.3":[true,false,false,false,true,true],"HEX.W7.6":[false,false,false,true,true,false],"NONE":[false,false,false,false,false,false],"OMUX0.S":[true,false,false,false,true,false],"OMUX11.N":[false,true,false,false,false,false],"OMUX2.S":[false,true,false,false,true,false],"OUT.FAN6":[true,false,false,false,false,false]}},"INT:MUX.DBL.N0.0":{"bits":[[0,14,1],[0,13,3],[0,15,0],[0,14,0],[0,14,2],[0,14,3]],"values":{"DBL.E0.1":[true,false,false,false,true,true],"DBL.E1.2":[false,false,false,true,true,true],"DBL.N0.2":[false,true,false,false,false,true],"DBL.N6.3":[false,true,false,false,true,true],"DBL.W0.1":[true,false,false,false,false,true],"DBL.W6.3":[false,false,true,false,false,true],"HEX.E0.3":[false,false,false,true,false,true],"HEX.E0.6":[false,false,false,true,false,false],"HEX.N0.6":[false,false,true,false,false,false],"HEX.S0.6":[false,false,false,true,true,false],"HEX.W0.3":[false,false,true,false,true,true],"HEX.W7.7":[false,false,true,false,true,false],"NONE":[false,false,false,false,false,false],"OMUX0":[true,false,false,false,true,false],"OMUX8.EN":[false,true,false,false,false,false],"OMUX9.N":[false,true,false,false,true,false],"OUT.FAN3":[true,false,false,false,false,false]}},"INT:MUX.DBL.N1.0":{"bits":[[0,13,11],[0,14,8],[0,14,9],[0,15,8],[0,14,10],[0,14,11]],"values":{"DBL.E1.1":[false,false,true,false,true,true],"DBL.E2.2":[false,false,true,false,false,true],"DBL.N1.2":[true,false,false,false,false,true],"DBL.N7.3":[true,false,false,false,true,true],"DBL.W1.1":[false,true,false,false,false,true],"DBL.W7.3":[false,true,false,false,true,true],"HEX.E1.3":[false,false,false,true,true,true],"HEX.E1.6":[false,true,false,false,false,false],"HEX.N1.6":[false,false,false,true,false,false],"HEX.S1.6":[false,true,false,false,true,false],"HEX.W0.6":[false,false,false,true,true,false],"HEX.W1.3":[false,false,false,true,false,true],"NONE":[false,false,false,false,false,false],"OMUX10.N":[true,false,false,false,false,false],"OMUX10.NW":[true,false,false,false,true,false],"OUT.FAN2":[false,false,true,false,false,false],"OUT.FAN4":[false,false,true,false,true,false]}},"INT:MUX.DBL.N2.0":{"bits":[[0,13,19],[0,14,17],[0,15,16],[0,14,16],[0,14,18],[0,14,19]],"values":{"DBL.E2.1":[false,true,false,false,true,true],"DBL.E3.2":[false,false,false,true,true,true],"DBL.N0.2":[true,false,false,false,true,true],"DBL.N2.2":[true,false,false,false,false,true],"DBL.W0.2":[false,false,true,false,false,true],"DBL.W2.1":[false,true,false,false,false,true],"HEX.E2.3":[false,false,false,true,false,true],"HEX.E2.6":[false,false,false,true,false,false],"HEX.N2.6":[false,false,true,false,false,false],"HEX.S2.6":[false,false,false,true,true,false],"HEX.W1.6":[false,false,true,false,true,false],"HEX.W2.3":[false,false,true,false,true,true],"NONE":[false,false,false,false,false,false],"OMUX1.W":[true,false,false,false,true,false],"OMUX12.NE":[true,false,false,false,false,false],"OMUX4":[false,true,false,false,false,false],"OUT.FAN5":[false,true,false,false,true,false]}},"INT:MUX.DBL.N3.0":{"bits":[[0,13,27],[0,14,24],[0,14,25],[0,15,24],[0,14,26],[0,14,27]],"values":{"DBL.E3.1":[false,false,true,false,true,true],"DBL.E4.2":[false,false,true,false,false,true],"DBL.N1.2":[true,false,false,false,true,true],"DBL.N3.2":[true,false,false,false,false,true],"DBL.W1.2":[false,true,false,false,true,true],"DBL.W3.1":[false,true,false,false,false,true],"HEX.E3.3":[false,false,false,true,true,true],"HEX.E3.6":[false,true,false,false,false,false],"HEX.N3.6":[false,false,false,true,false,false],"HEX.S3.6":[false,true,false,false,true,false],"HEX.W2.6":[false,false,false,true,true,false],"HEX.W3.3":[false,false,false,true,false,true],"NONE":[false,false,false,false,false,false],"OMUX14.WN":[true,false,false,false,true,false],"OMUX8.EN":[true,false,false,false,false,false],"OUT.FAN3":[false,false,true,false,true,false],"OUT.FAN4":[false,false,true,false,false,false]}},"INT:MUX.DBL.N4.0":{"bits":[[0,13,35],[0,15,32],[0,14,33],[0,14,32],[0,14,34],[0,14,35]],"values":{"DBL.E4.1":[false,false,true,false,true,true],"DBL.E5.2":[false,false,false,true,true,true],"DBL.N2.2":[true,false,false,false,true,true],"DBL.N4.2":[true,false,false,false,false,true],"DBL.W2.2":[false,true,false,false,false,true],"DBL.W4.1":[false,false,true,false,false,true],"HEX.E4.3":[false,false,false,true,false,true],"HEX.E4.6":[false,false,false,true,false,false],"HEX.N4.6":[false,true,false,false,false,false],"HEX.S4.6":[false,false,false,true,true,false],"HEX.W3.6":[false,true,false,false,true,false],"HEX.W4.3":[false,true,false,false,true,true],"NONE":[false,false,false,false,false,false],"OMUX10.NW":[true,false,false,false,true,false],"OMUX7.E":[true,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,true,false],"OUT.FAN5":[false,false,true,false,false,false]}},"INT:MUX.DBL.N5.0":{"bits":[[0,13,43],[0,14,40],[0,14,41],[0,15,40],[0,14,42],[0,14,43]],"values":{"DBL.E5.1":[false,false,true,false,true,true],"DBL.E6.2":[false,false,true,false,false,true],"DBL.N3.2":[true,false,false,false,true,true],"DBL.N5.2":[true,false,false,false,false,true],"DBL.W3.2":[false,true,false,false,true,true],"DBL.W5.1":[false,true,false,false,false,true],"HEX.E5.3":[false,false,false,true,true,true],"HEX.E5.6":[false,true,false,false,false,false],"HEX.N5.6":[false,false,false,true,false,false],"HEX.S5.6":[false,true,false,false,true,false],"HEX.W4.6":[false,false,false,true,true,false],"HEX.W5.3":[false,false,false,true,false,true],"NONE":[false,false,false,false,false,false],"OMUX12.N":[true,false,false,false,true,false],"OMUX12.NE":[true,false,false,false,false,false],"OUT.FAN1":[false,false,true,false,false,false],"OUT.FAN6":[false,false,true,false,true,false]}},"INT:MUX.DBL.N6.0":{"bits":[[0,13,51],[0,15,48],[0,14,49],[0,14,48],[0,14,50],[0,14,51]],"values":{"DBL.E6.1":[false,false,true,false,true,true],"DBL.E7.2":[false,false,false,true,true,true],"DBL.N4.2":[true,false,false,false,true,true],"DBL.N6.2":[true,false,false,false,false,true],"DBL.W4.2":[false,true,false,false,false,true],"DBL.W6.1":[false,false,true,false,false,true],"HEX.E6.3":[false,false,false,true,false,true],"HEX.E6.6":[false,false,false,true,false,false],"HEX.N6.6":[false,true,false,false,false,false],"HEX.S6.6":[false,false,false,true,true,false],"HEX.W5.6":[false,true,false,false,true,false],"HEX.W6.3":[false,true,false,false,true,true],"NONE":[false,false,false,false,false,false],"OMUX14.WN":[true,false,false,false,true,false],"OMUX9":[true,false,false,false,false,false],"OUT.FAN0":[false,false,true,false,false,false],"OUT.FAN7":[false,false,true,false,true,false]}},"INT:MUX.DBL.N7.0":{"bits":[[0,13,59],[0,14,57],[0,14,56],[0,15,56],[0,14,58],[0,14,59]],"values":{"DBL.E0.3":[false,true,false,false,false,true],"DBL.E7.1":[false,true,false,false,true,true],"DBL.N5.2":[true,false,false,false,true,true],"DBL.N7.2":[true,false,false,false,false,true],"DBL.W5.2":[false,false,true,false,true,true],"DBL.W7.1":[false,false,true,false,false,true],"HEX.E7.3":[false,false,false,true,true,true],"HEX.E7.6":[false,false,true,false,false,false],"HEX.N7.6":[false,false,false,true,false,false],"HEX.S7.6":[false,false,true,false,true,false],"HEX.W6.6":[false,false,false,true,true,false],"HEX.W7.3":[false,false,false,true,false,true],"NONE":[false,false,false,false,false,false],"OMUX11":[false,true,false,false,true,false],"OMUX11.N":[true,false,false,false,false,false],"OMUX9.W":[true,false,false,false,true,false],"OUT.FAN6":[false,true,false,false,false,false]}},"INT:MUX.DBL.S0.0":{"bits":[[0,13,1],[0,13,2],[0,15,1],[0,13,0],[0,15,2],[0,15,3]],"values":{"DBL.E0.1":[true,false,false,false,true,true],"DBL.E1.2":[false,false,false,true,true,true],"DBL.S0.2":[false,true,false,false,true,true],"DBL.S2.2":[false,true,false,false,false,true],"DBL.W0.1":[true,false,false,false,false,true],"DBL.W6.3":[false,false,true,false,false,true],"HEX.E0.3":[false,false,false,true,false,true],"HEX.E0.6":[false,false,false,true,false,false],"HEX.N0.6":[false,false,true,false,false,false],"HEX.S0.6":[false,false,false,true,true,false],"HEX.W0.3":[false,false,true,false,true,true],"HEX.W7.7":[false,false,true,false,true,false],"NONE":[false,false,false,false,false,false],"OMUX0":[true,false,false,false,true,false],"OMUX0.S":[false,true,false,false,false,false],"OMUX2":[false,true,false,false,true,false],"OUT.FAN3":[true,false,false,false,false,false]}},"INT:MUX.DBL.S1.0":{"bits":[[0,13,10],[0,13,8],[0,13,9],[0,15,9],[0,15,10],[0,15,11]],"values":{"DBL.E1.1":[false,false,true,false,true,true],"DBL.E2.2":[false,false,true,false,false,true],"DBL.S1.2":[true,false,false,false,true,true],"DBL.S3.2":[true,false,false,false,false,true],"DBL.W1.1":[false,true,false,false,false,true],"DBL.W7.3":[false,true,false,false,true,true],"HEX.E1.3":[false,false,false,true,true,true],"HEX.E1.6":[false,true,false,false,false,false],"HEX.N1.6":[false,false,false,true,false,false],"HEX.S1.6":[false,true,false,false,true,false],"HEX.W0.6":[false,false,false,true,true,false],"HEX.W1.3":[false,false,false,true,false,true],"NONE":[false,false,false,false,false,false],"OMUX2":[true,false,false,false,false,false],"OMUX2.E":[true,false,false,false,true,false],"OUT.FAN2":[false,false,true,false,false,false],"OUT.FAN4":[false,false,true,false,true,false]}},"INT:MUX.DBL.S2.0":{"bits":[[0,13,17],[0,13,18],[0,15,17],[0,13,16],[0,15,18],[0,15,19]],"values":{"DBL.E2.1":[true,false,false,false,true,true],"DBL.E3.2":[false,false,false,true,true,true],"DBL.S2.2":[false,true,false,false,true,true],"DBL.S4.2":[false,true,false,false,false,true],"DBL.W0.2":[false,false,true,false,false,true],"DBL.W2.1":[true,false,false,false,false,true],"HEX.E2.3":[false,false,false,true,false,true],"HEX.E2.6":[false,false,false,true,false,false],"HEX.N2.6":[false,false,true,false,false,false],"HEX.S2.6":[false,false,false,true,true,false],"HEX.W1.6":[false,false,true,false,true,false],"HEX.W2.3":[false,false,true,false,true,true],"NONE":[false,false,false,false,false,false],"OMUX4":[true,false,false,false,false,false],"OMUX4.S":[false,true,false,false,true,false],"OMUX6":[false,true,false,false,false,false],"OUT.FAN5":[true,false,false,false,true,false]}},"INT:MUX.DBL.S3.0":{"bits":[[0,13,26],[0,13,24],[0,13,25],[0,15,25],[0,15,26],[0,15,27]],"values":{"DBL.E3.1":[false,false,true,false,true,true],"DBL.E4.2":[false,false,true,false,false,true],"DBL.S3.2":[true,false,false,false,true,true],"DBL.S5.2":[true,false,false,false,false,true],"DBL.W1.2":[false,true,false,false,true,true],"DBL.W3.1":[false,true,false,false,false,true],"HEX.E3.3":[false,false,false,true,true,true],"HEX.E3.6":[false,true,false,false,false,false],"HEX.N3.6":[false,fa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,[0,18,5],[0,17,5],[0,17,4]],"values":{"HEX.N0.3":[false,false,true,false,true],"HEX.N7.7":[false,true,false,true,false],"HEX.S0.3":[false,true,false,true,true],"HEX.S2.6":[false,true,false,false,false],"HEX.W0.6":[true,false,false,true,true],"HEX.W6.7":[true,false,false,false,true],"LH.6":[false,true,false,false,true],"NONE":[false,false,false,false,false],"OMUX0.S":[true,false,false,false,false],"OMUX10.NW":[true,false,false,true,false],"OUT.FAN3":[false,false,true,false,false],"OUT.FAN4":[false,false,true,true,false]}},"INT:MUX.HEX.W1.0":{"bits":[[0,18,12],[0,17,14],[0,17,15],[0,16,13],[0,16,12]],"values":{"HEX.N0.6":[false,true,false,false,false],"HEX.N1.3":[false,false,true,false,true],"HEX.S1.3":[false,true,false,true,false],"HEX.S3.6":[false,true,false,true,true],"HEX.W1.6":[true,false,false,true,true],"HEX.W7.7":[true,false,false,false,true],"LH.0":[false,true,false,false,true],"NONE":[false,false,false,false,false],"OMUX1.W":[true,false,false,true,false],"OMUX2":[true,false,false,false,false],"OUT.FAN2":[false,false,true,false,false],"OUT.FAN5":[false,false,true,true,false]}},"INT:MUX.HEX.W2.0":{"bits":[[0,18,21],[0,16,22],[0,16,23],[0,17,21],[0,17,20]],"values":{"HEX.N1.6":[false,false,true,true,false],"HEX.N2.3":[true,false,false,false,true],"HEX.S2.3":[false,false,true,true,true],"HEX.S4.6":[false,false,true,false,false],"HEX.W0.6":[false,true,false,false,true],"HEX.W2.6":[false,true,false,true,true],"LH.6":[false,false,true,false,true],"NONE":[false,false,false,false,false],"OMUX14.WN":[false,true,false,true,false],"OMUX4":[true,false,false,false,false],"OMUX6":[false,true,false,false,false],"OUT.FAN3":[true,false,false,true,false]}},"INT:MUX.HEX.W3.0":{"bits":[[0,18,28],[0,17,30],[0,17,31],[0,16,29],[0,16,28]],"values":{"HEX.N2.6":[false,true,false,false,false],"HEX.N3.3":[false,false,true,false,true],"HEX.S3.3":[false,true,false,true,false],"HEX.S5.6":[false,true,false,true,true],"HEX.W1.6":[true,false,false,false,true],"HEX.W3.6":[true,false,false,true,true],"LH.0":[false,true,false,false,true],"NONE":[false,false,false,false,false],"OMUX10.NW":[true,false,false,true,false],"OMUX6.W":[true,false,false,false,false],"OUT.FAN2":[false,false,true,true,false],"OUT.FAN4":[false,false,true,false,false]}},"INT:MUX.HEX.W4.0":{"bits":[[0,16,38],[0,16,39],[0,18,37],[0,17,37],[0,17,36]],"values":{"HEX.N3.6":[false,true,false,true,false],"HEX.N4.3":[false,false,true,false,true],"HEX.S4.3":[false,true,false,true,true],"HEX.S6.6":[false,true,false,false,false],"HEX.W2.6":[true,false,false,false,true],"HEX.W4.6":[true,false,false,true,true],"LH.6":[false,true,false,false,true],"NONE":[false,false,false,false,false],"OMUX1.WS":[true,false,false,false,false],"OMUX12.N":[true,false,false,true,false],"OUT.FAN5":[false,false,true,false,false],"OUT.FAN6":[false,false,true,true,false]}},"INT:MUX.HEX.W5.0":{"bits":[[0,18,44],[0,17,46],[0,17,47],[0,16,45],[0,16,44]],"values":{"HEX.N4.6":[false,true,false,false,false],"HEX.N5.3":[false,false,true,false,true],"HEX.S5.3":[false,true,false,true,false],"HEX.S7.6":[false,true,false,true,true],"HEX.W3.6":[true,false,false,false,true],"HEX.W5.6":[true,false,false,true,true],"LH.0":[false,true,false,false,true],"NONE":[false,false,false,false,false],"OMUX14.WN":[true,false,false,true,false],"OMUX3.S":[true,false,false,false,false],"OUT.FAN1":[false,false,true,false,false],"OUT.FAN7":[false,false,true,true,false]}},"INT:MUX.HEX.W6.0":{"bits":[[0,16,54],[0,18,53],[0,16,55],[0,17,53],[0,17,52]],"values":{"HEX.N5.6":[false,false,true,true,false],"HEX.N6.3":[false,true,false,false,true],"HEX.S0.7":[false,false,true,false,false],"HEX.S6.3":[false,false,true,true,true],"HEX.W4.6":[true,false,false,false,true],"HEX.W6.6":[true,false,false,true,true],"LH.6":[false,false,true,false,true],"NONE":[false,false,false,false,false],"OMUX11":[false,true,false,true,false],"OMUX5.SW":[true,false,false,false,false],"OMUX9.W":[true,false,false,true,false],"OUT.FAN0":[false,true,false,false,false]}},"INT:MUX.HEX.W7.0":{"bits":[[0,17,63],[0,18,60],[0,17,62],[0,16,61],[0,16,60]],"values":{"HEX.N6.6":[false,false,true,false,false],"HEX.N7.3":[true,false,false,false,true],"HEX.S1.7":[false,false,true,true,true],"HEX.S7.3":[false,false,true,true,false],"HEX.W5.6":[false,true,false,false,true],"HEX.W7.6":[false,true,false,true,true],"LH.0":[false,false,true,false,true],"NONE":[false,false,false,false,false],"OMUX0.S":[true,false,false,true,false],"OMUX1.WS":[false,true,false,false,false],"OMUX9":[false,true,false,true,false],"OUT.FAN6":[true,false,false,false,false]}},"INT:MUX.IMUX.CE0":{"bits":[[0,4,52],[0,4,54],[0,5,54],[0,5,51],[0,4,56],[0,4,55]],"values":{"DBL.E6.0":[true,false,false,false,true,true],"DBL.E6.1":[true,false,false,false,false,true],"DBL.W6.1":[true,false,false,false,true,false],"DBL.W6.2":[true,false,false,false,false,false],"HEX.N7.0":[false,false,false,true,true,false],"HEX.N7.1":[false,false,true,false,true,false],"HEX.N7.2":[false,true,false,false,true,false],"HEX.N7.3":[false,false,false,true,false,false],"HEX.N7.4":[false,false,true,false,false,false],"HEX.N7.5":[false,true,false,false,false,false],"HEX.S7.1":[false,true,false,false,true,true],"HEX.S7.2":[false,false,true,false,true,true],"HEX.S7.3":[false,false,false,true,true,true],"HEX.S7.4":[false,true,false,false,false,true],"HEX.S7.5":[false,false,true,false,false,true],"HEX.S7.6":[false,false,false,true,false,true],"PULLUP":[false,false,false,false,false,false]}},"INT:MUX.IMUX.CE1":{"bits":[[0,4,59],[0,5,61],[0,5,58],[0,4,61],[0,4,57],[0,4,58]],"values":{"DBL.E7.0":[true,false,false,false,false,true],"DBL.E7.1":[true,false,false,false,true,true],"DBL.W7.1":[true,false,false,false,false,false],"DBL.W7.2":[true,false,false,false,true,false],"HEX.N7.0":[false,false,false,true,true,false],"HEX.N7.1":[false,false,true,false,true,false],"HEX.N7.2":[false,true,false,false,true,false],"HEX.N7.3":[false,false,false,true,false,false],"HEX.N7.4":[false,false,true,false,false,false],"HEX.N7.5":[false,true,false,false,false,false],"HEX.S7.1":[false,true,false,false,true,true],"HEX.S7.2":[false,false,true,false,true,true],"HEX.S7.3":[false,false,false,true,true,true],"HEX.S7.4":[false,true,false,false,false,true],"HEX.S7.5":[false,false,true,false,false,true],"HEX.S7.6":[false,false,false,true,false,true],"PULLUP":[false,false,false,false,false,false]}},"INT:MUX.IMUX.CE2":{"bits":[[0,5,52],[0,5,55],[0,4,53],[0,5,53],[0,4,50],[0,4,51]],"values":{"DBL.E6.0":[true,false,false,false,true,true],"DBL.E6.1":[true,false,false,false,false,true],"DBL.W6.1":[true,false,false,false,true,false],"DBL.W6.2":[true,false,false,false,false,false],"HEX.N7.0":[false,false,false,true,true,false],"HEX.N7.1":[false,false,true,false,true,false],"HEX.N7.2":[false,true,false,false,true,false],"HEX.N7.3":[false,false,false,true,false,false],"HEX.N7.4":[false,false,true,false,false,false],"HEX.N7.5":[false,true,false,false,false,false],"HEX.S7.1":[false,true,false,false,true,true],"HEX.S7.2":[false,false,true,false,true,true],"HEX.S7.3":[false,false,false,true,true,true],"HEX.S7.4":[false,true,false,false,false,true],"HEX.S7.5":[false,false,true,false,false,true],"HEX.S7.6":[false,false,false,true,false,true],"PULLUP":[false,false,false,false,false,false]}},"INT:MUX.IMUX.CE3":{"bits":[[0,5,59],[0,5,62],[0,4,60],[0,5,60],[0,4,63],[0,4,62]],"values":{"DBL.E7.0":[true,false,false,false,false,true],"DBL.E7.1":[true,false,false,false,true,true],"DBL.W7.1":[true,false,false,false,false,false],"DBL.W7.2":[true,false,false,false,true,false],"HEX.N7.0":[false,false,false,true,true,false],"HEX.N7.1":[false,false,true,false,true,false],"HEX.N7.2":[false,true,false,false,true,false],"HEX.N7.3":[false,false,false,true,false,false],"HEX.N7.4":[false,false,true,false,false,false],"HEX.N7.5":[false,true,false,false,false,false],"HEX.S7.1":[false,true,false,false,true,true],"HEX.S7.2":[false,false,true,false,true,true],"HEX.S7.3":[false,false,false,true,true,true],"HEX.S7.4":[false,true,false,false,false,true],"HEX.S7.5":[false,false,true,false,false,true],"HEX.S7.6":[false,false,false,true,false,true],"PULLUP":[false,false,false,false,false,false]}},"INT:MUX.IMUX.CLK0":{"bits":[[0,5,19],[0,4,16],[0,4,20],[0,5,23],[0,4,23],[0,4,21],[0,4,26],[0,4,24],[0,5,25],[0,5,24]],"values":{"DBL.E3.0":[false,false,false,false,false,true,true,false,false,false],"DBL.E3.1":[false,false,false,false,true,false,true,false,false,false],"DBL.W3.1":[false,false,false,false,true,false,false,true,false,false],"DBL.W3.2":[false,false,false,false,false,true,false,true,false,false],"GCLK0":[true,false,false,false,false,false,true,false,false,false],"GCLK1":[false,true,false,false,false,false,true,false,false,false],"GCLK2":[false,false,true,false,false,false,true,false,false,false],"GCLK3":[false,false,false,true,false,false,true,false,false,false],"GCLK4":[true,false,false,false,false,false,false,true,false,false],"GCLK5":[false,true,false,false,false,false,false,true,false,false],"GCLK6":[false,false,true,false,false,false,false,true,false,false],"GCLK7":[false,false,false,true,false,false,false,true,false,false],"HEX.N4.0":[false,true,false,false,false,false,false,false,false,true],"HEX.N4.1":[false,false,false,true,false,false,false,false,false,true],"HEX.N4.2":[false,false,false,false,false,true,false,false,false,true],"HEX.N4.3":[false,true,false,false,false,false,false,false,true,false],"HEX.N4.4":[false,false,false,true,false,false,false,false,true,false],"HEX.N4.5":[false,false,false,false,true,false,false,false,true,false],"HEX.S4.1":[false,false,false,false,false,true,false,false,true,false],"HEX.S4.2":[false,false,true,false,false,false,false,false,true,false],"HEX.S4.3":[true,false,false,false,false,false,false,false,true,false],"HEX.S4.4":[false,false,false,false,true,false,false,false,false,true],"HEX.S4.5":[false,false,true,false,false,false,false,false,false,true],"HEX.S4.6":[true,false,false,false,false,false,false,false,false,true],"PULLUP":[false,false,false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.CLK1":{"bits":[[0,5,44],[0,4,47],[0,4,43],[0,5,40],[0,4,40],[0,4,42],[0,4,37],[0,4,39],[0,5,38],[0,5,39]],"values":{"DBL.E4.0":[false,false,false,false,false,true,true,false,false,false],"DBL.E4.1":[false,false,false,false,true,false,true,false,false,false],"DBL.W4.1":[false,false,false,false,true,false,false,true,false,false],"DBL.W4.2":[false,false,false,false,false,true,false,true,false,false],"GCLK0":[true,false,false,false,false,false,true,false,false,false],"GCLK1":[false,true,false,false,false,false,true,false,false,false],"GCLK2":[false,false,true,false,false,false,true,false,false,false],"GCLK3":[false,false,false,true,false,false,true,false,false,false],"GCLK4":[true,false,false,false,false,false,false,true,false,false],"GCLK5":[false,true,false,false,false,false,false,true,false,false],"GCLK6":[false,false,true,false,false,false,false,true,false,false],"GCLK7":[false,false,false,true,false,false,false,true,false,false],"HEX.N4.0":[false,true,false,false,false,false,false,false,false,true],"HEX.N4.1":[false,false,false,true,false,false,false,false,false,true],"HEX.N4.2":[false,false,false,false,false,true,false,false,false,true],"HEX.N4.3":[false,true,false,false,false,false,false,false,true,false],"HEX.N4.4":[false,false,false,true,false,false,false,false,true,false],"HEX.N4.5":[false,false,false,false,true,false,false,false,true,false],"HEX.S4.1":[false,false,false,false,false,true,false,false,true,false],"HEX.S4.2":[false,false,true,false,false,false,false,false,true,false],"HEX.S4.3":[true,false,false,false,false,false,false,false,true,false],"HEX.S4.4":[false,false,false,false,true,false,false,false,false,true],"HEX.S4.5":[false,false,true,false,false,false,false,false,false,true],"HEX.S4.6":[true,false,false,false,false,false,false,false,false,true],"PULLUP":[false,false,false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.CLK2":{"bits":[[0,4,19],[0,5,20],[0,5,21],[0,4,25],[0,4,22],[0,5,22],[0,4,17],[0,4,18],[0,5,18],[0,5,17]],"values":{"DBL.E3.0":[false,false,false,false,false,true,true,false,false,false],"DBL.E3.1":[false,false,false,false,true,false,true,false,false,false],"DBL.W3.1":[false,false,false,false,true,false,false,true,false,false],"DBL.W3.2":[false,false,false,false,false,true,false,true,false,false],"GCLK0":[true,false,false,false,false,false,true,false,false,false],"GCLK1":[false,true,false,false,false,false,true,false,false,false],"GCLK2":[false,false,true,false,false,false,true,false,false,false],"GCLK3":[false,false,false,true,false,false,true,false,false,false],"GCLK4":[true,false,false,false,false,false,false,true,false,false],"GCLK5":[false,true,false,false,false,false,false,true,false,false],"GCLK6":[false,false,true,false,false,false,false,true,false,false],"GCLK7":[false,false,false,true,false,false,false,true,false,false],"HEX.N4.0":[false,true,false,false,false,false,false,false,false,true],"HEX.N4.1":[false,false,false,true,false,false,false,false,false,true],"HEX.N4.2":[false,false,false,false,false,true,false,false,false,true],"HEX.N4.3":[false,true,false,false,false,false,false,false,true,false],"HEX.N4.4":[false,false,false,true,false,false,false,false,true,false],"HEX.N4.5":[false,false,false,false,true,false,false,false,true,false],"HEX.S4.1":[false,false,false,false,false,true,false,false,true,false],"HEX.S4.2":[false,false,true,false,false,false,false,false,true,false],"HEX.S4.3":[true,false,false,false,false,false,false,false,true,false],"HEX.S4.4":[false,false,false,false,true,false,false,false,false,true],"HEX.S4.5":[false,false,true,false,false,false,false,false,false,true],"HEX.S4.6":[true,false,false,false,false,false,false,false,false,true],"PULLUP":[false,false,false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.CLK3":{"bits":[[0,4,44],[0,5,43],[0,5,42],[0,4,38],[0,4,41],[0,5,41],[0,4,46],[0,4,45],[0,5,45],[0,5,46]],"values":{"DBL.E4.0":[false,false,false,false,false,true,true,false,false,false],"DBL.E4.1":[false,false,false,false,true,false,true,false,false,false],"DBL.W4.1":[false,false,false,false,true,false,false,true,false,false],"DBL.W4.2":[false,false,false,false,false,true,false,true,false,false],"GCLK0":[true,false,false,false,false,false,true,false,false,false],"GCLK1":[false,true,false,false,false,false,true,false,false,false],"GCLK2":[false,false,true,false,false,false,true,false,false,false],"GCLK3":[false,false,false,true,false,false,true,false,false,false],"GCLK4":[true,false,false,false,false,false,false,true,false,false],"GCLK5":[false,true,false,false,false,false,false,true,false,false],"GCLK6":[false,false,true,false,false,false,false,true,false,false],"GCLK7":[false,false,false,true,false,false,false,true,false,false],"HEX.N4.0":[false,true,false,false,false,false,false,false,false,true],"HEX.N4.1":[false,false,false,true,false,false,false,false,false,true],"HEX.N4.2":[false,false,false,false,false,true,false,false,false,true],"HEX.N4.3":[false,true,false,false,false,false,false,false,true,false],"HEX.N4.4":[false,false,false,true,false,false,false,false,true,false],"HEX.N4.5":[false,false,false,false,true,false,false,false,true,false],"HEX.S4.1":[false,false,false,false,false,true,false,false,true,false],"HEX.S4.2":[false,false,true,false,false,false,false,false,true,false],"HEX.S4.3":[true,false,false,false,false,false,false,false,true,false],"HEX.S4.4":[false,false,false,false,true,false,false,false,false,true],"HEX.S4.5":[false,false,true,false,false,false,false,false,false,true],"HEX.S4.6":[true,false,false,false,false,false,false,false,false,true],"PULLUP":[false,false,false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.DATA0":{"bits":[[0,8,39],[0,9,39],[0,10,39],[0,8,45],[0,10,43],[0,9,41],[0,9,40],[0,9,42]],"values":{"DBL.E6.1":[false,false,false,false,true,true,false,true],"DBL.E6.2":[false,false,false,true,false,true,false,true],"DBL.E7.0":[false,false,false,true,false,false,true,false],"DBL.E7.1":[true,false,false,false,false,false,true,false],"DBL.E7.2":[false,true,false,false,false,false,false,true],"DBL.N6.1":[false,false,true,false,false,true,false,true],"DBL.N6.2":[false,false,true,false,false,false,false,true],"DBL.N7.1":[false,false,true,false,false,true,true,true],"DBL.N7.2":[true,false,false,false,false,true,true,true],"DBL.S6.0":[false,false,false,false,true,true,true,true],"DBL.S6.1":[false,false,false,false,true,false,true,false],"DBL.S6.2":[false,false,true,false,false,false,true,false],"DBL.S7.1":[false,true,false,false,false,true,false,true],"DBL.S7.2":[false,true,false,false,false,true,true,true],"DBL.W6.0":[false,false,false,true,false,false,false,true],"DBL.W6.1":[false,false,false,false,true,false,false,true],"DBL.W6.2":[true,false,false,false,false,true,false,true],"DBL.W7.1":[true,false,false,false,false,false,false,true],"DBL.W7.2":[false,true,false,false,false,false,true,false],"IMUX.FAN.BY2":[false,false,false,true,false,false,false,false],"IMUX.FAN.BY3":[false,false,false,true,false,true,true,true],"OMUX13":[false,false,true,false,false,false,false,false],"OMUX13.E":[false,false,false,true,false,true,true,false],"OMUX14.W":[false,false,false,false,true,true,true,false],"OMUX15.N":[false,false,true,false,false,true,true,false],"OMUX5.S":[true,false,false,false,false,true,true,false],"OMUX5.SW":[true,false,false,false,false,false,false,false],"OMUX7.ES":[false,true,false,false,false,true,true,false],"OUT.FAN0":[false,false,false,false,true,false,false,false],"OUT.FAN7":[false,true,false,false,false,false,false,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.DATA1":{"bits":[[0,10,9],[0,12,11],[0,10,11],[0,11,12],[0,11,7],[0,12,10],[0,12,9],[0,12,8]],"values":{"DBL.E0.0":[false,true,false,false,false,true,false,false],"DBL.E0.1":[false,true,false,false,false,false,true,false],"DBL.E0.2":[false,false,false,false,true,true,false,false],"DBL.E1.1":[true,false,false,false,false,false,true,true],"DBL.E1.2":[false,true,false,false,false,true,false,true],"DBL.N0.1":[false,false,true,false,false,true,false,false],"DBL.N0.2":[false,false,true,false,false,true,false,true],"DBL.N1.1":[false,false,true,false,false,false,false,false],"DBL.N1.2":[false,false,false,true,false,false,false,false],"DBL.S0.0":[true,false,false,false,false,false,false,false],"DBL.S0.1":[false,false,true,false,false,false,true,true],"DBL.S0.2":[false,false,false,true,false,false,true,true],"DBL.S1.1":[false,true,false,false,false,false,false,false],"DBL.S1.2":[false,false,false,false,true,false,true,true],"DBL.W0.0":[false,false,false,false,true,true,false,true],"DBL.W0.1":[true,false,false,false,false,true,false,true],"DBL.W0.2":[false,false,false,true,false,true,false,false],"DBL.W1.1":[false,false,false,true,false,true,false,true],"DBL.W1.2":[false,false,false,false,true,false,true,false],"IMUX.FAN.BY0":[false,false,false,false,true,false,false,false],"IMUX.FAN.BY1":[false,true,false,false,false,true,true,true],"OMUX0.S":[true,false,false,false,false,true,true,true],"OMUX1.W":[true,false,false,false,false,true,false,false],"OMUX10.N":[false,false,false,false,true,true,true,true],"OMUX10.NW":[true,false,false,false,false,false,true,false],"OMUX2":[false,true,false,false,false,false,true,true],"OMUX2.E":[false,false,true,false,false,true,true,true],"OMUX8.EN":[false,false,false,true,false,false,true,false],"OUT.FAN3":[false,false,false,true,false,true,true,true],"OUT.FAN4":[false,false,true,false,false,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.DATA10":{"bits":[[0,12,56],[0,10,50],[0,11,57],[0,12,57],[0,11,52],[0,11,53],[0,11,55],[0,11,54]],"values":{"DBL.E4.1":[false,false,true,false,false,false,true,true],"DBL.E4.2":[false,false,false,true,false,false,true,true],"DBL.E5.0":[false,false,false,false,true,false,true,true],"DBL.E5.1":[false,false,true,false,false,true,false,false],"DBL.E5.2":[false,false,false,false,true,false,false,true],"DBL.N4.1":[false,true,false,false,false,false,t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OMUX2":[false,true,false,false,false,false,true,true],"OMUX2.E":[false,false,true,false,false,true,true,true],"OMUX8.EN":[false,false,false,true,false,false,true,false],"OUT.FAN3":[false,false,false,true,false,true,true,true],"OUT.FAN4":[false,false,true,false,false,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.DATA13":{"bits":[[0,8,50],[0,9,45],[0,10,45],[0,8,51],[0,9,50],[0,9,47],[0,9,46],[0,9,48]],"values":{"DBL.E6.1":[false,false,false,false,true,true,false,true],"DBL.E6.2":[false,false,false,true,false,true,false,true],"DBL.E7.0":[false,false,false,true,false,false,true,false],"DBL.E7.1":[true,false,false,false,false,false,true,false],"DBL.E7.2":[false,true,false,false,false,false,false,true],"DBL.N6.1":[false,false,true,false,false,true,false,true],"DBL.N6.2":[false,false,true,false,false,false,false,true],"DBL.N7.1":[false,false,true,false,false,true,true,true],"DBL.N7.2":[true,false,false,false,false,true,true,true],"DBL.S6.0":[false,false,false,false,true,true,true,true],"DBL.S6.1":[false,false,false,false,true,false,true,false],"DBL.S6.2":[false,false,true,false,false,false,true,false],"DBL.S7.1":[false,true,false,false,false,true,false,true],"DBL.S7.2":[false,true,false,false,false,true,true,true],"DBL.W6.0":[false,false,false,true,false,false,false,true],"DBL.W6.1":[false,false,false,false,true,false,false,true],"DBL.W6.2":[true,false,false,false,false,true,false,true],"DBL.W7.1":[true,false,false,false,false,false,false,true],"DBL.W7.2":[false,true,false,false,false,false,true,false],"IMUX.FAN.BY2":[false,false,false,true,false,false,false,false],"IMUX.FAN.BY3":[false,false,false,true,false,true,true,true],"OMUX13":[false,false,true,false,false,false,false,false],"OMUX13.E":[false,false,false,true,false,true,true,false],"OMUX14.W":[false,false,false,false,true,true,true,false],"OMUX15.N":[false,false,true,false,false,true,true,false],"OMUX5.S":[true,false,false,false,false,true,true,false],"OMUX5.SW":[true,false,false,false,false,false,false,false],"OMUX7.ES":[false,true,false,false,false,true,true,false],"OUT.FAN0":[false,false,false,false,true,false,false,false],"OUT.FAN7":[false,true,false,false,false,false,false,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.DATA14":{"bits":[[0,10,14],[0,12,17],[0,10,17],[0,11,19],[0,11,14],[0,12,14],[0,12,15],[0,12,16]],"values":{"DBL.E0.0":[false,true,false,false,false,true,false,false],"DBL.E0.1":[false,true,false,false,false,false,true,false],"DBL.E0.2":[false,false,false,false,true,true,false,false],"DBL.E1.1":[true,false,false,false,false,false,true,true],"DBL.E1.2":[false,true,false,false,false,true,false,true],"DBL.N0.1":[false,false,true,false,false,true,false,false],"DBL.N0.2":[false,false,true,false,false,true,false,true],"DBL.N1.1":[false,false,true,false,false,false,false,false],"DBL.N1.2":[false,false,false,true,false,false,false,false],"DBL.S0.0":[true,false,false,false,false,false,false,false],"DBL.S0.1":[false,false,true,false,false,false,true,true],"DBL.S0.2":[false,false,false,true,false,false,true,true],"DBL.S1.1":[false,true,false,false,false,false,false,false],"DBL.S1.2":[false,false,false,false,true,false,true,true],"DBL.W0.0":[false,false,false,false,true,true,false,true],"DBL.W0.1":[true,false,false,false,false,true,false,true],"DBL.W0.2":[false,false,false,true,false,true,false,false],"DBL.W1.1":[false,false,false,true,false,true,false,true],"DBL.W1.2":[false,false,false,false,true,false,true,false],"IMUX.FAN.BY0":[false,false,false,false,true,false,false,false],"IMUX.FAN.BY1":[false,true,false,false,false,true,true,true],"OMUX0.S":[true,false,false,false,false,true,true,true],"OMUX1.W":[true,false,false,false,false,true,false,false],"OMUX10.N":[false,false,false,false,true,true,true,true],"OMUX10.NW":[true,false,false,false,false,false,true,false],"OMUX2":[false,true,false,false,false,false,true,true],"OMUX2.E":[false,false,true,false,false,true,true,true],"OMUX8.EN":[false,false,false,true,false,false,true,false],"OUT.FAN3":[false,false,false,true,false,true,true,true],"OUT.FAN4":[false,false,true,false,false,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.DATA15":{"bits":[[0,8,58],[0,9,58],[0,10,59],[0,8,63],[0,10,62],[0,9,61],[0,9,62],[0,9,60]],"values":{"DBL.E6.1":[false,false,false,false,true,true,false,true],"DBL.E6.2":[false,false,false,true,false,true,false,true],"DBL.E7.0":[false,false,false,true,false,false,true,false],"DBL.E7.1":[true,false,false,false,false,false,true,false],"DBL.E7.2":[false,true,false,false,false,false,false,true],"DBL.N6.1":[false,false,true,false,false,true,false,true],"DBL.N6.2":[false,false,true,false,false,false,false,true],"DBL.N7.1":[false,false,true,false,false,true,true,true],"DBL.N7.2":[true,false,false,false,false,true,true,true],"DBL.S6.0":[false,false,false,false,true,true,true,true],"DBL.S6.1":[false,false,false,false,true,false,true,false],"DBL.S6.2":[false,fal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alse,false,false,false,false]}},"INT:MUX.IMUX.DATA18":{"bits":[[0,10,55],[0,9,56],[0,10,53],[0,8,52],[0,9,51],[0,8,55],[0,8,53],[0,8,54]],"values":{"DBL.E6.1":[false,false,false,false,true,true,false,true],"DBL.E6.2":[false,false,false,true,false,true,false,true],"DBL.E7.0":[false,false,false,true,false,false,true,false],"DBL.E7.1":[true,false,false,false,false,false,true,false],"DBL.E7.2":[false,true,false,false,false,false,false,true],"DBL.N6.1":[false,false,true,false,false,true,false,true],"DBL.N6.2":[false,false,true,false,false,false,false,true],"DBL.N7.1":[false,false,true,false,false,true,true,true],"DBL.N7.2":[true,false,false,false,false,true,true,true],"DBL.S6.0":[false,false,false,false,true,true,true,true],"DBL.S6.1":[false,false,false,false,true,false,true,false],"DBL.S6.2":[false,false,true,false,false,false,true,false],"DBL.S7.1":[false,true,false,false,false,true,false,true],"DBL.S7.2":[false,true,false,false,false,true,true,true],"DBL.W6.0":[false,false,false,true,false,false,false,true],"DBL.W6.1":[false,false,false,false,true,false,false,true],"DBL.W6.2":[true,false,false,false,false,true,false,true],"DBL.W7.1":[true,false,false,false,false,false,false,true],"DBL.W7.2":[false,true,false,false,false,false,true,false],"IMUX.FAN.BY2":[false,false,false,true,false,false,false,false],"IMUX.FAN.BY3":[false,false,false,true,false,true,true,true],"OMUX13":[false,false,true,false,false,false,false,false],"OMUX13.E":[false,false,false,true,false,true,true,false],"OMUX14.W":[false,false,false,false,true,true,true,false],"OMUX15.N":[false,false,true,false,false,true,true,false],"OMUX5.S":[true,false,false,false,false,true,true,false],"OMUX5.SW":[true,false,false,false,false,false,false,false],"OMUX7.ES":[false,true,false,false,false,true,true,false],"OUT.FAN0":[false,false,false,false,true,false,false,false],"OUT.FAN7":[false,true,false,false,false,false,false,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.DATA19":{"bits":[[0,12,24],[0,12,18],[0,10,25],[0,10,21],[0,11,24],[0,11,23],[0,11,21],[0,11,22]],"values":{"DBL.E0.0":[false,true,false,false,false,true,false,false],"DBL.E0.1":[false,true,false,false,false,false,true,false],"DBL.E0.2":[false,false,false,false,true,true,false,false],"DBL.E1.1":[true,false,false,false,false,false,true,true],"DBL.E1.2":[false,true,false,false,false,true,false,true],"DBL.N0.1":[false,false,true,false,false,true,false,false],"DBL.N0.2":[false,false,true,false,false,true,false,true],"DBL.N1.1":[false,false,true,false,false,false,false,false],"DBL.N1.2":[false,false,false,true,false,false,false,false],"DBL.S0.0":[true,false,false,false,false,false,false,false],"DBL.S0.1":[false,false,true,false,false,false,true,true],"DBL.S0.2":[false,false,false,true,false,false,true,true],"DBL.S1.1":[false,true,false,false,false,false,false,false],"DBL.S1.2":[false,false,false,false,true,false,true,true],"DBL.W0.0":[false,false,false,false,true,true,false,true],"DBL.W0.1":[true,false,false,false,false,true,false,true],"DBL.W0.2":[false,false,false,true,false,true,false,false],"DBL.W1.1":[false,false,false,true,false,true,false,true],"DBL.W1.2":[false,false,false,false,true,false,true,false],"IMUX.FAN.BY0":[false,false,false,false,true,false,false,false],"IMUX.FAN.BY1":[false,true,false,false,false,true,true,true],"OMUX0.S":[true,false,false,false,false,true,true,true],"OMUX1.W":[true,false,false,false,false,true,false,false],"OMUX10.N":[false,false,false,false,true,true,true,true],"OMUX10.NW":[true,false,false,false,false,false,true,false],"OMUX2":[false,true,false,false,false,false,true,true],"OMUX2.E":[false,false,true,false,false,true,true,true],"OMUX8.EN":[false,false,false,true,false,false,true,false],"OUT.FAN3":[false,false,false,true,false,true,true,true],"OUT.FAN4":[false,false,true,false,false,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.DATA2":{"bits":[[0,8,56],[0,9,52],[0,10,51],[0,8,57],[0,9,57],[0,9,55],[0,9,53],[0,9,54]],"values":{"DBL.E6.1":[false,false,false,false,true,true,false,true],"DBL.E6.2":[false,false,false,true,false,true,false,true],"DBL.E7.0":[false,false,false,true,false,false,true,false],"DBL.E7.1":[true,false,false,false,false,false,true,false],"DBL.E7.2":[false,true,false,false,false,false,false,true],"DBL.N6.1":[false,false,true,false,false,true,false,true],"DBL.N6.2":[false,false,true,false,false,false,false,true],"DBL.N7.1":[false,false,true,false,false,true,true,true],"DBL.N7.2":[true,false,false,false,false,true,true,true],"DBL.S6.0":[false,false,false,false,true,true,true,true],"DBL.S6.1":[false,false,false,false,true,false,true,false],"DBL.S6.2":[false,false,true,false,false,false,true,false],"DBL.S7.1":[false,true,false,false,false,true,false,true],"DBL.S7.2":[false,true,false,false,false,true,true,true],"DBL.W6.0":[false,false,false,true,false,false,false,true],"DBL.W6.1":[false,false,false,false,true,false,false,true],"DBL.W6.2":[true,false,false,false,false,tru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ue],"DBL.E3.1":[false,true,false,false,false,true,true,false],"DBL.E3.2":[false,false,false,false,true,false,true,true],"DBL.N2.1":[true,false,false,false,false,false,false,true],"DBL.N2.2":[true,false,false,false,false,false,true,true],"DBL.N3.1":[true,false,false,false,false,false,false,false],"DBL.N3.2":[false,true,false,false,false,false,false,false],"DBL.S2.0":[false,false,false,true,false,false,false,false],"DBL.S2.1":[false,false,false,false,true,false,false,false],"DBL.S2.2":[true,false,false,false,false,true,true,false],"DBL.S3.1":[false,false,false,false,true,false,false,true],"DBL.S3.2":[false,false,true,false,false,false,false,false],"DBL.W2.0":[false,false,false,false,true,true,false,false],"DBL.W2.1":[false,false,false,true,false,true,true,false],"DBL.W2.2":[false,true,false,false,false,false,false,true],"DBL.W3.1":[false,true,false,false,false,false,true,true],"DBL.W3.2":[false,false,true,false,false,true,true,false],"IMUX.FAN.BX2":[false,false,false,false,true,true,true,false],"IMUX.FAN.BX3":[false,false,true,false,false,true,false,false],"OMUX12.N":[false,false,false,true,false,true,false,false],"OMUX12.NE":[false,false,true,false,false,true,true,true],"OMUX14.WN":[false,true,false,false,false,true,true,true],"OMUX4.S":[true,false,false,false,false,true,false,false],"OMUX6":[true,false,false,false,false,true,true,true],"OMUX6.W":[false,true,false,false,false,true,false,false],"OMUX7.E":[false,false,true,false,false,false,true,true],"OUT.FAN2":[false,false,false,true,false,true,true,true],"OUT.FAN5":[false,false,false,false,true,true,true,true],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.DATA23":{"bits":[[0,10,60],[0,11,59],[0,10,56],[0,12,59],[0,11,63],[0,12,62],[0,12,61],[0,12,60]],"values":{"DBL.E4.1":[false,false,true,false,false,false,true,true],"DBL.E4.2":[false,false,false,true,false,false,true,true],"DBL.E5.0":[false,false,false,false,true,false,true,true],"DBL.E5.1":[false,false,true,false,false,true,false,false],"DBL.E5.2":[false,false,false,false,true,false,false,true],"DBL.N4.1":[false,true,false,false,false,false,true,true],"DBL.N4.2":[false,false,false,true,false,false,false,false],"DBL.N5.1":[false,true,false,false,false,true,true,true],"DBL.N5.2":[true,false,false,false,false,true,true,true],"DBL.S4.0":[false,false,true,false,false,true,true,true],"DBL.S4.1":[false,true,false,false,false,true,false,false],"DBL.S4.2":[false,false,true,false,false,true,true,false],"DBL.S5.1":[false,false,false,false,true,true,true,true],"DBL.S5.2":[false,true,false,false,false,false,false,true],"DBL.W4.0":[false,false,false,true,false,false,false,true],"DBL.W4.1":[false,false,false,false,true,true,true,false],"DBL.W4.2":[true,false,false,false,false,false,true,true],"DBL.W5.1":[true,false,false,false,false,false,false,true],"DBL.W5.2":[false,false,false,true,false,true,true,false],"IMUX.FAN.BX0":[false,false,false,false,true,true,false,false],"IMUX.FAN.BX1":[false,false,true,false,false,false,false,false],"OMUX1.WS":[true,false,false,false,false,true,false,false],"OMUX11.N":[false,false,false,true,false,true,false,false],"OMUX3.S":[true,false,false,false,false,false,false,false],"OMUX3.SE":[false,true,false,false,false,true,true,false],"OMUX8.E":[false,false,true,false,false,false,false,true],"OMUX9":[false,true,false,false,false,false,false,false],"OMUX9.W":[true,false,false,false,false,true,true,false],"OUT.FAN1":[false,false,false,true,false,true,true,true],"OUT.FAN6":[false,false,false,false,true,false,false,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.DATA24":{"bits":[[0,12,44],[0,10,40],[0,11,38],[0,12,40],[0,11,43],[0,12,43],[0,12,41],[0,12,42]],"values":{"DBL.E4.1":[false,false,true,false,false,false,true,true],"DBL.E4.2":[false,false,false,true,false,false,true,true],"DBL.E5.0":[false,false,false,false,true,false,true,true],"DBL.E5.1":[false,false,true,false,false,true,false,false],"DBL.E5.2":[false,false,false,false,true,false,false,true],"DBL.N4.1":[false,true,false,false,false,false,true,true],"DBL.N4.2":[false,false,false,true,false,false,false,false],"DBL.N5.1":[false,true,false,false,false,true,true,true],"DBL.N5.2":[true,false,false,false,false,true,true,true],"DBL.S4.0":[false,false,true,false,false,true,true,true],"DBL.S4.1":[false,true,false,false,false,true,false,false],"DBL.S4.2":[false,false,true,false,false,true,true,false],"DBL.S5.1":[false,false,false,false,true,true,true,true],"DBL.S5.2":[false,true,false,false,false,false,false,true],"DBL.W4.0":[false,false,false,true,false,false,false,true],"DBL.W4.1":[false,false,false,false,true,true,true,false],"DBL.W4.2":[true,false,false,false,false,false,true,true],"DBL.W5.1":[true,false,false,false,false,false,false,true],"DBL.W5.2":[false,false,false,true,false,true,true,false],"IMUX.FAN.BX0":[false,false,false,false,true,true,false,false],"IMUX.FAN.BX1":[false,false,true,false,false,false,false,false],"OMUX1.WS":[true,false,false,false,false,true,false,false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,true,false,false,false,false,false,false],"DBL.S2.0":[false,false,false,true,false,false,false,false],"DBL.S2.1":[false,false,false,false,true,false,false,false],"DBL.S2.2":[true,false,false,false,false,true,true,false],"DBL.S3.1":[false,false,false,false,true,false,false,true],"DBL.S3.2":[false,false,true,false,false,false,false,false],"DBL.W2.0":[false,false,false,false,true,true,false,false],"DBL.W2.1":[false,false,false,true,false,true,true,false],"DBL.W2.2":[false,true,false,false,false,false,false,true],"DBL.W3.1":[false,true,false,false,false,false,true,true],"DBL.W3.2":[false,false,true,false,false,true,true,false],"IMUX.FAN.BX2":[false,false,false,false,true,true,true,false],"IMUX.FAN.BX3":[false,false,true,false,false,true,false,false],"OMUX12.N":[false,false,false,true,false,true,false,false],"OMUX12.NE":[false,false,true,false,false,true,true,true],"OMUX14.WN":[false,true,false,false,false,true,true,true],"OMUX4.S":[true,false,false,false,false,true,false,false],"OMUX6":[true,false,false,false,false,true,true,true],"OMUX6.W":[false,true,false,false,false,true,false,false],"OMUX7.E":[false,false,true,false,false,false,true,true],"OUT.FAN2":[false,false,false,true,false,true,true,true],"OUT.FAN5":[false,false,false,false,true,true,true,true],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.DATA28":{"bits":[[0,12,5],[0,12,0],[0,10,5],[0,10,0],[0,11,5],[0,11,1],[0,11,3],[0,11,2]],"values":{"DBL.E0.0":[false,true,false,false,false,true,false,false],"DBL.E0.1":[false,true,false,false,false,false,true,false],"DBL.E0.2":[false,false,false,false,true,true,false,false],"DBL.E1.1":[true,false,false,false,false,false,true,true],"DBL.E1.2":[false,true,false,false,false,true,false,true],"DBL.N0.1":[false,false,true,false,false,true,false,false],"DBL.N0.2":[false,false,true,false,false,true,false,true],"DBL.N1.1":[false,false,true,false,false,false,false,false],"DBL.N1.2":[false,false,false,true,false,false,false,false],"DBL.S0.0":[true,false,false,false,false,false,false,false],"DBL.S0.1":[false,false,true,false,false,false,true,true],"DBL.S0.2":[false,false,false,true,false,false,true,true],"DBL.S1.1":[false,true,false,false,false,false,false,false],"DBL.S1.2":[false,false,false,false,true,false,true,true],"DBL.W0.0":[false,false,false,false,true,true,false,true],"DBL.W0.1":[true,false,false,false,false,true,false,true],"DBL.W0.2":[false,false,false,true,false,true,false,false],"DBL.W1.1":[false,false,false,true,false,true,false,true],"DBL.W1.2":[false,false,false,false,true,false,true,false],"IMUX.FAN.BY0":[false,false,false,false,true,false,false,false],"IMUX.FAN.BY1":[false,true,false,false,false,true,true,true],"OMUX0.S":[true,false,false,false,false,true,true,true],"OMUX1.W":[true,false,false,false,false,true,false,false],"OMUX10.N":[false,false,false,false,true,true,true,true],"OMUX10.NW":[true,false,false,false,false,false,true,false],"OMUX2":[false,true,false,false,false,false,true,true],"OMUX2.E":[false,false,true,false,false,true,true,true],"OMUX8.EN":[false,false,false,true,false,false,true,false],"OUT.FAN3":[false,false,false,true,false,true,true,true],"OUT.FAN4":[false,false,true,false,false,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.DATA29":{"bits":[[0,10,48],[0,9,49],[0,10,47],[0,8,46],[0,9,44],[0,8,47],[0,8,49],[0,8,48]],"values":{"DBL.E6.1":[false,false,false,false,true,true,false,true],"DBL.E6.2":[false,false,false,true,false,true,false,true],"DBL.E7.0":[false,false,false,true,false,false,true,false],"DBL.E7.1":[true,false,false,false,false,false,true,false],"DBL.E7.2":[false,true,false,false,false,false,false,true],"DBL.N6.1":[false,false,true,false,false,true,false,true],"DBL.N6.2":[false,false,true,false,false,false,false,true],"DBL.N7.1":[false,false,true,false,false,true,true,true],"DBL.N7.2":[true,false,false,false,false,true,true,true],"DBL.S6.0":[false,false,false,false,true,true,true,true],"DBL.S6.1":[false,false,false,false,true,false,true,false],"DBL.S6.2":[false,false,true,false,false,false,true,false],"DBL.S7.1":[false,true,false,false,false,true,false,true],"DBL.S7.2":[false,true,false,false,false,true,true,true],"DBL.W6.0":[false,false,false,true,false,false,false,true],"DBL.W6.1":[false,false,false,false,true,false,false,true],"DBL.W6.2":[true,false,false,false,false,true,false,true],"DBL.W7.1":[true,false,false,false,false,false,false,true],"DBL.W7.2":[false,true,false,false,false,false,true,false],"IMUX.FAN.BY2":[false,false,false,true,false,false,false,false],"IMUX.FAN.BY3":[false,false,false,true,false,true,true,true],"OMUX13":[false,false,true,false,false,false,false,false],"OMUX13.E":[false,false,false,true,false,true,true,false],"OMUX14.W":[false,false,false,false,true,true,true,false],"OMUX15.N":[false,false,true,false,false,true,true,false],"OMUX5.S":[true,false,false,false,false,true,true,false],"OMUX5.SW":[true,false,false,false,false,false,false,false],"OMUX7.ES":[false,true,false,false,false,true,true,false],"OUT.FAN0":[false,false,false,false,true,false,false,false],"OUT.FAN7":[false,true,false,false,false,false,false,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.DATA3":{"bits":[[0,12,19],[0,12,23],[0,10,23],[0,11,25],[0,11,20],[0,12,20],[0,12,21],[0,12,22]],"values":{"DBL.E0.0":[false,true,false,false,false,true,false,false],"DBL.E0.1":[false,true,false,false,false,false,true,false],"DBL.E0.2":[false,false,false,false,true,true,false,false],"DBL.E1.1":[true,false,false,false,false,false,true,true],"DBL.E1.2":[false,true,false,false,false,true,false,true],"DBL.N0.1":[false,false,true,false,false,true,false,false],"DBL.N0.2":[false,false,true,false,false,true,false,true],"DBL.N1.1":[false,false,true,false,false,false,false,false],"DBL.N1.2":[false,false,false,true,false,false,false,false],"DBL.S0.0":[true,false,false,false,false,false,false,false],"DBL.S0.1":[false,false,true,false,false,false,true,true],"DBL.S0.2":[false,false,false,true,false,false,true,true],"DBL.S1.1":[false,true,false,false,false,false,false,false],"DBL.S1.2":[false,false,false,false,true,false,true,true],"DBL.W0.0":[false,false,false,false,true,true,false,true],"DBL.W0.1":[true,false,false,false,false,true,false,true],"DBL.W0.2":[false,false,false,true,false,true,false,false],"DBL.W1.1":[false,false,false,true,false,true,false,true],"DBL.W1.2":[false,false,false,false,true,false,true,false],"IMUX.FAN.BY0":[false,false,false,false,true,false,false,false],"IMUX.FAN.BY1":[false,true,false,false,false,true,true,true],"OMUX0.S":[true,false,false,false,false,true,true,true],"OMUX1.W":[true,false,false,false,false,true,false,false],"OMUX10.N":[false,false,false,false,true,true,true,true],"OMUX10.NW":[true,false,false,false,false,false,true,false],"OMUX2":[false,true,false,false,false,false,true,true],"OMUX2.E":[false,false,true,false,false,true,true,true],"OMUX8.EN":[false,false,false,true,false,false,true,false],"OUT.FAN3":[false,false,false,true,false,true,true,true],"OUT.FAN4":[false,false,true,false,false,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.DATA30":{"bits":[[0,12,13],[0,12,12],[0,10,19],[0,11,13],[0,11,18],[0,11,17],[0,11,15],[0,11,16]],"values":{"DBL.E0.0":[false,true,false,false,false,true,false,false],"DBL.E0.1":[false,true,false,false,false,false,true,false],"DBL.E0.2":[false,false,false,false,true,true,false,false],"DBL.E1.1":[true,false,false,false,false,false,true,true],"DBL.E1.2":[false,true,false,false,false,true,false,true],"DBL.N0.1":[false,false,true,false,false,true,false,false],"DBL.N0.2":[false,false,true,false,false,true,false,true],"DBL.N1.1":[false,false,true,false,false,false,false,false],"DBL.N1.2":[false,false,false,true,false,false,false,false],"DBL.S0.0":[true,false,false,false,false,false,false,false],"DBL.S0.1":[false,false,true,false,false,false,true,true],"DBL.S0.2":[false,false,false,true,false,false,true,true],"DBL.S1.1":[false,true,false,false,false,false,false,false],"DBL.S1.2":[false,false,false,false,true,false,true,true],"DBL.W0.0":[false,false,false,false,true,true,false,true],"DBL.W0.1":[true,false,false,false,false,true,false,true],"DBL.W0.2":[false,false,false,true,false,true,false,false],"DBL.W1.1":[false,false,false,true,false,true,false,true],"DBL.W1.2":[false,false,false,false,true,false,true,false],"IMUX.FAN.BY0":[false,false,false,false,true,false,false,false],"IMUX.FAN.BY1":[false,true,false,false,false,true,true,true],"OMUX0.S":[true,false,false,false,false,true,true,true],"OMUX1.W":[true,false,false,false,false,true,false,false],"OMUX10.N":[false,false,false,false,true,true,true,true],"OMUX10.NW":[true,false,false,false,false,false,true,false],"OMUX2":[false,true,false,false,false,false,true,true],"OMUX2.E":[false,false,true,false,false,true,true,true],"OMUX8.EN":[false,false,false,true,false,false,true,false],"OUT.FAN3":[false,false,false,true,false,true,true,true],"OUT.FAN4":[false,false,true,false,false,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.DATA31":{"bits":[[0,10,61],[0,9,63],[0,9,59],[0,8,59],[0,10,57],[0,8,61],[0,8,62],[0,8,60]],"values":{"DBL.E6.1":[false,false,false,false,true,true,false,true],"DBL.E6.2":[false,false,false,true,false,true,false,true],"DBL.E7.0":[false,false,false,true,false,false,true,false],"DBL.E7.1":[true,false,false,false,false,false,true,false],"DBL.E7.2":[false,true,false,false,false,false,false,true],"DBL.N6.1":[false,false,true,false,false,true,false,true],"DBL.N6.2":[false,false,true,false,false,false,false,true],"DBL.N7.1":[false,false,true,false,false,true,true,true],"DBL.N7.2":[true,false,false,false,false,true,true,true],"DBL.S6.0":[false,false,false,false,true,true,true,true],"DBL.S6.1":[false,false,false,false,true,false,true,false],"DBL.S6.2":[false,false,true,false,false,false,true,false],"DBL.S7.1":[false,true,false,false,false,true,false,true],"DBL.S7.2":[false,true,false,false,false,t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,false,true,false,false,true,false,true],"DBL.N6.2":[false,false,true,false,false,false,false,true],"DBL.N7.1":[false,false,true,false,false,true,true,true],"DBL.N7.2":[true,false,false,false,false,true,true,true],"DBL.S6.0":[false,false,false,false,true,true,true,true],"DBL.S6.1":[false,false,false,false,true,false,true,false],"DBL.S6.2":[false,false,true,false,false,false,true,false],"DBL.S7.1":[false,true,false,false,false,true,false,true],"DBL.S7.2":[false,true,false,false,false,true,true,true],"DBL.W6.0":[false,false,false,true,false,false,false,true],"DBL.W6.1":[false,false,false,false,true,false,false,true],"DBL.W6.2":[true,false,false,false,false,true,false,true],"DBL.W7.1":[true,false,false,false,false,false,false,true],"DBL.W7.2":[false,true,false,false,false,false,true,false],"IMUX.FAN.BY2":[false,false,false,true,false,false,false,false],"IMUX.FAN.BY3":[false,false,false,true,false,true,true,true],"OMUX13":[false,false,true,false,false,false,false,false],"OMUX13.E":[false,false,false,true,false,true,true,false],"OMUX14.W":[false,false,false,false,true,true,true,false],"OMUX15.N":[false,false,true,false,false,true,true,false],"OMUX5.S":[true,false,false,false,false,true,true,false],"OMUX5.SW":[true,false,false,false,false,false,false,false],"OMUX7.ES":[false,true,false,false,false,true,true,false],"OUT.FAN0":[false,false,false,false,true,false,false,false],"OUT.FAN7":[false,true,false,false,false,false,false,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.FAN.BX2":{"bits":[[0,12,30],[0,12,26],[0,10,29],[0,11,31],[0,11,30],[0,12,27],[0,12,28],[0,12,29]],"values":{"DBL.E0.0":[false,true,false,false,false,true,false,false],"DBL.E0.1":[false,true,false,false,false,false,true,false],"DBL.E0.2":[false,false,false,false,true,true,false,false],"DBL.E1.1":[true,false,false,false,false,false,true,true],"DBL.E1.2":[false,true,false,false,false,true,false,true],"DBL.N0.1":[false,false,true,false,false,true,false,false],"DBL.N0.2":[false,false,true,false,false,true,false,true],"DBL.N1.1":[false,false,true,false,false,false,false,false],"DBL.N1.2":[false,false,false,true,false,false,false,false],"DBL.S0.0":[true,false,false,false,false,false,false,false],"DBL.S0.1":[false,false,true,false,false,false,true,true],"DBL.S0.2":[false,false,false,true,false,false,true,true],"DBL.S1.1":[false,true,false,false,false,false,false,false],"DBL.S1.2":[false,false,false,false,true,false,true,true],"DBL.W0.0":[false,false,false,false,true,true,false,true],"DBL.W0.1":[true,false,false,false,false,true,false,true],"DBL.W0.2":[false,false,false,true,false,true,false,false],"DBL.W1.1":[false,false,false,true,false,true,false,true],"DBL.W1.2":[false,false,false,false,true,false,true,false],"IMUX.FAN.BY0":[false,false,false,false,true,false,false,false],"IMUX.FAN.BY1":[false,true,false,false,false,true,true,true],"OMUX0.S":[true,false,false,false,false,true,true,true],"OMUX1.W":[true,false,false,false,false,true,false,false],"OMUX10.N":[false,false,false,false,true,true,true,true],"OMUX10.NW":[true,false,false,false,false,false,true,false],"OMUX2":[false,true,false,false,false,false,true,true],"OMUX2.E":[false,false,true,false,false,true,true,true],"OMUX8.EN":[false,false,false,true,false,false,true,false],"OUT.FAN3":[false,false,false,true,false,true,true,true],"OUT.FAN4":[false,false,true,false,false,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.FAN.BX3":{"bits":[[0,8,38],[0,9,37],[0,10,36],[0,8,32],[0,10,33],[0,9,34],[0,9,36],[0,9,35]],"values":{"DBL.E6.1":[false,false,false,false,true,true,false,true],"DBL.E6.2":[false,false,false,true,false,true,false,true],"DBL.E7.0":[false,false,false,true,false,false,true,false],"DBL.E7.1":[true,false,false,false,false,false,true,false],"DBL.E7.2":[false,true,false,false,false,false,false,true],"DBL.N6.1":[false,false,true,false,false,true,false,true],"DBL.N6.2":[false,false,true,false,false,false,false,true],"DBL.N7.1":[false,false,true,false,false,true,true,true],"DBL.N7.2":[true,false,false,false,false,true,true,true],"DBL.S6.0":[false,false,false,false,true,true,true,true],"DBL.S6.1":[false,false,false,false,true,false,true,false],"DBL.S6.2":[false,false,true,false,false,false,true,false],"DBL.S7.1":[false,true,false,false,false,true,false,true],"DBL.S7.2":[false,true,false,false,false,true,true,true],"DBL.W6.0":[false,false,false,true,false,false,false,true],"DBL.W6.1":[false,false,false,false,true,false,false,true],"DBL.W6.2":[true,false,false,false,false,true,false,true],"DBL.W7.1":[true,false,false,false,false,false,false,true],"DBL.W7.2":[false,true,false,false,false,false,true,false],"IMUX.FAN.BY2":[false,false,false,true,false,false,false,false],"IMUX.FAN.BY3":[false,false,false,true,false,true,true,true],"OMUX13":[false,false,true,false,false,false,false,false],"OMUX13.E":[false,false,false,true,false,true,true,false],"OMUX14.W":[false,false,false,false,true,true,true,false],"OMUX15.N":[false,false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,"values":{"DBL.E0.0":[true,false,false,false,false,true],"DBL.E0.1":[true,false,false,false,false,false],"DBL.W0.1":[true,false,false,false,true,false],"DBL.W0.2":[true,false,false,false,true,true],"HEX.N0.0":[false,true,false,false,true,false],"HEX.N0.1":[false,false,true,false,true,false],"HEX.N0.2":[false,false,false,true,true,false],"HEX.N0.3":[false,true,false,false,true,true],"HEX.N0.4":[false,false,true,false,true,true],"HEX.N0.5":[false,false,false,true,true,true],"HEX.S0.1":[false,true,false,false,false,true],"HEX.S0.2":[false,false,true,false,false,true],"HEX.S0.3":[false,false,false,true,false,true],"HEX.S0.4":[false,true,false,false,false,false],"HEX.S0.5":[false,false,true,false,false,false],"HEX.S0.6":[false,false,false,true,false,false],"PULLUP":[false,false,false,false,false,false]}},"INT:MUX.IMUX.SR3":{"bits":[[0,5,11],[0,5,10],[0,4,10],[0,5,8],[0,4,12],[0,4,13]],"values":{"DBL.E1.0":[true,false,false,false,false,true],"DBL.E1.1":[true,false,false,false,false,false],"DBL.W1.1":[true,false,false,false,true,false],"DBL.W1.2":[true,false,false,false,true,true],"HEX.N0.0":[false,true,false,false,true,false],"HEX.N0.1":[false,false,true,false,true,false],"HEX.N0.2":[false,false,false,true,true,false],"HEX.N0.3":[false,true,false,false,true,true],"HEX.N0.4":[false,false,true,false,true,true],"HEX.N0.5":[false,false,false,true,true,true],"HEX.S0.1":[false,true,false,false,false,true],"HEX.S0.2":[false,false,true,false,false,true],"HEX.S0.3":[false,false,false,true,false,true],"HEX.S0.4":[false,true,false,false,false,false],"HEX.S0.5":[false,false,true,false,false,false],"HEX.S0.6":[false,false,false,true,false,false],"PULLUP":[false,false,false,false,false,false]}},"INT:MUX.LH.0":{"bits":[[0,18,40],[0,18,41],[0,18,38]],"values":{"DBL.E4.1":[false,true,false],"DBL.W4.1":[true,false,false],"NONE":[false,false,false],"OMUX11":[false,true,true],"OMUX4.S":[true,false,true]}},"INT:MUX.LH.6":{"bits":[[0,18,23],[0,18,22],[0,18,25]],"values":{"DBL.E3.1":[false,true,false],"DBL.W3.1":[false,true,true],"NONE":[false,false,false],"OMUX15.N":[true,false,true],"OMUX4":[true,false,false]}},"INT:MUX.LV.0":{"bits":[[0,18,0],[0,18,6],[0,18,1],[0,18,7],[0,18,8]],"values":{"DBL.E2.1":[false,true,false,true,false],"DBL.W1.1":[false,false,true,true,true],"HEX.E0.1":[true,false,false,false,true],"HEX.E0.2":[false,false,true,true,false],"HEX.E0.3":[false,true,false,true,true],"HEX.E0.4":[true,false,false,true,true],"HEX.E0.5":[true,false,false,false,false],"HEX.E0.6":[false,false,true,false,false],"NONE":[false,false,false,false,false],"OMUX0":[true,false,false,true,false],"OMUX2.E":[false,true,false,false,false]}},"INT:MUX.LV.6":{"bits":[[0,18,63],[0,18,57],[0,18,62],[0,18,56],[0,18,55]],"values":{"DBL.E7.1":[true,false,false,true,false],"DBL.W7.1":[false,true,false,false,false],"HEX.W6.0":[false,false,true,true,false],"HEX.W6.1":[false,false,true,false,false],"HEX.W6.2":[true,false,false,false,true],"HEX.W6.3":[false,true,false,true,false],"HEX.W6.4":[true,false,false,true,true],"HEX.W6.5":[false,false,true,true,true],"NONE":[false,false,false,false,false],"OMUX15":[false,true,false,true,true],"OMUX9.W":[true,false,false,false,false]}},"INT:MUX.OMUX0":{"bits":[[0,6,5],[0,6,2],[0,7,4],[0,6,3],[0,7,7],[0,7,0],[0,6,7],[0,6,6]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}},"INT:MUX.OMUX1":{"bits":[[0,7,5],[0,7,2],[0,7,3],[0,6,4],[0,7,6],[0,7,1],[0,6,0],[0,6,1]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}},"INT:MUX.OMUX10":{"bits":[[0,6,42],[0,6,45],[0,7,43],[0,6,44],[0,7,40],[0,7,47],[0,6,40],[0,6,41]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}},"INT:MUX.OMUX11":{"bits":[[0,7,42],[0,7,45],[0,7,44],[0,6,43],[0,7,41],[0,7,46],[0,6,47],[0,6,46]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}},"INT:MUX.OMUX12":{"bits":[[0,6,53],[0,6,50],[0,7,52],[0,6,51],[0,7,55],[0,7,48],[0,6,55],[0,6,54]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}},"INT:MUX.OMUX13":{"bits":[[0,7,53],[0,7,50],[0,7,51],[0,6,52],[0,7,54],[0,7,49],[0,6,48],[0,6,49]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}},"INT:MUX.OMUX14":{"bits":[[0,6,58],[0,6,61],[0,7,59],[0,6,60],[0,7,56],[0,7,63],[0,6,56],[0,6,57]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}},"INT:MUX.OMUX15":{"bits":[[0,7,58],[0,7,61],[0,7,60],[0,6,59],[0,7,57],[0,7,62],[0,6,63],[0,6,62]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}},"INT:MUX.OMUX2":{"bits":[[0,6,10],[0,6,13],[0,7,11],[0,6,12],[0,7,8],[0,7,15],[0,6,8],[0,6,9]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}},"INT:MUX.OMUX3":{"bits":[[0,7,10],[0,7,13],[0,7,12],[0,6,11],[0,7,9],[0,7,14],[0,6,15],[0,6,14]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}},"INT:MUX.OMUX4":{"bits":[[0,6,21],[0,6,18],[0,7,20],[0,6,19],[0,7,23],[0,7,16],[0,6,23],[0,6,22]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}},"INT:MUX.OMUX5":{"bits":[[0,7,21],[0,7,18],[0,7,19],[0,6,20],[0,7,22],[0,7,17],[0,6,16],[0,6,17]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}},"INT:MUX.OMUX6":{"bits":[[0,6,26],[0,6,29],[0,7,27],[0,6,28],[0,7,24],[0,7,31],[0,6,24],[0,6,25]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}},"INT:MUX.OMUX7":{"bits":[[0,7,26],[0,7,29],[0,7,28],[0,6,27],[0,7,25],[0,7,30],[0,6,31],[0,6,30]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}},"INT:MUX.OMUX8":{"bits":[[0,6,37],[0,6,34],[0,7,36],[0,6,35],[0,7,39],[0,7,32],[0,6,39],[0,6,38]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}},"INT:MUX.OMUX9":{"bits":[[0,7,37],[0,7,34],[0,7,35],[0,6,36],[0,7,38],[0,7,33],[0,6,32],[0,6,33]],"values":{"NONE":[false,false,false,false,false,false,false,false],"OUT.FAN0":[true,false,false,false,false,false,true,false],"OUT.FAN1":[false,true,false,false,false,false,false,false],"OUT.FAN2":[false,false,true,false,false,false,false,false],"OUT.FAN3":[false,false,false,true,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false,false],"OUT.FAN5":[false,false,false,false,true,false,false,false],"OUT.FAN6":[false,false,false,false,false,true,false,true],"OUT.FAN7":[false,false,false,false,false,true,true,true],"OUT.SEC0":[false,false,true,false,false,false,false,true],"OUT.SEC1":[false,false,false,true,false,false,false,true],"OUT.SEC10":[false,true,false,false,false,false,false,true],"OUT.SEC11":[false,true,false,false,false,false,true,true],"OUT.SEC12":[false,false,true,false,false,false,true,true],"OUT.SEC13":[false,false,false,true,false,false,true,true],"OUT.SEC14":[true,false,false,false,false,false,true,true],"OUT.SEC15":[false,false,false,false,true,false,true,true],"OUT.SEC2":[true,false,false,false,false,false,false,true],"OUT.SEC3":[false,false,false,false,true,false,false,true],"OUT.SEC4":[false,false,false,false,false,true,true,false],"OUT.SEC5":[false,true,false,false,false,false,true,false],"OUT.SEC6":[false,false,true,false,false,false,true,false],"OUT.SEC7":[false,false,false,true,false,false,true,false],"OUT.SEC8":[false,false,false,false,false,true,false,false],"OUT.SEC9":[false,false,false,false,true,false,true,false]}}},"INT.IOI.FC":{"INT:INV.IMUX.CE0":{"bits":[[0,5,56]],"invert":true},"INT:INV.IMUX.CE1":{"bits":[[0,5,57]],"invert":true},"INT:INV.IMUX.CE2":{"bits":[[0,5,50]],"invert":true},"INT:INV.IMUX.CE3":{"bits":[[0,5,63]],"invert":true},"INT:INV.IMUX.SR0":{"bits":[[0,5,6]],"invert":true},"INT:INV.IMUX.SR1":{"bits":[[0,5,7]],"invert":true},"INT:INV.IMUX.SR2":{"bits":[[0,5,0]],"invert":true},"INT:INV.IMUX.SR3":{"bits":[[0,5,13]],"invert":true},"INT:MUX.DBL.E0.0":{"bits":[[0,13,5],[0,13,6],[0,13,7],[0,15,6],[0,15,5],[0,15,4]],"values":{"DBL.E0.2":[true,false,false,false,false,true],"DBL.E2.2":[true,false,false,false,true,true],"DBL.N0.1":[false,false,true,false,true,true],"DBL.N7.3":[false,false,true,false,false,true],"DBL.S0.1":[false,true,false,false,true,true],"DBL.S2.2":[false,true,false,false,false,true],"HEX.E0.6":[false,false,true,false,false,false],"HEX.N0.3":[false,false,false,true,false,true],"HEX.N0.6":[false,false,false,true,false,false],"HEX.S0.3":[false,false,false,true,true,true],"HEX.S1.6":[false,false,true,false,true,false],"HEX.W0.6":[false,false,false,true,true,false],"NONE":[false,false,false,false,false,false],"OMUX2.E":[true,false,false,false,true,false],"OMUX8.EN":[true,false,false,false,false,false],"OUT.FAN4":[false,true,false,false,true,false]}},"INT:MUX.DBL.E1.0":{"bits":[[0,13,13],[0,13,15],[0,15,14],[0,13,14],[0,15,13],[0,15,12]],"values":{"DBL.E1.2":[true,false,false,false,false,true],"DBL.E3.2":[true,false,false,false,true,true],"DBL.N0.2":[false,false,true,false,false,true],"DBL.N1.1":[false,false,true,false,true,true],"DBL.S1.1":[false,true,false,false,false,true],"DBL.S3.2":[false,true,false,false,true,true],"HEX.E1.6":[false,true,false,false,false,false],"HEX.N1.3":[false,false,false,true,false,true],"HEX.N1.6":[false,false,true,false,false,false],"HEX.S1.3":[false,false,false,true,true,true],"HEX.S2.6":[false,true,false,false,true,false],"HEX.W1.6":[false,false,true,false,true,false],"NONE":[false,false,false,false,false,false],"OMUX10.N":[true,false,false,false,false,false],"OMUX4.S":[true,false,false,false,true,false],"OUT.FAN5":[false,false,false,true,true,false]}},"INT:MUX.DBL.E2.0":{"bits":[[0,13,22],[0,13,21],[0,13,23],[0,15,22],[0,15,21],[0,15,20]],"values":{"DBL.E2.2":[false,true,false,false,false,true],"DBL.E4.2":[false,true,false,false,true,true],"DBL.N1.2":[false,false,true,false,false,true],"DBL.N2.1":[false,false,true,false,true,true],"DBL.S2.1":[true,false,false,false,true,true],"DBL.S4.2":[true,false,false,false,false,true],"HEX.E2.6":[false,false,true,false,false,false],"HEX.N2.3":[false,false,false,true,false,true],"HEX.N2.6":[false,false,false,true,false,false],"HEX.S2.3":[false,false,false,true,true,true],"HEX.S3.6":[false,false,true,false,true,false],"HEX.W2.6":[false,false,false,true,true,false],"NONE":[false,false,false,false,false,false],"OMUX12.NE":[false,true,false,false,false,false],"OMUX4":[true,false,false,false,false,false],"OMUX6":[false,true,false,false,true,false]}},"INT:MUX.DBL.E3.0":{"bits":[[0,13,29],[0,13,31],[0,15,30],[0,13,30],[0,15,29],[0,15,28]],"values":{"DBL.E3.2":[true,false,false,false,false,true],"DBL.E5.2":[true,false,false,false,true,true],"DBL.N2.2":[false,false,true,false,false,true],"DBL.N3.1":[false,false,true,false,true,true],"DBL.S3.1":[false,true,false,false,false,true],"DBL.S5.2":[false,true,false,false,true,true],"HEX.E3.6":[false,true,false,false,false,false],"HEX.N3.3":[false,false,false,true,false,true],"HEX.N3.6":[false,false,true,false,false,false],"HEX.S3.3":[false,false,false,true,true,true],"HEX.S4.6":[false,true,false,false,true,false],"HEX.W3.6":[false,false,true,false,true,false],"NONE":[false,false,false,false,false,false],"OMUX3.SE":[true,false,false,false,true,false],"OMUX8.EN":[true,false,false,false,false,false],"OUT.FAN4":[false,false,false,true,false,false]}},"INT:MUX.DBL.E4.0":{"bits":[[0,13,37],[0,13,38],[0,13,39],[0,15,38],[0,15,37],[0,15,36]],"values":{"DBL.E4.2":[true,false,false,false,false,true],"DBL.E6.2":[true,false,false,false,true,true],"DBL.N3.2":[false,false,true,false,false,true],"DBL.N4.1":[false,false,true,false,true,true],"DBL.S4.1":[false,true,false,false,true,true],"DBL.S6.2":[false,true,false,false,false,true],"HEX.E4.6":[false,false,true,false,false,false],"HEX.N4.3":[false,false,false,true,false,true],"HEX.N4.6":[false,false,false,true,false,false],"HEX.S4.3":[false,false,false,true,true,true],"HEX.S5.6":[false,false,true,false,true,false],"HEX.W4.6":[false,false,false,true,true,false],"NONE":[false,false,false,false,false,false],"OMUX7.E":[true,false,false,false,false,false],"OMUX8.E":[true,false,false,false,true,false],"OUT.FAN5":[false,true,false,false,false,false],"OUT.FAN6":[false,true,false,false,true,false]}},"INT:MUX.DBL.E5.0":{"bits":[[0,13,45],[0,13,47],[0,15,46],[0,13,46],[0,15,45],[0,15,44]],"values":{"DBL.E5.2":[true,false,false,false,false,true],"DBL.E7.2":[true,false,false,false,true,true],"DBL.N4.2":[false,false,true,false,false,true],"DBL.N5.1":[false,false,true,false,true,true],"DBL.S5.1":[false,true,false,false,false,true],"DBL.S7.2":[false,true,false,false,true,true],"HEX.E5.6":[false,true,false,false,false,false],"HEX.N5.3":[false,false,false,true,false,true],"HEX.N5.6":[false,false,true,false,false,false],"HEX.S5.3":[false,false,false,true,true,true],"HEX.S6.6":[false,true,false,false,true,false],"HEX.W5.6":[false,false,true,false,true,false],"NONE":[false,false,false,false,false,false],"OMUX12.NE":[true,false,false,false,false,false],"OMUX7.ES":[true,false,false,false,true,false],"OUT.FAN7":[false,false,false,true,true,false]}},"INT:MUX.DBL.E6.0":{"bits":[[0,13,53],[0,13,54],[0,13,55],[0,15,54],[0,15,53],[0,15,52]],"values":{"DBL.E0.3":[true,false,false,false,true,true],"DBL.E6.2":[true,false,false,false,false,true],"DBL.N5.2":[false,false,true,false,false,true],"DBL.N6.1":[false,false,true,false,true,true],"DBL.S0.3":[false,true,false,false,false,true],"DBL.S6.1":[false,true,false,false,true,true],"HEX.E6.6":[false,false,true,false,false,false],"HEX.N6.3":[false,false,false,true,false,true],"HEX.N6.6":[false,false,false,true,false,false],"HEX.S6.3":[false,false,false,true,true,true],"HEX.S7.6":[false,false,true,false,true,false],"HEX.W6.6":[false,false,false,true,true,false],"NONE":[false,false,false,false,false,false],"OMUX11":[false,true,false,false,true,false],"OMUX3.SE":[true,false,false,false,true,false],"OMUX9":[true,false,false,false,false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true,true,true,true],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.FAN.BX0":{"bits":[[0,12,25],[0,12,31],[0,10,26],[0,10,31],[0,11,26],[0,11,27],[0,11,28],[0,11,29]],"values":{"DBL.E0.0":[false,true,false,false,false,true,false,false],"DBL.E0.1":[false,true,false,false,false,false,true,false],"DBL.E0.2":[false,false,false,false,true,true,false,false],"DBL.E1.1":[true,false,false,false,false,false,true,true],"DBL.E1.2":[false,true,false,false,false,true,false,true],"DBL.N0.1":[false,false,true,false,false,true,false,false],"DBL.N0.2":[false,false,true,false,false,true,false,true],"DBL.N1.1":[false,false,true,false,false,false,false,false],"DBL.N1.2":[false,false,false,true,false,false,false,false],"DBL.S0.0":[true,false,false,false,false,false,false,false],"DBL.S0.1":[false,false,true,false,false,false,true,true],"DBL.S0.2":[false,false,false,true,false,false,true,true],"DBL.S1.1":[false,true,false,false,false,false,false,false],"DBL.S1.2":[false,false,false,false,true,false,true,true],"DBL.W0.0":[false,false,false,false,true,true,false,true],"DBL.W0.1":[true,false,false,false,false,true,false,true],"DBL.W0.2":[false,false,false,true,false,true,false,false],"DBL.W1.1":[false,false,false,true,false,true,false,true],"DBL.W1.2":[false,false,false,false,true,false,true,false],"IMUX.FAN.BY0":[false,false,false,false,true,false,false,false],"IMUX.FAN.BY1":[false,true,false,false,false,true,true,true],"NONE":[false,false,false,false,false,false,false,false],"OMUX0.S":[true,false,false,false,false,true,true,true],"OMUX1.W":[true,false,false,false,false,true,false,false],"OMUX10.N":[false,false,false,false,true,true,true,true],"OMUX10.NW":[true,false,false,false,false,false,true,false],"OMUX2":[false,true,false,false,false,false,true,true],"OMUX2.E":[false,false,true,false,false,true,true,true],"OMUX8.EN":[false,false,false,true,false,false,true,false],"OUT.FAN4":[false,false,true,false,false,false,true,false]}},"INT:MUX.IMUX.FAN.BX1":{"bits":[[0,8,33],[0,9,33],[0,10,35],[0,8,37],[0,9,32],[0,8,34],[0,8,36],[0,8,35]],"values":{"DBL.E6.1":[false,false,false,false,true,true,false,true],"DBL.E6.2":[false,false,false,true,false,true,false,true],"DBL.E7.0":[false,false,false,true,false,false,true,false],"DBL.E7.1":[true,false,false,false,false,false,true,false],"DBL.E7.2":[false,true,false,false,false,false,false,true],"DBL.N6.1":[false,false,true,false,false,true,false,true],"DBL.N6.2":[false,false,true,false,false,false,false,true],"DBL.N7.1":[false,false,true,false,false,true,true,true],"DBL.N7.2":[true,false,false,false,false,true,true,true],"DBL.S6.0":[false,false,false,false,true,true,true,true],"DBL.S6.1":[false,false,false,false,true,false,true,false],"DBL.S6.2":[false,false,true,false,false,false,true,false],"DBL.S7.1":[false,true,false,false,false,true,false,true],"DBL.S7.2":[false,true,false,false,false,true,true,true],"DBL.W6.0":[false,false,false,true,false,false,false,true],"DBL.W6.1":[false,false,false,false,true,false,false,true],"DBL.W6.2":[true,false,false,false,false,true,false,true],"DBL.W7.1":[true,false,false,false,false,false,false,true],"DBL.W7.2":[false,true,false,false,false,false,true,false],"IMUX.FAN.BY2":[false,false,false,true,false,false,false,false],"IMUX.FAN.BY3":[false,false,false,true,false,true,true,true],"NONE":[false,false,false,false,false,false,false,false],"OMUX13":[false,false,true,false,false,false,false,false],"OMUX13.E":[false,false,false,true,false,true,true,false],"OMUX14.W":[false,false,false,false,true,true,true,false],"OMUX15.N":[false,false,true,false,false,true,true,false],"OMUX5.S":[true,false,false,false,false,true,true,false],"OMUX5.SW":[true,false,false,false,false,false,false,false],"OMUX7.ES":[false,true,false,false,false,true,true,false],"OUT.FAN7":[false,true,false,false,false,false,false,false]}},"INT:MUX.IMUX.FAN.BX2":{"bits":[[0,12,30],[0,12,26],[0,10,29],[0,11,31],[0,11,30],[0,12,27],[0,12,28],[0,12,29]],"values":{"DBL.E0.0":[false,true,false,false,false,true,false,false],"DBL.E0.1":[false,true,false,false,false,false,true,false],"DBL.E0.2":[false,false,false,false,true,true,false,false],"DBL.E1.1":[true,false,false,false,false,false,true,true],"DBL.E1.2":[false,true,false,false,false,true,false,true],"DBL.N0.1":[false,false,true,false,false,true,false,false],"DBL.N0.2":[false,false,true,false,false,true,false,true],"DBL.N1.1":[false,false,true,false,false,false,false,false],"DBL.N1.2":[false,false,false,true,false,false,false,false],"DBL.S0.0":[true,false,false,false,false,false,false,false],"DBL.S0.1":[false,false,true,false,false,false,true,true],"DBL.S0.2":[false,false,false,true,false,false,true,true],"DBL.S1.1":[false,true,false,false,false,false,false,false],"DBL.S1.2":[false,false,false,false,true,false,true,true],"DBL.W0.0":[false,false,false,false,true,true,false,true],"DBL.W0.1":[true,false,false,false,false,true,false,true],"DBL.W0.2":[false,false,false,true,false,true,false,false],"DBL.W1.1":[false,false,false,true,false,true,false,true],"DBL.W1.2":[false,false,false,false,true,false,true,false],"IMUX.FAN.BY0":[false,false,false,false,true,false,false,false],"IMUX.FAN.BY1":[false,true,false,false,false,true,true,true],"NONE":[false,false,false,false,false,false,false,false],"OMUX0.S":[true,false,false,false,false,true,true,true],"OMUX1.W":[true,false,false,false,false,true,false,false],"OMUX10.N":[false,false,false,false,true,true,true,true],"OMUX10.NW":[true,false,false,false,false,false,true,false],"OMUX2":[false,true,false,false,false,false,true,true],"OMUX2.E":[false,false,true,false,false,true,true,true],"OMUX8.EN":[false,false,false,true,false,false,true,false],"OUT.FAN4":[false,false,true,false,false,false,true,false]}},"INT:MUX.IMUX.FAN.BX3":{"bits":[[0,8,38],[0,9,37],[0,10,36],[0,8,32],[0,10,33],[0,9,34],[0,9,36],[0,9,35]],"values":{"DBL.E6.1":[false,false,false,false,true,true,false,true],"DBL.E6.2":[false,false,false,true,false,true,false,true],"DBL.E7.0":[false,false,false,true,false,false,true,false],"DBL.E7.1":[true,false,false,false,false,false,true,false],"DBL.E7.2":[false,true,false,false,false,false,false,true],"DBL.N6.1":[false,false,true,false,false,true,false,true],"DBL.N6.2":[false,false,true,false,false,false,false,true],"DBL.N7.1":[false,false,true,false,false,true,true,true],"DBL.N7.2":[true,false,false,false,false,true,true,true],"DBL.S6.0":[false,false,false,false,true,true,true,true],"DBL.S6.1":[false,false,false,false,true,false,true,false],"DBL.S6.2":[false,false,true,false,false,false,true,false],"DBL.S7.1":[false,true,false,false,false,true,false,true],"DBL.S7.2":[false,true,false,false,false,true,true,true],"DBL.W6.0":[false,false,false,true,false,false,false,true],"DBL.W6.1":[false,false,false,false,true,false,false,true],"DBL.W6.2":[true,false,false,false,false,true,false,true],"DBL.W7.1":[true,false,false,false,false,false,false,true],"DBL.W7.2":[false,true,false,false,false,false,true,false],"IMUX.FAN.BY2":[false,false,false,true,false,false,false,false],"IMUX.FAN.BY3":[false,false,false,true,false,true,true,true],"NONE":[false,false,false,false,false,false,false,false],"OMUX13":[false,false,true,false,false,false,false,false],"OMUX13.E":[false,false,false,true,false,true,true,false],"OMUX14.W":[false,false,false,false,true,true,true,false],"OMUX15.N":[false,false,true,false,false,true,true,false],"OMUX5.S":[true,false,false,false,false,true,true,false],"OMUX5.SW":[true,false,false,false,false,false,false,false],"OMUX7.ES":[false,true,false,false,false,true,true,false],"OUT.FAN7":[false,true,false,false,false,false,false,false]}},"INT:MUX.IMUX.FAN.BY0":{"bits":[[0,10,27],[0,10,30],[0,9,26],[0,8,25],[0,8,31],[0,9,28],[0,9,29],[0,9,27]],"values":{"DBL.E2.1":[false,false,false,true,false,false,false,true],"DBL.E2.2":[false,false,true,false,false,false,false,true],"DBL.E3.0":[false,false,false,true,false,false,true,true],"DBL.E3.1":[false,true,false,false,false,true,true,false],"DBL.E3.2":[false,false,false,false,true,false,true,true],"DBL.N2.1":[true,false,false,false,false,false,false,true],"DBL.N2.2":[true,false,false,false,false,false,true,true],"DBL.N3.1":[true,false,false,false,false,false,false,false],"DBL.N3.2":[false,true,false,false,false,false,false,false],"DBL.S2.0":[false,false,false,true,false,false,false,false],"DBL.S2.1":[false,false,false,false,true,false,false,false],"DBL.S2.2":[true,false,false,false,false,true,true,false],"DBL.S3.1":[false,false,false,false,true,false,false,true],"DBL.S3.2":[false,false,true,false,false,false,false,false],"DBL.W2.0":[false,false,false,false,true,true,false,false],"DBL.W2.1":[false,false,false,true,false,true,true,false],"DBL.W2.2":[false,true,false,false,false,false,false,true],"DBL.W3.1":[false,true,false,false,false,false,true,true],"DBL.W3.2":[false,false,true,false,false,true,true,false],"IMUX.FAN.BX2":[false,false,false,false,true,true,true,false],"IMUX.FAN.BX3":[false,false,true,false,false,true,false,false],"NONE":[false,false,false,false,false,false,false,false],"OMUX12.N":[false,false,false,true,false,true,false,false],"OMUX12.NE":[false,false,true,false,false,true,true,true],"OMUX14.WN":[false,true,false,false,false,true,true,true],"OMUX4.S":[true,false,false,false,false,true,false,false],"OMUX6":[true,false,false,false,false,true,true,true],"OMUX6.W":[false,true,false,false,false,true,false,false],"OMUX7.E":[false,false,true,false,false,false,true,true],"OUT.FAN5":[false,false,false,false,true,true,true,true]}},"INT:MUX.IMUX.FAN.BY1":{"bits":[[0,12,33],[0,10,34],[0,11,32],[0,12,37],[0,11,33],[0,12,36],[0,12,34],[0,12,35]],"values":{"DBL.E4.1":[false,false,true,false,false,false,true,true],"DBL.E4.2":[false,false,false,true,false,false,true,true],"DBL.E5.0":[false,false,false,false,true,false,true,true],"DBL.E5.1":[false,false,true,false,false,true,false,false],"DBL.E5.2":[false,false,false,false,true,false,false,true],"DBL.N4.1":[false,true,false,false,false,false,true,true],"DBL.N4.2":[false,false,false,true,false,false,false,false],"DBL.N5.1":[false,true,false,false,false,true,true,true],"DBL.N5.2":[true,false,false,false,false,true,true,true],"DBL.S4.0":[false,false,true,false,false,true,true,true],"DBL.S4.1":[false,true,false,false,false,true,false,false],"DBL.S4.2":[false,false,true,false,false,true,true,false],"DBL.S5.1":[false,false,false,false,true,true,true,true],"DBL.S5.2":[false,true,false,false,false,false,false,true],"DBL.W4.0":[false,false,false,true,false,false,false,true],"DBL.W4.1":[false,false,false,false,true,true,true,false],"DBL.W4.2":[true,false,false,false,false,false,true,true],"DBL.W5.1":[true,false,false,false,false,false,false,true],"DBL.W5.2":[false,false,false,true,false,true,true,false],"IMUX.FAN.BX0":[false,false,false,false,true,true,false,false],"IMUX.FAN.BX1":[false,false,true,false,false,false,false,false],"NONE":[false,false,false,false,false,false,false,false],"OMUX1.WS":[true,false,false,false,false,true,false,false],"OMUX11.N":[false,false,false,true,false,true,false,false],"OMUX3.S":[true,false,false,false,false,false,false,false],"OMUX3.SE":[false,true,false,false,false,true,true,false],"OMUX8.E":[false,false,true,false,false,false,false,true],"OMUX9":[false,true,false,false,false,false,false,false],"OMUX9.W":[true,false,false,false,false,true,true,false],"OUT.FAN6":[false,false,false,false,true,false,false,false]}},"INT:MUX.IMUX.FAN.BY2":{"bits":[[0,10,28],[0,9,31],[0,9,30],[0,8,30],[0,8,26],[0,8,28],[0,8,29],[0,8,27]],"values":{"DBL.E2.1":[false,false,false,true,false,false,false,true],"DBL.E2.2":[false,false,true,false,false,false,false,true],"DBL.E3.0":[false,false,false,true,false,false,true,true],"DBL.E3.1":[false,true,false,false,false,true,true,false],"DBL.E3.2":[false,false,false,false,true,false,true,true],"DBL.N2.1":[true,false,false,false,false,false,false,true],"DBL.N2.2":[true,false,false,false,false,false,true,true],"DBL.N3.1":[true,false,false,false,false,false,false,false],"DBL.N3.2":[false,true,false,false,false,false,false,false],"DBL.S2.0":[false,false,false,true,false,false,false,false],"DBL.S2.1":[false,false,false,false,true,false,false,false],"DBL.S2.2":[true,false,false,false,false,true,true,false],"DBL.S3.1":[false,false,false,false,true,false,false,true],"DBL.S3.2":[false,false,true,false,false,false,false,false],"DBL.W2.0":[false,false,false,false,true,true,false,false],"DBL.W2.1":[false,false,false,true,false,true,true,false],"DBL.W2.2":[false,true,false,false,false,false,false,true],"DBL.W3.1":[false,true,false,false,false,false,true,true],"DBL.W3.2":[false,false,true,false,false,true,true,false],"IMUX.FAN.BX2":[false,false,false,false,true,true,true,false],"IMUX.FAN.BX3":[false,false,true,false,false,true,false,false],"NONE":[false,false,false,false,false,false,false,false],"OMUX12.N":[false,false,false,true,false,true,false,false],"OMUX12.NE":[false,false,true,false,false,true,true,true],"OMUX14.WN":[false,true,false,false,false,true,true,true],"OMUX4.S":[true,false,false,false,false,true,false,false],"OMUX6":[true,false,false,false,false,true,true,true],"OMUX6.W":[false,true,false,false,false,true,false,false],"OMUX7.E":[false,false,true,false,false,false,true,true],"OUT.FAN5":[false,false,false,false,true,true,true,true]}},"INT:MUX.IMUX.FAN.BY3":{"bits":[[0,12,38],[0,10,37],[0,10,32],[0,12,32],[0,11,37],[0,11,36],[0,11,34],[0,11,35]],"values":{"DBL.E4.1":[false,false,true,false,false,false,true,true],"DBL.E4.2":[false,false,false,true,false,false,true,true],"DBL.E5.0":[false,false,false,false,true,false,true,true],"DBL.E5.1":[false,false,true,false,false,true,false,false],"DBL.E5.2":[false,false,false,false,true,false,false,true],"DBL.N4.1":[false,true,false,false,false,false,true,true],"DBL.N4.2":[false,false,false,true,false,false,false,false],"DBL.N5.1":[false,true,false,false,false,true,true,true],"DBL.N5.2":[true,false,false,false,false,true,true,true],"DBL.S4.0":[false,false,true,false,false,true,true,true],"DBL.S4.1":[false,true,false,false,false,true,false,false],"DBL.S4.2":[false,false,true,false,false,true,true,false],"DBL.S5.1":[false,false,false,false,true,true,true,true],"DBL.S5.2":[false,true,false,false,false,false,false,true],"DBL.W4.0":[false,false,false,true,false,false,false,true],"DBL.W4.1":[false,false,false,false,true,true,true,false],"DBL.W4.2":[true,false,false,false,false,false,true,true],"DBL.W5.1":[true,false,false,false,false,false,false,true],"DBL.W5.2":[false,false,false,true,false,true,true,false],"IMUX.FAN.BX0":[false,false,false,false,true,true,false,false],"IMUX.FAN.BX1":[false,false,true,false,false,false,false,false],"NONE":[false,false,false,false,false,false,false,false],"OMUX1.WS":[true,false,false,false,false,true,false,false],"OMUX11.N":[false,false,false,true,false,true,false,false],"OMUX3.S":[true,false,false,false,false,false,false,false],"OMUX3.SE":[false,true,false,false,false,true,true,false],"OMUX8.E":[false,false,true,false,false,false,false,true],"OMUX9":[false,true,false,false,false,false,false,false],"OMUX9.W":[true,false,false,false,false,true,true,false],"OUT.FAN6":[false,false,false,false,true,false,false,false]}},"INT:MUX.IMUX.IOCLK0":{"bits":[[0,4,21],[0,4,19],[0,5,20],[0,4,18],[0,5,16],[0,5,23],[0,4,22],[0,4,23]],"values":{"DBL.E4.0":[true,false,false,false,false,false,false,true],"DBL.E4.1":[false,false,false,true,false,false,false,true],"DBL.W4.1":[false,false,false,false,true,false,false,true],"DBL.W4.2":[false,false,false,false,false,true,true,false],"GCLK0":[true,false,false,false,false,false,true,false],"GCLK1":[true,false,false,false,false,false,true,true],"GCLK2":[false,true,false,false,false,false,true,true],"GCLK3":[false,false,true,false,false,false,true,true],"GCLK4":[false,false,false,true,false,false,true,true],"GCLK5":[false,false,false,false,true,false,true,true],"GCLK6":[false,true,false,false,false,false,false,true],"GCLK7":[false,false,true,false,false,false,false,true],"HEX.N4.0":[false,false,false,false,true,false,false,false],"HEX.N4.1":[true,false,false,false,false,false,false,false],"HEX.N4.2":[false,false,true,false,false,false,false,false],"HEX.N4.3":[false,true,false,false,false,false,true,false],"HEX.N4.4":[false,false,true,false,false,false,true,false],"HEX.N4.5":[false,false,false,false,false,true,false,true],"HEX.S4.1":[false,false,false,true,false,false,true,false],"HEX.S4.2":[false,false,false,false,false,true,true,true],"HEX.S4.3":[false,false,false,true,false,false,false,false],"HEX.S4.4":[false,true,false,false,false,false,false,false],"HEX.S4.5":[false,false,false,false,false,true,false,false],"HEX.S4.6":[false,false,false,false,true,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.IOCLK1":{"bits":[[0,5,21],[0,4,20],[0,5,19],[0,5,18],[0,5,17],[0,5,22],[0,4,17],[0,4,16]],"values":{"DBL.E4.0":[true,false,false,false,false,false,false,true],"DBL.E4.1":[false,false,false,true,false,false,false,true],"DBL.W4.1":[false,false,false,false,true,false,false,true],"DBL.W4.2":[false,false,false,false,false,true,true,false],"GCLK0":[true,false,false,false,false,false,true,false],"GCLK1":[true,false,false,false,false,false,true,true],"GCLK2":[false,true,false,false,false,false,true,true],"GCLK3":[false,false,true,false,false,false,true,true],"GCLK4":[false,false,false,true,false,false,true,true],"GCLK5":[false,false,false,false,true,false,true,true],"GCLK6":[false,true,false,false,false,false,false,true],"GCLK7":[false,false,true,false,false,false,false,true],"HEX.N4.0":[false,false,false,false,true,false,false,false],"HEX.N4.1":[true,false,false,false,false,false,false,false],"HEX.N4.2":[false,false,true,false,false,false,false,false],"HEX.N4.3":[false,true,false,false,false,false,true,false],"HEX.N4.4":[false,false,true,false,false,false,true,false],"HEX.N4.5":[false,false,false,false,false,true,false,true],"HEX.S4.1":[false,false,false,true,false,false,true,false],"HEX.S4.2":[false,false,false,false,false,true,true,true],"HEX.S4.3":[false,false,false,true,false,false,false,false],"HEX.S4.4":[false,true,false,false,false,false,false,false],"HEX.S4.5":[false,false,false,false,false,true,false,false],"HEX.S4.6":[false,false,false,false,true,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.IOCLK2":{"bits":[[0,4,37],[0,4,35],[0,5,36],[0,4,34],[0,5,32],[0,5,39],[0,4,38],[0,4,39]],"values":{"DBL.E4.0":[true,false,false,false,false,false,false,true],"DBL.E4.1":[false,false,false,true,false,false,false,true],"DBL.W4.1":[false,false,false,false,true,false,false,true],"DBL.W4.2":[false,false,false,false,false,true,true,false],"GCLK0":[true,false,false,false,false,false,true,false],"GCLK1":[true,false,false,false,false,false,true,true],"GCLK2":[false,true,false,false,false,false,true,true],"GCLK3":[false,false,true,false,false,false,true,true],"GCLK4":[false,false,false,true,false,false,true,true],"GCLK5":[false,false,false,false,true,false,true,true],"GCLK6":[false,true,false,false,false,false,false,true],"GCLK7":[false,false,true,false,false,false,false,true],"HEX.N4.0":[false,false,false,false,true,false,false,false],"HEX.N4.1":[true,false,false,false,false,false,false,false],"HEX.N4.2":[false,false,true,false,false,false,false,false],"HEX.N4.3":[false,true,false,false,false,false,true,false],"HEX.N4.4":[false,false,true,false,false,false,true,false],"HEX.N4.5":[false,false,false,false,false,true,false,true],"HEX.S4.1":[false,false,false,true,false,false,true,false],"HEX.S4.2":[false,false,false,false,false,true,true,true],"HEX.S4.3":[false,false,false,true,false,false,false,false],"HEX.S4.4":[false,true,false,false,false,false,false,false],"HEX.S4.5":[false,false,false,false,false,true,false,false],"HEX.S4.6":[false,false,false,false,true,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.IOCLK3":{"bits":[[0,5,37],[0,4,36],[0,5,35],[0,5,34],[0,5,33],[0,5,38],[0,4,33],[0,4,32]],"values":{"DBL.E4.0":[true,false,false,false,false,false,false,true],"DBL.E4.1":[false,false,false,true,false,false,false,true],"DBL.W4.1":[false,false,false,false,true,false,false,true],"DBL.W4.2":[false,false,false,false,false,true,true,false],"GCLK0":[true,false,false,false,false,false,true,false],"GCLK1":[true,false,false,false,false,false,true,true],"GCLK2":[false,true,false,false,false,false,true,true],"GCLK3":[false,false,true,false,false,false,true,true],"GCLK4":[false,false,false,true,false,false,true,true],"GCLK5":[false,false,false,false,true,false,true,true],"GCLK6":[false,true,false,false,false,false,false,true],"GCLK7":[false,false,true,false,false,false,false,true],"HEX.N4.0":[false,false,false,false,true,false,false,false],"HEX.N4.1":[true,false,false,false,false,false,false,false],"HEX.N4.2":[false,false,true,false,false,false,false,false],"HEX.N4.3":[false,true,false,false,false,false,true,false],"HEX.N4.4":[false,false,true,false,false,false,true,false],"HEX.N4.5":[false,false,false,false,false,true,false,true],"HEX.S4.1":[false,false,false,true,false,false,true,false],"HEX.S4.2":[false,false,false,false,false,true,true,true],"HEX.S4.3":[false,false,false,true,false,false,false,false],"HEX.S4.4":[false,true,false,false,false,false,false,false],"HEX.S4.5":[false,false,false,false,false,true,false,false],"HEX.S4.6":[false,false,false,false,true,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.IOCLK4":{"bits":[[0,4,26],[0,4,28],[0,5,27],[0,4,29],[0,5,31],[0,5,24],[0,4,25],[0,4,24]],"values":{"DBL.E4.0":[true,false,false,false,false,false,false,true],"DBL.E4.1":[false,false,false,true,false,false,false,true],"DBL.W4.1":[false,false,false,false,true,false,false,true],"DBL.W4.2":[false,false,false,false,false,true,true,false],"GCLK0":[true,false,false,false,false,false,true,false],"GCLK1":[true,false,false,false,false,false,true,true],"GCLK2":[false,true,false,false,false,false,true,true],"GCLK3":[false,false,true,false,false,false,true,true],"GCLK4":[false,false,false,true,false,false,true,true],"GCLK5":[false,false,false,false,true,false,true,true],"GCLK6":[false,true,false,false,false,false,false,true],"GCLK7":[false,false,true,false,false,false,false,true],"HEX.N4.0":[false,false,false,false,true,false,false,false],"HEX.N4.1":[true,false,false,false,false,false,false,false],"HEX.N4.2":[false,false,true,false,false,false,false,false],"HEX.N4.3":[false,true,false,false,false,false,true,false],"HEX.N4.4":[false,false,true,false,false,false,true,false],"HEX.N4.5":[false,false,false,false,false,true,false,true],"HEX.S4.1":[false,false,false,true,false,false,true,false],"HEX.S4.2":[false,false,false,false,false,true,true,true],"HEX.S4.3":[false,false,false,true,false,false,false,false],"HEX.S4.4":[false,true,false,false,false,false,false,false],"HEX.S4.5":[false,false,false,false,false,true,false,false],"HEX.S4.6":[false,false,false,false,true,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.IOCLK5":{"bits":[[0,5,26],[0,4,27],[0,5,28],[0,5,29],[0,5,30],[0,5,25],[0,4,30],[0,4,31]],"values":{"DBL.E4.0":[true,false,false,false,false,false,false,true],"DBL.E4.1":[false,false,false,true,false,false,false,true],"DBL.W4.1":[false,false,false,false,true,false,false,true],"DBL.W4.2":[false,false,false,false,false,true,true,false],"GCLK0":[true,false,false,false,false,false,true,false],"GCLK1":[true,false,false,false,false,false,true,true],"GCLK2":[false,true,false,false,false,false,true,true],"GCLK3":[false,false,true,false,false,false,true,true],"GCLK4":[false,false,false,true,false,false,true,true],"GCLK5":[false,false,false,false,true,false,true,true],"GCLK6":[false,true,false,false,false,false,false,true],"GCLK7":[false,false,true,false,false,false,false,true],"HEX.N4.0":[false,false,false,false,true,false,false,false],"HEX.N4.1":[true,false,false,false,false,false,false,false],"HEX.N4.2":[false,false,true,false,false,false,false,false],"HEX.N4.3":[false,true,false,false,false,false,true,false],"HEX.N4.4":[false,false,true,false,false,false,true,false],"HEX.N4.5":[false,false,false,false,false,true,false,true],"HEX.S4.1":[false,false,false,true,false,false,true,false],"HEX.S4.2":[false,false,false,false,false,true,true,true],"HEX.S4.3":[false,false,false,true,false,false,false,false],"HEX.S4.4":[false,true,false,false,false,false,false,false],"HEX.S4.5":[false,false,false,false,false,true,false,false],"HEX.S4.6":[false,false,false,false,true,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.IOCLK6":{"bits":[[0,4,42],[0,4,44],[0,5,43],[0,4,45],[0,5,47],[0,5,40],[0,4,41],[0,4,40]],"values":{"DBL.E4.0":[true,false,false,false,false,false,false,true],"DBL.E4.1":[false,false,false,true,false,false,false,true],"DBL.W4.1":[false,false,false,false,true,false,false,true],"DBL.W4.2":[false,false,false,false,false,true,true,false],"GCLK0":[true,false,false,false,false,false,true,false],"GCLK1":[true,false,false,false,false,false,true,true],"GCLK2":[false,true,false,false,false,false,true,true],"GCLK3":[false,false,true,false,false,false,true,true],"GCLK4":[false,false,false,true,false,false,true,true],"GCLK5":[false,false,false,false,true,false,true,true],"GCLK6":[false,true,false,false,false,false,false,true],"GCLK7":[false,false,true,false,false,false,false,true],"HEX.N4.0":[false,false,false,false,true,false,false,false],"HEX.N4.1":[true,false,false,false,false,false,false,false],"HEX.N4.2":[false,false,true,false,false,false,false,false],"HEX.N4.3":[false,true,false,false,false,false,true,false],"HEX.N4.4":[false,false,true,false,false,false,true,false],"HEX.N4.5":[false,false,false,false,false,true,false,true],"HEX.S4.1":[false,false,false,true,false,false,true,false],"HEX.S4.2":[false,false,false,false,false,true,true,true],"HEX.S4.3":[false,false,false,true,false,false,false,false],"HEX.S4.4":[false,true,false,false,false,false,false,false],"HEX.S4.5":[false,false,false,false,false,true,false,false],"HEX.S4.6":[false,false,false,false,true,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.IOCLK7":{"bits":[[0,5,42],[0,4,43],[0,5,44],[0,5,45],[0,5,46],[0,5,41],[0,4,46],[0,4,47]],"values":{"DBL.E4.0":[true,false,false,false,false,false,false,true],"DBL.E4.1":[false,false,false,true,false,false,false,true],"DBL.W4.1":[false,false,false,false,true,false,false,true],"DBL.W4.2":[false,false,false,false,false,true,true,false],"GCLK0":[true,false,false,false,false,false,true,false],"GCLK1":[true,false,false,false,false,false,true,true],"GCLK2":[false,true,false,false,false,false,true,true],"GCLK3":[false,false,true,false,false,false,true,true],"GCLK4":[false,false,false,true,false,false,true,true],"GCLK5":[false,false,false,false,true,false,true,true],"GCLK6":[false,true,false,false,false,false,false,true],"GCLK7":[false,false,true,false,false,false,false,true],"HEX.N4.0":[false,false,false,false,true,false,false,false],"HEX.N4.1":[true,false,false,false,false,false,false,false],"HEX.N4.2":[false,false,true,false,false,false,false,false],"HEX.N4.3":[false,true,false,false,false,false,true,false],"HEX.N4.4":[false,false,true,false,false,false,true,false],"HEX.N4.5":[false,false,false,false,false,true,false,true],"HEX.S4.1":[false,false,false,true,false,false,true,false],"HEX.S4.2":[false,false,false,false,false,true,true,true],"HEX.S4.3":[false,false,false,true,false,false,false,false],"HEX.S4.4":[false,true,false,false,false,false,false,false],"HEX.S4.5":[false,false,false,false,false,true,false,false],"HEX.S4.6":[false,false,false,false,true,false,true,false],"PULLUP":[false,false,false,false,false,false,false,false]}},"INT:MUX.IMUX.SR0":{"bits":[[0,5,2],[0,4,2],[0,5,5],[0,4,4],[0,4,5],[0,4,6]],"values":{"DBL.E0.0":[true,false,false,false,false,true],"DBL.E0.1":[true,false,false,false,false,false],"DBL.W0.1":[true,false,false,false,true,false],"DBL.W0.2":[true,false,false,false,true,true],"HEX.N0.0":[false,true,false,false,true,false],"HEX.N0.1":[false,false,true,false,true,false],"HEX.N0.2":[false,false,false,true,true,false],"HEX.N0.3":[false,true,false,false,true,true],"HEX.N0.4":[false,false,true,false,true,true],"HEX.N0.5":[false,false,false,true,true,true],"HEX.S0.1":[false,true,false,false,false,true],"HEX.S0.2":[false,false,true,false,false,true],"HEX.S0.3":[false,false,false,true,false,true],"HEX.S0.4":[false,true,false,false,false,false],"HEX.S0.5":[false,false,true,false,false,false],"HEX.S0.6":[false,false,false,true,false,false],"PULLUP":[false,false,false,false,false,false]}},"INT:MUX.IMUX.SR1":{"bits":[[0,4,11],[0,5,12],[0,5,9],[0,4,9],[0,4,8],[0,4,7]],"values":{"DBL.E1.0":[true,false,false,false,false,true],"DBL.E1.1":[true,false,false,false,false,false],"DBL.W1.1":[true,false,false,false,true,false],"DBL.W1.2":[true,false,false,false,true,true],"HEX.N0.0":[false,true,false,false,true,false],"HEX.N0.1":[false,false,true,false,true,false],"HEX.N0.2":[false,false,false,true,true,false],"HEX.N0.3":[false,true,false,false,true,true],"HEX.N0.4":[false,false,true,false,true,true],"HEX.N0.5":[false,false,false,true,true,true],"HEX.S0.1":[false,true,false,false,false,true],"HEX.S0.2":[false,false,true,false,false,true],"HEX.S0.3":[false,false,false,true,false,true],"HEX.S0.4":[false,true,false,false,false,false],"HEX.S0.5":[false,false,true,false,false,false],"HEX.S0.6":[false,false,false,true,false,false],"PULLUP":[false,false,false,false,false,false]}},"INT:MUX.IMUX.SR2":{"bits":[[0,5,1],[0,5,3],[0,4,3],[0,5,4],[0,4,1],[0,4,0]],"values":{"DBL.E0.0":[true,false,false,false,false,true],"DBL.E0.1":[true,false,false,false,false,false],"DBL.W0.1":[true,false,false,false,true,false],"DBL.W0.2":[true,false,false,false,true,true],"HEX.N0.0":[false,true,false,false,true,false],"HEX.N0.1":[false,false,true,false,true,false],"HEX.N0.2":[false,false,false,true,true,false],"HEX.N0.3":[false,true,false,false,true,true],"HEX.N0.4":[false,false,true,false,true,true],"HEX.N0.5":[false,false,false,true,true,true],"HEX.S0.1":[false,true,false,false,false,true],"HEX.S0.2":[false,false,true,false,false,true],"HEX.S0.3":[false,false,false,true,false,true],"HEX.S0.4":[false,true,false,false,false,false],"HEX.S0.5":[false,false,true,false,false,false],"HEX.S0.6":[false,false,false,true,false,false],"PULLUP":[false,false,false,false,false,false]}},"INT:MUX.IMUX.SR3":{"bits":[[0,5,11],[0,5,10],[0,4,10],[0,5,8],[0,4,12],[0,4,13]],"values":{"DBL.E1.0":[true,false,false,false,false,true],"DBL.E1.1":[true,false,false,false,false,false],"DBL.W1.1":[true,false,false,false,true,false],"DBL.W1.2":[true,false,false,false,true,true],"HEX.N0.0":[false,true,false,false,true,false],"HEX.N0.1":[false,false,true,false,true,false],"HEX.N0.2":[false,false,false,true,true,false],"HEX.N0.3":[false,true,false,false,true,true],"HEX.N0.4":[false,false,true,false,true,true],"HEX.N0.5":[false,false,false,true,true,true],"HEX.S0.1":[false,true,false,false,false,true],"HEX.S0.2":[false,false,true,false,false,true],"HEX.S0.3":[false,false,false,true,false,true],"HEX.S0.4":[false,true,false,false,false,false],"HEX.S0.5":[false,false,true,false,false,false],"HEX.S0.6":[false,false,false,true,false,false],"PULLUP":[false,false,false,false,false,false]}},"INT:MUX.LH.0":{"bits":[[0,18,40],[0,18,41],[0,18,38]],"values":{"DBL.E4.1":[false,true,false],"DBL.W4.1":[true,false,false],"NONE":[false,false,false],"OMUX11":[false,true,true],"OMUX4.S":[true,false,true]}},"INT:MUX.LH.6":{"bits":[[0,18,23],[0,18,22],[0,18,25]],"values":{"DBL.E3.1":[false,true,false],"DBL.W3.1":[false,true,true],"NONE":[false,false,false],"OMUX15.N":[true,false,true],"OMUX4":[true,false,false]}},"INT:MUX.LV.0":{"bits":[[0,18,0],[0,18,6],[0,18,1],[0,18,7],[0,18,8]],"values":{"DBL.E2.1":[false,true,false,true,false],"DBL.W1.1":[false,false,true,true,true],"HEX.E0.1":[true,false,false,false,true],"HEX.E0.2":[false,false,true,true,false],"HEX.E0.3":[false,true,false,true,true],"HEX.E0.4":[true,false,false,true,true],"HEX.E0.5":[true,false,false,false,false],"HEX.E0.6":[false,false,true,false,false],"NONE":[false,false,false,false,false],"OMUX0":[true,false,false,true,false],"OMUX2.E":[false,true,false,false,false]}},"INT:MUX.LV.6":{"bits":[[0,18,63],[0,18,57],[0,18,62],[0,18,56],[0,18,55]],"values":{"DBL.E7.1":[true,false,false,true,false],"DBL.W7.1":[false,true,false,false,false],"HEX.W6.0":[false,false,true,true,false],"HEX.W6.1":[false,false,true,false,false],"HEX.W6.2":[true,false,false,false,true],"HEX.W6.3":[false,true,false,true,false],"HEX.W6.4":[true,false,false,true,true],"HEX.W6.5":[false,false,true,true,true],"NONE":[false,false,false,false,false],"OMUX15":[false,true,false,true,true],"OMUX9.W":[true,false,false,false,false]}},"INT:MUX.OMUX0":{"bits":[[0,6,5],[0,7,7],[0,7,0],[0,6,3],[0,6,2],[0,6,6],[0,6,7]],"values":{"NONE":[false,false,false,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false],"OUT.FAN5":[false,true,false,false,false,false,false],"OUT.FAN6":[false,false,true,false,false,true,false],"OUT.FAN7":[false,false,true,false,false,true,true],"OUT.SEC10":[false,false,false,false,true,true,false],"OUT.SEC11":[false,true,false,false,false,true,true],"OUT.SEC8":[false,false,true,false,false,false,false],"OUT.SEC9":[false,false,false,true,false,true,true]}},"INT:MUX.OMUX1":{"bits":[[0,7,5],[0,7,6],[0,7,1],[0,6,4],[0,7,2],[0,6,1],[0,6,0]],"values":{"NONE":[false,false,false,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false],"OUT.FAN5":[false,true,false,false,false,false,false],"OUT.FAN6":[false,false,true,false,false,true,false],"OUT.FAN7":[false,false,true,false,false,true,true],"OUT.SEC10":[false,false,false,false,true,true,false],"OUT.SEC11":[false,true,false,false,false,true,true],"OUT.SEC8":[false,false,true,false,false,false,false],"OUT.SEC9":[false,false,false,true,false,true,true]}},"INT:MUX.OMUX10":{"bits":[[0,6,42],[0,7,40],[0,7,47],[0,6,44],[0,6,45],[0,6,41],[0,6,40]],"values":{"NONE":[false,false,false,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false],"OUT.FAN5":[false,true,false,false,false,false,false],"OUT.FAN6":[false,false,true,false,false,true,false],"OUT.FAN7":[false,false,true,false,false,true,true],"OUT.SEC10":[false,false,false,false,true,true,false],"OUT.SEC11":[false,true,false,false,false,true,true],"OUT.SEC8":[false,false,true,false,false,false,false],"OUT.SEC9":[false,false,false,true,false,true,true]}},"INT:MUX.OMUX11":{"bits":[[0,7,42],[0,7,41],[0,7,46],[0,6,43],[0,7,45],[0,6,46],[0,6,47]],"values":{"NONE":[false,false,false,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false],"OUT.FAN5":[false,true,false,false,false,false,false],"OUT.FAN6":[false,false,true,false,false,true,false],"OUT.FAN7":[false,false,true,false,false,true,true],"OUT.SEC10":[false,false,false,false,true,true,false],"OUT.SEC11":[false,true,false,false,false,true,true],"OUT.SEC8":[false,false,true,false,false,false,false],"OUT.SEC9":[false,false,false,true,false,true,true]}},"INT:MUX.OMUX12":{"bits":[[0,6,53],[0,7,55],[0,7,48],[0,6,51],[0,6,50],[0,6,54],[0,6,55]],"values":{"NONE":[false,false,false,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false],"OUT.FAN5":[false,true,false,false,false,false,false],"OUT.FAN6":[false,false,true,false,false,true,false],"OUT.FAN7":[false,false,true,false,false,true,true],"OUT.SEC10":[false,false,false,false,true,true,false],"OUT.SEC11":[false,true,false,false,false,true,true],"OUT.SEC8":[false,false,true,false,false,false,false],"OUT.SEC9":[false,false,false,true,false,true,true]}},"INT:MUX.OMUX13":{"bits":[[0,7,53],[0,7,54],[0,7,49],[0,6,52],[0,7,50],[0,6,49],[0,6,48]],"values":{"NONE":[false,false,false,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false],"OUT.FAN5":[false,true,false,false,false,false,false],"OUT.FAN6":[false,false,true,false,false,true,false],"OUT.FAN7":[false,false,true,false,false,true,true],"OUT.SEC10":[false,false,false,false,true,true,false],"OUT.SEC11":[false,true,false,false,false,true,true],"OUT.SEC8":[false,false,true,false,false,false,false],"OUT.SEC9":[false,false,false,true,false,true,true]}},"INT:MUX.OMUX14":{"bits":[[0,6,58],[0,7,56],[0,7,63],[0,6,60],[0,6,61],[0,6,57],[0,6,56]],"values":{"NONE":[false,false,false,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false],"OUT.FAN5":[false,true,false,false,false,false,false],"OUT.FAN6":[false,false,true,false,false,true,false],"OUT.FAN7":[false,false,true,false,false,true,true],"OUT.SEC10":[false,false,false,false,true,true,false],"OUT.SEC11":[false,true,false,false,false,true,true],"OUT.SEC8":[false,false,true,false,false,false,false],"OUT.SEC9":[false,false,false,true,false,true,true]}},"INT:MUX.OMUX15":{"bits":[[0,7,58],[0,7,57],[0,7,62],[0,6,59],[0,7,61],[0,6,62],[0,6,63]],"values":{"NONE":[false,false,false,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false],"OUT.FAN5":[false,true,false,false,false,false,false],"OUT.FAN6":[false,false,true,false,false,true,false],"OUT.FAN7":[false,false,true,false,false,true,true],"OUT.SEC10":[false,false,false,false,true,true,false],"OUT.SEC11":[false,true,false,false,false,true,true],"OUT.SEC8":[false,false,true,false,false,false,false],"OUT.SEC9":[false,false,false,true,false,true,true]}},"INT:MUX.OMUX2":{"bits":[[0,6,10],[0,7,8],[0,7,15],[0,6,12],[0,6,13],[0,6,9],[0,6,8]],"values":{"NONE":[false,false,false,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false],"OUT.FAN5":[false,true,false,false,false,false,false],"OUT.FAN6":[false,false,true,false,false,true,false],"OUT.FAN7":[false,false,true,false,false,true,true],"OUT.SEC10":[false,false,false,false,true,true,false],"OUT.SEC11":[false,true,false,false,false,true,true],"OUT.SEC8":[false,false,true,false,false,false,false],"OUT.SEC9":[false,false,false,true,false,true,true]}},"INT:MUX.OMUX3":{"bits":[[0,7,10],[0,7,9],[0,7,14],[0,6,11],[0,7,13],[0,6,14],[0,6,15]],"values":{"NONE":[false,false,false,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false],"OUT.FAN5":[false,true,false,false,false,false,false],"OUT.FAN6":[false,false,true,false,false,true,false],"OUT.FAN7":[false,false,true,false,false,true,true],"OUT.SEC10":[false,false,false,false,true,true,false],"OUT.SEC11":[false,true,false,false,false,true,true],"OUT.SEC8":[false,false,true,false,false,false,false],"OUT.SEC9":[false,false,false,true,false,true,true]}},"INT:MUX.OMUX4":{"bits":[[0,6,21],[0,7,23],[0,7,16],[0,6,19],[0,6,18],[0,6,22],[0,6,23]],"values":{"NONE":[false,false,false,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false],"OUT.FAN5":[false,true,false,false,false,false,false],"OUT.FAN6":[false,false,true,false,false,true,false],"OUT.FAN7":[false,false,true,false,false,true,true],"OUT.SEC10":[false,false,false,false,true,true,false],"OUT.SEC11":[false,true,false,false,false,true,true],"OUT.SEC8":[false,false,true,false,false,false,false],"OUT.SEC9":[false,false,false,true,false,true,true]}},"INT:MUX.OMUX5":{"bits":[[0,7,21],[0,7,22],[0,7,17],[0,6,20],[0,7,18],[0,6,17],[0,6,16]],"values":{"NONE":[false,false,false,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false],"OUT.FAN5":[false,true,false,false,false,false,false],"OUT.FAN6":[false,false,true,false,false,true,false],"OUT.FAN7":[false,false,true,false,false,true,true],"OUT.SEC10":[false,false,false,false,true,true,false],"OUT.SEC11":[false,true,false,false,false,true,true],"OUT.SEC8":[false,false,true,false,false,false,false],"OUT.SEC9":[false,false,false,true,false,true,true]}},"INT:MUX.OMUX6":{"bits":[[0,6,26],[0,7,24],[0,7,31],[0,6,28],[0,6,29],[0,6,25],[0,6,24]],"values":{"NONE":[false,false,false,false,false,false,false],"OUT.FAN4":[true,false,false,false,false,false,false],"OUT.FAN5":[false,true,false,false,false,false,false],"OUT.FAN6":[false,false,true,false,false,true,false],"OUT.FAN7":[false,false,true,false,false,true,true],"OUT.SEC10":[false,fal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:[[0,1,11]],"invert":false},"OBUF0:INV.CLK":{"bits":[[0,3,14]],"invert":true},"OBUF0:INV.O":{"bits":[[0,1,0]],"invert":false},"OBUF0:INV.REV":{"bits":[[0,3,9]],"invert":true},"OBUF0:OMUX":{"bits":[[0,1,12],[0,1,15]],"values":{"NONE":[false,false],"O":[true,false],"OFF":[false,true]}},"OBUF1:FF_INIT":{"bits":[[0,1,24]],"invert":true},"OBUF1:FF_LATCH":{"bits":[[0,1,18]],"invert":false},"OBUF1:FF_REV_ENABLE":{"bits":[[0,1,22]],"invert":false},"OBUF1:FF_SRVAL":{"bits":[[0,1,27]],"invert":true},"OBUF1:FF_SR_ENABLE":{"bits":[[0,1,21]],"invert":false},"OBUF1:FF_SYNC":{"bits":[[0,1,20]],"invert":false},"OBUF1:INV.CLK":{"bits":[[0,3,18]],"invert":true},"OBUF1:INV.O":{"bits":[[0,1,26]],"invert":false},"OBUF1:INV.REV":{"bits":[[0,3,22]],"invert":true},"OBUF1:OMUX":{"bits":[[0,1,23],[0,1,25]],"values":{"NONE":[false,false],"O":[true,false],"OFF":[false,true]}},"OBUF2:FF_INIT":{"bits":[[0,1,39]],"invert":true},"OBUF2:FF_LATCH":{"bits":[[0,1,46]],"invert":false},"OBUF2:FF_REV_ENABLE":{"bits":[[0,1,41]],"invert":false},"OBUF2:FF_SRVAL":{"bits":[[0,1,35]],"invert":true},"OBUF2:FF_SR_ENABLE":{"bits":[[0,1,42]],"invert":false},"OBUF2:FF_SYNC":{"bits":[[0,1,43]],"invert":false},"OBUF2:INV.CLK":{"bits":[[0,3,46]],"invert":true},"OBUF2:INV.O":{"bits":[[0,1,32]],"invert":false},"OBUF2:INV.REV":{"bits":[[0,3,41]],"invert":true},"OBUF2:OMUX":{"bits":[[0,1,44],[0,1,47]],"values":{"NONE":[false,false],"O":[true,false],"OFF":[false,true]}},"OBUF3:FF_INIT":{"bits":[[0,1,56]],"invert":true},"OBUF3:FF_LATCH":{"bits":[[0,1,50]],"invert":false},"OBUF3:FF_REV_ENABLE":{"bits":[[0,1,54]],"invert":false},"OBUF3:FF_SRVAL":{"bits":[[0,1,59]],"invert":true},"OBUF3:FF_SR_ENABLE":{"bits":[[0,1,53]],"invert":false},"OBUF3:FF_SYNC":{"bits":[[0,1,52]],"invert":false},"OBUF3:INV.CLK":{"bits":[[0,3,50]],"invert":true},"OBUF3:INV.O":{"bits":[[0,1,58]],"invert":false},"OBUF3:INV.REV":{"bits":[[0,3,54]],"invert":true},"OBUF3:OMUX":{"bits":[[0,1,55],[0,1,57]],"values":{"NONE":[false,false],"O":[true,false],"OFF":[false,true]}}},"LL.FC":{"MISC:MISR_CLOCK":{"bits":[[0,0,1]],"invert":false},"MISC:MISR_RESET":{"bits":[[0,0,0]],"invert":false},"MISC:SEND_VGG":{"bits":[[0,1,8],[0,1,9],[0,1,10],[0,1,11]],"invert":false},"MISC:VGG_ENABLE_OFFCHIP":{"bits":[[0,1,13]],"invert":false},"MISC:VGG_SENDMAX":{"bits":[[0,1,12]],"invert":false}},"LR.FC":{"ICAP:ENABLE":{"bits":[[0,1,3]],"invert":false},"MISC:ABUFF":{"bits":[[0,0,40],[0,0,41],[0,0,42],[0,0,43]],"invert":false},"MISC:MISR_CLOCK":{"bits":[[0,0,1]],"invert":false},"MISC:MISR_RESET":{"bits":[[0,0,0]],"invert":false},"STARTUP:GSR_SYNC":{"bits":[[0,1,0]],"invert":false},"STARTUP:GTS_GSR_ENABLE":{"bits":[[0,1,4]],"invert":false},"STARTUP:GTS_SYNC":{"bits":[[0,1,1]],"invert":false}},"RANDOR":{"RANDOR:MODE":{"bits":[],"values":{"AND":[],"OR":[]}}},"RANDOR_INIT":{"RANDOR_INIT:MODE":{"bits":[[0,0,63]],"values":{"AND":[true],"OR":[false]}}},"REG.COR.FC":{"CAPTURE:ONESHOT":{"bits":[[0,0,23]],"invert":false},"STARTUP:BUSCLK_FREQ":{"bits":[[0,0,17],[0,0,18]],"values":{"100":[false,false],"200":[true,true],"25":[true,false],"50":[false,true]}},"STARTUP:CONFIG_RATE":{"bits":[[0,0,19],[0,0,20],[0,0,21]],"values":{"100":[false,true,true],"12":[true,false,false],"25":[false,true,false],"3":[false,false,true],"50":[true,true,false],"6":[false,false,false]}},"STARTUP:CRC":{"bits":[[0,0,29]],"invert":true},"STARTUP:DONE_CYCLE":{"bits":[[0,0,12],[0,0,13],[0,0,14]],"values":{"1":[false,false,false],"2":[true,false,false],"3":[false,true,false],"4":[true,true,false],"5":[false,false,true],"6":[true,false,true],"KEEP":[true,true,true]}},"STARTUP:DONE_PIPE":{"bits":[[0,0,25]],"invert":false},"STARTUP:DRIVE_DONE":{"bits":[[0,0,24]],"invert":false},"STARTUP:GTS_CYCLE":{"bits":[[0,0,3],[0,0,4],[0,0,5]],"values":{"1":[false,false,false],"2":[true,false,false],"3":[false,true,false],"4":[true,true,false],"5":[false,false,true],"6":[true,false,true],"DONE":[false,true,true],"KEEP":[true,true,true]}},"STARTUP:GWE_CYCLE":{"bits":[[0,0,0],[0,0,1],[0,0,2]],"values":{"1":[false,false,false],"2":[true,false,false],"3":[false,true,false],"4":[true,true,false],"5":[false,false,true],"6":[true,false,true],"DONE":[false,true,true],"KEEP":[true,true,true]}},"STARTUP:STARTUPCLK":{"bits":[[0,0,15],[0,0,16]],"values":{"CCLK":[false,false],"JTAGCLK":[false,true],"USERCLK":[true,false]}},"STARTUP:VRDSEL":{"bits":[[0,0,30],[0,0,31]],"values":{"100":[false,false],"80":[true,true],"90":[false,true],"95":[true,false]}}},"REG.CTL.S3":{"MISC:BCLK_TEST":{"bits":[[0,0,2]],"invert":false},"MISC:GTS_USR_B":{"bits":[[0,0,0]],"invert":false},"MISC:PERSIST":{"bits":[[0,0,3]],"invert":false},"MISC:SECURITY":{"bits":[[0,0,4],[0,0,5]],"values":{"LEVEL1":[true,false],"LEVEL2":[false,true],"NONE":[false,false]}},"MISC:VGG_TEST":{"bits":[[0,0,1]],"invert":false}},"UL.FC":{"MISC:MISR_CLOCK":{"bits":[[0,0,1]],"invert":false},"MISC:MISR_RESET":{"bits":[[0,0,0]],"invert":false},"MISC:TEST_LL":{"bits":[[0,1,32]],"invert":false}},"UR.FC":{"BSCAN:TDO_ENABLE":{"bits":[[0,0,16],[0,1,16]],"invert":false},"BSCAN:USERID":{"bits":[[0,1,32],[0,0,32],[0,1,31],[0,0,31],[0,1,30],[0,0,30],[0,1,29],[0,0,29],[0,1,28],[0,0,28],[0,1,27],[0,0,27],[0,1,26],[0,0,26],[0,1,25],[0,0,25],[0,1,24],[0,0,24],[0,1,23],[0,0,23],[0,1,22],[0,0,22],[0,1,21],[0,0,21],[0,0,20],[0,1,20],[0,1,19],[0,0,19],[0,0,18],[0,1,18],[0,1,17],[0,0,17]],"invert":true},"MISC:MISR_CLOCK":{"bits":[[0,0,1]],"invert":false},"MISC:MISR_RESET":{"bits":[[0,0,0]],"invert":false}}}}
\ No newline at end of file
diff --git a/docs/gen_xilinx.py b/docs/gen_xilinx.py
index 22c259ea..314874d2 100644
--- a/docs/gen_xilinx.py
+++ b/docs/gen_xilinx.py
@@ -1,6 +1,6 @@
 import json
 
-for kind in ["xc5k", "xcv", "xc2v", "xc3s", "xc6s", "xc4v", "xc5v", "xc6v", "xc7v"]:
+for kind in ["xc5k", "xcv", "xc2v", "xc3s", "xcexf", "xc6s", "xc4v", "xc5v", "xc6v", "xc7v"]:
     with open(f"../databases/{kind}-tiledb.json") as dbf:
         db = json.load(dbf)
 
diff --git a/docs/xilinx/fpgacore/clb.rst b/docs/xilinx/fpgacore/clb.rst
new file mode 100644
index 00000000..9e81a6d1
--- /dev/null
+++ b/docs/xilinx/fpgacore/clb.rst
@@ -0,0 +1,39 @@
+.. _fpgacore-clb:
+
+Configurable Logic Block
+########################
+
+The CLB is identical to Spartan 3.
+
+
+Bitstream
+=========
+
+The data for a CLB is located in the same bitstream tile as the associated ``INT.CLB`` tile.
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-CLB.html
+
+
+``RESERVED_ANDOR``
+==================
+
+TODO: wtf is this even
+
+
+``RANDOR``
+----------
+
+This tile overlaps ``IOI.*``.
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-RANDOR.html
+
+
+``RANDOR_INIT``
+---------------
+
+This tile overlaps top-left interconnect tile.
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-RANDOR_INIT.html
diff --git a/docs/xilinx/fpgacore/clock.rst b/docs/xilinx/fpgacore/clock.rst
new file mode 100644
index 00000000..1732a94b
--- /dev/null
+++ b/docs/xilinx/fpgacore/clock.rst
@@ -0,0 +1,78 @@
+.. _fpgacore-clock:
+
+Clock interconnect
+##################
+
+.. todo:: document
+
+
+Clock source — spine bottom and top
+===================================
+
+.. todo:: document
+
+
+Bitstream — bottom tiles
+------------------------
+
+.. todo:: document
+
+
+``CLKB.FC``
++++++++++++
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-CLKB.FC.html
+
+
+Bitstream — top tiles
+---------------------
+
+.. todo:: document
+
+
+``CLKT.FC``
++++++++++++
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-CLKT.FC.html
+
+
+The ``CLKC`` clock center tile
+==============================
+
+.. todo:: document
+
+
+The ``GCLKVM`` secondary clock center tiles
+===========================================
+
+The ``GCLKVM`` tiles are located on the intersection of secondary vertical clock spines and the horizontal clock spine.
+
+.. todo:: document
+
+
+``GCLKVM.S3``
+-------------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-GCLKVM.S3.html
+
+
+The ``GCLKVC`` clock spine distribution tiles
+=============================================
+
+.. todo:: document
+
+
+The ``GCLKH`` clock row distribution tiles
+==========================================
+
+.. todo:: document
+
+
+``GCLKH``
+---------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-GCLKH.html
diff --git a/docs/xilinx/fpgacore/config.rst b/docs/xilinx/fpgacore/config.rst
new file mode 100644
index 00000000..1d2ac732
--- /dev/null
+++ b/docs/xilinx/fpgacore/config.rst
@@ -0,0 +1,20 @@
+.. _fpgacore-config:
+
+Configuration registers
+#######################
+
+.. todo:: document
+
+
+``COR.FC``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-REG.COR.FC.html
+
+
+``CTL.S3``
+==========
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-REG.CTL.S3.html
diff --git a/docs/xilinx/fpgacore/corner.rst b/docs/xilinx/fpgacore/corner.rst
new file mode 100644
index 00000000..b8a061cb
--- /dev/null
+++ b/docs/xilinx/fpgacore/corner.rst
@@ -0,0 +1,58 @@
+.. _fpgacore-corner:
+
+Corners
+#######
+
+.. todo:: document
+
+
+Lower left
+==========
+
+.. todo:: document
+
+
+``LL.FC``
+---------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-LL.FC.html
+
+
+Upper left
+==========
+
+.. todo:: document
+
+
+``UL.FC``
+---------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-UL.FC.html
+
+
+Lower right
+===========
+
+.. todo:: document
+
+
+``LR.FC``
+---------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-LR.FC.html
+
+
+Upper right
+===========
+
+.. todo:: document
+
+
+``UR.FC``
+---------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-UR.FC.html
diff --git a/docs/xilinx/fpgacore/index.rst b/docs/xilinx/fpgacore/index.rst
new file mode 100644
index 00000000..9b9291f4
--- /dev/null
+++ b/docs/xilinx/fpgacore/index.rst
@@ -0,0 +1,15 @@
+FPGAcore
+########
+
+.. todo:: intro document, bitstream format, other tiles, jtag, ...
+
+.. toctree::
+   :maxdepth: 2
+   :caption: Contents:
+
+   interconnect
+   clb
+   clock
+   io
+   corner
+   config
diff --git a/docs/xilinx/fpgacore/interconnect.rst b/docs/xilinx/fpgacore/interconnect.rst
new file mode 100644
index 00000000..0a582d1e
--- /dev/null
+++ b/docs/xilinx/fpgacore/interconnect.rst
@@ -0,0 +1,29 @@
+.. _fpgacore-interconnect:
+
+General interconnect
+####################
+
+FPGAcore interconnect is identical to Spartan 3 with one exception: there are 12 long lines for each orientation instead of 24.
+
+
+Bitstream — interconnect tiles
+==============================
+
+The interconnect tiles are 19×64 bits. The space on the left is unused by the interconnect tile, and contains data for whatever primitive is associated with the interconnect tile.
+
+``INT.CLB``
+-----------
+
+Used with ``CLB`` tiles.
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-INT.CLB.html
+
+
+``INT.IOI.FC``
+--------------
+
+Used with ``IOI`` tiles.
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-INT.IOI.FC.html
diff --git a/docs/xilinx/fpgacore/io.rst b/docs/xilinx/fpgacore/io.rst
new file mode 100644
index 00000000..be14d080
--- /dev/null
+++ b/docs/xilinx/fpgacore/io.rst
@@ -0,0 +1,53 @@
+.. _fpgacore-io:
+
+Input / Output
+##############
+
+.. todo:: document
+
+
+I/O interface
+=============
+
+.. todo:: document
+
+
+``IOI.FC``
+----------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-IOI.FC.html
+
+
+I/O buffers — Spartan 3
+=======================
+
+.. todo:: document
+
+
+``IOBS.FC.T``
+-------------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-IOBS.FC.T.html
+
+
+``IOBS.FC.R``
+-------------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-IOBS.FC.R.html
+
+
+``IOBS.FC.B``
+-------------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-IOBS.FC.B.html
+
+
+``IOBS.FC.L``
+-------------
+
+.. raw:: html
+   :file: ../gen/tile-xcexf-IOBS.FC.L.html
diff --git a/docs/xilinx/index.rst b/docs/xilinx/index.rst
index e3549b9e..86f23cf2 100644
--- a/docs/xilinx/index.rst
+++ b/docs/xilinx/index.rst
@@ -9,6 +9,7 @@ Xilinx FPGAs
    virtex/index
    virtex2/index
    spartan3/index
+   fpgacore/index
    spartan6/index
    virtex4/index
    virtex5/index
diff --git a/docs/xilinx/virtex/dll.rst b/docs/xilinx/virtex/dll.rst
index 830c8a6b..fde765f1 100644
--- a/docs/xilinx/virtex/dll.rst
+++ b/docs/xilinx/virtex/dll.rst
@@ -1,3 +1,5 @@
+.. _virtex-dll:
+
 Delay Locked Loop
 #################
 
diff --git a/prjcombine_ise_dump/src/bin/dump_ise_parts.rs b/prjcombine_ise_dump/src/bin/dump_ise_parts.rs
index a8720405..e4cd1fba 100644
--- a/prjcombine_ise_dump/src/bin/dump_ise_parts.rs
+++ b/prjcombine_ise_dump/src/bin/dump_ise_parts.rs
@@ -65,6 +65,7 @@ fn main() -> Result<(), Box<dyn Error>> {
             "virtex2" => vec!["virtex2", "qvirtex2", "qrvirtex2"],
             "virtex2p" => vec!["virtex2p", "qvirtex2p"],
             "spartan3" => vec!["spartan3", "aspartan3"],
+            "fpgacore" => vec!["fpgacore"],
             "spartan3e" => vec!["spartan3e", "aspartan3e"],
             "spartan3a" => vec!["spartan3a", "aspartan3a"],
             "spartan3adsp" => vec!["spartan3adsp", "aspartan3adsp"],
diff --git a/prjcombine_ise_dump/src/partgen.rs b/prjcombine_ise_dump/src/partgen.rs
index 15b05b08..f5580c38 100644
--- a/prjcombine_ise_dump/src/partgen.rs
+++ b/prjcombine_ise_dump/src/partgen.rs
@@ -151,6 +151,7 @@ const PATTERNS: &[(&str, &str, &str)] = &[
     ("x[cq]2vpx?[0-9]+", "[a-z]{2}[0-9]+", "virtex2p"),
     ("xc3s[0-9]+l?", "[a-z]{2}[0-9]+", "spartan3"),
     ("xa3s[0-9]+l?", "[a-z]{2}g[0-9]+", "spartan3"),
+    ("xcexf[0-9]+", "die", "fpgacore"),
     ("xc3s[0-9]+e", "[a-z]{2}[0-9]+", "spartan3e"),
     ("xa3s[0-9]+e", "[a-z]{2}g[0-9]+", "spartan3e"),
     ("xc3s[0-9]+a", "[a-z]{2}[0-9]+", "spartan3a"),
diff --git a/prjcombine_ise_hammer/src/bram/spartan6.rs b/prjcombine_ise_hammer/src/bram/spartan6.rs
index d862990b..e50a701a 100644
--- a/prjcombine_ise_hammer/src/bram/spartan6.rs
+++ b/prjcombine_ise_hammer/src/bram/spartan6.rs
@@ -6,7 +6,7 @@ use prjcombine_types::TileItem;
 
 use crate::{
     backend::IseBackend,
-    diff::{xlat_bitvec, xlat_bool, xlat_enum, CollectorCtx},
+    diff::{xlat_bit, xlat_bitvec, xlat_bool, xlat_enum, CollectorCtx},
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_inv, fuzz_multi, fuzz_multi_attr_hex, fuzz_one, fuzz_one_extras,
@@ -421,10 +421,8 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         let diff1_h0 = ctx.state.get_diff(tile, "BRAM_H0", attr, val1);
         let diff1_h1 = ctx.state.get_diff(tile, "BRAM_H1", attr, val1);
         assert_eq!(diff1_f, diff1_h0.combine(&diff1_h1));
-        ctx.tiledb
-            .insert(tile, "BRAM_H0", attr, xlat_bitvec(vec![diff1_h0]));
-        ctx.tiledb
-            .insert(tile, "BRAM_H1", attr, xlat_bitvec(vec![diff1_h1]));
+        ctx.tiledb.insert(tile, "BRAM_H0", attr, xlat_bit(diff1_h0));
+        ctx.tiledb.insert(tile, "BRAM_H1", attr, xlat_bit(diff1_h1));
     }
     for (attr, bel, sattr) in [
         ("BW_EN_A", "BRAM_H0", "BW_EN_A_D"),
@@ -433,7 +431,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         ("BW_EN_B", "BRAM_H1", "BW_EN_B_U"),
     ] {
         let diff = ctx.state.get_diff(tile, "BRAM_F", sattr, "1");
-        ctx.tiledb.insert(tile, bel, attr, xlat_bitvec(vec![diff]));
+        ctx.tiledb.insert(tile, bel, attr, xlat_bit(diff));
     }
 
     for (attr, bel, sattr) in [
diff --git a/prjcombine_ise_hammer/src/bram/virtex2.rs b/prjcombine_ise_hammer/src/bram/virtex2.rs
index 8a18cb54..c620ea14 100644
--- a/prjcombine_ise_hammer/src/bram/virtex2.rs
+++ b/prjcombine_ise_hammer/src/bram/virtex2.rs
@@ -7,7 +7,7 @@ use unnamed_entity::EntityId;
 
 use crate::{
     backend::IseBackend,
-    diff::{extract_bitvec_val, xlat_bitvec, xlat_enum, CollectorCtx, Diff},
+    diff::{extract_bitvec_val, xlat_bit, xlat_bitvec, xlat_enum, CollectorCtx, Diff},
     fgen::TileBits,
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_multi, fuzz_one,
@@ -21,6 +21,7 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
     let tile_name = match grid_kind {
         GridKind::Virtex2 | GridKind::Virtex2P | GridKind::Virtex2PX => "BRAM",
         GridKind::Spartan3 => "BRAM.S3",
+        GridKind::FpgaCore => unreachable!(),
         GridKind::Spartan3E => "BRAM.S3E",
         GridKind::Spartan3A => "BRAM.S3A",
         GridKind::Spartan3ADsp => "BRAM.S3ADSP",
@@ -334,6 +335,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     let int_tiles = match grid_kind {
         GridKind::Virtex2 | GridKind::Virtex2P | GridKind::Virtex2PX => &["INT.BRAM"; 4],
         GridKind::Spartan3 => &["INT.BRAM.S3"; 4],
+        GridKind::FpgaCore => unreachable!(),
         GridKind::Spartan3E => &["INT.BRAM.S3E"; 4],
         GridKind::Spartan3A => &[
             "INT.BRAM.S3A.03",
@@ -346,6 +348,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     let tile = match grid_kind {
         GridKind::Virtex2 | GridKind::Virtex2P | GridKind::Virtex2PX => "BRAM",
         GridKind::Spartan3 => "BRAM.S3",
+        GridKind::FpgaCore => unreachable!(),
         GridKind::Spartan3E => "BRAM.S3E",
         GridKind::Spartan3A => "BRAM.S3A",
         GridKind::Spartan3ADsp => "BRAM.S3ADSP",
@@ -583,9 +586,8 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             let f_clk_b = ctx.state.get_diff(tile, "MULT", "CLKINV", "CLK_B");
             let (f_clk, f_clk_b, f_reg) = Diff::split(f_clk, f_clk_b);
             f_clk.assert_empty();
-            ctx.tiledb
-                .insert(tile, "MULT", "REG", xlat_bitvec(vec![f_reg]));
-            ctx.insert_int_inv(int_tiles, tile, "MULT", "CLK", xlat_bitvec(vec![f_clk_b]));
+            ctx.tiledb.insert(tile, "MULT", "REG", xlat_bit(f_reg));
+            ctx.insert_int_inv(int_tiles, tile, "MULT", "CLK", xlat_bit(f_clk_b));
             ctx.collect_int_inv(int_tiles, tile, "MULT", "CE", grid_kind.is_virtex2());
             ctx.collect_int_inv(int_tiles, tile, "MULT", "RST", grid_kind.is_virtex2());
             present.discard_bits(&ctx.item_int_inv(int_tiles, tile, "MULT", "CE"));
diff --git a/prjcombine_ise_hammer/src/bram/virtex5.rs b/prjcombine_ise_hammer/src/bram/virtex5.rs
index f5c5b5ed..9c9744b4 100644
--- a/prjcombine_ise_hammer/src/bram/virtex5.rs
+++ b/prjcombine_ise_hammer/src/bram/virtex5.rs
@@ -3,7 +3,7 @@ use prjcombine_hammer::Session;
 
 use crate::{
     backend::IseBackend,
-    diff::{xlat_bitvec, xlat_enum, xlat_enum_int, CollectorCtx, Diff},
+    diff::{xlat_bit, xlat_bitvec, xlat_enum, xlat_enum_int, CollectorCtx, Diff},
     fgen::TileBits,
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_enum_suffix, fuzz_inv_suffix, fuzz_multi, fuzz_one,
@@ -460,7 +460,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             .state
             .get_diff(tile, bel, "PRESENT", format!("FIFO36_EXP.{opt}"));
         diff = diff.combine(&!&present_fifo36);
-        ctx.tiledb.insert(tile, bel, opt, xlat_bitvec(vec![diff]));
+        ctx.tiledb.insert(tile, bel, opt, xlat_bit(diff));
     }
     let mut diffs = vec![("NONE", Diff::default())];
     for val in ["WW0", "WW1"] {
@@ -550,9 +550,9 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         if matches!(val, "1010" | "1111") {
             let (diff_l, diff_u) = split_diff_ul(diff);
             ctx.tiledb
-                .insert(tile, bel, "TSCRUB_DLY_L", xlat_bitvec(vec![diff_l]));
+                .insert(tile, bel, "TSCRUB_DLY_L", xlat_bit(diff_l));
             ctx.tiledb
-                .insert(tile, bel, "TSCRUB_DLY_U", xlat_bitvec(vec![diff_u]));
+                .insert(tile, bel, "TSCRUB_DLY_U", xlat_bit(diff_u));
         } else {
             diff.assert_empty();
         }
@@ -723,7 +723,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                 .get_diff(tile, bel, format!("EN_ECC_WRITE.{mode}"), "TRUE");
             diff.apply_bit_diff(&item, true, false);
             ctx.tiledb
-                .insert(tile, bel, "EN_ECC_WRITE_NO_READ", xlat_bitvec(vec![diff]));
+                .insert(tile, bel, "EN_ECC_WRITE_NO_READ", xlat_bit(diff));
         }
         ctx.tiledb.insert(tile, bel, "EN_ECC_WRITE", item);
     }
@@ -1061,8 +1061,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             .get_diff(tile, bel, format!("EN_SYN.{mode}"), "TRUE");
         diff.apply_enum_diff(ctx.tiledb.item(tile, bel, "DOA_REG_L"), "0", "1");
         diff.apply_enum_diff(ctx.tiledb.item(tile, bel, "DOB_REG_L"), "0", "1");
-        ctx.tiledb
-            .insert(tile, bel, "EN_SYN", xlat_bitvec(vec![diff]));
+        ctx.tiledb.insert(tile, bel, "EN_SYN", xlat_bit(diff));
     }
     for mode in ["FIFO36_EXP", "FIFO36_72_EXP"] {
         let mut diff = ctx
@@ -1072,8 +1071,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         diff.apply_enum_diff(ctx.tiledb.item(tile, bel, "DOA_REG_U"), "0", "1");
         diff.apply_enum_diff(ctx.tiledb.item(tile, bel, "DOB_REG_L"), "0", "1");
         diff.apply_enum_diff(ctx.tiledb.item(tile, bel, "DOB_REG_U"), "0", "1");
-        ctx.tiledb
-            .insert(tile, bel, "EN_SYN", xlat_bitvec(vec![diff]));
+        ctx.tiledb.insert(tile, bel, "EN_SYN", xlat_bit(diff));
     }
     let mut d0 = ctx.state.get_diff(tile, bel, "DO_REG_U.RAMBFIFO18_36", "0");
     let mut d1 = ctx.state.get_diff(tile, bel, "DO_REG_U.RAMBFIFO18_36", "1");
@@ -1218,7 +1216,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                 );
                 if ab == 'A' {
                     ctx.tiledb
-                        .insert(tile, bel, format!("{rw}_SDP_{ul}"), xlat_bitvec(vec![diff]));
+                        .insert(tile, bel, format!("{rw}_SDP_{ul}"), xlat_bit(diff));
                 } else {
                     diff.assert_empty();
                 }
@@ -1365,5 +1363,5 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
 
     assert_eq!(present_fifo36, present_fifo36_72);
     ctx.tiledb
-        .insert(tile, bel, "IS_FIFO_U", xlat_bitvec(vec![present_fifo36]));
+        .insert(tile, bel, "IS_FIFO_U", xlat_bit(present_fifo36));
 }
diff --git a/prjcombine_ise_hammer/src/bram/virtex6.rs b/prjcombine_ise_hammer/src/bram/virtex6.rs
index 107a0544..c6cac54b 100644
--- a/prjcombine_ise_hammer/src/bram/virtex6.rs
+++ b/prjcombine_ise_hammer/src/bram/virtex6.rs
@@ -5,7 +5,7 @@ use prjcombine_xilinx_geom::ExpandedDevice;
 
 use crate::{
     backend::IseBackend,
-    diff::{xlat_bitvec, xlat_enum, xlat_enum_int, CollectorCtx},
+    diff::{xlat_bit, xlat_bitvec, xlat_enum, xlat_enum_int, CollectorCtx},
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_enum_suffix, fuzz_inv, fuzz_multi_attr_hex, fuzz_multi_extras, fuzz_one,
@@ -1059,12 +1059,8 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     .state
                     .peek_diff(tile, bel, format!("{rw}_WIDTH_{ba}"), "18"),
             );
-            ctx.tiledb.insert(
-                tile,
-                "BRAM",
-                format!("{rw}_SDP_{ul}"),
-                xlat_bitvec(vec![diff]),
-            );
+            ctx.tiledb
+                .insert(tile, "BRAM", format!("{rw}_SDP_{ul}"), xlat_bit(diff));
         }
         for val in ["0", "1", "2", "4", "9", "18", "36"] {
             let diff = ctx
@@ -1140,7 +1136,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                 tile,
                 "BRAM",
                 format!("{rw}_MUX_UL_{ab}"),
-                xlat_bitvec(vec![diff_mux]),
+                xlat_bit(diff_mux),
             );
         }
     }
@@ -1267,12 +1263,8 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                 .assert_empty();
             let mut diff = ctx.state.get_diff(tile, bel, "EN_ECC_WRITE", "TRUE");
             diff.apply_bit_diff(&item, true, false);
-            ctx.tiledb.insert(
-                tile,
-                "BRAM",
-                "EN_ECC_WRITE_NO_READ",
-                xlat_bitvec(vec![diff]),
-            );
+            ctx.tiledb
+                .insert(tile, "BRAM", "EN_ECC_WRITE_NO_READ", xlat_bit(diff));
         }
         ctx.tiledb.insert(tile, "BRAM", "EN_ECC_WRITE", item);
     }
@@ -1359,9 +1351,9 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     present_ramb18_u.assert_empty();
     let is_fifo_u = present_fifo36.combine(&!&present_fifo18);
     ctx.tiledb
-        .insert(tile, "BRAM", "IS_FIFO", xlat_bitvec(vec![present_fifo18]));
+        .insert(tile, "BRAM", "IS_FIFO", xlat_bit(present_fifo18));
     ctx.tiledb
-        .insert(tile, "BRAM", "IS_FIFO_U", xlat_bitvec(vec![is_fifo_u]));
+        .insert(tile, "BRAM", "IS_FIFO_U", xlat_bit(is_fifo_u));
 
     for (bel, attr) in [
         ("BRAM_F", "BYPASS_RSR"),
diff --git a/prjcombine_ise_hammer/src/clb.rs b/prjcombine_ise_hammer/src/clb.rs
index f7aaa18e..c24c3eca 100644
--- a/prjcombine_ise_hammer/src/clb.rs
+++ b/prjcombine_ise_hammer/src/clb.rs
@@ -1,4 +1,4 @@
-pub mod xc5200;
 pub mod virtex;
 pub mod virtex2;
 pub mod virtex5;
+pub mod xc5200;
diff --git a/prjcombine_ise_hammer/src/clb/virtex.rs b/prjcombine_ise_hammer/src/clb/virtex.rs
index a9bfd6ed..c9cfc129 100644
--- a/prjcombine_ise_hammer/src/clb/virtex.rs
+++ b/prjcombine_ise_hammer/src/clb/virtex.rs
@@ -3,7 +3,7 @@ use prjcombine_types::TileItem;
 
 use crate::{
     backend::{FeatureBit, IseBackend},
-    diff::{xlat_bitvec, xlat_bool, xlat_enum, CollectorCtx},
+    diff::{xlat_bit, xlat_bool, xlat_enum, CollectorCtx},
     fgen::TileBits,
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_multi,
@@ -330,19 +330,17 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         ctx.state
             .get_diff(tile, bel, "SYNC_ATTR", "ASYNC")
             .assert_empty();
-        ctx.tiledb
-            .insert(tile, bel, "FF_SYNC", xlat_bitvec(vec![ff_sync]));
+        ctx.tiledb.insert(tile, bel, "FF_SYNC", xlat_bit(ff_sync));
 
         let revused = ctx.state.get_diff(tile, bel, "REVUSED", "0");
         ctx.tiledb
-            .insert(tile, bel, "FF_REV_ENABLE", xlat_bitvec(vec![revused]));
+            .insert(tile, bel, "FF_REV_ENABLE", xlat_bit(revused));
 
         let ff_latch = ctx.state.get_diff(tile, bel, "FFX", "#LATCH");
         assert_eq!(ff_latch, ctx.state.get_diff(tile, bel, "FFY", "#LATCH"));
         ctx.state.get_diff(tile, bel, "FFX", "#FF").assert_empty();
         ctx.state.get_diff(tile, bel, "FFY", "#FF").assert_empty();
-        ctx.tiledb
-            .insert(tile, bel, "FF_LATCH", xlat_bitvec(vec![ff_latch]));
+        ctx.tiledb.insert(tile, bel, "FF_LATCH", xlat_bit(ff_latch));
 
         ctx.collect_enum_bool(tile, bel, "INITX", "LOW", "HIGH");
         ctx.collect_enum_bool(tile, bel, "INITY", "LOW", "HIGH");
diff --git a/prjcombine_ise_hammer/src/clb/virtex2.rs b/prjcombine_ise_hammer/src/clb/virtex2.rs
index f4d63aff..4fb888b4 100644
--- a/prjcombine_ise_hammer/src/clb/virtex2.rs
+++ b/prjcombine_ise_hammer/src/clb/virtex2.rs
@@ -3,7 +3,7 @@ use prjcombine_xilinx_geom::ExpandedDevice;
 
 use crate::{
     backend::IseBackend,
-    diff::{xlat_bitvec, xlat_enum, CollectorCtx, Diff},
+    diff::{xlat_bit, xlat_enum, CollectorCtx, Diff},
     fgen::{TileBits, TileKV},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_inv, fuzz_multi, fuzz_one,
@@ -658,19 +658,15 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             let g_ram = ctx.state.get_diff("CLB", bel, "G", "#RAM:0");
             let (f_ram, g_ram, ram) = Diff::split(f_ram, g_ram);
             ctx.tiledb
-                .insert("CLB", bel, "FF_SR_ENABLE", xlat_bitvec(vec![!ram]));
+                .insert("CLB", bel, "FF_SR_ENABLE", xlat_bit(!ram));
             let f_shift_d = ctx.state.get_diff("CLB", bel, "F_ATTR", "SHIFT_REG");
             let g_shift_d = ctx.state.get_diff("CLB", bel, "G_ATTR", "SHIFT_REG");
             let f_shift = f_ram.combine(&f_shift_d);
             let g_shift = g_ram.combine(&g_shift_d);
-            ctx.tiledb
-                .insert("CLB", bel, "F_RAM", xlat_bitvec(vec![f_ram]));
-            ctx.tiledb
-                .insert("CLB", bel, "G_RAM", xlat_bitvec(vec![g_ram]));
-            ctx.tiledb
-                .insert("CLB", bel, "F_SHIFT", xlat_bitvec(vec![f_shift]));
-            ctx.tiledb
-                .insert("CLB", bel, "G_SHIFT", xlat_bitvec(vec![g_shift]));
+            ctx.tiledb.insert("CLB", bel, "F_RAM", xlat_bit(f_ram));
+            ctx.tiledb.insert("CLB", bel, "G_RAM", xlat_bit(g_ram));
+            ctx.tiledb.insert("CLB", bel, "F_SHIFT", xlat_bit(f_shift));
+            ctx.tiledb.insert("CLB", bel, "G_SHIFT", xlat_bit(g_shift));
 
             let dif_bx = ctx.state.get_diff("CLB", bel, "DIF_MUX", "BX");
             let dif_alt = ctx.state.get_diff("CLB", bel, "DIF_MUX", "ALTDIF");
@@ -717,9 +713,9 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     );
                     // TODO should these have better names?
                     ctx.tiledb
-                        .insert("CLB", bel, "SLICEWE0USED", xlat_bitvec(vec![slicewe0used]));
+                        .insert("CLB", bel, "SLICEWE0USED", xlat_bit(slicewe0used));
                     ctx.tiledb
-                        .insert("CLB", bel, "BYOUTUSED", xlat_bitvec(vec![byoutused]));
+                        .insert("CLB", bel, "BYOUTUSED", xlat_bit(byoutused));
                 }
                 Mode::Spartan3 => {
                     ctx.state
@@ -731,14 +727,10 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     let slicewe0used = ctx.state.get_diff("CLB", bel, "SLICEWE0USED", "0");
                     let slicewe1used = ctx.state.get_diff("CLB", bel, "SLICEWE1USED", "0");
                     ctx.tiledb
-                        .insert("CLB", bel, "SLICEWE0USED", xlat_bitvec(vec![slicewe0used]));
+                        .insert("CLB", bel, "SLICEWE0USED", xlat_bit(slicewe0used));
                     if idx == 0 {
-                        ctx.tiledb.insert(
-                            "CLB",
-                            bel,
-                            "SLICEWE1USED",
-                            xlat_bitvec(vec![slicewe1used]),
-                        );
+                        ctx.tiledb
+                            .insert("CLB", bel, "SLICEWE1USED", xlat_bit(slicewe1used));
                     } else {
                         slicewe1used.assert_empty();
                     }
@@ -754,30 +746,14 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     let f_slicewe1used = ctx.state.get_diff("CLB", bel, "SLICEWE1USED.F", "0");
                     let g_slicewe0used = ctx.state.get_diff("CLB", bel, "SLICEWE0USED.G", "0");
                     let g_slicewe1used = ctx.state.get_diff("CLB", bel, "SLICEWE1USED.G", "0");
-                    ctx.tiledb.insert(
-                        "CLB",
-                        bel,
-                        "F_SLICEWE0USED",
-                        xlat_bitvec(vec![f_slicewe0used]),
-                    );
-                    ctx.tiledb.insert(
-                        "CLB",
-                        bel,
-                        "F_SLICEWE1USED",
-                        xlat_bitvec(vec![f_slicewe1used]),
-                    );
-                    ctx.tiledb.insert(
-                        "CLB",
-                        bel,
-                        "G_SLICEWE0USED",
-                        xlat_bitvec(vec![g_slicewe0used]),
-                    );
-                    ctx.tiledb.insert(
-                        "CLB",
-                        bel,
-                        "G_SLICEWE1USED",
-                        xlat_bitvec(vec![g_slicewe1used]),
-                    );
+                    ctx.tiledb
+                        .insert("CLB", bel, "F_SLICEWE0USED", xlat_bit(f_slicewe0used));
+                    ctx.tiledb
+                        .insert("CLB", bel, "F_SLICEWE1USED", xlat_bit(f_slicewe1used));
+                    ctx.tiledb
+                        .insert("CLB", bel, "G_SLICEWE0USED", xlat_bit(g_slicewe0used));
+                    ctx.tiledb
+                        .insert("CLB", bel, "G_SLICEWE1USED", xlat_bit(g_slicewe1used));
                 }
             }
         }
@@ -901,7 +877,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         ctx.state.get_diff("CLB", bel, "FFX", "#FF").assert_empty();
         ctx.state.get_diff("CLB", bel, "FFY", "#FF").assert_empty();
         ctx.tiledb
-            .insert("CLB", bel, "FF_LATCH", xlat_bitvec(vec![ff_latch]));
+            .insert("CLB", bel, "FF_LATCH", xlat_bit(ff_latch));
 
         let item = ctx.extract_bit("CLB", bel, "REVUSED", "0");
         ctx.tiledb.insert("CLB", bel, "FF_REV_ENABLE", item);
diff --git a/prjcombine_ise_hammer/src/clb/virtex5.rs b/prjcombine_ise_hammer/src/clb/virtex5.rs
index e28ae732..d0989634 100644
--- a/prjcombine_ise_hammer/src/clb/virtex5.rs
+++ b/prjcombine_ise_hammer/src/clb/virtex5.rs
@@ -3,7 +3,7 @@ use prjcombine_xilinx_geom::ExpandedDevice;
 
 use crate::{
     backend::IseBackend,
-    diff::{xlat_bitvec, xlat_enum, CollectorCtx, Diff, OcdMode},
+    diff::{xlat_bit, xlat_enum, CollectorCtx, Diff, OcdMode},
     fgen::{TileBits, TileRelation},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_inv, fuzz_multi, fuzz_one,
@@ -832,7 +832,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                 ctx.collect_enum(tile, bel, "WEMUX", &["WE", "CE"]);
                 for attr in ["WA7USED", "WA8USED"] {
                     let diff = ctx.state.get_diff(tile, bel, attr, "0");
-                    ctx.tiledb.insert(tile, bel, attr, xlat_bitvec(vec![diff]));
+                    ctx.tiledb.insert(tile, bel, attr, xlat_bit(diff));
                 }
                 let di_muxes = match mode {
                     Mode::Virtex5 | Mode::Spartan6 => [
@@ -1084,21 +1084,20 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             ctx.state
                 .get_diff(tile, bel, "SYNC_ATTR", "ASYNC")
                 .assert_empty();
-            ctx.tiledb
-                .insert(tile, bel, "FF_SYNC", xlat_bitvec(vec![ff_sync]));
+            ctx.tiledb.insert(tile, bel, "FF_SYNC", xlat_bit(ff_sync));
             ctx.collect_inv(tile, bel, "CLK");
             if mode == Mode::Virtex5 {
                 let revused = ctx.state.get_diff(tile, bel, "REVUSED", "0");
                 ctx.tiledb
-                    .insert(tile, bel, "FF_REV_ENABLE", xlat_bitvec(vec![revused]));
+                    .insert(tile, bel, "FF_REV_ENABLE", xlat_bit(revused));
             }
             if matches!(mode, Mode::Virtex5 | Mode::Spartan6) {
                 let ceused = ctx.state.get_diff(tile, bel, "CEUSED", "0");
                 ctx.tiledb
-                    .insert(tile, bel, "FF_CE_ENABLE", xlat_bitvec(vec![ceused]));
+                    .insert(tile, bel, "FF_CE_ENABLE", xlat_bit(ceused));
                 let srused = ctx.state.get_diff(tile, bel, "SRUSED", "0");
                 ctx.tiledb
-                    .insert(tile, bel, "FF_SR_ENABLE", xlat_bitvec(vec![srused]));
+                    .insert(tile, bel, "FF_SR_ENABLE", xlat_bit(srused));
             } else {
                 ctx.state
                     .get_diff(tile, bel, "CEUSEDMUX", "1")
@@ -1108,10 +1107,10 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     .assert_empty();
                 let ceused = ctx.state.get_diff(tile, bel, "CEUSEDMUX", "IN");
                 ctx.tiledb
-                    .insert(tile, bel, "FF_CE_ENABLE", xlat_bitvec(vec![ceused]));
+                    .insert(tile, bel, "FF_CE_ENABLE", xlat_bit(ceused));
                 let srused = ctx.state.get_diff(tile, bel, "SRUSEDMUX", "IN");
                 ctx.tiledb
-                    .insert(tile, bel, "FF_SR_ENABLE", xlat_bitvec(vec![srused]));
+                    .insert(tile, bel, "FF_SR_ENABLE", xlat_bit(srused));
             }
             if mode != Mode::Virtex6 {
                 let ff_latch = ctx.state.get_diff(tile, bel, "AFF", "#LATCH");
@@ -1125,20 +1124,15 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                         assert_eq!(ff_latch, ctx.state.get_diff(tile, bel, attr, "OR2L"));
                     }
                 }
-                ctx.tiledb
-                    .insert(tile, bel, "FF_LATCH", xlat_bitvec(vec![ff_latch]));
+                ctx.tiledb.insert(tile, bel, "FF_LATCH", xlat_bit(ff_latch));
             } else {
                 for attr in ["AFF", "BFF", "CFF", "DFF"] {
                     ctx.state.get_diff(tile, bel, attr, "#FF").assert_empty();
                     let ff_latch = ctx.state.get_diff(tile, bel, attr, "#LATCH");
                     assert_eq!(ff_latch, ctx.state.get_diff(tile, bel, attr, "AND2L"));
                     assert_eq!(ff_latch, ctx.state.get_diff(tile, bel, attr, "OR2L"));
-                    ctx.tiledb.insert(
-                        tile,
-                        bel,
-                        format!("{attr}_LATCH"),
-                        xlat_bitvec(vec![ff_latch]),
-                    );
+                    ctx.tiledb
+                        .insert(tile, bel, format!("{attr}_LATCH"), xlat_bit(ff_latch));
                 }
             }
             match mode {
diff --git a/prjcombine_ise_hammer/src/clk/spartan6.rs b/prjcombine_ise_hammer/src/clk/spartan6.rs
index 0f11b1ff..0b57029b 100644
--- a/prjcombine_ise_hammer/src/clk/spartan6.rs
+++ b/prjcombine_ise_hammer/src/clk/spartan6.rs
@@ -8,7 +8,7 @@ use unnamed_entity::EntityId;
 
 use crate::{
     backend::IseBackend,
-    diff::{xlat_bit_wide, xlat_bitvec, xlat_enum, xlat_enum_ocd, CollectorCtx, OcdMode},
+    diff::{xlat_bit, xlat_bit_wide, xlat_enum, xlat_enum_ocd, CollectorCtx, OcdMode},
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits, TileKV},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_inv, fuzz_one, fuzz_one_extras,
@@ -928,8 +928,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                 .assert_empty();
             let diff = ctx.state.get_diff(tile, bel, "CMT_ENABLE", "1");
             assert_eq!(diff, ctx.state.get_diff(tile, bel_fb, "CMT_ENABLE", "1"));
-            ctx.tiledb
-                .insert(tile, bel, "CMT_ENABLE", xlat_bitvec(vec![diff]));
+            ctx.tiledb.insert(tile, bel, "CMT_ENABLE", xlat_bit(diff));
             ctx.collect_bit(tile, bel, "IOCLK_ENABLE", "1");
             ctx.collect_enum(tile, bel, "CKPIN", &["VCC", "DIVCLK", "CLKPIN"]);
             ctx.collect_enum_bool(tile, bel, "R_EDGE", "FALSE", "TRUE");
@@ -937,8 +936,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             let mut diff = ctx.state.get_diff(tile, bel, "PRESENT", "BUFIO2_2CLK");
             diff.apply_bit_diff(ctx.tiledb.item(tile, bel, "R_EDGE"), true, false);
             diff.apply_bit_diff(ctx.tiledb.item(tile, bel, "DIVIDE_BYPASS"), false, true);
-            ctx.tiledb
-                .insert(tile, bel, "ENABLE_2CLK", xlat_bitvec(vec![diff]));
+            ctx.tiledb.insert(tile, bel, "ENABLE_2CLK", xlat_bit(diff));
 
             let mut pos_edge = vec![];
             let mut pos_bits = HashSet::new();
@@ -985,8 +983,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             }
             ctx.tiledb
                 .insert(tile, bel, "I", xlat_enum_ocd(diffs, OcdMode::BitOrder));
-            ctx.tiledb
-                .insert(tile, bel, "ENABLE", xlat_bitvec(vec![enable]));
+            ctx.tiledb.insert(tile, bel, "ENABLE", xlat_bit(enable));
             ctx.collect_enum_ocd(
                 tile,
                 bel,
@@ -1016,8 +1013,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             }
             ctx.tiledb
                 .insert(tile, bel, "FB_I", xlat_enum_ocd(diffs, OcdMode::BitOrder));
-            ctx.tiledb
-                .insert(tile, bel, "FB_ENABLE", xlat_bitvec(vec![enable]));
+            ctx.tiledb.insert(tile, bel, "FB_ENABLE", xlat_bit(enable));
 
             let mut present = ctx.state.get_diff(tile, bel_fb, "PRESENT", "BUFIO2FB_2CLK");
             present.apply_bitvec_diff_int(ctx.tiledb.item(tile, bel, "FB_DIVIDE_BYPASS"), 0, 0xf);
@@ -1100,9 +1096,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                 ctx.collect_bit(tile, bel, "MISR_ENABLE", "1");
                 let mut diff = ctx.state.get_diff(tile, bel, "MISR_ENABLE_RESET", "1");
                 diff.apply_bit_diff(ctx.tiledb.item(tile, bel, "MISR_ENABLE"), true, false);
-                ctx.tiledb
-                    .insert(tile, bel, "MISR_RESET", xlat_bitvec(vec![diff]));
-
+                ctx.tiledb.insert(tile, bel, "MISR_RESET", xlat_bit(diff));
             } else {
                 // they're sometimes working, sometimes not, in nonsensical ways; just kill them
                 ctx.state.get_diff(tile, bel, "MISR_ENABLE", "1");
@@ -1132,8 +1126,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         assert_eq!(bits.len(), 1);
         for (_, diff) in &mut diffs {
             let enable = diff.split_bits(&bits);
-            ctx.tiledb
-                .insert(tile, bel, "ENABLE", xlat_bitvec(vec![enable]));
+            ctx.tiledb.insert(tile, bel, "ENABLE", xlat_bit(enable));
         }
         ctx.tiledb
             .insert(tile, bel, "PCI_CE_DELAY", xlat_enum(diffs));
diff --git a/prjcombine_ise_hammer/src/clk/virtex2.rs b/prjcombine_ise_hammer/src/clk/virtex2.rs
index 4e2c6eab..e9d2a1f0 100644
--- a/prjcombine_ise_hammer/src/clk/virtex2.rs
+++ b/prjcombine_ise_hammer/src/clk/virtex2.rs
@@ -6,7 +6,7 @@ use unnamed_entity::EntityId;
 
 use crate::{
     backend::IseBackend,
-    diff::{xlat_bitvec, xlat_enum, xlat_enum_default, CollectorCtx},
+    diff::{xlat_bit, xlat_enum, xlat_enum_default, CollectorCtx},
     fgen::{TileBits, TileKV},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_inv, fuzz_one,
@@ -24,6 +24,7 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
         GridKind::Virtex2P => ("CLKB.V2P", "CLKT.V2P"),
         GridKind::Virtex2PX => ("CLKB.V2PX", "CLKT.V2PX"),
         GridKind::Spartan3 => ("CLKB.S3", "CLKT.S3"),
+        GridKind::FpgaCore => ("CLKB.FC", "CLKT.FC"),
         GridKind::Spartan3E => ("CLKB.S3E", "CLKT.S3E"),
         GridKind::Spartan3A => ("CLKB.S3A", "CLKT.S3A"),
         GridKind::Spartan3ADsp => ("CLKB.S3A", "CLKT.S3A"),
@@ -31,37 +32,54 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
     let bufg_num = if grid_kind.is_virtex2() { 8 } else { 4 };
     for tile in [clkb, clkt] {
         for i in 0..bufg_num {
-            let ctx = FuzzCtx::new(
-                session,
-                backend,
-                tile,
-                format!("BUFGMUX{i}"),
-                TileBits::SpineEnd,
-            );
-            fuzz_one!(ctx, "PRESENT", "1", [(special TileKV::StabilizeGclkc)], [(mode "BUFGMUX")]);
-            fuzz_inv!(ctx, "S", [
-                (global_mutex "BUFG", "TEST"),
-                (mode "BUFGMUX"),
-                (attr "DISABLE_ATTR", "LOW")
-            ]);
-            fuzz_enum!(ctx, "DISABLE_ATTR", ["HIGH", "LOW"], [
-                (global_mutex "BUFG", "TEST"),
-                (mode "BUFGMUX"),
-                (pin "S")
-            ]);
-            let inps = if grid_kind.is_spartan3ea() {
-                &["CKIL", "CKIR", "DCM_OUT_L", "DCM_OUT_R"][..]
+            if edev.grid.kind != GridKind::FpgaCore {
+                let ctx = FuzzCtx::new(
+                    session,
+                    backend,
+                    tile,
+                    format!("BUFGMUX{i}"),
+                    TileBits::SpineEnd,
+                );
+                fuzz_one!(ctx, "PRESENT", "1", [(special TileKV::StabilizeGclkc)], [(mode "BUFGMUX")]);
+                fuzz_inv!(ctx, "S", [
+                    (global_mutex "BUFG", "TEST"),
+                    (mode "BUFGMUX"),
+                    (attr "DISABLE_ATTR", "LOW")
+                ]);
+                fuzz_enum!(ctx, "DISABLE_ATTR", ["HIGH", "LOW"], [
+                    (global_mutex "BUFG", "TEST"),
+                    (mode "BUFGMUX"),
+                    (pin "S")
+                ]);
+                let inps = if grid_kind.is_spartan3ea() {
+                    &["CKIL", "CKIR", "DCM_OUT_L", "DCM_OUT_R"][..]
+                } else {
+                    &["CKI", "DCM_OUT_L", "DCM_OUT_R"]
+                };
+                for &inp in inps {
+                    fuzz_one!(ctx, "MUX.CLK", inp, [
+                        (mutex "MUX.CLK", inp)
+                    ], [(pip (pin inp), (pin "CLK"))]);
+                }
+                fuzz_one!(ctx, "MUX.CLK", "INT", [
+                    (mutex "MUX.CLK", "INT")
+                ], [(pip (pin_far "CLK"), (pin "CLK"))]);
             } else {
-                &["CKI", "DCM_OUT_L", "DCM_OUT_R"]
-            };
-            for &inp in inps {
-                fuzz_one!(ctx, "MUX.CLK", inp, [
-                    (mutex "MUX.CLK", inp)
-                ], [(pip (pin inp), (pin "CLK"))]);
+                let ctx = FuzzCtx::new(
+                    session,
+                    backend,
+                    tile,
+                    format!("BUFG{i}"),
+                    TileBits::SpineEnd,
+                );
+                fuzz_one!(ctx, "PRESENT", "1", [], [(mode "BUFG")]);
+                fuzz_one!(ctx, "MUX.CLK", "CKI", [
+                    (mutex "MUX.CLK", "CKI")
+                ], [(pip (pin "CKI"), (pin "CLK"))]);
+                fuzz_one!(ctx, "MUX.CLK", "INT", [
+                    (mutex "MUX.CLK", "INT")
+                ], [(pip (pin_far "CLK"), (pin "CLK"))]);
             }
-            fuzz_one!(ctx, "MUX.CLK", "INT", [
-                (mutex "MUX.CLK", "INT")
-            ], [(pip (pin_far "CLK"), (pin "CLK"))]);
         }
         if grid_kind.is_virtex2() {
             let bels = if tile.starts_with("CLKB") {
@@ -238,13 +256,11 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
                 for bt in ["B", "T"] {
                     let out_name = format!("OUT_{bt}{i}");
                     let inp_name = format!("IN_CORE{i}");
-                    fuzz_one!(
-                        ctx,
-                        format!("BUF.{out_name}"),
-                        &inp_name,
-                        [],
-                        [(pip(pin & inp_name), (pin & out_name))]
-                    );
+                    fuzz_one!(ctx, format!("BUF.{out_name}"), &inp_name, [
+                        (global_mutex_none "MISR_CLOCK")
+                    ], [
+                        (pip(pin & inp_name), (pin & out_name))
+                    ]);
                 }
             }
         }
@@ -277,7 +293,7 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
         "GCLKH.0",
         "GCLKH.DSP",
     ] {
-        if tile != "GCLKH" && grid_kind.is_virtex2() {
+        if tile != "GCLKH" && (grid_kind.is_virtex2() || grid_kind == GridKind::FpgaCore) {
             continue;
         }
         let node_kind = backend.egrid.db.get_node(tile);
@@ -303,13 +319,12 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
                         continue;
                     }
                     let out_name = format!("OUT_{bt}{i}");
-                    fuzz_one!(
-                        ctx,
-                        &out_name,
-                        &inp_name,
-                        [(tile_mutex & inp_name, &out_name)],
-                        [(pip(pin & inp_name), (pin & out_name))]
-                    );
+                    fuzz_one!(ctx, &out_name, &inp_name, [
+                        (global_mutex_none "MISR_CLOCK"),
+                        (tile_mutex &inp_name, &out_name)
+                    ], [
+                        (pip (pin &inp_name), (pin &out_name))
+                    ]);
                 }
             }
         }
@@ -329,7 +344,7 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
         }
     }
 
-    if !grid_kind.is_spartan3ea() {
+    if !grid_kind.is_spartan3ea() && grid_kind != GridKind::FpgaCore {
         // DCMCONN
         for tile in ["DCMCONN.BOT", "DCMCONN.TOP"] {
             let mut ctx = FuzzCtx::new(
@@ -365,7 +380,8 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
                 );
             }
         }
-    } else {
+    }
+    if grid_kind.is_spartan3ea() {
         // PCI_CE_*
         for tile in ["PCI_CE_S", "PCI_CE_N", "PCI_CE_W", "PCI_CE_E", "PCI_CE_CNR"] {
             if let Some(ctx) = FuzzCtx::try_new(session, backend, tile, tile, TileBits::Null) {
@@ -377,7 +393,7 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
         }
     }
 
-    if !grid_kind.is_virtex2() {
+    if !grid_kind.is_virtex2() && grid_kind != GridKind::FpgaCore {
         // PTE2OMUX
         for tile in ["INT.DCM", "INT.DCM.S3E.DUMMY"] {
             let node_kind = backend.egrid.db.get_node(tile);
@@ -423,6 +439,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         GridKind::Virtex2P => ("CLKB.V2P", "CLKT.V2P"),
         GridKind::Virtex2PX => ("CLKB.V2PX", "CLKT.V2PX"),
         GridKind::Spartan3 => ("CLKB.S3", "CLKT.S3"),
+        GridKind::FpgaCore => ("CLKB.FC", "CLKT.FC"),
         GridKind::Spartan3E => ("CLKB.S3E", "CLKT.S3E"),
         GridKind::Spartan3A => ("CLKB.S3A", "CLKT.S3A"),
         GridKind::Spartan3ADsp => ("CLKB.S3A", "CLKT.S3A"),
@@ -430,28 +447,35 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     let bufg_num = if grid_kind.is_virtex2() { 8 } else { 4 };
     for tile in [clkb, clkt] {
         for i in 0..bufg_num {
-            let node_kind = intdb.get_node(tile);
-            let bel = &intdb.nodes[node_kind].bels[BelId::from_idx(i)];
-            let pin = &bel.pins["S"];
-            let bel = format!("BUFGMUX{i}");
-            let bel = &bel;
-            ctx.state.get_diff(tile, bel, "PRESENT", "1").assert_empty();
-            assert_eq!(pin.wires.len(), 1);
-            let wire = pin.wires.first().unwrap();
-            let sinv = ctx.extract_enum_bool(tile, bel, "SINV", "S", "S_B");
-            ctx.tiledb.insert(
-                tile,
-                "INT",
-                format!("INV.{}.{}", wire.0, intdb.wires.key(wire.1)),
-                sinv,
-            );
-            ctx.collect_enum(tile, bel, "DISABLE_ATTR", &["HIGH", "LOW"]);
-            let inps = if grid_kind.is_spartan3ea() {
-                &["INT", "CKIL", "CKIR", "DCM_OUT_L", "DCM_OUT_R"][..]
+            if edev.grid.kind != GridKind::FpgaCore {
+                let node_kind = intdb.get_node(tile);
+                let bel = &intdb.nodes[node_kind].bels[BelId::from_idx(i)];
+                let pin = &bel.pins["S"];
+                let bel = format!("BUFGMUX{i}");
+                let bel = &bel;
+                ctx.state.get_diff(tile, bel, "PRESENT", "1").assert_empty();
+                assert_eq!(pin.wires.len(), 1);
+                let wire = pin.wires.first().unwrap();
+                let sinv = ctx.extract_enum_bool(tile, bel, "SINV", "S", "S_B");
+                ctx.tiledb.insert(
+                    tile,
+                    "INT",
+                    format!("INV.{}.{}", wire.0, intdb.wires.key(wire.1)),
+                    sinv,
+                );
+                ctx.collect_enum(tile, bel, "DISABLE_ATTR", &["HIGH", "LOW"]);
+                let inps = if grid_kind.is_spartan3ea() {
+                    &["INT", "CKIL", "CKIR", "DCM_OUT_L", "DCM_OUT_R"][..]
+                } else {
+                    &["INT", "CKI", "DCM_OUT_L", "DCM_OUT_R"]
+                };
+                ctx.collect_enum(tile, bel, "MUX.CLK", inps);
             } else {
-                &["INT", "CKI", "DCM_OUT_L", "DCM_OUT_R"]
-            };
-            ctx.collect_enum(tile, bel, "MUX.CLK", inps);
+                let bel = format!("BUFG{i}");
+                let bel = &bel;
+                ctx.state.get_diff(tile, bel, "PRESENT", "1").assert_empty();
+                ctx.collect_enum(tile, bel, "MUX.CLK", &["INT", "CKI"]);
+            }
         }
     }
 
@@ -495,8 +519,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                 present.discard_bits(&item);
                 ctx.tiledb.insert(tile, bel, "DELAY", item);
             }
-            ctx.tiledb
-                .insert(tile, bel, "ENABLE", xlat_bitvec(vec![present]));
+            ctx.tiledb.insert(tile, bel, "ENABLE", xlat_bit(present));
         }
     }
 
@@ -578,7 +601,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         "GCLKH.UNI.S",
         "GCLKH.UNI.N",
     ] {
-        if tile != "GCLKH" && grid_kind.is_virtex2() {
+        if tile != "GCLKH" && (grid_kind.is_virtex2() || grid_kind == GridKind::FpgaCore) {
             continue;
         }
         let node_kind = intdb.get_node(tile);
@@ -618,7 +641,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         }
     }
 
-    if !grid_kind.is_virtex2() {
+    if !grid_kind.is_virtex2() && grid_kind != GridKind::FpgaCore {
         // PTE2OMUX
         for tile in ["INT.DCM", "INT.DCM.S3E.DUMMY"] {
             let node_kind = intdb.get_node(tile);
diff --git a/prjcombine_ise_hammer/src/clk/virtex4.rs b/prjcombine_ise_hammer/src/clk/virtex4.rs
index c1f3f77b..bd8be94b 100644
--- a/prjcombine_ise_hammer/src/clk/virtex4.rs
+++ b/prjcombine_ise_hammer/src/clk/virtex4.rs
@@ -5,7 +5,7 @@ use unnamed_entity::EntityId;
 
 use crate::{
     backend::IseBackend,
-    diff::{xlat_bit_wide, xlat_bitvec, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
+    diff::{xlat_bit, xlat_bit_wide, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
     fgen::{BelRelation, ExtraFeature, ExtraFeatureKind, TileBits, TileKV, TileRelation},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_one, fuzz_one_extras,
@@ -453,12 +453,8 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             };
             ctx.tiledb
                 .insert(tile, bel, giob, xlat_bit_wide(diff.clone()));
-            ctx.tiledb.insert(
-                term,
-                "CLK_TERM",
-                "GIOB_ENABLE",
-                xlat_bitvec(vec![diff_term.clone()]),
-            );
+            ctx.tiledb
+                .insert(term, "CLK_TERM", "GIOB_ENABLE", xlat_bit(diff_term.clone()));
         }
         for i in 0..32 {
             let mux = format!("MUX.MUXBUS{i}");
@@ -537,7 +533,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         }
         for (i, diff) in inp_diffs.into_iter().enumerate() {
             ctx.tiledb
-                .insert(tile, bel, format!("BUF.GCLK{i}"), xlat_bitvec(vec![diff]));
+                .insert(tile, bel, format!("BUF.GCLK{i}"), xlat_bit(diff));
         }
     }
     {
@@ -602,10 +598,8 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             let diff0 = ctx.state.get_diff(tile, bel, "BUF.VIOCLK0", "1");
             let diff1 = ctx.state.get_diff(tile, bel, "BUF.VIOCLK1", "1");
             let (diff0, diff1, diffc) = Diff::split(diff0, diff1);
-            ctx.tiledb
-                .insert(tile, bel, "BUF.VIOCLK0", xlat_bitvec(vec![diff0]));
-            ctx.tiledb
-                .insert(tile, bel, "BUF.VIOCLK1", xlat_bitvec(vec![diff1]));
+            ctx.tiledb.insert(tile, bel, "BUF.VIOCLK0", xlat_bit(diff0));
+            ctx.tiledb.insert(tile, bel, "BUF.VIOCLK1", xlat_bit(diff1));
             ctx.tiledb
                 .insert(tile, bel, "VIOCLK_ENABLE", xlat_bit_wide(diffc));
             let (has_s, has_n) = match tile {
@@ -679,36 +673,24 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     .state
                     .get_diff(tile, bel, format!("BUF.HCLK_{ud}{i}"), "1");
                 let diff = diff.combine(&!&hclk_giob);
-                ctx.tiledb.insert(
-                    tile,
-                    bel,
-                    format!("BUF.HCLK_{ud}{i}"),
-                    xlat_bitvec(vec![diff]),
-                );
+                ctx.tiledb
+                    .insert(tile, bel, format!("BUF.HCLK_{ud}{i}"), xlat_bit(diff));
             }
             for i in 0..16 {
                 let diff = ctx
                     .state
                     .get_diff(tile, bel, format!("BUF.GIOB_{ud}{i}"), "1");
                 let diff = diff.combine(&!&hclk_giob);
-                ctx.tiledb.insert(
-                    tile,
-                    bel,
-                    format!("BUF.GIOB_{ud}{i}"),
-                    xlat_bitvec(vec![diff]),
-                );
+                ctx.tiledb
+                    .insert(tile, bel, format!("BUF.GIOB_{ud}{i}"), xlat_bit(diff));
             }
             for i in 0..4 {
                 let diff = ctx
                     .state
                     .get_diff(tile, bel, format!("BUF.MGT_{ud}{i}"), "1");
                 let diff = diff.combine(&!&common_mgt);
-                ctx.tiledb.insert(
-                    tile,
-                    bel,
-                    format!("BUF.MGT_{ud}{i}"),
-                    xlat_bitvec(vec![diff]),
-                );
+                ctx.tiledb
+                    .insert(tile, bel, format!("BUF.MGT_{ud}{i}"), xlat_bit(diff));
             }
         }
         let hclk_giob = hclk_giob.combine(&!&common);
@@ -737,24 +719,16 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                 .state
                 .get_diff(tile, bel, format!("BUF.HCLK_{ud}{i}"), "1");
             let diff = diff.combine(&!&common);
-            ctx.tiledb.insert(
-                tile,
-                bel,
-                format!("BUF.HCLK_{ud}{i}"),
-                xlat_bitvec(vec![diff]),
-            );
+            ctx.tiledb
+                .insert(tile, bel, format!("BUF.HCLK_{ud}{i}"), xlat_bit(diff));
         }
         for i in 0..16 {
             let diff = ctx
                 .state
                 .get_diff(tile, bel, format!("BUF.GIOB_{ud}{i}"), "1");
             let diff = diff.combine(&!&common);
-            ctx.tiledb.insert(
-                tile,
-                bel,
-                format!("BUF.GIOB_{ud}{i}"),
-                xlat_bitvec(vec![diff]),
-            );
+            ctx.tiledb
+                .insert(tile, bel, format!("BUF.GIOB_{ud}{i}"), xlat_bit(diff));
         }
         if edev.col_lgt.is_some() {
             let (_, _, common_mgt) = Diff::split(
@@ -770,12 +744,8 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     .state
                     .get_diff(tile, bel, format!("BUF.MGT_{ud}{i}"), "1");
                 let diff = diff.combine(&!&common_mgt);
-                ctx.tiledb.insert(
-                    tile,
-                    bel,
-                    format!("BUF.MGT_{ud}{i}"),
-                    xlat_bitvec(vec![diff]),
-                );
+                ctx.tiledb
+                    .insert(tile, bel, format!("BUF.MGT_{ud}{i}"), xlat_bit(diff));
             }
             let common_mgt = common_mgt.combine(&!&common);
             ctx.tiledb
diff --git a/prjcombine_ise_hammer/src/clk/virtex5.rs b/prjcombine_ise_hammer/src/clk/virtex5.rs
index 316217e9..a8dd11cf 100644
--- a/prjcombine_ise_hammer/src/clk/virtex5.rs
+++ b/prjcombine_ise_hammer/src/clk/virtex5.rs
@@ -5,7 +5,7 @@ use unnamed_entity::EntityId;
 
 use crate::{
     backend::IseBackend,
-    diff::{xlat_bit_wide, xlat_bitvec, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
+    diff::{xlat_bit, xlat_bit_wide, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
     fgen::{BelRelation, ExtraFeature, ExtraFeatureKind, TileBits, TileRelation},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_one, fuzz_one_extras,
@@ -342,7 +342,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         }
         for (i, diff) in inp_diffs.into_iter().enumerate() {
             ctx.tiledb
-                .insert(tile, bel, format!("BUF.GCLK{i}"), xlat_bitvec(vec![diff]));
+                .insert(tile, bel, format!("BUF.GCLK{i}"), xlat_bit(diff));
         }
     }
     for (tile, bel) in [
@@ -370,12 +370,8 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     .peek_diff(tile, bel, "MUX.MUXBUS1", format!("MGT_{lr}{i}"))
                     .clone();
                 let (_, _, diff) = Diff::split(diff_a, diff_b);
-                ctx.tiledb.insert(
-                    tile,
-                    bel,
-                    format!("BUF.MGT_{lr}{i}"),
-                    xlat_bitvec(vec![diff]),
-                );
+                ctx.tiledb
+                    .insert(tile, bel, format!("BUF.MGT_{lr}{i}"), xlat_bit(diff));
             }
         }
         for i in 0..32 {
@@ -470,8 +466,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         let (_, _, enable) = Diff::split(diffs[0].1.clone(), diffs[1].1.clone());
         for (bel, mut diff) in diffs {
             diff = diff.combine(&!&enable);
-            ctx.tiledb
-                .insert(tile, bel, "ENABLE", xlat_bitvec(vec![diff]));
+            ctx.tiledb.insert(tile, bel, "ENABLE", xlat_bit(diff));
         }
         ctx.tiledb
             .insert(tile, "IOCLK", "IOCLK_ENABLE", xlat_bit_wide(enable));
diff --git a/prjcombine_ise_hammer/src/dcm/spartan3e.rs b/prjcombine_ise_hammer/src/dcm/spartan3e.rs
index a84d1272..d8f2b011 100644
--- a/prjcombine_ise_hammer/src/dcm/spartan3e.rs
+++ b/prjcombine_ise_hammer/src/dcm/spartan3e.rs
@@ -9,7 +9,7 @@ use prjcombine_xilinx_geom::ExpandedDevice;
 
 use crate::{
     backend::{IseBackend, PinFromKind},
-    diff::{extract_bitvec_val, xlat_bitvec, CollectorCtx, Diff},
+    diff::{extract_bitvec_val, xlat_bit, xlat_bitvec, CollectorCtx, Diff},
     fgen::{ExtraFeature, TileBits},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_inv, fuzz_multi, fuzz_one, fuzz_one_extras,
@@ -471,11 +471,11 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             let diff_fx = ctx.state.get_diff(tile, bel, pin, "1.CLKFX");
             let diff_fx = diff_fx.combine(&!&diff_fb);
             let diff_fb = diff_fb.combine(&!&diff);
-            ctx.tiledb.insert(tile, bel, pin, xlat_bitvec(vec![diff]));
+            ctx.tiledb.insert(tile, bel, pin, xlat_bit(diff));
             ctx.tiledb
-                .insert(tile, bel, "DLL_ENABLE", xlat_bitvec(vec![diff_fb]));
+                .insert(tile, bel, "DLL_ENABLE", xlat_bit(diff_fb));
             ctx.tiledb
-                .insert(tile, bel, "DFS_FEEDBACK", xlat_bitvec(vec![diff_fx]));
+                .insert(tile, bel, "DFS_FEEDBACK", xlat_bit(diff_fx));
         }
 
         ctx.state
@@ -484,8 +484,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         let diff = ctx
             .state
             .get_diff(tile, bel, "VERY_HIGH_FREQUENCY", "1.CLKFB");
-        ctx.tiledb
-            .insert(tile, bel, "DLL_ENABLE", xlat_bitvec(vec![!diff]));
+        ctx.tiledb.insert(tile, bel, "DLL_ENABLE", xlat_bit(!diff));
 
         let (_, _, dfs_en) = Diff::split(
             ctx.state.peek_diff(tile, bel, "CLKFX", "1").clone(),
@@ -497,10 +496,9 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             assert_eq!(diff, diff_fb);
             let diff = diff.combine(&!&dfs_en);
             let pin = if pin == "CONCUR" { pin } else { "CLKFX" };
-            ctx.tiledb.insert(tile, bel, pin, xlat_bitvec(vec![diff]));
+            ctx.tiledb.insert(tile, bel, pin, xlat_bit(diff));
         }
-        ctx.tiledb
-            .insert(tile, bel, "DFS_ENABLE", xlat_bitvec(vec![dfs_en]));
+        ctx.tiledb.insert(tile, bel, "DFS_ENABLE", xlat_bit(dfs_en));
 
         let item = ctx.tiledb.item(tile, bel, "DESKEW_ADJUST");
         let val = extract_bitvec_val(
@@ -518,7 +516,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         diff.apply_bitvec_diff_int(&item, 2, 0);
         ctx.tiledb.insert(tile, bel, "PHASE_SHIFT", item);
         ctx.tiledb
-            .insert(tile, bel, "PHASE_SHIFT_NEGATIVE", xlat_bitvec(vec![diff]));
+            .insert(tile, bel, "PHASE_SHIFT_NEGATIVE", xlat_bit(diff));
 
         ctx.state
             .get_diff(tile, bel, "CLKOUT_PHASE_SHIFT", "NONE")
@@ -528,10 +526,9 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             .state
             .get_diff(tile, bel, "CLKOUT_PHASE_SHIFT", "VARIABLE");
         let diff_v = diff_v.combine(&!&diff_f);
+        ctx.tiledb.insert(tile, bel, "PS_ENABLE", xlat_bit(diff_f));
         ctx.tiledb
-            .insert(tile, bel, "PS_ENABLE", xlat_bitvec(vec![diff_f]));
-        ctx.tiledb
-            .insert(tile, bel, "PS_VARIABLE", xlat_bitvec(vec![diff_v]));
+            .insert(tile, bel, "PS_VARIABLE", xlat_bit(diff_v));
 
         for (attr, bits) in [
             ("CLKDV_COUNT_MAX", &cfg_dll_c.bits[1..5]),
@@ -630,7 +627,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         }
         let mut diff_b = diff_b.combine(&!&diff_a);
         ctx.tiledb
-            .insert(tile, bel, "PERIOD_NOT_HF", xlat_bitvec(vec![!diff_a]));
+            .insert(tile, bel, "PERIOD_NOT_HF", xlat_bit(!diff_a));
         ctx.tiledb.insert(
             tile,
             bel,
diff --git a/prjcombine_ise_hammer/src/dcm/spartan6.rs b/prjcombine_ise_hammer/src/dcm/spartan6.rs
index fa3a6806..32eddf2c 100644
--- a/prjcombine_ise_hammer/src/dcm/spartan6.rs
+++ b/prjcombine_ise_hammer/src/dcm/spartan6.rs
@@ -8,7 +8,7 @@ use unnamed_entity::EntityId;
 
 use crate::{
     backend::{IseBackend, PinFromKind},
-    diff::{xlat_bitvec, xlat_enum_default, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
+    diff::{xlat_bit, xlat_bitvec, xlat_enum_default, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits, TileRelation},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_enum_suffix, fuzz_inv, fuzz_multi, fuzz_one, fuzz_one_extras,
@@ -516,7 +516,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             present_dcm = present_dcm.combine(&diff);
             present_dcm_clkgen = present_dcm.combine(&diff);
             ctx.tiledb
-                .insert(tile, bel, format!("INV.{pin}"), xlat_bitvec(vec![!diff]));
+                .insert(tile, bel, format!("INV.{pin}"), xlat_bit(!diff));
         }
 
         // hrm. concerning.
@@ -604,7 +604,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             tile,
             bel,
             "CLKIN_CLKFB_ENABLE",
-            xlat_bitvec(vec![clkin_clkfb_enable]),
+            xlat_bit(clkin_clkfb_enable),
         );
         ctx.collect_enum(
             tile,
@@ -665,19 +665,17 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             if ctx.device.name.ends_with('l') && pin == "CLKDV" {
                 diff.apply_bitvec_diff_int(ctx.tiledb.item(tile, bel, "DLL_S"), 0, 0x40);
             }
-            ctx.tiledb.insert(tile, bel, pin, xlat_bitvec(vec![diff]));
+            ctx.tiledb.insert(tile, bel, pin, xlat_bit(diff));
             ctx.tiledb
-                .insert(tile, bel, "DFS_FEEDBACK", xlat_bitvec(vec![diff_fx]));
+                .insert(tile, bel, "DFS_FEEDBACK", xlat_bit(diff_fx));
         }
-        ctx.tiledb
-            .insert(tile, bel, "DLL_ENABLE", xlat_bitvec(vec![dll_en]));
+        ctx.tiledb.insert(tile, bel, "DLL_ENABLE", xlat_bit(dll_en));
 
         ctx.state
             .get_diff(tile, bel, "VERY_HIGH_FREQUENCY", "FALSE")
             .assert_empty();
         let diff = ctx.state.get_diff(tile, bel, "VERY_HIGH_FREQUENCY", "TRUE");
-        ctx.tiledb
-            .insert(tile, bel, "DLL_ENABLE", xlat_bitvec(vec![!diff]));
+        ctx.tiledb.insert(tile, bel, "DLL_ENABLE", xlat_bit(!diff));
 
         for attr in ["PIN.PROGCLK", "PIN.PROGEN", "PIN.PROGDATA"] {
             let item = ctx.extract_bit(tile, bel, attr, "1");
@@ -694,10 +692,9 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             assert_eq!(diff, diff_fb);
             let diff = diff.combine(&!&dfs_en);
             let pin = if pin == "CONCUR" { pin } else { "CLKFX" };
-            ctx.tiledb.insert(tile, bel, pin, xlat_bitvec(vec![diff]));
+            ctx.tiledb.insert(tile, bel, pin, xlat_bit(diff));
         }
-        ctx.tiledb
-            .insert(tile, bel, "DFS_ENABLE", xlat_bitvec(vec![dfs_en]));
+        ctx.tiledb.insert(tile, bel, "DFS_ENABLE", xlat_bit(dfs_en));
 
         let mut diffs = vec![ctx.state.get_diff(tile, bel, "PHASE_SHIFT", "-255")];
         diffs.extend(ctx.state.get_diffs(tile, bel, "PHASE_SHIFT", ""));
@@ -706,7 +703,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         diff.apply_bitvec_diff_int(&item, 2, 0);
         ctx.tiledb.insert(tile, bel, "PHASE_SHIFT", item);
         ctx.tiledb
-            .insert(tile, bel, "PHASE_SHIFT_NEGATIVE", xlat_bitvec(vec![diff]));
+            .insert(tile, bel, "PHASE_SHIFT_NEGATIVE", xlat_bit(diff));
 
         ctx.collect_enum(
             tile,
diff --git a/prjcombine_ise_hammer/src/dcm/virtex.rs b/prjcombine_ise_hammer/src/dcm/virtex.rs
index 9e44aacf..1c9683b7 100644
--- a/prjcombine_ise_hammer/src/dcm/virtex.rs
+++ b/prjcombine_ise_hammer/src/dcm/virtex.rs
@@ -10,7 +10,7 @@ use prjcombine_xilinx_geom::ExpandedDevice;
 
 use crate::{
     backend::{FeatureBit, IseBackend},
-    diff::{xlat_bitvec, xlat_bool, xlat_enum, CollectorCtx},
+    diff::{xlat_bit, xlat_bool, xlat_enum, CollectorCtx},
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits, TileKV},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_one, fuzz_one_extras,
@@ -340,8 +340,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
 
         present.apply_bit_diff(ctx.tiledb.item(tile, bel, "CFG_O_14"), true, false);
         if ctx.device.name.ends_with('e') {
-            ctx.tiledb
-                .insert(tile, bel, "ENABLE", xlat_bitvec(vec![present]));
+            ctx.tiledb.insert(tile, bel, "ENABLE", xlat_bit(present));
         } else {
             present.assert_empty();
         }
diff --git a/prjcombine_ise_hammer/src/dcm/virtex2.rs b/prjcombine_ise_hammer/src/dcm/virtex2.rs
index 47939b85..14c92eea 100644
--- a/prjcombine_ise_hammer/src/dcm/virtex2.rs
+++ b/prjcombine_ise_hammer/src/dcm/virtex2.rs
@@ -9,8 +9,8 @@ use prjcombine_xilinx_geom::ExpandedDevice;
 use crate::{
     backend::{FeatureBit, IseBackend, PinFromKind},
     diff::{
-        extract_bitvec_val, extract_bitvec_val_part, xlat_bit_wide, xlat_bitvec, xlat_bool,
-        xlat_enum, CollectorCtx, Diff,
+        extract_bitvec_val, extract_bitvec_val_part, xlat_bit, xlat_bit_wide, xlat_bitvec,
+        xlat_bool, xlat_enum, CollectorCtx, Diff,
     },
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits},
     fuzz::FuzzCtx,
@@ -590,16 +590,11 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         let en_dummy_osc = !ctx.state.get_diff(tile, bel, "EN_DUMMY_OSC", "0");
         let non_stop = ctx.state.get_diff(tile, bel, "NON_STOP", "1");
         let (en_dummy_osc, non_stop, common) = Diff::split(en_dummy_osc, non_stop);
-        ctx.tiledb
-            .insert(tile, bel, "NON_STOP", xlat_bitvec(vec![non_stop]));
+        ctx.tiledb.insert(tile, bel, "NON_STOP", xlat_bit(non_stop));
         ctx.tiledb
             .insert(tile, bel, "EN_DUMMY_OSC", xlat_bit_wide(en_dummy_osc));
-        ctx.tiledb.insert(
-            tile,
-            bel,
-            "EN_DUMMY_OSC_OR_NON_STOP",
-            xlat_bitvec(vec![common]),
-        );
+        ctx.tiledb
+            .insert(tile, bel, "EN_DUMMY_OSC_OR_NON_STOP", xlat_bit(common));
     } else {
         ctx.collect_enum_bool(tile, bel, "EN_DUMMY_OSC", "0", "1");
         ctx.collect_enum_bool(tile, bel, "NON_STOP", "0", "1");
@@ -696,8 +691,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         ctx.tiledb
             .insert(tile, bel, format!("INV.{pin}"), xlat_bool(d0, d1));
         if edev.grid.kind.is_virtex2() {
-            ctx.tiledb
-                .insert(tile, bel, "TEST_ENABLE", xlat_bitvec(vec![dc]));
+            ctx.tiledb.insert(tile, bel, "TEST_ENABLE", xlat_bit(dc));
         } else {
             dc.assert_empty();
         }
@@ -731,21 +725,19 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         assert_eq!(diff, diff_fb);
         assert_eq!(diff, diff_fx);
         let diff = diff.combine(&!&en_dll);
-        ctx.tiledb.insert(tile, bel, pin, xlat_bitvec(vec![diff]));
+        ctx.tiledb.insert(tile, bel, pin, xlat_bit(diff));
     }
     for pin in ["CLKFX", "CLKFX180", "CONCUR"] {
         let diff = ctx.state.get_diff(tile, bel, pin, "1");
         let diff_fb = ctx.state.get_diff(tile, bel, pin, "1.CLKFB");
         let diff_fb = diff_fb.combine(&!&diff);
         let diff = diff.combine(&!&en_dfs);
-        ctx.tiledb.insert(tile, bel, pin, xlat_bitvec(vec![diff]));
+        ctx.tiledb.insert(tile, bel, pin, xlat_bit(diff));
         ctx.tiledb
-            .insert(tile, bel, "DFS_FEEDBACK", xlat_bitvec(vec![diff_fb]));
+            .insert(tile, bel, "DFS_FEEDBACK", xlat_bit(diff_fb));
     }
-    ctx.tiledb
-        .insert(tile, bel, "DLL_ENABLE", xlat_bitvec(vec![en_dll]));
-    ctx.tiledb
-        .insert(tile, bel, "DFS_ENABLE", xlat_bitvec(vec![en_dfs]));
+    ctx.tiledb.insert(tile, bel, "DLL_ENABLE", xlat_bit(en_dll));
+    ctx.tiledb.insert(tile, bel, "DFS_ENABLE", xlat_bit(en_dfs));
     ctx.collect_bit(tile, bel, "CLKFB", "1");
 
     ctx.collect_bit(tile, bel, "CLKIN_IOB", "1");
@@ -764,7 +756,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         &bitvec![0; 8],
     );
     ctx.tiledb
-        .insert(tile, bel, "PHASE_SHIFT_NEGATIVE", xlat_bitvec(vec![diff]));
+        .insert(tile, bel, "PHASE_SHIFT_NEGATIVE", xlat_bit(diff));
 
     ctx.state
         .get_diff(tile, bel, "CLKOUT_PHASE_SHIFT", "NONE")
@@ -782,8 +774,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     assert_eq!(variable, variable_n);
     let fixed_n = fixed_n.combine(&!&fixed);
     let (fixed, variable, en_ps) = Diff::split(fixed, variable);
-    ctx.tiledb
-        .insert(tile, bel, "PS_ENABLE", xlat_bitvec(vec![en_ps]));
+    ctx.tiledb.insert(tile, bel, "PS_ENABLE", xlat_bit(en_ps));
     ctx.tiledb
         .insert(tile, bel, "PS_CENTERED", xlat_bool(fixed, variable));
 
@@ -959,7 +950,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         dss_base.apply_bit_diff(ctx.tiledb.item(tile, bel, "PS_ENABLE"), true, false);
         dss_base.apply_bit_diff(ctx.tiledb.item(tile, bel, "PS_CENTERED"), true, false);
         ctx.tiledb
-            .insert(tile, bel, "DSS_ENABLE", xlat_bitvec(vec![dss_base]));
+            .insert(tile, bel, "DSS_ENABLE", xlat_bit(dss_base));
     } else {
         for val in ["NONE", "SPREAD_2", "SPREAD_4", "SPREAD_6", "SPREAD_8"] {
             ctx.state
diff --git a/prjcombine_ise_hammer/src/dcm/virtex4.rs b/prjcombine_ise_hammer/src/dcm/virtex4.rs
index 9f1b2c15..ac390730 100644
--- a/prjcombine_ise_hammer/src/dcm/virtex4.rs
+++ b/prjcombine_ise_hammer/src/dcm/virtex4.rs
@@ -6,7 +6,7 @@ use prjcombine_types::{TileItem, TileItemKind};
 
 use crate::{
     backend::{FeatureBit, IseBackend, PinFromKind},
-    diff::{xlat_bitvec, xlat_enum, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
+    diff::{xlat_bit, xlat_bitvec, xlat_enum, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
     fgen::TileBits,
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_inv, fuzz_multi_attr_bin, fuzz_multi_attr_dec, fuzz_multi_attr_dec_delta,
@@ -465,7 +465,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     let diff_0 = ctx.state.get_diff(tile, bel, "CLK0", "1");
     let diff_0 = diff_0.combine(&!&diff);
     ctx.tiledb
-        .insert(tile, bel, "CLK0_ENABLE", xlat_bitvec(vec![diff_0]));
+        .insert(tile, bel, "CLK0_ENABLE", xlat_bit(diff_0));
     // ???
     ctx.tiledb.insert(
         tile,
@@ -522,14 +522,12 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         TileItem::from_bit(reg_bit(0x51, 10), false),
     );
 
-    ctx.tiledb
-        .insert(tile, bel, "DLL_ENABLE", xlat_bitvec(vec![diff]));
+    ctx.tiledb.insert(tile, bel, "DLL_ENABLE", xlat_bit(diff));
     let diff = ctx.state.get_diff(tile, bel, "CLKFX", "1");
     for pin in ["CLKFX180", "CONCUR"] {
         assert_eq!(diff, ctx.state.get_diff(tile, bel, pin, "1"));
     }
-    ctx.tiledb
-        .insert(tile, bel, "DFS_ENABLE", xlat_bitvec(vec![diff]));
+    ctx.tiledb.insert(tile, bel, "DFS_ENABLE", xlat_bit(diff));
 
     ctx.collect_bitvec(tile, bel, "BGM_VLDLY", "");
     ctx.collect_bitvec(tile, bel, "BGM_LDLY", "");
@@ -572,7 +570,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     let mut diff = ctx.state.get_diff(tile, bel, "PHASE_SHIFT", "-1");
     diff.apply_bitvec_diff_int(ctx.tiledb.item(tile, bel, "PHASE_SHIFT"), 1, 0);
     ctx.tiledb
-        .insert(tile, bel, "PHASE_SHIFT_NEGATIVE", xlat_bitvec(vec![diff]));
+        .insert(tile, bel, "PHASE_SHIFT_NEGATIVE", xlat_bit(diff));
 
     let mut diffs = vec![];
     for val in [
@@ -679,14 +677,10 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         assert_eq!(d, dd);
         match val {
             "NONE" => d.assert_empty(),
-            "FIXED" | "VARIABLE_POSITIVE" => {
-                ctx.tiledb
-                    .insert(tile, bel, "PS_ENABLE", xlat_bitvec(vec![d]))
-            }
+            "FIXED" | "VARIABLE_POSITIVE" => ctx.tiledb.insert(tile, bel, "PS_ENABLE", xlat_bit(d)),
             "VARIABLE_CENTER" => {
                 d.apply_bit_diff(ctx.tiledb.item(tile, bel, "PS_ENABLE"), true, false);
-                ctx.tiledb
-                    .insert(tile, bel, "PS_CENTERED", xlat_bitvec(vec![d]));
+                ctx.tiledb.insert(tile, bel, "PS_CENTERED", xlat_bit(d));
             }
             "DIRECT" => {
                 d.apply_bit_diff(ctx.tiledb.item(tile, bel, "PS_ENABLE"), true, false);
@@ -695,8 +689,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     "AUTO_ZD2",
                     "AUTO_DPS",
                 );
-                ctx.tiledb
-                    .insert(tile, bel, "PS_DIRECT", xlat_bitvec(vec![d]));
+                ctx.tiledb.insert(tile, bel, "PS_DIRECT", xlat_bit(d));
             }
             _ => unreachable!(),
         }
@@ -827,8 +820,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     ctx.collect_bit(tile, bel, "CLKIN_IOB", "1");
     let mut diff = ctx.state.get_diff(tile, bel, "CLKFB_IOB", "1");
     diff.apply_bit_diff(ctx.tiledb.item(tile, bel, "DCM_EXT_FB_EN"), true, false);
-    ctx.tiledb
-        .insert(tile, bel, "CLKFB_IOB", xlat_bitvec(vec![diff]));
+    ctx.tiledb.insert(tile, bel, "CLKFB_IOB", xlat_bit(diff));
     ctx.collect_bit(tile, bel, "CLKIN_ENABLE", "1");
     ctx.collect_bit(tile, bel, "CLKFB_ENABLE", "1");
 
@@ -849,8 +841,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             .get_diff(tile, bel, "CLK_FEEDBACK.CLKFB", "2X")
             .combine(&!&d2)
     );
-    ctx.tiledb
-        .insert(tile, bel, "CLKFB_FEEDBACK", xlat_bitvec(vec![df]));
+    ctx.tiledb.insert(tile, bel, "CLKFB_FEEDBACK", xlat_bit(df));
     ctx.tiledb.insert(
         tile,
         bel,
@@ -872,7 +863,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     present.apply_bit_diff(ctx.tiledb.item(tile, bel, "CONCUR_ENABLE"), true, false);
 
     ctx.tiledb
-        .insert(tile, bel, "UNK_ALWAYS_SET", xlat_bitvec(vec![present]));
+        .insert(tile, bel, "UNK_ALWAYS_SET", xlat_bit(present));
 
     for pin in ["CLKIN", "CLKFB"] {
         let mut diffs = vec![];
diff --git a/prjcombine_ise_hammer/src/diff.rs b/prjcombine_ise_hammer/src/diff.rs
index 4d80b356..387470a1 100644
--- a/prjcombine_ise_hammer/src/diff.rs
+++ b/prjcombine_ise_hammer/src/diff.rs
@@ -304,6 +304,10 @@ pub fn xlat_bitvec(diffs: Vec<Diff>) -> TileItem<FeatureBit> {
     }
 }
 
+pub fn xlat_bit(diff: Diff) -> TileItem<FeatureBit> {
+    xlat_bitvec(vec![diff])
+}
+
 pub fn xlat_bit_wide(diff: Diff) -> TileItem<FeatureBit> {
     let mut invert = BitVec::new();
     let mut bits = vec![];
@@ -566,7 +570,7 @@ pub fn xlat_bool_default(diff0: Diff, diff1: Diff) -> (TileItem<FeatureBit>, boo
         diff1.assert_empty();
         (!diff0, true)
     };
-    (xlat_bitvec(vec![diff]), res)
+    (xlat_bit(diff), res)
 }
 
 pub fn xlat_bool(diff0: Diff, diff1: Diff) -> TileItem<FeatureBit> {
@@ -690,7 +694,7 @@ impl<'a, 'b: 'a> CollectorCtx<'a, 'b> {
         val: &str,
     ) -> TileItem<FeatureBit> {
         let diff = self.state.get_diff(tile, bel, attr, val);
-        xlat_bitvec(vec![diff])
+        xlat_bit(diff)
     }
 
     #[must_use]
@@ -950,7 +954,11 @@ impl<'a, 'b: 'a> CollectorCtx<'a, 'b> {
     }
 }
 
-pub fn extract_bitvec_val_part(item: &TileItem<FeatureBit>, base: &BitVec, diff: &mut Diff) -> BitVec {
+pub fn extract_bitvec_val_part(
+    item: &TileItem<FeatureBit>,
+    base: &BitVec,
+    diff: &mut Diff,
+) -> BitVec {
     let TileItemKind::BitVec { ref invert } = item.kind else {
         unreachable!()
     };
diff --git a/prjcombine_ise_hammer/src/fgen.rs b/prjcombine_ise_hammer/src/fgen.rs
index fca65959..2e793f82 100644
--- a/prjcombine_ise_hammer/src/fgen.rs
+++ b/prjcombine_ise_hammer/src/fgen.rs
@@ -2847,6 +2847,7 @@ impl TileBits {
                         vec![edev.btile_main(col, row), edev.btile_btterm(col, row)]
                     }
                     prjcombine_virtex2::grid::GridKind::Spartan3 => vec![edev.btile_main(col, row)],
+                    prjcombine_virtex2::grid::GridKind::FpgaCore => unreachable!(),
                     prjcombine_virtex2::grid::GridKind::Spartan3E
                     | prjcombine_virtex2::grid::GridKind::Spartan3A
                     | prjcombine_virtex2::grid::GridKind::Spartan3ADsp => {
@@ -2971,11 +2972,14 @@ impl TileBits {
 #[derive(Debug, Copy, Clone, Eq, PartialEq)]
 pub enum ExtraFeatureKind {
     MainFixed(ColId, RowId),
+    Corner(ColId, RowId),
     AllDcms,
     AllOtherDcms,
     AllBrams,
     AllColumnIo,
     AllIobs,
+    AllGclkvm,
+    AllHclk,
     Pcilogic(Dir),
     VirtexClkBt,
     DcmVreg,
@@ -2983,6 +2987,7 @@ pub enum ExtraFeatureKind {
     DcmUL,
     DcmLR,
     DcmUR,
+    FpgaCoreIob(Dir),
     HclkDcm(Dir),
     HclkCcm(Dir),
     MgtRepeater(Dir, Option<Dir>),
@@ -3004,6 +3009,15 @@ impl ExtraFeatureKind {
                 ExpandedDevice::Virtex(edev) => {
                     vec![vec![edev.btile_main(col, row)]]
                 }
+                ExpandedDevice::Virtex2(edev) => {
+                    vec![vec![edev.btile_main(col, row)]]
+                }
+                _ => todo!(),
+            },
+            ExtraFeatureKind::Corner(col, row) => match backend.edev {
+                ExpandedDevice::Virtex2(edev) => {
+                    vec![vec![edev.btile_lrterm(col, row)]]
+                }
                 _ => todo!(),
             },
             ExtraFeatureKind::AllDcms => match backend.edev {
@@ -3024,9 +3038,10 @@ impl ExtraFeatureKind {
                         prjcombine_virtex2::grid::GridKind::Virtex2P
                         | prjcombine_virtex2::grid::GridKind::Virtex2PX => "DCM.V2P",
                         prjcombine_virtex2::grid::GridKind::Spartan3 => "DCM.S3",
-                        prjcombine_virtex2::grid::GridKind::Spartan3E => todo!(),
-                        prjcombine_virtex2::grid::GridKind::Spartan3A => todo!(),
-                        prjcombine_virtex2::grid::GridKind::Spartan3ADsp => todo!(),
+                        prjcombine_virtex2::grid::GridKind::FpgaCore => unreachable!(),
+                        prjcombine_virtex2::grid::GridKind::Spartan3E => unreachable!(),
+                        prjcombine_virtex2::grid::GridKind::Spartan3A => unreachable!(),
+                        prjcombine_virtex2::grid::GridKind::Spartan3ADsp => unreachable!(),
                     };
                     let node = backend.egrid.db.get_node(node);
                     backend.egrid.node_index[node]
@@ -3128,6 +3143,31 @@ impl ExtraFeatureKind {
                     .map(|loc| vec![edev.btile_main(loc.1, loc.2)])
                     .collect()
             }
+            ExtraFeatureKind::AllGclkvm => {
+                let ExpandedDevice::Virtex2(edev) = backend.edev else {
+                    unreachable!()
+                };
+                let node = backend.egrid.db.get_node("GCLKVM.S3");
+                backend.egrid.node_index[node]
+                    .iter()
+                    .map(|loc| {
+                        vec![
+                            edev.btile_clkv(loc.1, loc.2 - 1),
+                            edev.btile_clkv(loc.1, loc.2),
+                        ]
+                    })
+                    .collect()
+            }
+            ExtraFeatureKind::AllHclk => {
+                let ExpandedDevice::Virtex2(edev) = backend.edev else {
+                    unreachable!()
+                };
+                let node = backend.egrid.db.get_node("GCLKH");
+                backend.egrid.node_index[node]
+                    .iter()
+                    .map(|loc| vec![edev.btile_hclk(loc.1, loc.2)])
+                    .collect()
+            }
             ExtraFeatureKind::Pcilogic(dir) => {
                 let ExpandedDevice::Virtex(edev) = backend.edev else {
                     unreachable!()
@@ -3213,6 +3253,41 @@ impl ExtraFeatureKind {
                     .unwrap();
                 vec![TileBits::Dcm.get_bits(backend, (loc.0, col, row, layer))]
             }
+            ExtraFeatureKind::FpgaCoreIob(dir) => {
+                let ExpandedDevice::Virtex2(edev) = backend.edev else {
+                    unreachable!()
+                };
+                match dir {
+                    Dir::W => {
+                        if loc.1 != edev.grid.col_left() {
+                            vec![]
+                        } else {
+                            vec![vec![edev.btile_lrterm(loc.1, loc.2)]]
+                        }
+                    }
+                    Dir::E => {
+                        if loc.1 != edev.grid.col_right() {
+                            vec![]
+                        } else {
+                            vec![vec![edev.btile_lrterm(loc.1, loc.2)]]
+                        }
+                    }
+                    Dir::S => {
+                        if loc.2 != edev.grid.row_bot() {
+                            vec![]
+                        } else {
+                            vec![vec![edev.btile_btterm(loc.1, loc.2)]]
+                        }
+                    }
+                    Dir::N => {
+                        if loc.2 != edev.grid.row_top() {
+                            vec![]
+                        } else {
+                            vec![vec![edev.btile_btterm(loc.1, loc.2)]]
+                        }
+                    }
+                }
+            }
             ExtraFeatureKind::HclkDcm(dir) => {
                 let ExpandedDevice::Virtex4(edev) = backend.edev else {
                     unreachable!()
diff --git a/prjcombine_ise_hammer/src/fuzz.rs b/prjcombine_ise_hammer/src/fuzz.rs
index 3ebe88a0..c556c4cf 100644
--- a/prjcombine_ise_hammer/src/fuzz.rs
+++ b/prjcombine_ise_hammer/src/fuzz.rs
@@ -115,6 +115,7 @@ impl<'sm, 's, 'a, 'b> FuzzCtx<'sm, 's, 'a, 'b> {
                 prjcombine_virtex2::grid::GridKind::Virtex2P
                 | prjcombine_virtex2::grid::GridKind::Virtex2PX => "LL.V2P",
                 prjcombine_virtex2::grid::GridKind::Spartan3 => "LL.S3",
+                prjcombine_virtex2::grid::GridKind::FpgaCore => "LL.FC",
                 prjcombine_virtex2::grid::GridKind::Spartan3E => "LL.S3E",
                 prjcombine_virtex2::grid::GridKind::Spartan3A
                 | prjcombine_virtex2::grid::GridKind::Spartan3ADsp => "LL.S3A",
@@ -141,7 +142,10 @@ impl<'sm, 's, 'a, 'b> FuzzCtx<'sm, 's, 'a, 'b> {
 #[macro_export]
 macro_rules! fuzz_wire {
     ($ctx:ident, (int $tile:expr, $wire:expr)) => {
-        $crate::fgen::TileWire::IntWire((<prjcombine_int::db::NodeTileId as unnamed_entity::EntityId>::from_idx($tile), $ctx.backend.egrid.db.get_wire(&$wire[..])))
+        $crate::fgen::TileWire::IntWire((
+            <prjcombine_int::db::NodeTileId as unnamed_entity::EntityId>::from_idx($tile),
+            $ctx.backend.egrid.db.get_wire(&$wire[..]),
+        ))
     };
     ($ctx:ident, (pin $pin:expr)) => {
         $crate::fgen::TileWire::BelPinNear($ctx.bel, $pin.to_string())
diff --git a/prjcombine_ise_hammer/src/gt/spartan6.rs b/prjcombine_ise_hammer/src/gt/spartan6.rs
index 0a28f545..ebf9715d 100644
--- a/prjcombine_ise_hammer/src/gt/spartan6.rs
+++ b/prjcombine_ise_hammer/src/gt/spartan6.rs
@@ -9,7 +9,7 @@ use unnamed_entity::EntityId;
 
 use crate::{
     backend::{FeatureBit, IseBackend},
-    diff::{xlat_bitvec, xlat_enum, CollectorCtx, OcdMode},
+    diff::{xlat_bit, xlat_bitvec, xlat_enum, CollectorCtx, OcdMode},
     fgen::{TileBits, TileKV},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_inv, fuzz_multi_attr_bin, fuzz_multi_attr_dec, fuzz_multi_attr_hex, fuzz_one,
@@ -410,7 +410,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             tile,
             bel,
             format!("REFSELPLL{i}_STATIC_ENABLE"),
-            xlat_bitvec(vec![refselpll_static]),
+            xlat_bit(refselpll_static),
         );
     }
 }
diff --git a/prjcombine_ise_hammer/src/gt/virtex4.rs b/prjcombine_ise_hammer/src/gt/virtex4.rs
index fe5ebefd..a56cbcf6 100644
--- a/prjcombine_ise_hammer/src/gt/virtex4.rs
+++ b/prjcombine_ise_hammer/src/gt/virtex4.rs
@@ -6,7 +6,10 @@ use unnamed_entity::EntityId;
 
 use crate::{
     backend::{FeatureBit, IseBackend},
-    diff::{xlat_bitvec, xlat_enum, xlat_enum_default, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
+    diff::{
+        xlat_bit, xlat_bitvec, xlat_enum, xlat_enum_default, xlat_enum_ocd, CollectorCtx, Diff,
+        OcdMode,
+    },
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits, TileRelation},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_inv, fuzz_multi_attr_bin, fuzz_multi_attr_dec, fuzz_multi_attr_hex, fuzz_one,
@@ -757,7 +760,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             tile,
             "GT11_COMMON",
             "FWDCLK_OUT_ENABLE",
-            xlat_bitvec(vec![fwdclk_out_enable]),
+            xlat_bit(fwdclk_out_enable),
         );
 
         for i in 0..2 {
@@ -810,13 +813,13 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         tile,
         "GT11_COMMON",
         "SYNCLK_DRIVE_ENABLE",
-        xlat_bitvec(vec![synclk_drive_enable]),
+        xlat_bit(synclk_drive_enable),
     );
     ctx.tiledb.insert(
         tile,
         "GT11_COMMON",
         "SYNCLK_ENABLE",
-        xlat_bitvec(vec![synclk_enable]),
+        xlat_bit(synclk_enable),
     );
 
     let item = ctx.extract_enum(
diff --git a/prjcombine_ise_hammer/src/int.rs b/prjcombine_ise_hammer/src/int.rs
index aad3caf6..d4c62fce 100644
--- a/prjcombine_ise_hammer/src/int.rs
+++ b/prjcombine_ise_hammer/src/int.rs
@@ -68,6 +68,7 @@ pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBacke
                     TileKV::NodeIntSrcFilter(wire_from),
                     TileKV::NodeMutexShared(wire_from),
                     TileKV::IntMutexShared("MAIN".to_string()),
+                    TileKV::GlobalMutexNone("MISR_CLOCK".to_string()),
                 ];
                 let fuzz = vec![
                     TileFuzzKV::NodeMutexExclusive(wire_to),
diff --git a/prjcombine_ise_hammer/src/int/virtex.rs b/prjcombine_ise_hammer/src/int/virtex.rs
index 2ddf22ee..20d44467 100644
--- a/prjcombine_ise_hammer/src/int/virtex.rs
+++ b/prjcombine_ise_hammer/src/int/virtex.rs
@@ -10,7 +10,7 @@ use unnamed_entity::EntityId;
 
 use crate::{
     backend::{FeatureId, IseBackend},
-    diff::{xlat_bitvec, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
+    diff::{xlat_bit, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
     fgen::{BelFuzzKV, BelKV, TileBits, TileFuzzKV, TileFuzzerGen, TileKV, TileRelation},
 };
 
@@ -770,7 +770,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                         println!("UMM {out_name} {in_name} PASS IS EMPTY");
                         continue;
                     }
-                    let item = xlat_bitvec(vec![diff]);
+                    let item = xlat_bit(diff);
                     let name = if matches!(
                         intdb.wires[wire_from.1],
                         WireKind::PipOut | WireKind::PipBranch(_)
@@ -805,15 +805,11 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                                 .get_diff(tile, "INT", &mux_name, format!("{in_name}.NOALT"));
                         let (alt, noalt, common) = Diff::split(diff, noalt_diff);
                         if mux_name.contains("CLKIN") {
-                            ctx.tiledb
-                                .insert(tile, "DLL", "CLKIN_PAD", xlat_bitvec(vec![noalt]));
-                            ctx.tiledb
-                                .insert(tile, "DLL", "CLKFB_PAD", xlat_bitvec(vec![!alt]));
+                            ctx.tiledb.insert(tile, "DLL", "CLKIN_PAD", xlat_bit(noalt));
+                            ctx.tiledb.insert(tile, "DLL", "CLKFB_PAD", xlat_bit(!alt));
                         } else {
-                            ctx.tiledb
-                                .insert(tile, "DLL", "CLKFB_PAD", xlat_bitvec(vec![noalt]));
-                            ctx.tiledb
-                                .insert(tile, "DLL", "CLKIN_PAD", xlat_bitvec(vec![!alt]));
+                            ctx.tiledb.insert(tile, "DLL", "CLKFB_PAD", xlat_bit(noalt));
+                            ctx.tiledb.insert(tile, "DLL", "CLKIN_PAD", xlat_bit(!alt));
                         }
                         diff = common;
                     }
@@ -835,7 +831,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                             tile,
                             "INT",
                             format!("BUF.{out_name}.{in_name}"),
-                            xlat_bitvec(vec![diff]),
+                            xlat_bit(diff),
                         );
                     } else {
                         if diff.bits.is_empty() {
@@ -895,12 +891,8 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     }
                     let item = xlat_enum_ocd(inps, OcdMode::Mux);
                     ctx.tiledb.insert(tile, "INT", mux_name, item);
-                    ctx.tiledb.insert(
-                        tile,
-                        "INT",
-                        format!("DRIVE.{out_name}"),
-                        xlat_bitvec(vec![drive]),
-                    );
+                    ctx.tiledb
+                        .insert(tile, "INT", format!("DRIVE.{out_name}"), xlat_bit(drive));
                 } else {
                     if !got_empty {
                         inps.push(("NONE".to_string(), Diff::default()));
diff --git a/prjcombine_ise_hammer/src/int/xc5200.rs b/prjcombine_ise_hammer/src/int/xc5200.rs
index 9cda103b..f002a3eb 100644
--- a/prjcombine_ise_hammer/src/int/xc5200.rs
+++ b/prjcombine_ise_hammer/src/int/xc5200.rs
@@ -3,7 +3,7 @@ use prjcombine_int::db::WireKind;
 
 use crate::{
     backend::{FeatureBit, FeatureId, IseBackend},
-    diff::{xlat_bitvec, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
+    diff::{xlat_bit, xlat_enum_ocd, CollectorCtx, Diff, OcdMode},
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits, TileFuzzKV, TileFuzzerGen, TileKV},
 };
 
@@ -188,7 +188,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                         }
                         _ => (),
                     }
-                    let item = xlat_bitvec(vec![diff]);
+                    let item = xlat_bit(diff);
                     let name =
                         if intdb.wires[wire_from.1] != WireKind::MuxOut && wire_from < wire_to {
                             format!("PASS.{in_name}.{out_name}")
diff --git a/prjcombine_ise_hammer/src/intf.rs b/prjcombine_ise_hammer/src/intf.rs
index 4870fdc0..dd28a140 100644
--- a/prjcombine_ise_hammer/src/intf.rs
+++ b/prjcombine_ise_hammer/src/intf.rs
@@ -5,7 +5,7 @@ use prjcombine_xilinx_geom::ExpandedDevice;
 
 use crate::{
     backend::{FeatureId, IseBackend},
-    diff::{xlat_bitvec, xlat_enum, xlat_enum_default, CollectorCtx, Diff},
+    diff::{xlat_bit, xlat_enum, xlat_enum_default, CollectorCtx, Diff},
     fgen::{TileBits, TileFuzzKV, TileFuzzerGen, TileKV},
 };
 
@@ -183,7 +183,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             }
         }
         ctx.tiledb
-            .insert(name, "INTF", "TEST_ENABLE", xlat_bitvec(vec![test_diff]));
+            .insert(name, "INTF", "TEST_ENABLE", xlat_bit(test_diff));
         if let ExpandedDevice::Virtex4(edev) = ctx.edev {
             match edev.kind {
                 prjcombine_virtex4::grid::GridKind::Virtex4 => {
diff --git a/prjcombine_ise_hammer/src/io.rs b/prjcombine_ise_hammer/src/io.rs
index 5e866759..914de424 100644
--- a/prjcombine_ise_hammer/src/io.rs
+++ b/prjcombine_ise_hammer/src/io.rs
@@ -1,3 +1,4 @@
-pub mod xc5200;
+pub mod fpgacore;
 pub mod virtex;
 pub mod virtex2;
+pub mod xc5200;
diff --git a/prjcombine_ise_hammer/src/io/fpgacore.rs b/prjcombine_ise_hammer/src/io/fpgacore.rs
new file mode 100644
index 00000000..b7a72a74
--- /dev/null
+++ b/prjcombine_ise_hammer/src/io/fpgacore.rs
@@ -0,0 +1,258 @@
+use prjcombine_hammer::Session;
+use prjcombine_int::db::Dir;
+use prjcombine_types::TileItem;
+
+use crate::{
+    backend::{FeatureBit, IseBackend},
+    diff::{xlat_bit, xlat_bit_wide, xlat_bool, CollectorCtx, Diff},
+    fgen::{ExtraFeature, ExtraFeatureKind, TileBits},
+    fuzz::FuzzCtx,
+    fuzz_enum, fuzz_inv, fuzz_one, fuzz_one_extras,
+};
+
+fn make_iob_extras(bel: &str, attr: &str, val: &str) -> Vec<ExtraFeature> {
+    [
+        ("IOBS.FC.L", Dir::W),
+        ("IOBS.FC.R", Dir::E),
+        ("IOBS.FC.B", Dir::S),
+        ("IOBS.FC.T", Dir::N),
+    ]
+    .into_iter()
+    .map(|(tile, dir)| ExtraFeature::new(ExtraFeatureKind::FpgaCoreIob(dir), tile, bel, attr, val))
+    .collect()
+}
+
+pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBackend<'a>) {
+    let tile = "IOI.FC";
+    for i in 0..4 {
+        let bel = &format!("IBUF{i}");
+        let ctx = FuzzCtx::new(session, backend, tile, bel, TileBits::MainAuto);
+        fuzz_one_extras!(ctx, "ENABLE", "1", [
+        ], [
+            (mode "IBUF")
+        ], make_iob_extras(bel, "ENABLE", "1"));
+        fuzz_one_extras!(ctx, "ENABLE_O2IPADPATH", "1", [
+            (mode "IBUF")
+        ], [
+            (attr "ENABLE_O2IPADPATH", "ENABLE_O2IPADPATH")
+        ], make_iob_extras(bel, "ENABLE_O2IPADPATH", "1"));
+        fuzz_one!(ctx, "ENABLE_O2IPATH", "1", [
+            (mode "IBUF"),
+            (attr "ENABLE_O2IQPATH", "")
+        ], [
+            (attr "ENABLE_O2IPATH", "ENABLE_O2IPATH")
+        ]);
+        fuzz_one!(ctx, "ENABLE_O2IQPATH", "1", [
+            (mode "IBUF"),
+            (attr "ENABLE_O2IPATH", "")
+        ], [
+            (attr "ENABLE_O2IQPATH", "ENABLE_O2IQPATH")
+        ]);
+        fuzz_enum!(ctx, "IMUX", ["0", "1"], [
+            (mode "IBUF"),
+            (attr "IFFDMUX", "1"),
+            (attr "IFF", "#FF"),
+            (pin "I"),
+            (pin "IQ")
+        ]);
+        fuzz_enum!(ctx, "IFFDMUX", ["0", "1"], [
+            (mode "IBUF"),
+            (attr "IMUX", "1"),
+            (attr "IFF", "#FF"),
+            (pin "I"),
+            (pin "IQ")
+        ]);
+        fuzz_enum!(ctx, "IFF", ["#FF", "#LATCH"], [
+            (mode "IBUF"),
+            (attr "IFFDMUX", "1"),
+            (attr "IFF_INIT_ATTR", "INIT1"),
+            (attr "CEINV", "CE_B"),
+            (pin "IQ"),
+            (pin "CE")
+        ]);
+        fuzz_enum!(ctx, "IFFATTRBOX", ["SYNC", "ASYNC"], [
+            (mode "IBUF"),
+            (attr "IFF", "#FF"),
+            (attr "IFFDMUX", "1"),
+            (pin "IQ")
+        ]);
+        fuzz_enum!(ctx, "IFF_INIT_ATTR", ["INIT0", "INIT1"], [
+            (mode "IBUF"),
+            (attr "IFF", "#FF"),
+            (attr "IFFDMUX", "1"),
+            (attr "IFF_SR_ATTR", "SRLOW"),
+            (pin "IQ")
+        ]);
+        fuzz_enum!(ctx, "IFF_SR_ATTR", ["SRLOW", "SRHIGH"], [
+            (mode "IBUF"),
+            (attr "IFF", "#FF"),
+            (attr "IFFDMUX", "1"),
+            (attr "IFF_INIT_ATTR", "INIT0"),
+            (pin "IQ")
+        ]);
+
+        for pin in ["CLK", "CE", "SR", "REV"] {
+            fuzz_inv!(ctx, pin, [(mode "IBUF"), (pin "IQ"), (attr "IFF", "#FF")]);
+        }
+    }
+    for i in 0..4 {
+        let bel = &format!("OBUF{i}");
+        let ctx = FuzzCtx::new(
+            session,
+            backend,
+            tile,
+            format!("OBUF{i}"),
+            TileBits::MainAuto,
+        );
+        fuzz_one_extras!(ctx, "ENABLE", "1", [
+        ], [
+            (mode "OBUF"),
+            (attr "ENABLE_MISR", "FALSE")
+        ], make_iob_extras(bel, "ENABLE", "1"));
+        fuzz_one_extras!(ctx, "ENABLE_MISR", "TRUE", [
+            (mode "OBUF")
+        ], [
+            (attr_diff "ENABLE_MISR", "FALSE", "TRUE")
+        ], make_iob_extras(bel, "ENABLE_MISR", "TRUE"));
+        for pin in ["CLK", "CE", "SR", "REV", "O"] {
+            fuzz_inv!(ctx, pin, [(mode "OBUF"), (attr "OMUX", "OFF"), (attr "OFF", "#FF")]);
+        }
+        fuzz_enum!(ctx, "OFF", ["#FF", "#LATCH"], [
+            (mode "OBUF"),
+            (attr "OINV", "O"),
+            (attr "OFF_INIT_ATTR", "INIT1"),
+            (attr "CEINV", "CE_B"),
+            (pin "O"),
+            (pin "CE")
+        ]);
+        fuzz_enum!(ctx, "OFFATTRBOX", ["SYNC", "ASYNC"], [
+            (mode "OBUF"),
+            (attr "OFF", "#FF"),
+            (attr "OINV", "O"),
+            (pin "O")
+        ]);
+        fuzz_enum!(ctx, "OFF_INIT_ATTR", ["INIT0", "INIT1"], [
+            (mode "OBUF"),
+            (attr "OFF", "#FF"),
+            (attr "OINV", "O"),
+            (attr "OFF_SR_ATTR", "SRLOW"),
+            (pin "O")
+        ]);
+        fuzz_enum!(ctx, "OFF_SR_ATTR", ["SRLOW", "SRHIGH"], [
+            (mode "OBUF"),
+            (attr "OFF", "#FF"),
+            (attr "OINV", "O"),
+            (attr "OFF_INIT_ATTR", "INIT0"),
+            (pin "O")
+        ]);
+        fuzz_enum!(ctx, "OMUX", ["O", "OFF"], [
+            (mode "OBUF"),
+            (attr "OFF", "#FF"),
+            (attr "OINV", "O"),
+            (pin "O")
+        ]);
+    }
+}
+
+pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
+    for i in 0..4 {
+        let tile = "IOI.FC";
+        let bel = &format!("IBUF{i}");
+        ctx.state.get_diff(tile, bel, "ENABLE", "1").assert_empty();
+        ctx.state
+            .get_diff(tile, bel, "ENABLE_O2IPADPATH", "1")
+            .assert_empty();
+        let diff_i = ctx.state.get_diff(tile, bel, "ENABLE_O2IPATH", "1");
+        let diff_iq = ctx.state.get_diff(tile, bel, "ENABLE_O2IQPATH", "1");
+        let (diff_i, diff_iq, diff_common) = Diff::split(diff_i, diff_iq);
+        ctx.tiledb
+            .insert(tile, bel, "ENABLE_O2IPATH", xlat_bit(diff_i));
+        ctx.tiledb
+            .insert(tile, bel, "ENABLE_O2IQPATH", xlat_bit(diff_iq));
+        ctx.tiledb
+            .insert(tile, bel, "ENABLE_O2I_O2IQ_PATH", xlat_bit(diff_common));
+        for pin in ["CLK", "CE"] {
+            ctx.collect_inv(tile, bel, pin);
+        }
+        for pin in ["REV", "SR"] {
+            let d0 = ctx.state.get_diff(tile, bel, format!("{pin}INV"), pin);
+            let d1 = ctx
+                .state
+                .get_diff(tile, bel, format!("{pin}INV"), format!("{pin}_B"));
+            let (d0, d1, de) = Diff::split(d0, d1);
+            ctx.tiledb
+                .insert(tile, bel, format!("INV.{pin}"), xlat_bool(d0, d1));
+            ctx.tiledb
+                .insert(tile, bel, format!("FF_{pin}_ENABLE"), xlat_bit(de));
+        }
+        ctx.state.get_diff(tile, bel, "IMUX", "1").assert_empty();
+        ctx.state.get_diff(tile, bel, "IFFDMUX", "1").assert_empty();
+        let diff_i = ctx.state.get_diff(tile, bel, "IMUX", "0");
+        let diff_iff = ctx.state.get_diff(tile, bel, "IFFDMUX", "0");
+        let (diff_i, diff_iff, diff_common) = Diff::split(diff_i, diff_iff);
+        ctx.tiledb
+            .insert(tile, bel, "I_DELAY_ENABLE", xlat_bit(diff_i));
+        ctx.tiledb
+            .insert(tile, bel, "IFF_DELAY_ENABLE", xlat_bit(diff_iff));
+        ctx.tiledb
+            .insert(tile, bel, "DELAY_ENABLE", xlat_bit_wide(diff_common));
+        let item = ctx.extract_enum_bool(tile, bel, "IFF", "#FF", "#LATCH");
+        ctx.tiledb.insert(tile, bel, "FF_LATCH", item);
+        let item = ctx.extract_enum_bool(tile, bel, "IFFATTRBOX", "ASYNC", "SYNC");
+        ctx.tiledb.insert(tile, bel, "FF_SYNC", item);
+        let item = ctx.extract_enum_bool(tile, bel, "IFF_INIT_ATTR", "INIT0", "INIT1");
+        ctx.tiledb.insert(tile, bel, "FF_INIT", item);
+        let item = ctx.extract_enum_bool(tile, bel, "IFF_SR_ATTR", "SRLOW", "SRHIGH");
+        ctx.tiledb.insert(tile, bel, "FF_SRVAL", item);
+        ctx.tiledb.insert(
+            tile,
+            bel,
+            "READBACK_I",
+            TileItem::from_bit(FeatureBit::new(0, 3, [0, 31, 32, 63][i]), false),
+        );
+        for tile in ["IOBS.FC.B", "IOBS.FC.T", "IOBS.FC.L", "IOBS.FC.R"] {
+            ctx.collect_bit(tile, bel, "ENABLE", "1");
+            ctx.collect_bit(tile, bel, "ENABLE_O2IPADPATH", "1");
+        }
+    }
+    for i in 0..4 {
+        let tile = "IOI.FC";
+        let bel = &format!("OBUF{i}");
+        ctx.state.get_diff(tile, bel, "ENABLE", "1").assert_empty();
+        ctx.state
+            .get_diff(tile, bel, "ENABLE_MISR", "TRUE")
+            .assert_empty();
+        for pin in ["CLK", "O"] {
+            ctx.collect_inv(tile, bel, pin);
+        }
+        ctx.collect_int_inv(&["INT.IOI.FC"], tile, bel, "CE", false);
+        for pin in ["REV", "SR"] {
+            let d0 = ctx.state.get_diff(tile, bel, format!("{pin}INV"), pin);
+            let d1 = ctx
+                .state
+                .get_diff(tile, bel, format!("{pin}INV"), format!("{pin}_B"));
+            let (d0, d1, de) = Diff::split(d0, d1);
+            if pin == "REV" {
+                ctx.tiledb
+                    .insert(tile, bel, format!("INV.{pin}"), xlat_bool(d0, d1));
+            } else {
+                ctx.insert_int_inv(&["INT.IOI.FC"], tile, bel, pin, xlat_bool(d0, d1));
+            }
+            ctx.tiledb
+                .insert(tile, bel, format!("FF_{pin}_ENABLE"), xlat_bit(de));
+        }
+        let item = ctx.extract_enum_bool(tile, bel, "OFF", "#FF", "#LATCH");
+        ctx.tiledb.insert(tile, bel, "FF_LATCH", item);
+        let item = ctx.extract_enum_bool(tile, bel, "OFFATTRBOX", "ASYNC", "SYNC");
+        ctx.tiledb.insert(tile, bel, "FF_SYNC", item);
+        let item = ctx.extract_enum_bool(tile, bel, "OFF_INIT_ATTR", "INIT0", "INIT1");
+        ctx.tiledb.insert(tile, bel, "FF_INIT", item);
+        let item = ctx.extract_enum_bool(tile, bel, "OFF_SR_ATTR", "SRLOW", "SRHIGH");
+        ctx.tiledb.insert(tile, bel, "FF_SRVAL", item);
+        ctx.collect_enum_default(tile, bel, "OMUX", &["O", "OFF"], "NONE");
+        for tile in ["IOBS.FC.B", "IOBS.FC.T", "IOBS.FC.L", "IOBS.FC.R"] {
+            ctx.collect_bit_wide(tile, bel, "ENABLE", "1");
+            ctx.collect_bit(tile, bel, "ENABLE_MISR", "TRUE");
+        }
+    }
+}
diff --git a/prjcombine_ise_hammer/src/io/virtex.rs b/prjcombine_ise_hammer/src/io/virtex.rs
index 3b00e24a..2144de3f 100644
--- a/prjcombine_ise_hammer/src/io/virtex.rs
+++ b/prjcombine_ise_hammer/src/io/virtex.rs
@@ -10,7 +10,7 @@ use unnamed_entity::EntityId;
 
 use crate::{
     backend::{FeatureBit, IseBackend},
-    diff::{xlat_bitvec, xlat_bool, xlat_enum, CollectorCtx, Diff},
+    diff::{xlat_bit, xlat_bitvec, xlat_bool, xlat_enum, CollectorCtx, Diff},
     fgen::{BelKV, ExtraFeature, ExtraFeatureKind, TileBits},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_one, fuzz_one_extras,
@@ -499,7 +499,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                 .state
                 .get_diff(tile, bel, "SHORTEN_JTAG_CHAIN", "0")
                 .combine(&!&present);
-            let item = xlat_bitvec(vec![!diff]);
+            let item = xlat_bit(!diff);
             ctx.tiledb.insert(tile, bel, "SHORTEN_JTAG_CHAIN", item);
             for (pin, pin_b, pinmux) in [
                 ("SR", "SR_B", "SRMUX"),
@@ -684,8 +684,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
 
             if has_any_vref(edev, ctx.device, ctx.db, tile, BelId::from_idx(i)).is_some() {
                 let diff = present.combine(&!&ctx.state.get_diff(tile, bel, "PRESENT", "NOT_VREF"));
-                ctx.tiledb
-                    .insert(tile_iob, bel, "VREF", xlat_bitvec(vec![diff]));
+                ctx.tiledb.insert(tile_iob, bel, "VREF", xlat_bit(diff));
             }
 
             let mut diffs_istd = vec![];
diff --git a/prjcombine_ise_hammer/src/io/virtex2.rs b/prjcombine_ise_hammer/src/io/virtex2.rs
index 03eb4fb2..ba9d76a3 100644
--- a/prjcombine_ise_hammer/src/io/virtex2.rs
+++ b/prjcombine_ise_hammer/src/io/virtex2.rs
@@ -11,7 +11,7 @@ use unnamed_entity::EntityId;
 use crate::{
     backend::{FeatureBit, IseBackend},
     diff::{
-        enum_ocd_swap_bits, xlat_bit_wide, xlat_bitvec, xlat_enum, xlat_enum_ocd,
+        enum_ocd_swap_bits, xlat_bit, xlat_bit_wide, xlat_bitvec, xlat_enum, xlat_enum_ocd,
         xlat_item_tile_fwd, CollectorCtx, Diff, OcdMode,
     },
     fgen::{BelKV, TileBits, TileKV, TileRelation},
@@ -2625,6 +2625,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                 _ => "INT.IOI",
             },
             GridKind::Spartan3 => "INT.IOI.S3",
+            GridKind::FpgaCore => unreachable!(),
             GridKind::Spartan3E => "INT.IOI.S3E",
             GridKind::Spartan3A | GridKind::Spartan3ADsp => {
                 if tile == "IOI.S3A.LR" {
@@ -2825,7 +2826,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     ctx.tiledb
                         .insert(tile, bel, "IFF_DELAY", xlat_bitvec(vec![!b0_iff, !b1_iff]));
                     ctx.tiledb
-                        .insert(tile, bel, "DELAY_COMMON", xlat_bitvec(vec![!common]));
+                        .insert(tile, bel, "DELAY_COMMON", xlat_bit(!common));
                     let item = ctx.extract_bit(tile, bel, "DELAY_ADJ_ATTRBOX", "VARIABLE");
                     ctx.tiledb.insert(tile, bel, "DELAY_VARIABLE", item);
                 }
@@ -2854,14 +2855,12 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                 let en = ctx.state.get_diff(tile, bel, "MISR_ENABLE", "1");
                 let en_rst = ctx.state.get_diff(tile, bel, "MISR_ENABLE_RESET", "1");
                 let rst = en_rst.combine(&!&en);
-                ctx.tiledb
-                    .insert(tile, bel, "MISR_RESET", xlat_bitvec(vec![rst]));
+                ctx.tiledb.insert(tile, bel, "MISR_RESET", xlat_bit(rst));
                 let clk1 = ctx.state.get_diff(tile, bel, "MISR_ENABLE_OTCLK1", "1");
                 let clk2 = ctx.state.get_diff(tile, bel, "MISR_ENABLE_OTCLK2", "1");
                 assert_eq!(en, clk1);
                 let (clk1, clk2, en) = Diff::split(clk1, clk2);
-                ctx.tiledb
-                    .insert(tile, bel, "MISR_ENABLE", xlat_bitvec(vec![en]));
+                ctx.tiledb.insert(tile, bel, "MISR_ENABLE", xlat_bit(en));
                 ctx.tiledb.insert(
                     tile,
                     bel,
@@ -2969,6 +2968,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         let ioi_tile = match edev.grid.kind {
             GridKind::Virtex2 | GridKind::Virtex2P | GridKind::Virtex2PX => "IOI",
             GridKind::Spartan3 => "IOI.S3",
+            GridKind::FpgaCore => unreachable!(),
             GridKind::Spartan3E => "IOI.S3E",
             GridKind::Spartan3A | GridKind::Spartan3ADsp => match &tile[..] {
                 "IOBS.S3A.B2" => "IOI.S3A.B",
@@ -3103,7 +3103,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     );
 
                     ctx.tiledb
-                        .insert(tile, bel, "DELAY_COMMON", xlat_bitvec(vec![!common]));
+                        .insert(tile, bel, "DELAY_COMMON", xlat_bit(!common));
                 } else {
                     for val in ["DLY14", "DLY15", "DLY16"] {
                         ctx.state
@@ -3212,7 +3212,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     );
 
                     ctx.tiledb
-                        .insert(tile, bel, "DELAY_COMMON", xlat_bitvec(vec![!common]));
+                        .insert(tile, bel, "DELAY_COMMON", xlat_bit(!common));
                 }
             }
             if edev.grid.kind.is_spartan3a()
@@ -3269,7 +3269,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                 ctx.tiledb
                     .insert(tile, bel, "IFF_DELAY", xlat_bitvec(vec![!b0_iff, !b1_iff]));
                 ctx.tiledb
-                    .insert(tile, bel, "DELAY_COMMON", xlat_bitvec(vec![!common]));
+                    .insert(tile, bel, "DELAY_COMMON", xlat_bit(!common));
                 let item = ctx.extract_bit(tile, bel, "DELAY_ADJ_ATTRBOX", "VARIABLE");
                 ctx.tiledb.insert(tile, bel, "DELAY_VARIABLE", item);
             }
@@ -3386,8 +3386,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                 );
                 let mut vref = present.combine(&!present_vref);
                 vref.discard_bits(ctx.tiledb.item(tile, bel, "PULL"));
-                ctx.tiledb
-                    .insert(tile, bel, "VREF", xlat_bitvec(vec![vref]));
+                ctx.tiledb.insert(tile, bel, "VREF", xlat_bit(vref));
             }
 
             // PCI cruft
@@ -3396,7 +3395,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                 ibuf_diff.discard_bits(ctx.tiledb.item(tile, bel, "IBUF_MODE"));
                 if iob.is_ibuf {
                     ctx.tiledb
-                        .insert(tile, bel, "PCI_INPUT", xlat_bitvec(vec![ibuf_diff]));
+                        .insert(tile, bel, "PCI_INPUT", xlat_bit(ibuf_diff));
                 } else {
                     let obuf_diff = ctx
                         .state
@@ -3404,9 +3403,8 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                         .clone();
                     let (ibuf_diff, _, common) = Diff::split(ibuf_diff, obuf_diff);
                     ctx.tiledb
-                        .insert(tile, bel, "PCI_INPUT", xlat_bitvec(vec![ibuf_diff]));
-                    ctx.tiledb
-                        .insert(tile, bel, "PCI_CLAMP", xlat_bitvec(vec![common]));
+                        .insert(tile, bel, "PCI_INPUT", xlat_bit(ibuf_diff));
+                    ctx.tiledb.insert(tile, bel, "PCI_CLAMP", xlat_bit(common));
                 }
             }
 
@@ -3613,7 +3611,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     diff.apply_enum_diff(item, "NONE", "TERM_SPLIT");
                     diff = !diff;
                     vr_slew = Some(diff.split_bits(&slew_bits));
-                    ctx.tiledb.insert(tile, bel, "VR", xlat_bitvec(vec![diff]));
+                    ctx.tiledb.insert(tile, bel, "VR", xlat_bit(diff));
                 }
                 if matches!(
                     edev.grid.kind,
@@ -3626,12 +3624,8 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     let diff_q = ctx.state.get_diff(tile, bel, "DCIUPDATEMODE", "QUIET");
                     assert_eq!(diff_c, diff_q);
                     let diff = diff_a.combine(&!diff_c);
-                    ctx.tiledb.insert(
-                        tile,
-                        bel,
-                        "DCIUPDATEMODE_ASREQUIRED",
-                        xlat_bitvec(vec![diff]),
-                    );
+                    ctx.tiledb
+                        .insert(tile, bel, "DCIUPDATEMODE_ASREQUIRED", xlat_bit(diff));
                 }
                 let mut present = ctx.state.get_diff(tile, bel, "PRESENT", "IOB");
                 if edev.grid.kind.is_spartan3ea() {
@@ -3820,6 +3814,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     GridKind::Virtex2 => "V2",
                     GridKind::Virtex2P | GridKind::Virtex2PX => "V2P",
                     GridKind::Spartan3 => "S3",
+                    GridKind::FpgaCore => unreachable!(),
                     GridKind::Spartan3E => "S3E",
                     GridKind::Spartan3A | GridKind::Spartan3ADsp => {
                         if is_s3a_lr {
@@ -3945,8 +3940,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
                     diff.assert_empty();
                 } else {
                     // ???
-                    ctx.tiledb
-                        .insert(tile, bel, "ENABLE", xlat_bitvec(vec![diff]));
+                    ctx.tiledb.insert(tile, bel, "ENABLE", xlat_bit(diff));
                 }
             }
             if has_any_brefclk(edev, tile, i).is_some() {
diff --git a/prjcombine_ise_hammer/src/io/xc5200.rs b/prjcombine_ise_hammer/src/io/xc5200.rs
index 3d6942ae..110b203d 100644
--- a/prjcombine_ise_hammer/src/io/xc5200.rs
+++ b/prjcombine_ise_hammer/src/io/xc5200.rs
@@ -7,7 +7,13 @@ use crate::{
 pub fn add_fuzzers<'a>(session: &mut Session<IseBackend<'a>>, backend: &IseBackend<'a>) {
     for tile in ["IO.L", "IO.R", "IO.B", "IO.T"] {
         for i in 0..4 {
-            let ctx = FuzzCtx::new(session, backend, tile, format!("IOB{i}"), TileBits::MainAuto);
+            let ctx = FuzzCtx::new(
+                session,
+                backend,
+                tile,
+                format!("IOB{i}"),
+                TileBits::MainAuto,
+            );
             fuzz_enum!(ctx, "SLEW", ["SLOW", "FAST"], [(mode "IOB")]);
             fuzz_enum!(ctx, "PULL", ["PULLUP", "PULLDOWN"], [(mode "IOB")]);
             fuzz_enum!(ctx, "IMUX", ["I", "INOT"], [(mode "IOB"), (attr "DELAYMUX", "NODELAY"), (pin "I")]);
diff --git a/prjcombine_ise_hammer/src/main.rs b/prjcombine_ise_hammer/src/main.rs
index 872338fa..0fc19201 100644
--- a/prjcombine_ise_hammer/src/main.rs
+++ b/prjcombine_ise_hammer/src/main.rs
@@ -136,7 +136,9 @@ fn main() -> Result<(), Box<dyn Error>> {
                     tbus::add_fuzzers(&mut hammer, &backend);
                 }
                 clk::virtex2::add_fuzzers(&mut hammer, &backend);
-                bram::virtex2::add_fuzzers(&mut hammer, &backend);
+                if edev.grid.kind != prjcombine_virtex2::grid::GridKind::FpgaCore {
+                    bram::virtex2::add_fuzzers(&mut hammer, &backend);
+                }
                 if edev.grid.kind == prjcombine_virtex2::grid::GridKind::Spartan3ADsp {
                     dsp::spartan3adsp::add_fuzzers(&mut hammer, &backend);
                 }
@@ -144,9 +146,13 @@ fn main() -> Result<(), Box<dyn Error>> {
                     misc::virtex2::add_fuzzers(&mut hammer, &backend, skip_io);
                 }
                 if !skip_io {
-                    io::virtex2::add_fuzzers(&mut hammer, &backend);
+                    if edev.grid.kind != prjcombine_virtex2::grid::GridKind::FpgaCore {
+                        io::virtex2::add_fuzzers(&mut hammer, &backend);
+                    } else {
+                        io::fpgacore::add_fuzzers(&mut hammer, &backend);
+                    }
                 }
-                if !skip_dcm {
+                if !skip_dcm && edev.grid.kind != prjcombine_virtex2::grid::GridKind::FpgaCore {
                     if !edev.grid.kind.is_spartan3ea() {
                         dcm::virtex2::add_fuzzers(&mut hammer, &backend);
                     } else {
@@ -295,7 +301,9 @@ fn main() -> Result<(), Box<dyn Error>> {
                     tbus::collect_fuzzers(&mut ctx);
                 }
                 clk::virtex2::collect_fuzzers(&mut ctx);
-                bram::virtex2::collect_fuzzers(&mut ctx);
+                if edev.grid.kind != prjcombine_virtex2::grid::GridKind::FpgaCore {
+                    bram::virtex2::collect_fuzzers(&mut ctx);
+                }
                 if edev.grid.kind == prjcombine_virtex2::grid::GridKind::Spartan3ADsp {
                     dsp::spartan3adsp::collect_fuzzers(&mut ctx);
                 }
@@ -303,9 +311,13 @@ fn main() -> Result<(), Box<dyn Error>> {
                     misc::virtex2::collect_fuzzers(&mut ctx, skip_io);
                 }
                 if !skip_io {
-                    io::virtex2::collect_fuzzers(&mut ctx);
+                    if edev.grid.kind != prjcombine_virtex2::grid::GridKind::FpgaCore {
+                        io::virtex2::collect_fuzzers(&mut ctx);
+                    } else {
+                        io::fpgacore::collect_fuzzers(&mut ctx);
+                    }
                 }
-                if !skip_dcm {
+                if !skip_dcm && edev.grid.kind != prjcombine_virtex2::grid::GridKind::FpgaCore {
                     if !edev.grid.kind.is_spartan3ea() {
                         dcm::virtex2::collect_fuzzers(&mut ctx);
                     } else {
diff --git a/prjcombine_ise_hammer/src/misc.rs b/prjcombine_ise_hammer/src/misc.rs
index ad36897a..55941930 100644
--- a/prjcombine_ise_hammer/src/misc.rs
+++ b/prjcombine_ise_hammer/src/misc.rs
@@ -1,8 +1,7 @@
-pub mod xc5200;
+pub mod spartan6;
 pub mod virtex;
 pub mod virtex2;
 pub mod virtex4;
 pub mod virtex5;
 pub mod virtex6;
-pub mod spartan6;
-
+pub mod xc5200;
diff --git a/prjcombine_ise_hammer/src/misc/spartan6.rs b/prjcombine_ise_hammer/src/misc/spartan6.rs
index 9212d5d5..1d50ac92 100644
--- a/prjcombine_ise_hammer/src/misc/spartan6.rs
+++ b/prjcombine_ise_hammer/src/misc/spartan6.rs
@@ -6,7 +6,7 @@ use prjcombine_xilinx_geom::ExpandedDevice;
 
 use crate::{
     backend::{FeatureBit, IseBackend},
-    diff::{concat_bitvec, xlat_bitvec, CollectorCtx, OcdMode},
+    diff::{concat_bitvec, xlat_bit, CollectorCtx, OcdMode},
     fgen::{ExtraFeature, TileBits},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_multi, fuzz_multi_attr_dec, fuzz_one, fuzz_one_extras,
@@ -430,12 +430,10 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         ctx.collect_bit(tile, bel, "MISR_V_ENABLE", "1");
         let mut diff = ctx.state.get_diff(tile, bel, "MISR_H_ENABLE_RESET", "1");
         diff.apply_bit_diff(ctx.tiledb.item(tile, bel, "MISR_H_ENABLE"), true, false);
-        ctx.tiledb
-            .insert(tile, bel, "MISR_H_RESET", xlat_bitvec(vec![diff]));
+        ctx.tiledb.insert(tile, bel, "MISR_H_RESET", xlat_bit(diff));
         let mut diff = ctx.state.get_diff(tile, bel, "MISR_V_ENABLE_RESET", "1");
         diff.apply_bit_diff(ctx.tiledb.item(tile, bel, "MISR_V_ENABLE"), true, false);
-        ctx.tiledb
-            .insert(tile, bel, "MISR_V_RESET", xlat_bitvec(vec![diff]));
+        ctx.tiledb.insert(tile, bel, "MISR_V_RESET", xlat_bit(diff));
     }
 
     {
@@ -631,7 +629,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         diff.apply_bitvec_diff_int(&item, 1, 0xc8);
         ctx.tiledb.insert(tile, bel, "CCLK_DIVISOR", item);
         ctx.tiledb
-            .insert(tile, bel, "EXT_CCLK_ENABLE", xlat_bitvec(vec![diff]));
+            .insert(tile, bel, "EXT_CCLK_ENABLE", xlat_bit(diff));
         ctx.collect_enum_int(tile, bel, "CCLK_DLY", 0..4, 0);
         ctx.collect_enum_int(tile, bel, "CCLK_SEP", 0..4, 0);
         for val in ["0", "1", "2", "3"] {
diff --git a/prjcombine_ise_hammer/src/misc/virtex2.rs b/prjcombine_ise_hammer/src/misc/virtex2.rs
index 982c93c6..e6578c1b 100644
--- a/prjcombine_ise_hammer/src/misc/virtex2.rs
+++ b/prjcombine_ise_hammer/src/misc/virtex2.rs
@@ -15,12 +15,12 @@ use unnamed_entity::EntityId;
 use crate::{
     backend::{FeatureBit, FeatureId, IseBackend, Key},
     diff::{
-        concat_bitvec, xlat_bit_wide, xlat_bitvec, xlat_bool, xlat_bool_default, xlat_enum,
-        xlat_enum_ocd, xlat_item_tile, CollectorCtx, Diff, OcdMode,
+        concat_bitvec, xlat_bit, xlat_bit_wide, xlat_bitvec, xlat_bool, xlat_bool_default,
+        xlat_enum, xlat_enum_ocd, xlat_item_tile, CollectorCtx, Diff, OcdMode,
     },
-    fgen::{TileBits, TileFuzzKV, TileFuzzerGen, TileKV},
+    fgen::{ExtraFeature, ExtraFeatureKind, TileBits, TileFuzzKV, TileFuzzerGen, TileKV},
     fuzz::FuzzCtx,
-    fuzz_enum, fuzz_inv, fuzz_multi, fuzz_one,
+    fuzz_enum, fuzz_inv, fuzz_multi, fuzz_one, fuzz_one_extras,
     io::virtex2::{get_iostds, DciKind, DiffKind},
 };
 
@@ -38,6 +38,7 @@ pub fn add_fuzzers<'a>(
         prjcombine_virtex2::grid::GridKind::Virtex2P
         | prjcombine_virtex2::grid::GridKind::Virtex2PX => ("LL.V2P", "UL.V2P", "LR.V2P", "UR.V2P"),
         prjcombine_virtex2::grid::GridKind::Spartan3 => ("LL.S3", "UL.S3", "LR.S3", "UR.S3"),
+        prjcombine_virtex2::grid::GridKind::FpgaCore => ("LL.FC", "UL.FC", "LR.FC", "UR.FC"),
         prjcombine_virtex2::grid::GridKind::Spartan3E => ("LL.S3E", "UL.S3E", "LR.S3E", "UR.S3E"),
         prjcombine_virtex2::grid::GridKind::Spartan3A
         | prjcombine_virtex2::grid::GridKind::Spartan3ADsp => {
@@ -49,6 +50,8 @@ pub fn add_fuzzers<'a>(
         "REG.COR"
     } else if edev.grid.kind == GridKind::Spartan3 {
         "REG.COR.S3"
+    } else if edev.grid.kind == GridKind::FpgaCore {
+        "REG.COR.FC"
     } else {
         "REG.COR.S3E"
     };
@@ -117,7 +120,7 @@ pub fn add_fuzzers<'a>(
     if edev.grid.kind.is_spartan3a() {
         fuzz_pull(&mut ctx, "CCLK2PIN");
         fuzz_pull(&mut ctx, "MOSI2PIN");
-    } else if edev.grid.kind != GridKind::Spartan3E {
+    } else if edev.grid.kind != GridKind::Spartan3E && edev.grid.kind != GridKind::FpgaCore {
         fuzz_pull(&mut ctx, "M0PIN");
         fuzz_pull(&mut ctx, "M1PIN");
         fuzz_pull(&mut ctx, "M2PIN");
@@ -134,12 +137,14 @@ pub fn add_fuzzers<'a>(
 
     // UL
     let mut ctx = FuzzCtx::new_fake_bel(session, backend, ul, "MISC", TileBits::Cfg);
-    fuzz_global(&mut ctx, "PROGPIN", &["PULLUP", "PULLNONE"]);
-    fuzz_pull(&mut ctx, "TDIPIN");
+    if edev.grid.kind != GridKind::FpgaCore {
+        fuzz_global(&mut ctx, "PROGPIN", &["PULLUP", "PULLNONE"]);
+        fuzz_pull(&mut ctx, "TDIPIN");
+    }
     if edev.grid.kind.is_spartan3a() {
         fuzz_pull(&mut ctx, "TMSPIN");
     }
-    if !edev.grid.kind.is_spartan3ea() {
+    if !edev.grid.kind.is_spartan3ea() && edev.grid.kind != GridKind::FpgaCore {
         fuzz_pull(&mut ctx, "HSWAPENPIN");
     }
     if edev.grid.kind.is_virtex2() {
@@ -159,13 +164,22 @@ pub fn add_fuzzers<'a>(
 
     // LR
     let mut ctx = FuzzCtx::new_fake_bel(session, backend, lr, "MISC", TileBits::Cfg);
-    fuzz_global(&mut ctx, "DONEPIN", &["PULLUP", "PULLNONE"]);
-    if !edev.grid.kind.is_spartan3a() {
+    if edev.grid.kind != GridKind::FpgaCore {
+        fuzz_global(&mut ctx, "DONEPIN", &["PULLUP", "PULLNONE"]);
+    }
+    if !edev.grid.kind.is_spartan3a() && edev.grid.kind != GridKind::FpgaCore {
         fuzz_global(&mut ctx, "CCLKPIN", &["PULLUP", "PULLNONE"]);
     }
     if edev.grid.kind.is_virtex2() {
         fuzz_global(&mut ctx, "POWERDOWNPIN", &["PULLUP", "PULLNONE"]);
     }
+    if edev.grid.kind == GridKind::FpgaCore {
+        for attr in ["ABUFF0", "ABUFF1", "ABUFF2", "ABUFF3"] {
+            for val in ["0", "1"] {
+                fuzz_one!(ctx, attr, val, [], [(global_opt attr, val)]);
+            }
+        }
+    }
     let mut ctx = FuzzCtx::new(session, backend, lr, "STARTUP", TileBits::Cfg);
     fuzz_one!(ctx, "PRESENT", "1", [], [(mode "STARTUP")]);
     fuzz_inv!(ctx, "CLK", [(mode "STARTUP"), (global_opt "STARTUPCLK", "JTAGCLK")]);
@@ -227,13 +241,15 @@ pub fn add_fuzzers<'a>(
 
     // UR
     let mut ctx = FuzzCtx::new_fake_bel(session, backend, ur, "MISC", TileBits::Cfg);
-    fuzz_pull(&mut ctx, "TCKPIN");
-    fuzz_pull(&mut ctx, "TDOPIN");
-    if !edev.grid.kind.is_spartan3a() {
-        fuzz_pull(&mut ctx, "TMSPIN");
-    } else {
-        fuzz_pull(&mut ctx, "MISO2PIN");
-        fuzz_pull(&mut ctx, "CSO2PIN");
+    if edev.grid.kind != GridKind::FpgaCore {
+        fuzz_pull(&mut ctx, "TCKPIN");
+        fuzz_pull(&mut ctx, "TDOPIN");
+        if !edev.grid.kind.is_spartan3a() {
+            fuzz_pull(&mut ctx, "TMSPIN");
+        } else {
+            fuzz_pull(&mut ctx, "MISO2PIN");
+            fuzz_pull(&mut ctx, "CSO2PIN");
+        }
     }
     let ctx = FuzzCtx::new(session, backend, ur, "BSCAN", TileBits::Cfg);
     fuzz_one!(ctx, "PRESENT", "1", [], [(mode "BSCAN")]);
@@ -245,8 +261,124 @@ pub fn add_fuzzers<'a>(
         fuzz_one!(ctx, "PRESENT", "1", [], [(mode "JTAGPPC")]);
     }
 
+    if edev.grid.kind == GridKind::FpgaCore {
+        let ctx = FuzzCtx::new_fake_tile(session, backend, "NULL", "NULL", TileBits::Null);
+        for val in ["NO", "YES"] {
+            let extras = vec![
+                ExtraFeature::new(
+                    ExtraFeatureKind::Corner(edev.grid.col_left(), edev.grid.row_bot()),
+                    "LL.FC",
+                    "MISC",
+                    "MISR_RESET",
+                    val,
+                ),
+                ExtraFeature::new(
+                    ExtraFeatureKind::Corner(edev.grid.col_left(), edev.grid.row_top()),
+                    "UL.FC",
+                    "MISC",
+                    "MISR_RESET",
+                    val,
+                ),
+                ExtraFeature::new(
+                    ExtraFeatureKind::Corner(edev.grid.col_right(), edev.grid.row_bot()),
+                    "LR.FC",
+                    "MISC",
+                    "MISR_RESET",
+                    val,
+                ),
+                ExtraFeature::new(
+                    ExtraFeatureKind::Corner(edev.grid.col_right(), edev.grid.row_top()),
+                    "UR.FC",
+                    "MISC",
+                    "MISR_RESET",
+                    val,
+                ),
+            ];
+            fuzz_one_extras!(ctx, "MISR_RESET", val, [], [
+                (global_opt "MISRRESET", val)
+            ], extras);
+        }
+        let extras = vec![
+            ExtraFeature::new(
+                ExtraFeatureKind::Corner(edev.grid.col_left(), edev.grid.row_bot()),
+                "LL.FC",
+                "MISC",
+                "MISR_CLOCK",
+                "GCLK0",
+            ),
+            ExtraFeature::new(
+                ExtraFeatureKind::Corner(edev.grid.col_left(), edev.grid.row_top()),
+                "UL.FC",
+                "MISC",
+                "MISR_CLOCK",
+                "GCLK0",
+            ),
+            ExtraFeature::new(
+                ExtraFeatureKind::Corner(edev.grid.col_right(), edev.grid.row_bot()),
+                "LR.FC",
+                "MISC",
+                "MISR_CLOCK",
+                "GCLK0",
+            ),
+            ExtraFeature::new(
+                ExtraFeatureKind::Corner(edev.grid.col_right(), edev.grid.row_top()),
+                "UR.FC",
+                "MISC",
+                "MISR_CLOCK",
+                "GCLK0",
+            ),
+            ExtraFeature::new(
+                ExtraFeatureKind::MainFixed(edev.grid.col_left(), edev.grid.row_bot()),
+                "CNR",
+                "MISC",
+                "MISR_CLOCK",
+                "GCLK0",
+            ),
+            ExtraFeature::new(
+                ExtraFeatureKind::MainFixed(edev.grid.col_left(), edev.grid.row_top()),
+                "CNR",
+                "MISC",
+                "MISR_CLOCK",
+                "GCLK0",
+            ),
+            ExtraFeature::new(
+                ExtraFeatureKind::MainFixed(edev.grid.col_right(), edev.grid.row_bot()),
+                "CNR",
+                "MISC",
+                "MISR_CLOCK",
+                "GCLK0",
+            ),
+            ExtraFeature::new(
+                ExtraFeatureKind::MainFixed(edev.grid.col_right(), edev.grid.row_top()),
+                "CNR",
+                "MISC",
+                "MISR_CLOCK",
+                "GCLK0",
+            ),
+            ExtraFeature::new(
+                ExtraFeatureKind::AllGclkvm,
+                "GCLKVM.S3",
+                "GCLKVM",
+                "MISR_CLOCK",
+                "GCLK0",
+            ),
+            ExtraFeature::new(
+                ExtraFeatureKind::AllHclk,
+                "GCLKH",
+                "GCLKH",
+                "MISR_CLOCK",
+                "GCLK0",
+            ),
+        ];
+        fuzz_one_extras!(ctx, "MISR_CLOCK", "GCLK0", [
+            (global_mutex "MISR_CLOCK", "YUP")
+        ], [
+            (global_opt "MISRCLOCK", "GCLK0")
+        ], extras);
+    }
+
     // I/O bank misc control
-    if !skip_io {
+    if !skip_io && edev.grid.kind != GridKind::FpgaCore {
         let package = backend
             .device
             .bonds
@@ -941,8 +1073,10 @@ pub fn add_fuzzers<'a>(
             fuzz_one!(ctx, "DONE_CYCLE", val, [], [(global_opt "DONE_CYCLE", val)]);
         }
         for val in ["0", "1", "2", "3", "4", "5", "6", "NOWAIT"] {
-            fuzz_one!(ctx, "LCK_CYCLE", val, [], [(global_opt "LCK_CYCLE", val)]);
-            if edev.grid.kind != GridKind::Spartan3E {
+            if edev.grid.kind != GridKind::FpgaCore {
+                fuzz_one!(ctx, "LCK_CYCLE", val, [], [(global_opt "LCK_CYCLE", val)]);
+            }
+            if edev.grid.kind != GridKind::Spartan3E && edev.grid.kind != GridKind::FpgaCore {
                 // option is accepted on S3E, but doesn't do anything
                 fuzz_one!(ctx, "MATCH_CYCLE", val, [(global_mutex "DCI", "NO")], [(global_opt "MATCH_CYCLE", val)]);
             }
@@ -952,7 +1086,9 @@ pub fn add_fuzzers<'a>(
             fuzz_one!(ctx, "DONE_PIPE", val, [], [(global_opt "DONEPIPE", val)]);
         }
         for val in ["ENABLE", "DISABLE"] {
-            fuzz_one!(ctx, "DCM_SHUTDOWN", val, [], [(global_opt "DCMSHUTDOWN", val)]);
+            if edev.grid.kind != GridKind::FpgaCore {
+                fuzz_one!(ctx, "DCM_SHUTDOWN", val, [], [(global_opt "DCMSHUTDOWN", val)]);
+            }
             if edev.grid.kind.is_virtex2() {
                 fuzz_one!(ctx, "DCI_SHUTDOWN", val, [], [(global_opt "DCISHUTDOWN", val)]);
                 fuzz_one!(ctx, "POWERDOWN_STATUS", val, [], [(global_opt "POWERDOWNSTATUS", val)]);
@@ -963,7 +1099,7 @@ pub fn add_fuzzers<'a>(
                 "4", "5", "7", "8", "9", "10", "13", "15", "20", "26", "30", "34", "41", "51",
                 "55", "60", "130",
             ][..]
-        } else if edev.grid.kind == GridKind::Spartan3 {
+        } else if !edev.grid.kind.is_spartan3ea() {
             &["6", "12", "25", "50", "3", "100"][..]
         } else {
             &["1", "3", "6", "12", "25", "50"][..]
@@ -978,7 +1114,7 @@ pub fn add_fuzzers<'a>(
             for val in ["100", "25", "50", "200"] {
                 fuzz_one!(ctx, "BUSCLK_FREQ", val, [], [(global_opt "BUSCLKFREQ", val)]);
             }
-            let vals = if edev.grid.kind == GridKind::Spartan3 {
+            let vals = if !edev.grid.kind.is_spartan3ea() {
                 &["80", "90", "95", "100"]
             } else {
                 &["70", "75", "80", "90"]
@@ -1237,6 +1373,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
         prjcombine_virtex2::grid::GridKind::Virtex2P
         | prjcombine_virtex2::grid::GridKind::Virtex2PX => ("LL.V2P", "UL.V2P", "LR.V2P", "UR.V2P"),
         prjcombine_virtex2::grid::GridKind::Spartan3 => ("LL.S3", "UL.S3", "LR.S3", "UR.S3"),
+        prjcombine_virtex2::grid::GridKind::FpgaCore => ("LL.FC", "UL.FC", "LR.FC", "UR.FC"),
         prjcombine_virtex2::grid::GridKind::Spartan3E => ("LL.S3E", "UL.S3E", "LR.S3E", "UR.S3E"),
         prjcombine_virtex2::grid::GridKind::Spartan3A
         | prjcombine_virtex2::grid::GridKind::Spartan3ADsp => {
@@ -1264,8 +1401,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
         for tile in [ll, ul, lr, ur] {
             for bel in ["DCIRESET0", "DCIRESET1"] {
                 let diff = ctx.state.get_diff(tile, bel, "PRESENT", "1");
-                ctx.tiledb
-                    .insert(tile, bel, "ENABLE", xlat_bitvec(vec![diff]));
+                ctx.tiledb.insert(tile, bel, "ENABLE", xlat_bit(diff));
             }
         }
     }
@@ -1340,12 +1476,12 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
                 .assert_empty();
             let (diff_cnr, diff_reg) = get_split_diff(ctx, tile, bel, "VGG_ENABLE_OFFCHIP", "YES");
             ctx.tiledb
-                .insert(tile, bel, "VGG_ENABLE_OFFCHIP", xlat_bitvec(vec![diff_cnr]));
+                .insert(tile, bel, "VGG_ENABLE_OFFCHIP", xlat_bit(diff_cnr));
             ctx.tiledb.insert(
                 "REG.COR1.S3A",
                 bel,
                 "VGG_ENABLE_OFFCHIP",
-                xlat_bitvec(vec![diff_reg]),
+                xlat_bit(diff_reg),
             );
 
             let (item_cnr, item_reg, def) =
@@ -1397,7 +1533,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
     if edev.grid.kind.is_spartan3a() {
         ctx.collect_enum(tile, bel, "CCLK2PIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
         ctx.collect_enum(tile, bel, "MOSI2PIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
-    } else if edev.grid.kind != GridKind::Spartan3E {
+    } else if edev.grid.kind != GridKind::Spartan3E && edev.grid.kind != GridKind::FpgaCore {
         ctx.collect_enum(tile, bel, "M0PIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
         ctx.collect_enum(tile, bel, "M1PIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
         ctx.collect_enum(tile, bel, "M2PIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
@@ -1417,12 +1553,14 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
     // UL
     let tile = ul;
     let bel = "MISC";
-    ctx.collect_enum(tile, bel, "PROGPIN", &["PULLUP", "PULLNONE"]);
-    ctx.collect_enum(tile, bel, "TDIPIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
+    if edev.grid.kind != GridKind::FpgaCore {
+        ctx.collect_enum(tile, bel, "PROGPIN", &["PULLUP", "PULLNONE"]);
+        ctx.collect_enum(tile, bel, "TDIPIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
+    }
     if edev.grid.kind.is_spartan3a() {
         ctx.collect_enum(tile, bel, "TMSPIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
     }
-    if !edev.grid.kind.is_spartan3ea() {
+    if !edev.grid.kind.is_spartan3ea() && edev.grid.kind != GridKind::FpgaCore {
         ctx.collect_enum(tile, bel, "HSWAPENPIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
     }
     if !edev.grid.kind.is_virtex2() {
@@ -1435,10 +1573,8 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
         let mut diffs = diff.split_tiles(&[&[0, 1], &[2, 3]]);
         let diff_ur = diffs.pop().unwrap();
         let diff_ul = diffs.pop().unwrap();
-        ctx.tiledb
-            .insert(tile, bel, "TEST_LL", xlat_bitvec(vec![diff_ul]));
-        ctx.tiledb
-            .insert(ur, bel, "TEST_LL", xlat_bitvec(vec![diff_ur]));
+        ctx.tiledb.insert(tile, bel, "TEST_LL", xlat_bit(diff_ul));
+        ctx.tiledb.insert(ur, bel, "TEST_LL", xlat_bit(diff_ur));
     }
 
     ctx.state
@@ -1453,13 +1589,36 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
     // LR
     let tile = lr;
     let bel = "MISC";
-    ctx.collect_enum(tile, bel, "DONEPIN", &["PULLUP", "PULLNONE"]);
-    if !edev.grid.kind.is_spartan3a() {
+    if edev.grid.kind != GridKind::FpgaCore {
+        ctx.collect_enum(tile, bel, "DONEPIN", &["PULLUP", "PULLNONE"]);
+    }
+    if !edev.grid.kind.is_spartan3a() && edev.grid.kind != GridKind::FpgaCore {
         ctx.collect_enum(tile, bel, "CCLKPIN", &["PULLUP", "PULLNONE"]);
     }
     if edev.grid.kind.is_virtex2() {
         ctx.collect_enum(tile, bel, "POWERDOWNPIN", &["PULLUP", "PULLNONE"]);
     }
+    if edev.grid.kind == GridKind::FpgaCore {
+        let mut bits = vec![];
+        let mut inverts = bitvec![];
+        for attr in ["ABUFF0", "ABUFF1", "ABUFF2", "ABUFF3"] {
+            let item = ctx.extract_enum_bool(tile, bel, attr, "0", "1");
+            bits.extend(item.bits);
+            let TileItemKind::BitVec { invert } = item.kind else {
+                unreachable!()
+            };
+            inverts.extend(invert);
+        }
+        ctx.tiledb.insert(
+            tile,
+            bel,
+            "ABUFF",
+            TileItem {
+                bits,
+                kind: TileItemKind::BitVec { invert: inverts },
+            },
+        );
+    }
     let bel = "STARTUP";
     ctx.state.get_diff(tile, bel, "PRESENT", "1").assert_empty();
     let item = ctx.extract_enum_bool(tile, bel, "CLKINV", "CLK", "CLK_B");
@@ -1486,7 +1645,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
     ctx.insert_int_inv(int_tiles, tile, bel, "GSR", xlat_item_tile(item, int_tidx));
     assert_eq!(dc_gts, dc_gsr);
     ctx.tiledb
-        .insert(tile, bel, "GTS_GSR_ENABLE", xlat_bitvec(vec![dc_gts]));
+        .insert(tile, bel, "GTS_GSR_ENABLE", xlat_bit(dc_gts));
     ctx.collect_enum_bool(tile, bel, "GTS_SYNC", "NO", "YES");
     ctx.collect_enum_bool(tile, bel, "GSR_SYNC", "NO", "YES");
     if edev.grid.kind.is_virtex2() {
@@ -1528,7 +1687,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
             xlat_item_tile(item, int_tidx),
         );
         let diff = ctx.state.get_diff(tile, bel, "PRESENT", "1");
-        let item = xlat_bitvec(vec![diff]);
+        let item = xlat_bit(diff);
         if edev.grid.kind.is_spartan3a() {
             let item = xlat_item_tile(item, reg_tidx);
             ctx.tiledb.insert("REG.CTL.S3A", "ICAP", "ENABLE", item);
@@ -1564,20 +1723,21 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
         let diff_cnr = diffs.pop().unwrap();
         diff_int.discard_bits(&ctx.item_int_inv(int_tiles, tile, bel, "MOSI"));
         diff_int.assert_empty();
-        ctx.tiledb
-            .insert(tile, bel, "ENABLE", xlat_bitvec(vec![diff_cnr]));
+        ctx.tiledb.insert(tile, bel, "ENABLE", xlat_bit(diff_cnr));
     }
 
     // UR
     let tile = ur;
     let bel = "MISC";
-    ctx.collect_enum(tile, bel, "TCKPIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
-    ctx.collect_enum(tile, bel, "TDOPIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
-    if !edev.grid.kind.is_spartan3a() {
-        ctx.collect_enum(tile, bel, "TMSPIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
-    } else {
-        ctx.collect_enum(tile, bel, "MISO2PIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
-        ctx.collect_enum(tile, bel, "CSO2PIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
+    if edev.grid.kind != GridKind::FpgaCore {
+        ctx.collect_enum(tile, bel, "TCKPIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
+        ctx.collect_enum(tile, bel, "TDOPIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
+        if !edev.grid.kind.is_spartan3a() {
+            ctx.collect_enum(tile, bel, "TMSPIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
+        } else {
+            ctx.collect_enum(tile, bel, "MISO2PIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
+            ctx.collect_enum(tile, bel, "CSO2PIN", &["PULLDOWN", "PULLUP", "PULLNONE"]);
+        }
     }
     let bel = "BSCAN";
     ctx.state.get_diff(tile, bel, "PRESENT", "1").assert_empty();
@@ -1602,12 +1762,24 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
     if edev.grid.kind.is_virtex2p() {
         let bel = "JTAGPPC";
         let diff = ctx.state.get_diff(tile, bel, "PRESENT", "1");
-        ctx.tiledb
-            .insert(tile, bel, "ENABLE", xlat_bitvec(vec![diff]));
+        ctx.tiledb.insert(tile, bel, "ENABLE", xlat_bit(diff));
+    }
+
+    if edev.grid.kind == GridKind::FpgaCore {
+        for tile in ["LL.FC", "UL.FC", "LR.FC", "UR.FC"] {
+            let bel = "MISC";
+            ctx.collect_bit(tile, bel, "MISR_CLOCK", "GCLK0");
+            ctx.collect_enum_bool(tile, bel, "MISR_RESET", "NO", "YES");
+        }
+        // could be verified, but meh; they just route given GCLK to CLK3 of every corner tile.
+        ctx.state.get_diff("CNR", "MISC", "MISR_CLOCK", "GCLK0");
+        ctx.state.get_diff("GCLKH", "GCLKH", "MISR_CLOCK", "GCLK0");
+        ctx.state
+            .get_diff("GCLKVM.S3", "GCLKVM", "MISR_CLOCK", "GCLK0");
     }
 
     // I/O bank misc control
-    if !skip_io {
+    if !skip_io && edev.grid.kind != GridKind::FpgaCore {
         if !edev.grid.kind.is_spartan3ea() {
             for (tile, bel) in [
                 (ul, "DCI0"),
@@ -1680,11 +1852,10 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
                     let diff_p = ctx.state.get_diff(tile, bel, "PRESENT", "1");
                     let diff_t = ctx.state.get_diff(tile, bel, "PRESENT", "TEST");
                     assert_eq!(diff_p, diff.combine(&diff_fdh));
-                    ctx.tiledb
-                        .insert(tile, bel, "ENABLE", xlat_bitvec(vec![diff]));
+                    ctx.tiledb.insert(tile, bel, "ENABLE", xlat_bit(diff));
                     let diff_t = diff_t.combine(&!diff_p);
                     ctx.tiledb
-                        .insert(tile, bel, "TEST_ENABLE", xlat_bitvec(vec![diff_t]));
+                        .insert(tile, bel, "TEST_ENABLE", xlat_bit(diff_t));
                 } else {
                     let diff_ar = ctx
                         .state
@@ -1702,15 +1873,13 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
                     assert_eq!(diff_c, diff_ar);
                     let diff_q = diff_q.combine(&!&diff_c);
                     let diff_p = diff_p.combine(&!&diff_c).combine(&!&diff_fdh);
+                    ctx.tiledb.insert(tile, bel, "ENABLE", xlat_bit(diff_c));
+                    ctx.tiledb.insert(tile, bel, "QUIET", xlat_bit(diff_q));
                     ctx.tiledb
-                        .insert(tile, bel, "ENABLE", xlat_bitvec(vec![diff_c]));
-                    ctx.tiledb
-                        .insert(tile, bel, "QUIET", xlat_bitvec(vec![diff_q]));
-                    ctx.tiledb
-                        .insert(tile, bel, "TEST_ENABLE", xlat_bitvec(vec![diff_p]));
+                        .insert(tile, bel, "TEST_ENABLE", xlat_bit(diff_p));
                 }
                 ctx.tiledb
-                    .insert(tile, bel, "FORCE_DONE_HIGH", xlat_bitvec(vec![diff_fdh]));
+                    .insert(tile, bel, "FORCE_DONE_HIGH", xlat_bit(diff_fdh));
 
                 // DCI TERM stuff
                 let mut vals_split = vec![("NONE", Diff::default())];
@@ -1805,22 +1974,14 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
                 let diff5 = diff.filter_tiles(&[8, 5]);
                 let diff6 = diff.filter_tiles(&[6]);
                 let diff7 = diff.filter_tiles(&[7]);
-                ctx.tiledb
-                    .insert(ul, "DCI1", "QUIET", xlat_bitvec(vec![diff0]));
-                ctx.tiledb
-                    .insert(ur, "DCI1", "QUIET", xlat_bitvec(vec![diff1]));
-                ctx.tiledb
-                    .insert(ur, "DCI0", "QUIET", xlat_bitvec(vec![diff2]));
-                ctx.tiledb
-                    .insert(lr, "DCI0", "QUIET", xlat_bitvec(vec![diff3]));
-                ctx.tiledb
-                    .insert(lr, "DCI1", "QUIET", xlat_bitvec(vec![diff4]));
-                ctx.tiledb
-                    .insert(ll, "DCI1", "QUIET", xlat_bitvec(vec![diff5]));
-                ctx.tiledb
-                    .insert(ll, "DCI0", "QUIET", xlat_bitvec(vec![diff6]));
-                ctx.tiledb
-                    .insert(ul, "DCI0", "QUIET", xlat_bitvec(vec![diff7]));
+                ctx.tiledb.insert(ul, "DCI1", "QUIET", xlat_bit(diff0));
+                ctx.tiledb.insert(ur, "DCI1", "QUIET", xlat_bit(diff1));
+                ctx.tiledb.insert(ur, "DCI0", "QUIET", xlat_bit(diff2));
+                ctx.tiledb.insert(lr, "DCI0", "QUIET", xlat_bit(diff3));
+                ctx.tiledb.insert(lr, "DCI1", "QUIET", xlat_bit(diff4));
+                ctx.tiledb.insert(ll, "DCI1", "QUIET", xlat_bit(diff5));
+                ctx.tiledb.insert(ll, "DCI0", "QUIET", xlat_bit(diff6));
+                ctx.tiledb.insert(ul, "DCI0", "QUIET", xlat_bit(diff7));
             }
 
             let tile = ll;
@@ -1847,7 +2008,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
                 alt_diff.apply_bit_diff(ctx.tiledb.item(tile, bel, "ENABLE"), true, false);
                 alt_diff = alt_diff.combine(&!&diff);
                 ctx.tiledb
-                    .insert(tile, "MISC", "DCI_ALTVR", xlat_bitvec(vec![alt_diff]));
+                    .insert(tile, "MISC", "DCI_ALTVR", xlat_bit(alt_diff));
             }
             if edev.grid.kind.is_virtex2() {
                 diff.apply_bitvec_diff(
@@ -1857,7 +2018,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
                 );
             }
             ctx.tiledb
-                .insert(tile, "MISC", "DCI_CLK_ENABLE", xlat_bitvec(vec![diff]));
+                .insert(tile, "MISC", "DCI_CLK_ENABLE", xlat_bit(diff));
         } else {
             let banks = if edev.grid.kind == GridKind::Spartan3E {
                 &[ul, ur, lr, ll][..]
@@ -1971,6 +2132,8 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
             "REG.COR"
         } else if edev.grid.kind == GridKind::Spartan3 {
             "REG.COR.S3"
+        } else if edev.grid.kind == GridKind::FpgaCore {
+            "REG.COR.FC"
         } else {
             "REG.COR.S3E"
         };
@@ -1993,13 +2156,15 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
             "DONE_CYCLE",
             &["1", "2", "3", "4", "5", "6", "KEEP"],
         );
-        ctx.collect_enum(
-            tile,
-            bel,
-            "LCK_CYCLE",
-            &["0", "1", "2", "3", "4", "5", "6", "NOWAIT"],
-        );
-        if edev.grid.kind != GridKind::Spartan3E {
+        if edev.grid.kind != GridKind::FpgaCore {
+            ctx.collect_enum(
+                tile,
+                bel,
+                "LCK_CYCLE",
+                &["0", "1", "2", "3", "4", "5", "6", "NOWAIT"],
+            );
+        }
+        if edev.grid.kind != GridKind::Spartan3E && edev.grid.kind != GridKind::FpgaCore {
             ctx.collect_enum(
                 tile,
                 bel,
@@ -2016,7 +2181,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
                 "4", "5", "7", "8", "9", "10", "13", "15", "20", "26", "30", "34", "41", "51",
                 "55", "60", "130",
             ][..]
-        } else if edev.grid.kind == GridKind::Spartan3 {
+        } else if !edev.grid.kind.is_spartan3ea() {
             &["3", "6", "12", "25", "50", "100"][..]
         } else {
             &["1", "3", "6", "12", "25", "50"][..]
@@ -2027,7 +2192,9 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
         }
         ctx.collect_enum_bool(tile, bel, "DRIVE_DONE", "NO", "YES");
         ctx.collect_enum_bool(tile, bel, "DONE_PIPE", "NO", "YES");
-        ctx.collect_enum_bool(tile, bel, "DCM_SHUTDOWN", "DISABLE", "ENABLE");
+        if edev.grid.kind != GridKind::FpgaCore {
+            ctx.collect_enum_bool(tile, bel, "DCM_SHUTDOWN", "DISABLE", "ENABLE");
+        }
         if edev.grid.kind.is_virtex2() {
             ctx.collect_enum_bool(tile, bel, "POWERDOWN_STATUS", "DISABLE", "ENABLE");
             ctx.state
@@ -2038,7 +2205,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_io: bool) {
                 .assert_empty();
         }
         ctx.collect_enum_bool(tile, bel, "CRC", "DISABLE", "ENABLE");
-        if edev.grid.kind == GridKind::Spartan3 {
+        if matches!(edev.grid.kind, GridKind::Spartan3 | GridKind::FpgaCore) {
             ctx.collect_enum(tile, bel, "VRDSEL", &["100", "95", "90", "80"]);
         } else if edev.grid.kind == GridKind::Spartan3E {
             // ??? 70 == 75?
diff --git a/prjcombine_ise_hammer/src/misc/virtex4.rs b/prjcombine_ise_hammer/src/misc/virtex4.rs
index e266f96c..ea159131 100644
--- a/prjcombine_ise_hammer/src/misc/virtex4.rs
+++ b/prjcombine_ise_hammer/src/misc/virtex4.rs
@@ -8,7 +8,7 @@ use unnamed_entity::EntityId;
 
 use crate::{
     backend::{FeatureBit, IseBackend},
-    diff::{xlat_bitvec, xlat_enum_ocd, xlat_item_tile, CollectorCtx, Diff, OcdMode},
+    diff::{xlat_bit, xlat_bitvec, xlat_enum_ocd, xlat_item_tile, CollectorCtx, Diff, OcdMode},
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits, TileRelation},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_inv, fuzz_multi, fuzz_one, fuzz_one_extras,
@@ -440,7 +440,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
             ctx.state.peek_diff(tile, bel, "MUX.I0", "CKINT0").clone(),
             ctx.state.peek_diff(tile, bel, "MUX.I1", "CKINT0").clone(),
         );
-        let ien_item = xlat_bitvec(vec![ien_diff]);
+        let ien_item = xlat_bit(ien_diff);
         for mux in ["MUX.I0", "MUX.I1"] {
             let mut vals = vec![("NONE", Diff::default())];
             for val in [
@@ -468,18 +468,10 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
         } else {
             let diffs = diff.split_tiles(&[&[32], &[33]]);
             let [diff_b, diff_t] = diffs.try_into().unwrap();
-            ctx.tiledb.insert(
-                "CLK_TERM_B",
-                "CLK_TERM",
-                "GCLK_ENABLE",
-                xlat_bitvec(vec![diff_b]),
-            );
-            ctx.tiledb.insert(
-                "CLK_TERM_T",
-                "CLK_TERM",
-                "GCLK_ENABLE",
-                xlat_bitvec(vec![diff_t]),
-            );
+            ctx.tiledb
+                .insert("CLK_TERM_B", "CLK_TERM", "GCLK_ENABLE", xlat_bit(diff_b));
+            ctx.tiledb
+                .insert("CLK_TERM_T", "CLK_TERM", "GCLK_ENABLE", xlat_bit(diff_t));
         }
     }
 
diff --git a/prjcombine_ise_hammer/src/misc/virtex5.rs b/prjcombine_ise_hammer/src/misc/virtex5.rs
index 8fe3cc68..16167a14 100644
--- a/prjcombine_ise_hammer/src/misc/virtex5.rs
+++ b/prjcombine_ise_hammer/src/misc/virtex5.rs
@@ -8,7 +8,7 @@ use unnamed_entity::EntityId;
 
 use crate::{
     backend::{FeatureBit, IseBackend},
-    diff::{xlat_bitvec, CollectorCtx, OcdMode},
+    diff::{xlat_bit, xlat_bitvec, CollectorCtx, OcdMode},
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_inv, fuzz_multi, fuzz_multi_attr_hex, fuzz_one, fuzz_one_extras,
@@ -591,6 +591,5 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     let bel = "MISC";
     let mut diff = ctx.state.get_diff(tile, bel, "DD_OVERRIDE", "YES");
     diff.bits.remove(&FeatureBit::new(1, 0, 0));
-    ctx.tiledb
-        .insert(tile, bel, "DD_OVERRIDE", xlat_bitvec(vec![diff]));
+    ctx.tiledb.insert(tile, bel, "DD_OVERRIDE", xlat_bit(diff));
 }
diff --git a/prjcombine_ise_hammer/src/misc/virtex6.rs b/prjcombine_ise_hammer/src/misc/virtex6.rs
index c63c5a0e..25bb184c 100644
--- a/prjcombine_ise_hammer/src/misc/virtex6.rs
+++ b/prjcombine_ise_hammer/src/misc/virtex6.rs
@@ -5,7 +5,7 @@ use prjcombine_virtex_bitstream::Reg;
 
 use crate::{
     backend::{FeatureBit, IseBackend},
-    diff::{xlat_bitvec, xlat_enum_ocd, CollectorCtx, OcdMode},
+    diff::{xlat_bit, xlat_bitvec, xlat_enum_ocd, CollectorCtx, OcdMode},
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_inv, fuzz_multi, fuzz_multi_attr_hex, fuzz_one, fuzz_one_extras,
@@ -678,8 +678,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx) {
     let bel = "MISC";
     let mut diff = ctx.state.get_diff(tile, bel, "FUSE_SHADOW", "");
     diff.bits.remove(&FeatureBit::new(1, 0, 0));
-    ctx.tiledb
-        .insert(tile, bel, "FUSE_SHADOW", xlat_bitvec(vec![diff]));
+    ctx.tiledb.insert(tile, bel, "FUSE_SHADOW", xlat_bit(diff));
 
     let tile = "REG.TRIM";
     let bel = "MISC";
diff --git a/prjcombine_ise_hammer/src/pll.rs b/prjcombine_ise_hammer/src/pll.rs
index 758885cf..ce3f0940 100644
--- a/prjcombine_ise_hammer/src/pll.rs
+++ b/prjcombine_ise_hammer/src/pll.rs
@@ -1 +1 @@
-pub mod spartan6;
\ No newline at end of file
+pub mod spartan6;
diff --git a/prjcombine_ise_hammer/src/pll/spartan6.rs b/prjcombine_ise_hammer/src/pll/spartan6.rs
index 8879b713..01a2a266 100644
--- a/prjcombine_ise_hammer/src/pll/spartan6.rs
+++ b/prjcombine_ise_hammer/src/pll/spartan6.rs
@@ -6,7 +6,7 @@ use unnamed_entity::EntityId;
 
 use crate::{
     backend::{FeatureBit, IseBackend},
-    diff::{extract_bitvec_val_part, xlat_bitvec, xlat_enum_ocd, CollectorCtx, OcdMode},
+    diff::{extract_bitvec_val_part, xlat_bit, xlat_enum_ocd, CollectorCtx, OcdMode},
     fgen::{ExtraFeature, ExtraFeatureKind, TileBits, TileRelation},
     fuzz::FuzzCtx,
     fuzz_enum, fuzz_inv, fuzz_multi_attr_bin, fuzz_multi_attr_dec, fuzz_one, fuzz_one_extras,
@@ -718,7 +718,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_dcm: bool) {
         let diff2 = diff2.combine(&!&diff1);
         diffs.push((val, diff1));
         ctx.tiledb
-            .insert(tile, bel, "CLKINSEL_STATIC", xlat_bitvec(vec![diff2]));
+            .insert(tile, bel, "CLKINSEL_STATIC", xlat_bit(diff2));
     }
     for val in ["CKINT1", "CLK_FROM_DCM0", "CLK_FROM_DCM1"] {
         let mut diff = ctx.state.get_diff(tile, bel, "MUX.CLKIN2", val);
@@ -730,7 +730,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_dcm: bool) {
 
     let diff = ctx.state.get_diff(tile, bel, "PLL_CLKCNTRL", "");
     ctx.tiledb
-        .insert(tile, bel, "CLKIN_CLKFBIN_USED", xlat_bitvec(vec![!diff]));
+        .insert(tile, bel, "CLKIN_CLKFBIN_USED", xlat_bit(!diff));
 
     let mut diffs = ctx.state.get_diffs(tile, bel, "PLL_IO_CLKSRC", "");
     diffs[0].apply_enum_diff(
@@ -854,8 +854,7 @@ pub fn collect_fuzzers(ctx: &mut CollectorCtx, skip_dcm: bool) {
     present.apply_bitvec_diff_int(ctx.tiledb.item(tile, bel, "PLL_CP"), 2, 0);
     present.apply_bitvec_diff_int(ctx.tiledb.item(tile, bel, "PLL_CP_REPL"), 2, 0);
 
-    ctx.tiledb
-        .insert(tile, bel, "ENABLE", xlat_bitvec(vec![present]));
+    ctx.tiledb.insert(tile, bel, "ENABLE", xlat_bit(present));
 
     ctx.state
         .get_diff(tile, bel, "COMPENSATION", "SYSTEM_SYNCHRONOUS")
diff --git a/prjcombine_rawdump/src/bin/rd2html.rs b/prjcombine_rawdump/src/bin/rd2html.rs
index 18d3a135..1bf37026 100644
--- a/prjcombine_rawdump/src/bin/rd2html.rs
+++ b/prjcombine_rawdump/src/bin/rd2html.rs
@@ -526,6 +526,11 @@ const SPARTAN3_TILES: &[TileInfo] = &[
     TileInfo("EMPTY16X2", SINGLE, &[]),
     TileInfo("EMPTY0X3", SINGLE, &[]),
     TileInfo("EMPTY0X2", SINGLE, &[]),
+    // FPGACORE
+    TileInfo("BTERM", SINGLE, &["bterm", "iob"]),
+    TileInfo("TTERM", SINGLE, &["tterm", "iob"]),
+    TileInfo("BCLKTERM", SINGLE, &["bterm", "iob"]),
+    TileInfo("TCLKTERM", SINGLE, &["tterm", "iob"]),
 ];
 
 const SPARTAN3E_TILES: &[TileInfo] = &[
@@ -3561,7 +3566,7 @@ fn main() -> Result<(), Box<dyn Error>> {
         "xc5200" => (XC5200_TILES, true),
         "virtex" | "virtexe" => (VIRTEX_TILES, false),
         "virtex2" | "virtex2p" => (VIRTEX2_TILES, false),
-        "spartan3" => (SPARTAN3_TILES, false),
+        "spartan3" | "fpgacore" => (SPARTAN3_TILES, false),
         "spartan3e" | "spartan3a" | "spartan3adsp" => (SPARTAN3E_TILES, false),
         "spartan6" => (SPARTAN6_TILES, true),
         "virtex4" => (VIRTEX4_TILES, false),
diff --git a/prjcombine_rdbuild/src/lib.rs b/prjcombine_rdbuild/src/lib.rs
index ef4effad..31ae76e6 100644
--- a/prjcombine_rdbuild/src/lib.rs
+++ b/prjcombine_rdbuild/src/lib.rs
@@ -267,6 +267,16 @@ impl PartBuilder {
                 let base = self.part.slot_kinds.get_or_insert(base);
                 let (bx, by) = minxy[&base];
                 TkSiteSlot::Xy(base, (x - bx) as u8, (y - by) as u8)
+            } else if self.part.family == "fpgacore" && k.starts_with("IBUF") {
+                TkSiteSlot::Indexed(
+                    self.part.slot_kinds.get_or_insert("IBUF"),
+                    from_pinnum(p, "I"),
+                )
+            } else if self.part.family == "fpgacore" && k.starts_with("OBUF") {
+                TkSiteSlot::Indexed(
+                    self.part.slot_kinds.get_or_insert("OBUF"),
+                    from_pinnum(p, "O"),
+                )
             } else if (self.part.family.starts_with("virtex2")
                 || self.part.family.starts_with("spartan3"))
                 && (k.starts_with("IOB") || k.starts_with("IBUF") || k.starts_with("DIFF"))
@@ -278,6 +288,7 @@ impl PartBuilder {
             } else if ((self.part.family.starts_with("virtex2") || self.part.family == "spartan3")
                 && k.starts_with("DCI"))
                 || (self.part.family == "spartan3" && k == "BUFGMUX")
+                || (self.part.family == "fpgacore" && k == "BUFG")
             {
                 TkSiteSlot::Indexed(self.part.slot_kinds.get_or_insert(k), get_lastnum(n))
             } else if self.part.family.starts_with("virtex2") && k == "BUFGMUX" {
diff --git a/prjcombine_spartan6/src/bond.rs b/prjcombine_spartan6/src/bond.rs
index 578a8996..d250d92d 100644
--- a/prjcombine_spartan6/src/bond.rs
+++ b/prjcombine_spartan6/src/bond.rs
@@ -76,6 +76,10 @@ impl Bond {
                 _ => (),
             }
         }
-        ExpandedBond { bond: self, ios, gts }
+        ExpandedBond {
+            bond: self,
+            ios,
+            gts,
+        }
     }
 }
diff --git a/prjcombine_virtex/src/expanded.rs b/prjcombine_virtex/src/expanded.rs
index 544dcd54..a3395d69 100644
--- a/prjcombine_virtex/src/expanded.rs
+++ b/prjcombine_virtex/src/expanded.rs
@@ -65,11 +65,7 @@ impl<'a> ExpandedDevice<'a> {
         } else {
             unreachable!()
         };
-        Io {
-            coord,
-            bank,
-            name,
-        }
+        Io { coord, bank, name }
     }
 
     pub fn get_bonded_ios(&'a self) -> Vec<Io<'a>> {
diff --git a/prjcombine_virtex2/src/bond.rs b/prjcombine_virtex2/src/bond.rs
index 18084a59..3822c0f7 100644
--- a/prjcombine_virtex2/src/bond.rs
+++ b/prjcombine_virtex2/src/bond.rs
@@ -79,6 +79,10 @@ impl Bond {
                 _ => (),
             }
         }
-        ExpandedBond { bond: self, ios, gts }
+        ExpandedBond {
+            bond: self,
+            ios,
+            gts,
+        }
     }
 }
diff --git a/prjcombine_virtex2/src/expand.rs b/prjcombine_virtex2/src/expand.rs
index 4461c5b1..6713f8fa 100644
--- a/prjcombine_virtex2/src/expand.rs
+++ b/prjcombine_virtex2/src/expand.rs
@@ -324,6 +324,7 @@ impl<'a, 'b> Expander<'a, 'b> {
             GridKind::Virtex2 => "LL.V2",
             GridKind::Virtex2P | GridKind::Virtex2PX => "LL.V2P",
             GridKind::Spartan3 => "LL.S3",
+            GridKind::FpgaCore => "LL.FC",
             GridKind::Spartan3E => "LL.S3E",
             GridKind::Spartan3A | GridKind::Spartan3ADsp => "LL.S3A",
         };
@@ -354,6 +355,7 @@ impl<'a, 'b> Expander<'a, 'b> {
             GridKind::Virtex2 => "LR.V2",
             GridKind::Virtex2P | GridKind::Virtex2PX => "LR.V2P",
             GridKind::Spartan3 => "LR.S3",
+            GridKind::FpgaCore => "LR.FC",
             GridKind::Spartan3E => "LR.S3E",
             GridKind::Spartan3A | GridKind::Spartan3ADsp => "LR.S3A",
         };
@@ -397,6 +399,7 @@ impl<'a, 'b> Expander<'a, 'b> {
             GridKind::Virtex2 => "UL.V2",
             GridKind::Virtex2P | GridKind::Virtex2PX => "UL.V2P",
             GridKind::Spartan3 => "UL.S3",
+            GridKind::FpgaCore => "UL.FC",
             GridKind::Spartan3E => "UL.S3E",
             GridKind::Spartan3A | GridKind::Spartan3ADsp => "UL.S3A",
         };
@@ -434,6 +437,7 @@ impl<'a, 'b> Expander<'a, 'b> {
             GridKind::Virtex2 => "UR.V2",
             GridKind::Virtex2P | GridKind::Virtex2PX => "UR.V2P",
             GridKind::Spartan3 => "UR.S3",
+            GridKind::FpgaCore => "UR.FC",
             GridKind::Spartan3E => "UR.S3E",
             GridKind::Spartan3A | GridKind::Spartan3ADsp => "UR.S3A",
         };
@@ -559,6 +563,16 @@ impl<'a, 'b> Expander<'a, 'b> {
                     ioi_naming = "IOI.S3.T";
                     iobs = &[2, 1, 0];
                 }
+                GridKind::FpgaCore => {
+                    pads = &[3, 7, 2, 6, 1, 5, 0, 4];
+                    iobs_kind = Some(("IOBS.FC.T", 1));
+                    ipads = &[];
+                    int_kind = "INT.IOI.FC";
+                    int_naming = "INT.IOI.FC";
+                    ioi_kind = "IOI.FC";
+                    ioi_naming = "IOI.FC.T";
+                    iobs = &[3, 7, 2, 6, 1, 5, 0, 4];
+                }
                 GridKind::Spartan3E => {
                     (pads, ipads, term, iobs_kind) = match cd.io {
                         ColumnIoKind::Single => {
@@ -726,7 +740,11 @@ impl<'a, 'b> Expander<'a, 'b> {
                 } else {
                     col.to_idx() - 1
                 };
-                node.add_bel(0, format!("RANDOR_X{x}Y1"));
+                if self.grid.kind == GridKind::FpgaCore {
+                    node.add_bel(0, format!("RANDOR_X{x}Y0"));
+                } else {
+                    node.add_bel(0, format!("RANDOR_X{x}Y1"));
+                }
             }
         }
     }
@@ -798,6 +816,16 @@ impl<'a, 'b> Expander<'a, 'b> {
                     ioi_naming = "IOI.S3.R";
                     iobs = &[2, 1, 0];
                 }
+                GridKind::FpgaCore => {
+                    pads = &[3, 7, 2, 6, 1, 5, 0, 4];
+                    iobs_kind = Some(("IOBS.FC.R", 1));
+                    ipads = &[];
+                    int_kind = "INT.IOI.FC";
+                    int_naming = "INT.IOI.FC";
+                    ioi_kind = "IOI.FC";
+                    ioi_naming = "IOI.FC.R";
+                    iobs = &[3, 7, 2, 6, 1, 5, 0, 4];
+                }
                 GridKind::Spartan3E => {
                     (pads, ipads, term, iobs_kind) = match rd {
                         RowIoKind::Single => {
@@ -1073,6 +1101,16 @@ impl<'a, 'b> Expander<'a, 'b> {
                     ioi_naming = "IOI.S3.B";
                     iobs = &[2, 1, 0];
                 }
+                GridKind::FpgaCore => {
+                    pads = &[3, 7, 2, 6, 1, 5, 0, 4];
+                    iobs_kind = Some(("IOBS.FC.B", 1));
+                    ipads = &[];
+                    int_kind = "INT.IOI.FC";
+                    int_naming = "INT.IOI.FC";
+                    ioi_kind = "IOI.FC";
+                    ioi_naming = "IOI.FC.B";
+                    iobs = &[3, 7, 2, 6, 1, 5, 0, 4];
+                }
                 GridKind::Spartan3E => {
                     (pads, ipads, term, iobs_kind) = match cd.io {
                         ColumnIoKind::Single => {
@@ -1245,7 +1283,7 @@ impl<'a, 'b> Expander<'a, 'b> {
                     &coords,
                 );
             }
-            if !self.grid.kind.is_virtex2() {
+            if !self.grid.kind.is_virtex2() && self.grid.kind != GridKind::FpgaCore {
                 let node = self.die.add_xnode(
                     (col, row),
                     self.db.get_node("RANDOR"),
@@ -1330,6 +1368,16 @@ impl<'a, 'b> Expander<'a, 'b> {
                     ioi_naming = "IOI.S3.L";
                     iobs = &[0, 1, 2];
                 }
+                GridKind::FpgaCore => {
+                    pads = &[0, 4, 1, 5, 2, 6, 3, 7];
+                    iobs_kind = Some(("IOBS.FC.L", 1));
+                    ipads = &[];
+                    int_kind = "INT.IOI.FC";
+                    int_naming = "INT.IOI.FC";
+                    ioi_kind = "IOI.FC";
+                    ioi_naming = "IOI.FC.L";
+                    iobs = &[0, 4, 1, 5, 2, 6, 3, 7];
+                }
                 GridKind::Spartan3E => {
                     (pads, ipads, term, iobs_kind) = match rd {
                         RowIoKind::Single => {
@@ -1590,6 +1638,7 @@ impl<'a, 'b> Expander<'a, 'b> {
         let bram_kind = match self.grid.kind {
             GridKind::Virtex2 | GridKind::Virtex2P | GridKind::Virtex2PX => ["INT.BRAM"; 4],
             GridKind::Spartan3 => ["INT.BRAM.S3"; 4],
+            GridKind::FpgaCore => return,
             GridKind::Spartan3E => ["INT.BRAM.S3E"; 4],
             GridKind::Spartan3A => [
                 "INT.BRAM.S3A.03",
@@ -1644,6 +1693,7 @@ impl<'a, 'b> Expander<'a, 'b> {
                     | GridKind::Virtex2P
                     | GridKind::Virtex2PX
                     | GridKind::Spartan3 => "INT.BRAM",
+                    GridKind::FpgaCore => unreachable!(),
                     GridKind::Spartan3E | GridKind::Spartan3A => {
                         if self.rows_brk.contains(&row) {
                             "INT.BRAM.BRK"
@@ -1715,6 +1765,7 @@ impl<'a, 'b> Expander<'a, 'b> {
                     let kind = match self.grid.kind {
                         GridKind::Virtex2 | GridKind::Virtex2P | GridKind::Virtex2PX => "BRAM",
                         GridKind::Spartan3 => "BRAM.S3",
+                        GridKind::FpgaCore => unreachable!(),
                         GridKind::Spartan3E => "BRAM.S3E",
                         GridKind::Spartan3A => "BRAM.S3A",
                         GridKind::Spartan3ADsp => "BRAM.S3ADSP",
@@ -2838,6 +2889,11 @@ impl<'a, 'b> Expander<'a, 'b> {
     }
 
     fn fill_clkbt_s3(&mut self) {
+        let (clkb, clkt, bufg) = match self.grid.kind {
+            GridKind::Spartan3 => ("CLKB.S3", "CLKT.S3", "BUFGMUX"),
+            GridKind::FpgaCore => ("CLKB.FC", "CLKT.FC", "BUFG"),
+            _ => unreachable!(),
+        };
         let row_b = self.grid.row_bot();
         let row_t = self.grid.row_top();
         let vyb = 0;
@@ -2845,29 +2901,29 @@ impl<'a, 'b> Expander<'a, 'b> {
         let vx = self.vcc_xlut[self.grid.col_clk] - 1;
         let node = self.die.add_xnode(
             (self.grid.col_clk, row_b),
-            self.db.get_node("CLKB.S3"),
+            self.db.get_node(clkb),
             &["CLKB"],
-            self.db.get_node_naming("CLKB.S3"),
+            self.db.get_node_naming(clkb),
             &[(self.grid.col_clk - 1, row_b)],
         );
         node.tie_name = Some(format!("VCC_X{vx}Y{vyb}"));
-        node.add_bel(0, "BUFGMUX0".to_string());
-        node.add_bel(1, "BUFGMUX1".to_string());
-        node.add_bel(2, "BUFGMUX2".to_string());
-        node.add_bel(3, "BUFGMUX3".to_string());
+        node.add_bel(0, format!("{bufg}0"));
+        node.add_bel(1, format!("{bufg}1"));
+        node.add_bel(2, format!("{bufg}2"));
+        node.add_bel(3, format!("{bufg}3"));
         node.add_bel(4, format!("GSIG_X{x}Y0", x = self.grid.col_clk.to_idx()));
         let node = self.die.add_xnode(
             (self.grid.col_clk, row_t),
-            self.db.get_node("CLKT.S3"),
+            self.db.get_node(clkt),
             &["CLKT"],
-            self.db.get_node_naming("CLKT.S3"),
+            self.db.get_node_naming(clkt),
             &[(self.grid.col_clk - 1, row_t)],
         );
         node.tie_name = Some(format!("VCC_X{vx}Y{vyt}"));
-        node.add_bel(0, "BUFGMUX4".to_string());
-        node.add_bel(1, "BUFGMUX5".to_string());
-        node.add_bel(2, "BUFGMUX6".to_string());
-        node.add_bel(3, "BUFGMUX7".to_string());
+        node.add_bel(0, format!("{bufg}4"));
+        node.add_bel(1, format!("{bufg}5"));
+        node.add_bel(2, format!("{bufg}6"));
+        node.add_bel(3, format!("{bufg}7"));
         node.add_bel(4, format!("GSIG_X{x}Y1", x = self.grid.col_clk.to_idx()));
     }
 
@@ -3164,7 +3220,9 @@ impl<'a, 'b> Expander<'a, 'b> {
                 }
                 let mut kind = "GCLKH";
                 let mut naming = "GCLKH";
-                let name = if self.grid.kind.is_virtex2() || self.grid.kind == GridKind::Spartan3 {
+                let name = if self.grid.kind.is_virtex2()
+                    || matches!(self.grid.kind, GridKind::Spartan3 | GridKind::FpgaCore)
+                {
                     let mut r = self.grid.rows_hclk.len() - i;
                     if self.grid.columns[col].kind == ColumnKind::Bram {
                         let c = self.bramclut[col];
@@ -3274,10 +3332,12 @@ impl<'a, 'b> Expander<'a, 'b> {
                     self.db.get_node_naming(naming),
                     &[(col, row_m - 1), (col, row_m)],
                 );
-                if self.grid.kind.is_virtex2() || self.grid.kind == GridKind::Spartan3 {
+                if self.grid.kind.is_virtex2()
+                    || matches!(self.grid.kind, GridKind::Spartan3 | GridKind::FpgaCore)
+                {
                     let gsx = if col < self.grid.col_clk {
                         col.to_idx()
-                    } else if self.grid.kind == GridKind::Spartan3 {
+                    } else if !self.grid.kind.is_spartan3ea() {
                         col.to_idx() + 1
                     } else {
                         col.to_idx() + 2
@@ -3342,7 +3402,8 @@ impl<'a, 'b> Expander<'a, 'b> {
             } else if let Some((col_cl, col_cr)) = self.grid.cols_clkv {
                 let r = self.grid.rows_hclk.len() - i;
                 for (lr, col) in [('L', col_cl), ('R', col_cr)] {
-                    let name = if self.grid.kind == GridKind::Spartan3 {
+                    let name = if matches!(self.grid.kind, GridKind::Spartan3 | GridKind::FpgaCore)
+                    {
                         format!("{lr}CLKVCR{r}")
                     } else {
                         let x = self.xlut[col] - 1;
@@ -3389,7 +3450,7 @@ impl<'a, 'b> Expander<'a, 'b> {
 
     fn fill_gclkvm(&mut self) {
         if let Some((col_cl, col_cr)) = self.grid.cols_clkv {
-            if self.grid.kind == GridKind::Spartan3 {
+            if matches!(self.grid.kind, GridKind::Spartan3 | GridKind::FpgaCore) {
                 self.die.add_xnode(
                     (col_cl, self.grid.row_mid()),
                     self.db.get_node("GCLKVM.S3"),
@@ -3625,7 +3686,7 @@ impl Grid {
         expander.fill_int_sites();
         if self.kind.is_virtex2() {
             expander.fill_clkbt_v2();
-        } else if self.kind == GridKind::Spartan3 {
+        } else if matches!(self.kind, GridKind::Spartan3 | GridKind::FpgaCore) {
             expander.fill_clkbt_s3();
         } else {
             expander.fill_clkbt_s3e();
diff --git a/prjcombine_virtex2/src/expanded.rs b/prjcombine_virtex2/src/expanded.rs
index 6c3e29ac..c770bec5 100644
--- a/prjcombine_virtex2/src/expanded.rs
+++ b/prjcombine_virtex2/src/expanded.rs
@@ -102,6 +102,7 @@ impl<'a> ExpandedDevice<'a> {
                     unreachable!()
                 }
             }
+            GridKind::FpgaCore => 0,
             GridKind::Spartan3E | GridKind::Spartan3A | GridKind::Spartan3ADsp => {
                 if coord.row == self.grid.row_top() {
                     0
@@ -156,6 +157,7 @@ impl<'a> ExpandedDevice<'a> {
                     }
                 }
             }
+            GridKind::FpgaCore => IoDiffKind::None,
             GridKind::Spartan3E => match coord.iob.to_idx() {
                 0 => IoDiffKind::P(TileIobId::from_idx(1)),
                 1 => IoDiffKind::N(TileIobId::from_idx(0)),
diff --git a/prjcombine_virtex2/src/grid.rs b/prjcombine_virtex2/src/grid.rs
index 61a56e6c..3725222d 100644
--- a/prjcombine_virtex2/src/grid.rs
+++ b/prjcombine_virtex2/src/grid.rs
@@ -21,6 +21,7 @@ pub enum GridKind {
     Virtex2P,
     Virtex2PX,
     Spartan3,
+    FpgaCore,
     Spartan3E,
     Spartan3A,
     Spartan3ADsp,
@@ -296,7 +297,7 @@ impl Grid {
                 }
                 _ => None,
             }
-        } else if self.kind == GridKind::Spartan3 {
+        } else if matches!(self.kind, GridKind::Spartan3 | GridKind::FpgaCore) {
             match edge {
                 Dir::S => {
                     if idx < 2 {
diff --git a/prjcombine_virtex2_rd2db/src/bond.rs b/prjcombine_virtex2_rd2db/src/bond.rs
index 89105d30..1dcc9f98 100644
--- a/prjcombine_virtex2_rd2db/src/bond.rs
+++ b/prjcombine_virtex2_rd2db/src/bond.rs
@@ -5,6 +5,7 @@ use prjcombine_virtex2::bond::{Bond, BondPin, CfgPin, GtPin};
 use prjcombine_virtex2::expanded::ExpandedDevice;
 
 use prjcombine_rdgrid::split_num;
+use prjcombine_virtex2::grid::GridKind;
 
 pub fn make_bond(edev: &ExpandedDevice, pins: &[PkgPin]) -> Bond {
     let mut bond_pins = BTreeMap::new();
@@ -19,11 +20,16 @@ pub fn make_bond(edev: &ExpandedDevice, pins: &[PkgPin]) -> Bond {
         let bpin = if let Some(ref pad) = pin.pad {
             if pad.starts_with("PAD") || pad.starts_with("IPAD") || pad.starts_with("CLK") {
                 let io = io_lookup[pad];
-                assert_eq!(pin.vref_bank, Some(io.bank));
-                let old = io_banks.insert(io.bank, pin.vcco_bank.unwrap());
-                assert!(old.is_none() || old == Some(pin.vcco_bank.unwrap()));
-                if pin.func.contains("VREF_") {
-                    vref.insert(io.coord);
+                if edev.grid.kind != GridKind::FpgaCore {
+                    assert_eq!(pin.vref_bank, Some(io.bank));
+                    let old = io_banks.insert(io.bank, pin.vcco_bank.unwrap());
+                    assert!(old.is_none() || old == Some(pin.vcco_bank.unwrap()));
+                    if pin.func.contains("VREF_") {
+                        vref.insert(io.coord);
+                    }
+                } else {
+                    assert_eq!(pin.vref_bank, None);
+                    assert_eq!(pin.vcco_bank, None);
                 }
                 BondPin::Io(io.coord)
             } else if let Some((n, b)) = split_num(pad) {
diff --git a/prjcombine_virtex2_rd2db/src/grid.rs b/prjcombine_virtex2_rd2db/src/grid.rs
index d2e9a778..821824d9 100644
--- a/prjcombine_virtex2_rd2db/src/grid.rs
+++ b/prjcombine_virtex2_rd2db/src/grid.rs
@@ -23,6 +23,7 @@ fn get_kind(rd: &Part) -> GridKind {
             }
         }
         "spartan3" => GridKind::Spartan3,
+        "fpgacore" => GridKind::FpgaCore,
         "spartan3e" => GridKind::Spartan3E,
         "spartan3a" => GridKind::Spartan3A,
         "spartan3adsp" => GridKind::Spartan3ADsp,
@@ -136,6 +137,10 @@ fn get_cols_io(rd: &Part, int: &IntGrid, kind: GridKind, cols: &mut EntityVec<Co
                     }
                 }
             }
+            GridKind::FpgaCore => {
+                cols[col].io = ColumnIoKind::Single;
+                col += 1;
+            }
             GridKind::Spartan3A | GridKind::Spartan3ADsp => {
                 for i in 0..2 {
                     cols[col].io = ColumnIoKind::Double(i as u8);
@@ -260,7 +265,7 @@ fn get_rows(rd: &Part, int: &IntGrid, kind: GridKind) -> EntityVec<RowId, RowIoK
                     }
                 }
             }
-            GridKind::Spartan3 => {
+            GridKind::Spartan3 | GridKind::FpgaCore => {
                 res.push(RowIoKind::Single);
             }
             GridKind::Spartan3E => {
@@ -394,6 +399,9 @@ fn get_has_small_int(rd: &Part) -> bool {
 }
 
 fn handle_spec_io(rd: &Part, grid: &mut Grid, int: &IntGrid) {
+    if grid.kind == GridKind::FpgaCore {
+        return;
+    }
     let mut io_lookup = HashMap::new();
     for (&crd, tile) in &rd.tiles {
         let tk = &rd.tile_kinds[tile.kind];
diff --git a/prjcombine_virtex2_rd2db/src/int_s3.rs b/prjcombine_virtex2_rd2db/src/int_s3.rs
index 0b3015d1..f26a6ef8 100644
--- a/prjcombine_virtex2_rd2db/src/int_s3.rs
+++ b/prjcombine_virtex2_rd2db/src/int_s3.rs
@@ -5,7 +5,14 @@ use unnamed_entity::EntityId;
 use prjcombine_rdintb::IntBuilder;
 
 pub fn make_int_db(rd: &Part) -> IntDb {
-    let mut builder = IntBuilder::new("spartan3", rd);
+    let mut builder = IntBuilder::new(
+        if rd.family == "fpgacore" {
+            "fpgacore"
+        } else {
+            "spartan3"
+        },
+        rd,
+    );
 
     builder.wire(
         "PULLUP",
@@ -167,7 +174,8 @@ pub fn make_int_db(rd: &Part) -> IntDb {
         }
     }
 
-    let lh: Vec<_> = (0..24)
+    let ll_len = if rd.family == "fpgacore" { 12 } else { 24 };
+    let lh: Vec<_> = (0..ll_len)
         .map(|i| {
             builder.wire(
                 format!("LH.{i}"),
@@ -176,11 +184,11 @@ pub fn make_int_db(rd: &Part) -> IntDb {
             )
         })
         .collect();
-    for i in 0..24 {
-        builder.conn_branch(lh[i], Dir::E, lh[(i + 1) % 24]);
+    for i in 0..ll_len {
+        builder.conn_branch(lh[i], Dir::E, lh[(i + 1) % ll_len]);
     }
 
-    let lv: Vec<_> = (0..24)
+    let lv: Vec<_> = (0..ll_len)
         .map(|i| {
             builder.wire(
                 format!("LV.{i}"),
@@ -189,8 +197,8 @@ pub fn make_int_db(rd: &Part) -> IntDb {
             )
         })
         .collect();
-    for i in 0..24 {
-        builder.conn_branch(lv[i], Dir::N, lv[(i + 23) % 24]);
+    for i in 0..ll_len {
+        builder.conn_branch(lv[i], Dir::N, lv[(i + ll_len - 1) % ll_len]);
     }
 
     // The set/reset inputs.
@@ -200,6 +208,7 @@ pub fn make_int_db(rd: &Part) -> IntDb {
             &[
                 format!("SR{i}"),
                 format!("IOIS_SR{i}"),
+                format!("IOIS_OSR{i}"),
                 format!("CNR_SR{i}"),
                 format!("BRAM_SR{i}"),
                 format!("MACC_SR{i}"),
@@ -225,7 +234,17 @@ pub fn make_int_db(rd: &Part) -> IntDb {
     }
 
     for i in 0..8 {
-        builder.mux_out(format!("IMUX.IOCLK{i}"), &[format!("IOIS_CLK{i}")]);
+        builder.mux_out(
+            format!("IMUX.IOCLK{i}"),
+            &[
+                format!("IOIS_CLK{i}"),
+                if i % 2 == 0 {
+                    format!("IOIS_ICLK{ii}", ii = i / 2)
+                } else {
+                    format!("IOIS_OCLK{ii}", ii = i / 2)
+                },
+            ],
+        );
     }
 
     // The clock enables.
@@ -235,6 +254,7 @@ pub fn make_int_db(rd: &Part) -> IntDb {
             &[
                 format!("CE_B{i}"),
                 format!("IOIS_CE_B{i}"),
+                format!("IOIS_OCE_B{i}"),
                 format!("CNR_CE_B{i}"),
                 format!("BRAM_CE_B{i}"),
                 format!("MACC_CE_B{i}"),
@@ -287,6 +307,42 @@ pub fn make_int_db(rd: &Part) -> IntDb {
                     (i >> 2 & 3) + 1,
                     i & 3
                 ),
+                // FPGACORE
+                [
+                    "IOIS_IREV0",
+                    "IOIS_IREV1",
+                    "IOIS_IREV2",
+                    "IOIS_IREV3",
+                    "IOIS_OREV0",
+                    "IOIS_OREV1",
+                    "IOIS_OREV2",
+                    "IOIS_OREV3",
+                    "IOIS_ICE_B0",
+                    "IOIS_ICE_B1",
+                    "IOIS_ICE_B2",
+                    "IOIS_ICE_B3",
+                    "IOIS_ISR0",
+                    "IOIS_ISR1",
+                    "IOIS_ISR2",
+                    "IOIS_ISR3",
+                    "",
+                    "",
+                    "",
+                    "",
+                    "",
+                    "",
+                    "",
+                    "",
+                    "IOIS_O0",
+                    "IOIS_O1",
+                    "IOIS_O2",
+                    "IOIS_O3",
+                    "",
+                    "",
+                    "",
+                    "",
+                ][i]
+                    .to_string(),
                 format!("CNR_DATA_IN{i}"),
                 [
                     "BRAM_DIA_B18",
@@ -453,6 +509,7 @@ pub fn make_int_db(rd: &Part) -> IntDb {
                     "IOIS_X0", "IOIS_X1", "IOIS_X2", "IOIS_X3", "IOIS_Y0", "IOIS_Y1", "IOIS_Y2",
                     "IOIS_Y3",
                 ][i],
+                ["", "", "", "", "IOIS_I0", "IOIS_I1", "IOIS_I2", "IOIS_I3"][i],
                 // In BRAM, used for low data outputs.
                 [
                     "BRAM_DOA0",
@@ -511,6 +568,10 @@ pub fn make_int_db(rd: &Part) -> IntDb {
                     "", "", "", "", "", "", "", "", "IOIS_XQ0", "IOIS_XQ1", "IOIS_XQ2", "IOIS_XQ3",
                     "IOIS_YQ0", "IOIS_YQ1", "IOIS_YQ2", "IOIS_YQ3",
                 ][i],
+                [
+                    "", "", "", "", "", "", "", "", "IOIS_IQ0", "IOIS_IQ1", "IOIS_IQ2", "IOIS_IQ3",
+                    "", "", "", "",
+                ][i],
                 // sigh. this does not appear to actually be true.
                 [
                     "",
@@ -837,6 +898,11 @@ pub fn make_int_db(rd: &Part) -> IntDb {
         builder.extract_node("BIBUFS", "INT.IOI.S3E", "INT.IOI", &bels_int);
         builder.extract_node("TIOIS", "INT.IOI.S3E", "INT.IOI", &bels_int);
         builder.extract_node("TIBUFS", "INT.IOI.S3E", "INT.IOI", &bels_int);
+    } else if rd.family == "fpgacore" {
+        builder.extract_node("LIOIS", "INT.IOI.FC", "INT.IOI.FC", &bels_int);
+        builder.extract_node("RIOIS", "INT.IOI.FC", "INT.IOI.FC", &bels_int);
+        builder.extract_node("BIOIS", "INT.IOI.FC", "INT.IOI.FC", &bels_int);
+        builder.extract_node("TIOIS", "INT.IOI.FC", "INT.IOI.FC", &bels_int);
     } else {
         // NOTE: could be unified by pulling extra muxes from CLB
         builder.extract_node("LIOIS", "INT.IOI.S3", "INT.IOI", &bels_int);
@@ -1032,6 +1098,33 @@ pub fn make_int_db(rd: &Part) -> IntDb {
         ] {
             builder.make_marker_bel(kind, kind, kind, num);
         }
+    } else if rd.family == "fpgacore" {
+        let bels_ioi = [
+            builder
+                .bel_indexed("IBUF0", "IBUF", 0)
+                .extra_wire_force("IBUF", "IOIS_IBUF0"),
+            builder
+                .bel_indexed("IBUF1", "IBUF", 1)
+                .extra_wire_force("IBUF", "IOIS_IBUF1"),
+            builder.bel_indexed("IBUF2", "IBUF", 2),
+            builder.bel_indexed("IBUF3", "IBUF", 3),
+            builder.bel_indexed("OBUF0", "OBUF", 0),
+            builder.bel_indexed("OBUF1", "OBUF", 1),
+            builder.bel_indexed("OBUF2", "OBUF", 2),
+            builder.bel_indexed("OBUF3", "OBUF", 3),
+        ];
+        builder.extract_node_bels("LIOIS", "IOI.FC", "IOI.FC.L", &bels_ioi);
+        builder.extract_node_bels("RIOIS", "IOI.FC", "IOI.FC.R", &bels_ioi);
+        builder.extract_node_bels("BIOIS", "IOI.FC", "IOI.FC.B", &bels_ioi);
+        builder.extract_node_bels("TIOIS", "IOI.FC", "IOI.FC.T", &bels_ioi);
+        for (kind, num) in [
+            ("IOBS.FC.B", 1),
+            ("IOBS.FC.T", 1),
+            ("IOBS.FC.L", 1),
+            ("IOBS.FC.R", 1),
+        ] {
+            builder.make_marker_bel(kind, kind, kind, num);
+        }
     } else if rd.family == "spartan3e" {
         let bels_ioi_tb = [
             builder
@@ -1218,17 +1311,19 @@ pub fn make_int_db(rd: &Part) -> IntDb {
             builder.make_marker_bel(kind, kind, kind, num);
         }
     }
-    let bels_randor_b = [builder
-        .bel_xy("RANDOR", "RANDOR", 0, 0)
-        .pins_name_only(&["CIN0", "CIN1", "CPREV", "O"])];
+    if rd.family != "fpgacore" {
+        let bels_randor_b = [builder
+            .bel_xy("RANDOR", "RANDOR", 0, 0)
+            .pins_name_only(&["CIN0", "CIN1", "CPREV", "O"])];
+        builder.extract_node_bels("BIOIS", "RANDOR", "RANDOR.B", &bels_randor_b);
+        builder.extract_node_bels("BIOIB", "RANDOR", "RANDOR.B", &bels_randor_b);
+        builder.extract_node_bels("BIBUFS", "RANDOR", "RANDOR.B", &bels_randor_b);
+    }
     let bels_randor_t = [builder
         .bel_xy("RANDOR", "RANDOR", 0, 0)
         .pins_name_only(&["CIN0", "CIN1"])
         .pin_name_only("CPREV", 1)
         .pin_name_only("O", 1)];
-    builder.extract_node_bels("BIOIS", "RANDOR", "RANDOR.B", &bels_randor_b);
-    builder.extract_node_bels("BIOIB", "RANDOR", "RANDOR.B", &bels_randor_b);
-    builder.extract_node_bels("BIBUFS", "RANDOR", "RANDOR.B", &bels_randor_b);
     builder.extract_node_bels("TIOIS", "RANDOR", "RANDOR.T", &bels_randor_t);
     builder.extract_node_bels("TIOIB", "RANDOR", "RANDOR.T", &bels_randor_t);
     builder.extract_node_bels("TIBUFS", "RANDOR", "RANDOR.T", &bels_randor_t);
@@ -1236,7 +1331,7 @@ pub fn make_int_db(rd: &Part) -> IntDb {
     if rd.family == "spartan3" {
         let bels_dcm = [builder.bel_xy("DCM", "DCM", 0, 0)];
         builder.extract_node_bels("BRAM_IOIS", "DCM.S3", "DCM.S3", &bels_dcm);
-    } else {
+    } else if rd.family != "fpgacore" {
         let bels_dcm = [
             builder.bel_xy("DCM", "DCM", 0, 0),
             builder
@@ -1343,74 +1438,96 @@ pub fn make_int_db(rd: &Part) -> IntDb {
                     .extra_int_out("O", &["UR_CARRY_IN"]),
             ],
         );
+    } else if rd.family == "fpgacore" {
+        builder.extract_node_bels("LL", "LL.FC", "LL.FC", &[]);
+        builder.extract_node_bels(
+            "LR",
+            "LR.FC",
+            "LR.FC",
+            &[
+                builder.bel_single("STARTUP", "STARTUP"),
+                builder.bel_single("CAPTURE", "CAPTURE"),
+                builder.bel_single("ICAP", "ICAP"),
+            ],
+        );
+        builder.extract_node_bels("UL", "UL.FC", "UL.FC", &[builder.bel_single("PMV", "PMV")]);
+        builder.extract_node_bels(
+            "UR",
+            "UR.FC",
+            "UR.FC",
+            &[
+                builder.bel_single("BSCAN", "BSCAN"),
+                builder
+                    .bel_virtual("RANDOR_OUT")
+                    .extra_int_out("O", &["UR_CARRY_IN"]),
+            ],
+        );
+    } else if rd.family == "spartan3e" {
+        builder.extract_node_bels("LL", "LL.S3E", "LL.S3E", &[]);
+        builder.extract_node_bels(
+            "LR",
+            "LR.S3E",
+            "LR.S3E",
+            &[
+                builder.bel_single("STARTUP", "STARTUP"),
+                builder.bel_single("CAPTURE", "CAPTURE"),
+                builder.bel_single("ICAP", "ICAP").pin_force_int(
+                    "I2",
+                    (NodeTileId::from_idx(0), lr_di2.unwrap()),
+                    "CNR_DATA_IN2",
+                ),
+            ],
+        );
+        builder.extract_node_bels(
+            "UL",
+            "UL.S3E",
+            "UL.S3E",
+            &[builder.bel_single("PMV", "PMV")],
+        );
+        builder.extract_node_bels(
+            "UR",
+            "UR.S3E",
+            "UR.S3E",
+            &[
+                builder.bel_single("BSCAN", "BSCAN"),
+                builder
+                    .bel_virtual("RANDOR_OUT")
+                    .extra_int_out("O", &["UR_CARRY_IN"]),
+            ],
+        );
     } else {
-        if rd.family == "spartan3e" {
-            builder.extract_node_bels("LL", "LL.S3E", "LL.S3E", &[]);
-            builder.extract_node_bels(
-                "LR",
-                "LR.S3E",
-                "LR.S3E",
-                &[
-                    builder.bel_single("STARTUP", "STARTUP"),
-                    builder.bel_single("CAPTURE", "CAPTURE"),
-                    builder.bel_single("ICAP", "ICAP").pin_force_int(
-                        "I2",
-                        (NodeTileId::from_idx(0), lr_di2.unwrap()),
-                        "CNR_DATA_IN2",
-                    ),
-                ],
-            );
-            builder.extract_node_bels(
-                "UL",
-                "UL.S3E",
-                "UL.S3E",
-                &[builder.bel_single("PMV", "PMV")],
-            );
-            builder.extract_node_bels(
-                "UR",
-                "UR.S3E",
-                "UR.S3E",
-                &[
-                    builder.bel_single("BSCAN", "BSCAN"),
-                    builder
-                        .bel_virtual("RANDOR_OUT")
-                        .extra_int_out("O", &["UR_CARRY_IN"]),
-                ],
-            );
-        } else {
-            builder.extract_node_bels("LL", "LL.S3A", "LL.S3A", &[]);
-            builder.extract_node_bels(
-                "LR",
-                "LR.S3A",
-                "LR.S3A",
-                &[
-                    builder.bel_single("STARTUP", "STARTUP"),
-                    builder.bel_single("CAPTURE", "CAPTURE"),
-                    builder.bel_single("ICAP", "ICAP"),
-                    builder.bel_single("SPI_ACCESS", "SPI_ACCESS"),
-                ],
-            );
-            builder.extract_node_bels(
-                "UL",
-                "UL.S3A",
-                "UL.S3A",
-                &[
-                    builder.bel_single("PMV", "PMV"),
-                    builder.bel_single("DNA_PORT", "DNA_PORT"),
-                ],
-            );
-            builder.extract_node_bels(
-                "UR",
-                "UR.S3A",
-                "UR.S3A",
-                &[
-                    builder.bel_single("BSCAN", "BSCAN"),
-                    builder
-                        .bel_virtual("RANDOR_OUT")
-                        .extra_int_out("O", &["UR_CARRY_IN"]),
-                ],
-            );
-        }
+        builder.extract_node_bels("LL", "LL.S3A", "LL.S3A", &[]);
+        builder.extract_node_bels(
+            "LR",
+            "LR.S3A",
+            "LR.S3A",
+            &[
+                builder.bel_single("STARTUP", "STARTUP"),
+                builder.bel_single("CAPTURE", "CAPTURE"),
+                builder.bel_single("ICAP", "ICAP"),
+                builder.bel_single("SPI_ACCESS", "SPI_ACCESS"),
+            ],
+        );
+        builder.extract_node_bels(
+            "UL",
+            "UL.S3A",
+            "UL.S3A",
+            &[
+                builder.bel_single("PMV", "PMV"),
+                builder.bel_single("DNA_PORT", "DNA_PORT"),
+            ],
+        );
+        builder.extract_node_bels(
+            "UR",
+            "UR.S3A",
+            "UR.S3A",
+            &[
+                builder.bel_single("BSCAN", "BSCAN"),
+                builder
+                    .bel_virtual("RANDOR_OUT")
+                    .extra_int_out("O", &["UR_CARRY_IN"]),
+            ],
+        );
     }
 
     for tkn in [
@@ -1753,7 +1870,14 @@ pub fn make_int_db(rd: &Part) -> IntDb {
 
     for tkn in ["CLKB", "CLKB_LL"] {
         for &xy in rd.tiles_by_kind_name(tkn) {
-            let xy_l = xy.delta(-1, if rd.family == "spartan3" { 0 } else { 1 });
+            let xy_l = xy.delta(
+                -1,
+                if rd.family == "spartan3" || rd.family == "fpgacore" {
+                    0
+                } else {
+                    1
+                },
+            );
             if rd.family == "spartan3" {
                 builder.extract_xnode(
                     "CLKB.S3",
@@ -1798,6 +1922,38 @@ pub fn make_int_db(rd: &Part) -> IntDb {
                     ],
                     &lh,
                 );
+            } else if rd.family == "fpgacore" {
+                builder.extract_xnode(
+                    "CLKB.FC",
+                    xy,
+                    &[],
+                    &[xy_l],
+                    "CLKB.FC",
+                    &[
+                        builder
+                            .bel_indexed("BUFG0", "BUFG", 0)
+                            .pin_name_only("I", 0)
+                            .extra_wire("CKI", &["CLKB_CKI0"])
+                            .extra_int_in("CLK", &["CLKB_GCLK0"]),
+                        builder
+                            .bel_indexed("BUFG1", "BUFG", 1)
+                            .pin_name_only("I", 0)
+                            .extra_wire("CKI", &["CLKB_CKI1"])
+                            .extra_int_in("CLK", &["CLKB_GCLK1"]),
+                        builder
+                            .bel_indexed("BUFG2", "BUFG", 2)
+                            .pin_name_only("I", 0)
+                            .extra_wire("CKI", &["CLKB_CKI2"])
+                            .extra_int_in("CLK", &["CLKB_GCLK2"]),
+                        builder
+                            .bel_indexed("BUFG3", "BUFG", 3)
+                            .pin_name_only("I", 0)
+                            .extra_wire("CKI", &["CLKB_CKI3"])
+                            .extra_int_in("CLK", &["CLKB_GCLK3"]),
+                        builder.bel_virtual("GLOBALSIG.B"),
+                    ],
+                    &lh,
+                );
             } else {
                 let kind = if rd.family == "spartan3e" {
                     "CLKB.S3E"
@@ -1969,6 +2125,38 @@ pub fn make_int_db(rd: &Part) -> IntDb {
                     ],
                     &lh,
                 );
+            } else if rd.family == "fpgacore" {
+                builder.extract_xnode(
+                    "CLKT.FC",
+                    xy,
+                    &[],
+                    &[xy_l],
+                    "CLKT.FC",
+                    &[
+                        builder
+                            .bel_indexed("BUFG0", "BUFG", 4)
+                            .pin_name_only("I", 0)
+                            .extra_wire("CKI", &["CLKT_CKI0"])
+                            .extra_int_in("CLK", &["CLKT_GCLK0"]),
+                        builder
+                            .bel_indexed("BUFG1", "BUFG", 5)
+                            .pin_name_only("I", 0)
+                            .extra_wire("CKI", &["CLKT_CKI1"])
+                            .extra_int_in("CLK", &["CLKT_GCLK1"]),
+                        builder
+                            .bel_indexed("BUFG2", "BUFG", 6)
+                            .pin_name_only("I", 0)
+                            .extra_wire("CKI", &["CLKT_CKI2"])
+                            .extra_int_in("CLK", &["CLKT_GCLK2"]),
+                        builder
+                            .bel_indexed("BUFG3", "BUFG", 7)
+                            .pin_name_only("I", 0)
+                            .extra_wire("CKI", &["CLKT_CKI3"])
+                            .extra_int_in("CLK", &["CLKT_GCLK3"]),
+                        builder.bel_virtual("GLOBALSIG.T"),
+                    ],
+                    &lh,
+                );
             } else {
                 let kind = if rd.family == "spartan3e" {
                     "CLKT.S3E"
@@ -2156,7 +2344,7 @@ pub fn make_int_db(rd: &Part) -> IntDb {
         }
     }
 
-    if rd.family != "spartan3" {
+    if rd.family != "spartan3" && rd.family != "fpgacore" {
         for tkn in ["CLKL", "CLKR"] {
             for &xy in rd.tiles_by_kind_name(tkn) {
                 let xy_o = xy.delta(if xy.x == 0 { 1 } else { -1 }, 0);
@@ -2367,7 +2555,7 @@ pub fn make_int_db(rd: &Part) -> IntDb {
                 builder.extract_intf_tile_multi("INTF.DSP", xy, &int_xy, "INTF.DSP", false);
             }
         }
-    } else {
+    } else if rd.family != "fpgacore" {
         let kind = match &*rd.family {
             "spartan3" => "BRAM.S3",
             "spartan3e" => "BRAM.S3E",
@@ -2502,7 +2690,7 @@ pub fn make_int_db(rd: &Part) -> IntDb {
         }
     }
 
-    if rd.family != "spartan3" {
+    if rd.family != "spartan3" && rd.family != "fpgacore" {
         let dummy_xy = Coord { x: 0, y: 0 };
         let bel_globalsig = builder.bel_virtual("GLOBALSIG");
         let mut bel = builder.bel_virtual("GCLKH");
diff --git a/prjcombine_virtex2_rdverify/src/clk.rs b/prjcombine_virtex2_rdverify/src/clk.rs
index 8856a124..cf169732 100644
--- a/prjcombine_virtex2_rdverify/src/clk.rs
+++ b/prjcombine_virtex2_rdverify/src/clk.rs
@@ -193,6 +193,38 @@ pub fn verify_bufgmux(edev: &ExpandedDevice<'_>, vrf: &mut Verifier, bel: &BelCo
     }
 }
 
+pub fn verify_bufg(edev: &ExpandedDevice<'_>, vrf: &mut Verifier, bel: &BelContext<'_>) {
+    vrf.verify_bel(bel, "BUFG", &[("I", SitePinDir::In)], &["CLK"]);
+    vrf.claim_node(&[bel.fwire("I")]);
+    vrf.claim_pip(bel.crd(), bel.wire("I"), bel.wire("CLK"));
+    let edge = if bel.row == edev.grid.row_bot() {
+        Dir::S
+    } else if bel.row == edev.grid.row_top() {
+        Dir::N
+    } else {
+        unreachable!()
+    };
+    let crd = edev.grid.get_clk_io(edge, bel.bid.to_idx()).unwrap();
+    let obel = vrf
+        .find_bel(
+            bel.die,
+            (crd.col, crd.row),
+            match crd.iob.to_idx() {
+                0 => "IBUF0",
+                1 => "IBUF1",
+                2 => "IBUF2",
+                3 => "IBUF3",
+                _ => unreachable!(),
+            },
+        )
+        .unwrap();
+    vrf.claim_node(&[bel.fwire("CKI"), obel.fwire("IBUF")]);
+    vrf.claim_pip(obel.crd(), obel.wire("IBUF"), obel.wire("I"));
+    vrf.claim_pip(bel.crd(), bel.wire("CLK"), bel.wire("CKI"));
+    // let obel = vrf.find_bel_sibling(bel, "VCC");
+    // vrf.claim_pip(bel.crd(), bel.wire_far("CLK"), obel.wire("VCCOUT"));
+}
+
 pub fn verify_gclkh(edev: &ExpandedDevice<'_>, vrf: &mut Verifier, bel: &BelContext<'_>) {
     for i in 0..8 {
         for bt in ["B", "T"] {
@@ -311,8 +343,13 @@ pub fn verify_clkc_s3(edev: &ExpandedDevice<'_>, vrf: &mut Verifier, bel: &BelCo
         } else {
             edev.grid.row_top()
         };
+        let bufg = if edev.grid.kind == GridKind::FpgaCore {
+            "BUFG"
+        } else {
+            "BUFGMUX"
+        };
         let obel = vrf
-            .find_bel(bel.die, (edev.grid.col_clk, srow), &format!("BUFGMUX{j}"))
+            .find_bel(bel.die, (edev.grid.col_clk, srow), &format!("{bufg}{j}"))
             .unwrap();
         vrf.verify_node(&[bel.fwire(&format!("IN_{bt}{j}")), obel.fwire_far("O")]);
     }
@@ -364,7 +401,7 @@ pub fn verify_gclkvm(edev: &ExpandedDevice<'_>, vrf: &mut Verifier, bel: &BelCon
                 bel.wire(&format!("OUT_{bt}{i}")),
                 bel.wire(&format!("IN_CORE{i}")),
             );
-            if edev.grid.kind != GridKind::Spartan3 {
+            if edev.grid.kind.is_spartan3ea() {
                 vrf.claim_pip(
                     bel.crd(),
                     bel.wire(&format!("OUT_{bt}{i}")),
@@ -379,7 +416,7 @@ pub fn verify_gclkvm(edev: &ExpandedDevice<'_>, vrf: &mut Verifier, bel: &BelCon
             bel.fwire(&format!("IN_CORE{i}")),
             obel.fwire(&format!("OUT{i}")),
         ]);
-        if edev.grid.kind != GridKind::Spartan3 {
+        if edev.grid.kind.is_spartan3ea() {
             let scol = if bel.col < edev.grid.col_clk {
                 edev.grid.col_left()
             } else {
diff --git a/prjcombine_virtex2_rdverify/src/lib.rs b/prjcombine_virtex2_rdverify/src/lib.rs
index fdde7eee..d56f693b 100644
--- a/prjcombine_virtex2_rdverify/src/lib.rs
+++ b/prjcombine_virtex2_rdverify/src/lib.rs
@@ -199,6 +199,8 @@ fn verify_bel(edev: &ExpandedDevice<'_>, vrf: &mut Verifier, bel: &BelContext<'_
 
         _ if bel.key.starts_with("IOI") => io::verify_ioi(edev, vrf, bel),
         _ if bel.key.starts_with("IOBS") => (),
+        _ if bel.key.starts_with("IBUF") => vrf.verify_bel(bel, "IBUF", &[], &[]),
+        _ if bel.key.starts_with("OBUF") => vrf.verify_bel(bel, "OBUF", &[], &[]),
         "CLK_P" | "CLK_N" => {
             vrf.verify_bel(bel, bel.key, &[("I", SitePinDir::Out)], &[]);
             vrf.claim_node(&[bel.fwire("I")]);
@@ -218,6 +220,7 @@ fn verify_bel(edev: &ExpandedDevice<'_>, vrf: &mut Verifier, bel: &BelContext<'_
 
         "BREFCLK" => clk::verify_brefclk(edev, vrf, bel),
         _ if bel.key.starts_with("BUFGMUX") => clk::verify_bufgmux(edev, vrf, bel),
+        _ if bel.key.starts_with("BUFG") => clk::verify_bufg(edev, vrf, bel),
         _ if bel.key.starts_with("GCLKH") => clk::verify_gclkh(edev, vrf, bel),
         "GCLKC" => clk::verify_gclkc(edev, vrf, bel),
         "CLKC" => {
diff --git a/prjcombine_virtex_bitstream/src/lib.rs b/prjcombine_virtex_bitstream/src/lib.rs
index 496086f0..3de41521 100644
--- a/prjcombine_virtex_bitstream/src/lib.rs
+++ b/prjcombine_virtex_bitstream/src/lib.rs
@@ -45,6 +45,7 @@ pub enum Reg {
     FakeIgnoreCrc,
     FakeEncrypted,
     FakeDoubleCclkFrequency,
+    FakeHasSwitch,
 }
 
 #[derive(Clone, Copy, PartialEq, Eq, Hash, PartialOrd, Ord, Debug)]
diff --git a/prjcombine_virtex_bitstream/src/parse.rs b/prjcombine_virtex_bitstream/src/parse.rs
index eae5711f..dca951d0 100644
--- a/prjcombine_virtex_bitstream/src/parse.rs
+++ b/prjcombine_virtex_bitstream/src/parse.rs
@@ -42,7 +42,10 @@ fn parse_xc5200_bitstream(bs: &mut Bitstream, data: &[u8]) {
     } else if bit_length == data.len() * 8 - 3 {
         bs.regs[Reg::FakeLcAlignmentDone] = Some(1);
     } else {
-        panic!("weird length {bit_length} [total {total}]", total = data.len() * 8);
+        panic!(
+            "weird length {bit_length} [total {total}]",
+            total = data.len() * 8
+        );
     }
     let mut pos = 6;
     let frame_len = bs.frame_len;
@@ -371,7 +374,13 @@ fn parse_virtex_bitstream(bs: &mut Bitstream, data: &[u8], key: &KeyData) {
         Some(Packet::Mask(val)) => val,
         p => panic!("expected mask got {p:?}"),
     };
-    assert_eq!(packets.next(), Some(Packet::CmdSwitch));
+    match packets.next() {
+        Some(Packet::CmdSwitch) => {
+            bs.regs[Reg::FakeHasSwitch] = Some(1);
+        }
+        Some(Packet::CmdNull) => (),
+        p => panic!("expected switch or null got {p:?}"),
+    }
 
     // main loop
     let mut fi = 0;
diff --git a/prjcombine_xc5200/src/expand.rs b/prjcombine_xc5200/src/expand.rs
index 6b266184..e833787c 100644
--- a/prjcombine_xc5200/src/expand.rs
+++ b/prjcombine_xc5200/src/expand.rs
@@ -1,6 +1,8 @@
 use prjcombine_int::db::IntDb;
 use prjcombine_int::grid::{DieId, ExpandedGrid};
-use prjcombine_virtex_bitstream::{BitstreamGeom, DeviceKind, DieBitstreamGeom, FrameAddr, FrameInfo};
+use prjcombine_virtex_bitstream::{
+    BitstreamGeom, DeviceKind, DieBitstreamGeom, FrameAddr, FrameInfo,
+};
 use unnamed_entity::{EntityId, EntityVec};
 
 use crate::expanded::ExpandedDevice;
diff --git a/prjcombine_xilinx_geom/src/bin/xgprint.rs b/prjcombine_xilinx_geom/src/bin/xgprint.rs
index 6abd4f67..0773df9c 100644
--- a/prjcombine_xilinx_geom/src/bin/xgprint.rs
+++ b/prjcombine_xilinx_geom/src/bin/xgprint.rs
@@ -1289,7 +1289,10 @@ mod ultrascale {
 }
 
 mod versal {
-    use prjcombine_versal::{bond::Bond, grid::{ColumnKind, Grid}};
+    use prjcombine_versal::{
+        bond::Bond,
+        grid::{ColumnKind, Grid},
+    };
     use unnamed_entity::EntityId;
 
     pub fn print_grid(grid: &Grid) {
diff --git a/prjcombine_xilinx_geom/src/lib.rs b/prjcombine_xilinx_geom/src/lib.rs
index 34027277..3b4704df 100644
--- a/prjcombine_xilinx_geom/src/lib.rs
+++ b/prjcombine_xilinx_geom/src/lib.rs
@@ -93,7 +93,7 @@ pub enum ExpandedBond<'a> {
 }
 
 impl Bond {
-    pub fn expand (&self) -> ExpandedBond {
+    pub fn expand(&self) -> ExpandedBond {
         match self {
             Bond::Xc4k(bond) => ExpandedBond::Xc4k(bond.expand()),
             Bond::Xc5200(bond) => ExpandedBond::Xc5200(bond.expand()),
@@ -212,6 +212,8 @@ impl GeomDb {
             Grid::Virtex2(grid) => {
                 let intdb = if grid.kind.is_virtex2() {
                     &self.ints["virtex2"]
+                } else if grid.kind == prjcombine_virtex2::grid::GridKind::FpgaCore {
+                    &self.ints["fpgacore"]
                 } else {
                     &self.ints["spartan3"]
                 };
diff --git a/prjcombine_xilinx_rd2geom/src/main.rs b/prjcombine_xilinx_rd2geom/src/main.rs
index 3da74bd9..957e1972 100644
--- a/prjcombine_xilinx_rd2geom/src/main.rs
+++ b/prjcombine_xilinx_rd2geom/src/main.rs
@@ -56,7 +56,7 @@ fn main() -> Result<(), Box<dyn Error>> {
                         "xc5200" => xc5200::ingest(&rd, verify),
                         "virtex" | "virtexe" => virtex::ingest(&rd, verify),
                         "virtex2" | "virtex2p" | "spartan3" | "spartan3e" | "spartan3a"
-                        | "spartan3adsp" => virtex2::ingest(&rd, verify),
+                        | "spartan3adsp" | "fpgacore" => virtex2::ingest(&rd, verify),
                         "spartan6" => spartan6::ingest(&rd, verify),
                         "virtex4" => virtex4::ingest(&rd, verify),
                         "virtex5" => virtex5::ingest(&rd, verify),