From fb02bece80d6f430a4a2c9a39caadb1b737897d7 Mon Sep 17 00:00:00 2001 From: valeros Date: Mon, 14 Sep 2020 18:16:18 +0300 Subject: [PATCH 1/4] Download OpenOCD by default Used by a custom target for uploading bitstream --- platform.json | 1 - 1 file changed, 1 deletion(-) diff --git a/platform.json b/platform.json index a112383..a2ac87c 100644 --- a/platform.json +++ b/platform.json @@ -45,7 +45,6 @@ "version": "0.0.0-alpha+sha.ca4b2392d8" }, "tool-openocd-riscv-chipsalliance": { - "optional": true, "type": "uploader", "owner": "platformio", "version": "~1.1000.0" From baa99fcb2a1e41e672e43b4c56fb669b3b2cbe57 Mon Sep 17 00:00:00 2001 From: valeros Date: Mon, 14 Sep 2020 18:27:24 +0300 Subject: [PATCH 2/4] Delete existing trace file before generating new one // Resolve #3 --- builder/main.py | 5 ++--- 1 file changed, 2 insertions(+), 3 deletions(-) diff --git a/builder/main.py b/builder/main.py index 9ef22b0..fbc0967 100644 --- a/builder/main.py +++ b/builder/main.py @@ -71,8 +71,7 @@ def generate_disassembly(target, source, env): def run_verilator(target, source, env): trace_file = os.path.join(env.subst("$BUILD_DIR"), "trace.vcd") if os.path.isfile(trace_file): - print("Trace file %s already exists" % trace_file) - return + os.remove(trace_file) cmd = [ os.path.join( @@ -85,7 +84,7 @@ def run_verilator(target, source, env): p = subprocess.Popen(cmd, cwd=env.subst("$BUILD_DIR")) - # Wait for sometime while data is being collected + # Wait for some time while data is being collected time.sleep(3) p.terminate() From 0440d2d3294a4d2e30c3bcf3d7373cc56ba6743f Mon Sep 17 00:00:00 2001 From: valeros Date: Thu, 1 Oct 2020 11:44:49 +0300 Subject: [PATCH 3/4] Set the default env name in examples to "rvfpga" --- examples/native-asm/platformio.ini | 2 +- examples/native-bare_c/platformio.ini | 4 ++-- examples/psp-hello-world/platformio.ini | 2 +- examples/rtosal-freertos/platformio.ini | 2 +- 4 files changed, 5 insertions(+), 5 deletions(-) diff --git a/examples/native-asm/platformio.ini b/examples/native-asm/platformio.ini index 69d2689..53020de 100644 --- a/examples/native-asm/platformio.ini +++ b/examples/native-asm/platformio.ini @@ -7,7 +7,7 @@ ; Please visit documentation for the other options and examples ; http://docs.platformio.org/page/projectconf.html -[env:swervolf_nexys] +[env:rvfpga] platform = chipsalliance board = swervolf_nexys board_build.ldscript = ld/link.ld diff --git a/examples/native-bare_c/platformio.ini b/examples/native-bare_c/platformio.ini index ae86713..54bad19 100644 --- a/examples/native-bare_c/platformio.ini +++ b/examples/native-bare_c/platformio.ini @@ -7,7 +7,7 @@ ; Please visit documentation for the other options and examples ; http://docs.platformio.org/page/projectconf.html -[env:swervolf_nexys] +[env:rvfpga] platform = chipsalliance board = swervolf_nexys board_build.ldscript = ld/link.ld @@ -17,7 +17,7 @@ board_build.ldscript = ld/link.ld ; debug_init_break = tbreak main ; Path to a bitstream used with "program_fpga" target -board_build.bitstream_file = swervolf_0.7.bit +; board_build.bitstream_file = swervolf_0.7.bit ; Path to Vivado project files for "generate_bitstream" target ; board_build.swervolf_run_tc = swervolf_0.6_run.tcl diff --git a/examples/psp-hello-world/platformio.ini b/examples/psp-hello-world/platformio.ini index f9d2284..a0bc46f 100644 --- a/examples/psp-hello-world/platformio.ini +++ b/examples/psp-hello-world/platformio.ini @@ -7,7 +7,7 @@ ; Please visit documentation for the other options and examples ; http://docs.platformio.org/page/projectconf.html -[env:swervolf_nexys] +[env:rvfpga] platform = chipsalliance board = swervolf_nexys framework = wd-riscv-sdk diff --git a/examples/rtosal-freertos/platformio.ini b/examples/rtosal-freertos/platformio.ini index 3a47cf5..e9e762d 100644 --- a/examples/rtosal-freertos/platformio.ini +++ b/examples/rtosal-freertos/platformio.ini @@ -7,7 +7,7 @@ ; Please visit documentation for the other options and examples ; http://docs.platformio.org/page/projectconf.html -[env:swervolf nexys] +[env:rvfpga] platform = chipsalliance board = swervolf_nexys framework = wd-riscv-sdk, freertos From f8b586d30821250e6610ac79ad9a6cb1186fc872 Mon Sep 17 00:00:00 2001 From: valeros Date: Thu, 1 Oct 2020 11:47:08 +0300 Subject: [PATCH 4/4] Bump version to 1.0.1 --- platform.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform.json b/platform.json index a2ac87c..b35fe18 100644 --- a/platform.json +++ b/platform.json @@ -17,7 +17,7 @@ "type": "git", "url": "https://github.com/platformio/platform-chipsalliance.git" }, - "version": "1.0.0", + "version": "1.0.1", "frameworks": { "wd-riscv-sdk": { "package": "framework-wd-riscv-sdk",