From fd7c51cf862049e6fe3a768447ceaacbef766b30 Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Tue, 10 Jul 2018 00:28:59 +0300 Subject: [PATCH 1/3] Add support for new Adafruit boards: ItsyBitsy M0, Feather M4 (SAMD51), ItsyBitsy M4, Metro M4, pIRkey // Resolve #32 --- boards/adafruit_circuitplayground_m0.json | 5 +- boards/adafruit_feather_m0.json | 3 +- boards/adafruit_feather_m0_express.json | 3 +- boards/adafruit_feather_m4.json | 58 + boards/adafruit_gemma_m0.json | 3 +- boards/adafruit_itsybitsy_m0.json | 50 + boards/adafruit_itsybitsy_m4.json | 59 + boards/adafruit_metro_m0.json | 3 +- boards/adafruit_metro_m4.json | 58 + boards/adafruit_pirkey.json | 50 + boards/adafruit_trinket_m0.json | 3 +- boards/mkr1000USB.json | 1 + boards/mkrfox1200.json | 1 + boards/mkrgsm1400.json | 1 + boards/mkrwan1300.json | 1 + boards/mkrzero.json | 1 + boards/mzeroUSB.json | 1 + boards/mzeroproUSB.json | 1 + boards/sparkfun_samd21_dev_usb.json | 1 + boards/sparkfun_samd21_mini_usb.json | 1 + boards/tian.json | 1 + boards/zeroUSB.json | 1 + builder/frameworks/arduino.py | 50 +- builder/main.py | 31 +- examples/arduino-blink/platformio.ini | 5 + examples/arduino-external-libs/platformio.ini | 5 + examples/arduino-internal-libs/platformio.ini | 13 +- misc/svd/ATSAMD51J19A.svd | 38760 ++++++++++++++++ platform.json | 2 +- platform.py | 13 +- 30 files changed, 39137 insertions(+), 48 deletions(-) create mode 100644 boards/adafruit_feather_m4.json create mode 100644 boards/adafruit_itsybitsy_m0.json create mode 100644 boards/adafruit_itsybitsy_m4.json create mode 100644 boards/adafruit_metro_m4.json create mode 100644 boards/adafruit_pirkey.json create mode 100644 misc/svd/ATSAMD51J19A.svd diff --git a/boards/adafruit_circuitplayground_m0.json b/boards/adafruit_circuitplayground_m0.json index 81a570e..5d9a0bb 100644 --- a/boards/adafruit_circuitplayground_m0.json +++ b/boards/adafruit_circuitplayground_m0.json @@ -1,8 +1,8 @@ { "build": { - "core": "samd", + "core": "adafruit", "cpu": "cortex-m0plus", - "extra_flags": "-D__SAMD21G18A__ -DCRYSTALLESS -DARDUINO_ARCH_SAMD -DARDUINO_SAMD_ZERO -DADAFRUIT_CIRCUITPLAYGROUND_M0 -DARDUINO_SAMD_CIRCUITPLAYGROUND_EXPRESS ", + "extra_flags": "-D__SAMD21G18A__ -DCRYSTALLESS -DARM_MATH_CM0PLUS -DARDUINO_ARCH_SAMD -DARDUINO_SAMD_ZERO -DADAFRUIT_CIRCUITPLAYGROUND_M0 -DARDUINO_SAMD_CIRCUITPLAYGROUND_EXPRESS", "f_cpu": "48000000L", "hwids": [ [ @@ -40,6 +40,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x2000", "use_1200bps_touch": true, "wait_for_upload_port": true }, diff --git a/boards/adafruit_feather_m0.json b/boards/adafruit_feather_m0.json index 628dac1..9404c15 100644 --- a/boards/adafruit_feather_m0.json +++ b/boards/adafruit_feather_m0.json @@ -2,7 +2,7 @@ "build": { "core": "adafruit", "cpu": "cortex-m0plus", - "extra_flags": "-DARDUINO_ARCH_SAMD -DARDUINO_SAMD_ZERO -DARDUINO_SAMD_FEATHER_M0 -D__SAMD21G18A__", + "extra_flags": "-DARDUINO_ARCH_SAMD -DARDUINO_SAMD_ZERO -DARDUINO_SAMD_FEATHER_M0 -DARM_MATH_CM0PLUS -D__SAMD21G18A__", "f_cpu": "48000000L", "hwids": [ [ @@ -41,6 +41,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x2000", "use_1200bps_touch": true, "wait_for_upload_port": true }, diff --git a/boards/adafruit_feather_m0_express.json b/boards/adafruit_feather_m0_express.json index 5c40314..4a6fc5d 100644 --- a/boards/adafruit_feather_m0_express.json +++ b/boards/adafruit_feather_m0_express.json @@ -2,7 +2,7 @@ "build": { "core": "adafruit", "cpu": "cortex-m0plus", - "extra_flags": "-DARDUINO_ARCH_SAMD -DARDUINO_SAMD_ZERO -DARDUINO_SAMD_FEATHER_M0 -DARDUINO_SAMD_FEATHER_M0_EXPRESS -D__SAMD21G18A__", + "extra_flags": "-DARDUINO_ARCH_SAMD -DARDUINO_SAMD_ZERO -DARDUINO_SAMD_FEATHER_M0 -DARDUINO_SAMD_FEATHER_M0_EXPRESS -DARM_MATH_CM0PLUS -D__SAMD21G18A__", "f_cpu": "48000000L", "hwids": [ [ @@ -41,6 +41,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x2000", "use_1200bps_touch": true, "wait_for_upload_port": true }, diff --git a/boards/adafruit_feather_m4.json b/boards/adafruit_feather_m4.json new file mode 100644 index 0000000..acdd73a --- /dev/null +++ b/boards/adafruit_feather_m4.json @@ -0,0 +1,58 @@ +{ + "build": { + "core": "adafruit", + "cpu": "cortex-m4", + "extra_flags": [ + "-DARDUINO_ARCH_SAMD", + "-DARDUINO_FEATHER_M4", + "-DADAFRUIT_FEATHER_M4_EXPRESS", + "-D__SAMD51J19A__", + "-D__SAMD51__", + "-D__FPU_PRESENT", + "-DARM_MATH_CM4" + ], + "f_cpu": "120000000L", + "hwids": [ + [ + "0x239A", + "0x8022" + ], + [ + "0x239A", + "0x0022" + ] + ], + "ldscript": "flash_with_bootloader.ld", + "mcu": "samd51j19a", + "system": "samd", + "usb_product": "Adafruit Feather M4", + "variant": "feather_m4" + }, + "debug": { + "openocd_chipname": "at91samd51j19", + "svd_path": "ATSAMD51J19A.svd" + }, + "frameworks": [ + "arduino" + ], + "name": "Adafruit Feather M4 (SAMD51)", + "upload": { + "disable_flushing": true, + "maximum_ram_size": 196608, + "maximum_size": 507904, + "native_usb": true, + "protocol": "sam-ba", + "protocols": [ + "sam-ba", + "blackmagic", + "jlink", + "atmel-ice" + ], + "require_upload_port": true, + "section_start": "0x4000", + "use_1200bps_touch": true, + "wait_for_upload_port": true + }, + "url": "https://www.adafruit.com/product/3857", + "vendor": "Adafruit" +} diff --git a/boards/adafruit_gemma_m0.json b/boards/adafruit_gemma_m0.json index 5f8e839..09152cf 100644 --- a/boards/adafruit_gemma_m0.json +++ b/boards/adafruit_gemma_m0.json @@ -2,7 +2,7 @@ "build": { "core": "adafruit", "cpu": "cortex-m0plus", - "extra_flags": "-DARDUINO_ARCH_SAMD -DARDUINO_GEMMA_M0 -DCRYSTALLESS -DADAFRUIT_GEMMA_M0 -D__SAMD21E18A__", + "extra_flags": "-DARDUINO_ARCH_SAMD -DARDUINO_GEMMA_M0 -DARM_MATH_CM0PLUS -DCRYSTALLESS -DADAFRUIT_GEMMA_M0 -D__SAMD21E18A__", "f_cpu": "48000000L", "hwids": [ [ @@ -41,6 +41,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x2000", "use_1200bps_touch": true, "wait_for_upload_port": true }, diff --git a/boards/adafruit_itsybitsy_m0.json b/boards/adafruit_itsybitsy_m0.json new file mode 100644 index 0000000..c38b585 --- /dev/null +++ b/boards/adafruit_itsybitsy_m0.json @@ -0,0 +1,50 @@ +{ + "build": { + "core": "adafruit", + "cpu": "cortex-m0plus", + "extra_flags": "-DARDUINO_ARCH_SAMD -DARDUINO_ITSYBITSY_M0 -DADAFRUIT_ITSYBITSY_M0 -DCRYSTALLESS -DARM_MATH_CM0PLUS -D__SAMD21G18A__", + "f_cpu": "48000000L", + "hwids": [ + [ + "0x239A", + "0x800F" + ], + [ + "0x239A", + "0x000F" + ] + ], + "ldscript": "flash_with_bootloader.ld", + "mcu": "samd21g18a", + "system": "samd", + "usb_product": "ItsyBitsy M0 Express", + "variant": "itsybitsy_m0" + }, + "debug": { + "openocd_chipname": "at91samd21g18", + "svd_path": "ATSAMD21G18A.svd" + }, + "frameworks": [ + "arduino" + ], + "name": "Adafruit ItsyBitsy M0", + "upload": { + "disable_flushing": true, + "maximum_ram_size": 32768, + "maximum_size": 262144, + "native_usb": true, + "protocol": "sam-ba", + "protocols": [ + "sam-ba", + "blackmagic", + "jlink", + "atmel-ice" + ], + "require_upload_port": true, + "section_start": "0x2000", + "use_1200bps_touch": true, + "wait_for_upload_port": true + }, + "url": "https://www.adafruit.com/product/3727", + "vendor": "Adafruit" +} diff --git a/boards/adafruit_itsybitsy_m4.json b/boards/adafruit_itsybitsy_m4.json new file mode 100644 index 0000000..8bb0f26 --- /dev/null +++ b/boards/adafruit_itsybitsy_m4.json @@ -0,0 +1,59 @@ +{ + "build": { + "core": "adafruit", + "cpu": "cortex-m4", + "extra_flags": [ + "-DARDUINO_ARCH_SAMD", + "-DARDUINO_ITSYBITSY_M4", + "-DADAFRUIT_ITSYBITSY_M4_EXPRESS", + "-D__SAMD51J19A__", + "-D__SAMD51__", + "-D__FPU_PRESENT", + "-DARM_MATH_CM4", + "-DCRYSTALLESS" + ], + "f_cpu": "120000000L", + "hwids": [ + [ + "0x239A", + "0x802B" + ], + [ + "0x239A", + "0x002B" + ] + ], + "ldscript": "flash_with_bootloader.ld", + "mcu": "samd51j19a", + "system": "samd", + "usb_product": "Adafruit ItsyBitsy M4", + "variant": "itsybitsy_m4" + }, + "debug": { + "openocd_chipname": "at91samd51j19", + "svd_path": "ATSAMD51J19A.svd" + }, + "frameworks": [ + "arduino" + ], + "name": "Adafruit ItsyBitsy M4 (SAMD51)", + "upload": { + "disable_flushing": true, + "maximum_ram_size": 196608, + "maximum_size": 507904, + "native_usb": true, + "protocol": "sam-ba", + "protocols": [ + "sam-ba", + "blackmagic", + "jlink", + "atmel-ice" + ], + "require_upload_port": true, + "section_start": "0x4000", + "use_1200bps_touch": true, + "wait_for_upload_port": true + }, + "url": "https://www.adafruit.com/product/3800", + "vendor": "Adafruit" +} diff --git a/boards/adafruit_metro_m0.json b/boards/adafruit_metro_m0.json index 4d5e288..78883ce 100644 --- a/boards/adafruit_metro_m0.json +++ b/boards/adafruit_metro_m0.json @@ -2,7 +2,7 @@ "build": { "core": "adafruit", "cpu": "cortex-m0plus", - "extra_flags": "-DARDUINO_ARCH_SAMD -DARDUINO_SAMD_ZERO -DDADAFRUIT_METRO_M0_EXPRESS -D__SAMD21G18A__", + "extra_flags": "-DARDUINO_ARCH_SAMD -DARDUINO_SAMD_ZERO -DDADAFRUIT_METRO_M0_EXPRESS -DARM_MATH_CM0PLUS -D__SAMD21G18A__", "f_cpu": "48000000L", "hwids": [ [ @@ -41,6 +41,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x2000", "use_1200bps_touch": true, "wait_for_upload_port": true }, diff --git a/boards/adafruit_metro_m4.json b/boards/adafruit_metro_m4.json new file mode 100644 index 0000000..d2ea9fd --- /dev/null +++ b/boards/adafruit_metro_m4.json @@ -0,0 +1,58 @@ +{ + "build": { + "core": "adafruit", + "cpu": "cortex-m4", + "extra_flags": [ + "-DARDUINO_ARCH_SAMD", + "-DARDUINO_METRO_M4", + "-DADAFRUIT_METRO_M4_EXPRESS", + "-D__SAMD51J19A__", + "-D__SAMD51__", + "-D__FPU_PRESENT", + "-DARM_MATH_CM4" + ], + "f_cpu": "120000000L", + "hwids": [ + [ + "0x239A", + "0x8020" + ], + [ + "0x239A", + "0x0020" + ] + ], + "ldscript": "flash_with_bootloader.ld", + "mcu": "samd51j19a", + "system": "samd", + "usb_product": "Adafruit Metro M4", + "variant": "metro_m4" + }, + "debug": { + "openocd_chipname": "at91samd51j19", + "svd_path": "ATSAMD51J19A.svd" + }, + "frameworks": [ + "arduino" + ], + "name": "Adafruit Metro M4 (SAMD51)", + "upload": { + "disable_flushing": true, + "maximum_ram_size": 196608, + "maximum_size": 507904, + "native_usb": true, + "protocol": "sam-ba", + "protocols": [ + "sam-ba", + "blackmagic", + "jlink", + "atmel-ice" + ], + "require_upload_port": true, + "section_start": "0x4000", + "use_1200bps_touch": true, + "wait_for_upload_port": true + }, + "url": "https://www.adafruit.com/product/3382", + "vendor": "Adafruit" +} diff --git a/boards/adafruit_pirkey.json b/boards/adafruit_pirkey.json new file mode 100644 index 0000000..cb3d3cb --- /dev/null +++ b/boards/adafruit_pirkey.json @@ -0,0 +1,50 @@ +{ + "build": { + "core": "adafruit", + "cpu": "cortex-m0plus", + "extra_flags": "-DARDUINO_ARCH_SAMD -DARDUINO_PIRKEY -DARM_MATH_CM0PLUS -DCRYSTALLESS -DADAFRUIT_PIRKEY -D__SAMD21E18A__", + "f_cpu": "48000000L", + "hwids": [ + [ + "0x239A", + "0x801E" + ], + [ + "0x239A", + "0x001E" + ] + ], + "ldscript": "flash_with_bootloader.ld", + "mcu": "samd21e18a", + "system": "samd", + "usb_product": "pIRKey", + "variant": "pirkey" + }, + "debug": { + "openocd_chipname": "at91samd21e18", + "svd_path": "ATSAMD21E18A.svd" + }, + "frameworks": [ + "arduino" + ], + "name": "Adafruit pIRkey", + "upload": { + "disable_flushing": true, + "maximum_ram_size": 32768, + "maximum_size": 262144, + "native_usb": true, + "protocol": "sam-ba", + "protocols": [ + "sam-ba", + "blackmagic", + "jlink", + "atmel-ice" + ], + "require_upload_port": true, + "section_start": "0x2000", + "use_1200bps_touch": true, + "wait_for_upload_port": true + }, + "url": "https://www.adafruit.com/product/3364", + "vendor": "Adafruit" +} diff --git a/boards/adafruit_trinket_m0.json b/boards/adafruit_trinket_m0.json index 8fa48ad..8a97d12 100644 --- a/boards/adafruit_trinket_m0.json +++ b/boards/adafruit_trinket_m0.json @@ -2,7 +2,7 @@ "build": { "core": "adafruit", "cpu": "cortex-m0plus", - "extra_flags": "-DARDUINO_ARCH_SAMD -DARDUINO_TRINKET_M0 -DCRYSTALLESS -DADAFRUIT_TRINKET_M0 -D__SAMD21E18A__", + "extra_flags": "-DARDUINO_ARCH_SAMD -DARDUINO_TRINKET_M0 -DCRYSTALLESS -DADAFRUIT_TRINKET_M0 -DARM_MATH_CM0PLUS -D__SAMD21E18A__", "f_cpu": "48000000L", "hwids": [ [ @@ -41,6 +41,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x2000", "use_1200bps_touch": true, "wait_for_upload_port": true }, diff --git a/boards/mkr1000USB.json b/boards/mkr1000USB.json index ce20c4d..8766661 100644 --- a/boards/mkr1000USB.json +++ b/boards/mkr1000USB.json @@ -51,6 +51,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x2000", "use_1200bps_touch": true, "wait_for_upload_port": true }, diff --git a/boards/mkrfox1200.json b/boards/mkrfox1200.json index 9fff622..7a2fc4b 100644 --- a/boards/mkrfox1200.json +++ b/boards/mkrfox1200.json @@ -40,6 +40,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x2000", "use_1200bps_touch": true, "wait_for_upload_port": true }, diff --git a/boards/mkrgsm1400.json b/boards/mkrgsm1400.json index eee3126..fa3fe90 100644 --- a/boards/mkrgsm1400.json +++ b/boards/mkrgsm1400.json @@ -40,6 +40,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x2000", "use_1200bps_touch": true, "wait_for_upload_port": true }, diff --git a/boards/mkrwan1300.json b/boards/mkrwan1300.json index 087f2dc..1dd2a20 100644 --- a/boards/mkrwan1300.json +++ b/boards/mkrwan1300.json @@ -40,6 +40,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x2000", "use_1200bps_touch": true, "wait_for_upload_port": true }, diff --git a/boards/mkrzero.json b/boards/mkrzero.json index 63745a9..5f0ad2e 100644 --- a/boards/mkrzero.json +++ b/boards/mkrzero.json @@ -40,6 +40,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x2000", "use_1200bps_touch": true, "wait_for_upload_port": true }, diff --git a/boards/mzeroUSB.json b/boards/mzeroUSB.json index 23c3671..6e8f785 100644 --- a/boards/mzeroUSB.json +++ b/boards/mzeroUSB.json @@ -39,6 +39,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x4000", "speed": 57600, "use_1200bps_touch": true, "wait_for_upload_port": true diff --git a/boards/mzeroproUSB.json b/boards/mzeroproUSB.json index 0a90c42..0bddc99 100644 --- a/boards/mzeroproUSB.json +++ b/boards/mzeroproUSB.json @@ -50,6 +50,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x4000", "speed": 57600, "use_1200bps_touch": true, "wait_for_upload_port": true diff --git a/boards/sparkfun_samd21_dev_usb.json b/boards/sparkfun_samd21_dev_usb.json index 5afafc1..a6c89b0 100644 --- a/boards/sparkfun_samd21_dev_usb.json +++ b/boards/sparkfun_samd21_dev_usb.json @@ -40,6 +40,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x2000", "use_1200bps_touch": true, "wait_for_upload_port": true }, diff --git a/boards/sparkfun_samd21_mini_usb.json b/boards/sparkfun_samd21_mini_usb.json index c2a9816..4b36627 100644 --- a/boards/sparkfun_samd21_mini_usb.json +++ b/boards/sparkfun_samd21_mini_usb.json @@ -40,6 +40,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x2000", "use_1200bps_touch": true, "wait_for_upload_port": true }, diff --git a/boards/tian.json b/boards/tian.json index 0abebc4..ddb3595 100644 --- a/boards/tian.json +++ b/boards/tian.json @@ -42,6 +42,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x4000", "speed": 57600, "use_1200bps_touch": true, "wait_for_upload_port": true diff --git a/boards/zeroUSB.json b/boards/zeroUSB.json index 1f9a17c..49c2493 100644 --- a/boards/zeroUSB.json +++ b/boards/zeroUSB.json @@ -47,6 +47,7 @@ "atmel-ice" ], "require_upload_port": true, + "section_start": "0x2000", "use_1200bps_touch": true, "wait_for_upload_port": true }, diff --git a/builder/frameworks/arduino.py b/builder/frameworks/arduino.py index 74cfe2b..345d79f 100644 --- a/builder/frameworks/arduino.py +++ b/builder/frameworks/arduino.py @@ -28,23 +28,24 @@ env = DefaultEnvironment() platform = env.PioPlatform() +board = env.BoardConfig() FRAMEWORK_DIR = platform.get_package_dir("framework-arduinosam") assert isdir(FRAMEWORK_DIR) -BUILD_CORE = env.BoardConfig().get("build.core", "") -BUILD_SYSTEM = env.BoardConfig().get("build.system", BUILD_CORE) +BUILD_CORE = board.get("build.core", "") +BUILD_SYSTEM = board.get("build.system", BUILD_CORE) SYSTEM_DIR = join(FRAMEWORK_DIR, "system", BUILD_SYSTEM) # USB flags ARDUINO_USBDEFINES = [("ARDUINO", 10805)] if "build.usb_product" in env.BoardConfig(): ARDUINO_USBDEFINES += [ - ("USB_VID", env.BoardConfig().get("build.hwids")[0][0]), - ("USB_PID", env.BoardConfig().get("build.hwids")[0][1]), + ("USB_VID", board.get("build.hwids")[0][0]), + ("USB_PID", board.get("build.hwids")[0][1]), ("USB_PRODUCT", '\\"%s\\"' % - env.BoardConfig().get("build.usb_product", "").replace('"', "")), + board.get("build.usb_product", "").replace('"', "")), ("USB_MANUFACTURER", '\\"%s\\"' % - env.BoardConfig().get("vendor", "").replace('"', "")) + board.get("vendor", "").replace('"', "")) ] @@ -57,7 +58,7 @@ LIBPATH=[ join(FRAMEWORK_DIR, "variants", - env.BoardConfig().get("build.variant"), "linker_scripts", "gcc") + board.get("build.variant"), "linker_scripts", "gcc") ] ) @@ -71,11 +72,26 @@ LIBPATH=[ join(SYSTEM_DIR, "CMSIS", "CMSIS", "Lib", "GCC"), join(FRAMEWORK_DIR, "variants", - env.BoardConfig().get("build.variant")) - ], - - LIBS=["arm_cortexM0l_math"] + board.get("build.variant")) + ] ) + if board.get("build.cpu") == "cortex-m4": + env.Prepend( + CCFLAGS=[ + "-mfloat-abi=hard", + "-mfpu=fpv4-sp-d16" + ], + LINKFLAGS=[ + "-mfloat-abi=hard", + "-mfpu=fpv4-sp-d16" + ], + LIBS=["arm_cortexM4lf_math"] + ) + else: + env.Prepend( + LIBS=["arm_cortexM0l_math"] + ) + elif BUILD_SYSTEM == "sam": env.Append( CPPDEFINES=[ @@ -89,8 +105,7 @@ ], LIBPATH=[ - join(FRAMEWORK_DIR, "variants", - env.BoardConfig().get("build.variant")) + join(FRAMEWORK_DIR, "variants", board.get("build.variant")) ], LINKFLAGS=[ @@ -100,7 +115,7 @@ "-u", "_getpid" ], - LIBS=["sam_sam3x8e_gcc_rel"] + LIBS=["sam_sam3x8e_gcc_rel", "gcc"] ) @@ -123,14 +138,11 @@ if "build.variant" in env.BoardConfig(): env.Append( - CPPPATH=[ - join(FRAMEWORK_DIR, "variants", - env.BoardConfig().get("build.variant")) - ] + CPPPATH=[join(FRAMEWORK_DIR, "variants", board.get("build.variant"))] ) libs.append(env.BuildLibrary( join("$BUILD_DIR", "FrameworkArduinoVariant"), - join(FRAMEWORK_DIR, "variants", env.BoardConfig().get("build.variant")) + join(FRAMEWORK_DIR, "variants", board.get("build.variant")) )) libs.append(env.BuildLibrary( diff --git a/builder/main.py b/builder/main.py index 76898ac..daad650 100644 --- a/builder/main.py +++ b/builder/main.py @@ -47,8 +47,9 @@ def BeforeUpload(target, source, env): # pylint: disable=W0613,W0621 env = DefaultEnvironment() platform = env.PioPlatform() +board = env.BoardConfig() upload_protocol = env.subst("$UPLOAD_PROTOCOL") -build_mcu = env.get("BOARD_MCU", env.BoardConfig().get("build.mcu", "")) +build_mcu = env.get("BOARD_MCU", board.get("build.mcu", "")) env.Replace( AR="arm-none-eabi-ar", @@ -74,7 +75,7 @@ def BeforeUpload(target, source, env): # pylint: disable=W0613,W0621 "-fdata-sections", "-Wall", "-mthumb", - "-mcpu=%s" % env.BoardConfig().get("build.cpu"), + "-mcpu=%s" % board.get("build.cpu"), "-nostdlib", "--param", "max-inline-insns-single=500" ], @@ -94,7 +95,8 @@ def BeforeUpload(target, source, env): # pylint: disable=W0613,W0621 LINKFLAGS=[ "-Os", "-mthumb", - "-mcpu=%s" % env.BoardConfig().get("build.cpu"), + "-mcpu=%s" % board.get("build.cpu"), + "-Wl,--cref", "-Wl,--gc-sections", "-Wl,--check-sections", "-Wl,--unresolved-symbols=report-all", @@ -102,7 +104,7 @@ def BeforeUpload(target, source, env): # pylint: disable=W0613,W0621 "-Wl,--warn-section-align" ], - LIBS=["c", "gcc", "m"], + LIBS=["m"], SIZEPROGREGEXP=r"^(?:\.text|\.data|\.rodata|\.text.align|\.ARM.exidx)\s+(\d+).*", SIZEDATAREGEXP=r"^(?:\.data|\.bss|\.noinit)\s+(\d+).*", @@ -186,7 +188,7 @@ def BeforeUpload(target, source, env): # pylint: disable=W0613,W0621 # Target: Upload by default .bin file # -debug_tools = env.BoardConfig().get("debug.tools", {}) +debug_tools = board.get("debug.tools", {}) upload_actions = [] if upload_protocol.startswith("blackmagic"): @@ -218,17 +220,24 @@ def BeforeUpload(target, source, env): # pylint: disable=W0613,W0621 "--erase", "--write", "--verify", - "--reset", - "-U", - "true" if env.BoardConfig().get( - "upload.native_usb", False) else "false" + "--reset" ], UPLOADCMD="$UPLOADER $UPLOADERFLAGS $SOURCES" ) + if board.get("build.core") == "adafruit": + env.Append( + UPLOADERFLAGS=["-U", "--offset", + board.get("upload.section_start")]) + else: + env.Append(UPLOADERFLAGS=[ + "-U", "true" + if env.BoardConfig().get("upload.native_usb", False) else "false" + ]) if "sam3x8e" in build_mcu: env.Append(UPLOADERFLAGS=["--boot"]) if int(ARGUMENTS.get("PIOVERBOSE", 0)): env.Prepend(UPLOADERFLAGS=["--info", "--debug"]) + upload_actions = [ env.VerboseAction(BeforeUpload, "Looking for upload port..."), env.VerboseAction("$UPLOADCMD", "Uploading $SOURCE") @@ -263,8 +272,8 @@ def BeforeUpload(target, source, env): # pylint: disable=W0613,W0621 "arguments", []) + [ "-c", "program {{$SOURCE}} verify reset %s; shutdown" % - env.BoardConfig().get("upload.section_start", "") - ], + board.get("upload.section_start", "") + ], UPLOADCMD="$UPLOADER $UPLOADERFLAGS" ) env['UPLOADERFLAGS'] = [ diff --git a/examples/arduino-blink/platformio.ini b/examples/arduino-blink/platformio.ini index 4dbe70b..6c952df 100644 --- a/examples/arduino-blink/platformio.ini +++ b/examples/arduino-blink/platformio.ini @@ -17,6 +17,11 @@ platform = atmelsam framework = arduino board = adafruit_feather_m0 +[env:adafruit_metro_m4] +platform = atmelsam +framework = arduino +board = adafruit_metro_m4 + [env:due] platform = atmelsam framework = arduino diff --git a/examples/arduino-external-libs/platformio.ini b/examples/arduino-external-libs/platformio.ini index d9abed1..4601064 100644 --- a/examples/arduino-external-libs/platformio.ini +++ b/examples/arduino-external-libs/platformio.ini @@ -17,6 +17,11 @@ platform = atmelsam framework = arduino board = adafruit_feather_m0 +[env:adafruit_metro_m4] +platform = atmelsam +framework = arduino +board = adafruit_metro_m4 + [env:due] platform = atmelsam framework = arduino diff --git a/examples/arduino-internal-libs/platformio.ini b/examples/arduino-internal-libs/platformio.ini index 63c0354..07ccf8e 100644 --- a/examples/arduino-internal-libs/platformio.ini +++ b/examples/arduino-internal-libs/platformio.ini @@ -7,16 +7,21 @@ ; Please visit documentation for the other options and examples ; http://docs.platformio.org/page/projectconf.html -; [env:adafruit_gemma_m0] -; platform = atmelsam -; framework = arduino -; board = adafruit_gemma_m0 +[env:adafruit_itsybitsy_m0] +platform = atmelsam +framework = arduino +board = adafruit_itsybitsy_m0 [env:adafruit_feather_m0] platform = atmelsam framework = arduino board = adafruit_feather_m0 +[env:adafruit_metro_m4] +platform = atmelsam +framework = arduino +board = adafruit_metro_m4 + [env:due] platform = atmelsam framework = arduino diff --git a/misc/svd/ATSAMD51J19A.svd b/misc/svd/ATSAMD51J19A.svd new file mode 100644 index 0000000..ff7c7fd --- /dev/null +++ b/misc/svd/ATSAMD51J19A.svd @@ -0,0 +1,38760 @@ + + + Atmel Corporation + ATMEL + ATSAMD51J19A + SAMD51 + A + Atmel ATSAMD51J19A device: Cortex-M4 Microcontroller with 512KB Flash, 192KB SRAM, 64-pin package (refer to http://www.atmel.com/devices/SAMD51J19A.aspx for more) + + ============================================================================\n + Atmel Microcontroller Software Support\n + ============================================================================\n + Copyright (c) 2017 Atmel Corporation,\n + a wholly owned subsidiary of Microchip Technology Inc.\n +\n + Licensed under the Apache License, Version 2.0 (the "License");\n + you may not use this file except in compliance with the License.\n + You may obtain a copy of the Licence at\n +\n + http://www.apache.org/licenses/LICENSE-2.0\n +\n + Unless required by applicable law or agreed to in writing, software\n + distributed under the License is distributed on an "AS IS" BASIS,\n + WITHOUT WARRANTIES OR CONDITIONS OF ANY KIND, either express or implied.\n + See the License for the specific language governing permissions and\n + limitations under the License.\n + ============================================================================ + + + CM4 + r0p1 + little + true + true + 3 + false + + system_samd51 + 8 + 32 + 32 + read-write + 0x00000000 + 0xFFFFFFFF + + + AC + 1.0.0 + Analog Comparators + AC + AC_ + 0x42002000 + + 0 + 0x40 + registers + + + AC_INTREQ + 122 + + + + CTRLA + Control A + 0x00 + 8 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B + 0x01 + 8 + write-only + + + START0 + Comparator 0 Start Comparison + 0 + 1 + + + START1 + Comparator 1 Start Comparison + 1 + 1 + + + + + EVCTRL + Event Control + 0x02 + 16 + + + COMPEO0 + Comparator 0 Event Output Enable + 0 + 1 + + + COMPEO1 + Comparator 1 Event Output Enable + 1 + 1 + + + WINEO0 + Window 0 Event Output Enable + 4 + 1 + + + COMPEI0 + Comparator 0 Event Input Enable + 8 + 1 + + + COMPEI1 + Comparator 1 Event Input Enable + 9 + 1 + + + INVEI0 + Comparator 0 Input Event Invert Enable + 12 + 1 + + + INVEI1 + Comparator 1 Input Event Invert Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x04 + 8 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x05 + 8 + + + COMP0 + Comparator 0 Interrupt Enable + 0 + 1 + + + COMP1 + Comparator 1 Interrupt Enable + 1 + 1 + + + WIN0 + Window 0 Interrupt Enable + 4 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x06 + 8 + + + COMP0 + Comparator 0 + 0 + 1 + + + COMP1 + Comparator 1 + 1 + 1 + + + WIN0 + Window 0 + 4 + 1 + + + + + STATUSA + Status A + 0x07 + 8 + read-only + + + STATE0 + Comparator 0 Current State + 0 + 1 + read-only + + + STATE1 + Comparator 1 Current State + 1 + 1 + read-only + + + WSTATE0 + Window 0 Current State + 4 + 2 + read-only + + WSTATE0Select + + ABOVE + Signal is above window + 0x0 + + + INSIDE + Signal is inside window + 0x1 + + + BELOW + Signal is below window + 0x2 + + + + + + + STATUSB + Status B + 0x08 + 8 + read-only + + + READY0 + Comparator 0 Ready + 0 + 1 + read-only + + + READY1 + Comparator 1 Ready + 1 + 1 + read-only + + + + + DBGCTRL + Debug Control + 0x09 + 8 + + + DBGRUN + Debug Run + 0 + 1 + + + + + WINCTRL + Window Control + 0x0A + 8 + + + WEN0 + Window 0 Mode Enable + 0 + 1 + + + WINTSEL0 + Window 0 Interrupt Selection + 1 + 2 + + WINTSEL0Select + + ABOVE + Interrupt on signal above window + 0x0 + + + INSIDE + Interrupt on signal inside window + 0x1 + + + BELOW + Interrupt on signal below window + 0x2 + + + OUTSIDE + Interrupt on signal outside window + 0x3 + + + + + + + 2 + 0x1 + SCALER%s + Scaler n + 0x0C + 8 + + + VALUE + Scaler Value + 0 + 6 + + + + + 2 + 0x4 + COMPCTRL%s + Comparator Control n + 0x10 + 32 + + + ENABLE + Enable + 1 + 1 + + + SINGLE + Single-Shot Mode + 2 + 1 + + + INTSEL + Interrupt Selection + 3 + 2 + + INTSELSelect + + TOGGLE + Interrupt on comparator output toggle + 0x0 + + + RISING + Interrupt on comparator output rising + 0x1 + + + FALLING + Interrupt on comparator output falling + 0x2 + + + EOC + Interrupt on end of comparison (single-shot mode only) + 0x3 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + MUXNEG + Negative Input Mux Selection + 8 + 3 + + MUXNEGSelect + + PIN0 + I/O pin 0 + 0x0 + + + PIN1 + I/O pin 1 + 0x1 + + + PIN2 + I/O pin 2 + 0x2 + + + PIN3 + I/O pin 3 + 0x3 + + + GND + Ground + 0x4 + + + VSCALE + VDD scaler + 0x5 + + + BANDGAP + Internal bandgap voltage + 0x6 + + + DAC + DAC output + 0x7 + + + + + MUXPOS + Positive Input Mux Selection + 12 + 3 + + MUXPOSSelect + + PIN0 + I/O pin 0 + 0x0 + + + PIN1 + I/O pin 1 + 0x1 + + + PIN2 + I/O pin 2 + 0x2 + + + PIN3 + I/O pin 3 + 0x3 + + + VSCALE + VDD Scaler + 0x4 + + + + + SWAP + Swap Inputs and Invert + 15 + 1 + + + SPEED + Speed Selection + 16 + 2 + + SPEEDSelect + + HIGH + High speed + 0x3 + + + + + HYSTEN + Hysteresis Enable + 19 + 1 + + + HYST + Hysteresis Level + 20 + 2 + + HYSTSelect + + HYST50 + 50mV + 0x0 + + + HYST100 + 100mV + 0x1 + + + HYST150 + 150mV + 0x2 + + + + + FLEN + Filter Length + 24 + 3 + + FLENSelect + + OFF + No filtering + 0x0 + + + MAJ3 + 3-bit majority function (2 of 3) + 0x1 + + + MAJ5 + 5-bit majority function (3 of 5) + 0x2 + + + + + OUT + Output + 28 + 2 + + OUTSelect + + OFF + The output of COMPn is not routed to the COMPn I/O port + 0x0 + + + ASYNC + The asynchronous output of COMPn is routed to the COMPn I/O port + 0x1 + + + SYNC + The synchronous output (including filtering) of COMPn is routed to the COMPn I/O port + 0x2 + + + + + + + SYNCBUSY + Synchronization Busy + 0x20 + 32 + read-only + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + read-only + + + ENABLE + Enable Synchronization Busy + 1 + 1 + read-only + + + WINCTRL + WINCTRL Synchronization Busy + 2 + 1 + read-only + + + COMPCTRL0 + COMPCTRL 0 Synchronization Busy + 3 + 1 + read-only + + + COMPCTRL1 + COMPCTRL 1 Synchronization Busy + 4 + 1 + read-only + + + + + CALIB + Calibration + 0x24 + 16 + 0x0101 + + + BIAS0 + COMP0/1 Bias Scaling + 0 + 2 + + + + + + + ADC0 + 1.0.0 + Analog Digital Converter 0 + ADC + ADC_ + 0x43001C00 + + 0 + 0x80 + registers + + + ADC0_INTREQ_0 + 118 + + + ADC0_INTREQ_1 + 119 + + + + CTRLA + Control A + 0x00 + 16 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + DUALSEL + Dual Mode Trigger Selection + 3 + 2 + + DUALSELSelect + + BOTH + Start event or software trigger will start a conversion on both ADCs + 0x0 + + + INTERLEAVE + START event or software trigger will alternatingly start a conversion on ADC0 and ADC1 + 0x1 + + + + + SLAVEEN + Slave Enable + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + PRESCALER + Prescaler Configuration + 8 + 3 + + PRESCALERSelect + + DIV2 + Peripheral clock divided by 2 + 0x0 + + + DIV4 + Peripheral clock divided by 4 + 0x1 + + + DIV8 + Peripheral clock divided by 8 + 0x2 + + + DIV16 + Peripheral clock divided by 16 + 0x3 + + + DIV32 + Peripheral clock divided by 32 + 0x4 + + + DIV64 + Peripheral clock divided by 64 + 0x5 + + + DIV128 + Peripheral clock divided by 128 + 0x6 + + + DIV256 + Peripheral clock divided by 256 + 0x7 + + + + + R2R + Rail to Rail Operation Enable + 15 + 1 + + + + + EVCTRL + Event Control + 0x02 + 8 + + + FLUSHEI + Flush Event Input Enable + 0 + 1 + + + STARTEI + Start Conversion Event Input Enable + 1 + 1 + + + FLUSHINV + Flush Event Invert Enable + 2 + 1 + + + STARTINV + Start Conversion Event Invert Enable + 3 + 1 + + + RESRDYEO + Result Ready Event Out + 4 + 1 + + + WINMONEO + Window Monitor Event Out + 5 + 1 + + + + + DBGCTRL + Debug Control + 0x03 + 8 + + + DBGRUN + Debug Run + 0 + 1 + + + + + INPUTCTRL + Input Control + 0x04 + 16 + + + MUXPOS + Positive Mux Input Selection + 0 + 5 + + MUXPOSSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + AIN6 + ADC AIN6 Pin + 0x6 + + + AIN7 + ADC AIN7 Pin + 0x7 + + + AIN8 + ADC AIN8 Pin + 0x8 + + + AIN9 + ADC AIN9 Pin + 0x9 + + + AIN10 + ADC AIN10 Pin + 0xa + + + AIN11 + ADC AIN11 Pin + 0xb + + + AIN12 + ADC AIN12 Pin + 0xc + + + AIN13 + ADC AIN13 Pin + 0xd + + + AIN14 + ADC AIN14 Pin + 0xe + + + AIN15 + ADC AIN15 Pin + 0xf + + + AIN16 + ADC AIN16 Pin + 0x10 + + + AIN17 + ADC AIN17 Pin + 0x11 + + + AIN18 + ADC AIN18 Pin + 0x12 + + + AIN19 + ADC AIN19 Pin + 0x13 + + + AIN20 + ADC AIN20 Pin + 0x14 + + + AIN21 + ADC AIN21 Pin + 0x15 + + + AIN22 + ADC AIN22 Pin + 0x16 + + + AIN23 + ADC AIN23 Pin + 0x17 + + + SCALEDCOREVCC + 1/4 Scaled Core Supply + 0x18 + + + SCALEDVBAT + 1/4 Scaled VBAT Supply + 0x19 + + + SCALEDIOVCC + 1/4 Scaled I/O Supply + 0x1a + + + BANDGAP + Bandgap Voltage + 0x1b + + + PTAT + Temperature Sensor + 0x1c + + + CTAT + Temperature Sensor + 0x1d + + + DAC + DAC Output + 0x1e + + + PTC + PTC output (only on ADC0) + 0x1f + + + + + DIFFMODE + Differential Mode + 7 + 1 + + + MUXNEG + Negative Mux Input Selection + 8 + 5 + + MUXNEGSelect + + AIN0 + ADC AIN0 Pin + 0x0 + + + AIN1 + ADC AIN1 Pin + 0x1 + + + AIN2 + ADC AIN2 Pin + 0x2 + + + AIN3 + ADC AIN3 Pin + 0x3 + + + AIN4 + ADC AIN4 Pin + 0x4 + + + AIN5 + ADC AIN5 Pin + 0x5 + + + AIN6 + ADC AIN6 Pin + 0x6 + + + AIN7 + ADC AIN7 Pin + 0x7 + + + GND + Internal Ground + 0x18 + + + + + DSEQSTOP + Stop DMA Sequencing + 15 + 1 + + + + + CTRLB + Control B + 0x06 + 16 + + + LEFTADJ + Left-Adjusted Result + 0 + 1 + + + FREERUN + Free Running Mode + 1 + 1 + + + CORREN + Digital Correction Logic Enable + 2 + 1 + + + RESSEL + Conversion Result Resolution + 3 + 2 + + RESSELSelect + + 12BIT + 12-bit result + 0x0 + + + 16BIT + For averaging mode output + 0x1 + + + 10BIT + 10-bit result + 0x2 + + + 8BIT + 8-bit result + 0x3 + + + + + WINMODE + Window Monitor Mode + 8 + 3 + + WINMODESelect + + DISABLE + No window mode (default) + 0x0 + + + MODE1 + RESULT > WINLT + 0x1 + + + MODE2 + RESULT < WINUT + 0x2 + + + MODE3 + WINLT < RESULT < WINUT + 0x3 + + + MODE4 + !(WINLT < RESULT < WINUT) + 0x4 + + + + + WINSS + Window Single Sample + 11 + 1 + + + + + REFCTRL + Reference Control + 0x08 + 8 + + + REFSEL + Reference Selection + 0 + 4 + + REFSELSelect + + INTREF + Internal Bandgap Reference + 0x0 + + + INTVCC0 + 1/2 VDDANA + 0x2 + + + INTVCC1 + VDDANA + 0x3 + + + AREFA + External Reference + 0x4 + + + AREFB + External Reference + 0x5 + + + AREFC + External Reference (only on ADC1) + 0x6 + + + + + REFCOMP + Reference Buffer Offset Compensation Enable + 7 + 1 + + + + + AVGCTRL + Average Control + 0x0A + 8 + + + SAMPLENUM + Number of Samples to be Collected + 0 + 4 + + SAMPLENUMSelect + + 1 + 1 sample + 0x0 + + + 2 + 2 samples + 0x1 + + + 4 + 4 samples + 0x2 + + + 8 + 8 samples + 0x3 + + + 16 + 16 samples + 0x4 + + + 32 + 32 samples + 0x5 + + + 64 + 64 samples + 0x6 + + + 128 + 128 samples + 0x7 + + + 256 + 256 samples + 0x8 + + + 512 + 512 samples + 0x9 + + + 1024 + 1024 samples + 0xa + + + + + ADJRES + Adjusting Result / Division Coefficient + 4 + 3 + + + + + SAMPCTRL + Sample Time Control + 0x0B + 8 + + + SAMPLEN + Sampling Time Length + 0 + 6 + + + OFFCOMP + Comparator Offset Compensation Enable + 7 + 1 + + + + + WINLT + Window Monitor Lower Threshold + 0x0C + 16 + + + WINLT + Window Lower Threshold + 0 + 16 + + + + + WINUT + Window Monitor Upper Threshold + 0x0E + 16 + + + WINUT + Window Upper Threshold + 0 + 16 + + + + + GAINCORR + Gain Correction + 0x10 + 16 + + + GAINCORR + Gain Correction Value + 0 + 12 + + + + + OFFSETCORR + Offset Correction + 0x12 + 16 + + + OFFSETCORR + Offset Correction Value + 0 + 12 + + + + + SWTRIG + Software Trigger + 0x14 + 8 + + + FLUSH + ADC Conversion Flush + 0 + 1 + + + START + Start ADC Conversion + 1 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x2C + 8 + + + RESRDY + Result Ready Interrupt Disable + 0 + 1 + + + OVERRUN + Overrun Interrupt Disable + 1 + 1 + + + WINMON + Window Monitor Interrupt Disable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x2D + 8 + + + RESRDY + Result Ready Interrupt Enable + 0 + 1 + + + OVERRUN + Overrun Interrupt Enable + 1 + 1 + + + WINMON + Window Monitor Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2E + 8 + + + RESRDY + Result Ready Interrupt Flag + 0 + 1 + + + OVERRUN + Overrun Interrupt Flag + 1 + 1 + + + WINMON + Window Monitor Interrupt Flag + 2 + 1 + + + + + STATUS + Status + 0x2F + 8 + read-only + + + ADCBUSY + ADC Busy Status + 0 + 1 + read-only + + + WCC + Window Comparator Counter + 2 + 6 + read-only + + + + + SYNCBUSY + Synchronization Busy + 0x30 + 32 + read-only + + + SWRST + SWRST Synchronization Busy + 0 + 1 + read-only + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + read-only + + + INPUTCTRL + Input Control Synchronization Busy + 2 + 1 + read-only + + + CTRLB + Control B Synchronization Busy + 3 + 1 + read-only + + + REFCTRL + Reference Control Synchronization Busy + 4 + 1 + read-only + + + AVGCTRL + Average Control Synchronization Busy + 5 + 1 + read-only + + + SAMPCTRL + Sampling Time Control Synchronization Busy + 6 + 1 + read-only + + + WINLT + Window Monitor Lower Threshold Synchronization Busy + 7 + 1 + read-only + + + WINUT + Window Monitor Upper Threshold Synchronization Busy + 8 + 1 + read-only + + + GAINCORR + Gain Correction Synchronization Busy + 9 + 1 + read-only + + + OFFSETCORR + Offset Correction Synchronization Busy + 10 + 1 + read-only + + + SWTRIG + Software Trigger Synchronization Busy + 11 + 1 + read-only + + + + + DSEQDATA + DMA Sequencial Data + 0x34 + 32 + write-only + + + DATA + DMA Sequential Data + 0 + 32 + write-only + + + + + DSEQCTRL + DMA Sequential Control + 0x38 + 32 + + + INPUTCTRL + Input Control + 0 + 1 + + + CTRLB + Control B + 1 + 1 + + + REFCTRL + Reference Control + 2 + 1 + + + AVGCTRL + Average Control + 3 + 1 + + + SAMPCTRL + Sampling Time Control + 4 + 1 + + + WINLT + Window Monitor Lower Threshold + 5 + 1 + + + WINUT + Window Monitor Upper Threshold + 6 + 1 + + + GAINCORR + Gain Correction + 7 + 1 + + + OFFSETCORR + Offset Correction + 8 + 1 + + + AUTOSTART + ADC Auto-Start Conversion + 31 + 1 + + + + + DSEQSTAT + DMA Sequencial Status + 0x3C + 32 + read-only + + + INPUTCTRL + Input Control + 0 + 1 + read-only + + + CTRLB + Control B + 1 + 1 + read-only + + + REFCTRL + Reference Control + 2 + 1 + read-only + + + AVGCTRL + Average Control + 3 + 1 + read-only + + + SAMPCTRL + Sampling Time Control + 4 + 1 + read-only + + + WINLT + Window Monitor Lower Threshold + 5 + 1 + read-only + + + WINUT + Window Monitor Upper Threshold + 6 + 1 + read-only + + + GAINCORR + Gain Correction + 7 + 1 + read-only + + + OFFSETCORR + Offset Correction + 8 + 1 + read-only + + + BUSY + DMA Sequencing Busy + 31 + 1 + read-only + + + + + RESULT + Result Conversion Value + 0x40 + 16 + read-only + + + RESULT + Result Conversion Value + 0 + 16 + read-only + + + + + RESS + Last Sample Result + 0x44 + 16 + read-only + + + RESS + Last ADC conversion result + 0 + 16 + read-only + + + + + CALIB + Calibration + 0x48 + 16 + + + BIASCOMP + Bias Comparator Scaling + 0 + 3 + + + BIASR2R + Bias R2R Ampli scaling + 4 + 3 + + + BIASREFBUF + Bias Reference Buffer Scaling + 8 + 3 + + + + + + + ADC1 + Analog Digital Converter 1 + 0x43002000 + + ADC1_INTREQ_0 + 120 + + + ADC1_INTREQ_1 + 121 + + + + AES + 2.2.0 + Advanced Encryption Standard + AES + AES_ + 0x42002400 + + 0 + 0x100 + registers + + + AES_INTREQ + 130 + + + + CTRLA + Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + AESMODE + AES Modes of operation + 2 + 3 + + AESMODESelect + + ECB + Electronic code book mode + 0x0 + + + CBC + Cipher block chaining mode + 0x1 + + + OFB + Output feedback mode + 0x2 + + + CFB + Cipher feedback mode + 0x3 + + + COUNTER + Counter mode + 0x4 + + + CCM + CCM mode + 0x5 + + + GCM + Galois counter mode + 0x6 + + + + + CFBS + Cipher Feedback Block Size + 5 + 3 + + CFBSSelect + + 128BIT + 128-bit Input data block for Encryption/Decryption in Cipher Feedback mode + 0x0 + + + 64BIT + 64-bit Input data block for Encryption/Decryption in Cipher Feedback mode + 0x1 + + + 32BIT + 32-bit Input data block for Encryption/Decryption in Cipher Feedback mode + 0x2 + + + 16BIT + 16-bit Input data block for Encryption/Decryption in Cipher Feedback mode + 0x3 + + + 8BIT + 8-bit Input data block for Encryption/Decryption in Cipher Feedback mode + 0x4 + + + + + KEYSIZE + Encryption Key Size + 8 + 2 + + KEYSIZESelect + + 128BIT + 128-bit Key for Encryption / Decryption + 0x0 + + + 192BIT + 192-bit Key for Encryption / Decryption + 0x1 + + + 256BIT + 256-bit Key for Encryption / Decryption + 0x2 + + + + + CIPHER + Cipher Mode + 10 + 1 + + CIPHERSelect + + DEC + Decryption + 0x0 + + + ENC + Encryption + 0x1 + + + + + STARTMODE + Start Mode Select + 11 + 1 + + STARTMODESelect + + MANUAL + Start Encryption / Decryption in Manual mode + 0x0 + + + AUTO + Start Encryption / Decryption in Auto mode + 0x1 + + + + + LOD + Last Output Data Mode + 12 + 1 + + LODSelect + + NONE + No effect + 0x0 + + + LAST + Start encryption in Last Output Data mode + 0x1 + + + + + KEYGEN + Last Key Generation + 13 + 1 + + KEYGENSelect + + NONE + No effect + 0x0 + + + LAST + Start Computation of the last NK words of the expanded key + 0x1 + + + + + XORKEY + XOR Key Operation + 14 + 1 + + XORKEYSelect + + NONE + No effect + 0x0 + + + XOR + The user keyword gets XORed with the previous keyword register content. + 0x1 + + + + + CTYPE + Counter Measure Type + 16 + 4 + + + + + CTRLB + Control B + 0x04 + 8 + + + START + Start Encryption/Decryption + 0 + 1 + + + NEWMSG + New message + 1 + 1 + + + EOM + End of message + 2 + 1 + + + GFMUL + GF Multiplication + 3 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x05 + 8 + + + ENCCMP + Encryption Complete Interrupt Enable + 0 + 1 + + + GFMCMP + GF Multiplication Complete Interrupt Enable + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x06 + 8 + + + ENCCMP + Encryption Complete Interrupt Enable + 0 + 1 + + + GFMCMP + GF Multiplication Complete Interrupt Enable + 1 + 1 + + + + + INTFLAG + Interrupt Flag Status + 0x07 + 8 + + + ENCCMP + Encryption Complete + 0 + 1 + + + GFMCMP + GF Multiplication Complete + 1 + 1 + + + + + DATABUFPTR + Data buffer pointer + 0x08 + 8 + + + INDATAPTR + Input Data Pointer + 0 + 2 + + + + + DBGCTRL + Debug control + 0x09 + 8 + + + DBGRUN + Debug Run + 0 + 1 + + + + + 8 + 0x4 + KEYWORD%s + Keyword n + 0x0C + 32 + write-only + + + INDATA + Indata + 0x38 + 32 + + + 4 + 0x4 + INTVECTV%s + Initialisation Vector n + 0x3C + 32 + write-only + + + 4 + 0x4 + HASHKEY%s + Hash key n + 0x5C + 32 + + + 4 + 0x4 + GHASH%s + Galois Hash n + 0x6C + 32 + + + CIPLEN + Cipher Length + 0x80 + 32 + + + RANDSEED + Random Seed + 0x84 + 32 + + + + + CCL + 1.1.0 + Configurable Custom Logic + CCL + CCL_ + 0x42003800 + + 0 + 0x40 + registers + + + + CTRL + Control + 0x0 + 8 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + + + 2 + 0x1 + SEQCTRL%s + SEQ Control x + 0x4 + 8 + + + SEQSEL + Sequential Selection + 0 + 4 + + SEQSELSelect + + DISABLE + Sequential logic is disabled + 0x0 + + + DFF + D flip flop + 0x1 + + + JK + JK flip flop + 0x2 + + + LATCH + D latch + 0x3 + + + RS + RS latch + 0x4 + + + + + + + 4 + 0x4 + LUTCTRL%s + LUT Control x + 0x8 + 32 + + + ENABLE + LUT Enable + 1 + 1 + + + FILTSEL + Filter Selection + 4 + 2 + + FILTSELSelect + + DISABLE + Filter disabled + 0x0 + + + SYNCH + Synchronizer enabled + 0x1 + + + FILTER + Filter enabled + 0x2 + + + + + EDGESEL + Edge Selection + 7 + 1 + + + INSEL0 + Input Selection 0 + 8 + 4 + + INSEL0Select + + MASK + Masked input + 0x0 + + + FEEDBACK + Feedback input source + 0x1 + + + LINK + Linked LUT input source + 0x2 + + + EVENT + Event input source + 0x3 + + + IO + I/O pin input source + 0x4 + + + AC + AC input source + 0x5 + + + TC + TC input source + 0x6 + + + ALTTC + Alternate TC input source + 0x7 + + + TCC + TCC input source + 0x8 + + + SERCOM + SERCOM input source + 0x9 + + + + + INSEL1 + Input Selection 1 + 12 + 4 + + INSEL1Select + + MASK + Masked input + 0x0 + + + FEEDBACK + Feedback input source + 0x1 + + + LINK + Linked LUT input source + 0x2 + + + EVENT + Event input source + 0x3 + + + IO + I/O pin input source + 0x4 + + + AC + AC input source + 0x5 + + + TC + TC input source + 0x6 + + + ALTTC + Alternate TC input source + 0x7 + + + TCC + TCC input source + 0x8 + + + SERCOM + SERCOM input source + 0x9 + + + + + INSEL2 + Input Selection 2 + 16 + 4 + + INSEL2Select + + MASK + Masked input + 0x0 + + + FEEDBACK + Feedback input source + 0x1 + + + LINK + Linked LUT input source + 0x2 + + + EVENT + Event input source + 0x3 + + + IO + I/O pin input source + 0x4 + + + AC + AC input source + 0x5 + + + TC + TC input source + 0x6 + + + ALTTC + Alternate TC input source + 0x7 + + + TCC + TCC input source + 0x8 + + + SERCOM + SERCOM input source + 0x9 + + + + + INVEI + Inverted Event Input Enable + 20 + 1 + + + LUTEI + LUT Event Input Enable + 21 + 1 + + + LUTEO + LUT Event Output Enable + 22 + 1 + + + TRUTH + Truth Value + 24 + 8 + + + + + + + CMCC + 6.0.0 + Cortex M Cache Controller + CMCC + CMCC_ + 0x41006000 + + 0 + 0x40 + registers + + + + TYPE + Cache Type Register + 0x00 + 32 + read-only + 0x000012D2 + + + GCLK + dynamic Clock Gating supported + 1 + 1 + + + RRP + Round Robin Policy supported + 4 + 1 + + + WAYNUM + Number of Way + 5 + 2 + + WAYNUMSelect + + DMAPPED + Direct Mapped Cache + 0x0 + + + ARCH2WAY + 2-WAY set associative + 0x1 + + + ARCH4WAY + 4-WAY set associative + 0x2 + + + + + LCKDOWN + Lock Down supported + 7 + 1 + + + CSIZE + Cache Size + 8 + 3 + + CSIZESelect + + CSIZE_1KB + Cache Size is 1 KB + 0x0 + + + CSIZE_2KB + Cache Size is 2 KB + 0x1 + + + CSIZE_4KB + Cache Size is 4 KB + 0x2 + + + CSIZE_8KB + Cache Size is 8 KB + 0x3 + + + CSIZE_16KB + Cache Size is 16 KB + 0x4 + + + CSIZE_32KB + Cache Size is 32 KB + 0x5 + + + CSIZE_64KB + Cache Size is 64 KB + 0x6 + + + + + CLSIZE + Cache Line Size + 11 + 3 + + CLSIZESelect + + CLSIZE_4B + Cache Line Size is 4 bytes + 0x0 + + + CLSIZE_8B + Cache Line Size is 8 bytes + 0x1 + + + CLSIZE_16B + Cache Line Size is 16 bytes + 0x2 + + + CLSIZE_32B + Cache Line Size is 32 bytes + 0x3 + + + CLSIZE_64B + Cache Line Size is 64 bytes + 0x4 + + + CLSIZE_128B + Cache Line Size is 128 bytes + 0x5 + + + + + + + CFG + Cache Configuration Register + 0x04 + 32 + 0x00000020 + + + ICDIS + Instruction Cache Disable + 1 + 1 + + + DCDIS + Data Cache Disable + 2 + 1 + + + CSIZESW + Cache size configured by software + 4 + 3 + + CSIZESWSelect + + CONF_CSIZE_1KB + the Cache Size is configured to 1KB + 0x0 + + + CONF_CSIZE_2KB + the Cache Size is configured to 2KB + 0x1 + + + CONF_CSIZE_4KB + the Cache Size is configured to 4KB + 0x2 + + + CONF_CSIZE_8KB + the Cache Size is configured to 8KB + 0x3 + + + CONF_CSIZE_16KB + the Cache Size is configured to 16KB + 0x4 + + + CONF_CSIZE_32KB + the Cache Size is configured to 32KB + 0x5 + + + CONF_CSIZE_64KB + the Cache Size is configured to 64KB + 0x6 + + + + + + + CTRL + Cache Control Register + 0x08 + 32 + write-only + + + CEN + Cache Controller Enable + 0 + 1 + + + + + SR + Cache Status Register + 0x0C + 32 + read-only + + + CSTS + Cache Controller Status + 0 + 1 + + + + + LCKWAY + Cache Lock per Way Register + 0x10 + 32 + + + LCKWAY + Lockdown way Register + 0 + 4 + + + + + MAINT0 + Cache Maintenance Register 0 + 0x20 + 32 + write-only + + + INVALL + Cache Controller invalidate All + 0 + 1 + + + + + MAINT1 + Cache Maintenance Register 1 + 0x24 + 32 + write-only + + + INDEX + Invalidate Index + 4 + 8 + + + WAY + Invalidate Way + 28 + 4 + + WAYSelect + + WAY0 + Way 0 is selection for index invalidation + 0x0 + + + WAY1 + Way 1 is selection for index invalidation + 0x1 + + + WAY2 + Way 2 is selection for index invalidation + 0x2 + + + WAY3 + Way 3 is selection for index invalidation + 0x3 + + + + + + + MCFG + Cache Monitor Configuration Register + 0x28 + 32 + + + MODE + Cache Controller Monitor Counter Mode + 0 + 2 + + MODESelect + + CYCLE_COUNT + cycle counter + 0x0 + + + IHIT_COUNT + instruction hit counter + 0x1 + + + DHIT_COUNT + data hit counter + 0x2 + + + + + + + MEN + Cache Monitor Enable Register + 0x2C + 32 + + + MENABLE + Cache Controller Monitor Enable + 0 + 1 + + + + + MCTRL + Cache Monitor Control Register + 0x30 + 32 + write-only + + + SWRST + Cache Controller Software Reset + 0 + 1 + + + + + MSR + Cache Monitor Status Register + 0x34 + 32 + read-only + + + EVENT_CNT + Monitor Event Counter + 0 + 32 + + + + + + + DAC + 1.0.0 + Digital-to-Analog Converter + DAC + DAC_ + 0x43002400 + + 0 + 0x20 + registers + + + DAC_INTREQ_0 + 123 + + + DAC_INTREQ_1 + 124 + + + DAC_INTREQ_2 + 125 + + + DAC_INTREQ_3 + 126 + + + DAC_INTREQ_4 + 127 + + + + CTRLA + Control A + 0x00 + 8 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable DAC Controller + 1 + 1 + + + + + CTRLB + Control B + 0x01 + 8 + 0x02 + + + DIFF + Differential mode enable + 0 + 1 + + + REFSEL + Reference Selection for DAC0/1 + 1 + 2 + + REFSELSelect + + VREFPU + External reference unbuffered + 0x0 + + + VDDANA + Analog supply + 0x1 + + + VREFPB + External reference buffered + 0x2 + + + INTREF + Internal bandgap reference + 0x3 + + + + + + + EVCTRL + Event Control + 0x02 + 8 + + + STARTEI0 + Start Conversion Event Input DAC 0 + 0 + 1 + + + STARTEI1 + Start Conversion Event Input DAC 1 + 1 + 1 + + + EMPTYEO0 + Data Buffer Empty Event Output DAC 0 + 2 + 1 + + + EMPTYEO1 + Data Buffer Empty Event Output DAC 1 + 3 + 1 + + + INVEI0 + Enable Invertion of DAC 0 input event + 4 + 1 + + + INVEI1 + Enable Invertion of DAC 1 input event + 5 + 1 + + + RESRDYEO0 + Result Ready Event Output 0 + 6 + 1 + + + RESRDYEO1 + Result Ready Event Output 1 + 7 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x04 + 8 + + + UNDERRUN0 + Underrun 0 Interrupt Enable + 0 + 1 + + + UNDERRUN1 + Underrun 1 Interrupt Enable + 1 + 1 + + + EMPTY0 + Data Buffer 0 Empty Interrupt Enable + 2 + 1 + + + EMPTY1 + Data Buffer 1 Empty Interrupt Enable + 3 + 1 + + + RESRDY0 + Result 0 Ready Interrupt Enable + 4 + 1 + + + RESRDY1 + Result 1 Ready Interrupt Enable + 5 + 1 + + + OVERRUN0 + Overrun 0 Interrupt Enable + 6 + 1 + + + OVERRUN1 + Overrun 1 Interrupt Enable + 7 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x05 + 8 + + + UNDERRUN0 + Underrun 0 Interrupt Enable + 0 + 1 + + + UNDERRUN1 + Underrun 1 Interrupt Enable + 1 + 1 + + + EMPTY0 + Data Buffer 0 Empty Interrupt Enable + 2 + 1 + + + EMPTY1 + Data Buffer 1 Empty Interrupt Enable + 3 + 1 + + + RESRDY0 + Result 0 Ready Interrupt Enable + 4 + 1 + + + RESRDY1 + Result 1 Ready Interrupt Enable + 5 + 1 + + + OVERRUN0 + Overrun 0 Interrupt Enable + 6 + 1 + + + OVERRUN1 + Overrun 1 Interrupt Enable + 7 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x06 + 8 + + + UNDERRUN0 + Result 0 Underrun + 0 + 1 + + + UNDERRUN1 + Result 1 Underrun + 1 + 1 + + + EMPTY0 + Data Buffer 0 Empty + 2 + 1 + + + EMPTY1 + Data Buffer 1 Empty + 3 + 1 + + + RESRDY0 + Result 0 Ready + 4 + 1 + + + RESRDY1 + Result 1 Ready + 5 + 1 + + + OVERRUN0 + Result 0 Overrun + 6 + 1 + + + OVERRUN1 + Result 1 Overrun + 7 + 1 + + + + + STATUS + Status + 0x07 + 8 + read-only + + + READY0 + DAC 0 Startup Ready + 0 + 1 + read-only + + + READY1 + DAC 1 Startup Ready + 1 + 1 + read-only + + + EOC0 + DAC 0 End of Conversion + 2 + 1 + read-only + + + EOC1 + DAC 1 End of Conversion + 3 + 1 + read-only + + + + + SYNCBUSY + Synchronization Busy + 0x08 + 32 + read-only + + + SWRST + Software Reset + 0 + 1 + read-only + + + ENABLE + DAC Enable Status + 1 + 1 + read-only + + + DATA0 + Data DAC 0 + 2 + 1 + read-only + + + DATA1 + Data DAC 1 + 3 + 1 + read-only + + + DATABUF0 + Data Buffer DAC 0 + 4 + 1 + read-only + + + DATABUF1 + Data Buffer DAC 1 + 5 + 1 + read-only + + + + + 2 + 0x2 + DACCTRL%s + DAC n Control + 0x0C + 16 + + + LEFTADJ + Left Adjusted Data + 0 + 1 + + + ENABLE + Enable DAC0 + 1 + 1 + + + CCTRL + Current Control + 2 + 2 + + CCTRLSelect + + CC100K + GCLK_DAC <= 1.2MHz (100kSPS) + 0x0 + + + CC1M + 1.2MHz < GCLK_DAC <= 6MHz (500kSPS) + 0x1 + + + CC12M + 6MHz < GCLK_DAC <= 12MHz (1MSPS) + 0x2 + + + + + FEXT + Standalone Filter + 5 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + DITHER + Dithering Mode + 7 + 1 + + + REFRESH + Refresh period + 8 + 4 + + + OSR + Sampling Rate + 13 + 3 + + + + + 2 + 0x2 + DATA%s + DAC n Data + 0x10 + 16 + write-only + + + DATA + DAC0 Data + 0 + 16 + write-only + + + + + 2 + 0x2 + DATABUF%s + DAC n Data Buffer + 0x14 + 16 + write-only + + + DATABUF + DAC0 Data Buffer + 0 + 16 + write-only + + + + + DBGCTRL + Debug Control + 0x18 + 8 + + + DBGRUN + Debug Run + 0 + 1 + + + + + 2 + 0x2 + RESULT%s + Filter Result + 0x1C + 16 + read-only + + + RESULT + Filter Result + 0 + 16 + read-only + + + + + + + DMAC + 1.0.0 + Direct Memory Access Controller + DMAC + DMAC_ + 0x4100A000 + + 0 + 0x400 + registers + + + DMAC_INTREQ_0 + 31 + + + DMAC_INTREQ_1 + 32 + + + DMAC_INTREQ_2 + 33 + + + DMAC_INTREQ_3 + 34 + + + DMAC_INTREQ_4 + 35 + + + + CTRL + Control + 0x00 + 16 + + + SWRST + Software Reset + 0 + 1 + + + DMAENABLE + DMA Enable + 1 + 1 + + + LVLEN0 + Priority Level 0 Enable + 8 + 1 + + + LVLEN1 + Priority Level 1 Enable + 9 + 1 + + + LVLEN2 + Priority Level 2 Enable + 10 + 1 + + + LVLEN3 + Priority Level 3 Enable + 11 + 1 + + + + + CRCCTRL + CRC Control + 0x02 + 16 + + + CRCBEATSIZE + CRC Beat Size + 0 + 2 + + CRCBEATSIZESelect + + BYTE + 8-bit bus transfer + 0x0 + + + HWORD + 16-bit bus transfer + 0x1 + + + WORD + 32-bit bus transfer + 0x2 + + + + + CRCPOLY + CRC Polynomial Type + 2 + 2 + + CRCPOLYSelect + + CRC16 + CRC-16 (CRC-CCITT) + 0x0 + + + CRC32 + CRC32 (IEEE 802.3) + 0x1 + + + + + CRCSRC + CRC Input Source + 8 + 6 + + CRCSRCSelect + + DISABLE + CRC Disabled + 0x0 + + + IO + I/O interface + 0x1 + + + + + CRCMODE + CRC Operating Mode + 14 + 2 + + CRCMODESelect + + DEFAULT + Default operating mode + 0x0 + + + CRCMON + Memory CRC monitor operating mode + 0x2 + + + CRCGEN + Memory CRC generation operating mode + 0x3 + + + + + + + CRCDATAIN + CRC Data Input + 0x04 + 32 + + + CRCDATAIN + CRC Data Input + 0 + 32 + + + + + CRCCHKSUM + CRC Checksum + 0x08 + 32 + + + CRCCHKSUM + CRC Checksum + 0 + 32 + + + + + CRCSTATUS + CRC Status + 0x0C + 8 + + + CRCBUSY + CRC Module Busy + 0 + 1 + + + CRCZERO + CRC Zero + 1 + 1 + read-only + + + CRCERR + CRC Error + 2 + 1 + read-only + + + + + DBGCTRL + Debug Control + 0x0D + 8 + + + DBGRUN + Debug Run + 0 + 1 + + + + + SWTRIGCTRL + Software Trigger Control + 0x10 + 32 + + + SWTRIG0 + Channel 0 Software Trigger + 0 + 1 + + + SWTRIG1 + Channel 1 Software Trigger + 1 + 1 + + + SWTRIG2 + Channel 2 Software Trigger + 2 + 1 + + + SWTRIG3 + Channel 3 Software Trigger + 3 + 1 + + + SWTRIG4 + Channel 4 Software Trigger + 4 + 1 + + + SWTRIG5 + Channel 5 Software Trigger + 5 + 1 + + + SWTRIG6 + Channel 6 Software Trigger + 6 + 1 + + + SWTRIG7 + Channel 7 Software Trigger + 7 + 1 + + + SWTRIG8 + Channel 8 Software Trigger + 8 + 1 + + + SWTRIG9 + Channel 9 Software Trigger + 9 + 1 + + + SWTRIG10 + Channel 10 Software Trigger + 10 + 1 + + + SWTRIG11 + Channel 11 Software Trigger + 11 + 1 + + + SWTRIG12 + Channel 12 Software Trigger + 12 + 1 + + + SWTRIG13 + Channel 13 Software Trigger + 13 + 1 + + + SWTRIG14 + Channel 14 Software Trigger + 14 + 1 + + + SWTRIG15 + Channel 15 Software Trigger + 15 + 1 + + + SWTRIG16 + Channel 16 Software Trigger + 16 + 1 + + + SWTRIG17 + Channel 17 Software Trigger + 17 + 1 + + + SWTRIG18 + Channel 18 Software Trigger + 18 + 1 + + + SWTRIG19 + Channel 19 Software Trigger + 19 + 1 + + + SWTRIG20 + Channel 20 Software Trigger + 20 + 1 + + + SWTRIG21 + Channel 21 Software Trigger + 21 + 1 + + + SWTRIG22 + Channel 22 Software Trigger + 22 + 1 + + + SWTRIG23 + Channel 23 Software Trigger + 23 + 1 + + + SWTRIG24 + Channel 24 Software Trigger + 24 + 1 + + + SWTRIG25 + Channel 25 Software Trigger + 25 + 1 + + + SWTRIG26 + Channel 26 Software Trigger + 26 + 1 + + + SWTRIG27 + Channel 27 Software Trigger + 27 + 1 + + + SWTRIG28 + Channel 28 Software Trigger + 28 + 1 + + + SWTRIG29 + Channel 29 Software Trigger + 29 + 1 + + + SWTRIG30 + Channel 30 Software Trigger + 30 + 1 + + + SWTRIG31 + Channel 31 Software Trigger + 31 + 1 + + + + + PRICTRL0 + Priority Control 0 + 0x14 + 32 + 0x40404040 + + + LVLPRI0 + Level 0 Channel Priority Number + 0 + 5 + + + QOS0 + Level 0 Quality of Service + 5 + 2 + + QOS0Select + + REGULAR + Regular delivery + 0x0 + + + SHORTAGE + Bandwidth shortage + 0x1 + + + SENSITIVE + Latency sensitive + 0x2 + + + CRITICAL + Latency critical + 0x3 + + + + + RRLVLEN0 + Level 0 Round-Robin Scheduling Enable + 7 + 1 + + + LVLPRI1 + Level 1 Channel Priority Number + 8 + 5 + + + QOS1 + Level 1 Quality of Service + 13 + 2 + + QOS1Select + + REGULAR + Regular delivery + 0x0 + + + SHORTAGE + Bandwidth shortage + 0x1 + + + SENSITIVE + Latency sensitive + 0x2 + + + CRITICAL + Latency critical + 0x3 + + + + + RRLVLEN1 + Level 1 Round-Robin Scheduling Enable + 15 + 1 + + + LVLPRI2 + Level 2 Channel Priority Number + 16 + 5 + + + QOS2 + Level 2 Quality of Service + 21 + 2 + + QOS2Select + + REGULAR + Regular delivery + 0x0 + + + SHORTAGE + Bandwidth shortage + 0x1 + + + SENSITIVE + Latency sensitive + 0x2 + + + CRITICAL + Latency critical + 0x3 + + + + + RRLVLEN2 + Level 2 Round-Robin Scheduling Enable + 23 + 1 + + + LVLPRI3 + Level 3 Channel Priority Number + 24 + 5 + + + QOS3 + Level 3 Quality of Service + 29 + 2 + + QOS3Select + + REGULAR + Regular delivery + 0x0 + + + SHORTAGE + Bandwidth shortage + 0x1 + + + SENSITIVE + Latency sensitive + 0x2 + + + CRITICAL + Latency critical + 0x3 + + + + + RRLVLEN3 + Level 3 Round-Robin Scheduling Enable + 31 + 1 + + + + + INTPEND + Interrupt Pending + 0x20 + 16 + + + ID + Channel ID + 0 + 5 + + + TERR + Transfer Error + 8 + 1 + + + TCMPL + Transfer Complete + 9 + 1 + + + SUSP + Channel Suspend + 10 + 1 + + + CRCERR + CRC Error + 12 + 1 + + + FERR + Fetch Error + 13 + 1 + read-only + + + BUSY + Busy + 14 + 1 + read-only + + + PEND + Pending + 15 + 1 + read-only + + + + + INTSTATUS + Interrupt Status + 0x24 + 32 + read-only + + + CHINT0 + Channel 0 Pending Interrupt + 0 + 1 + read-only + + + CHINT1 + Channel 1 Pending Interrupt + 1 + 1 + read-only + + + CHINT2 + Channel 2 Pending Interrupt + 2 + 1 + read-only + + + CHINT3 + Channel 3 Pending Interrupt + 3 + 1 + read-only + + + CHINT4 + Channel 4 Pending Interrupt + 4 + 1 + read-only + + + CHINT5 + Channel 5 Pending Interrupt + 5 + 1 + read-only + + + CHINT6 + Channel 6 Pending Interrupt + 6 + 1 + read-only + + + CHINT7 + Channel 7 Pending Interrupt + 7 + 1 + read-only + + + CHINT8 + Channel 8 Pending Interrupt + 8 + 1 + read-only + + + CHINT9 + Channel 9 Pending Interrupt + 9 + 1 + read-only + + + CHINT10 + Channel 10 Pending Interrupt + 10 + 1 + read-only + + + CHINT11 + Channel 11 Pending Interrupt + 11 + 1 + read-only + + + CHINT12 + Channel 12 Pending Interrupt + 12 + 1 + read-only + + + CHINT13 + Channel 13 Pending Interrupt + 13 + 1 + read-only + + + CHINT14 + Channel 14 Pending Interrupt + 14 + 1 + read-only + + + CHINT15 + Channel 15 Pending Interrupt + 15 + 1 + read-only + + + CHINT16 + Channel 16 Pending Interrupt + 16 + 1 + read-only + + + CHINT17 + Channel 17 Pending Interrupt + 17 + 1 + read-only + + + CHINT18 + Channel 18 Pending Interrupt + 18 + 1 + read-only + + + CHINT19 + Channel 19 Pending Interrupt + 19 + 1 + read-only + + + CHINT20 + Channel 20 Pending Interrupt + 20 + 1 + read-only + + + CHINT21 + Channel 21 Pending Interrupt + 21 + 1 + read-only + + + CHINT22 + Channel 22 Pending Interrupt + 22 + 1 + read-only + + + CHINT23 + Channel 23 Pending Interrupt + 23 + 1 + read-only + + + CHINT24 + Channel 24 Pending Interrupt + 24 + 1 + read-only + + + CHINT25 + Channel 25 Pending Interrupt + 25 + 1 + read-only + + + CHINT26 + Channel 26 Pending Interrupt + 26 + 1 + read-only + + + CHINT27 + Channel 27 Pending Interrupt + 27 + 1 + read-only + + + CHINT28 + Channel 28 Pending Interrupt + 28 + 1 + read-only + + + CHINT29 + Channel 29 Pending Interrupt + 29 + 1 + read-only + + + CHINT30 + Channel 30 Pending Interrupt + 30 + 1 + read-only + + + CHINT31 + Channel 31 Pending Interrupt + 31 + 1 + read-only + + + + + BUSYCH + Busy Channels + 0x28 + 32 + read-only + + + BUSYCH0 + Busy Channel 0 + 0 + 1 + read-only + + + BUSYCH1 + Busy Channel 1 + 1 + 1 + read-only + + + BUSYCH2 + Busy Channel 2 + 2 + 1 + read-only + + + BUSYCH3 + Busy Channel 3 + 3 + 1 + read-only + + + BUSYCH4 + Busy Channel 4 + 4 + 1 + read-only + + + BUSYCH5 + Busy Channel 5 + 5 + 1 + read-only + + + BUSYCH6 + Busy Channel 6 + 6 + 1 + read-only + + + BUSYCH7 + Busy Channel 7 + 7 + 1 + read-only + + + BUSYCH8 + Busy Channel 8 + 8 + 1 + read-only + + + BUSYCH9 + Busy Channel 9 + 9 + 1 + read-only + + + BUSYCH10 + Busy Channel 10 + 10 + 1 + read-only + + + BUSYCH11 + Busy Channel 11 + 11 + 1 + read-only + + + BUSYCH12 + Busy Channel 12 + 12 + 1 + read-only + + + BUSYCH13 + Busy Channel 13 + 13 + 1 + read-only + + + BUSYCH14 + Busy Channel 14 + 14 + 1 + read-only + + + BUSYCH15 + Busy Channel 15 + 15 + 1 + read-only + + + BUSYCH16 + Busy Channel 16 + 16 + 1 + read-only + + + BUSYCH17 + Busy Channel 17 + 17 + 1 + read-only + + + BUSYCH18 + Busy Channel 18 + 18 + 1 + read-only + + + BUSYCH19 + Busy Channel 19 + 19 + 1 + read-only + + + BUSYCH20 + Busy Channel 20 + 20 + 1 + read-only + + + BUSYCH21 + Busy Channel 21 + 21 + 1 + read-only + + + BUSYCH22 + Busy Channel 22 + 22 + 1 + read-only + + + BUSYCH23 + Busy Channel 23 + 23 + 1 + read-only + + + BUSYCH24 + Busy Channel 24 + 24 + 1 + read-only + + + BUSYCH25 + Busy Channel 25 + 25 + 1 + read-only + + + BUSYCH26 + Busy Channel 26 + 26 + 1 + read-only + + + BUSYCH27 + Busy Channel 27 + 27 + 1 + read-only + + + BUSYCH28 + Busy Channel 28 + 28 + 1 + read-only + + + BUSYCH29 + Busy Channel 29 + 29 + 1 + read-only + + + BUSYCH30 + Busy Channel 30 + 30 + 1 + read-only + + + BUSYCH31 + Busy Channel 31 + 31 + 1 + read-only + + + + + PENDCH + Pending Channels + 0x2C + 32 + read-only + + + PENDCH0 + Pending Channel 0 + 0 + 1 + read-only + + + PENDCH1 + Pending Channel 1 + 1 + 1 + read-only + + + PENDCH2 + Pending Channel 2 + 2 + 1 + read-only + + + PENDCH3 + Pending Channel 3 + 3 + 1 + read-only + + + PENDCH4 + Pending Channel 4 + 4 + 1 + read-only + + + PENDCH5 + Pending Channel 5 + 5 + 1 + read-only + + + PENDCH6 + Pending Channel 6 + 6 + 1 + read-only + + + PENDCH7 + Pending Channel 7 + 7 + 1 + read-only + + + PENDCH8 + Pending Channel 8 + 8 + 1 + read-only + + + PENDCH9 + Pending Channel 9 + 9 + 1 + read-only + + + PENDCH10 + Pending Channel 10 + 10 + 1 + read-only + + + PENDCH11 + Pending Channel 11 + 11 + 1 + read-only + + + PENDCH12 + Pending Channel 12 + 12 + 1 + read-only + + + PENDCH13 + Pending Channel 13 + 13 + 1 + read-only + + + PENDCH14 + Pending Channel 14 + 14 + 1 + read-only + + + PENDCH15 + Pending Channel 15 + 15 + 1 + read-only + + + PENDCH16 + Pending Channel 16 + 16 + 1 + read-only + + + PENDCH17 + Pending Channel 17 + 17 + 1 + read-only + + + PENDCH18 + Pending Channel 18 + 18 + 1 + read-only + + + PENDCH19 + Pending Channel 19 + 19 + 1 + read-only + + + PENDCH20 + Pending Channel 20 + 20 + 1 + read-only + + + PENDCH21 + Pending Channel 21 + 21 + 1 + read-only + + + PENDCH22 + Pending Channel 22 + 22 + 1 + read-only + + + PENDCH23 + Pending Channel 23 + 23 + 1 + read-only + + + PENDCH24 + Pending Channel 24 + 24 + 1 + read-only + + + PENDCH25 + Pending Channel 25 + 25 + 1 + read-only + + + PENDCH26 + Pending Channel 26 + 26 + 1 + read-only + + + PENDCH27 + Pending Channel 27 + 27 + 1 + read-only + + + PENDCH28 + Pending Channel 28 + 28 + 1 + read-only + + + PENDCH29 + Pending Channel 29 + 29 + 1 + read-only + + + PENDCH30 + Pending Channel 30 + 30 + 1 + read-only + + + PENDCH31 + Pending Channel 31 + 31 + 1 + read-only + + + + + ACTIVE + Active Channel and Levels + 0x30 + 32 + read-only + + + LVLEX0 + Level 0 Channel Trigger Request Executing + 0 + 1 + read-only + + + LVLEX1 + Level 1 Channel Trigger Request Executing + 1 + 1 + read-only + + + LVLEX2 + Level 2 Channel Trigger Request Executing + 2 + 1 + read-only + + + LVLEX3 + Level 3 Channel Trigger Request Executing + 3 + 1 + read-only + + + ID + Active Channel ID + 8 + 5 + read-only + + + ABUSY + Active Channel Busy + 15 + 1 + read-only + + + BTCNT + Active Channel Block Transfer Count + 16 + 16 + read-only + + + + + BASEADDR + Descriptor Memory Section Base Address + 0x34 + 32 + + + BASEADDR + Descriptor Memory Base Address + 0 + 32 + + + + + WRBADDR + Write-Back Memory Section Base Address + 0x38 + 32 + + + WRBADDR + Write-Back Memory Base Address + 0 + 32 + + + + + 32 + 0x10 + CHCTRLA%s + Channel n Control A + 0x40 + 32 + + + SWRST + Channel Software Reset + 0 + 1 + + + ENABLE + Channel Enable + 1 + 1 + + + RUNSTDBY + Channel Run in Standby + 6 + 1 + + + TRIGSRC + Trigger Source + 8 + 7 + + TRIGSRCSelect + + DISABLE + Only software/event triggers + 0x0 + + + + + TRIGACT + Trigger Action + 20 + 2 + + TRIGACTSelect + + BLOCK + One trigger required for each block transfer + 0x0 + + + BURST + One trigger required for each burst transfer + 0x2 + + + TRANSACTION + One trigger required for each transaction + 0x3 + + + + + BURSTLEN + Burst Length + 24 + 4 + + BURSTLENSelect + + SINGLE + Single-beat burst length + 0x0 + + + 2BEAT + 2-beats burst length + 0x1 + + + 3BEAT + 3-beats burst length + 0x2 + + + 4BEAT + 4-beats burst length + 0x3 + + + 5BEAT + 5-beats burst length + 0x4 + + + 6BEAT + 6-beats burst length + 0x5 + + + 7BEAT + 7-beats burst length + 0x6 + + + 8BEAT + 8-beats burst length + 0x7 + + + 9BEAT + 9-beats burst length + 0x8 + + + 10BEAT + 10-beats burst length + 0x9 + + + 11BEAT + 11-beats burst length + 0xa + + + 12BEAT + 12-beats burst length + 0xb + + + 13BEAT + 13-beats burst length + 0xc + + + 14BEAT + 14-beats burst length + 0xd + + + 15BEAT + 15-beats burst length + 0xe + + + 16BEAT + 16-beats burst length + 0xf + + + + + THRESHOLD + FIFO Threshold + 28 + 2 + + THRESHOLDSelect + + 1BEAT + Destination write starts after each beat source address read + 0x0 + + + 2BEATS + Destination write starts after 2-beats source address read + 0x1 + + + 4BEATS + Destination write starts after 4-beats source address read + 0x2 + + + 8BEATS + Destination write starts after 8-beats source address read + 0x3 + + + + + + + 32 + 0x10 + CHCTRLB%s + Channel n Control B + 0x44 + 8 + + + CMD + Software Command + 0 + 2 + + CMDSelect + + NOACT + No action + 0x0 + + + SUSPEND + Channel suspend operation + 0x1 + + + RESUME + Channel resume operation + 0x2 + + + + + + + 32 + 0x10 + CHPRILVL%s + Channel n Priority Level + 0x45 + 8 + + + PRILVL + Channel Priority Level + 0 + 2 + + PRILVLSelect + + LVL0 + Channel Priority Level 0 (Lowest Level) + 0x0 + + + LVL1 + Channel Priority Level 1 + 0x1 + + + LVL2 + Channel Priority Level 2 + 0x2 + + + LVL3 + Channel Priority Level 3 + 0x3 + + + LVL4 + Channel Priority Level 4 + 0x4 + + + LVL5 + Channel Priority Level 5 + 0x5 + + + LVL6 + Channel Priority Level 6 + 0x6 + + + LVL7 + Channel Priority Level 7 (Highest Level) + 0x7 + + + + + + + 32 + 0x10 + CHEVCTRL%s + Channel n Event Control + 0x46 + 8 + + + EVACT + Channel Event Input Action + 0 + 3 + + EVACTSelect + + NOACT + No action + 0x0 + + + TRIG + Transfer and periodic transfer trigger + 0x1 + + + CTRIG + Conditional transfer trigger + 0x2 + + + CBLOCK + Conditional block transfer + 0x3 + + + SUSPEND + Channel suspend operation + 0x4 + + + RESUME + Channel resume operation + 0x5 + + + SSKIP + Skip next block suspend action + 0x6 + + + INCPRI + Increase priority + 0x7 + + + + + EVOMODE + Channel Event Output Mode + 4 + 2 + + EVOMODESelect + + DEFAULT + Block event output selection. Refer to BTCTRL.EVOSEL for available selections. + 0x0 + + + TRIGACT + Ongoing trigger action + 0x1 + + + + + EVIE + Channel Event Input Enable + 6 + 1 + + + EVOE + Channel Event Output Enable + 7 + 1 + + + + + 32 + 0x10 + CHINTENCLR%s + Channel n Interrupt Enable Clear + 0x4C + 8 + + + TERR + Channel Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Channel Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + 32 + 0x10 + CHINTENSET%s + Channel n Interrupt Enable Set + 0x4D + 8 + + + TERR + Channel Transfer Error Interrupt Enable + 0 + 1 + + + TCMPL + Channel Transfer Complete Interrupt Enable + 1 + 1 + + + SUSP + Channel Suspend Interrupt Enable + 2 + 1 + + + + + 32 + 0x10 + CHINTFLAG%s + Channel n Interrupt Flag Status and Clear + 0x4E + 8 + + + TERR + Channel Transfer Error + 0 + 1 + + + TCMPL + Channel Transfer Complete + 1 + 1 + + + SUSP + Channel Suspend + 2 + 1 + + + + + 32 + 0x10 + CHSTATUS%s + Channel n Status + 0x4F + 8 + + + PEND + Channel Pending + 0 + 1 + read-only + + + BUSY + Channel Busy + 1 + 1 + read-only + + + FERR + Channel Fetch Error + 2 + 1 + read-only + + + CRCERR + Channel CRC Error + 3 + 1 + + + + + + + DSU + 1.0.0 + Device Service Unit + DSU + DSU_ + 0x41002000 + + 0 + 0x2000 + registers + + + + CTRL + Control + 0x0000 + 8 + write-only + + + SWRST + Software Reset + 0 + 1 + write-only + + + CRC + 32-bit Cyclic Redundancy Code + 2 + 1 + write-only + + + MBIST + Memory built-in self-test + 3 + 1 + write-only + + + CE + Chip-Erase + 4 + 1 + write-only + + + ARR + Auxiliary Row Read + 6 + 1 + write-only + + + SMSA + Start Memory Stream Access + 7 + 1 + write-only + + + + + STATUSA + Status A + 0x0001 + 8 + + + DONE + Done + 0 + 1 + + + CRSTEXT + CPU Reset Phase Extension + 1 + 1 + + + BERR + Bus Error + 2 + 1 + + + FAIL + Failure + 3 + 1 + + + PERR + Protection Error + 4 + 1 + + + + + STATUSB + Status B + 0x0002 + 8 + read-only + + + PROT + Protected + 0 + 1 + read-only + + + DBGPRES + Debugger Present + 1 + 1 + read-only + + + DCCD0 + Debug Communication Channel 0 Dirty + 2 + 1 + read-only + + + DCCD1 + Debug Communication Channel 1 Dirty + 3 + 1 + read-only + + + HPE + Hot-Plugging Enable + 4 + 1 + read-only + + + CELCK + Chip Erase Locked + 5 + 1 + read-only + + + TDCCD0 + Test Debug Communication Channel 0 Dirty + 6 + 1 + read-only + + + TDCCD1 + Test Debug Communication Channel 1 Dirty + 7 + 1 + read-only + + + + + ADDR + Address + 0x0004 + 32 + + + AMOD + Access Mode + 0 + 2 + + + ADDR + Address + 2 + 30 + + + + + LENGTH + Length + 0x0008 + 32 + + + LENGTH + Length + 2 + 30 + + + + + DATA + Data + 0x000C + 32 + + + DATA + Data + 0 + 32 + + + + + 2 + 0x4 + DCC%s + Debug Communication Channel n + 0x0010 + 32 + + + DATA + Data + 0 + 32 + + + + + DID + Device Identification + 0x0018 + 32 + read-only + 0x60060005 + + + DEVSEL + Device Select + 0 + 8 + read-only + + + REVISION + Revision Number + 8 + 4 + read-only + + + DIE + Die Number + 12 + 4 + read-only + + + SERIES + Series + 16 + 6 + read-only + + SERIESSelect + + 0 + Cortex-M0+ processor, basic feature set + 0x0 + + + 1 + Cortex-M0+ processor, USB + 0x1 + + + + + FAMILY + Family + 23 + 5 + read-only + + FAMILYSelect + + 0 + General purpose microcontroller + 0x0 + + + 1 + PicoPower + 0x1 + + + + + PROCESSOR + Processor + 28 + 4 + read-only + + PROCESSORSelect + + CM0P + Cortex-M0+ + 0x1 + + + CM23 + Cortex-M23 + 0x2 + + + CM3 + Cortex-M3 + 0x3 + + + CM4 + Cortex-M4 + 0x5 + + + CM4F + Cortex-M4 with FPU + 0x6 + + + CM33 + Cortex-M33 + 0x7 + + + + + + + CFG + Configuration + 0x001C + 32 + 0x00000002 + + + LQOS + Latency Quality Of Service + 0 + 2 + + + DCCDMALEVEL + DMA Trigger Level + 2 + 2 + + DCCDMALEVELSelect + + EMPTY + Trigger rises when DCC is empty + 0x0 + + + FULL + Trigger rises when DCC is full + 0x1 + + + + + ETBRAMEN + Trace Control + 4 + 1 + + + + + MBCTRL + MBIST Control + 0x0040 + 32 + + + SWRST + MBIST Software Reset + 0 + 1 + + + ENABLE + MBIST Enable + 1 + 1 + + + + + MBCONFIG + MBIST Configuration + 0x0044 + 32 + + + ALGO + MBIST Algorithm + 0 + 5 + + ALGOSelect + + MEMCLEAR + Memory Clear (1n) + 0x0 + + + VERIFY + Memory Verify (1n) + 0x1 + + + CLEARVER + Memory Clear and Verify (2n) + 0x2 + + + ADDR_DEC + Address Decoder (2n) + 0x3 + + + MARCH_LR + March LR (14n) + 0x4 + + + MARCH_SR + March SR (14n) + 0x5 + + + MARCH_SS + March SS (22n) + 0x6 + + + CRC_UP + CRC increasing address (1n) + 0x8 + + + CRC_DOWN + CRC decreasing address (1n) + 0x9 + + + + + DEFRDMARGIN + Force Default Read Margin + 6 + 1 + + + DBG + Enable Debug Mode + 7 + 1 + + + + + MBWORD + MBIST Background Word + 0x0048 + 32 + + + DATA + MBIST Background Word + 0 + 32 + + + + + MBGSTAT + MBIST Global Status + 0x004C + 32 + + + ALLDONE + MBIST Completed + 0 + 1 + + + FAILED + MBIST Failed + 1 + 1 + + + ERRINFO + MBIST Error Info Present + 2 + 1 + + + CONFIGURED + MBIST Configuration Sent + 3 + 1 + + + + + MBDFAIL + MBIST Fail Data + 0x0050 + 32 + read-only + + + DATA + Error Data Read + 0 + 32 + + + + + MBDEXP + MBIST Expected Data + 0x0054 + 32 + read-only + + + DATA + Expected Data + 0 + 32 + + + + + MBAFAIL + MBIST Fail Address + 0x0058 + 32 + read-only + + + ADDR + Error Address + 0 + 14 + + + + + MBCONTEXT + MBIST Fail Context + 0x005C + 32 + read-only + + + SUBSTEP + Algorithm Sub-step + 0 + 5 + + SUBSTEPSelect + + R0_1 + 0x1 + + + R1_1 + 0x3 + + + R0_2 + 0x5 + + + R1_2 + 0x7 + + + R0_3 + 0x9 + + + R1_3 + 0xb + + + + + STEP + Algorithm Step + 5 + 5 + + STEPSelect + + DOWN_R0W1 + 0x2 + + + UP_R1W0R0W1 + 0x3 + + + UP_R1W0 + 0x4 + + + UP_R0W1R1W0 + 0x5 + + + UP_R0 + 0x6 + + + UP_R0R0W0R0W1 + 0x7 + + + UP_R1R1W1R1W0 + 0x8 + + + DOWN_R0R0W0R0W1 + 0x9 + + + DOWN_R1R1W1R1W0 + 0xa + + + UP_R0R0 + 0xc + + + DOWN_R1W0R0W1 + 0xe + + + DOWN_R1R1 + 0xf + + + + + PORT + DPRAM Port Index + 10 + 1 + + + + + MBENABLE0 + MBIST Memory Enable 0 + 0x0060 + 32 + + + ENABLE0 + Memory 0 MBIST Enable + 0 + 1 + + + ENABLE1 + Memory 1 MBIST Enable + 1 + 1 + + + ENABLE2 + Memory 2 MBIST Enable + 2 + 1 + + + ENABLE3 + Memory 3 MBIST Enable + 3 + 1 + + + ENABLE4 + Memory 4 MBIST Enable + 4 + 1 + + + ENABLE5 + Memory 5 MBIST Enable + 5 + 1 + + + ENABLE6 + Memory 6 MBIST Enable + 6 + 1 + + + ENABLE7 + Memory 7 MBIST Enable + 7 + 1 + + + ENABLE8 + Memory 8 MBIST Enable + 8 + 1 + + + ENABLE9 + Memory 9 MBIST Enable + 9 + 1 + + + ENABLE10 + Memory 10 MBIST Enable + 10 + 1 + + + ENABLE11 + Memory 11 MBIST Enable + 11 + 1 + + + ENABLE12 + Memory 12 MBIST Enable + 12 + 1 + + + ENABLE13 + Memory 13 MBIST Enable + 13 + 1 + + + ENABLE14 + Memory 14 MBIST Enable + 14 + 1 + + + ENABLE15 + Memory 15 MBIST Enable + 15 + 1 + + + ENABLE16 + Memory 16 MBIST Enable + 16 + 1 + + + ENABLE17 + Memory 17 MBIST Enable + 17 + 1 + + + ENABLE18 + Memory 18 MBIST Enable + 18 + 1 + + + ENABLE19 + Memory 19 MBIST Enable + 19 + 1 + + + ENABLE20 + Memory 20 MBIST Enable + 20 + 1 + + + ENABLE21 + Memory 21 MBIST Enable + 21 + 1 + + + ENABLE22 + Memory 22 MBIST Enable + 22 + 1 + + + ENABLE23 + Memory 23 MBIST Enable + 23 + 1 + + + ENABLE24 + Memory 24 MBIST Enable + 24 + 1 + + + ENABLE25 + Memory 25 MBIST Enable + 25 + 1 + + + ENABLE26 + Memory 26 MBIST Enable + 26 + 1 + + + ENABLE27 + Memory 27 MBIST Enable + 27 + 1 + + + ENABLE28 + Memory 28 MBIST Enable + 28 + 1 + + + + + MBBUSY0 + MBIST Memory Busy 0 + 0x0068 + 32 + read-only + + + BUSY0 + Memory 0 BIST Busy + 0 + 1 + + + BUSY1 + Memory 1 BIST Busy + 1 + 1 + + + BUSY2 + Memory 2 BIST Busy + 2 + 1 + + + BUSY3 + Memory 3 BIST Busy + 3 + 1 + + + BUSY4 + Memory 4 BIST Busy + 4 + 1 + + + BUSY5 + Memory 5 BIST Busy + 5 + 1 + + + BUSY6 + Memory 6 BIST Busy + 6 + 1 + + + BUSY7 + Memory 7 BIST Busy + 7 + 1 + + + BUSY8 + Memory 8 BIST Busy + 8 + 1 + + + BUSY9 + Memory 9 BIST Busy + 9 + 1 + + + BUSY10 + Memory 10 BIST Busy + 10 + 1 + + + BUSY11 + Memory 11 BIST Busy + 11 + 1 + + + BUSY12 + Memory 12 BIST Busy + 12 + 1 + + + BUSY13 + Memory 13 BIST Busy + 13 + 1 + + + BUSY14 + Memory 14 BIST Busy + 14 + 1 + + + BUSY15 + Memory 15 BIST Busy + 15 + 1 + + + BUSY16 + Memory 16 BIST Busy + 16 + 1 + + + BUSY17 + Memory 17 BIST Busy + 17 + 1 + + + BUSY18 + Memory 18 BIST Busy + 18 + 1 + + + BUSY19 + Memory 19 BIST Busy + 19 + 1 + + + BUSY20 + Memory 20 BIST Busy + 20 + 1 + + + BUSY21 + Memory 21 BIST Busy + 21 + 1 + + + BUSY22 + Memory 22 BIST Busy + 22 + 1 + + + BUSY23 + Memory 23 BIST Busy + 23 + 1 + + + BUSY24 + Memory 24 BIST Busy + 24 + 1 + + + BUSY25 + Memory 25 BIST Busy + 25 + 1 + + + BUSY26 + Memory 26 BIST Busy + 26 + 1 + + + BUSY27 + Memory 27 BIST Busy + 27 + 1 + + + BUSY28 + Memory 28 BIST Busy + 28 + 1 + + + + + MBSTATUS0 + MBIST Memory Status 0 + 0x0070 + 32 + + + STATUS0 + Memory 0 MBIST Status + 0 + 1 + + + STATUS1 + Memory 1 MBIST Status + 1 + 1 + + + STATUS2 + Memory 2 MBIST Status + 2 + 1 + + + STATUS3 + Memory 3 MBIST Status + 3 + 1 + + + STATUS4 + Memory 4 MBIST Status + 4 + 1 + + + STATUS5 + Memory 5 MBIST Status + 5 + 1 + + + STATUS6 + Memory 6 MBIST Status + 6 + 1 + + + STATUS7 + Memory 7 MBIST Status + 7 + 1 + + + STATUS8 + Memory 8 MBIST Status + 8 + 1 + + + STATUS9 + Memory 9 MBIST Status + 9 + 1 + + + STATUS10 + Memory 10 MBIST Status + 10 + 1 + + + STATUS11 + Memory 11 MBIST Status + 11 + 1 + + + STATUS12 + Memory 12 MBIST Status + 12 + 1 + + + STATUS13 + Memory 13 MBIST Status + 13 + 1 + + + STATUS14 + Memory 14 MBIST Status + 14 + 1 + + + STATUS15 + Memory 15 MBIST Status + 15 + 1 + + + STATUS16 + Memory 16 MBIST Status + 16 + 1 + + + STATUS17 + Memory 17 MBIST Status + 17 + 1 + + + STATUS18 + Memory 18 MBIST Status + 18 + 1 + + + STATUS19 + Memory 19 MBIST Status + 19 + 1 + + + STATUS20 + Memory 20 MBIST Status + 20 + 1 + + + STATUS21 + Memory 21 MBIST Status + 21 + 1 + + + STATUS22 + Memory 22 MBIST Status + 22 + 1 + + + STATUS23 + Memory 23 MBIST Status + 23 + 1 + + + STATUS24 + Memory 24 MBIST Status + 24 + 1 + + + STATUS25 + Memory 25 MBIST Status + 25 + 1 + + + STATUS26 + Memory 26 MBIST Status + 26 + 1 + + + STATUS27 + Memory 27 MBIST Status + 27 + 1 + + + STATUS28 + Memory 28 MBIST Status + 28 + 1 + + + + + 2 + 0x4 + DCFG%s + Device Configuration + 0x00F0 + 32 + + + DCFG + Device Configuration + 0 + 32 + + + + + ENTRY0 + CoreSight ROM Table Entry 0 + 0x1000 + 32 + read-only + 0x9F0FC002 + + + EPRES + Entry Present + 0 + 1 + + + FMT + Format + 1 + 1 + read-only + + + ADDOFF + Address Offset + 12 + 20 + read-only + + + + + ENTRY1 + CoreSight ROM Table Entry 1 + 0x1004 + 32 + read-only + + + END + CoreSight ROM Table End + 0x1008 + 32 + read-only + + + END + End Marker + 0 + 32 + + + + + MEMTYPE + CoreSight ROM Table Memory Type + 0x1FCC + 32 + read-only + + + SMEMP + System Memory Present + 0 + 1 + + + + + PID4 + Peripheral Identification 4 + 0x1FD0 + 32 + read-only + + + JEPCC + JEP-106 Continuation Code + 0 + 4 + + + FKBC + 4KB count + 4 + 4 + read-only + + + + + PID5 + Peripheral Identification 5 + 0x1FD4 + 32 + read-only + + + PID6 + Peripheral Identification 6 + 0x1FD8 + 32 + read-only + + + PID7 + Peripheral Identification 7 + 0x1FDC + 32 + read-only + + + PID0 + Peripheral Identification 0 + 0x1FE0 + 32 + read-only + 0x000000D0 + + + PARTNBL + Part Number Low + 0 + 8 + + + + + PID1 + Peripheral Identification 1 + 0x1FE4 + 32 + read-only + 0x000000FC + + + PARTNBH + Part Number High + 0 + 4 + + + JEPIDCL + Low part of the JEP-106 Identity Code + 4 + 4 + read-only + + + + + PID2 + Peripheral Identification 2 + 0x1FE8 + 32 + read-only + 0x00000009 + + + JEPIDCH + JEP-106 Identity Code High + 0 + 3 + + + JEPU + JEP-106 Identity Code is used + 3 + 1 + read-only + + + REVISION + Revision Number + 4 + 4 + read-only + + + + + PID3 + Peripheral Identification 3 + 0x1FEC + 32 + read-only + + + CUSMOD + ARM CUSMOD + 0 + 4 + + + REVAND + Revision Number + 4 + 4 + read-only + + + + + CID0 + Component Identification 0 + 0x1FF0 + 32 + read-only + 0x0000000D + + + PREAMBLEB0 + Preamble Byte 0 + 0 + 8 + read-only + + + + + CID1 + Component Identification 1 + 0x1FF4 + 32 + read-only + 0x00000010 + + + PREAMBLE + Preamble + 0 + 4 + read-only + + + CCLASS + Component Class + 4 + 4 + read-only + + + + + CID2 + Component Identification 2 + 0x1FF8 + 32 + read-only + 0x00000005 + + + PREAMBLEB2 + Preamble Byte 2 + 0 + 8 + read-only + + + + + CID3 + Component Identification 3 + 0x1FFC + 32 + read-only + 0x000000B1 + + + PREAMBLEB3 + Preamble Byte 3 + 0 + 8 + + + + + + + EIC + 3.0.0 + External Interrupt Controller + EIC + EIC_ + 0x40002800 + + 0 + 0x40 + registers + + + EIC_INTREQ_0 + 12 + + + EIC_INTREQ_1 + 13 + + + EIC_INTREQ_2 + 14 + + + EIC_INTREQ_3 + 15 + + + EIC_INTREQ_4 + 16 + + + EIC_INTREQ_5 + 17 + + + EIC_INTREQ_6 + 18 + + + EIC_INTREQ_7 + 19 + + + EIC_INTREQ_8 + 20 + + + EIC_INTREQ_9 + 21 + + + EIC_INTREQ_10 + 22 + + + EIC_INTREQ_11 + 23 + + + EIC_INTREQ_12 + 24 + + + EIC_INTREQ_13 + 25 + + + EIC_INTREQ_14 + 26 + + + EIC_INTREQ_15 + 27 + + + + CTRLA + Control A + 0x00 + 8 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + CKSEL + Clock Selection + 4 + 1 + + + + + NMICTRL + Non-Maskable Interrupt Control + 0x01 + 8 + + + NMISENSE + Non-Maskable Interrupt Sense Configuration + 0 + 3 + + NMISENSESelect + + NONE + No detection + 0x0 + + + RISE + Rising-edge detection + 0x1 + + + FALL + Falling-edge detection + 0x2 + + + BOTH + Both-edges detection + 0x3 + + + HIGH + High-level detection + 0x4 + + + LOW + Low-level detection + 0x5 + + + + + NMIFILTEN + Non-Maskable Interrupt Filter Enable + 3 + 1 + + + NMIASYNCH + Asynchronous Edge Detection Mode + 4 + 1 + + + + + NMIFLAG + Non-Maskable Interrupt Flag Status and Clear + 0x02 + 16 + + + NMI + Non-Maskable Interrupt + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x04 + 32 + read-only + + + SWRST + Software Reset Synchronization Busy Status + 0 + 1 + read-only + + + ENABLE + Enable Synchronization Busy Status + 1 + 1 + read-only + + + + + EVCTRL + Event Control + 0x08 + 32 + + + EXTINTEO + External Interrupt Event Output Enable + 0 + 16 + + + + + INTENCLR + Interrupt Enable Clear + 0x0C + 32 + + + EXTINT + External Interrupt Enable + 0 + 16 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 32 + + + EXTINT + External Interrupt Enable + 0 + 16 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 32 + + + EXTINT + External Interrupt + 0 + 16 + + + + + ASYNCH + External Interrupt Asynchronous Mode + 0x18 + 32 + + + ASYNCH + Asynchronous Edge Detection Mode + 0 + 16 + + + + + 2 + 0x4 + CONFIG%s + External Interrupt Sense Configuration + 0x1C + 32 + + + SENSE0 + Input Sense Configuration 0 + 0 + 3 + + SENSE0Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN0 + Filter Enable 0 + 3 + 1 + + + SENSE1 + Input Sense Configuration 1 + 4 + 3 + + SENSE1Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN1 + Filter Enable 1 + 7 + 1 + + + SENSE2 + Input Sense Configuration 2 + 8 + 3 + + SENSE2Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN2 + Filter Enable 2 + 11 + 1 + + + SENSE3 + Input Sense Configuration 3 + 12 + 3 + + SENSE3Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN3 + Filter Enable 3 + 15 + 1 + + + SENSE4 + Input Sense Configuration 4 + 16 + 3 + + SENSE4Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN4 + Filter Enable 4 + 19 + 1 + + + SENSE5 + Input Sense Configuration 5 + 20 + 3 + + SENSE5Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN5 + Filter Enable 5 + 23 + 1 + + + SENSE6 + Input Sense Configuration 6 + 24 + 3 + + SENSE6Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN6 + Filter Enable 6 + 27 + 1 + + + SENSE7 + Input Sense Configuration 7 + 28 + 3 + + SENSE7Select + + NONE + No detection + 0x0 + + + RISE + Rising edge detection + 0x1 + + + FALL + Falling edge detection + 0x2 + + + BOTH + Both edges detection + 0x3 + + + HIGH + High level detection + 0x4 + + + LOW + Low level detection + 0x5 + + + + + FILTEN7 + Filter Enable 7 + 31 + 1 + + + + + DEBOUNCEN + Debouncer Enable + 0x30 + 32 + + + DEBOUNCEN + Debouncer Enable + 0 + 16 + + + + + DPRESCALER + Debouncer Prescaler + 0x34 + 32 + + + PRESCALER0 + Debouncer Prescaler + 0 + 3 + + + PRESCALER1 + Debouncer Prescaler + 4 + 3 + + + STATES0 + Debouncer number of states + 3 + 1 + + + STATES1 + Debouncer number of states + 7 + 1 + + + TICKON + Pin Sampler frequency selection + 16 + 1 + + + + + PINSTATE + Pin State + 0x38 + 32 + read-only + + + PINSTATE + Pin State + 0 + 16 + read-only + + + + + + + EVSYS + 1.0.0 + Event System Interface + EVSYS + EVSYS_ + 0x4100E000 + + 0 + 0x400 + registers + + + EVSYS_INTREQ_0 + 36 + + + EVSYS_INTREQ_1 + 37 + + + EVSYS_INTREQ_2 + 38 + + + EVSYS_INTREQ_3 + 39 + + + EVSYS_INTREQ_4 + 40 + + + + CTRLA + Control + 0x000 + 8 + + + SWRST + Software Reset + 0 + 1 + write-only + + + + + SWEVT + Software Event + 0x004 + 32 + write-only + + + CHANNEL0 + Channel 0 Software Selection + 0 + 1 + write-only + + + CHANNEL1 + Channel 1 Software Selection + 1 + 1 + write-only + + + CHANNEL2 + Channel 2 Software Selection + 2 + 1 + write-only + + + CHANNEL3 + Channel 3 Software Selection + 3 + 1 + write-only + + + CHANNEL4 + Channel 4 Software Selection + 4 + 1 + write-only + + + CHANNEL5 + Channel 5 Software Selection + 5 + 1 + write-only + + + CHANNEL6 + Channel 6 Software Selection + 6 + 1 + write-only + + + CHANNEL7 + Channel 7 Software Selection + 7 + 1 + write-only + + + CHANNEL8 + Channel 8 Software Selection + 8 + 1 + write-only + + + CHANNEL9 + Channel 9 Software Selection + 9 + 1 + write-only + + + CHANNEL10 + Channel 10 Software Selection + 10 + 1 + write-only + + + CHANNEL11 + Channel 11 Software Selection + 11 + 1 + write-only + + + CHANNEL12 + Channel 12 Software Selection + 12 + 1 + write-only + + + CHANNEL13 + Channel 13 Software Selection + 13 + 1 + write-only + + + CHANNEL14 + Channel 14 Software Selection + 14 + 1 + write-only + + + CHANNEL15 + Channel 15 Software Selection + 15 + 1 + write-only + + + CHANNEL16 + Channel 16 Software Selection + 16 + 1 + write-only + + + CHANNEL17 + Channel 17 Software Selection + 17 + 1 + write-only + + + CHANNEL18 + Channel 18 Software Selection + 18 + 1 + write-only + + + CHANNEL19 + Channel 19 Software Selection + 19 + 1 + write-only + + + CHANNEL20 + Channel 20 Software Selection + 20 + 1 + write-only + + + CHANNEL21 + Channel 21 Software Selection + 21 + 1 + write-only + + + CHANNEL22 + Channel 22 Software Selection + 22 + 1 + write-only + + + CHANNEL23 + Channel 23 Software Selection + 23 + 1 + write-only + + + CHANNEL24 + Channel 24 Software Selection + 24 + 1 + write-only + + + CHANNEL25 + Channel 25 Software Selection + 25 + 1 + write-only + + + CHANNEL26 + Channel 26 Software Selection + 26 + 1 + write-only + + + CHANNEL27 + Channel 27 Software Selection + 27 + 1 + write-only + + + CHANNEL28 + Channel 28 Software Selection + 28 + 1 + write-only + + + CHANNEL29 + Channel 29 Software Selection + 29 + 1 + write-only + + + CHANNEL30 + Channel 30 Software Selection + 30 + 1 + write-only + + + CHANNEL31 + Channel 31 Software Selection + 31 + 1 + write-only + + + + + PRICTRL + Priority Control + 0x008 + 8 + + + PRI + Channel Priority Number + 0 + 4 + + + RREN + Round-Robin Scheduling Enable + 7 + 1 + + + + + INTPEND + Channel Pending Interrupt + 0x010 + 16 + 0x4000 + + + ID + Channel ID + 0 + 4 + + + OVR + Channel Overrun + 8 + 1 + + + EVD + Channel Event Detected + 9 + 1 + + + READY + Ready + 14 + 1 + read-only + + + BUSY + Busy + 15 + 1 + read-only + + + + + INTSTATUS + Interrupt Status + 0x014 + 32 + read-only + + + CHINT0 + Channel 0 Pending Interrupt + 0 + 1 + read-only + + + CHINT1 + Channel 1 Pending Interrupt + 1 + 1 + read-only + + + CHINT2 + Channel 2 Pending Interrupt + 2 + 1 + read-only + + + CHINT3 + Channel 3 Pending Interrupt + 3 + 1 + read-only + + + CHINT4 + Channel 4 Pending Interrupt + 4 + 1 + read-only + + + CHINT5 + Channel 5 Pending Interrupt + 5 + 1 + read-only + + + CHINT6 + Channel 6 Pending Interrupt + 6 + 1 + read-only + + + CHINT7 + Channel 7 Pending Interrupt + 7 + 1 + read-only + + + CHINT8 + Channel 8 Pending Interrupt + 8 + 1 + read-only + + + CHINT9 + Channel 9 Pending Interrupt + 9 + 1 + read-only + + + CHINT10 + Channel 10 Pending Interrupt + 10 + 1 + read-only + + + CHINT11 + Channel 11 Pending Interrupt + 11 + 1 + read-only + + + + + BUSYCH + Busy Channels + 0x018 + 32 + read-only + + + BUSYCH0 + Busy Channel 0 + 0 + 1 + + + BUSYCH1 + Busy Channel 1 + 1 + 1 + + + BUSYCH2 + Busy Channel 2 + 2 + 1 + + + BUSYCH3 + Busy Channel 3 + 3 + 1 + + + BUSYCH4 + Busy Channel 4 + 4 + 1 + + + BUSYCH5 + Busy Channel 5 + 5 + 1 + + + BUSYCH6 + Busy Channel 6 + 6 + 1 + + + BUSYCH7 + Busy Channel 7 + 7 + 1 + + + BUSYCH8 + Busy Channel 8 + 8 + 1 + + + BUSYCH9 + Busy Channel 9 + 9 + 1 + + + BUSYCH10 + Busy Channel 10 + 10 + 1 + + + BUSYCH11 + Busy Channel 11 + 11 + 1 + + + + + READYUSR + Ready Users + 0x01C + 32 + read-only + 0xFFFFFFFF + + + READYUSR0 + Ready User for Channel 0 + 0 + 1 + read-only + + + READYUSR1 + Ready User for Channel 1 + 1 + 1 + read-only + + + READYUSR2 + Ready User for Channel 2 + 2 + 1 + read-only + + + READYUSR3 + Ready User for Channel 3 + 3 + 1 + read-only + + + READYUSR4 + Ready User for Channel 4 + 4 + 1 + read-only + + + READYUSR5 + Ready User for Channel 5 + 5 + 1 + read-only + + + READYUSR6 + Ready User for Channel 6 + 6 + 1 + read-only + + + READYUSR7 + Ready User for Channel 7 + 7 + 1 + read-only + + + READYUSR8 + Ready User for Channel 8 + 8 + 1 + read-only + + + READYUSR9 + Ready User for Channel 9 + 9 + 1 + read-only + + + READYUSR10 + Ready User for Channel 10 + 10 + 1 + read-only + + + READYUSR11 + Ready User for Channel 11 + 11 + 1 + read-only + + + + + 32 + 0x8 + CHANNEL%s + Channel n Control + 0x020 + 32 + 0x00008000 + + + EVGEN + Event Generator Selection + 0 + 7 + + + PATH + Path Selection + 8 + 2 + + PATHSelect + + SYNCHRONOUS + Synchronous path + 0x0 + + + RESYNCHRONIZED + Resynchronized path + 0x1 + + + ASYNCHRONOUS + Asynchronous path + 0x2 + + + + + EDGSEL + Edge Detection Selection + 10 + 2 + + EDGSELSelect + + NO_EVT_OUTPUT + No event output when using the resynchronized or synchronous path + 0x0 + + + RISING_EDGE + Event detection only on the rising edge of the signal from the event generator when using the resynchronized or synchronous path + 0x1 + + + FALLING_EDGE + Event detection only on the falling edge of the signal from the event generator when using the resynchronized or synchronous path + 0x2 + + + BOTH_EDGES + Event detection on rising and falling edges of the signal from the event generator when using the resynchronized or synchronous path + 0x3 + + + + + RUNSTDBY + Run in standby + 14 + 1 + + + ONDEMAND + Generic Clock On Demand + 15 + 1 + + + + + 32 + 0x8 + CHINTENCLR%s + Channel n Interrupt Enable Clear + 0x024 + 8 + + + OVR + Channel Overrun Interrupt Disable + 0 + 1 + + + EVD + Channel Event Detected Interrupt Disable + 1 + 1 + + + + + 32 + 0x8 + CHINTENSET%s + Channel n Interrupt Enable Set + 0x025 + 8 + + + OVR + Channel Overrun Interrupt Enable + 0 + 1 + + + EVD + Channel Event Detected Interrupt Enable + 1 + 1 + + + + + 32 + 0x8 + CHINTFLAG%s + Channel n Interrupt Flag Status and Clear + 0x026 + 8 + + + OVR + Channel Overrun + 0 + 1 + + + EVD + Channel Event Detected + 1 + 1 + + + + + 32 + 0x8 + CHSTATUS%s + Channel n Status + 0x027 + 8 + read-only + 0x01 + + + RDYUSR + Ready User + 0 + 1 + read-only + + + BUSYCH + Busy Channel + 1 + 1 + read-only + + + + + 67 + 0x4 + USER%s + User Multiplexer n + 0x120 + 32 + + + CHANNEL + Channel Event Selection + 0 + 6 + + + + + + + FREQM + 1.1.0 + Frequency Meter + FREQM + FREQM_ + 0x40002C00 + + 0 + 0x20 + registers + + + FREQM_INTREQ + 28 + + + + CTRLA + Control A Register + 0x00 + 8 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + CTRLB + Control B Register + 0x01 + 8 + write-only + + + START + Start Measurement + 0 + 1 + write-only + + + + + CFGA + Config A register + 0x02 + 16 + + + REFNUM + Number of Reference Clock Cycles + 0 + 8 + + + + + INTENCLR + Interrupt Enable Clear Register + 0x08 + 8 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set Register + 0x09 + 8 + + + DONE + Measurement Done Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Register + 0x0A + 8 + + + DONE + Measurement Done + 0 + 1 + + + + + STATUS + Status Register + 0x0B + 8 + + + BUSY + FREQM Status + 0 + 1 + read-only + + + OVF + Sticky Count Value Overflow + 1 + 1 + + + + + SYNCBUSY + Synchronization Busy Register + 0x0C + 32 + read-only + + + SWRST + Software Reset + 0 + 1 + read-only + + + ENABLE + Enable + 1 + 1 + read-only + + + + + VALUE + Count Value Register + 0x10 + 32 + read-only + + + VALUE + Measurement Value + 0 + 24 + read-only + + + + + + + GCLK + 1.2.0 + Generic Clock Generator + GCLK + GCLK_ + 0x40001C00 + + 0 + 0x400 + registers + + + + CTRLA + Control + 0x00 + 8 + + + SWRST + Software Reset + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x04 + 32 + read-only + + + SWRST + Software Reset Synchroniation Busy bit + 0 + 1 + read-only + + + GENCTRL0 + Generic Clock Generator Control 0 Synchronization Busy bits + 2 + 1 + read-only + + GENCTRL0Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + GCLK9 + Generic clock generator 9 + 0x200 + + + GCLK10 + Generic clock generator 10 + 0x400 + + + GCLK11 + Generic clock generator 11 + 0x800 + + + + + GENCTRL1 + Generic Clock Generator Control 1 Synchronization Busy bits + 3 + 1 + read-only + + GENCTRL1Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + GCLK9 + Generic clock generator 9 + 0x200 + + + GCLK10 + Generic clock generator 10 + 0x400 + + + GCLK11 + Generic clock generator 11 + 0x800 + + + + + GENCTRL2 + Generic Clock Generator Control 2 Synchronization Busy bits + 4 + 1 + read-only + + GENCTRL2Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + GCLK9 + Generic clock generator 9 + 0x200 + + + GCLK10 + Generic clock generator 10 + 0x400 + + + GCLK11 + Generic clock generator 11 + 0x800 + + + + + GENCTRL3 + Generic Clock Generator Control 3 Synchronization Busy bits + 5 + 1 + read-only + + GENCTRL3Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + GCLK9 + Generic clock generator 9 + 0x200 + + + GCLK10 + Generic clock generator 10 + 0x400 + + + GCLK11 + Generic clock generator 11 + 0x800 + + + + + GENCTRL4 + Generic Clock Generator Control 4 Synchronization Busy bits + 6 + 1 + read-only + + GENCTRL4Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + GCLK9 + Generic clock generator 9 + 0x200 + + + GCLK10 + Generic clock generator 10 + 0x400 + + + GCLK11 + Generic clock generator 11 + 0x800 + + + + + GENCTRL5 + Generic Clock Generator Control 5 Synchronization Busy bits + 7 + 1 + read-only + + GENCTRL5Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + GCLK9 + Generic clock generator 9 + 0x200 + + + GCLK10 + Generic clock generator 10 + 0x400 + + + GCLK11 + Generic clock generator 11 + 0x800 + + + + + GENCTRL6 + Generic Clock Generator Control 6 Synchronization Busy bits + 8 + 1 + read-only + + GENCTRL6Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + GCLK9 + Generic clock generator 9 + 0x200 + + + GCLK10 + Generic clock generator 10 + 0x400 + + + GCLK11 + Generic clock generator 11 + 0x800 + + + + + GENCTRL7 + Generic Clock Generator Control 7 Synchronization Busy bits + 9 + 1 + read-only + + GENCTRL7Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + GCLK9 + Generic clock generator 9 + 0x200 + + + GCLK10 + Generic clock generator 10 + 0x400 + + + GCLK11 + Generic clock generator 11 + 0x800 + + + + + GENCTRL8 + Generic Clock Generator Control 8 Synchronization Busy bits + 10 + 1 + read-only + + GENCTRL8Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + GCLK9 + Generic clock generator 9 + 0x200 + + + GCLK10 + Generic clock generator 10 + 0x400 + + + GCLK11 + Generic clock generator 11 + 0x800 + + + + + GENCTRL9 + Generic Clock Generator Control 9 Synchronization Busy bits + 11 + 1 + read-only + + GENCTRL9Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + GCLK9 + Generic clock generator 9 + 0x200 + + + GCLK10 + Generic clock generator 10 + 0x400 + + + GCLK11 + Generic clock generator 11 + 0x800 + + + + + GENCTRL10 + Generic Clock Generator Control 10 Synchronization Busy bits + 12 + 1 + read-only + + GENCTRL10Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + GCLK9 + Generic clock generator 9 + 0x200 + + + GCLK10 + Generic clock generator 10 + 0x400 + + + GCLK11 + Generic clock generator 11 + 0x800 + + + + + GENCTRL11 + Generic Clock Generator Control 11 Synchronization Busy bits + 13 + 1 + read-only + + GENCTRL11Select + + GCLK0 + Generic clock generator 0 + 0x1 + + + GCLK1 + Generic clock generator 1 + 0x2 + + + GCLK2 + Generic clock generator 2 + 0x4 + + + GCLK3 + Generic clock generator 3 + 0x8 + + + GCLK4 + Generic clock generator 4 + 0x10 + + + GCLK5 + Generic clock generator 5 + 0x20 + + + GCLK6 + Generic clock generator 6 + 0x40 + + + GCLK7 + Generic clock generator 7 + 0x80 + + + GCLK8 + Generic clock generator 8 + 0x100 + + + GCLK9 + Generic clock generator 9 + 0x200 + + + GCLK10 + Generic clock generator 10 + 0x400 + + + GCLK11 + Generic clock generator 11 + 0x800 + + + + + + + 12 + 0x4 + GENCTRL%s + Generic Clock Generator Control + 0x20 + 32 + + + SRC + Source Select + 0 + 4 + + SRCSelect + + XOSC0 + XOSC0 oscillator output + 0x0 + + + XOSC1 + XOSC1 oscillator output + 0x1 + + + GCLKIN + Generator input pad + 0x2 + + + GCLKGEN1 + Generic clock generator 1 output + 0x3 + + + OSCULP32K + OSCULP32K oscillator output + 0x4 + + + XOSC32K + XOSC32K oscillator output + 0x5 + + + DFLL + DFLL output + 0x6 + + + DPLL0 + DPLL0 output + 0x7 + + + DPLL1 + DPLL1 output + 0x8 + + + + + GENEN + Generic Clock Generator Enable + 8 + 1 + + + IDC + Improve Duty Cycle + 9 + 1 + + + OOV + Output Off Value + 10 + 1 + + + OE + Output Enable + 11 + 1 + + + DIVSEL + Divide Selection + 12 + 1 + + + RUNSTDBY + Run in Standby + 13 + 1 + + + DIV + Division Factor + 16 + 16 + + + + + 48 + 0x4 + PCHCTRL%s + Peripheral Clock Control + 0x80 + 32 + + + GEN + Generic Clock Generator + 0 + 4 + + GENSelect + + GCLK0 + Generic clock generator 0 + 0x0 + + + GCLK1 + Generic clock generator 1 + 0x1 + + + GCLK2 + Generic clock generator 2 + 0x2 + + + GCLK3 + Generic clock generator 3 + 0x3 + + + GCLK4 + Generic clock generator 4 + 0x4 + + + GCLK5 + Generic clock generator 5 + 0x5 + + + GCLK6 + Generic clock generator 6 + 0x6 + + + GCLK7 + Generic clock generator 7 + 0x7 + + + GCLK8 + Generic clock generator 8 + 0x8 + + + GCLK9 + Generic clock generator 9 + 0x9 + + + GCLK10 + Generic clock generator 10 + 0xa + + + GCLK11 + Generic clock generator 11 + 0xb + + + + + CHEN + Channel Enable + 6 + 1 + + + WRTLOCK + Write Lock + 7 + 1 + + + + + + + HMATRIX + 2.1.4 + HSB Matrix + HMATRIXB + HMATRIXB_ + 0x4100C000 + + 0 + 0x180 + registers + + + + 5 + 0x8 + PRAS%s + Priority A for Slave + 0x080 + 32 + + + 5 + 0x8 + PRBS%s + Priority B for Slave + 0x084 + 32 + + + + + ICM + 1.2.0 + Integrity Check Monitor + ICM + ICM_ + 0x42002C00 + + 0 + 0x80 + registers + + + ICM_INTREQ + 132 + + + + CFG + Configuration + 0x00 + 32 + + + WBDIS + Write Back Disable + 0 + 1 + + + EOMDIS + End of Monitoring Disable + 1 + 1 + + + SLBDIS + Secondary List Branching Disable + 2 + 1 + + + BBC + Bus Burden Control + 4 + 4 + + + ASCD + Automatic Switch To Compare Digest + 8 + 1 + + + DUALBUFF + Dual Input Buffer + 9 + 1 + + + UIHASH + User Initial Hash Value + 12 + 1 + + + UALGO + User SHA Algorithm + 13 + 3 + + UALGOSelect + + SHA1 + SHA1 Algorithm + 0x0 + + + SHA256 + SHA256 Algorithm + 0x1 + + + SHA224 + SHA224 Algorithm + 0x4 + + + + + HAPROT + Region Hash Area Protection + 16 + 6 + + + DAPROT + Region Descriptor Area Protection + 24 + 6 + + + + + CTRL + Control + 0x04 + 32 + write-only + + + ENABLE + ICM Enable + 0 + 1 + + + DISABLE + ICM Disable Register + 1 + 1 + + + SWRST + Software Reset + 2 + 1 + + + REHASH + Recompute Internal Hash + 4 + 4 + + + RMDIS + Region Monitoring Disable + 8 + 4 + + + RMEN + Region Monitoring Enable + 12 + 4 + + + + + SR + Status + 0x08 + 32 + read-only + + + ENABLE + ICM Controller Enable Register + 0 + 1 + + + RAWRMDIS + RAW Region Monitoring Disabled Status + 8 + 4 + + + RMDIS + Region Monitoring Disabled Status + 12 + 4 + + + + + IER + Interrupt Enable + 0x10 + 32 + write-only + + + RHC + Region Hash Completed Interrupt Enable + 0 + 4 + + + RDM + Region Digest Mismatch Interrupt Enable + 4 + 4 + + + RBE + Region Bus Error Interrupt Enable + 8 + 4 + + + RWC + Region Wrap Condition detected Interrupt Enable + 12 + 4 + + + REC + Region End bit Condition Detected Interrupt Enable + 16 + 4 + + + RSU + Region Status Updated Interrupt Disable + 20 + 4 + + + URAD + Undefined Register Access Detection Interrupt Enable + 24 + 1 + + + + + IDR + Interrupt Disable + 0x14 + 32 + write-only + + + RHC + Region Hash Completed Interrupt Disable + 0 + 4 + + + RDM + Region Digest Mismatch Interrupt Disable + 4 + 4 + + + RBE + Region Bus Error Interrupt Disable + 8 + 4 + + + RWC + Region Wrap Condition Detected Interrupt Disable + 12 + 4 + + + REC + Region End bit Condition detected Interrupt Disable + 16 + 4 + + + RSU + Region Status Updated Interrupt Disable + 20 + 4 + + + URAD + Undefined Register Access Detection Interrupt Disable + 24 + 1 + + + + + IMR + Interrupt Mask + 0x18 + 32 + read-only + + + RHC + Region Hash Completed Interrupt Mask + 0 + 4 + + + RDM + Region Digest Mismatch Interrupt Mask + 4 + 4 + + + RBE + Region Bus Error Interrupt Mask + 8 + 4 + + + RWC + Region Wrap Condition Detected Interrupt Mask + 12 + 4 + + + REC + Region End bit Condition Detected Interrupt Mask + 16 + 4 + + + RSU + Region Status Updated Interrupt Mask + 20 + 4 + + + URAD + Undefined Register Access Detection Interrupt Mask + 24 + 1 + + + + + ISR + Interrupt Status + 0x1C + 32 + read-only + + + RHC + Region Hash Completed + 0 + 4 + + + RDM + Region Digest Mismatch + 4 + 4 + + + RBE + Region Bus Error + 8 + 4 + + + RWC + Region Wrap Condition Detected + 12 + 4 + + + REC + Region End bit Condition Detected + 16 + 4 + + + RSU + Region Status Updated Detected + 20 + 4 + + + URAD + Undefined Register Access Detection Status + 24 + 1 + + + + + UASR + Undefined Access Status + 0x20 + 32 + read-only + + + URAT + Undefined Register Access Trace + 0 + 3 + + URATSelect + + UNSPEC_STRUCT_MEMBER + Unspecified structure member set to one detected when the descriptor is loaded + 0x0 + + + CFG_MODIFIED + CFG modified during active monitoring + 0x1 + + + DSCR_MODIFIED + DSCR modified during active monitoring + 0x2 + + + HASH_MODIFIED + HASH modified during active monitoring + 0x3 + + + READ_ACCESS + Write-only register read access + 0x4 + + + + + + + DSCR + Region Descriptor Area Start Address + 0x30 + 32 + + + DASA + Descriptor Area Start Address + 6 + 26 + + + + + HASH + Region Hash Area Start Address + 0x34 + 32 + + + HASA + Hash Area Start Address + 7 + 25 + + + + + 8 + 0x4 + UIHVAL%s + User Initial Hash Value n + 0x38 + 32 + write-only + + + VAL + Initial Hash Value + 0 + 32 + + + + + + + I2S + 2.0.0 + Inter-IC Sound Interface + I2S + I2S_ + 0x43002800 + + 0 + 0x40 + registers + + + I2S_INTREQ + 128 + + + + CTRLA + Control A + 0x00 + 8 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable + 3 + 1 + + + TXEN + Tx Serializer Enable + 4 + 1 + + + RXEN + Rx Serializer Enable + 5 + 1 + + + + + 2 + 0x4 + CLKCTRL%s + Clock Unit n Control + 0x04 + 32 + + + SLOTSIZE + Slot Size + 0 + 2 + + SLOTSIZESelect + + 8 + 8-bit Slot for Clock Unit n + 0x0 + + + 16 + 16-bit Slot for Clock Unit n + 0x1 + + + 24 + 24-bit Slot for Clock Unit n + 0x2 + + + 32 + 32-bit Slot for Clock Unit n + 0x3 + + + + + NBSLOTS + Number of Slots in Frame + 2 + 3 + + + FSWIDTH + Frame Sync Width + 5 + 2 + + FSWIDTHSelect + + SLOT + Frame Sync Pulse is 1 Slot wide (default for I2S protocol) + 0x0 + + + HALF + Frame Sync Pulse is half a Frame wide + 0x1 + + + BIT + Frame Sync Pulse is 1 Bit wide + 0x2 + + + BURST + Clock Unit n operates in Burst mode, with a 1-bit wide Frame Sync pulse per Data sample, only when Data transfer is requested + 0x3 + + + + + BITDELAY + Data Delay from Frame Sync + 7 + 1 + + BITDELAYSelect + + LJ + Left Justified (0 Bit Delay) + 0x0 + + + I2S + I2S (1 Bit Delay) + 0x1 + + + + + FSSEL + Frame Sync Select + 8 + 1 + + FSSELSelect + + SCKDIV + Divided Serial Clock n is used as Frame Sync n source + 0x0 + + + FSPIN + FSn input pin is used as Frame Sync n source + 0x1 + + + + + FSINV + Frame Sync Invert + 9 + 1 + + + FSOUTINV + Frame Sync Output Invert + 10 + 1 + + + SCKSEL + Serial Clock Select + 11 + 1 + + SCKSELSelect + + MCKDIV + Divided Master Clock n is used as Serial Clock n source + 0x0 + + + SCKPIN + SCKn input pin is used as Serial Clock n source + 0x1 + + + + + SCKOUTINV + Serial Clock Output Invert + 12 + 1 + + + MCKSEL + Master Clock Select + 13 + 1 + + MCKSELSelect + + GCLK + GCLK_I2S_n is used as Master Clock n source + 0x0 + + + MCKPIN + MCKn input pin is used as Master Clock n source + 0x1 + + + + + MCKEN + Master Clock Enable + 14 + 1 + + + MCKOUTINV + Master Clock Output Invert + 15 + 1 + + + MCKDIV + Master Clock Division Factor + 16 + 6 + + + MCKOUTDIV + Master Clock Output Division Factor + 24 + 6 + + + + + INTENCLR + Interrupt Enable Clear + 0x0C + 16 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x10 + 16 + + + RXRDY0 + Receive Ready 0 Interrupt Enable + 0 + 1 + + + RXRDY1 + Receive Ready 1 Interrupt Enable + 1 + 1 + + + RXOR0 + Receive Overrun 0 Interrupt Enable + 4 + 1 + + + RXOR1 + Receive Overrun 1 Interrupt Enable + 5 + 1 + + + TXRDY0 + Transmit Ready 0 Interrupt Enable + 8 + 1 + + + TXRDY1 + Transmit Ready 1 Interrupt Enable + 9 + 1 + + + TXUR0 + Transmit Underrun 0 Interrupt Enable + 12 + 1 + + + TXUR1 + Transmit Underrun 1 Interrupt Enable + 13 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x14 + 16 + + + RXRDY0 + Receive Ready 0 + 0 + 1 + + + RXRDY1 + Receive Ready 1 + 1 + 1 + + + RXOR0 + Receive Overrun 0 + 4 + 1 + + + RXOR1 + Receive Overrun 1 + 5 + 1 + + + TXRDY0 + Transmit Ready 0 + 8 + 1 + + + TXRDY1 + Transmit Ready 1 + 9 + 1 + + + TXUR0 + Transmit Underrun 0 + 12 + 1 + + + TXUR1 + Transmit Underrun 1 + 13 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x18 + 16 + read-only + + + SWRST + Software Reset Synchronization Status + 0 + 1 + + + ENABLE + Enable Synchronization Status + 1 + 1 + + + CKEN0 + Clock Unit 0 Enable Synchronization Status + 2 + 1 + + + CKEN1 + Clock Unit 1 Enable Synchronization Status + 3 + 1 + + + TXEN + Tx Serializer Enable Synchronization Status + 4 + 1 + + + RXEN + Rx Serializer Enable Synchronization Status + 5 + 1 + + + TXDATA + Tx Data Synchronization Status + 8 + 1 + + + RXDATA + Rx Data Synchronization Status + 9 + 1 + + + + + TXCTRL + Tx Serializer Control + 0x20 + 32 + + + TXDEFAULT + Line Default Line when Slot Disabled + 2 + 2 + + TXDEFAULTSelect + + ZERO + Output Default Value is 0 + 0x0 + + + ONE + Output Default Value is 1 + 0x1 + + + HIZ + Output Default Value is high impedance + 0x3 + + + + + TXSAME + Transmit Data when Underrun + 4 + 1 + + TXSAMESelect + + ZERO + Zero data transmitted in case of underrun + 0x0 + + + SAME + Last data transmitted in case of underrun + 0x1 + + + + + SLOTADJ + Data Slot Formatting Adjust + 7 + 1 + + SLOTADJSelect + + RIGHT + Data is right adjusted in slot + 0x0 + + + LEFT + Data is left adjusted in slot + 0x1 + + + + + DATASIZE + Data Word Size + 8 + 3 + + DATASIZESelect + + 32 + 32 bits + 0x0 + + + 24 + 24 bits + 0x1 + + + 20 + 20 bits + 0x2 + + + 18 + 18 bits + 0x3 + + + 16 + 16 bits + 0x4 + + + 16C + 16 bits compact stereo + 0x5 + + + 8 + 8 bits + 0x6 + + + 8C + 8 bits compact stereo + 0x7 + + + + + WORDADJ + Data Word Formatting Adjust + 12 + 1 + + WORDADJSelect + + RIGHT + Data is right adjusted in word + 0x0 + + + LEFT + Data is left adjusted in word + 0x1 + + + + + EXTEND + Data Formatting Bit Extension + 13 + 2 + + EXTENDSelect + + ZERO + Extend with zeroes + 0x0 + + + ONE + Extend with ones + 0x1 + + + MSBIT + Extend with Most Significant Bit + 0x2 + + + LSBIT + Extend with Least Significant Bit + 0x3 + + + + + BITREV + Data Formatting Bit Reverse + 15 + 1 + + BITREVSelect + + MSBIT + Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) + 0x0 + + + LSBIT + Transfer Data Least Significant Bit (LSB) first + 0x1 + + + + + SLOTDIS0 + Slot 0 Disabled for this Serializer + 16 + 1 + + + SLOTDIS1 + Slot 1 Disabled for this Serializer + 17 + 1 + + + SLOTDIS2 + Slot 2 Disabled for this Serializer + 18 + 1 + + + SLOTDIS3 + Slot 3 Disabled for this Serializer + 19 + 1 + + + SLOTDIS4 + Slot 4 Disabled for this Serializer + 20 + 1 + + + SLOTDIS5 + Slot 5 Disabled for this Serializer + 21 + 1 + + + SLOTDIS6 + Slot 6 Disabled for this Serializer + 22 + 1 + + + SLOTDIS7 + Slot 7 Disabled for this Serializer + 23 + 1 + + + MONO + Mono Mode + 24 + 1 + + MONOSelect + + STEREO + Normal mode + 0x0 + + + MONO + Left channel data is duplicated to right channel + 0x1 + + + + + DMA + Single or Multiple DMA Channels + 25 + 1 + + DMASelect + + SINGLE + Single DMA channel + 0x0 + + + MULTIPLE + One DMA channel per data channel + 0x1 + + + + + + + RXCTRL + Rx Serializer Control + 0x24 + 32 + + + SERMODE + Serializer Mode + 0 + 2 + + SERMODESelect + + RX + Receive + 0x0 + + + PDM2 + Receive one PDM data on each serial clock edge + 0x2 + + + + + CLKSEL + Clock Unit Selection + 5 + 1 + + CLKSELSelect + + CLK0 + Use Clock Unit 0 + 0x0 + + + CLK1 + Use Clock Unit 1 + 0x1 + + + + + SLOTADJ + Data Slot Formatting Adjust + 7 + 1 + + SLOTADJSelect + + RIGHT + Data is right adjusted in slot + 0x0 + + + LEFT + Data is left adjusted in slot + 0x1 + + + + + DATASIZE + Data Word Size + 8 + 3 + + DATASIZESelect + + 32 + 32 bits + 0x0 + + + 24 + 24 bits + 0x1 + + + 20 + 20 bits + 0x2 + + + 18 + 18 bits + 0x3 + + + 16 + 16 bits + 0x4 + + + 16C + 16 bits compact stereo + 0x5 + + + 8 + 8 bits + 0x6 + + + 8C + 8 bits compact stereo + 0x7 + + + + + WORDADJ + Data Word Formatting Adjust + 12 + 1 + + WORDADJSelect + + RIGHT + Data is right adjusted in word + 0x0 + + + LEFT + Data is left adjusted in word + 0x1 + + + + + EXTEND + Data Formatting Bit Extension + 13 + 2 + + EXTENDSelect + + ZERO + Extend with zeroes + 0x0 + + + ONE + Extend with ones + 0x1 + + + MSBIT + Extend with Most Significant Bit + 0x2 + + + LSBIT + Extend with Least Significant Bit + 0x3 + + + + + BITREV + Data Formatting Bit Reverse + 15 + 1 + + BITREVSelect + + MSBIT + Transfer Data Most Significant Bit (MSB) first (default for I2S protocol) + 0x0 + + + LSBIT + Transfer Data Least Significant Bit (LSB) first + 0x1 + + + + + SLOTDIS0 + Slot 0 Disabled for this Serializer + 16 + 1 + + + SLOTDIS1 + Slot 1 Disabled for this Serializer + 17 + 1 + + + SLOTDIS2 + Slot 2 Disabled for this Serializer + 18 + 1 + + + SLOTDIS3 + Slot 3 Disabled for this Serializer + 19 + 1 + + + SLOTDIS4 + Slot 4 Disabled for this Serializer + 20 + 1 + + + SLOTDIS5 + Slot 5 Disabled for this Serializer + 21 + 1 + + + SLOTDIS6 + Slot 6 Disabled for this Serializer + 22 + 1 + + + SLOTDIS7 + Slot 7 Disabled for this Serializer + 23 + 1 + + + MONO + Mono Mode + 24 + 1 + + MONOSelect + + STEREO + Normal mode + 0x0 + + + MONO + Left channel data is duplicated to right channel + 0x1 + + + + + DMA + Single or Multiple DMA Channels + 25 + 1 + + DMASelect + + SINGLE + Single DMA channel + 0x0 + + + MULTIPLE + One DMA channel per data channel + 0x1 + + + + + RXLOOP + Loop-back Test Mode + 26 + 1 + + + + + TXDATA + Tx Data + 0x30 + 32 + write-only + + + DATA + Sample Data + 0 + 32 + + + + + RXDATA + Rx Data + 0x34 + 32 + read-only + + + DATA + Sample Data + 0 + 32 + + + + + + + MCLK + 1.0.0 + Main Clock + MCLK + MCLK_ + 0x40000800 + + 0 + 0x80 + registers + + + MCLK_INTREQ + 1 + + + + INTENCLR + Interrupt Enable Clear + 0x01 + 8 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x02 + 8 + + + CKRDY + Clock Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x03 + 8 + 0x01 + + + CKRDY + Clock Ready + 0 + 1 + + + + + HSDIV + HS Clock Division + 0x04 + 8 + read-only + 0x01 + + + DIV + CPU Clock Division Factor + 0 + 8 + + DIVSelect + + DIV1 + Divide by 1 + 0x1 + + + + + + + CPUDIV + CPU Clock Division + 0x05 + 8 + 0x01 + + + DIV + Low-Power Clock Division Factor + 0 + 8 + + DIVSelect + + DIV1 + Divide by 1 + 0x1 + + + DIV2 + Divide by 2 + 0x2 + + + DIV4 + Divide by 4 + 0x4 + + + DIV8 + Divide by 8 + 0x8 + + + DIV16 + Divide by 16 + 0x10 + + + DIV32 + Divide by 32 + 0x20 + + + DIV64 + Divide by 64 + 0x40 + + + DIV128 + Divide by 128 + 0x80 + + + + + + + AHBMASK + AHB Mask + 0x10 + 32 + 0x00FFFFFF + + + HPB0_ + HPB0 AHB Clock Mask + 0 + 1 + + + HPB1_ + HPB1 AHB Clock Mask + 1 + 1 + + + HPB2_ + HPB2 AHB Clock Mask + 2 + 1 + + + HPB3_ + HPB3 AHB Clock Mask + 3 + 1 + + + DSU_ + DSU AHB Clock Mask + 4 + 1 + + + HMATRIX_ + HMATRIX AHB Clock Mask + 5 + 1 + + + NVMCTRL_ + NVMCTRL AHB Clock Mask + 6 + 1 + + + HSRAM_ + HSRAM AHB Clock Mask + 7 + 1 + + + CMCC_ + CMCC AHB Clock Mask + 8 + 1 + + + DMAC_ + DMAC AHB Clock Mask + 9 + 1 + + + USB_ + USB AHB Clock Mask + 10 + 1 + + + BKUPRAM_ + BKUPRAM AHB Clock Mask + 11 + 1 + + + PAC_ + PAC AHB Clock Mask + 12 + 1 + + + QSPI_ + QSPI AHB Clock Mask + 13 + 1 + + + SDHC0_ + SDHC0 AHB Clock Mask + 15 + 1 + + + ICM_ + ICM AHB Clock Mask + 19 + 1 + + + PUKCC_ + PUKCC AHB Clock Mask + 20 + 1 + + + QSPI_2X_ + QSPI_2X AHB Clock Mask + 21 + 1 + + + NVMCTRL_SMEEPROM_ + NVMCTRL_SMEEPROM AHB Clock Mask + 22 + 1 + + + NVMCTRL_CACHE_ + NVMCTRL_CACHE AHB Clock Mask + 23 + 1 + + + + + APBAMASK + APBA Mask + 0x14 + 32 + 0x000007FF + + + PAC_ + PAC APB Clock Enable + 0 + 1 + + + PM_ + PM APB Clock Enable + 1 + 1 + + + MCLK_ + MCLK APB Clock Enable + 2 + 1 + + + RSTC_ + RSTC APB Clock Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Clock Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Clock Enable + 5 + 1 + + + SUPC_ + SUPC APB Clock Enable + 6 + 1 + + + GCLK_ + GCLK APB Clock Enable + 7 + 1 + + + WDT_ + WDT APB Clock Enable + 8 + 1 + + + RTC_ + RTC APB Clock Enable + 9 + 1 + + + EIC_ + EIC APB Clock Enable + 10 + 1 + + + FREQM_ + FREQM APB Clock Enable + 11 + 1 + + + SERCOM0_ + SERCOM0 APB Clock Enable + 12 + 1 + + + SERCOM1_ + SERCOM1 APB Clock Enable + 13 + 1 + + + TC0_ + TC0 APB Clock Enable + 14 + 1 + + + TC1_ + TC1 APB Clock Enable + 15 + 1 + + + + + APBBMASK + APBB Mask + 0x18 + 32 + 0x00018056 + + + USB_ + USB APB Clock Enable + 0 + 1 + + + DSU_ + DSU APB Clock Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Clock Enable + 2 + 1 + + + PORT_ + PORT APB Clock Enable + 4 + 1 + + + HMATRIX_ + HMATRIX APB Clock Enable + 6 + 1 + + + EVSYS_ + EVSYS APB Clock Enable + 7 + 1 + + + SERCOM2_ + SERCOM2 APB Clock Enable + 9 + 1 + + + SERCOM3_ + SERCOM3 APB Clock Enable + 10 + 1 + + + TCC0_ + TCC0 APB Clock Enable + 11 + 1 + + + TCC1_ + TCC1 APB Clock Enable + 12 + 1 + + + TC2_ + TC2 APB Clock Enable + 13 + 1 + + + TC3_ + TC3 APB Clock Enable + 14 + 1 + + + TAL_ + TAL APB Clock Enable + 15 + 1 + + + RAMECC_ + RAMECC APB Clock Enable + 16 + 1 + + + + + APBCMASK + APBC Mask + 0x1C + 32 + 0x00002000 + + + TCC2_ + TCC2 APB Clock Enable + 3 + 1 + + + TCC3_ + TCC3 APB Clock Enable + 4 + 1 + + + TC4_ + TC4 APB Clock Enable + 5 + 1 + + + TC5_ + TC5 APB Clock Enable + 6 + 1 + + + PDEC_ + PDEC APB Clock Enable + 7 + 1 + + + AC_ + AC APB Clock Enable + 8 + 1 + + + AES_ + AES APB Clock Enable + 9 + 1 + + + TRNG_ + TRNG APB Clock Enable + 10 + 1 + + + ICM_ + ICM APB Clock Enable + 11 + 1 + + + QSPI_ + QSPI APB Clock Enable + 13 + 1 + + + CCL_ + CCL APB Clock Enable + 14 + 1 + + + + + APBDMASK + APBD Mask + 0x20 + 32 + + + SERCOM4_ + SERCOM4 APB Clock Enable + 0 + 1 + + + SERCOM5_ + SERCOM5 APB Clock Enable + 1 + 1 + + + TCC4_ + TCC4 APB Clock Enable + 4 + 1 + + + ADC0_ + ADC0 APB Clock Enable + 7 + 1 + + + ADC1_ + ADC1 APB Clock Enable + 8 + 1 + + + DAC_ + DAC APB Clock Enable + 9 + 1 + + + I2S_ + I2S APB Clock Enable + 10 + 1 + + + PCC_ + PCC APB Clock Enable + 11 + 1 + + + + + + + NVMCTRL + 1.0.0 + Non-Volatile Memory Controller + NVMCTRL + NVMCTRL_ + 0x41004000 + + 0 + 0x80 + registers + + + NVMCTRL_INTREQ_0 + 29 + + + NVMCTRL_INTREQ_1 + 30 + + + + CTRLA + Control A + 0x00 + 16 + 0x0004 + + + AUTOWS + Auto Wait State Enable + 2 + 1 + + + SUSPEN + Suspend Enable + 3 + 1 + + + WMODE + Write Mode + 4 + 2 + + WMODESelect + + MAN + Manual Write + 0x0 + + + ADW + Automatic Double Word Write + 0x1 + + + AQW + Automatic Quad Word + 0x2 + + + AP + Automatic Page Write + 0x3 + + + + + PRM + Power Reduction Mode during Sleep + 6 + 2 + + PRMSelect + + SEMIAUTO + NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. + 0x0 + + + FULLAUTO + NVM block enters low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode when system is not in standby mode. + 0x1 + + + MANUAL + NVM block does not enter low-power mode when entering standby mode. NVM block enters low-power mode when SPRM command is issued. NVM block exits low-power mode upon first access. + 0x3 + + + + + RWS + NVM Read Wait States + 8 + 4 + + + AHBNS0 + Force AHB0 access to NONSEQ, burst transfers are continuously rearbitrated + 12 + 1 + + + AHBNS1 + Force AHB1 access to NONSEQ, burst transfers are continuously rearbitrated + 13 + 1 + + + CACHEDIS0 + AHB0 Cache Disable + 14 + 1 + + + CACHEDIS1 + AHB1 Cache Disable + 15 + 1 + + + + + CTRLB + Control B + 0x04 + 16 + write-only + + + CMD + Command + 0 + 7 + write-only + + CMDSelect + + EP + Erase Page - Only supported in the USER and AUX pages. + 0x0 + + + EB + Erase Block - Erases the block addressed by the ADDR register, not supported in the user page + 0x1 + + + WP + Write Page - Writes the contents of the page buffer to the page addressed by the ADDR register, not supported in the user page + 0x3 + + + WQW + Write Quad Word - Writes a 128-bit word at the location addressed by the ADDR register. + 0x4 + + + SWRST + Software Reset - Power-Cycle the NVM memory and replay the device automatic calibration procedure and resets the module configuration registers + 0x10 + + + LR + Lock Region - Locks the region containing the address location in the ADDR register. + 0x11 + + + UR + Unlock Region - Unlocks the region containing the address location in the ADDR register. + 0x12 + + + SPRM + Sets the power reduction mode. + 0x13 + + + CPRM + Clears the power reduction mode. + 0x14 + + + PBC + Page Buffer Clear - Clears the page buffer. + 0x15 + + + SSB + Set Security Bit + 0x16 + + + BKSWRST + Bank swap and system reset, if SMEE is used also reallocate SMEE data into the opposite BANK + 0x17 + + + CELCK + Chip Erase Lock - DSU.CE command is not available + 0x18 + + + CEULCK + Chip Erase Unlock - DSU.CE command is available + 0x19 + + + SBPDIS + Sets STATUS.BPDIS, Boot loader protection is discarded until CBPDIS is issued or next start-up sequence + 0x1a + + + CBPDIS + Clears STATUS.BPDIS, Boot loader protection is not discarded + 0x1b + + + ASEES0 + Activate SmartEEPROM Sector 0, deactivate Sector 1 + 0x30 + + + ASEES1 + Activate SmartEEPROM Sector 1, deactivate Sector 0 + 0x31 + + + SEERALOC + Starts SmartEEPROM sector reallocation algorithm + 0x32 + + + SEEFLUSH + Flush SMEE data when in buffered mode + 0x33 + + + LSEE + Lock access to SmartEEPROM data from any mean + 0x34 + + + USEE + Unlock access to SmartEEPROM data + 0x35 + + + LSEER + Lock access to the SmartEEPROM Register Address Space (above 64KB) + 0x36 + + + USEER + Unlock access to the SmartEEPROM Register Address Space (above 64KB) + 0x37 + + + + + CMDEX + Command Execution + 8 + 8 + write-only + + CMDEXSelect + + KEY + Execution Key + 0xa5 + + + + + + + PARAM + NVM Parameter + 0x08 + 32 + read-only + 0x00060000 + + + NVMP + NVM Pages + 0 + 16 + read-only + + + PSZ + Page Size + 16 + 3 + read-only + + PSZSelect + + 8 + 8 bytes + 0x0 + + + 16 + 16 bytes + 0x1 + + + 32 + 32 bytes + 0x2 + + + 64 + 64 bytes + 0x3 + + + 128 + 128 bytes + 0x4 + + + 256 + 256 bytes + 0x5 + + + 512 + 512 bytes + 0x6 + + + 1024 + 1024 bytes + 0x7 + + + + + SEE + SmartEEPROM Supported + 31 + 1 + read-only + + + + + INTENCLR + Interrupt Enable Clear + 0x0C + 16 + + + DONE + Command Done Interrupt Clear + 0 + 1 + + + ADDRE + Address Error + 1 + 1 + + + PROGE + Programming Error Interrupt Clear + 2 + 1 + + + LOCKE + Lock Error Interrupt Clear + 3 + 1 + + + ECCSE + ECC Single Error Interrupt Clear + 4 + 1 + + + ECCDE + ECC Dual Error Interrupt Clear + 5 + 1 + + + NVME + NVM Error Interrupt Clear + 6 + 1 + + + SUSP + Suspended Write Or Erase Interrupt Clear + 7 + 1 + + + SEESFULL + Active SEES Full Interrupt Clear + 8 + 1 + + + SEESOVF + Active SEES Overflow Interrupt Clear + 9 + 1 + + + SEEWRC + SEE Write Completed Interrupt Clear + 10 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x0E + 16 + + + DONE + Command Done Interrupt Enable + 0 + 1 + + + ADDRE + Address Error Interrupt Enable + 1 + 1 + + + PROGE + Programming Error Interrupt Enable + 2 + 1 + + + LOCKE + Lock Error Interrupt Enable + 3 + 1 + + + ECCSE + ECC Single Error Interrupt Enable + 4 + 1 + + + ECCDE + ECC Dual Error Interrupt Enable + 5 + 1 + + + NVME + NVM Error Interrupt Enable + 6 + 1 + + + SUSP + Suspended Write Or Erase Interrupt Enable + 7 + 1 + + + SEESFULL + Active SEES Full Interrupt Enable + 8 + 1 + + + SEESOVF + Active SEES Overflow Interrupt Enable + 9 + 1 + + + SEEWRC + SEE Write Completed Interrupt Enable + 10 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x10 + 16 + + + DONE + Command Done + 0 + 1 + + + ADDRE + Address Error + 1 + 1 + + + PROGE + Programming Error + 2 + 1 + + + LOCKE + Lock Error + 3 + 1 + + + ECCSE + ECC Single Error + 4 + 1 + read-only + + + ECCDE + ECC Dual Error + 5 + 1 + read-only + + + NVME + NVM Error + 6 + 1 + + + SUSP + Suspended Write Or Erase Operation + 7 + 1 + + + SEESFULL + Active SEES Full + 8 + 1 + + + SEESOVF + Active SEES Overflow + 9 + 1 + + + SEEWRC + SEE Write Completed + 10 + 1 + + + + + STATUS + Status + 0x12 + 16 + read-only + + + READY + Ready to accept a command + 0 + 1 + read-only + + + PRM + Power Reduction Mode + 1 + 1 + read-only + + + LOAD + NVM Page Buffer Active Loading + 2 + 1 + read-only + + + SUSP + NVM Write Or Erase Operation Is Suspended + 3 + 1 + read-only + + + AFIRST + BANKA First + 4 + 1 + read-only + + + BPDIS + Boot Loader Protection Disable + 5 + 1 + read-only + + + BOOTPROT + Boot Loader Protection Size + 8 + 4 + read-only + + + + + ADDR + Address + 0x14 + 32 + + + ADDR + NVM Address + 0 + 24 + + + + + RUNLOCK + Lock Section + 0x18 + 32 + read-only + + + RUNLOCK + Region Un-Lock Bits + 0 + 32 + read-only + + + + + 2 + 0x4 + PBLDATA%s + Page Buffer Load Data x + 0x1C + 32 + read-only + 0xFFFFFFFF + + + DATA + Page Buffer Data + 0 + 32 + read-only + + + + + ECCERR + ECC Error Status Register + 0x24 + 32 + read-only + + + ADDR + Error Address + 0 + 24 + read-only + + + TYPEL + Low Double-Word Error Type + 28 + 2 + read-only + + TYPELSelect + + None + No Error Detected Since Last Read + 0x0 + + + Single + At Least One Single Error Detected Since last Read + 0x1 + + + Dual + At Least One Dual Error Detected Since Last Read + 0x2 + + + + + TYPEH + High Double-Word Error Type + 30 + 2 + read-only + + TYPEHSelect + + None + No Error Detected Since Last Read + 0x0 + + + Single + At Least One Single Error Detected Since last Read + 0x1 + + + Dual + At Least One Dual Error Detected Since Last Read + 0x2 + + + + + + + DBGCTRL + Debug Control + 0x28 + 8 + + + ECCDIS + Debugger ECC Read Disable + 0 + 1 + + + ECCELOG + Debugger ECC Error Tracking Mode + 1 + 1 + + + + + SEECFG + SmartEEPROM Configuration Register + 0x2A + 8 + + + WMODE + Write Mode + 0 + 1 + + WMODESelect + + UNBUFFERED + A NVM write command is issued after each write in the pagebuffer + 0x0 + + + BUFFERED + A NVM write command is issued when a write to a new page is requested + 0x1 + + + + + APRDIS + Automatic Page Reallocation Disable + 1 + 1 + + + + + SEESTAT + SmartEEPROM Status Register + 0x2C + 32 + read-only + + + ASEES + Active SmartEEPROM Sector + 0 + 1 + read-only + + + LOAD + Page Buffer Loaded + 1 + 1 + read-only + + + BUSY + Busy + 2 + 1 + read-only + + + LOCK + SmartEEPROM Write Access Is Locked + 3 + 1 + read-only + + + RLOCK + SmartEEPROM Write Access To Register Address Space Is Locked + 4 + 1 + read-only + + + SBLK + Blocks Number In a Sector + 8 + 4 + read-only + + + PSZ + SmartEEPROM Page Size + 16 + 3 + read-only + + + + + + + OSCCTRL + 1.0.0 + Oscillators Control + OSCCTRL + OSCCTRL_ + 0x40001000 + + 0 + 0x100 + registers + + + OSCCTRL_INTREQ_0 + 2 + + + OSCCTRL_INTREQ_1 + 3 + + + OSCCTRL_INTREQ_2 + 4 + + + OSCCTRL_INTREQ_3 + 5 + + + OSCCTRL_INTREQ_4 + 6 + + + + EVCTRL + Event Control + 0x00 + 8 + + + CFDEO0 + Clock 0 Failure Detector Event Output Enable + 0 + 1 + + + CFDEO1 + Clock 1 Failure Detector Event Output Enable + 1 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x04 + 32 + + + XOSCRDY0 + XOSC 0 Ready Interrupt Enable + 0 + 1 + + + XOSCRDY1 + XOSC 1 Ready Interrupt Enable + 1 + 1 + + + XOSCFAIL0 + XOSC 0 Clock Failure Detector Interrupt Enable + 2 + 1 + + + XOSCFAIL1 + XOSC 1 Clock Failure Detector Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 8 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 9 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 10 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 11 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 12 + 1 + + + DPLL0LCKR + DPLL0 Lock Rise Interrupt Enable + 16 + 1 + + + DPLL0LCKF + DPLL0 Lock Fall Interrupt Enable + 17 + 1 + + + DPLL0LTO + DPLL0 Lock Timeout Interrupt Enable + 18 + 1 + + + DPLL0LDRTO + DPLL0 Loop Divider Ratio Update Complete Interrupt Enable + 19 + 1 + + + DPLL1LCKR + DPLL1 Lock Rise Interrupt Enable + 24 + 1 + + + DPLL1LCKF + DPLL1 Lock Fall Interrupt Enable + 25 + 1 + + + DPLL1LTO + DPLL1 Lock Timeout Interrupt Enable + 26 + 1 + + + DPLL1LDRTO + DPLL1 Loop Divider Ratio Update Complete Interrupt Enable + 27 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x08 + 32 + + + XOSCRDY0 + XOSC 0 Ready Interrupt Enable + 0 + 1 + + + XOSCRDY1 + XOSC 1 Ready Interrupt Enable + 1 + 1 + + + XOSCFAIL0 + XOSC 0 Clock Failure Detector Interrupt Enable + 2 + 1 + + + XOSCFAIL1 + XOSC 1 Clock Failure Detector Interrupt Enable + 3 + 1 + + + DFLLRDY + DFLL Ready Interrupt Enable + 8 + 1 + + + DFLLOOB + DFLL Out Of Bounds Interrupt Enable + 9 + 1 + + + DFLLLCKF + DFLL Lock Fine Interrupt Enable + 10 + 1 + + + DFLLLCKC + DFLL Lock Coarse Interrupt Enable + 11 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped Interrupt Enable + 12 + 1 + + + DPLL0LCKR + DPLL0 Lock Rise Interrupt Enable + 16 + 1 + + + DPLL0LCKF + DPLL0 Lock Fall Interrupt Enable + 17 + 1 + + + DPLL0LTO + DPLL0 Lock Timeout Interrupt Enable + 18 + 1 + + + DPLL0LDRTO + DPLL0 Loop Divider Ratio Update Complete Interrupt Enable + 19 + 1 + + + DPLL1LCKR + DPLL1 Lock Rise Interrupt Enable + 24 + 1 + + + DPLL1LCKF + DPLL1 Lock Fall Interrupt Enable + 25 + 1 + + + DPLL1LTO + DPLL1 Lock Timeout Interrupt Enable + 26 + 1 + + + DPLL1LDRTO + DPLL1 Loop Divider Ratio Update Complete Interrupt Enable + 27 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x0C + 32 + + + XOSCRDY0 + XOSC 0 Ready + 0 + 1 + + + XOSCRDY1 + XOSC 1 Ready + 1 + 1 + + + XOSCFAIL0 + XOSC 0 Clock Failure Detector + 2 + 1 + + + XOSCFAIL1 + XOSC 1 Clock Failure Detector + 3 + 1 + + + DFLLRDY + DFLL Ready + 8 + 1 + + + DFLLOOB + DFLL Out Of Bounds + 9 + 1 + + + DFLLLCKF + DFLL Lock Fine + 10 + 1 + + + DFLLLCKC + DFLL Lock Coarse + 11 + 1 + + + DFLLRCS + DFLL Reference Clock Stopped + 12 + 1 + + + DPLL0LCKR + DPLL0 Lock Rise + 16 + 1 + + + DPLL0LCKF + DPLL0 Lock Fall + 17 + 1 + + + DPLL0LTO + DPLL0 Lock Timeout + 18 + 1 + + + DPLL0LDRTO + DPLL0 Loop Divider Ratio Update Complete + 19 + 1 + + + DPLL1LCKR + DPLL1 Lock Rise + 24 + 1 + + + DPLL1LCKF + DPLL1 Lock Fall + 25 + 1 + + + DPLL1LTO + DPLL1 Lock Timeout + 26 + 1 + + + DPLL1LDRTO + DPLL1 Loop Divider Ratio Update Complete + 27 + 1 + + + + + STATUS + Status + 0x10 + 32 + read-only + + + XOSCRDY0 + XOSC 0 Ready + 0 + 1 + read-only + + + XOSCRDY1 + XOSC 1 Ready + 1 + 1 + read-only + + + XOSCFAIL0 + XOSC 0 Clock Failure Detector + 2 + 1 + read-only + + + XOSCFAIL1 + XOSC 1 Clock Failure Detector + 3 + 1 + read-only + + + XOSCCKSW0 + XOSC 0 Clock Switch + 4 + 1 + read-only + + + XOSCCKSW1 + XOSC 1 Clock Switch + 5 + 1 + read-only + + + DFLLRDY + DFLL Ready + 8 + 1 + read-only + + + DFLLOOB + DFLL Out Of Bounds + 9 + 1 + read-only + + + DFLLLCKF + DFLL Lock Fine + 10 + 1 + read-only + + + DFLLLCKC + DFLL Lock Coarse + 11 + 1 + read-only + + + DFLLRCS + DFLL Reference Clock Stopped + 12 + 1 + read-only + + + DPLL0LCKR + DPLL0 Lock Rise + 16 + 1 + read-only + + + DPLL0LCKF + DPLL0 Lock Fall + 17 + 1 + read-only + + + DPLL0TO + DPLL0 Timeout + 18 + 1 + read-only + + + DPLL0LDRTO + DPLL0 Loop Divider Ratio Update Complete + 19 + 1 + read-only + + + DPLL1LCKR + DPLL1 Lock Rise + 24 + 1 + read-only + + + DPLL1LCKF + DPLL1 Lock Fall + 25 + 1 + read-only + + + DPLL1TO + DPLL1 Timeout + 26 + 1 + read-only + + + DPLL1LDRTO + DPLL1 Loop Divider Ratio Update Complete + 27 + 1 + read-only + + + + + 2 + 0x4 + XOSCCTRL%s + External Multipurpose Crystal Oscillator Control + 0x14 + 32 + 0x00000080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + LOWBUFGAIN + Low Buffer Gain Enable + 8 + 1 + + + IPTAT + Oscillator Current Reference + 9 + 2 + + + IMULT + Oscillator Current Multiplier + 11 + 4 + + + ENALC + Automatic Loop Control Enable + 15 + 1 + + + CFDEN + Clock Failure Detector Enable + 16 + 1 + + + SWBEN + Xosc Clock Switch Enable + 17 + 1 + + + STARTUP + Start-Up Time + 20 + 4 + + + CFDPRESC + Clock Failure Detector Prescaler + 24 + 4 + + + + + DFLLCTRLA + DFLL48M Control A + 0x1C + 8 + 0x82 + + + ENABLE + DFLL Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + DFLLCTRLB + DFLL48M Control B + 0x20 + 8 + + + MODE + Operating Mode Selection + 0 + 1 + + + STABLE + Stable DFLL Frequency + 1 + 1 + + + LLAW + Lose Lock After Wake + 2 + 1 + + + USBCRM + USB Clock Recovery Mode + 3 + 1 + + + CCDIS + Chill Cycle Disable + 4 + 1 + + + QLDIS + Quick Lock Disable + 5 + 1 + + + BPLCKC + Bypass Coarse Lock + 6 + 1 + + + WAITLOCK + Wait Lock + 7 + 1 + + + + + DFLLVAL + DFLL48M Value + 0x24 + 32 + + + FINE + Fine Value + 0 + 8 + + + COARSE + Coarse Value + 10 + 6 + + + DIFF + Multiplication Ratio Difference + 16 + 16 + read-only + + + + + DFLLMUL + DFLL48M Multiplier + 0x28 + 32 + + + MUL + DFLL Multiply Factor + 0 + 16 + + + FSTEP + Fine Maximum Step + 16 + 8 + + + CSTEP + Coarse Maximum Step + 26 + 6 + + + + + DFLLSYNC + DFLL48M Synchronization + 0x2C + 8 + + + ENABLE + ENABLE Synchronization Busy + 1 + 1 + read-only + + + DFLLCTRLB + DFLLCTRLB Synchronization Busy + 2 + 1 + read-only + + + DFLLVAL + DFLLVAL Synchronization Busy + 3 + 1 + read-only + + + DFLLMUL + DFLLMUL Synchronization Busy + 4 + 1 + read-only + + + + + 2 + 0x14 + DPLLCTRLA%s + DPLL Control A + 0x30 + 8 + 0x80 + + + ENABLE + DPLL Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + + + 2 + 0x14 + DPLLRATIO%s + DPLL Ratio Control + 0x34 + 32 + + + LDR + Loop Divider Ratio + 0 + 13 + + + LDRFRAC + Loop Divider Ratio Fractional Part + 16 + 5 + + + + + 2 + 0x14 + DPLLCTRLB%s + DPLL Control B + 0x38 + 32 + 0x00000020 + + + FILTER + Proportional Integral Filter Selection + 0 + 4 + + + WUF + Wake Up Fast + 4 + 1 + + + REFCLK + Reference Clock Selection + 5 + 3 + + REFCLKSelect + + GCLK + Dedicated GCLK clock reference + 0x0 + + + XOSC32 + XOSC32K clock reference + 0x1 + + + XOSC0 + XOSC0 clock reference + 0x2 + + + XOSC1 + XOSC1 clock reference + 0x3 + + + + + LTIME + Lock Time + 8 + 3 + + LTIMESelect + + DEFAULT + No time-out. Automatic lock + 0x0 + + + 800US + Time-out if no lock within 800us + 0x4 + + + 900US + Time-out if no lock within 900us + 0x5 + + + 1MS + Time-out if no lock within 1ms + 0x6 + + + 1P1MS + Time-out if no lock within 1.1ms + 0x7 + + + + + LBYPASS + Lock Bypass + 11 + 1 + + + DCOFILTER + Sigma-Delta DCO Filter Selection + 12 + 3 + + + DCOEN + DCO Filter Enable + 15 + 1 + + + DIV + Clock Divider + 16 + 11 + + + + + 2 + 0x14 + DPLLSYNCBUSY%s + DPLL Synchronization Busy + 0x3C + 32 + read-only + + + ENABLE + DPLL Enable Synchronization Status + 1 + 1 + read-only + + + DPLLRATIO + DPLL Loop Divider Ratio Synchronization Status + 2 + 1 + read-only + + + + + 2 + 0x14 + DPLLSTATUS%s + DPLL Status + 0x40 + 32 + read-only + + + LOCK + DPLL Lock Status + 0 + 1 + read-only + + + CLKRDY + DPLL Clock Ready + 1 + 1 + read-only + + + + + + + OSC32KCTRL + 1.0.0 + 32kHz Oscillators Control + OSC32KCTRL + OSC32KCTRL_ + 0x40001400 + + 0 + 0x40 + registers + + + OSC32KCTRL_INTREQ + 7 + + + + INTENCLR + Interrupt Enable Clear + 0x00 + 32 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + XOSC32KFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x04 + 32 + + + XOSC32KRDY + XOSC32K Ready Interrupt Enable + 0 + 1 + + + XOSC32KFAIL + XOSC32K Clock Failure Detector Interrupt Enable + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x08 + 32 + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + + + XOSC32KFAIL + XOSC32K Clock Failure Detector + 2 + 1 + + + + + STATUS + Power and Clocks Status + 0x0C + 32 + read-only + + + XOSC32KRDY + XOSC32K Ready + 0 + 1 + read-only + + + XOSC32KFAIL + XOSC32K Clock Failure Detector + 2 + 1 + read-only + + + XOSC32KSW + XOSC32K Clock switch + 3 + 1 + read-only + + + + + RTCCTRL + RTC Clock Selection + 0x10 + 8 + + + RTCSEL + RTC Clock Selection + 0 + 3 + + RTCSELSelect + + ULP1K + 1.024kHz from 32kHz internal ULP oscillator + 0x0 + + + ULP32K + 32.768kHz from 32kHz internal ULP oscillator + 0x1 + + + XOSC1K + 1.024kHz from 32.768kHz internal oscillator + 0x4 + + + XOSC32K + 32.768kHz from 32.768kHz external crystal oscillator + 0x5 + + + + + + + XOSC32K + 32kHz External Crystal Oscillator (XOSC32K) Control + 0x14 + 16 + 0x2080 + + + ENABLE + Oscillator Enable + 1 + 1 + + + XTALEN + Crystal Oscillator Enable + 2 + 1 + + + EN32K + 32kHz Output Enable + 3 + 1 + + + EN1K + 1kHz Output Enable + 4 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + ONDEMAND + On Demand Control + 7 + 1 + + + STARTUP + Oscillator Start-Up Time + 8 + 3 + + + WRTLOCK + Write Lock + 12 + 1 + + + CGM + Control Gain Mode + 13 + 2 + + CGMSelect + + XT + Standard mode + 0x1 + + + HS + High Speed mode + 0x2 + + + + + + + CFDCTRL + Clock Failure Detector Control + 0x16 + 8 + + + CFDEN + Clock Failure Detector Enable + 0 + 1 + + + SWBACK + Clock Switch Back + 1 + 1 + + + CFDPRESC + Clock Failure Detector Prescaler + 2 + 1 + + + + + EVCTRL + Event Control + 0x17 + 8 + + + CFDEO + Clock Failure Detector Event Output Enable + 0 + 1 + + + + + OSCULP32K + 32kHz Ultra Low Power Internal Oscillator (OSCULP32K) Control + 0x1C + 32 + + + EN32K + Enable Out 32k + 1 + 1 + + + EN1K + Enable Out 1k + 2 + 1 + + + CALIB + Oscillator Calibration + 8 + 6 + + + WRTLOCK + Write Lock + 15 + 1 + + + + + + + PAC + 1.2.0 + Peripheral Access Controller + PAC + PAC_ + 0x40000000 + + 0 + 0x80 + registers + + + PAC_INTREQ + 41 + + + + WRCTRL + Write control + 0x00 + 32 + + + PERID + Peripheral identifier + 0 + 16 + + + KEY + Peripheral access control key + 16 + 8 + + KEYSelect + + OFF + No action + 0x0 + + + CLR + Clear protection + 0x1 + + + SET + Set protection + 0x2 + + + SETLCK + Set and lock protection + 0x3 + + + + + + + EVCTRL + Event control + 0x04 + 8 + + + ERREO + Peripheral acess error event output + 0 + 1 + + + + + INTENCLR + Interrupt enable clear + 0x08 + 8 + + + ERR + Peripheral access error interrupt disable + 0 + 1 + + + + + INTENSET + Interrupt enable set + 0x09 + 8 + + + ERR + Peripheral access error interrupt enable + 0 + 1 + + + + + INTFLAGAHB + Bridge interrupt flag status + 0x10 + 32 + + + FLASH_ + FLASH + 0 + 1 + + + FLASH_ALT_ + FLASH_ALT + 1 + 1 + + + SEEPROM_ + SEEPROM + 2 + 1 + + + RAMCM4S_ + RAMCM4S + 3 + 1 + + + RAMPPPDSU_ + RAMPPPDSU + 4 + 1 + + + RAMDMAWR_ + RAMDMAWR + 5 + 1 + + + RAMDMACICM_ + RAMDMACICM + 6 + 1 + + + HPB0_ + HPB0 + 7 + 1 + + + HPB1_ + HPB1 + 8 + 1 + + + HPB2_ + HPB2 + 9 + 1 + + + HPB3_ + HPB3 + 10 + 1 + + + PUKCC_ + PUKCC + 11 + 1 + + + SDHC0_ + SDHC0 + 12 + 1 + + + QSPI_ + QSPI + 14 + 1 + + + BKUPRAM_ + BKUPRAM + 15 + 1 + + + + + INTFLAGA + Peripheral interrupt flag status - Bridge A + 0x14 + 32 + + + PAC_ + PAC + 0 + 1 + + + PM_ + PM + 1 + 1 + + + MCLK_ + MCLK + 2 + 1 + + + RSTC_ + RSTC + 3 + 1 + + + OSCCTRL_ + OSCCTRL + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL + 5 + 1 + + + SUPC_ + SUPC + 6 + 1 + + + GCLK_ + GCLK + 7 + 1 + + + WDT_ + WDT + 8 + 1 + + + RTC_ + RTC + 9 + 1 + + + EIC_ + EIC + 10 + 1 + + + FREQM_ + FREQM + 11 + 1 + + + SERCOM0_ + SERCOM0 + 12 + 1 + + + SERCOM1_ + SERCOM1 + 13 + 1 + + + TC0_ + TC0 + 14 + 1 + + + TC1_ + TC1 + 15 + 1 + + + + + INTFLAGB + Peripheral interrupt flag status - Bridge B + 0x18 + 32 + + + USB_ + USB + 0 + 1 + + + DSU_ + DSU + 1 + 1 + + + NVMCTRL_ + NVMCTRL + 2 + 1 + + + CMCC_ + CMCC + 3 + 1 + + + PORT_ + PORT + 4 + 1 + + + DMAC_ + DMAC + 5 + 1 + + + HMATRIX_ + HMATRIX + 6 + 1 + + + EVSYS_ + EVSYS + 7 + 1 + + + SERCOM2_ + SERCOM2 + 9 + 1 + + + SERCOM3_ + SERCOM3 + 10 + 1 + + + TCC0_ + TCC0 + 11 + 1 + + + TCC1_ + TCC1 + 12 + 1 + + + TC2_ + TC2 + 13 + 1 + + + TC3_ + TC3 + 14 + 1 + + + TAL_ + TAL + 15 + 1 + + + RAMECC_ + RAMECC + 16 + 1 + + + + + INTFLAGC + Peripheral interrupt flag status - Bridge C + 0x1C + 32 + + + TCC2_ + TCC2 + 3 + 1 + + + TCC3_ + TCC3 + 4 + 1 + + + TC4_ + TC4 + 5 + 1 + + + TC5_ + TC5 + 6 + 1 + + + PDEC_ + PDEC + 7 + 1 + + + AC_ + AC + 8 + 1 + + + AES_ + AES + 9 + 1 + + + TRNG_ + TRNG + 10 + 1 + + + ICM_ + ICM + 11 + 1 + + + PUKCC_ + PUKCC + 12 + 1 + + + QSPI_ + QSPI + 13 + 1 + + + CCL_ + CCL + 14 + 1 + + + + + INTFLAGD + Peripheral interrupt flag status - Bridge D + 0x20 + 32 + + + SERCOM4_ + SERCOM4 + 0 + 1 + + + SERCOM5_ + SERCOM5 + 1 + 1 + + + TCC4_ + TCC4 + 4 + 1 + + + ADC0_ + ADC0 + 7 + 1 + + + ADC1_ + ADC1 + 8 + 1 + + + DAC_ + DAC + 9 + 1 + + + I2S_ + I2S + 10 + 1 + + + PCC_ + PCC + 11 + 1 + + + + + STATUSA + Peripheral write protection status - Bridge A + 0x34 + 32 + read-only + 0x00010000 + + + PAC_ + PAC APB Protect Enable + 0 + 1 + + + PM_ + PM APB Protect Enable + 1 + 1 + + + MCLK_ + MCLK APB Protect Enable + 2 + 1 + + + RSTC_ + RSTC APB Protect Enable + 3 + 1 + + + OSCCTRL_ + OSCCTRL APB Protect Enable + 4 + 1 + + + OSC32KCTRL_ + OSC32KCTRL APB Protect Enable + 5 + 1 + + + SUPC_ + SUPC APB Protect Enable + 6 + 1 + + + GCLK_ + GCLK APB Protect Enable + 7 + 1 + + + WDT_ + WDT APB Protect Enable + 8 + 1 + + + RTC_ + RTC APB Protect Enable + 9 + 1 + + + EIC_ + EIC APB Protect Enable + 10 + 1 + + + FREQM_ + FREQM APB Protect Enable + 11 + 1 + + + SERCOM0_ + SERCOM0 APB Protect Enable + 12 + 1 + + + SERCOM1_ + SERCOM1 APB Protect Enable + 13 + 1 + + + TC0_ + TC0 APB Protect Enable + 14 + 1 + + + TC1_ + TC1 APB Protect Enable + 15 + 1 + + + + + STATUSB + Peripheral write protection status - Bridge B + 0x38 + 32 + read-only + 0x00000002 + + + USB_ + USB APB Protect Enable + 0 + 1 + + + DSU_ + DSU APB Protect Enable + 1 + 1 + + + NVMCTRL_ + NVMCTRL APB Protect Enable + 2 + 1 + + + CMCC_ + CMCC APB Protect Enable + 3 + 1 + + + PORT_ + PORT APB Protect Enable + 4 + 1 + + + DMAC_ + DMAC APB Protect Enable + 5 + 1 + + + HMATRIX_ + HMATRIX APB Protect Enable + 6 + 1 + + + EVSYS_ + EVSYS APB Protect Enable + 7 + 1 + + + SERCOM2_ + SERCOM2 APB Protect Enable + 9 + 1 + + + SERCOM3_ + SERCOM3 APB Protect Enable + 10 + 1 + + + TCC0_ + TCC0 APB Protect Enable + 11 + 1 + + + TCC1_ + TCC1 APB Protect Enable + 12 + 1 + + + TC2_ + TC2 APB Protect Enable + 13 + 1 + + + TC3_ + TC3 APB Protect Enable + 14 + 1 + + + TAL_ + TAL APB Protect Enable + 15 + 1 + + + RAMECC_ + RAMECC APB Protect Enable + 16 + 1 + + + + + STATUSC + Peripheral write protection status - Bridge C + 0x3C + 32 + read-only + + + TCC2_ + TCC2 APB Protect Enable + 3 + 1 + + + TCC3_ + TCC3 APB Protect Enable + 4 + 1 + + + TC4_ + TC4 APB Protect Enable + 5 + 1 + + + TC5_ + TC5 APB Protect Enable + 6 + 1 + + + PDEC_ + PDEC APB Protect Enable + 7 + 1 + + + AC_ + AC APB Protect Enable + 8 + 1 + + + AES_ + AES APB Protect Enable + 9 + 1 + + + TRNG_ + TRNG APB Protect Enable + 10 + 1 + + + ICM_ + ICM APB Protect Enable + 11 + 1 + + + PUKCC_ + PUKCC APB Protect Enable + 12 + 1 + + + QSPI_ + QSPI APB Protect Enable + 13 + 1 + + + CCL_ + CCL APB Protect Enable + 14 + 1 + + + + + STATUSD + Peripheral write protection status - Bridge D + 0x40 + 32 + read-only + + + SERCOM4_ + SERCOM4 APB Protect Enable + 0 + 1 + + + SERCOM5_ + SERCOM5 APB Protect Enable + 1 + 1 + + + TCC4_ + TCC4 APB Protect Enable + 4 + 1 + + + ADC0_ + ADC0 APB Protect Enable + 7 + 1 + + + ADC1_ + ADC1 APB Protect Enable + 8 + 1 + + + DAC_ + DAC APB Protect Enable + 9 + 1 + + + I2S_ + I2S APB Protect Enable + 10 + 1 + + + PCC_ + PCC APB Protect Enable + 11 + 1 + + + + + + + PCC + 1.1.0 + Parallel Capture Controller + PCC + PCC_ + 0x43002C00 + + 0 + 0x100 + registers + + + PCC_INTREQ + 129 + + + + MR + Mode Register + 0x00 + 32 + + + PCEN + Parallel Capture Enable + 0 + 1 + + + DSIZE + Data size + 4 + 2 + + + SCALE + Scale data + 8 + 1 + + + ALWYS + Always Sampling + 9 + 1 + + + HALFS + Half Sampling + 10 + 1 + + + FRSTS + First sample + 11 + 1 + + + ISIZE + Input Data Size + 16 + 3 + + + CID + Clear If Disabled + 30 + 2 + + + + + IER + Interrupt Enable Register + 0x04 + 32 + write-only + + + DRDY + Data Ready Interrupt Enable + 0 + 1 + + + OVRE + Overrun Error Interrupt Enable + 1 + 1 + + + + + IDR + Interrupt Disable Register + 0x08 + 32 + write-only + + + DRDY + Data Ready Interrupt Disable + 0 + 1 + + + OVRE + Overrun Error Interrupt Disable + 1 + 1 + + + + + IMR + Interrupt Mask Register + 0x0C + 32 + read-only + + + DRDY + Data Ready Interrupt Mask + 0 + 1 + + + OVRE + Overrun Error Interrupt Mask + 1 + 1 + + + + + ISR + Interrupt Status Register + 0x10 + 32 + read-only + + + DRDY + Data Ready Interrupt Status + 0 + 1 + + + OVRE + Overrun Error Interrupt Status + 1 + 1 + + + + + RHR + Reception Holding Register + 0x14 + 32 + read-only + + + RDATA + Reception Data + 0 + 32 + + + + + WPMR + Write Protection Mode Register + 0xE0 + 32 + + + WPEN + Write Protection Enable + 0 + 1 + + + WPKEY + Write Protection Key + 8 + 24 + + + + + WPSR + Write Protection Status Register + 0xE4 + 32 + read-only + + + WPVS + Write Protection Violation Source + 0 + 1 + + + WPVSRC + Write Protection Violation Status + 8 + 16 + + + + + + + PDEC + 1.0.0 + Quadrature Decodeur + PDEC + PDEC_ + 0x42001C00 + + 0 + 0x40 + registers + + + PDEC_INTREQ_0 + 115 + + + PDEC_INTREQ_1 + 116 + + + PDEC_INTREQ_2 + 117 + + + + CTRLA + Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + MODE + Operation Mode + 2 + 2 + + MODESelect + + QDEC + QDEC operating mode + 0x0 + + + HALL + HALL operating mode + 0x1 + + + COUNTER + COUNTER operating mode + 0x2 + + + + + RUNSTDBY + Run in Standby + 6 + 1 + + + CONF + PDEC Configuration + 8 + 3 + + CONFSelect + + X4 + Quadrature decoder direction + 0x0 + + + X4S + Secure Quadrature decoder direction + 0x1 + + + X2 + Decoder direction + 0x2 + + + X2S + Secure decoder direction + 0x3 + + + AUTOC + Auto correction mode + 0x4 + + + + + ALOCK + Auto Lock + 11 + 1 + + + SWAP + PDEC Phase A and B Swap + 14 + 1 + + + PEREN + Period Enable + 15 + 1 + + + PINEN0 + PDEC Input From Pin 0 Enable + 16 + 1 + + + PINEN1 + PDEC Input From Pin 1 Enable + 17 + 1 + + + PINEN2 + PDEC Input From Pin 2 Enable + 18 + 1 + + + PINVEN0 + IO Pin 0 Invert Enable + 20 + 1 + + + PINVEN1 + IO Pin 1 Invert Enable + 21 + 1 + + + PINVEN2 + IO Pin 2 Invert Enable + 22 + 1 + + + ANGULAR + Angular Counter Length + 24 + 3 + + + MAXCMP + Maximum Consecutive Missing Pulses + 28 + 4 + + + + + CTRLBCLR + Control B Clear + 0x04 + 8 + + + LUPD + Lock Update + 1 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a counter restart or retrigger + 0x1 + + + UPDATE + Force update of double buffered registers + 0x2 + + + READSYNC + Force a read synchronization of COUNT + 0x3 + + + START + Start QDEC/HALL + 0x4 + + + STOP + Stop QDEC/HALL + 0x5 + + + + + + + CTRLBSET + Control B Set + 0x05 + 8 + + + LUPD + Lock Update + 1 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a counter restart or retrigger + 0x1 + + + UPDATE + Force update of double buffered registers + 0x2 + + + READSYNC + Force a read synchronization of COUNT + 0x3 + + + Start + Start QDEC/HALL + 0x4 + + + Stop + Stop QDEC/HALL + 0x5 + + + + + + + EVCTRL + Event Control + 0x06 + 16 + + + EVACT + Event Action + 0 + 2 + + EVACTSelect + + OFF + Event action disabled + 0x0 + + + RETRIGGER + Start, restart or retrigger on event + 0x1 + + + COUNT + Count on event + 0x2 + + + + + EVINV + Inverted Event Input Enable + 2 + 3 + + + EVEI + Event Input Enable + 5 + 3 + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + ERREO + Error Output Event Enable + 9 + 1 + + + DIREO + Direction Output Event Enable + 10 + 1 + + + VLCEO + Velocity Output Event Enable + 11 + 1 + + + MCEO0 + Match Channel 0 Event Output Enable + 12 + 1 + + + MCEO1 + Match Channel 1 Event Output Enable + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x08 + 8 + + + OVF + Overflow/Underflow Interrupt Disable + 0 + 1 + + + ERR + Error Interrupt Disable + 1 + 1 + + + DIR + Direction Interrupt Disable + 2 + 1 + + + VLC + Velocity Interrupt Disable + 3 + 1 + + + MC0 + Channel 0 Compare Match Disable + 4 + 1 + + + MC1 + Channel 1 Compare Match Disable + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x09 + 8 + + + OVF + Overflow/Underflow Interrupt Enable + 0 + 1 + + + ERR + Error Interrupt Enable + 1 + 1 + + + DIR + Direction Interrupt Enable + 2 + 1 + + + VLC + Velocity Interrupt Enable + 3 + 1 + + + MC0 + Channel 0 Compare Match Enable + 4 + 1 + + + MC1 + Channel 1 Compare Match Enable + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x0A + 8 + + + OVF + Overflow/Underflow + 0 + 1 + + + ERR + Error + 1 + 1 + + + DIR + Direction Change + 2 + 1 + + + VLC + Velocity + 3 + 1 + + + MC0 + Channel 0 Compare Match + 4 + 1 + + + MC1 + Channel 1 Compare Match + 5 + 1 + + + + + STATUS + Status + 0x0C + 16 + 0x0040 + + + QERR + Quadrature Error Flag + 0 + 1 + + + IDXERR + Index Error Flag + 1 + 1 + + + MPERR + Missing Pulse Error flag + 2 + 1 + + + WINERR + Window Error Flag + 4 + 1 + + + HERR + Hall Error Flag + 5 + 1 + + + STOP + Stop + 6 + 1 + read-only + + + DIR + Direction Status Flag + 7 + 1 + read-only + + + PRESCBUFV + Prescaler Buffer Valid + 8 + 1 + read-only + + + FILTERBUFV + Filter Buffer Valid + 9 + 1 + read-only + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 12 + 1 + read-only + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 13 + 1 + read-only + + + + + DBGCTRL + Debug Control + 0x0F + 8 + + + DBGRUN + Debug Run Mode + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + + + ENABLE + Enable Synchronization Busy + 1 + 1 + + + CTRLB + Control B Synchronization Busy + 2 + 1 + + + STATUS + Status Synchronization Busy + 3 + 1 + + + PRESC + Prescaler Synchronization Busy + 4 + 1 + + + FILTER + Filter Synchronization Busy + 5 + 1 + + + COUNT + Count Synchronization Busy + 6 + 1 + + + CC0 + Compare Channel 0 Synchronization Busy + 7 + 1 + + + CC1 + Compare Channel 1 Synchronization Busy + 8 + 1 + + + + + PRESC + Prescaler Value + 0x14 + 8 + + + PRESC + Prescaler Value + 0 + 4 + + PRESCSelect + + DIV1 + No division + 0x0 + + + DIV2 + Divide by 2 + 0x1 + + + DIV4 + Divide by 4 + 0x2 + + + DIV8 + Divide by 8 + 0x3 + + + DIV16 + Divide by 16 + 0x4 + + + DIV32 + Divide by 32 + 0x5 + + + DIV64 + Divide by 64 + 0x6 + + + DIV128 + Divide by 128 + 0x7 + + + DIV256 + Divide by 256 + 0x8 + + + DIV512 + Divide by 512 + 0x9 + + + DIV1024 + Divide by 1024 + 0xa + + + + + + + FILTER + Filter Value + 0x15 + 8 + + + FILTER + Filter Value + 0 + 8 + + + + + PRESCBUF + Prescaler Buffer Value + 0x18 + 8 + + + PRESCBUF + Prescaler Buffer Value + 0 + 4 + + PRESCBUFSelect + + DIV1 + No division + 0x0 + + + DIV2 + Divide by 2 + 0x1 + + + DIV4 + Divide by 4 + 0x2 + + + DIV8 + Divide by 8 + 0x3 + + + DIV16 + Divide by 16 + 0x4 + + + DIV32 + Divide by 32 + 0x5 + + + DIV64 + Divide by 64 + 0x6 + + + DIV128 + Divide by 128 + 0x7 + + + DIV256 + Divide by 256 + 0x8 + + + DIV512 + Divide by 512 + 0x9 + + + DIV1024 + Divide by 1024 + 0xa + + + + + + + FILTERBUF + Filter Buffer Value + 0x19 + 8 + + + FILTERBUF + Filter Buffer Value + 0 + 8 + + + + + COUNT + Counter Value + 0x1C + 32 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 0x4 + CC%s + Channel n Compare Value + 0x20 + 32 + + + CC + Channel Compare Value + 0 + 16 + + + + + 2 + 0x4 + CCBUF%s + Channel Compare Buffer Value + 0x30 + 32 + + + CCBUF + Channel Compare Buffer Value + 0 + 16 + + + + + + + PM + 1.0.0 + Power Manager + PM + PM_ + 0x40000400 + + 0 + 0x40 + registers + + + PM_INTREQ + 0 + + + + CTRLA + Control A + 0x00 + 8 + + + IORET + I/O Retention + 2 + 1 + + + + + SLEEPCFG + Sleep Configuration + 0x01 + 8 + 0x02 + + + SLEEPMODE + Sleep Mode + 0 + 3 + + SLEEPMODESelect + + IDLE0 + CPU clock is OFF + 0x0 + + + IDLE1 + AHB clock is OFF + 0x1 + + + IDLE2 + APB clock are OFF + 0x2 + + + STANDBY + All Clocks are OFF + 0x4 + + + HIBERNATE + Backup domain is ON as well as some PDRAMs + 0x5 + + + BACKUP + Only Backup domain is powered ON + 0x6 + + + OFF + All power domains are powered OFF + 0x7 + + + + + + + INTENCLR + Interrupt Enable Clear + 0x04 + 8 + + + SLEEPRDY + Sleep Mode Entry Ready Enable + 0 + 1 + write-only + + + + + INTENSET + Interrupt Enable Set + 0x05 + 8 + + + SLEEPRDY + Sleep Mode Entry Ready Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x06 + 8 + + + SLEEPRDY + Sleep Mode Entry Ready + 0 + 1 + + + + + STDBYCFG + Standby Configuration + 0x08 + 8 + + + RAMCFG + Ram Configuration + 0 + 2 + + RAMCFGSelect + + RET + All the RAMs are retained + 0x0 + + + PARTIAL + Only the first 32K bytes are retained + 0x1 + + + OFF + All the RAMs are OFF + 0x2 + + + + + FASTWKUP + Fast Wakeup + 4 + 2 + + + + + HIBCFG + Hibernate Configuration + 0x09 + 8 + + + RAMCFG + Ram Configuration + 0 + 2 + + + BRAMCFG + Backup Ram Configuration + 2 + 2 + + + + + BKUPCFG + Backup Configuration + 0x0A + 8 + + + BRAMCFG + Ram Configuration + 0 + 2 + + + + + PWSAKDLY + Power Switch Acknowledge Delay + 0x12 + 8 + + + DLYVAL + Delay Value + 0 + 7 + + + IGNACK + Ignore Acknowledge + 7 + 1 + + + + + + + PORT + 2.2.0 + Port Module + PORT + PORT_ + 0x41008000 + + 0 + 0x200 + registers + + + + 2 + 0x80 + DIR%s + Data Direction + 0x00 + 32 + + + DIR + Port Data Direction + 0 + 32 + + + + + 2 + 0x80 + DIRCLR%s + Data Direction Clear + 0x04 + 32 + + + DIRCLR + Port Data Direction Clear + 0 + 32 + + + + + 2 + 0x80 + DIRSET%s + Data Direction Set + 0x08 + 32 + + + DIRSET + Port Data Direction Set + 0 + 32 + + + + + 2 + 0x80 + DIRTGL%s + Data Direction Toggle + 0x0C + 32 + + + DIRTGL + Port Data Direction Toggle + 0 + 32 + + + + + 2 + 0x80 + OUT%s + Data Output Value + 0x10 + 32 + + + OUT + PORT Data Output Value + 0 + 32 + + + + + 2 + 0x80 + OUTCLR%s + Data Output Value Clear + 0x14 + 32 + + + OUTCLR + PORT Data Output Value Clear + 0 + 32 + + + + + 2 + 0x80 + OUTSET%s + Data Output Value Set + 0x18 + 32 + + + OUTSET + PORT Data Output Value Set + 0 + 32 + + + + + 2 + 0x80 + OUTTGL%s + Data Output Value Toggle + 0x1C + 32 + + + OUTTGL + PORT Data Output Value Toggle + 0 + 32 + + + + + 2 + 0x80 + IN%s + Data Input Value + 0x20 + 32 + read-only + + + IN + PORT Data Input Value + 0 + 32 + read-only + + + + + 2 + 0x80 + CTRL%s + Control + 0x24 + 32 + + + SAMPLING + Input Sampling Mode + 0 + 32 + write-only + + + + + 2 + 0x80 + WRCONFIG%s + Write Configuration + 0x28 + 32 + write-only + + + PINMASK + Pin Mask for Multiple Pin Configuration + 0 + 16 + write-only + + + PMUXEN + Peripheral Multiplexer Enable + 16 + 1 + write-only + + + INEN + Input Enable + 17 + 1 + write-only + + + PULLEN + Pull Enable + 18 + 1 + write-only + + + DRVSTR + Output Driver Strength Selection + 22 + 1 + write-only + + + PMUX + Peripheral Multiplexing + 24 + 4 + write-only + + + WRPMUX + Write PMUX + 28 + 1 + write-only + + + WRPINCFG + Write PINCFG + 30 + 1 + write-only + + + HWSEL + Half-Word Select + 31 + 1 + write-only + + + + + 2 + 0x80 + EVCTRL%s + Event Input Control + 0x2C + 32 + + + PID0 + PORT Event Pin Identifier 0 + 0 + 5 + + + EVACT0 + PORT Event Action 0 + 5 + 2 + + EVACT0Select + + OUT + Event output to pin + 0x0 + + + SET + Set output register of pin on event + 0x1 + + + CLR + Clear output register of pin on event + 0x2 + + + TGL + Toggle output register of pin on event + 0x3 + + + + + PORTEI0 + PORT Event Input Enable 0 + 7 + 1 + + + PID1 + PORT Event Pin Identifier 1 + 8 + 5 + + + EVACT1 + PORT Event Action 1 + 13 + 2 + + + PORTEI1 + PORT Event Input Enable 1 + 15 + 1 + + + PID2 + PORT Event Pin Identifier 2 + 16 + 5 + + + EVACT2 + PORT Event Action 2 + 21 + 2 + + + PORTEI2 + PORT Event Input Enable 2 + 23 + 1 + + + PID3 + PORT Event Pin Identifier 3 + 24 + 5 + + + EVACT3 + PORT Event Action 3 + 29 + 2 + + + PORTEI3 + PORT Event Input Enable 3 + 31 + 1 + + + + + 16 + 0x1 + PMUX0_%s + Peripheral Multiplexing - Group 0 + 0x30 + 8 + + + PMUXE + Peripheral Multiplexing for Even-Numbered Pin + 0 + 4 + + + PMUXO + Peripheral Multiplexing for Odd-Numbered Pin + 4 + 4 + + + + + 16 + 0x1 + PMUX1_%s + Peripheral Multiplexing - Group 1 + 0xb0 + + + 32 + 0x1 + PINCFG0_%s + Pin Configuration - Group 0 + 0x40 + 8 + + + PMUXEN + Peripheral Multiplexer Enable + 0 + 1 + + + INEN + Input Enable + 1 + 1 + + + PULLEN + Pull Enable + 2 + 1 + + + DRVSTR + Output Driver Strength Selection + 6 + 1 + + + + + 32 + 0x1 + PINCFG1_%s + Pin Configuration - Group 1 + 0xc0 + + + + + QSPI + 1.6.3 + Quad SPI interface + QSPI + QSPI_ + 0x42003400 + + 0 + 0x80 + registers + + + QSPI_INTREQ + 134 + + + + CTRLA + Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + LASTXFER + Last Transfer + 24 + 1 + write-only + + + + + CTRLB + Control B + 0x04 + 32 + + + MODE + Serial Memory Mode + 0 + 1 + + MODESelect + + SPI + SPI operating mode + 0x0 + + + MEMORY + Serial Memory operating mode + 0x1 + + + + + LOOPEN + Local Loopback Enable + 1 + 1 + + + WDRBT + Wait Data Read Before Transfer + 2 + 1 + + + SMEMREG + Serial Memory reg + 3 + 1 + + + CSMODE + Chip Select Mode + 4 + 2 + + CSMODESelect + + NORELOAD + The chip select is deasserted if TD has not been reloaded before the end of the current transfer. + 0x0 + + + LASTXFER + The chip select is deasserted when the bit LASTXFER is written at 1 and the character written in TD has been transferred. + 0x1 + + + SYSTEMATICALLY + The chip select is deasserted systematically after each transfer. + 0x2 + + + + + DATALEN + Data Length + 8 + 4 + + DATALENSelect + + 8BITS + 8-bits transfer + 0x0 + + + 9BITS + 9 bits transfer + 0x1 + + + 10BITS + 10-bits transfer + 0x2 + + + 11BITS + 11-bits transfer + 0x3 + + + 12BITS + 12-bits transfer + 0x4 + + + 13BITS + 13-bits transfer + 0x5 + + + 14BITS + 14-bits transfer + 0x6 + + + 15BITS + 15-bits transfer + 0x7 + + + 16BITS + 16-bits transfer + 0x8 + + + + + DLYBCT + Delay Between Consecutive Transfers + 16 + 8 + + + DLYCS + Minimum Inactive CS Delay + 24 + 8 + + + + + BAUD + Baud Rate + 0x08 + 32 + + + CPOL + Clock Polarity + 0 + 1 + + + CPHA + Clock Phase + 1 + 1 + + + BAUD + Serial Clock Baud Rate + 8 + 8 + + + DLYBS + Delay Before SCK + 16 + 8 + + + + + RXDATA + Receive Data + 0x0C + 32 + read-only + + + DATA + Receive Data + 0 + 16 + read-only + + + + + TXDATA + Transmit Data + 0x10 + 32 + write-only + + + DATA + Transmit Data + 0 + 16 + write-only + + + + + INTENCLR + Interrupt Enable Clear + 0x14 + 32 + + + RXC + Receive Data Register Full Interrupt Disable + 0 + 1 + + + DRE + Transmit Data Register Empty Interrupt Disable + 1 + 1 + + + TXC + Transmission Complete Interrupt Disable + 2 + 1 + + + ERROR + Overrun Error Interrupt Disable + 3 + 1 + + + CSRISE + Chip Select Rise Interrupt Disable + 8 + 1 + + + INSTREND + Instruction End Interrupt Disable + 10 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x18 + 32 + + + RXC + Receive Data Register Full Interrupt Enable + 0 + 1 + + + DRE + Transmit Data Register Empty Interrupt Enable + 1 + 1 + + + TXC + Transmission Complete Interrupt Enable + 2 + 1 + + + ERROR + Overrun Error Interrupt Enable + 3 + 1 + + + CSRISE + Chip Select Rise Interrupt Enable + 8 + 1 + + + INSTREND + Instruction End Interrupt Enable + 10 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x1C + 32 + + + RXC + Receive Data Register Full + 0 + 1 + + + DRE + Transmit Data Register Empty + 1 + 1 + + + TXC + Transmission Complete + 2 + 1 + + + ERROR + Overrun Error + 3 + 1 + + + CSRISE + Chip Select Rise + 8 + 1 + + + INSTREND + Instruction End + 10 + 1 + + + + + STATUS + Status Register + 0x20 + 32 + read-only + 0x00000200 + + + ENABLE + Enable + 1 + 1 + read-only + + + CSSTATUS + Chip Select + 9 + 1 + read-only + + + + + INSTRADDR + Instruction Address + 0x30 + 32 + + + ADDR + Instruction Address + 0 + 32 + + + + + INSTRCTRL + Instruction Code + 0x34 + 32 + + + INSTR + Instruction Code + 0 + 8 + + + OPTCODE + Option Code + 16 + 8 + + + + + INSTRFRAME + Instruction Frame + 0x38 + 32 + + + WIDTH + Instruction Code, Address, Option Code and Data Width + 0 + 3 + + WIDTHSelect + + SINGLE_BIT_SPI + Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Single-bit SPI + 0x0 + + + DUAL_OUTPUT + Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Dual SPI + 0x1 + + + QUAD_OUTPUT + Instruction: Single-bit SPI / Address-Option: Single-bit SPI / Data: Quad SPI + 0x2 + + + DUAL_IO + Instruction: Single-bit SPI / Address-Option: Dual SPI / Data: Dual SPI + 0x3 + + + QUAD_IO + Instruction: Single-bit SPI / Address-Option: Quad SPI / Data: Quad SPI + 0x4 + + + DUAL_CMD + Instruction: Dual SPI / Address-Option: Dual SPI / Data: Dual SPI + 0x5 + + + QUAD_CMD + Instruction: Quad SPI / Address-Option: Quad SPI / Data: Quad SPI + 0x6 + + + + + INSTREN + Instruction Enable + 4 + 1 + + + ADDREN + Address Enable + 5 + 1 + + + OPTCODEEN + Option Enable + 6 + 1 + + + DATAEN + Data Enable + 7 + 1 + + + OPTCODELEN + Option Code Length + 8 + 2 + + OPTCODELENSelect + + 1BIT + 1-bit length option code + 0x0 + + + 2BITS + 2-bits length option code + 0x1 + + + 4BITS + 4-bits length option code + 0x2 + + + 8BITS + 8-bits length option code + 0x3 + + + + + ADDRLEN + Address Length + 10 + 1 + + ADDRLENSelect + + 24BITS + 24-bits address length + 0x0 + + + 32BITS + 32-bits address length + 0x1 + + + + + TFRTYPE + Data Transfer Type + 12 + 2 + + TFRTYPESelect + + READ + Read transfer from the serial memory.Scrambling is not performed.Read at random location (fetch) in the serial flash memory is not possible. + 0x0 + + + READMEMORY + Read data transfer from the serial memory.If enabled, scrambling is performed.Read at random location (fetch) in the serial flash memory is possible. + 0x1 + + + WRITE + Write transfer into the serial memory.Scrambling is not performed. + 0x2 + + + WRITEMEMORY + Write data transfer into the serial memory.If enabled, scrambling is performed. + 0x3 + + + + + CRMODE + Continuous Read Mode + 14 + 1 + + + DDREN + Double Data Rate Enable + 15 + 1 + + + DUMMYLEN + Dummy Cycles Length + 16 + 5 + + + + + SCRAMBCTRL + Scrambling Mode + 0x40 + 32 + + + ENABLE + Scrambling/Unscrambling Enable + 0 + 1 + + + RANDOMDIS + Scrambling/Unscrambling Random Value Disable + 1 + 1 + + + + + SCRAMBKEY + Scrambling Key + 0x44 + 32 + write-only + + + KEY + Scrambling User Key + 0 + 32 + write-only + + + + + + + RAMECC + 1.0.0 + RAM ECC + RAMECC + RAMECC_ + 0x41020000 + + 0 + 0x10 + registers + + + RAMECC_INTREQ + 45 + + + + INTENCLR + Interrupt Enable Clear + 0x0 + 8 + + + SINGLEE + Single Bit ECC Error Interrupt Enable Clear + 0 + 1 + + + DUALE + Dual Bit ECC Error Interrupt Enable Clear + 1 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x1 + 8 + + + SINGLEE + Single Bit ECC Error Interrupt Enable Set + 0 + 1 + + + DUALE + Dual Bit ECC Error Interrupt Enable Set + 1 + 1 + + + + + INTFLAG + Interrupt Flag + 0x2 + 8 + + + SINGLEE + Single Bit ECC Error Interrupt + 0 + 1 + + + DUALE + Dual Bit ECC Error Interrupt + 1 + 1 + + + + + STATUS + Status + 0x3 + 8 + read-only + + + ECCDIS + ECC Disable + 0 + 1 + read-only + + + + + ERRADDR + Error Address + 0x4 + 32 + read-only + + + ERRADDR + Error Address + 0 + 17 + read-only + + + + + DBGCTRL + Debug Control + 0xF + 8 + + + ECCDIS + ECC Disable + 0 + 1 + + + ECCELOG + ECC Error Log + 1 + 1 + + + + + + + RSTC + 4.0.0 + Reset Controller + RSTC + RSTC_ + 0x40000C00 + + 0 + 0x20 + registers + + + + RCAUSE + Reset Cause + 0x00 + 8 + read-only + + + POR + Power On Reset + 0 + 1 + + + BODCORE + Brown Out CORE Detector Reset + 1 + 1 + + + BODVDD + Brown Out VDD Detector Reset + 2 + 1 + + + NVM + NVM Reset + 3 + 1 + + + EXT + External Reset + 4 + 1 + + + WDT + Watchdog Reset + 5 + 1 + + + SYST + System Reset Request + 6 + 1 + + + BACKUP + Backup Reset + 7 + 1 + + + + + BKUPEXIT + Backup Exit Source + 0x02 + 8 + read-only + + + RTC + Real Timer Counter Interrupt + 1 + 1 + read-only + + + BBPS + Battery Backup Power Switch + 2 + 1 + read-only + + + HIB + Hibernate + 7 + 1 + read-only + + + + + + + RTC + 2.1.0 + Real-Time Counter + RTC + RTC_ + 0x40002400 + + 0 + 0x100 + registers + + + RTC_INTREQ + 11 + + + + MODE0 + 32-bit Counter with Single 32-bit Compare + RtcMode0 + 0x0 + + CTRLA + MODE0 Control A + 0x00 + 16 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xa + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xb + + + + + BKTRST + BKUP Registers Reset On Tamper Enable + 13 + 1 + + + GPTRST + GP Registers Reset On Tamper Enable + 14 + 1 + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + CTRLB + MODE0 Control B + 0x02 + 16 + + + GP0EN + General Purpose 0 Enable + 0 + 1 + + + GP2EN + General Purpose 2 Enable + 1 + 1 + + + DEBMAJ + Debouncer Majority Enable + 4 + 1 + + + DEBASYNC + Debouncer Asynchronous Enable + 5 + 1 + + + RTCOUT + RTC Output Enable + 6 + 1 + + + DMAEN + DMA Enable + 7 + 1 + + + DEBF + Debounce Freqnuency + 8 + 3 + + DEBFSelect + + DIV2 + CLK_RTC_DEB = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_DEB = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_DEB = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_DEB = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_DEB = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_DEB = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_DEB = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_DEB = CLK_RTC/256 + 0x7 + + + + + ACTF + Active Layer Freqnuency + 12 + 3 + + ACTFSelect + + DIV2 + CLK_RTC_OUT = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_OUT = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_OUT = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_OUT = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_OUT = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_OUT = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_OUT = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_OUT = CLK_RTC/256 + 0x7 + + + + + + + EVCTRL + MODE0 Event Control + 0x04 + 32 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + TAMPEREO + Tamper Event Output Enable + 14 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + TAMPEVEI + Tamper Event Input Enable + 16 + 1 + + + + + INTENCLR + MODE0 Interrupt Enable Clear + 0x08 + 16 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + write-only + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + write-only + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + write-only + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + write-only + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + write-only + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + write-only + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + write-only + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + write-only + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE0 Interrupt Enable Set + 0x0A + 16 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE0 Interrupt Flag Status and Clear + 0x0C + 16 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + TAMPER + Tamper + 14 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0x0E + 8 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE0 Synchronization Busy Status + 0x10 + 32 + read-only + + + SWRST + Software Reset Busy + 0 + 1 + read-only + + + ENABLE + Enable Bit Busy + 1 + 1 + read-only + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + read-only + + + COUNT + COUNT Register Busy + 3 + 1 + read-only + + + COMP0 + COMP 0 Register Busy + 5 + 1 + read-only + + + COMP1 + COMP 1 Register Busy + 6 + 1 + read-only + + + COUNTSYNC + Count Synchronization Enable Bit Busy + 15 + 1 + read-only + + + GP0 + General Purpose 0 Register Busy + 16 + 1 + read-only + + + GP1 + General Purpose 1 Register Busy + 17 + 1 + read-only + + + GP2 + General Purpose 2 Register Busy + 18 + 1 + read-only + + + GP3 + General Purpose 3 Register Busy + 19 + 1 + read-only + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE0 Counter Value + 0x18 + 32 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 0x4 + COMP%s + MODE0 Compare n Value + 0x20 + 32 + + + COMP + Compare Value + 0 + 32 + + + + + 4 + 0x4 + GP%s + General Purpose + 0x40 + 32 + + + GP + General Purpose + 0 + 32 + + + + + TAMPCTRL + Tamper Control + 0x60 + 32 + + + IN0ACT + Tamper Input 0 Action + 0 + 2 + + IN0ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN0 to OUT + 0x3 + + + + + IN1ACT + Tamper Input 1 Action + 2 + 2 + + IN1ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN1 to OUT + 0x3 + + + + + IN2ACT + Tamper Input 2 Action + 4 + 2 + + IN2ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN2 to OUT + 0x3 + + + + + IN3ACT + Tamper Input 3 Action + 6 + 2 + + IN3ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN3 to OUT + 0x3 + + + + + IN4ACT + Tamper Input 4 Action + 8 + 2 + + IN4ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN4 to OUT + 0x3 + + + + + TAMLVL0 + Tamper Level Select 0 + 16 + 1 + + + TAMLVL1 + Tamper Level Select 1 + 17 + 1 + + + TAMLVL2 + Tamper Level Select 2 + 18 + 1 + + + TAMLVL3 + Tamper Level Select 3 + 19 + 1 + + + TAMLVL4 + Tamper Level Select 4 + 20 + 1 + + + DEBNC0 + Debouncer Enable 0 + 24 + 1 + + + DEBNC1 + Debouncer Enable 1 + 25 + 1 + + + DEBNC2 + Debouncer Enable 2 + 26 + 1 + + + DEBNC3 + Debouncer Enable 3 + 27 + 1 + + + DEBNC4 + Debouncer Enable 4 + 28 + 1 + + + + + TIMESTAMP + MODE0 Timestamp + 0x64 + 32 + read-only + + + COUNT + Count Timestamp Value + 0 + 32 + read-only + + + + + TAMPID + Tamper ID + 0x68 + 32 + + + TAMPID0 + Tamper Input 0 Detected + 0 + 1 + + + TAMPID1 + Tamper Input 1 Detected + 1 + 1 + + + TAMPID2 + Tamper Input 2 Detected + 2 + 1 + + + TAMPID3 + Tamper Input 3 Detected + 3 + 1 + + + TAMPID4 + Tamper Input 4 Detected + 4 + 1 + + + TAMPEVT + Tamper Event Detected + 31 + 1 + + + + + 8 + 0x4 + BKUP%s + Backup + 0x80 + 32 + + + BKUP + Backup + 0 + 32 + + + + + + MODE1 + 16-bit Counter with Two 16-bit Compares + MODE0 + RtcMode1 + 0x0 + + CTRLA + MODE1 Control A + 0x00 + 16 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xa + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xb + + + + + BKTRST + BKUP Registers Reset On Tamper Enable + 13 + 1 + + + GPTRST + GP Registers Reset On Tamper Enable + 14 + 1 + + + COUNTSYNC + Count Read Synchronization Enable + 15 + 1 + + + + + CTRLB + MODE1 Control B + 0x02 + 16 + + + GP0EN + General Purpose 0 Enable + 0 + 1 + + + GP2EN + General Purpose 2 Enable + 1 + 1 + + + DEBMAJ + Debouncer Majority Enable + 4 + 1 + + + DEBASYNC + Debouncer Asynchronous Enable + 5 + 1 + + + RTCOUT + RTC Output Enable + 6 + 1 + + + DMAEN + DMA Enable + 7 + 1 + + + DEBF + Debounce Freqnuency + 8 + 3 + + DEBFSelect + + DIV2 + CLK_RTC_DEB = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_DEB = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_DEB = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_DEB = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_DEB = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_DEB = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_DEB = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_DEB = CLK_RTC/256 + 0x7 + + + + + ACTF + Active Layer Freqnuency + 12 + 3 + + ACTFSelect + + DIV2 + CLK_RTC_OUT = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_OUT = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_OUT = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_OUT = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_OUT = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_OUT = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_OUT = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_OUT = CLK_RTC/256 + 0x7 + + + + + + + EVCTRL + MODE1 Event Control + 0x04 + 32 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + CMPEO0 + Compare 0 Event Output Enable + 8 + 1 + + + CMPEO1 + Compare 1 Event Output Enable + 9 + 1 + + + CMPEO2 + Compare 2 Event Output Enable + 10 + 1 + + + CMPEO3 + Compare 3 Event Output Enable + 11 + 1 + + + TAMPEREO + Tamper Event Output Enable + 14 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + TAMPEVEI + Tamper Event Input Enable + 16 + 1 + + + + + INTENCLR + MODE1 Interrupt Enable Clear + 0x08 + 16 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + CMP2 + Compare 2 Interrupt Enable + 10 + 1 + + + CMP3 + Compare 3 Interrupt Enable + 11 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE1 Interrupt Enable Set + 0x0A + 16 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + CMP0 + Compare 0 Interrupt Enable + 8 + 1 + + + CMP1 + Compare 1 Interrupt Enable + 9 + 1 + + + CMP2 + Compare 2 Interrupt Enable + 10 + 1 + + + CMP3 + Compare 3 Interrupt Enable + 11 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE1 Interrupt Flag Status and Clear + 0x0C + 16 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + CMP0 + Compare 0 + 8 + 1 + + + CMP1 + Compare 1 + 9 + 1 + + + CMP2 + Compare 2 + 10 + 1 + + + CMP3 + Compare 3 + 11 + 1 + + + TAMPER + Tamper + 14 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0x0E + 8 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE1 Synchronization Busy Status + 0x10 + 32 + read-only + + + SWRST + Software Reset Bit Busy + 0 + 1 + read-only + + + ENABLE + Enable Bit Busy + 1 + 1 + read-only + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + read-only + + + COUNT + COUNT Register Busy + 3 + 1 + read-only + + + PER + PER Register Busy + 4 + 1 + read-only + + + COMP0 + COMP 0 Register Busy + 5 + 1 + read-only + + + COMP1 + COMP 1 Register Busy + 6 + 1 + read-only + + + COMP2 + COMP 2 Register Busy + 7 + 1 + read-only + + + COMP3 + COMP 3 Register Busy + 8 + 1 + read-only + + + COUNTSYNC + Count Synchronization Enable Bit Busy + 15 + 1 + read-only + + + GP0 + General Purpose 0 Register Busy + 16 + 1 + read-only + + + GP1 + General Purpose 1 Register Busy + 17 + 1 + read-only + + + GP2 + General Purpose 2 Register Busy + 18 + 1 + read-only + + + GP3 + General Purpose 3 Register Busy + 19 + 1 + read-only + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + COUNT + MODE1 Counter Value + 0x18 + 16 + + + COUNT + Counter Value + 0 + 16 + + + + + PER + MODE1 Counter Period + 0x1C + 16 + + + PER + Counter Period + 0 + 16 + + + + + 4 + 0x2 + COMP%s + MODE1 Compare n Value + 0x20 + 16 + + + COMP + Compare Value + 0 + 16 + + + + + 4 + 0x4 + GP%s + General Purpose + 0x40 + 32 + + + GP + General Purpose + 0 + 32 + + + + + TAMPCTRL + Tamper Control + 0x60 + 32 + + + IN0ACT + Tamper Input 0 Action + 0 + 2 + + IN0ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN0 to OUT + 0x3 + + + + + IN1ACT + Tamper Input 1 Action + 2 + 2 + + IN1ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN1 to OUT + 0x3 + + + + + IN2ACT + Tamper Input 2 Action + 4 + 2 + + IN2ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN2 to OUT + 0x3 + + + + + IN3ACT + Tamper Input 3 Action + 6 + 2 + + IN3ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN3 to OUT + 0x3 + + + + + IN4ACT + Tamper Input 4 Action + 8 + 2 + + IN4ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN4 to OUT + 0x3 + + + + + TAMLVL0 + Tamper Level Select 0 + 16 + 1 + + + TAMLVL1 + Tamper Level Select 1 + 17 + 1 + + + TAMLVL2 + Tamper Level Select 2 + 18 + 1 + + + TAMLVL3 + Tamper Level Select 3 + 19 + 1 + + + TAMLVL4 + Tamper Level Select 4 + 20 + 1 + + + DEBNC0 + Debouncer Enable 0 + 24 + 1 + + + DEBNC1 + Debouncer Enable 1 + 25 + 1 + + + DEBNC2 + Debouncer Enable 2 + 26 + 1 + + + DEBNC3 + Debouncer Enable 3 + 27 + 1 + + + DEBNC4 + Debouncer Enable 4 + 28 + 1 + + + + + TIMESTAMP + MODE1 Timestamp + 0x64 + 32 + read-only + + + COUNT + Count Timestamp Value + 0 + 16 + read-only + + + + + TAMPID + Tamper ID + 0x68 + 32 + + + TAMPID0 + Tamper Input 0 Detected + 0 + 1 + + + TAMPID1 + Tamper Input 1 Detected + 1 + 1 + + + TAMPID2 + Tamper Input 2 Detected + 2 + 1 + + + TAMPID3 + Tamper Input 3 Detected + 3 + 1 + + + TAMPID4 + Tamper Input 4 Detected + 4 + 1 + + + TAMPEVT + Tamper Event Detected + 31 + 1 + + + + + 8 + 0x4 + BKUP%s + Backup + 0x80 + 32 + + + BKUP + Backup + 0 + 32 + + + + + + MODE2 + Clock/Calendar with Alarm + MODE0 + RtcMode2 + 0x0 + + CTRLA + MODE2 Control A + 0x00 + 16 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 2 + + MODESelect + + COUNT32 + Mode 0: 32-bit Counter + 0x0 + + + COUNT16 + Mode 1: 16-bit Counter + 0x1 + + + CLOCK + Mode 2: Clock/Calendar + 0x2 + + + + + CLKREP + Clock Representation + 6 + 1 + + + MATCHCLR + Clear on Match + 7 + 1 + + + PRESCALER + Prescaler + 8 + 4 + + PRESCALERSelect + + OFF + CLK_RTC_CNT = GCLK_RTC/1 + 0x0 + + + DIV1 + CLK_RTC_CNT = GCLK_RTC/1 + 0x1 + + + DIV2 + CLK_RTC_CNT = GCLK_RTC/2 + 0x2 + + + DIV4 + CLK_RTC_CNT = GCLK_RTC/4 + 0x3 + + + DIV8 + CLK_RTC_CNT = GCLK_RTC/8 + 0x4 + + + DIV16 + CLK_RTC_CNT = GCLK_RTC/16 + 0x5 + + + DIV32 + CLK_RTC_CNT = GCLK_RTC/32 + 0x6 + + + DIV64 + CLK_RTC_CNT = GCLK_RTC/64 + 0x7 + + + DIV128 + CLK_RTC_CNT = GCLK_RTC/128 + 0x8 + + + DIV256 + CLK_RTC_CNT = GCLK_RTC/256 + 0x9 + + + DIV512 + CLK_RTC_CNT = GCLK_RTC/512 + 0xa + + + DIV1024 + CLK_RTC_CNT = GCLK_RTC/1024 + 0xb + + + + + BKTRST + BKUP Registers Reset On Tamper Enable + 13 + 1 + + + GPTRST + GP Registers Reset On Tamper Enable + 14 + 1 + + + CLOCKSYNC + Clock Read Synchronization Enable + 15 + 1 + + + + + CTRLB + MODE2 Control B + 0x02 + 16 + + + GP0EN + General Purpose 0 Enable + 0 + 1 + + + GP2EN + General Purpose 2 Enable + 1 + 1 + + + DEBMAJ + Debouncer Majority Enable + 4 + 1 + + + DEBASYNC + Debouncer Asynchronous Enable + 5 + 1 + + + RTCOUT + RTC Output Enable + 6 + 1 + + + DMAEN + DMA Enable + 7 + 1 + + + DEBF + Debounce Freqnuency + 8 + 3 + + DEBFSelect + + DIV2 + CLK_RTC_DEB = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_DEB = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_DEB = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_DEB = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_DEB = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_DEB = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_DEB = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_DEB = CLK_RTC/256 + 0x7 + + + + + ACTF + Active Layer Freqnuency + 12 + 3 + + ACTFSelect + + DIV2 + CLK_RTC_OUT = CLK_RTC/2 + 0x0 + + + DIV4 + CLK_RTC_OUT = CLK_RTC/4 + 0x1 + + + DIV8 + CLK_RTC_OUT = CLK_RTC/8 + 0x2 + + + DIV16 + CLK_RTC_OUT = CLK_RTC/16 + 0x3 + + + DIV32 + CLK_RTC_OUT = CLK_RTC/32 + 0x4 + + + DIV64 + CLK_RTC_OUT = CLK_RTC/64 + 0x5 + + + DIV128 + CLK_RTC_OUT = CLK_RTC/128 + 0x6 + + + DIV256 + CLK_RTC_OUT = CLK_RTC/256 + 0x7 + + + + + + + EVCTRL + MODE2 Event Control + 0x04 + 32 + + + PEREO0 + Periodic Interval 0 Event Output Enable + 0 + 1 + + + PEREO1 + Periodic Interval 1 Event Output Enable + 1 + 1 + + + PEREO2 + Periodic Interval 2 Event Output Enable + 2 + 1 + + + PEREO3 + Periodic Interval 3 Event Output Enable + 3 + 1 + + + PEREO4 + Periodic Interval 4 Event Output Enable + 4 + 1 + + + PEREO5 + Periodic Interval 5 Event Output Enable + 5 + 1 + + + PEREO6 + Periodic Interval 6 Event Output Enable + 6 + 1 + + + PEREO7 + Periodic Interval 7 Event Output Enable + 7 + 1 + + + ALARMEO0 + Alarm 0 Event Output Enable + 8 + 1 + + + ALARMEO1 + Alarm 1 Event Output Enable + 9 + 1 + + + TAMPEREO + Tamper Event Output Enable + 14 + 1 + + + OVFEO + Overflow Event Output Enable + 15 + 1 + + + TAMPEVEI + Tamper Event Input Enable + 16 + 1 + + + + + INTENCLR + MODE2 Interrupt Enable Clear + 0x08 + 16 + + + PER0 + Periodic Interval 0 Interrupt Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Interrupt Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Interrupt Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Interrupt Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Interrupt Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Interrupt Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Interrupt Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Interrupt Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + ALARM1 + Alarm 1 Interrupt Enable + 9 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTENSET + MODE2 Interrupt Enable Set + 0x0A + 16 + + + PER0 + Periodic Interval 0 Enable + 0 + 1 + + + PER1 + Periodic Interval 1 Enable + 1 + 1 + + + PER2 + Periodic Interval 2 Enable + 2 + 1 + + + PER3 + Periodic Interval 3 Enable + 3 + 1 + + + PER4 + Periodic Interval 4 Enable + 4 + 1 + + + PER5 + Periodic Interval 5 Enable + 5 + 1 + + + PER6 + Periodic Interval 6 Enable + 6 + 1 + + + PER7 + Periodic Interval 7 Enable + 7 + 1 + + + ALARM0 + Alarm 0 Interrupt Enable + 8 + 1 + + + ALARM1 + Alarm 1 Interrupt Enable + 9 + 1 + + + TAMPER + Tamper Enable + 14 + 1 + + + OVF + Overflow Interrupt Enable + 15 + 1 + + + + + INTFLAG + MODE2 Interrupt Flag Status and Clear + 0x0C + 16 + + + PER0 + Periodic Interval 0 + 0 + 1 + + + PER1 + Periodic Interval 1 + 1 + 1 + + + PER2 + Periodic Interval 2 + 2 + 1 + + + PER3 + Periodic Interval 3 + 3 + 1 + + + PER4 + Periodic Interval 4 + 4 + 1 + + + PER5 + Periodic Interval 5 + 5 + 1 + + + PER6 + Periodic Interval 6 + 6 + 1 + + + PER7 + Periodic Interval 7 + 7 + 1 + + + ALARM0 + Alarm 0 + 8 + 1 + + + ALARM1 + Alarm 1 + 9 + 1 + + + TAMPER + Tamper + 14 + 1 + + + OVF + Overflow + 15 + 1 + + + + + DBGCTRL + Debug Control + 0x0E + 8 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + MODE2 Synchronization Busy Status + 0x10 + 32 + read-only + + + SWRST + Software Reset Bit Busy + 0 + 1 + read-only + + + ENABLE + Enable Bit Busy + 1 + 1 + read-only + + + FREQCORR + FREQCORR Register Busy + 2 + 1 + read-only + + + CLOCK + CLOCK Register Busy + 3 + 1 + read-only + + + ALARM0 + ALARM 0 Register Busy + 5 + 1 + read-only + + + ALARM1 + ALARM 1 Register Busy + 6 + 1 + read-only + + + MASK0 + MASK 0 Register Busy + 11 + 1 + read-only + + + MASK1 + MASK 1 Register Busy + 12 + 1 + read-only + + + CLOCKSYNC + Clock Synchronization Enable Bit Busy + 15 + 1 + read-only + + + GP0 + General Purpose 0 Register Busy + 16 + 1 + read-only + + + GP1 + General Purpose 1 Register Busy + 17 + 1 + read-only + + + GP2 + General Purpose 2 Register Busy + 18 + 1 + read-only + + + GP3 + General Purpose 3 Register Busy + 19 + 1 + read-only + + + + + FREQCORR + Frequency Correction + 0x14 + 8 + + + VALUE + Correction Value + 0 + 7 + + + SIGN + Correction Sign + 7 + 1 + + + + + CLOCK + MODE2 Clock Value + 0x18 + 32 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x0 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + 2 + 0x8 + ALARM%s + MODE2 Alarm n Value + 0x20 + 32 + + + SECOND + Second + 0 + 6 + + + MINUTE + Minute + 6 + 6 + + + HOUR + Hour + 12 + 5 + + HOURSelect + + AM + Morning hour + 0x0 + + + PM + Afternoon hour + 0x10 + + + + + DAY + Day + 17 + 5 + + + MONTH + Month + 22 + 4 + + + YEAR + Year + 26 + 6 + + + + + 2 + 0x8 + MASK%s + MODE2 Alarm n Mask + 0x24 + 8 + + + SEL + Alarm Mask Selection + 0 + 3 + + SELSelect + + OFF + Alarm Disabled + 0x0 + + + SS + Match seconds only + 0x1 + + + MMSS + Match seconds and minutes only + 0x2 + + + HHMMSS + Match seconds, minutes, and hours only + 0x3 + + + DDHHMMSS + Match seconds, minutes, hours, and days only + 0x4 + + + MMDDHHMMSS + Match seconds, minutes, hours, days, and months only + 0x5 + + + YYMMDDHHMMSS + Match seconds, minutes, hours, days, months, and years + 0x6 + + + + + + + 4 + 0x4 + GP%s + General Purpose + 0x40 + 32 + + + GP + General Purpose + 0 + 32 + + + + + TAMPCTRL + Tamper Control + 0x60 + 32 + + + IN0ACT + Tamper Input 0 Action + 0 + 2 + + IN0ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN0 to OUT + 0x3 + + + + + IN1ACT + Tamper Input 1 Action + 2 + 2 + + IN1ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN1 to OUT + 0x3 + + + + + IN2ACT + Tamper Input 2 Action + 4 + 2 + + IN2ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN2 to OUT + 0x3 + + + + + IN3ACT + Tamper Input 3 Action + 6 + 2 + + IN3ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN3 to OUT + 0x3 + + + + + IN4ACT + Tamper Input 4 Action + 8 + 2 + + IN4ACTSelect + + OFF + Off (Disabled) + 0x0 + + + WAKE + Wake without timestamp + 0x1 + + + CAPTURE + Capture timestamp + 0x2 + + + ACTL + Compare IN4 to OUT + 0x3 + + + + + TAMLVL0 + Tamper Level Select 0 + 16 + 1 + + + TAMLVL1 + Tamper Level Select 1 + 17 + 1 + + + TAMLVL2 + Tamper Level Select 2 + 18 + 1 + + + TAMLVL3 + Tamper Level Select 3 + 19 + 1 + + + TAMLVL4 + Tamper Level Select 4 + 20 + 1 + + + DEBNC0 + Debouncer Enable 0 + 24 + 1 + + + DEBNC1 + Debouncer Enable 1 + 25 + 1 + + + DEBNC2 + Debouncer Enable 2 + 26 + 1 + + + DEBNC3 + Debouncer Enable 3 + 27 + 1 + + + DEBNC4 + Debouncer Enable 4 + 28 + 1 + + + + + TIMESTAMP + MODE2 Timestamp + 0x64 + 32 + read-only + + + SECOND + Second Timestamp Value + 0 + 6 + read-only + + + MINUTE + Minute Timestamp Value + 6 + 6 + read-only + + + HOUR + Hour Timestamp Value + 12 + 5 + read-only + + HOURSelect + + AM + AM when CLKREP in 12-hour + 0x0 + + + PM + PM when CLKREP in 12-hour + 0x10 + + + + + DAY + Day Timestamp Value + 17 + 5 + read-only + + + MONTH + Month Timestamp Value + 22 + 4 + read-only + + + YEAR + Year Timestamp Value + 26 + 6 + read-only + + + + + TAMPID + Tamper ID + 0x68 + 32 + + + TAMPID0 + Tamper Input 0 Detected + 0 + 1 + + + TAMPID1 + Tamper Input 1 Detected + 1 + 1 + + + TAMPID2 + Tamper Input 2 Detected + 2 + 1 + + + TAMPID3 + Tamper Input 3 Detected + 3 + 1 + + + TAMPID4 + Tamper Input 4 Detected + 4 + 1 + + + TAMPEVT + Tamper Event Detected + 31 + 1 + + + + + 8 + 0x4 + BKUP%s + Backup + 0x80 + 32 + + + BKUP + Backup + 0 + 32 + + + + + + + + SDHC0 + 1.8.3 + SD/MMC Host Controller + SDHC + SDHC_ + 0x45000000 + + 0 + 0x00000C00 + registers + + + SDHC0_INTREQ + 135 + + + + SSAR + SDMA System Address / Argument 2 + 0x000 + 32 + + + ADDR + SDMA System Address + 0 + 32 + + + + + SSAR_CMD23 + SDMA System Address / Argument 2 + SSAR + 0x000 + 32 + + + ARG2 + Argument 2 + 0 + 32 + + + + + BSR + Block Size + 0x004 + 16 + + + BLOCKSIZE + Transfer Block Size + 0 + 10 + + + BOUNDARY + SDMA Buffer Boundary + 12 + 3 + + BOUNDARYSelect + + 4K + 4k bytes + 0x0 + + + 8K + 8k bytes + 0x1 + + + 16K + 16k bytes + 0x2 + + + 32K + 32k bytes + 0x3 + + + 64K + 64k bytes + 0x4 + + + 128K + 128k bytes + 0x5 + + + 256K + 256k bytes + 0x6 + + + 512K + 512k bytes + 0x7 + + + + + + + BCR + Block Count + 0x006 + 16 + + + BCNT + Blocks Count for Current Transfer + 0 + 16 + + + + + ARG1R + Argument 1 + 0x008 + 32 + + + ARG + Argument 1 + 0 + 32 + + + + + TMR + Transfer Mode + 0x00C + 16 + + + DMAEN + DMA Enable + 0 + 1 + + DMAENSelect + + DISABLE + No data transfer or Non DMA data transfer + 0x0 + + + ENABLE + DMA data transfer + 0x1 + + + + + BCEN + Block Count Enable + 1 + 1 + + BCENSelect + + DISABLE + Disable + 0x0 + + + ENABLE + Enable + 0x1 + + + + + ACMDEN + Auto Command Enable + 2 + 2 + + ACMDENSelect + + DISABLED + Auto Command Disabled + 0x0 + + + CMD12 + Auto CMD12 Enable + 0x1 + + + CMD23 + Auto CMD23 Enable + 0x2 + + + + + DTDSEL + Data Transfer Direction Selection + 4 + 1 + + DTDSELSelect + + WRITE + Write (Host to Card) + 0x0 + + + READ + Read (Card to Host) + 0x1 + + + + + MSBSEL + Multi/Single Block Selection + 5 + 1 + + MSBSELSelect + + SINGLE + Single Block + 0x0 + + + MULTIPLE + Multiple Block + 0x1 + + + + + + + CR + Command + 0x00E + 16 + + + RESPTYP + Response Type + 0 + 2 + + RESPTYPSelect + + NONE + No response + 0x0 + + + 136_BIT + 136-bit response + 0x1 + + + 48_BIT + 48-bit response + 0x2 + + + 48_BIT_BUSY + 48-bit response check busy after response + 0x3 + + + + + CMDCCEN + Command CRC Check Enable + 3 + 1 + + CMDCCENSelect + + DISABLE + Disable + 0x0 + + + ENABLE + Enable + 0x1 + + + + + CMDICEN + Command Index Check Enable + 4 + 1 + + CMDICENSelect + + DISABLE + Disable + 0x0 + + + ENABLE + Enable + 0x1 + + + + + DPSEL + Data Present Select + 5 + 1 + + DPSELSelect + + NO_DATA + No Data Present + 0x0 + + + DATA + Data Present + 0x1 + + + + + CMDTYP + Command Type + 6 + 2 + + CMDTYPSelect + + NORMAL + Other commands + 0x0 + + + SUSPEND + CMD52 for writing Bus Suspend in CCCR + 0x1 + + + RESUME + CMD52 for writing Function Select in CCCR + 0x2 + + + ABORT + CMD12, CMD52 for writing I/O Abort in CCCR + 0x3 + + + + + CMDIDX + Command Index + 8 + 6 + + + + + 4 + 0x4 + RR%s + Response + 0x010 + 32 + read-only + + + CMDRESP + Command Response + 0 + 32 + + + + + BDPR + Buffer Data Port + 0x020 + 32 + + + BUFDATA + Buffer Data + 0 + 32 + + + + + PSR + Present State + 0x024 + 32 + read-only + 0x00F80000 + + + CMDINHC + Command Inhibit (CMD) + 0 + 1 + + CMDINHCSelect + + CAN + Can issue command using only CMD line + 0x0 + + + CANNOT + Cannot issue command + 0x1 + + + + + CMDINHD + Command Inhibit (DAT) + 1 + 1 + + CMDINHDSelect + + CAN + Can issue command which uses the DAT line + 0x0 + + + CANNOT + Cannot issue command which uses the DAT line + 0x1 + + + + + DLACT + DAT Line Active + 2 + 1 + + DLACTSelect + + INACTIVE + DAT Line Inactive + 0x0 + + + ACTIVE + DAT Line Active + 0x1 + + + + + RTREQ + Re-Tuning Request + 3 + 1 + + RTREQSelect + + OK + Fixed or well-tuned sampling clock + 0x0 + + + REQUIRED + Sampling clock needs re-tuning + 0x1 + + + + + WTACT + Write Transfer Active + 8 + 1 + + WTACTSelect + + NO + No valid data + 0x0 + + + YES + Transferring data + 0x1 + + + + + RTACT + Read Transfer Active + 9 + 1 + + RTACTSelect + + NO + No valid data + 0x0 + + + YES + Transferring data + 0x1 + + + + + BUFWREN + Buffer Write Enable + 10 + 1 + + BUFWRENSelect + + DISABLE + Write disable + 0x0 + + + ENABLE + Write enable + 0x1 + + + + + BUFRDEN + Buffer Read Enable + 11 + 1 + + BUFRDENSelect + + DISABLE + Read disable + 0x0 + + + ENABLE + Read enable + 0x1 + + + + + CARDINS + Card Inserted + 16 + 1 + + CARDINSSelect + + NO + Reset or Debouncing or No Card + 0x0 + + + YES + Card inserted + 0x1 + + + + + CARDSS + Card State Stable + 17 + 1 + + CARDSSSelect + + NO + Reset or Debouncing + 0x0 + + + YES + No Card or Insered + 0x1 + + + + + CARDDPL + Card Detect Pin Level + 18 + 1 + + CARDDPLSelect + + NO + No card present (SDCD#=1) + 0x0 + + + YES + Card present (SDCD#=0) + 0x1 + + + + + WRPPL + Write Protect Pin Level + 19 + 1 + + WRPPLSelect + + PROTECTED + Write protected (SDWP#=0) + 0x0 + + + ENABLED + Write enabled (SDWP#=1) + 0x1 + + + + + DATLL + DAT[3:0] Line Level + 20 + 4 + + + CMDLL + CMD Line Level + 24 + 1 + + + + + HC1R + Host Control 1 + 0x028 + 8 + 0xE00 + + + LEDCTRL + LED Control + 0 + 1 + + LEDCTRLSelect + + OFF + LED off + 0x0 + + + ON + LED on + 0x1 + + + + + DW + Data Width + 1 + 1 + + DWSelect + + 1BIT + 1-bit mode + 0x0 + + + 4BIT + 4-bit mode + 0x1 + + + + + HSEN + High Speed Enable + 2 + 1 + + HSENSelect + + NORMAL + Normal Speed mode + 0x0 + + + HIGH + High Speed mode + 0x1 + + + + + DMASEL + DMA Select + 3 + 2 + + DMASELSelect + + SDMA + SDMA is selected + 0x0 + + + 32BIT + 32-bit Address ADMA2 is selected + 0x2 + + + + + CARDDTL + Card Detect Test Level + 6 + 1 + + CARDDTLSelect + + NO + No Card + 0x0 + + + YES + Card Inserted + 0x1 + + + + + CARDDSEL + Card Detect Signal Selection + 7 + 1 + + CARDDSELSelect + + NORMAL + SDCD# is selected (for normal use) + 0x0 + + + TEST + The Card Select Test Level is selected (for test purpose) + 0x1 + + + + + + + HC1R_EMMC + Host Control 1 + HC1R + 0x028 + 8 + 0xE00 + + + DW + Data Width + 1 + 1 + + DWSelect + + 1BIT + 1-bit mode + 0x0 + + + 4BIT + 4-bit mode + 0x1 + + + + + HSEN + High Speed Enable + 2 + 1 + + HSENSelect + + NORMAL + Normal Speed mode + 0x0 + + + HIGH + High Speed mode + 0x1 + + + + + DMASEL + DMA Select + 3 + 2 + + DMASELSelect + + SDMA + SDMA is selected + 0x0 + + + 32BIT + 32-bit Address ADMA2 is selected + 0x2 + + + + + + + PCR + Power Control + 0x029 + 8 + 0x0E + + + SDBPWR + SD Bus Power + 0 + 1 + + SDBPWRSelect + + OFF + Power off + 0x0 + + + ON + Power on + 0x1 + + + + + SDBVSEL + SD Bus Voltage Select + 1 + 3 + + SDBVSELSelect + + 1V8 + 1.8V (Typ.) + 0x5 + + + 3V0 + 3.0V (Typ.) + 0x6 + + + 3V3 + 3.3V (Typ.) + 0x7 + + + + + + + BGCR + Block Gap Control + 0x02A + 8 + + + STPBGR + Stop at Block Gap Request + 0 + 1 + + STPBGRSelect + + TRANSFER + Transfer + 0x0 + + + STOP + Stop + 0x1 + + + + + CONTR + Continue Request + 1 + 1 + + CONTRSelect + + GO_ON + Not affected + 0x0 + + + RESTART + Restart + 0x1 + + + + + RWCTRL + Read Wait Control + 2 + 1 + + RWCTRLSelect + + DISABLE + Disable Read Wait Control + 0x0 + + + ENABLE + Enable Read Wait Control + 0x1 + + + + + INTBG + Interrupt at Block Gap + 3 + 1 + + INTBGSelect + + DISABLED + Disabled + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + + + BGCR_EMMC + Block Gap Control + BGCR + 0x02A + 8 + + + STPBGR + Stop at Block Gap Request + 0 + 1 + + STPBGRSelect + + TRANSFER + Transfer + 0x0 + + + STOP + Stop + 0x1 + + + + + CONTR + Continue Request + 1 + 1 + + CONTRSelect + + GO_ON + Not affected + 0x0 + + + RESTART + Restart + 0x1 + + + + + + + WCR + Wakeup Control + 0x02B + 8 + + + WKENCINT + Wakeup Event Enable on Card Interrupt + 0 + 1 + + WKENCINTSelect + + DISABLE + Disable + 0x0 + + + ENABLE + Enable + 0x1 + + + + + WKENCINS + Wakeup Event Enable on Card Insertion + 1 + 1 + + WKENCINSSelect + + DISABLE + Disable + 0x0 + + + ENABLE + Enable + 0x1 + + + + + WKENCREM + Wakeup Event Enable on Card Removal + 2 + 1 + + WKENCREMSelect + + DISABLE + Disable + 0x0 + + + ENABLE + Enable + 0x1 + + + + + + + CCR + Clock Control + 0x02C + 16 + + + INTCLKEN + Internal Clock Enable + 0 + 1 + + INTCLKENSelect + + OFF + Stop + 0x0 + + + ON + Oscillate + 0x1 + + + + + INTCLKS + Internal Clock Stable + 1 + 1 + read-only + + INTCLKSSelect + + NOT_READY + Not Ready + 0x0 + + + READY + Ready + 0x1 + + + + + SDCLKEN + SD Clock Enable + 2 + 1 + + SDCLKENSelect + + DISABLE + Disable + 0x0 + + + ENABLE + Enable + 0x1 + + + + + CLKGSEL + Clock Generator Select + 5 + 1 + + CLKGSELSelect + + DIV + Divided Clock Mode + 0x0 + + + PROG + Programmable Clock Mode + 0x1 + + + + + USDCLKFSEL + Upper Bits of SDCLK Frequency Select + 6 + 2 + + + SDCLKFSEL + SDCLK Frequency Select + 8 + 8 + + + + + TCR + Timeout Control + 0x02E + 8 + + + DTCVAL + Data Timeout Counter Value + 0 + 4 + + + + + SRR + Software Reset + 0x02F + 8 + + + SWRSTALL + Software Reset For All + 0 + 1 + + SWRSTALLSelect + + WORK + Work + 0x0 + + + RESET + Reset + 0x1 + + + + + SWRSTCMD + Software Reset For CMD Line + 1 + 1 + + SWRSTCMDSelect + + WORK + Work + 0x0 + + + RESET + Reset + 0x1 + + + + + SWRSTDAT + Software Reset For DAT Line + 2 + 1 + + SWRSTDATSelect + + WORK + Work + 0x0 + + + RESET + Reset + 0x1 + + + + + + + NISTR + Normal Interrupt Status + 0x030 + 16 + + + CMDC + Command Complete + 0 + 1 + + CMDCSelect + + NO + No command complete + 0x0 + + + YES + Command complete + 0x1 + + + + + TRFC + Transfer Complete + 1 + 1 + + TRFCSelect + + NO + Not complete + 0x0 + + + YES + Command execution is completed + 0x1 + + + + + BLKGE + Block Gap Event + 2 + 1 + + BLKGESelect + + NO + No Block Gap Event + 0x0 + + + STOP + Transaction stopped at block gap + 0x1 + + + + + DMAINT + DMA Interrupt + 3 + 1 + + DMAINTSelect + + NO + No DMA Interrupt + 0x0 + + + YES + DMA Interrupt is generated + 0x1 + + + + + BWRRDY + Buffer Write Ready + 4 + 1 + + BWRRDYSelect + + NO + Not ready to write buffer + 0x0 + + + YES + Ready to write buffer + 0x1 + + + + + BRDRDY + Buffer Read Ready + 5 + 1 + + BRDRDYSelect + + NO + Not ready to read buffer + 0x0 + + + YES + Ready to read buffer + 0x1 + + + + + CINS + Card Insertion + 6 + 1 + + CINSSelect + + NO + Card state stable or Debouncing + 0x0 + + + YES + Card inserted + 0x1 + + + + + CREM + Card Removal + 7 + 1 + + CREMSelect + + NO + Card state stable or Debouncing + 0x0 + + + YES + Card Removed + 0x1 + + + + + CINT + Card Interrupt + 8 + 1 + read-only + + CINTSelect + + NO + No Card Interrupt + 0x0 + + + YES + Generate Card Interrupt + 0x1 + + + + + ERRINT + Error Interrupt + 15 + 1 + read-only + + ERRINTSelect + + NO + No Error + 0x0 + + + YES + Error + 0x1 + + + + + + + NISTR_EMMC + Normal Interrupt Status + NISTR + 0x030 + 16 + + + CMDC + Command Complete + 0 + 1 + + CMDCSelect + + NO + No command complete + 0x0 + + + YES + Command complete + 0x1 + + + + + TRFC + Transfer Complete + 1 + 1 + + TRFCSelect + + NO + Not complete + 0x0 + + + YES + Command execution is completed + 0x1 + + + + + BLKGE + Block Gap Event + 2 + 1 + + BLKGESelect + + NO + No Block Gap Event + 0x0 + + + STOP + Transaction stopped at block gap + 0x1 + + + + + DMAINT + DMA Interrupt + 3 + 1 + + DMAINTSelect + + NO + No DMA Interrupt + 0x0 + + + YES + DMA Interrupt is generated + 0x1 + + + + + BWRRDY + Buffer Write Ready + 4 + 1 + + BWRRDYSelect + + NO + Not ready to write buffer + 0x0 + + + YES + Ready to write buffer + 0x1 + + + + + BRDRDY + Buffer Read Ready + 5 + 1 + + BRDRDYSelect + + NO + Not ready to read buffer + 0x0 + + + YES + Ready to read buffer + 0x1 + + + + + BOOTAR + Boot Acknowledge Received + 14 + 1 + + + ERRINT + Error Interrupt + 15 + 1 + read-only + + ERRINTSelect + + NO + No Error + 0x0 + + + YES + Error + 0x1 + + + + + + + EISTR + Error Interrupt Status + 0x032 + 16 + + + CMDTEO + Command Timeout Error + 0 + 1 + + CMDTEOSelect + + NO + No Error + 0x0 + + + YES + Timeout + 0x1 + + + + + CMDCRC + Command CRC Error + 1 + 1 + + CMDCRCSelect + + NO + No Error + 0x0 + + + YES + CRC Error Generated + 0x1 + + + + + CMDEND + Command End Bit Error + 2 + 1 + + CMDENDSelect + + NO + No error + 0x0 + + + YES + End Bit Error Generated + 0x1 + + + + + CMDIDX + Command Index Error + 3 + 1 + + CMDIDXSelect + + NO + No Error + 0x0 + + + YES + Error + 0x1 + + + + + DATTEO + Data Timeout Error + 4 + 1 + + DATTEOSelect + + NO + No Error + 0x0 + + + YES + Timeout + 0x1 + + + + + DATCRC + Data CRC Error + 5 + 1 + + DATCRCSelect + + NO + No Error + 0x0 + + + YES + Error + 0x1 + + + + + DATEND + Data End Bit Error + 6 + 1 + + DATENDSelect + + NO + No Error + 0x0 + + + YES + Error + 0x1 + + + + + CURLIM + Current Limit Error + 7 + 1 + + CURLIMSelect + + NO + No Error + 0x0 + + + YES + Power Fail + 0x1 + + + + + ACMD + Auto CMD Error + 8 + 1 + + ACMDSelect + + NO + No Error + 0x0 + + + YES + Error + 0x1 + + + + + ADMA + ADMA Error + 9 + 1 + + ADMASelect + + NO + No Error + 0x0 + + + YES + Error + 0x1 + + + + + + + EISTR_EMMC + Error Interrupt Status + EISTR + 0x032 + 16 + + + CMDTEO + Command Timeout Error + 0 + 1 + + CMDTEOSelect + + NO + No Error + 0x0 + + + YES + Timeout + 0x1 + + + + + CMDCRC + Command CRC Error + 1 + 1 + + CMDCRCSelect + + NO + No Error + 0x0 + + + YES + CRC Error Generated + 0x1 + + + + + CMDEND + Command End Bit Error + 2 + 1 + + CMDENDSelect + + NO + No error + 0x0 + + + YES + End Bit Error Generated + 0x1 + + + + + CMDIDX + Command Index Error + 3 + 1 + + CMDIDXSelect + + NO + No Error + 0x0 + + + YES + Error + 0x1 + + + + + DATTEO + Data Timeout Error + 4 + 1 + + DATTEOSelect + + NO + No Error + 0x0 + + + YES + Timeout + 0x1 + + + + + DATCRC + Data CRC Error + 5 + 1 + + DATCRCSelect + + NO + No Error + 0x0 + + + YES + Error + 0x1 + + + + + DATEND + Data End Bit Error + 6 + 1 + + DATENDSelect + + NO + No Error + 0x0 + + + YES + Error + 0x1 + + + + + CURLIM + Current Limit Error + 7 + 1 + + CURLIMSelect + + NO + No Error + 0x0 + + + YES + Power Fail + 0x1 + + + + + ACMD + Auto CMD Error + 8 + 1 + + ACMDSelect + + NO + No Error + 0x0 + + + YES + Error + 0x1 + + + + + ADMA + ADMA Error + 9 + 1 + + ADMASelect + + NO + No Error + 0x0 + + + YES + Error + 0x1 + + + + + BOOTAE + Boot Acknowledge Error + 12 + 1 + + BOOTAESelect + + 0 + FIFO contains at least one byte + 0x0 + + + 1 + FIFO is empty + 0x1 + + + + + + + NISTER + Normal Interrupt Status Enable + 0x034 + 16 + + + CMDC + Command Complete Status Enable + 0 + 1 + + CMDCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + TRFC + Transfer Complete Status Enable + 1 + 1 + + TRFCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BLKGE + Block Gap Event Status Enable + 2 + 1 + + BLKGESelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DMAINT + DMA Interrupt Status Enable + 3 + 1 + + DMAINTSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BWRRDY + Buffer Write Ready Status Enable + 4 + 1 + + BWRRDYSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BRDRDY + Buffer Read Ready Status Enable + 5 + 1 + + BRDRDYSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CINS + Card Insertion Status Enable + 6 + 1 + + CINSSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CREM + Card Removal Status Enable + 7 + 1 + + CREMSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CINT + Card Interrupt Status Enable + 8 + 1 + + CINTSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + + + NISTER_EMMC + Normal Interrupt Status Enable + NISTER + 0x034 + 16 + + + CMDC + Command Complete Status Enable + 0 + 1 + + CMDCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + TRFC + Transfer Complete Status Enable + 1 + 1 + + TRFCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BLKGE + Block Gap Event Status Enable + 2 + 1 + + BLKGESelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DMAINT + DMA Interrupt Status Enable + 3 + 1 + + DMAINTSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BWRRDY + Buffer Write Ready Status Enable + 4 + 1 + + BWRRDYSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BRDRDY + Buffer Read Ready Status Enable + 5 + 1 + + BRDRDYSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BOOTAR + Boot Acknowledge Received Status Enable + 14 + 1 + + + + + EISTER + Error Interrupt Status Enable + 0x036 + 16 + + + CMDTEO + Command Timeout Error Status Enable + 0 + 1 + + CMDTEOSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CMDCRC + Command CRC Error Status Enable + 1 + 1 + + CMDCRCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CMDEND + Command End Bit Error Status Enable + 2 + 1 + + CMDENDSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CMDIDX + Command Index Error Status Enable + 3 + 1 + + CMDIDXSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DATTEO + Data Timeout Error Status Enable + 4 + 1 + + DATTEOSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DATCRC + Data CRC Error Status Enable + 5 + 1 + + DATCRCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DATEND + Data End Bit Error Status Enable + 6 + 1 + + DATENDSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CURLIM + Current Limit Error Status Enable + 7 + 1 + + CURLIMSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + ACMD + Auto CMD Error Status Enable + 8 + 1 + + ACMDSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + ADMA + ADMA Error Status Enable + 9 + 1 + + ADMASelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + + + EISTER_EMMC + Error Interrupt Status Enable + EISTER + 0x036 + 16 + + + CMDTEO + Command Timeout Error Status Enable + 0 + 1 + + CMDTEOSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CMDCRC + Command CRC Error Status Enable + 1 + 1 + + CMDCRCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CMDEND + Command End Bit Error Status Enable + 2 + 1 + + CMDENDSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CMDIDX + Command Index Error Status Enable + 3 + 1 + + CMDIDXSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DATTEO + Data Timeout Error Status Enable + 4 + 1 + + DATTEOSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DATCRC + Data CRC Error Status Enable + 5 + 1 + + DATCRCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DATEND + Data End Bit Error Status Enable + 6 + 1 + + DATENDSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CURLIM + Current Limit Error Status Enable + 7 + 1 + + CURLIMSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + ACMD + Auto CMD Error Status Enable + 8 + 1 + + ACMDSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + ADMA + ADMA Error Status Enable + 9 + 1 + + ADMASelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BOOTAE + Boot Acknowledge Error Status Enable + 12 + 1 + + + + + NISIER + Normal Interrupt Signal Enable + 0x038 + 16 + + + CMDC + Command Complete Signal Enable + 0 + 1 + + CMDCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + TRFC + Transfer Complete Signal Enable + 1 + 1 + + TRFCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BLKGE + Block Gap Event Signal Enable + 2 + 1 + + BLKGESelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DMAINT + DMA Interrupt Signal Enable + 3 + 1 + + DMAINTSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BWRRDY + Buffer Write Ready Signal Enable + 4 + 1 + + BWRRDYSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BRDRDY + Buffer Read Ready Signal Enable + 5 + 1 + + BRDRDYSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CINS + Card Insertion Signal Enable + 6 + 1 + + CINSSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CREM + Card Removal Signal Enable + 7 + 1 + + CREMSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CINT + Card Interrupt Signal Enable + 8 + 1 + + CINTSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + + + NISIER_EMMC + Normal Interrupt Signal Enable + NISIER + 0x038 + 16 + + + CMDC + Command Complete Signal Enable + 0 + 1 + + CMDCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + TRFC + Transfer Complete Signal Enable + 1 + 1 + + TRFCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BLKGE + Block Gap Event Signal Enable + 2 + 1 + + BLKGESelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DMAINT + DMA Interrupt Signal Enable + 3 + 1 + + DMAINTSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BWRRDY + Buffer Write Ready Signal Enable + 4 + 1 + + BWRRDYSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BRDRDY + Buffer Read Ready Signal Enable + 5 + 1 + + BRDRDYSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BOOTAR + Boot Acknowledge Received Signal Enable + 14 + 1 + + + + + EISIER + Error Interrupt Signal Enable + 0x03A + 16 + + + CMDTEO + Command Timeout Error Signal Enable + 0 + 1 + + CMDTEOSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CMDCRC + Command CRC Error Signal Enable + 1 + 1 + + CMDCRCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CMDEND + Command End Bit Error Signal Enable + 2 + 1 + + CMDENDSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CMDIDX + Command Index Error Signal Enable + 3 + 1 + + CMDIDXSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DATTEO + Data Timeout Error Signal Enable + 4 + 1 + + DATTEOSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DATCRC + Data CRC Error Signal Enable + 5 + 1 + + DATCRCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DATEND + Data End Bit Error Signal Enable + 6 + 1 + + DATENDSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CURLIM + Current Limit Error Signal Enable + 7 + 1 + + CURLIMSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + ACMD + Auto CMD Error Signal Enable + 8 + 1 + + ACMDSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + ADMA + ADMA Error Signal Enable + 9 + 1 + + ADMASelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + + + EISIER_EMMC + Error Interrupt Signal Enable + EISIER + 0x03A + 16 + + + CMDTEO + Command Timeout Error Signal Enable + 0 + 1 + + CMDTEOSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CMDCRC + Command CRC Error Signal Enable + 1 + 1 + + CMDCRCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CMDEND + Command End Bit Error Signal Enable + 2 + 1 + + CMDENDSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CMDIDX + Command Index Error Signal Enable + 3 + 1 + + CMDIDXSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DATTEO + Data Timeout Error Signal Enable + 4 + 1 + + DATTEOSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DATCRC + Data CRC Error Signal Enable + 5 + 1 + + DATCRCSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + DATEND + Data End Bit Error Signal Enable + 6 + 1 + + DATENDSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + CURLIM + Current Limit Error Signal Enable + 7 + 1 + + CURLIMSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + ACMD + Auto CMD Error Signal Enable + 8 + 1 + + ACMDSelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + ADMA + ADMA Error Signal Enable + 9 + 1 + + ADMASelect + + MASKED + Masked + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + BOOTAE + Boot Acknowledge Error Signal Enable + 12 + 1 + + + + + ACESR + Auto CMD Error Status + 0x03C + 16 + read-only + + + ACMD12NE + Auto CMD12 Not Executed + 0 + 1 + read-only + + ACMD12NESelect + + EXEC + Executed + 0x0 + + + NOT_EXEC + Not executed + 0x1 + + + + + ACMDTEO + Auto CMD Timeout Error + 1 + 1 + read-only + + ACMDTEOSelect + + NO + No error + 0x0 + + + YES + Timeout + 0x1 + + + + + ACMDCRC + Auto CMD CRC Error + 2 + 1 + read-only + + ACMDCRCSelect + + NO + No error + 0x0 + + + YES + CRC Error Generated + 0x1 + + + + + ACMDEND + Auto CMD End Bit Error + 3 + 1 + read-only + + ACMDENDSelect + + NO + No error + 0x0 + + + YES + End Bit Error Generated + 0x1 + + + + + ACMDIDX + Auto CMD Index Error + 4 + 1 + read-only + + ACMDIDXSelect + + NO + No error + 0x0 + + + YES + Error + 0x1 + + + + + CMDNI + Command not Issued By Auto CMD12 Error + 7 + 1 + read-only + + CMDNISelect + + OK + No error + 0x0 + + + NOT_ISSUED + Not Issued + 0x1 + + + + + + + HC2R + Host Control 2 + 0x03E + 16 + + + UHSMS + UHS Mode Select + 0 + 3 + + UHSMSSelect + + SDR12 + SDR12 + 0x0 + + + SDR25 + SDR25 + 0x1 + + + SDR50 + SDR50 + 0x2 + + + SDR104 + SDR104 + 0x3 + + + DDR50 + DDR50 + 0x4 + + + + + VS18EN + 1.8V Signaling Enable + 3 + 1 + + VS18ENSelect + + S33V + 3.3V Signaling + 0x0 + + + S18V + 1.8V Signaling + 0x1 + + + + + DRVSEL + Driver Strength Select + 4 + 2 + + DRVSELSelect + + B + Driver Type B is Selected (Default) + 0x0 + + + A + Driver Type A is Selected + 0x1 + + + C + Driver Type C is Selected + 0x2 + + + D + Driver Type D is Selected + 0x3 + + + + + EXTUN + Execute Tuning + 6 + 1 + + EXTUNSelect + + NO + Not Tuned or Tuning Completed + 0x0 + + + REQUESTED + Execute Tuning + 0x1 + + + + + SLCKSEL + Sampling Clock Select + 7 + 1 + + SLCKSELSelect + + FIXED + Fixed clock is used to sample data + 0x0 + + + TUNED + Tuned clock is used to sample data + 0x1 + + + + + ASINTEN + Asynchronous Interrupt Enable + 14 + 1 + + ASINTENSelect + + DISABLED + Disabled + 0x0 + + + ENABLED + Enabled + 0x1 + + + + + PVALEN + Preset Value Enable + 15 + 1 + + PVALENSelect + + HOST + SDCLK and Driver Strength are controlled by Host Controller + 0x0 + + + AUTO + Automatic Selection by Preset Value is Enabled + 0x1 + + + + + + + HC2R_EMMC + Host Control 2 + HC2R + 0x03E + 16 + + + HS200EN + HS200 Mode Enable + 0 + 4 + + HS200ENSelect + + SDR12 + SDR12 + 0x0 + + + SDR25 + SDR25 + 0x1 + + + SDR50 + SDR50 + 0x2 + + + SDR104 + SDR104 + 0x3 + + + DDR50 + DDR50 + 0x4 + + + + + DRVSEL + Driver Strength Select + 4 + 2 + + DRVSELSelect + + B + Driver Type B is Selected (Default) + 0x0 + + + A + Driver Type A is Selected + 0x1 + + + C + Driver Type C is Selected + 0x2 + + + D + Driver Type D is Selected + 0x3 + + + + + EXTUN + Execute Tuning + 6 + 1 + + EXTUNSelect + + NO + Not Tuned or Tuning Completed + 0x0 + + + REQUESTED + Execute Tuning + 0x1 + + + + + SLCKSEL + Sampling Clock Select + 7 + 1 + + SLCKSELSelect + + FIXED + Fixed clock is used to sample data + 0x0 + + + TUNED + Tuned clock is used to sample data + 0x1 + + + + + PVALEN + Preset Value Enable + 15 + 1 + + PVALENSelect + + HOST + SDCLK and Driver Strength are controlled by Host Controller + 0x0 + + + AUTO + Automatic Selection by Preset Value is Enabled + 0x1 + + + + + + + CA0R + Capabilities 0 + 0x040 + 32 + read-only + 0x27E80080 + + + TEOCLKF + Timeout Clock Frequency + 0 + 6 + + TEOCLKFSelect + + OTHER + Get information via another method + 0x0 + + + + + TEOCLKU + Timeout Clock Unit + 7 + 1 + + TEOCLKUSelect + + KHZ + kHz + 0x0 + + + MHZ + MHz + 0x1 + + + + + BASECLKF + Base Clock Frequency + 8 + 8 + + BASECLKFSelect + + OTHER + Get information via another method + 0x0 + + + + + MAXBLKL + Max Block Length + 16 + 2 + + MAXBLKLSelect + + 512 + 512 bytes + 0x0 + + + 1024 + 1024 bytes + 0x1 + + + 2048 + 2048 bytes + 0x2 + + + + + ED8SUP + 8-bit Support for Embedded Device + 18 + 1 + + ED8SUPSelect + + NO + 8-bit Bus Width not Supported + 0x0 + + + YES + 8-bit Bus Width Supported + 0x1 + + + + + ADMA2SUP + ADMA2 Support + 19 + 1 + + ADMA2SUPSelect + + NO + ADMA2 not Supported + 0x0 + + + YES + ADMA2 Supported + 0x1 + + + + + HSSUP + High Speed Support + 21 + 1 + + HSSUPSelect + + NO + High Speed not Supported + 0x0 + + + YES + High Speed Supported + 0x1 + + + + + SDMASUP + SDMA Support + 22 + 1 + + SDMASUPSelect + + NO + SDMA not Supported + 0x0 + + + YES + SDMA Supported + 0x1 + + + + + SRSUP + Suspend/Resume Support + 23 + 1 + + SRSUPSelect + + NO + Suspend/Resume not Supported + 0x0 + + + YES + Suspend/Resume Supported + 0x1 + + + + + V33VSUP + Voltage Support 3.3V + 24 + 1 + + V33VSUPSelect + + NO + 3.3V Not Supported + 0x0 + + + YES + 3.3V Supported + 0x1 + + + + + V30VSUP + Voltage Support 3.0V + 25 + 1 + + V30VSUPSelect + + NO + 3.0V Not Supported + 0x0 + + + YES + 3.0V Supported + 0x1 + + + + + V18VSUP + Voltage Support 1.8V + 26 + 1 + + V18VSUPSelect + + NO + 1.8V Not Supported + 0x0 + + + YES + 1.8V Supported + 0x1 + + + + + SB64SUP + 64-Bit System Bus Support + 28 + 1 + + SB64SUPSelect + + NO + 32-bit Address Descriptors and System Bus + 0x0 + + + YES + 64-bit Address Descriptors and System Bus + 0x1 + + + + + ASINTSUP + Asynchronous Interrupt Support + 29 + 1 + + ASINTSUPSelect + + NO + Asynchronous Interrupt not Supported + 0x0 + + + YES + Asynchronous Interrupt supported + 0x1 + + + + + SLTYPE + Slot Type + 30 + 2 + + SLTYPESelect + + REMOVABLE + Removable Card Slot + 0x0 + + + EMBEDDED + Embedded Slot for One Device + 0x1 + + + + + + + CA1R + Capabilities 1 + 0x044 + 32 + read-only + 0x00000070 + + + SDR50SUP + SDR50 Support + 0 + 1 + + SDR50SUPSelect + + NO + SDR50 is Not Supported + 0x0 + + + YES + SDR50 is Supported + 0x1 + + + + + SDR104SUP + SDR104 Support + 1 + 1 + + SDR104SUPSelect + + NO + SDR104 is Not Supported + 0x0 + + + YES + SDR104 is Supported + 0x1 + + + + + DDR50SUP + DDR50 Support + 2 + 1 + + DDR50SUPSelect + + NO + DDR50 is Not Supported + 0x0 + + + YES + DDR50 is Supported + 0x1 + + + + + DRVASUP + Driver Type A Support + 4 + 1 + + DRVASUPSelect + + NO + Driver Type A is Not Supported + 0x0 + + + YES + Driver Type A is Supported + 0x1 + + + + + DRVCSUP + Driver Type C Support + 5 + 1 + + DRVCSUPSelect + + NO + Driver Type C is Not Supported + 0x0 + + + YES + Driver Type C is Supported + 0x1 + + + + + DRVDSUP + Driver Type D Support + 6 + 1 + + DRVDSUPSelect + + NO + Driver Type D is Not Supported + 0x0 + + + YES + Driver Type D is Supported + 0x1 + + + + + TCNTRT + Timer Count for Re-Tuning + 8 + 4 + + TCNTRTSelect + + DISABLED + Re-Tuning Timer disabled + 0x0 + + + 1S + 1 second + 0x1 + + + 2S + 2 seconds + 0x2 + + + 4S + 4 seconds + 0x3 + + + 8S + 8 seconds + 0x4 + + + 16S + 16 seconds + 0x5 + + + 32S + 32 seconds + 0x6 + + + 64S + 64 seconds + 0x7 + + + 128S + 128 seconds + 0x8 + + + 256S + 256 seconds + 0x9 + + + 512S + 512 seconds + 0xa + + + 1024S + 1024 seconds + 0xb + + + OTHER + Get information from other source + 0xf + + + + + TSDR50 + Use Tuning for SDR50 + 13 + 1 + + TSDR50Select + + NO + SDR50 does not require tuning + 0x0 + + + YES + SDR50 requires tuning + 0x1 + + + + + CLKMULT + Clock Multiplier + 16 + 8 + + CLKMULTSelect + + NO + Clock Multiplier is Not Supported + 0x0 + + + + + + + MCCAR + Maximum Current Capabilities + 0x048 + 32 + read-only + + + MAXCUR33V + Maximum Current for 3.3V + 0 + 8 + + MAXCUR33VSelect + + OTHER + Get information via another method + 0x0 + + + 4MA + 4mA + 0x1 + + + 8MA + 8mA + 0x2 + + + 12MA + 12mA + 0x3 + + + + + MAXCUR30V + Maximum Current for 3.0V + 8 + 8 + + MAXCUR30VSelect + + OTHER + Get information via another method + 0x0 + + + 4MA + 4mA + 0x1 + + + 8MA + 8mA + 0x2 + + + 12MA + 12mA + 0x3 + + + + + MAXCUR18V + Maximum Current for 1.8V + 16 + 8 + + MAXCUR18VSelect + + OTHER + Get information via another method + 0x0 + + + 4MA + 4mA + 0x1 + + + 8MA + 8mA + 0x2 + + + 12MA + 12mA + 0x3 + + + + + + + FERACES + Force Event for Auto CMD Error Status + 0x050 + 16 + write-only + + + ACMD12NE + Force Event for Auto CMD12 Not Executed + 0 + 1 + + ACMD12NESelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + ACMDTEO + Force Event for Auto CMD Timeout Error + 1 + 1 + + ACMDTEOSelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + ACMDCRC + Force Event for Auto CMD CRC Error + 2 + 1 + + ACMDCRCSelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + ACMDEND + Force Event for Auto CMD End Bit Error + 3 + 1 + + ACMDENDSelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + ACMDIDX + Force Event for Auto CMD Index Error + 4 + 1 + + ACMDIDXSelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + CMDNI + Force Event for Command Not Issued By Auto CMD12 Error + 7 + 1 + + CMDNISelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + + + FEREIS + Force Event for Error Interrupt Status + 0x052 + 16 + write-only + + + CMDTEO + Force Event for Command Timeout Error + 0 + 1 + + CMDTEOSelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + CMDCRC + Force Event for Command CRC Error + 1 + 1 + + CMDCRCSelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + CMDEND + Force Event for Command End Bit Error + 2 + 1 + + CMDENDSelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + CMDIDX + Force Event for Command Index Error + 3 + 1 + + CMDIDXSelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + DATTEO + Force Event for Data Timeout Error + 4 + 1 + + DATTEOSelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + DATCRC + Force Event for Data CRC Error + 5 + 1 + + DATCRCSelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + DATEND + Force Event for Data End Bit Error + 6 + 1 + + DATENDSelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + CURLIM + Force Event for Current Limit Error + 7 + 1 + + CURLIMSelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + ACMD + Force Event for Auto CMD Error + 8 + 1 + + ACMDSelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + ADMA + Force Event for ADMA Error + 9 + 1 + + ADMASelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + BOOTAE + Force Event for Boot Acknowledge Error + 12 + 1 + + BOOTAESelect + + NO + No Interrupt + 0x0 + + + YES + Interrupt is generated + 0x1 + + + + + + + AESR + ADMA Error Status + 0x054 + 8 + read-only + + + ERRST + ADMA Error State + 0 + 2 + + ERRSTSelect + + STOP + ST_STOP (Stop DMA) + 0x0 + + + FDS + ST_FDS (Fetch Descriptor) + 0x1 + + + TFR + ST_TFR (Transfer Data) + 0x3 + + + + + LMIS + ADMA Length Mismatch Error + 2 + 1 + + LMISSelect + + NO + No Error + 0x0 + + + YES + Error + 0x1 + + + + + + + 1 + 0x4 + ASAR%s + ADMA System Address n + 0x058 + 32 + + + ADMASA + ADMA System Address + 0 + 32 + + + + + 8 + 0x2 + PVR%s + Preset Value n + 0x060 + 16 + + + SDCLKFSEL + SDCLK Frequency Select Value for Initialization + 0 + 10 + + + CLKGSEL + Clock Generator Select Value for Initialization + 10 + 1 + + CLKGSELSelect + + DIV + Host Controller Ver2.00 Compatible Clock Generator (Divider) + 0x0 + + + PROG + Programmable Clock Generator + 0x1 + + + + + DRVSEL + Driver Strength Select Value for Initialization + 14 + 2 + + DRVSELSelect + + B + Driver Type B is Selected + 0x0 + + + A + Driver Type A is Selected + 0x1 + + + C + Driver Type C is Selected + 0x2 + + + D + Driver Type D is Selected + 0x3 + + + + + + + SISR + Slot Interrupt Status + 0x0FC + 16 + read-only + 0x20000 + + + INTSSL + Interrupt Signal for Each Slot + 0 + 1 + + + + + HCVR + Host Controller Version + 0x0FE + 16 + read-only + 0x1802 + + + SVER + Spec Version + 0 + 8 + + + VVER + Vendor Version + 8 + 8 + + + + + MC1R + MMC Control 1 + 0x204 + 8 + + + CMDTYP + e.MMC Command Type + 0 + 2 + + CMDTYPSelect + + NORMAL + Not a MMC specific command + 0x0 + + + WAITIRQ + Wait IRQ Command + 0x1 + + + STREAM + Stream Command + 0x2 + + + BOOT + Boot Command + 0x3 + + + + + DDR + e.MMC HSDDR Mode + 3 + 1 + + + OPD + e.MMC Open Drain Mode + 4 + 1 + + + BOOTA + e.MMC Boot Acknowledge Enable + 5 + 1 + + + RSTN + e.MMC Reset Signal + 6 + 1 + + + FCD + e.MMC Force Card Detect + 7 + 1 + + + + + MC2R + MMC Control 2 + 0x205 + 8 + write-only + + + SRESP + e.MMC Abort Wait IRQ + 0 + 1 + + + ABOOT + e.MMC Abort Boot + 1 + 1 + + + + + ACR + AHB Control + 0x208 + 32 + + + BMAX + AHB Maximum Burst + 0 + 2 + + BMAXSelect + + INCR16 + 0x0 + + + INCR8 + 0x1 + + + INCR4 + 0x2 + + + SINGLE + 0x3 + + + + + + + CC2R + Clock Control 2 + 0x20C + 32 + + + FSDCLKD + Force SDCK Disabled + 0 + 1 + + FSDCLKDSelect + + NOEFFECT + No effect + 0x0 + + + DISABLE + SDCLK can be stopped at any time after DATA transfer.SDCLK enable forcing for 8 SDCLK cycles is disabled + 0x1 + + + + + + + CACR + Capabilities Control + 0x230 + 32 + + + CAPWREN + Capabilities Registers Write Enable (Required to write the correct frequencies in the Capabilities Registers) + 0 + 1 + + + KEY + Key (0x46) + 8 + 8 + + + + + DBGR + Debug + 0x234 + 8 + + + NIDBG + Non-intrusive debug enable + 0 + 1 + + NIDBGSelect + + IDBG + Debugging is intrusive (reads of BDPR from debugger are considered and increment the internal buffer pointer) + 0x0 + + + NIDBG + Debugging is not intrusive (reads of BDPR from debugger are discarded and do not increment the internal buffer pointer) + 0x1 + + + + + + + + + SERCOM0 + 5.0.0 + Serial Communication Interface 0 + SERCOM + SERCOM_ + 0x40003000 + + 0 + 0x40 + registers + + + SERCOM0_INTREQ_0 + 46 + + + SERCOM0_INTREQ_1 + 47 + + + SERCOM0_INTREQ_2 + 48 + + + SERCOM0_INTREQ_3 + 49 + + + + I2CM + I2C Master Mode + SercomI2cm + 0x0 + + CTRLA + I2CM Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + + RUNSTDBY + Run in Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + + MEXTTOEN + Master SCL Low Extend Timeout + 22 + 1 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + INACTOUT + Inactive Time-Out + 28 + 2 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CM Control B + 0x04 + 32 + + + SMEN + Smart Mode Enable + 8 + 1 + + + QCEN + Quick Command Enable + 9 + 1 + + + CMD + Command + 16 + 2 + write-only + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + CTRLC + I2CM Control C + 0x08 + 32 + + + DATA32B + Data 32 Bit + 24 + 1 + + + + + BAUD + I2CM Baud Rate + 0x0C + 32 + + + BAUD + Baud Rate Value + 0 + 8 + + + BAUDLOW + Baud Rate Value Low + 8 + 8 + + + HSBAUD + High Speed Baud Rate Value + 16 + 8 + + + HSBAUDLOW + High Speed Baud Rate Value Low + 24 + 8 + + + + + INTENCLR + I2CM Interrupt Enable Clear + 0x14 + 8 + + + MB + Master On Bus Interrupt Disable + 0 + 1 + + + SB + Slave On Bus Interrupt Disable + 1 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CM Interrupt Enable Set + 0x16 + 8 + + + MB + Master On Bus Interrupt Enable + 0 + 1 + + + SB + Slave On Bus Interrupt Enable + 1 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CM Interrupt Flag Status and Clear + 0x18 + 8 + + + MB + Master On Bus Interrupt + 0 + 1 + + + SB + Slave On Bus Interrupt + 1 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CM Status + 0x1A + 16 + + + BUSERR + Bus Error + 0 + 1 + + + ARBLOST + Arbitration Lost + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + read-only + + + BUSSTATE + Bus State + 4 + 2 + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + read-only + + + MEXTTOUT + Master SCL Low Extend Timeout + 8 + 1 + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + LENERR + Length Error + 10 + 1 + + + + + SYNCBUSY + I2CM Synchronization Busy + 0x1C + 32 + read-only + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + read-only + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + read-only + + + SYSOP + System Operation Synchronization Busy + 2 + 1 + read-only + + + LENGTH + Length Synchronization Busy + 4 + 1 + read-only + + + + + ADDR + I2CM Address + 0x24 + 32 + + + ADDR + Address Value + 0 + 11 + + + LENEN + Length Enable + 13 + 1 + + + HS + High Speed Mode + 14 + 1 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + LEN + Length + 16 + 8 + + + + + DATA + I2CM Data + 0x28 + 32 + + + DATA + Data Value + 0 + 32 + + + + + DBGCTRL + I2CM Debug Control + 0x30 + 8 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + I2CS + I2C Slave Mode + I2CM + SercomI2cs + 0x0 + + CTRLA + I2CS Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + + RUNSTDBY + Run during Standby + 7 + 1 + + + PINOUT + Pin Usage + 16 + 1 + + + SDAHOLD + SDA Hold Time + 20 + 2 + + + SEXTTOEN + Slave SCL Low Extend Timeout + 23 + 1 + + + SPEED + Transfer Speed + 24 + 2 + + + SCLSM + SCL Clock Stretch Mode + 27 + 1 + + + LOWTOUTEN + SCL Low Timeout Enable + 30 + 1 + + + + + CTRLB + I2CS Control B + 0x04 + 32 + + + SMEN + Smart Mode Enable + 8 + 1 + + + GCMD + PMBus Group Command + 9 + 1 + + + AACKEN + Automatic Address Acknowledge + 10 + 1 + + + AMODE + Address Mode + 14 + 2 + + + CMD + Command + 16 + 2 + write-only + + + ACKACT + Acknowledge Action + 18 + 1 + + + + + CTRLC + I2CS Control C + 0x08 + 32 + + + SDASETUP + SDA Setup Time + 0 + 4 + + + DATA32B + Data 32 Bit + 24 + 1 + + + + + INTENCLR + I2CS Interrupt Enable Clear + 0x14 + 8 + + + PREC + Stop Received Interrupt Disable + 0 + 1 + + + AMATCH + Address Match Interrupt Disable + 1 + 1 + + + DRDY + Data Interrupt Disable + 2 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + I2CS Interrupt Enable Set + 0x16 + 8 + + + PREC + Stop Received Interrupt Enable + 0 + 1 + + + AMATCH + Address Match Interrupt Enable + 1 + 1 + + + DRDY + Data Interrupt Enable + 2 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + I2CS Interrupt Flag Status and Clear + 0x18 + 8 + + + PREC + Stop Received Interrupt + 0 + 1 + + + AMATCH + Address Match Interrupt + 1 + 1 + + + DRDY + Data Interrupt + 2 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + I2CS Status + 0x1A + 16 + + + BUSERR + Bus Error + 0 + 1 + + + COLL + Transmit Collision + 1 + 1 + + + RXNACK + Received Not Acknowledge + 2 + 1 + read-only + + + DIR + Read/Write Direction + 3 + 1 + read-only + + + SR + Repeated Start + 4 + 1 + read-only + + + LOWTOUT + SCL Low Timeout + 6 + 1 + + + CLKHOLD + Clock Hold + 7 + 1 + read-only + + + SEXTTOUT + Slave SCL Low Extend Timeout + 9 + 1 + + + HS + High Speed + 10 + 1 + + + LENERR + Transaction Length Error + 11 + 1 + + + + + SYNCBUSY + I2CS Synchronization Busy + 0x1C + 32 + read-only + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + read-only + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + read-only + + + LENGTH + Length Synchronization Busy + 4 + 1 + read-only + + + + + LENGTH + I2CS Length + 0x22 + 16 + + + LEN + Data Length + 0 + 8 + + + LENEN + Data Length Enable + 8 + 1 + + + + + ADDR + I2CS Address + 0x24 + 32 + + + GENCEN + General Call Address Enable + 0 + 1 + + + ADDR + Address Value + 1 + 10 + + + TENBITEN + Ten Bit Addressing Enable + 15 + 1 + + + ADDRMASK + Address Mask + 17 + 10 + + + + + DATA + I2CS Data + 0x28 + 32 + + + DATA + Data Value + 0 + 32 + + + + + + SPI + SPI Mode + I2CM + SercomSpi + 0x0 + + CTRLA + SPI Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + DOPO + Data Out Pinout + 16 + 2 + + + DIPO + Data In Pinout + 20 + 2 + + + FORM + Frame Format + 24 + 4 + + + CPHA + Clock Phase + 28 + 1 + + + CPOL + Clock Polarity + 29 + 1 + + + DORD + Data Order + 30 + 1 + + + + + CTRLB + SPI Control B + 0x04 + 32 + + + CHSIZE + Character Size + 0 + 3 + + + PLOADEN + Data Preload Enable + 6 + 1 + + + SSDE + Slave Select Low Detect Enable + 9 + 1 + + + MSSEN + Master Slave Select Enable + 13 + 1 + + + AMODE + Address Mode + 14 + 2 + + + RXEN + Receiver Enable + 17 + 1 + + + + + CTRLC + SPI Control C + 0x08 + 32 + + + ICSPACE + Inter-Character Spacing + 0 + 6 + + + DATA32B + Data 32 Bit + 24 + 1 + + + + + BAUD + SPI Baud Rate + 0x0C + 8 + + + BAUD + Baud Rate Value + 0 + 8 + + + + + INTENCLR + SPI Interrupt Enable Clear + 0x14 + 8 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + SSL + Slave Select Low Interrupt Disable + 3 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + SPI Interrupt Enable Set + 0x16 + 8 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + SSL + Slave Select Low Interrupt Enable + 3 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + SPI Interrupt Flag Status and Clear + 0x18 + 8 + + + DRE + Data Register Empty Interrupt + 0 + 1 + read-only + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + read-only + + + SSL + Slave Select Low Interrupt Flag + 3 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + SPI Status + 0x1A + 16 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + LENERR + Transaction Length Error + 11 + 1 + + + + + SYNCBUSY + SPI Synchronization Busy + 0x1C + 32 + read-only + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + read-only + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + read-only + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + read-only + + + LENGTH + LENGTH Synchronization Busy + 4 + 1 + read-only + + + + + LENGTH + SPI Length + 0x22 + 16 + + + LEN + Data Length + 0 + 8 + + + LENEN + Data Length Enable + 8 + 1 + + + + + ADDR + SPI Address + 0x24 + 32 + + + ADDR + Address Value + 0 + 8 + + + ADDRMASK + Address Mask + 16 + 8 + + + + + DATA + SPI Data + 0x28 + 32 + + + DATA + Data Value + 0 + 32 + + + + + DBGCTRL + SPI Debug Control + 0x30 + 8 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + USART + USART Mode + I2CM + SercomUsart + 0x0 + + CTRLA + USART Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + MODE + Operating Mode + 2 + 3 + + + RUNSTDBY + Run during Standby + 7 + 1 + + + IBON + Immediate Buffer Overflow Notification + 8 + 1 + + + TXINV + Transmit Data Invert + 9 + 1 + + + RXINV + Receive Data Invert + 10 + 1 + + + SAMPR + Sample + 13 + 3 + + + TXPO + Transmit Data Pinout + 16 + 2 + + + RXPO + Receive Data Pinout + 20 + 2 + + + SAMPA + Sample Adjustment + 22 + 2 + + + FORM + Frame Format + 24 + 4 + + + CMODE + Communication Mode + 28 + 1 + + + CPOL + Clock Polarity + 29 + 1 + + + DORD + Data Order + 30 + 1 + + + + + CTRLB + USART Control B + 0x04 + 32 + + + CHSIZE + Character Size + 0 + 3 + + + SBMODE + Stop Bit Mode + 6 + 1 + + + COLDEN + Collision Detection Enable + 8 + 1 + + + SFDE + Start of Frame Detection Enable + 9 + 1 + + + ENC + Encoding Format + 10 + 1 + + + PMODE + Parity Mode + 13 + 1 + + + TXEN + Transmitter Enable + 16 + 1 + + + RXEN + Receiver Enable + 17 + 1 + + + LINCMD + LIN Command + 24 + 2 + write-only + + + + + CTRLC + USART Control C + 0x08 + 32 + + + GTIME + Guard Time + 0 + 3 + + + BRKLEN + LIN Master Break Length + 8 + 2 + + + HDRDLY + LIN Master Header Delay + 10 + 2 + + + INACK + Inhibit Not Acknowledge + 16 + 1 + + + DSNACK + Disable Successive NACK + 17 + 1 + + + MAXITER + Maximum Iterations + 20 + 3 + + + DATA32B + Data 32 Bit + 24 + 2 + + + + + BAUD + USART Baud Rate + 0x0C + 16 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + BAUD_FRAC_MODE + USART Baud Rate + BAUD + 0x0C + 16 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_FRACFP_MODE + USART Baud Rate + BAUD + 0x0C + 16 + + + BAUD + Baud Rate Value + 0 + 13 + + + FP + Fractional Part + 13 + 3 + + + + + BAUD_USARTFP_MODE + USART Baud Rate + BAUD + 0x0C + 16 + + + BAUD + Baud Rate Value + 0 + 16 + + + + + RXPL + USART Receive Pulse Length + 0x0E + 8 + + + RXPL + Receive Pulse Length + 0 + 8 + + + + + INTENCLR + USART Interrupt Enable Clear + 0x14 + 8 + + + DRE + Data Register Empty Interrupt Disable + 0 + 1 + + + TXC + Transmit Complete Interrupt Disable + 1 + 1 + + + RXC + Receive Complete Interrupt Disable + 2 + 1 + + + RXS + Receive Start Interrupt Disable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Disable + 4 + 1 + + + RXBRK + Break Received Interrupt Disable + 5 + 1 + + + ERROR + Combined Error Interrupt Disable + 7 + 1 + + + + + INTENSET + USART Interrupt Enable Set + 0x16 + 8 + + + DRE + Data Register Empty Interrupt Enable + 0 + 1 + + + TXC + Transmit Complete Interrupt Enable + 1 + 1 + + + RXC + Receive Complete Interrupt Enable + 2 + 1 + + + RXS + Receive Start Interrupt Enable + 3 + 1 + + + CTSIC + Clear To Send Input Change Interrupt Enable + 4 + 1 + + + RXBRK + Break Received Interrupt Enable + 5 + 1 + + + ERROR + Combined Error Interrupt Enable + 7 + 1 + + + + + INTFLAG + USART Interrupt Flag Status and Clear + 0x18 + 8 + + + DRE + Data Register Empty Interrupt + 0 + 1 + read-only + + + TXC + Transmit Complete Interrupt + 1 + 1 + + + RXC + Receive Complete Interrupt + 2 + 1 + read-only + + + RXS + Receive Start Interrupt + 3 + 1 + write-only + + + CTSIC + Clear To Send Input Change Interrupt + 4 + 1 + + + RXBRK + Break Received Interrupt + 5 + 1 + + + ERROR + Combined Error Interrupt + 7 + 1 + + + + + STATUS + USART Status + 0x1A + 16 + + + PERR + Parity Error + 0 + 1 + + + FERR + Frame Error + 1 + 1 + + + BUFOVF + Buffer Overflow + 2 + 1 + + + CTS + Clear To Send + 3 + 1 + read-only + + + ISF + Inconsistent Sync Field + 4 + 1 + + + COLL + Collision Detected + 5 + 1 + + + TXE + Transmitter Empty + 6 + 1 + read-only + + + ITER + Maximum Number of Repetitions Reached + 7 + 1 + + + + + SYNCBUSY + USART Synchronization Busy + 0x1C + 32 + read-only + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + read-only + + + ENABLE + SERCOM Enable Synchronization Busy + 1 + 1 + read-only + + + CTRLB + CTRLB Synchronization Busy + 2 + 1 + read-only + + + RXERRCNT + RXERRCNT Synchronization Busy + 3 + 1 + read-only + + + LENGTH + LENGTH Synchronization Busy + 4 + 1 + read-only + + + + + RXERRCNT + USART Receive Error Count + 0x20 + 8 + read-only + + + LENGTH + USART Length + 0x22 + 16 + + + LEN + Data Length + 0 + 8 + + + LENEN + Data Length Enable + 8 + 2 + + + + + DATA + USART Data + 0x28 + 32 + + + DATA + Data Value + 0 + 32 + + + + + DBGCTRL + USART Debug Control + 0x30 + 8 + + + DBGSTOP + Debug Mode + 0 + 1 + + + + + + + + SERCOM1 + Serial Communication Interface 1 + 0x40003400 + + SERCOM1_INTREQ_0 + 50 + + + SERCOM1_INTREQ_1 + 51 + + + SERCOM1_INTREQ_2 + 52 + + + SERCOM1_INTREQ_3 + 53 + + + + SERCOM2 + Serial Communication Interface 2 + 0x41012000 + + SERCOM2_INTREQ_0 + 54 + + + SERCOM2_INTREQ_1 + 55 + + + SERCOM2_INTREQ_2 + 56 + + + SERCOM2_INTREQ_3 + 57 + + + + SERCOM3 + Serial Communication Interface 3 + 0x41014000 + + SERCOM3_INTREQ_0 + 58 + + + SERCOM3_INTREQ_1 + 59 + + + SERCOM3_INTREQ_2 + 60 + + + SERCOM3_INTREQ_3 + 61 + + + + SERCOM4 + Serial Communication Interface 4 + 0x43000000 + + SERCOM4_INTREQ_0 + 62 + + + SERCOM4_INTREQ_1 + 63 + + + SERCOM4_INTREQ_2 + 64 + + + SERCOM4_INTREQ_3 + 65 + + + + SERCOM5 + Serial Communication Interface 5 + 0x43000400 + + SERCOM5_INTREQ_0 + 66 + + + SERCOM5_INTREQ_1 + 67 + + + SERCOM5_INTREQ_2 + 68 + + + SERCOM5_INTREQ_3 + 69 + + + + SUPC + 1.0.0 + Supply Controller + SUPC + SUPC_ + 0x40001800 + + 0 + 0x80 + registers + + + SUPC_INTREQ_0 + 8 + + + SUPC_INTREQ_1 + 9 + + + + INTENCLR + Interrupt Enable Clear + 0x00 + 32 + + + BOD33RDY + BOD33 Ready + 0 + 1 + + + BOD33DET + BOD33 Detection + 1 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + + + BOD12RDY + BOD12 Ready + 3 + 1 + + + BOD12DET + BOD12 Detection + 4 + 1 + + + B12SRDY + BOD12 Synchronization Ready + 5 + 1 + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + + + VCORERDY + VDDCORE Ready + 10 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x04 + 32 + + + BOD33RDY + BOD33 Ready + 0 + 1 + + + BOD33DET + BOD33 Detection + 1 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + + + BOD12RDY + BOD12 Ready + 3 + 1 + + + BOD12DET + BOD12 Detection + 4 + 1 + + + B12SRDY + BOD12 Synchronization Ready + 5 + 1 + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + + + VCORERDY + VDDCORE Ready + 10 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x08 + 32 + + + BOD33RDY + BOD33 Ready + 0 + 1 + + + BOD33DET + BOD33 Detection + 1 + 1 + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + + + BOD12RDY + BOD12 Ready + 3 + 1 + + + BOD12DET + BOD12 Detection + 4 + 1 + + + B12SRDY + BOD12 Synchronization Ready + 5 + 1 + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + + + VCORERDY + VDDCORE Ready + 10 + 1 + + + + + STATUS + Power and Clocks Status + 0x0C + 32 + read-only + + + BOD33RDY + BOD33 Ready + 0 + 1 + read-only + + + BOD33DET + BOD33 Detection + 1 + 1 + read-only + + + B33SRDY + BOD33 Synchronization Ready + 2 + 1 + read-only + + + BOD12RDY + BOD12 Ready + 3 + 1 + read-only + + + BOD12DET + BOD12 Detection + 4 + 1 + read-only + + + B12SRDY + BOD12 Synchronization Ready + 5 + 1 + read-only + + + VREGRDY + Voltage Regulator Ready + 8 + 1 + read-only + + + VCORERDY + VDDCORE Ready + 10 + 1 + read-only + + + + + BOD33 + BOD33 Control + 0x10 + 32 + + + ENABLE + Enable + 1 + 1 + + + ACTION + Action when Threshold Crossed + 2 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BOD33 generates a reset + 0x1 + + + INT + The BOD33 generates an interrupt + 0x2 + + + BKUP + The BOD33 puts the device in backup sleep mode + 0x3 + + + + + STDBYCFG + Configuration in Standby mode + 4 + 1 + + + RUNSTDBY + Run in Standby mode + 5 + 1 + + + RUNHIB + Run in Hibernate mode + 6 + 1 + + + RUNBKUP + Run in Backup mode + 7 + 1 + + + HYST + Hysteresis value + 8 + 4 + + + PSEL + Prescaler Select + 12 + 3 + + PSELSelect + + NODIV + Not divided + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + + + LEVEL + Threshold Level for VDD + 16 + 8 + + + VBATLEVEL + Threshold Level in battery backup sleep mode for VBAT + 24 + 8 + + + + + BOD12 + BOD12 Control + 0x14 + 32 + + + ENABLE + Enable + 1 + 1 + + + HYST + Hysteresis Enable + 2 + 1 + + + ACTION + Action when Threshold Crossed + 3 + 2 + + ACTIONSelect + + NONE + No action + 0x0 + + + RESET + The BOD12 generates a reset + 0x1 + + + INT + The BOD12 generates an interrupt + 0x2 + + + + + STDBYCFG + Configuration in Standby mode + 5 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ACTCFG + Configuration in Active mode + 8 + 1 + + + PSEL + Prescaler Select + 12 + 4 + + PSELSelect + + DIV2 + Divide clock by 2 + 0x0 + + + DIV4 + Divide clock by 4 + 0x1 + + + DIV8 + Divide clock by 8 + 0x2 + + + DIV16 + Divide clock by 16 + 0x3 + + + DIV32 + Divide clock by 32 + 0x4 + + + DIV64 + Divide clock by 64 + 0x5 + + + DIV128 + Divide clock by 128 + 0x6 + + + DIV256 + Divide clock by 256 + 0x7 + + + DIV512 + Divide clock by 512 + 0x8 + + + DIV1024 + Divide clock by 1024 + 0x9 + + + DIV2048 + Divide clock by 2048 + 0xa + + + DIV4096 + Divide clock by 4096 + 0xb + + + DIV8192 + Divide clock by 8192 + 0xc + + + DIV16384 + Divide clock by 16384 + 0xd + + + DIV32768 + Divide clock by 32768 + 0xe + + + DIV65536 + Divide clock by 65536 + 0xf + + + + + LEVEL + Threshold Level + 16 + 6 + + + + + VREG + VREG Control + 0x18 + 32 + 0x00000002 + + + ENABLE + Enable + 1 + 1 + + + SEL + Voltage Regulator Selection + 2 + 1 + + SELSelect + + LDO + LDO selection + 0x0 + + + BUCK + Buck selection + 0x1 + + + + + RUNBKUP + Run in Backup mode + 7 + 1 + + + VSEN + Voltage Scaling Enable + 16 + 1 + + + VSPER + Voltage Scaling Period + 24 + 3 + + + + + VREF + VREF Control + 0x1C + 32 + + + TSEN + Temperature Sensor Output Enable + 1 + 1 + + + VREFOE + Voltage Reference Output Enable + 2 + 1 + + + TSSEL + Temperature Sensor Selection + 3 + 1 + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + On Demand Contrl + 7 + 1 + + + SEL + Voltage Reference Selection + 16 + 4 + + SELSelect + + 1V0 + 1.0V voltage reference typical value + 0x0 + + + 1V1 + 1.1V voltage reference typical value + 0x1 + + + 1V2 + 1.2V voltage reference typical value + 0x2 + + + 1V25 + 1.25V voltage reference typical value + 0x3 + + + 2V0 + 2.0V voltage reference typical value + 0x4 + + + 2V2 + 2.2V voltage reference typical value + 0x5 + + + 2V4 + 2.4V voltage reference typical value + 0x6 + + + 2V5 + 2.5V voltage reference typical value + 0x7 + + + + + + + BBPS + Battery Backup Power Switch + 0x20 + 32 + + + CONF + Battery Backup Configuration + 0 + 1 + + CONFSelect + + BOD33 + The power switch is handled by the BOD33 + 0x0 + + + FORCED + In Backup Domain, the backup domain is always supplied by battery backup power + 0x1 + + + + + WAKEEN + Wake Enable + 2 + 1 + + + + + BKOUT + Backup Output Control + 0x24 + 32 + + + EN + Enable Output + 0 + 2 + + + CLR + Clear Output + 8 + 2 + write-only + + + SET + Set Output + 16 + 2 + write-only + + + RTCTGL + RTC Toggle Output + 24 + 2 + + + + + BKIN + Backup Input Control + 0x28 + 32 + read-only + + + BKIN + Backup Input Value + 0 + 8 + read-only + + + + + + + TAL + 2.0.0 + Trigger Allocator + TAL + TAL_ + 0x4101E000 + + 0 + 0x400 + registers + + + TAL_INTREQ_0 + 42 + + + TAL_INTREQ_1 + 43 + + + + CTRLA + Control A + 0x000 + 8 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + + + EXTCTRL + External Break Control + 0x001 + 8 + + + ENABLE + Enable BRK Pin + 0 + 1 + + + INV + Invert BRK Pin + 1 + 1 + + + + + EVCTRL + Event Control + 0x004 + 16 + + + BRKEI + Break Input Event Enable + 0 + 1 + + + BRKEO + Break Output Event Enable + 1 + 1 + + + IRQMONEO0 + Interrupt Request Monitor 0 Output Event Enable + 2 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x008 + 8 + + + BRK + Break Interrupt Enable + 0 + 1 + + + IPS0 + Inter-Processor Signal Interrupt Enable for CPU 0 + 1 + 1 + + + IPS1 + Inter-Processor Signal Interrupt Enable for CPU 1 + 2 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x009 + 8 + + + BRK + Break Interrupt Enable + 0 + 1 + + + IPS0 + Inter-Processor Signal Interrupt Enable for CPU 0 + 1 + 1 + + + IPS1 + Inter-Processor Signal Interrupt Enable for CPU 1 + 2 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x00A + 8 + + + BRK + Break + 0 + 1 + + + IPS0 + Inter-Processor Signal for CPU 0 + 1 + 1 + + + IPS1 + Inter-Processor Signal for CPU 1 + 2 + 1 + + + + + GLOBMASK + Global Break Requests Mask + 0x00B + 8 + + + CPU0 + CPU 0 Break Master + 0 + 1 + + + CPU1 + CPU 1 Break Master + 1 + 1 + + + EVBRK + Event Break Master + 6 + 1 + + + EXTBRK + External Break Master + 7 + 1 + + + + + HALT + Debug Halt Request + 0x00C + 8 + write-only + + + CPU0 + CPU 0 Break Master + 0 + 1 + + + CPU1 + CPU 1 Break Master + 1 + 1 + + + EVBRK + Event Break Master + 6 + 1 + + + EXTBRK + External Break Master + 7 + 1 + + + + + RESTART + Debug Restart Request + 0x00D + 8 + write-only + + + CPU0 + CPU 0 Break Master + 0 + 1 + + + CPU1 + CPU 1 Break Master + 1 + 1 + + + EXTBRK + External Break Master + 7 + 1 + + + + + BRKSTATUS + Break Request Status + 0x00E + 16 + read-only + + + CPU0 + CPU 0 Break Request + 0 + 2 + + + CPU1 + CPU 1 Break Request + 2 + 2 + + + EVBRK + Event Break Request + 12 + 2 + + + EXTBRK + External Break Request + 14 + 2 + + + + + 4 + 0x2 + CTICTRLA%s + Cross-Trigger Interface n Control A + 0x010 + 8 + + + BRK + Action when global break issued + 0 + 2 + + BRKSelect + + BREAK + Break when requested + 0x0 + + + INTERRUPT + Trigger DBG interrupt instead of break + 0x1 + + + IGNORE + Ignore break request + 0x2 + + + + + RESTART + Action when global restart issued + 2 + 1 + + RESTARTSelect + + RESTART + Restart when requested + 0x0 + + + IGNORE + Ignore restart request + 0x1 + + + + + IPS + Action when inter-process resource freed + 3 + 1 + + IPSSelect + + EVENT + Generate CPU Event when awaited resource is freed. + 0x0 + + + INTERRUPT + Generate Interrupt when awaited resource is freed. + 0x1 + + + + + + + 4 + 0x2 + CTIMASK%s + Cross-Trigger Interface n Mask + 0x011 + 8 + + + CPU0 + CPU 0 Break Master + 0 + 1 + + + CPU1 + CPU 1 Break Master + 1 + 1 + + + EVBRK + Event Break Master + 6 + 1 + + + EXTBRK + External Break Master + 7 + 1 + + + + + 137 + 0x1 + INTSTATUS%s + Interrupt n Status + 0x020 + 8 + read-only + + + IRQ0 + Interrupt Status for Interrupt Request 0 within Interrupt n + 0 + 1 + + + IRQ1 + Interrupt Status for Interrupt Request 1 within Interrupt n + 1 + 1 + + + IRQ2 + Interrupt Status for Interrupt Request 2 within Interrupt n + 2 + 1 + + + IRQ3 + Interrupt Status for Interrupt Request 3 within Interrupt n + 3 + 1 + + + IRQ4 + Interrupt Status for Interrupt Request 4 within Interrupt n + 4 + 1 + + + IRQ5 + Interrupt Status for Interrupt Request 5 within Interrupt n + 5 + 1 + + + IRQ6 + Interrupt Status for Interrupt Request 6 within Interrupt n + 6 + 1 + + + IRQ7 + Interrupt Status for Interrupt Request 7 within Interrupt n + 7 + 1 + + + + + DMACPUSEL0 + DMA Channel Interrupts CPU Select 0 + 0x110 + 32 + + + CH0 + DMA Channel 0 Interrupt CPU Select + 0 + 1 + + + CH1 + DMA Channel 1 Interrupt CPU Select + 2 + 1 + + + CH2 + DMA Channel 2 Interrupt CPU Select + 4 + 1 + + + CH3 + DMA Channel 3 Interrupt CPU Select + 6 + 1 + + + CH4 + DMA Channel 4 Interrupt CPU Select + 8 + 1 + + + CH5 + DMA Channel 5 Interrupt CPU Select + 10 + 1 + + + CH6 + DMA Channel 6 Interrupt CPU Select + 12 + 1 + + + CH7 + DMA Channel 7 Interrupt CPU Select + 14 + 1 + + + CH8 + DMA Channel 8 Interrupt CPU Select + 16 + 1 + + + CH9 + DMA Channel 9 Interrupt CPU Select + 18 + 1 + + + CH10 + DMA Channel 10 Interrupt CPU Select + 20 + 1 + + + CH11 + DMA Channel 11 Interrupt CPU Select + 22 + 1 + + + CH12 + DMA Channel 12 Interrupt CPU Select + 24 + 1 + + + CH13 + DMA Channel 13 Interrupt CPU Select + 26 + 1 + + + CH14 + DMA Channel 14 Interrupt CPU Select + 28 + 1 + + + CH15 + DMA Channel 15 Interrupt CPU Select + 30 + 1 + + + + + DMACPUSEL1 + DMA Channel Interrupts CPU Select 1 + 0x114 + 32 + + + CH16 + DMA Channel 16 Interrupt CPU Select + 0 + 1 + + + CH17 + DMA Channel 17 Interrupt CPU Select + 2 + 1 + + + CH18 + DMA Channel 18 Interrupt CPU Select + 4 + 1 + + + CH19 + DMA Channel 19 Interrupt CPU Select + 6 + 1 + + + CH20 + DMA Channel 20 Interrupt CPU Select + 8 + 1 + + + CH21 + DMA Channel 21 Interrupt CPU Select + 10 + 1 + + + CH22 + DMA Channel 22 Interrupt CPU Select + 12 + 1 + + + CH23 + DMA Channel 23 Interrupt CPU Select + 14 + 1 + + + CH24 + DMA Channel 24 Interrupt CPU Select + 16 + 1 + + + CH25 + DMA Channel 25 Interrupt CPU Select + 18 + 1 + + + CH26 + DMA Channel 26 Interrupt CPU Select + 20 + 1 + + + CH27 + DMA Channel 27 Interrupt CPU Select + 22 + 1 + + + CH28 + DMA Channel 28 Interrupt CPU Select + 24 + 1 + + + CH29 + DMA Channel 29 Interrupt CPU Select + 26 + 1 + + + CH30 + DMA Channel 30 Interrupt CPU Select + 28 + 1 + + + CH31 + DMA Channel 31 Interrupt CPU Select + 30 + 1 + + + + + EVCPUSEL0 + EVSYS Channel Interrupts CPU Select 0 + 0x118 + 32 + + + CH0 + Event Channel 0 Interrupt CPU Select + 0 + 1 + + + CH1 + Event Channel 1 Interrupt CPU Select + 2 + 1 + + + CH2 + Event Channel 2 Interrupt CPU Select + 4 + 1 + + + CH3 + Event Channel 3 Interrupt CPU Select + 6 + 1 + + + CH4 + Event Channel 4 Interrupt CPU Select + 8 + 1 + + + CH5 + Event Channel 5 Interrupt CPU Select + 10 + 1 + + + CH6 + Event Channel 6 Interrupt CPU Select + 12 + 1 + + + CH7 + Event Channel 7 Interrupt CPU Select + 14 + 1 + + + CH8 + Event Channel 8 Interrupt CPU Select + 16 + 1 + + + CH9 + Event Channel 9 Interrupt CPU Select + 18 + 1 + + + CH10 + Event Channel 10 Interrupt CPU Select + 20 + 1 + + + CH11 + Event Channel 11 Interrupt CPU Select + 22 + 1 + + + + + EICCPUSEL0 + EIC External Interrupts CPU Select 0 + 0x120 + 32 + + + EXTINT0 + External Interrupt 0 CPU Select + 0 + 1 + + + EXTINT1 + External Interrupt 1 CPU Select + 2 + 1 + + + EXTINT2 + External Interrupt 2 CPU Select + 4 + 1 + + + EXTINT3 + External Interrupt 3 CPU Select + 6 + 1 + + + EXTINT4 + External Interrupt 4 CPU Select + 8 + 1 + + + EXTINT5 + External Interrupt 5 CPU Select + 10 + 1 + + + EXTINT6 + External Interrupt 6 CPU Select + 12 + 1 + + + EXTINT7 + External Interrupt 7 CPU Select + 14 + 1 + + + EXTINT8 + External Interrupt 8 CPU Select + 16 + 1 + + + EXTINT9 + External Interrupt 9 CPU Select + 18 + 1 + + + EXTINT10 + External Interrupt 10 CPU Select + 20 + 1 + + + EXTINT11 + External Interrupt 11 CPU Select + 22 + 1 + + + EXTINT12 + External Interrupt 12 CPU Select + 24 + 1 + + + EXTINT13 + External Interrupt 13 CPU Select + 26 + 1 + + + EXTINT14 + External Interrupt 14 CPU Select + 28 + 1 + + + EXTINT15 + External Interrupt 15 CPU Select + 30 + 1 + + + + + INTCPUSEL0 + Interrupts CPU Select 0 + 0x128 + 32 + + + PAC + PAC Interrupt CPU Select + 0 + 1 + + + PM + PM Interrupt CPU Select + 2 + 1 + + + MCLK + MCLK Interrupt CPU Select + 4 + 1 + + + OSCCTRL + OSCCTRL Interrupt CPU Select + 8 + 1 + + + OSC32KCTRL + OSC32KCTRL Interrupt CPU Select + 10 + 1 + + + SUPC + SUPC Interrupt CPU Select + 12 + 1 + + + WDT + WDT Interrupt CPU Select + 16 + 1 + + + RTC + RTC Interrupt CPU Select + 18 + 1 + + + EIC + EIC Interrupt CPU Select + 20 + 1 + + + FREQM + FREQM Interrupt CPU Select + 22 + 1 + + + SERCOM0 + SERCOM0 Interrupt CPU Select + 24 + 1 + + + SERCOM1 + SERCOM1 Interrupt CPU Select + 26 + 1 + + + TC0 + TC0 Interrupt CPU Select + 28 + 1 + + + TC1 + TC1 Interrupt CPU Select + 30 + 1 + + + + + INTCPUSEL1 + Interrupts CPU Select 1 + 0x12C + 32 + + + INTCPUSEL2 + Interrupts CPU Select 2 + 0x130 + 32 + + + USB + USB Interrupt CPU Select + 0 + 1 + + + NVMCTRL + NVMCTRL Interrupt CPU Select + 4 + 1 + + + DMAC + DMAC Interrupt CPU Select + 10 + 1 + + + EVSYS + EVSYS Interrupt CPU Select + 14 + 1 + + + PICOP + PICOP Interrupt CPU Select + 16 + 1 + + + SERCOM2 + SERCOM2 Interrupt CPU Select + 18 + 1 + + + SERCOM3 + SERCOM3 Interrupt CPU Select + 20 + 1 + + + TCC0 + TCC0 Interrupt CPU Select + 22 + 1 + + + TCC1 + TCC1 Interrupt CPU Select + 24 + 1 + + + TC2 + TC2 Interrupt CPU Select + 26 + 1 + + + TC3 + TC3 Interrupt CPU Select + 28 + 1 + + + TAL + TAL Interrupt CPU Select + 30 + 1 + + + + + INTCPUSEL3 + Interrupts CPU Select 3 + 0x134 + 32 + + + RAMECC + RAMECC Interrupt CPU Select + 0 + 1 + + + + + INTCPUSEL4 + Interrupts CPU Select 4 + 0x138 + 32 + + + CAN0 + CAN0 Interrupt CPU Select + 0 + 1 + + + CAN1 + CAN1 Interrupt CPU Select + 2 + 1 + + + GMAC + GMAC Interrupt CPU Select + 4 + 1 + + + TCC2 + TCC2 Interrupt CPU Select + 6 + 1 + + + TCC3 + TCC3 Interrupt CPU Select + 8 + 1 + + + TC4 + TC4 Interrupt CPU Select + 10 + 1 + + + TC5 + TC5 Interrupt CPU Select + 12 + 1 + + + PDEC + PDEC Interrupt CPU Select + 14 + 1 + + + AC + AC Interrupt CPU Select + 16 + 1 + + + AES + AES Interrupt CPU Select + 18 + 1 + + + TRNG + TRNG Interrupt CPU Select + 20 + 1 + + + ICM + ICM Interrupt CPU Select + 22 + 1 + + + PUKCC + PUKCC Interrupt CPU Select + 24 + 1 + + + QSPI + QSPI Interrupt CPU Select + 26 + 1 + + + + + INTCPUSEL5 + Interrupts CPU Select 5 + 0x13C + 32 + + + INTCPUSEL6 + Interrupts CPU Select 6 + 0x140 + 32 + + + SERCOM4 + SERCOM4 Interrupt CPU Select + 0 + 1 + + + SERCOM5 + SERCOM5 Interrupt CPU Select + 2 + 1 + + + SERCOM6 + SERCOM6 Interrupt CPU Select + 4 + 1 + + + SERCOM7 + SERCOM7 Interrupt CPU Select + 6 + 1 + + + TCC4 + TCC4 Interrupt CPU Select + 8 + 1 + + + TC6 + TC6 Interrupt CPU Select + 10 + 1 + + + TC7 + TC7 Interrupt CPU Select + 12 + 1 + + + ADC0 + ADC0 Interrupt CPU Select + 14 + 1 + + + ADC1 + ADC1 Interrupt CPU Select + 16 + 1 + + + DAC + DAC Interrupt CPU Select + 18 + 1 + + + I2S + I2S Interrupt CPU Select + 20 + 1 + + + PCC + PCC Interrupt CPU Select + 22 + 1 + + + + + INTCPUSEL7 + Interrupts CPU Select 7 + 0x144 + 32 + + + INTCPUSEL8 + Interrupts CPU Select 8 + 0x148 + 32 + + + SDHC0 + SDHC0 Interrupt CPU Select + 0 + 1 + + + SDHC1 + SDHC1 Interrupt CPU Select + 2 + 1 + + + + + IRQTRIG + Interrupt Trigger + 0x164 + 32 + + + ENABLE + Trigger Enable + 0 + 1 + + + IRQNUM + Interrupt Request Number + 8 + 8 + + + OVERRIDE + Interrupt Request Override Value + 16 + 8 + + + + + 1 + 0x2 + IRQMON%s + Interrupt Monitor Select + 0x168 + 16 + + + EXTEND + Extended Interrupt Request + 0 + 1 + + EXTENDSelect + + NO + Event is Interrupt Request signal + 0x0 + + + YES + Event is Interrupt Request signal extended until end of Interrupt Handler + 0x1 + + + + + DROP + Drop Shortened Events + 1 + 1 + + + CPUID + ID of CPU currently servicing this IRQ + 2 + 1 + + + IRQNUM + Interrupt Request Number + 8 + 8 + + + + + 5 + 0x4 + CPUIRQS0_%s + Interrupt Status m for CPU n - Group 0 + 0x180 + 32 + read-only + + + CPUIRQS + Interrupt Requests for CPU n + 0 + 32 + + + + + 5 + 0x4 + CPUIRQS1_%s + Interrupt Status m for CPU n - Group 1 + 0x1a0 + + + 2 + 0x4 + SMASK0_%s + Inter-Process Signal Mask m for CPU n - Group 0 + 0x200 + 32 + + + IPS0 + Inter-Process Signal 0 + 0 + 1 + + + IPS1 + Inter-Process Signal 1 + 1 + 1 + + + IPS2 + Inter-Process Signal 2 + 2 + 1 + + + IPS3 + Inter-Process Signal 3 + 3 + 1 + + + IPS4 + Inter-Process Signal 4 + 4 + 1 + + + IPS5 + Inter-Process Signal 5 + 5 + 1 + + + IPS6 + Inter-Process Signal 6 + 6 + 1 + + + IPS7 + Inter-Process Signal 7 + 7 + 1 + + + IPS8 + Inter-Process Signal 8 + 8 + 1 + + + IPS9 + Inter-Process Signal 9 + 9 + 1 + + + IPS10 + Inter-Process Signal 10 + 10 + 1 + + + IPS11 + Inter-Process Signal 11 + 11 + 1 + + + IPS12 + Inter-Process Signal 12 + 12 + 1 + + + IPS13 + Inter-Process Signal 13 + 13 + 1 + + + IPS14 + Inter-Process Signal 14 + 14 + 1 + + + IPS15 + Inter-Process Signal 15 + 15 + 1 + + + IPS16 + Inter-Process Signal 16 + 16 + 1 + + + IPS17 + Inter-Process Signal 17 + 17 + 1 + + + IPS18 + Inter-Process Signal 18 + 18 + 1 + + + IPS19 + Inter-Process Signal 19 + 19 + 1 + + + IPS20 + Inter-Process Signal 20 + 20 + 1 + + + IPS21 + Inter-Process Signal 21 + 21 + 1 + + + IPS22 + Inter-Process Signal 22 + 22 + 1 + + + IPS23 + Inter-Process Signal 23 + 23 + 1 + + + IPS24 + Inter-Process Signal 24 + 24 + 1 + + + IPS25 + Inter-Process Signal 25 + 25 + 1 + + + IPS26 + Inter-Process Signal 26 + 26 + 1 + + + IPS27 + Inter-Process Signal 27 + 27 + 1 + + + IPS28 + Inter-Process Signal 28 + 28 + 1 + + + IPS29 + Inter-Process Signal 29 + 29 + 1 + + + IPS30 + Inter-Process Signal 30 + 30 + 1 + + + IPS31 + Inter-Process Signal 31 + 31 + 1 + + + + + 2 + 0x4 + SMASK1_%s + Inter-Process Signal Mask m for CPU n - Group 1 + 0x208 + + + 2 + 0x4 + SFLAGCLR%s + Inter-Process Signal Flag Clear + 0x220 + 32 + write-only + + + IPS0 + Inter-Process Signal 0 + 0 + 1 + + + IPS1 + Inter-Process Signal 1 + 1 + 1 + + + IPS2 + Inter-Process Signal 2 + 2 + 1 + + + IPS3 + Inter-Process Signal 3 + 3 + 1 + + + IPS4 + Inter-Process Signal 4 + 4 + 1 + + + IPS5 + Inter-Process Signal 5 + 5 + 1 + + + IPS6 + Inter-Process Signal 6 + 6 + 1 + + + IPS7 + Inter-Process Signal 7 + 7 + 1 + + + IPS8 + Inter-Process Signal 8 + 8 + 1 + + + IPS9 + Inter-Process Signal 9 + 9 + 1 + + + IPS10 + Inter-Process Signal 10 + 10 + 1 + + + IPS11 + Inter-Process Signal 11 + 11 + 1 + + + IPS12 + Inter-Process Signal 12 + 12 + 1 + + + IPS13 + Inter-Process Signal 13 + 13 + 1 + + + IPS14 + Inter-Process Signal 14 + 14 + 1 + + + IPS15 + Inter-Process Signal 15 + 15 + 1 + + + IPS16 + Inter-Process Signal 16 + 16 + 1 + + + IPS17 + Inter-Process Signal 17 + 17 + 1 + + + IPS18 + Inter-Process Signal 18 + 18 + 1 + + + IPS19 + Inter-Process Signal 19 + 19 + 1 + + + IPS20 + Inter-Process Signal 20 + 20 + 1 + + + IPS21 + Inter-Process Signal 21 + 21 + 1 + + + IPS22 + Inter-Process Signal 22 + 22 + 1 + + + IPS23 + Inter-Process Signal 23 + 23 + 1 + + + IPS24 + Inter-Process Signal 24 + 24 + 1 + + + IPS25 + Inter-Process Signal 25 + 25 + 1 + + + IPS26 + Inter-Process Signal 26 + 26 + 1 + + + IPS27 + Inter-Process Signal 27 + 27 + 1 + + + IPS28 + Inter-Process Signal 28 + 28 + 1 + + + IPS29 + Inter-Process Signal 29 + 29 + 1 + + + IPS30 + Inter-Process Signal 30 + 30 + 1 + + + IPS31 + Inter-Process Signal 31 + 31 + 1 + + + + + 2 + 0x4 + SFLAGSET%s + Inter-Process Signal Flag Set + 0x228 + 32 + write-only + + + IPS0 + Inter-Process Signal 0 + 0 + 1 + + + IPS1 + Inter-Process Signal 1 + 1 + 1 + + + IPS2 + Inter-Process Signal 2 + 2 + 1 + + + IPS3 + Inter-Process Signal 3 + 3 + 1 + + + IPS4 + Inter-Process Signal 4 + 4 + 1 + + + IPS5 + Inter-Process Signal 5 + 5 + 1 + + + IPS6 + Inter-Process Signal 6 + 6 + 1 + + + IPS7 + Inter-Process Signal 7 + 7 + 1 + + + IPS8 + Inter-Process Signal 8 + 8 + 1 + + + IPS9 + Inter-Process Signal 9 + 9 + 1 + + + IPS10 + Inter-Process Signal 10 + 10 + 1 + + + IPS11 + Inter-Process Signal 11 + 11 + 1 + + + IPS12 + Inter-Process Signal 12 + 12 + 1 + + + IPS13 + Inter-Process Signal 13 + 13 + 1 + + + IPS14 + Inter-Process Signal 14 + 14 + 1 + + + IPS15 + Inter-Process Signal 15 + 15 + 1 + + + IPS16 + Inter-Process Signal 16 + 16 + 1 + + + IPS17 + Inter-Process Signal 17 + 17 + 1 + + + IPS18 + Inter-Process Signal 18 + 18 + 1 + + + IPS19 + Inter-Process Signal 19 + 19 + 1 + + + IPS20 + Inter-Process Signal 20 + 20 + 1 + + + IPS21 + Inter-Process Signal 21 + 21 + 1 + + + IPS22 + Inter-Process Signal 22 + 22 + 1 + + + IPS23 + Inter-Process Signal 23 + 23 + 1 + + + IPS24 + Inter-Process Signal 24 + 24 + 1 + + + IPS25 + Inter-Process Signal 25 + 25 + 1 + + + IPS26 + Inter-Process Signal 26 + 26 + 1 + + + IPS27 + Inter-Process Signal 27 + 27 + 1 + + + IPS28 + Inter-Process Signal 28 + 28 + 1 + + + IPS29 + Inter-Process Signal 29 + 29 + 1 + + + IPS30 + Inter-Process Signal 30 + 30 + 1 + + + IPS31 + Inter-Process Signal 31 + 31 + 1 + + + + + 2 + 0x4 + SFLAG%s + Inter-Process Signal Flag + 0x230 + 32 + read-only + + + IPS0 + Inter-Process Signal 0 + 0 + 1 + + + IPS1 + Inter-Process Signal 1 + 1 + 1 + + + IPS2 + Inter-Process Signal 2 + 2 + 1 + + + IPS3 + Inter-Process Signal 3 + 3 + 1 + + + IPS4 + Inter-Process Signal 4 + 4 + 1 + + + IPS5 + Inter-Process Signal 5 + 5 + 1 + + + IPS6 + Inter-Process Signal 6 + 6 + 1 + + + IPS7 + Inter-Process Signal 7 + 7 + 1 + + + IPS8 + Inter-Process Signal 8 + 8 + 1 + + + IPS9 + Inter-Process Signal 9 + 9 + 1 + + + IPS10 + Inter-Process Signal 10 + 10 + 1 + + + IPS11 + Inter-Process Signal 11 + 11 + 1 + + + IPS12 + Inter-Process Signal 12 + 12 + 1 + + + IPS13 + Inter-Process Signal 13 + 13 + 1 + + + IPS14 + Inter-Process Signal 14 + 14 + 1 + + + IPS15 + Inter-Process Signal 15 + 15 + 1 + + + IPS16 + Inter-Process Signal 16 + 16 + 1 + + + IPS17 + Inter-Process Signal 17 + 17 + 1 + + + IPS18 + Inter-Process Signal 18 + 18 + 1 + + + IPS19 + Inter-Process Signal 19 + 19 + 1 + + + IPS20 + Inter-Process Signal 20 + 20 + 1 + + + IPS21 + Inter-Process Signal 21 + 21 + 1 + + + IPS22 + Inter-Process Signal 22 + 22 + 1 + + + IPS23 + Inter-Process Signal 23 + 23 + 1 + + + IPS24 + Inter-Process Signal 24 + 24 + 1 + + + IPS25 + Inter-Process Signal 25 + 25 + 1 + + + IPS26 + Inter-Process Signal 26 + 26 + 1 + + + IPS27 + Inter-Process Signal 27 + 27 + 1 + + + IPS28 + Inter-Process Signal 28 + 28 + 1 + + + IPS29 + Inter-Process Signal 29 + 29 + 1 + + + IPS30 + Inter-Process Signal 30 + 30 + 1 + + + IPS31 + Inter-Process Signal 31 + 31 + 1 + + + + + 64 + 0x1 + SFLAGCLRR%s + Inter-Process Signal Flag Bit n + 0x300 + 8 + + + IPS + Inter-Process Signal n + 0 + 1 + + + + + + + TC0 + 3.0.0 + Basic Timer Counter 0 + TC + TC_ + 0x40003800 + + 0 + 0x40 + registers + + + TC0_INTREQ + 107 + + + + COUNT8 + 8-bit Counter Mode + TcCount8 + 0x0 + + CTRLA + Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0x0 + + + COUNT8 + Counter in 8-bit mode + 0x1 + + + COUNT32 + Counter in 32-bit mode + 0x2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0x0 + + + PRESC + Reload or reset the counter on next prescaler clock + 0x1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 0x2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + CAPTMODE0 + Capture Mode Channel 0 + 24 + 2 + + CAPTMODE0Select + + DEFAULT + Default capture + 0x0 + + + CAPTMIN + Minimum capture + 0x1 + + + CAPTMAX + Maximum capture + 0x2 + + + + + CAPTMODE1 + Capture mode Channel 1 + 27 + 2 + + CAPTMODE1Select + + DEFAULT + Default capture + 0x0 + + + CAPTMIN + Minimum capture + 0x1 + + + CAPTMAX + Maximum capture + 0x2 + + + + + + + CTRLBCLR + Control B Clear + 0x04 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + UPDATE + Force update of double-buffered register + 0x3 + + + READSYNC + Force a read synchronization of COUNT + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + CTRLBSET + Control B Set + 0x05 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + UPDATE + Force update of double-buffered register + 0x3 + + + READSYNC + Force a read synchronization of COUNT + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + EVCTRL + Event Control + 0x06 + 16 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0x0 + + + RETRIGGER + Start, restart or retrigger TC on event + 0x1 + + + COUNT + Count on event + 0x2 + + + START + Start TC on event + 0x3 + + + STAMP + Time stamp capture + 0x4 + + + PPW + Period catured in CC0, pulse width in CC1 + 0x5 + + + PWP + Period catured in CC1, pulse width in CC0 + 0x6 + + + PW + Pulse width capture + 0x7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x08 + 8 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x09 + 8 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x0A + 8 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0x0B + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + read-only + + + SLAVE + Slave Status Flag + 1 + 1 + read-only + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0x0C + 8 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0x0 + + + MFRQ + Match frequency + 0x1 + + + NPWM + Normal PWM + 0x2 + + + MPWM + Match PWM + 0x3 + + + + + + + DRVCTRL + Control C + 0x0D + 8 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x0F + 8 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT8 Count + 0x14 + 8 + + + COUNT + Counter Value + 0 + 8 + + + + + PER + COUNT8 Period + 0x1B + 8 + 0xFF + + + PER + Period Value + 0 + 8 + + + + + 2 + 0x1 + CC%s + COUNT8 Compare and Capture + 0x1C + 8 + + + CC + Counter/Compare Value + 0 + 8 + + + + + PERBUF + COUNT8 Period Buffer + 0x2F + 8 + 0xFF + + + PERBUF + Period Buffer Value + 0 + 8 + + + + + 2 + 0x1 + CCBUF%s + COUNT8 Compare and Capture Buffer + 0x30 + 8 + + + CCBUF + Counter/Compare Buffer Value + 0 + 8 + + + + + + COUNT16 + 16-bit Counter Mode + COUNT8 + TcCount16 + 0x0 + + CTRLA + Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0x0 + + + COUNT8 + Counter in 8-bit mode + 0x1 + + + COUNT32 + Counter in 32-bit mode + 0x2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0x0 + + + PRESC + Reload or reset the counter on next prescaler clock + 0x1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 0x2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + CAPTMODE0 + Capture Mode Channel 0 + 24 + 2 + + CAPTMODE0Select + + DEFAULT + Default capture + 0x0 + + + CAPTMIN + Minimum capture + 0x1 + + + CAPTMAX + Maximum capture + 0x2 + + + + + CAPTMODE1 + Capture mode Channel 1 + 27 + 2 + + CAPTMODE1Select + + DEFAULT + Default capture + 0x0 + + + CAPTMIN + Minimum capture + 0x1 + + + CAPTMAX + Maximum capture + 0x2 + + + + + + + CTRLBCLR + Control B Clear + 0x04 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + UPDATE + Force update of double-buffered register + 0x3 + + + READSYNC + Force a read synchronization of COUNT + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + CTRLBSET + Control B Set + 0x05 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + UPDATE + Force update of double-buffered register + 0x3 + + + READSYNC + Force a read synchronization of COUNT + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + EVCTRL + Event Control + 0x06 + 16 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0x0 + + + RETRIGGER + Start, restart or retrigger TC on event + 0x1 + + + COUNT + Count on event + 0x2 + + + START + Start TC on event + 0x3 + + + STAMP + Time stamp capture + 0x4 + + + PPW + Period catured in CC0, pulse width in CC1 + 0x5 + + + PWP + Period catured in CC1, pulse width in CC0 + 0x6 + + + PW + Pulse width capture + 0x7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x08 + 8 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x09 + 8 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x0A + 8 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0x0B + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + read-only + + + SLAVE + Slave Status Flag + 1 + 1 + read-only + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0x0C + 8 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0x0 + + + MFRQ + Match frequency + 0x1 + + + NPWM + Normal PWM + 0x2 + + + MPWM + Match PWM + 0x3 + + + + + + + DRVCTRL + Control C + 0x0D + 8 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x0F + 8 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT16 Count + 0x14 + 16 + + + COUNT + Counter Value + 0 + 16 + + + + + 2 + 0x2 + CC%s + COUNT16 Compare and Capture + 0x1C + 16 + + + CC + Counter/Compare Value + 0 + 16 + + + + + 2 + 0x2 + CCBUF%s + COUNT16 Compare and Capture Buffer + 0x30 + 16 + + + CCBUF + Counter/Compare Buffer Value + 0 + 16 + + + + + + COUNT32 + 32-bit Counter Mode + COUNT8 + TcCount32 + 0x0 + + CTRLA + Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + write-only + + + ENABLE + Enable + 1 + 1 + + + MODE + Timer Counter Mode + 2 + 2 + + MODESelect + + COUNT16 + Counter in 16-bit mode + 0x0 + + + COUNT8 + Counter in 8-bit mode + 0x1 + + + COUNT32 + Counter in 32-bit mode + 0x2 + + + + + PRESCSYNC + Prescaler and Counter Synchronization + 4 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset the counter on next generic clock + 0x0 + + + PRESC + Reload or reset the counter on next prescaler clock + 0x1 + + + RESYNC + Reload or reset the counter on next generic clock and reset the prescaler counter + 0x2 + + + + + RUNSTDBY + Run during Standby + 6 + 1 + + + ONDEMAND + Clock On Demand + 7 + 1 + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + Prescaler: GCLK_TC + 0x0 + + + DIV2 + Prescaler: GCLK_TC/2 + 0x1 + + + DIV4 + Prescaler: GCLK_TC/4 + 0x2 + + + DIV8 + Prescaler: GCLK_TC/8 + 0x3 + + + DIV16 + Prescaler: GCLK_TC/16 + 0x4 + + + DIV64 + Prescaler: GCLK_TC/64 + 0x5 + + + DIV256 + Prescaler: GCLK_TC/256 + 0x6 + + + DIV1024 + Prescaler: GCLK_TC/1024 + 0x7 + + + + + ALOCK + Auto Lock + 11 + 1 + + + CAPTEN0 + Capture Channel 0 Enable + 16 + 1 + + + CAPTEN1 + Capture Channel 1 Enable + 17 + 1 + + + COPEN0 + Capture On Pin 0 Enable + 20 + 1 + + + COPEN1 + Capture On Pin 1 Enable + 21 + 1 + + + CAPTMODE0 + Capture Mode Channel 0 + 24 + 2 + + CAPTMODE0Select + + DEFAULT + Default capture + 0x0 + + + CAPTMIN + Minimum capture + 0x1 + + + CAPTMAX + Maximum capture + 0x2 + + + + + CAPTMODE1 + Capture mode Channel 1 + 27 + 2 + + CAPTMODE1Select + + DEFAULT + Default capture + 0x0 + + + CAPTMIN + Minimum capture + 0x1 + + + CAPTMAX + Maximum capture + 0x2 + + + + + + + CTRLBCLR + Control B Clear + 0x04 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + UPDATE + Force update of double-buffered register + 0x3 + + + READSYNC + Force a read synchronization of COUNT + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + CTRLBSET + Control B Set + 0x05 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot on Counter + 2 + 1 + + + CMD + Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Force a start, restart or retrigger + 0x1 + + + STOP + Force a stop + 0x2 + + + UPDATE + Force update of double-buffered register + 0x3 + + + READSYNC + Force a read synchronization of COUNT + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + EVCTRL + Event Control + 0x06 + 16 + + + EVACT + Event Action + 0 + 3 + + EVACTSelect + + OFF + Event action disabled + 0x0 + + + RETRIGGER + Start, restart or retrigger TC on event + 0x1 + + + COUNT + Count on event + 0x2 + + + START + Start TC on event + 0x3 + + + STAMP + Time stamp capture + 0x4 + + + PPW + Period catured in CC0, pulse width in CC1 + 0x5 + + + PWP + Period catured in CC1, pulse width in CC0 + 0x6 + + + PW + Pulse width capture + 0x7 + + + + + TCINV + TC Event Input Polarity + 4 + 1 + + + TCEI + TC Event Enable + 5 + 1 + + + OVFEO + Event Output Enable + 8 + 1 + + + MCEO0 + MC Event Output Enable 0 + 12 + 1 + + + MCEO1 + MC Event Output Enable 1 + 13 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x08 + 8 + + + OVF + OVF Interrupt Disable + 0 + 1 + + + ERR + ERR Interrupt Disable + 1 + 1 + + + MC0 + MC Interrupt Disable 0 + 4 + 1 + + + MC1 + MC Interrupt Disable 1 + 5 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x09 + 8 + + + OVF + OVF Interrupt Enable + 0 + 1 + + + ERR + ERR Interrupt Enable + 1 + 1 + + + MC0 + MC Interrupt Enable 0 + 4 + 1 + + + MC1 + MC Interrupt Enable 1 + 5 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x0A + 8 + + + OVF + OVF Interrupt Flag + 0 + 1 + + + ERR + ERR Interrupt Flag + 1 + 1 + + + MC0 + MC Interrupt Flag 0 + 4 + 1 + + + MC1 + MC Interrupt Flag 1 + 5 + 1 + + + + + STATUS + Status + 0x0B + 8 + 0x01 + + + STOP + Stop Status Flag + 0 + 1 + read-only + + + SLAVE + Slave Status Flag + 1 + 1 + read-only + + + PERBUFV + Synchronization Busy Status + 3 + 1 + + + CCBUFV0 + Compare channel buffer 0 valid + 4 + 1 + + + CCBUFV1 + Compare channel buffer 1 valid + 5 + 1 + + + + + WAVE + Waveform Generation Control + 0x0C + 8 + + + WAVEGEN + Waveform Generation Mode + 0 + 2 + + WAVEGENSelect + + NFRQ + Normal frequency + 0x0 + + + MFRQ + Match frequency + 0x1 + + + NPWM + Normal PWM + 0x2 + + + MPWM + Match PWM + 0x3 + + + + + + + DRVCTRL + Control C + 0x0D + 8 + + + INVEN0 + Output Waveform Invert Enable 0 + 0 + 1 + + + INVEN1 + Output Waveform Invert Enable 1 + 1 + 1 + + + + + DBGCTRL + Debug Control + 0x0F + 8 + + + DBGRUN + Run During Debug + 0 + 1 + + + + + SYNCBUSY + Synchronization Status + 0x10 + 32 + read-only + + + SWRST + swrst + 0 + 1 + + + ENABLE + enable + 1 + 1 + + + CTRLB + CTRLB + 2 + 1 + + + STATUS + STATUS + 3 + 1 + + + COUNT + Counter + 4 + 1 + + + PER + Period + 5 + 1 + + + CC0 + Compare Channel 0 + 6 + 1 + + + CC1 + Compare Channel 1 + 7 + 1 + + + + + COUNT + COUNT32 Count + 0x14 + 32 + + + COUNT + Counter Value + 0 + 32 + + + + + 2 + 0x4 + CC%s + COUNT32 Compare and Capture + 0x1C + 32 + + + CC + Counter/Compare Value + 0 + 32 + + + + + 2 + 0x4 + CCBUF%s + COUNT32 Compare and Capture Buffer + 0x30 + 32 + + + CCBUF + Counter/Compare Buffer Value + 0 + 32 + + + + + + + + TC1 + Basic Timer Counter 1 + 0x40003C00 + + TC1_INTREQ + 108 + + + + TC2 + Basic Timer Counter 2 + 0x4101A000 + + TC2_INTREQ + 109 + + + + TC3 + Basic Timer Counter 3 + 0x4101C000 + + TC3_INTREQ + 110 + + + + TC4 + Basic Timer Counter 4 + 0x42001400 + + TC4_INTREQ + 111 + + + + TC5 + Basic Timer Counter 5 + 0x42001800 + + TC5_INTREQ + 112 + + + + TCC0 + 3.1.0 + Timer Counter Control 0 + TCC + TCC_ + 0x41016000 + + 0 + 0x090 + registers + + + TCC0_INTREQ_0 + 85 + + + TCC0_INTREQ_1 + 86 + + + TCC0_INTREQ_2 + 87 + + + TCC0_INTREQ_3 + 88 + + + TCC0_INTREQ_4 + 89 + + + TCC0_INTREQ_5 + 90 + + + TCC0_INTREQ_6 + 91 + + + + CTRLA + Control A + 0x00 + 32 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RESOLUTION + Enhanced Resolution + 5 + 2 + + RESOLUTIONSelect + + NONE + Dithering is disabled + 0x0 + + + DITH4 + Dithering is done every 16 PWM frames + 0x1 + + + DITH5 + Dithering is done every 32 PWM frames + 0x2 + + + DITH6 + Dithering is done every 64 PWM frames + 0x3 + + + + + PRESCALER + Prescaler + 8 + 3 + + PRESCALERSelect + + DIV1 + No division + 0x0 + + + DIV2 + Divide by 2 + 0x1 + + + DIV4 + Divide by 4 + 0x2 + + + DIV8 + Divide by 8 + 0x3 + + + DIV16 + Divide by 16 + 0x4 + + + DIV64 + Divide by 64 + 0x5 + + + DIV256 + Divide by 256 + 0x6 + + + DIV1024 + Divide by 1024 + 0x7 + + + + + RUNSTDBY + Run in Standby + 11 + 1 + + + PRESCSYNC + Prescaler and Counter Synchronization Selection + 12 + 2 + + PRESCSYNCSelect + + GCLK + Reload or reset counter on next GCLK + 0x0 + + + PRESC + Reload or reset counter on next prescaler clock + 0x1 + + + RESYNC + Reload or reset counter on next GCLK and reset prescaler counter + 0x2 + + + + + ALOCK + Auto Lock + 14 + 1 + + + MSYNC + Master Synchronization (only for TCC Slave Instance) + 15 + 1 + + + DMAOS + DMA One-shot Trigger Mode + 23 + 1 + + + CPTEN0 + Capture Channel 0 Enable + 24 + 1 + + + CPTEN1 + Capture Channel 1 Enable + 25 + 1 + + + CPTEN2 + Capture Channel 2 Enable + 26 + 1 + + + CPTEN3 + Capture Channel 3 Enable + 27 + 1 + + + CPTEN4 + Capture Channel 4 Enable + 28 + 1 + + + CPTEN5 + Capture Channel 5 Enable + 29 + 1 + + + + + CTRLBCLR + Control B Clear + 0x04 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0x0 + + + SET + Set index: cycle B will be forced in the next cycle + 0x1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 0x2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 0x3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Clear start, restart or retrigger + 0x1 + + + STOP + Force stop + 0x2 + + + UPDATE + Force update or double buffered registers + 0x3 + + + READSYNC + Force COUNT read synchronization + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + CTRLBSET + Control B Set + 0x05 + 8 + + + DIR + Counter Direction + 0 + 1 + + + LUPD + Lock Update + 1 + 1 + + + ONESHOT + One-Shot + 2 + 1 + + + IDXCMD + Ramp Index Command + 3 + 2 + + IDXCMDSelect + + DISABLE + Command disabled: Index toggles between cycles A and B + 0x0 + + + SET + Set index: cycle B will be forced in the next cycle + 0x1 + + + CLEAR + Clear index: cycle A will be forced in the next cycle + 0x2 + + + HOLD + Hold index: the next cycle will be the same as the current cycle + 0x3 + + + + + CMD + TCC Command + 5 + 3 + + CMDSelect + + NONE + No action + 0x0 + + + RETRIGGER + Clear start, restart or retrigger + 0x1 + + + STOP + Force stop + 0x2 + + + UPDATE + Force update or double buffered registers + 0x3 + + + READSYNC + Force COUNT read synchronization + 0x4 + + + DMAOS + One-shot DMA trigger + 0x5 + + + + + + + SYNCBUSY + Synchronization Busy + 0x08 + 32 + read-only + + + SWRST + Swrst Busy + 0 + 1 + + + ENABLE + Enable Busy + 1 + 1 + + + CTRLB + Ctrlb Busy + 2 + 1 + + + STATUS + Status Busy + 3 + 1 + + + COUNT + Count Busy + 4 + 1 + + + PATT + Pattern Busy + 5 + 1 + + + WAVE + Wave Busy + 6 + 1 + + + PER + Period Busy + 7 + 1 + + + CC0 + Compare Channel 0 Busy + 8 + 1 + + + CC1 + Compare Channel 1 Busy + 9 + 1 + + + CC2 + Compare Channel 2 Busy + 10 + 1 + + + CC3 + Compare Channel 3 Busy + 11 + 1 + + + CC4 + Compare Channel 4 Busy + 12 + 1 + + + CC5 + Compare Channel 5 Busy + 13 + 1 + + + + + FCTRLA + Recoverable Fault A Configuration + 0x0C + 32 + + + SRC + Fault A Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0x0 + + + ENABLE + MCEx (x=0,1) event input + 0x1 + + + INVERT + Inverted MCEx (x=0,1) event input + 0x2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 0x3 + + + + + KEEP + Fault A Keeper + 3 + 1 + + + QUAL + Fault A Qualification + 4 + 1 + + + BLANK + Fault A Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0x0 + + + RISE + Blanking applied from rising edge of the output waveform + 0x1 + + + FALL + Blanking applied from falling edge of the output waveform + 0x2 + + + BOTH + Blanking applied from each toggle of the output waveform + 0x3 + + + + + RESTART + Fault A Restart + 7 + 1 + + + HALT + Fault A Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0x0 + + + HW + Hardware halt action + 0x1 + + + SW + Software halt action + 0x2 + + + NR + Non-recoverable fault + 0x3 + + + + + CHSEL + Fault A Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0x0 + + + CC1 + Capture value stored in channel 1 + 0x1 + + + CC2 + Capture value stored in channel 2 + 0x2 + + + CC3 + Capture value stored in channel 3 + 0x3 + + + + + CAPTURE + Fault A Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0x0 + + + CAPT + Capture on fault + 0x1 + + + CAPTMIN + Minimum capture + 0x2 + + + CAPTMAX + Maximum capture + 0x3 + + + LOCMIN + Minimum local detection + 0x4 + + + LOCMAX + Maximum local detection + 0x5 + + + DERIV0 + Minimum and maximum local detection + 0x6 + + + CAPTMARK + Capture with ramp index as MSB value + 0x7 + + + + + BLANKPRESC + Fault A Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault A Blanking Time + 16 + 8 + + + FILTERVAL + Fault A Filter Value + 24 + 4 + + + + + FCTRLB + Recoverable Fault B Configuration + 0x10 + 32 + + + SRC + Fault B Source + 0 + 2 + + SRCSelect + + DISABLE + Fault input disabled + 0x0 + + + ENABLE + MCEx (x=0,1) event input + 0x1 + + + INVERT + Inverted MCEx (x=0,1) event input + 0x2 + + + ALTFAULT + Alternate fault (A or B) state at the end of the previous period + 0x3 + + + + + KEEP + Fault B Keeper + 3 + 1 + + + QUAL + Fault B Qualification + 4 + 1 + + + BLANK + Fault B Blanking Mode + 5 + 2 + + BLANKSelect + + START + Blanking applied from start of the ramp + 0x0 + + + RISE + Blanking applied from rising edge of the output waveform + 0x1 + + + FALL + Blanking applied from falling edge of the output waveform + 0x2 + + + BOTH + Blanking applied from each toggle of the output waveform + 0x3 + + + + + RESTART + Fault B Restart + 7 + 1 + + + HALT + Fault B Halt Mode + 8 + 2 + + HALTSelect + + DISABLE + Halt action disabled + 0x0 + + + HW + Hardware halt action + 0x1 + + + SW + Software halt action + 0x2 + + + NR + Non-recoverable fault + 0x3 + + + + + CHSEL + Fault B Capture Channel + 10 + 2 + + CHSELSelect + + CC0 + Capture value stored in channel 0 + 0x0 + + + CC1 + Capture value stored in channel 1 + 0x1 + + + CC2 + Capture value stored in channel 2 + 0x2 + + + CC3 + Capture value stored in channel 3 + 0x3 + + + + + CAPTURE + Fault B Capture Action + 12 + 3 + + CAPTURESelect + + DISABLE + No capture + 0x0 + + + CAPT + Capture on fault + 0x1 + + + CAPTMIN + Minimum capture + 0x2 + + + CAPTMAX + Maximum capture + 0x3 + + + LOCMIN + Minimum local detection + 0x4 + + + LOCMAX + Maximum local detection + 0x5 + + + DERIV0 + Minimum and maximum local detection + 0x6 + + + CAPTMARK + Capture with ramp index as MSB value + 0x7 + + + + + BLANKPRESC + Fault B Blanking Prescaler + 15 + 1 + + + BLANKVAL + Fault B Blanking Time + 16 + 8 + + + FILTERVAL + Fault B Filter Value + 24 + 4 + + + + + WEXCTRL + Waveform Extension Configuration + 0x14 + 32 + + + OTMX + Output Matrix + 0 + 2 + + + DTIEN0 + Dead-time Insertion Generator 0 Enable + 8 + 1 + + + DTIEN1 + Dead-time Insertion Generator 1 Enable + 9 + 1 + + + DTIEN2 + Dead-time Insertion Generator 2 Enable + 10 + 1 + + + DTIEN3 + Dead-time Insertion Generator 3 Enable + 11 + 1 + + + DTLS + Dead-time Low Side Outputs Value + 16 + 8 + + + DTHS + Dead-time High Side Outputs Value + 24 + 8 + + + + + DRVCTRL + Driver Control + 0x18 + 32 + + + NRE0 + Non-Recoverable State 0 Output Enable + 0 + 1 + + + NRE1 + Non-Recoverable State 1 Output Enable + 1 + 1 + + + NRE2 + Non-Recoverable State 2 Output Enable + 2 + 1 + + + NRE3 + Non-Recoverable State 3 Output Enable + 3 + 1 + + + NRE4 + Non-Recoverable State 4 Output Enable + 4 + 1 + + + NRE5 + Non-Recoverable State 5 Output Enable + 5 + 1 + + + NRE6 + Non-Recoverable State 6 Output Enable + 6 + 1 + + + NRE7 + Non-Recoverable State 7 Output Enable + 7 + 1 + + + NRV0 + Non-Recoverable State 0 Output Value + 8 + 1 + + + NRV1 + Non-Recoverable State 1 Output Value + 9 + 1 + + + NRV2 + Non-Recoverable State 2 Output Value + 10 + 1 + + + NRV3 + Non-Recoverable State 3 Output Value + 11 + 1 + + + NRV4 + Non-Recoverable State 4 Output Value + 12 + 1 + + + NRV5 + Non-Recoverable State 5 Output Value + 13 + 1 + + + NRV6 + Non-Recoverable State 6 Output Value + 14 + 1 + + + NRV7 + Non-Recoverable State 7 Output Value + 15 + 1 + + + INVEN0 + Output Waveform 0 Inversion + 16 + 1 + + + INVEN1 + Output Waveform 1 Inversion + 17 + 1 + + + INVEN2 + Output Waveform 2 Inversion + 18 + 1 + + + INVEN3 + Output Waveform 3 Inversion + 19 + 1 + + + INVEN4 + Output Waveform 4 Inversion + 20 + 1 + + + INVEN5 + Output Waveform 5 Inversion + 21 + 1 + + + INVEN6 + Output Waveform 6 Inversion + 22 + 1 + + + INVEN7 + Output Waveform 7 Inversion + 23 + 1 + + + FILTERVAL0 + Non-Recoverable Fault Input 0 Filter Value + 24 + 4 + + + FILTERVAL1 + Non-Recoverable Fault Input 1 Filter Value + 28 + 4 + + + + + DBGCTRL + Debug Control + 0x1E + 8 + + + DBGRUN + Debug Running Mode + 0 + 1 + + + FDDBD + Fault Detection on Debug Break Detection + 2 + 1 + + + + + EVCTRL + Event Control + 0x20 + 32 + + + EVACT0 + Timer/counter Input Event0 Action + 0 + 3 + + EVACT0Select + + OFF + Event action disabled + 0x0 + + + RETRIGGER + Start, restart or re-trigger counter on event + 0x1 + + + COUNTEV + Count on event + 0x2 + + + START + Start counter on event + 0x3 + + + INC + Increment counter on event + 0x4 + + + COUNT + Count on active state of asynchronous event + 0x5 + + + STAMP + Stamp capture + 0x6 + + + FAULT + Non-recoverable fault + 0x7 + + + + + EVACT1 + Timer/counter Input Event1 Action + 3 + 3 + + EVACT1Select + + OFF + Event action disabled + 0x0 + + + RETRIGGER + Re-trigger counter on event + 0x1 + + + DIR + Direction control + 0x2 + + + STOP + Stop counter on event + 0x3 + + + DEC + Decrement counter on event + 0x4 + + + PPW + Period capture value in CC0 register, pulse width capture value in CC1 register + 0x5 + + + PWP + Period capture value in CC1 register, pulse width capture value in CC0 register + 0x6 + + + FAULT + Non-recoverable fault + 0x7 + + + + + CNTSEL + Timer/counter Output Event Mode + 6 + 2 + + CNTSELSelect + + START + An interrupt/event is generated when a new counter cycle starts + 0x0 + + + END + An interrupt/event is generated when a counter cycle ends + 0x1 + + + BETWEEN + An interrupt/event is generated when a counter cycle ends, except for the first and last cycles + 0x2 + + + BOUNDARY + An interrupt/event is generated when a new counter cycle starts or a counter cycle ends + 0x3 + + + + + OVFEO + Overflow/Underflow Output Event Enable + 8 + 1 + + + TRGEO + Retrigger Output Event Enable + 9 + 1 + + + CNTEO + Timer/counter Output Event Enable + 10 + 1 + + + TCINV0 + Inverted Event 0 Input Enable + 12 + 1 + + + TCINV1 + Inverted Event 1 Input Enable + 13 + 1 + + + TCEI0 + Timer/counter Event 0 Input Enable + 14 + 1 + + + TCEI1 + Timer/counter Event 1 Input Enable + 15 + 1 + + + MCEI0 + Match or Capture Channel 0 Event Input Enable + 16 + 1 + + + MCEI1 + Match or Capture Channel 1 Event Input Enable + 17 + 1 + + + MCEI2 + Match or Capture Channel 2 Event Input Enable + 18 + 1 + + + MCEI3 + Match or Capture Channel 3 Event Input Enable + 19 + 1 + + + MCEI4 + Match or Capture Channel 4 Event Input Enable + 20 + 1 + + + MCEI5 + Match or Capture Channel 5 Event Input Enable + 21 + 1 + + + MCEO0 + Match or Capture Channel 0 Event Output Enable + 24 + 1 + + + MCEO1 + Match or Capture Channel 1 Event Output Enable + 25 + 1 + + + MCEO2 + Match or Capture Channel 2 Event Output Enable + 26 + 1 + + + MCEO3 + Match or Capture Channel 3 Event Output Enable + 27 + 1 + + + MCEO4 + Match or Capture Channel 4 Event Output Enable + 28 + 1 + + + MCEO5 + Match or Capture Channel 5 Event Output Enable + 29 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x24 + 32 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + MC4 + Match or Capture Channel 4 Interrupt Enable + 20 + 1 + + + MC5 + Match or Capture Channel 5 Interrupt Enable + 21 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x28 + 32 + + + OVF + Overflow Interrupt Enable + 0 + 1 + + + TRG + Retrigger Interrupt Enable + 1 + 1 + + + CNT + Counter Interrupt Enable + 2 + 1 + + + ERR + Error Interrupt Enable + 3 + 1 + + + UFS + Non-Recoverable Update Fault Interrupt Enable + 10 + 1 + + + DFS + Non-Recoverable Debug Fault Interrupt Enable + 11 + 1 + + + FAULTA + Recoverable Fault A Interrupt Enable + 12 + 1 + + + FAULTB + Recoverable Fault B Interrupt Enable + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 Interrupt Enable + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 Interrupt Enable + 15 + 1 + + + MC0 + Match or Capture Channel 0 Interrupt Enable + 16 + 1 + + + MC1 + Match or Capture Channel 1 Interrupt Enable + 17 + 1 + + + MC2 + Match or Capture Channel 2 Interrupt Enable + 18 + 1 + + + MC3 + Match or Capture Channel 3 Interrupt Enable + 19 + 1 + + + MC4 + Match or Capture Channel 4 Interrupt Enable + 20 + 1 + + + MC5 + Match or Capture Channel 5 Interrupt Enable + 21 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x2C + 32 + + + OVF + Overflow + 0 + 1 + + + TRG + Retrigger + 1 + 1 + + + CNT + Counter + 2 + 1 + + + ERR + Error + 3 + 1 + + + UFS + Non-Recoverable Update Fault + 10 + 1 + + + DFS + Non-Recoverable Debug Fault + 11 + 1 + + + FAULTA + Recoverable Fault A + 12 + 1 + + + FAULTB + Recoverable Fault B + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 + 15 + 1 + + + MC0 + Match or Capture 0 + 16 + 1 + + + MC1 + Match or Capture 1 + 17 + 1 + + + MC2 + Match or Capture 2 + 18 + 1 + + + MC3 + Match or Capture 3 + 19 + 1 + + + MC4 + Match or Capture 4 + 20 + 1 + + + MC5 + Match or Capture 5 + 21 + 1 + + + + + STATUS + Status + 0x30 + 32 + 0x00000001 + + + STOP + Stop + 0 + 1 + read-only + + + IDX + Ramp + 1 + 1 + read-only + + + UFS + Non-recoverable Update Fault State + 2 + 1 + + + DFS + Non-Recoverable Debug Fault State + 3 + 1 + + + SLAVE + Slave + 4 + 1 + read-only + + + PATTBUFV + Pattern Buffer Valid + 5 + 1 + + + PERBUFV + Period Buffer Valid + 7 + 1 + + + FAULTAIN + Recoverable Fault A Input + 8 + 1 + read-only + + + FAULTBIN + Recoverable Fault B Input + 9 + 1 + read-only + + + FAULT0IN + Non-Recoverable Fault0 Input + 10 + 1 + read-only + + + FAULT1IN + Non-Recoverable Fault1 Input + 11 + 1 + read-only + + + FAULTA + Recoverable Fault A State + 12 + 1 + + + FAULTB + Recoverable Fault B State + 13 + 1 + + + FAULT0 + Non-Recoverable Fault 0 State + 14 + 1 + + + FAULT1 + Non-Recoverable Fault 1 State + 15 + 1 + + + CCBUFV0 + Compare Channel 0 Buffer Valid + 16 + 1 + + + CCBUFV1 + Compare Channel 1 Buffer Valid + 17 + 1 + + + CCBUFV2 + Compare Channel 2 Buffer Valid + 18 + 1 + + + CCBUFV3 + Compare Channel 3 Buffer Valid + 19 + 1 + + + CCBUFV4 + Compare Channel 4 Buffer Valid + 20 + 1 + + + CCBUFV5 + Compare Channel 5 Buffer Valid + 21 + 1 + + + CMP0 + Compare Channel 0 Value + 24 + 1 + read-only + + + CMP1 + Compare Channel 1 Value + 25 + 1 + read-only + + + CMP2 + Compare Channel 2 Value + 26 + 1 + read-only + + + CMP3 + Compare Channel 3 Value + 27 + 1 + read-only + + + CMP4 + Compare Channel 4 Value + 28 + 1 + read-only + + + CMP5 + Compare Channel 5 Value + 29 + 1 + read-only + + + + + COUNT + Count + 0x34 + 32 + + + COUNT + Counter Value + 0 + 24 + + + + + COUNT_DITH4 + Count + COUNT + 0x34 + 32 + + + COUNT + Counter Value + 4 + 20 + + + + + COUNT_DITH5 + Count + COUNT + 0x34 + 32 + + + COUNT + Counter Value + 5 + 19 + + + + + COUNT_DITH6 + Count + COUNT + 0x34 + 32 + + + COUNT + Counter Value + 6 + 18 + + + + + PATT + Pattern + 0x38 + 16 + + + PGE0 + Pattern Generator 0 Output Enable + 0 + 1 + + + PGE1 + Pattern Generator 1 Output Enable + 1 + 1 + + + PGE2 + Pattern Generator 2 Output Enable + 2 + 1 + + + PGE3 + Pattern Generator 3 Output Enable + 3 + 1 + + + PGE4 + Pattern Generator 4 Output Enable + 4 + 1 + + + PGE5 + Pattern Generator 5 Output Enable + 5 + 1 + + + PGE6 + Pattern Generator 6 Output Enable + 6 + 1 + + + PGE7 + Pattern Generator 7 Output Enable + 7 + 1 + + + PGV0 + Pattern Generator 0 Output Value + 8 + 1 + + + PGV1 + Pattern Generator 1 Output Value + 9 + 1 + + + PGV2 + Pattern Generator 2 Output Value + 10 + 1 + + + PGV3 + Pattern Generator 3 Output Value + 11 + 1 + + + PGV4 + Pattern Generator 4 Output Value + 12 + 1 + + + PGV5 + Pattern Generator 5 Output Value + 13 + 1 + + + PGV6 + Pattern Generator 6 Output Value + 14 + 1 + + + PGV7 + Pattern Generator 7 Output Value + 15 + 1 + + + + + WAVE + Waveform Control + 0x3C + 32 + + + WAVEGEN + Waveform Generation + 0 + 3 + + WAVEGENSelect + + NFRQ + Normal frequency + 0x0 + + + MFRQ + Match frequency + 0x1 + + + NPWM + Normal PWM + 0x2 + + + DSCRITICAL + Dual-slope critical + 0x4 + + + DSBOTTOM + Dual-slope with interrupt/event condition when COUNT reaches ZERO + 0x5 + + + DSBOTH + Dual-slope with interrupt/event condition when COUNT reaches ZERO or TOP + 0x6 + + + DSTOP + Dual-slope with interrupt/event condition when COUNT reaches TOP + 0x7 + + + + + RAMP + Ramp Mode + 4 + 2 + + RAMPSelect + + RAMP1 + RAMP1 operation + 0x0 + + + RAMP2A + Alternative RAMP2 operation + 0x1 + + + RAMP2 + RAMP2 operation + 0x2 + + + RAMP2C + Critical RAMP2 operation + 0x3 + + + + + CIPEREN + Circular period Enable + 7 + 1 + + + CICCEN0 + Circular Channel 0 Enable + 8 + 1 + + + CICCEN1 + Circular Channel 1 Enable + 9 + 1 + + + CICCEN2 + Circular Channel 2 Enable + 10 + 1 + + + CICCEN3 + Circular Channel 3 Enable + 11 + 1 + + + POL0 + Channel 0 Polarity + 16 + 1 + + + POL1 + Channel 1 Polarity + 17 + 1 + + + POL2 + Channel 2 Polarity + 18 + 1 + + + POL3 + Channel 3 Polarity + 19 + 1 + + + POL4 + Channel 4 Polarity + 20 + 1 + + + POL5 + Channel 5 Polarity + 21 + 1 + + + SWAP0 + Swap DTI Output Pair 0 + 24 + 1 + + + SWAP1 + Swap DTI Output Pair 1 + 25 + 1 + + + SWAP2 + Swap DTI Output Pair 2 + 26 + 1 + + + SWAP3 + Swap DTI Output Pair 3 + 27 + 1 + + + + + PER + Period + 0x40 + 32 + 0xFFFFFFFF + + + PER + Period Value + 0 + 24 + + + + + PER_DITH4 + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 4 + + + PER + Period Value + 4 + 20 + + + + + PER_DITH5 + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 5 + + + PER + Period Value + 5 + 19 + + + + + PER_DITH6 + Period + PER + 0x40 + 32 + 0xFFFFFFFF + + + DITHER + Dithering Cycle Number + 0 + 6 + + + PER + Period Value + 6 + 18 + + + + + 6 + 0x4 + CC%s + Compare and Capture + 0x44 + 32 + + + CC + Channel Compare/Capture Value + 0 + 24 + + + + + 6 + 0x4 + CC%s_DITH4 + Compare and Capture + CC%s + 0x44 + 32 + + + DITHER + Dithering Cycle Number + 0 + 4 + + + CC + Channel Compare/Capture Value + 4 + 20 + + + + + 6 + 0x4 + CC%s_DITH5 + Compare and Capture + CC%s + 0x44 + 32 + + + DITHER + Dithering Cycle Number + 0 + 5 + + + CC + Channel Compare/Capture Value + 5 + 19 + + + + + 6 + 0x4 + CC%s_DITH6 + Compare and Capture + CC%s + 0x44 + 32 + + + DITHER + Dithering Cycle Number + 0 + 6 + + + CC + Channel Compare/Capture Value + 6 + 18 + + + + + PATTBUF + Pattern Buffer + 0x64 + 16 + + + PGEB0 + Pattern Generator 0 Output Enable Buffer + 0 + 1 + + + PGEB1 + Pattern Generator 1 Output Enable Buffer + 1 + 1 + + + PGEB2 + Pattern Generator 2 Output Enable Buffer + 2 + 1 + + + PGEB3 + Pattern Generator 3 Output Enable Buffer + 3 + 1 + + + PGEB4 + Pattern Generator 4 Output Enable Buffer + 4 + 1 + + + PGEB5 + Pattern Generator 5 Output Enable Buffer + 5 + 1 + + + PGEB6 + Pattern Generator 6 Output Enable Buffer + 6 + 1 + + + PGEB7 + Pattern Generator 7 Output Enable Buffer + 7 + 1 + + + PGVB0 + Pattern Generator 0 Output Enable + 8 + 1 + + + PGVB1 + Pattern Generator 1 Output Enable + 9 + 1 + + + PGVB2 + Pattern Generator 2 Output Enable + 10 + 1 + + + PGVB3 + Pattern Generator 3 Output Enable + 11 + 1 + + + PGVB4 + Pattern Generator 4 Output Enable + 12 + 1 + + + PGVB5 + Pattern Generator 5 Output Enable + 13 + 1 + + + PGVB6 + Pattern Generator 6 Output Enable + 14 + 1 + + + PGVB7 + Pattern Generator 7 Output Enable + 15 + 1 + + + + + PERBUF + Period Buffer + 0x6C + 32 + 0xFFFFFFFF + + + PERBUF + Period Buffer Value + 0 + 24 + + + + + PERBUF_DITH4 + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 4 + + + PERBUF + Period Buffer Value + 4 + 20 + + + + + PERBUF_DITH5 + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + PERBUF + Period Buffer Value + 5 + 19 + + + + + PERBUF_DITH6 + Period Buffer + PERBUF + 0x6C + 32 + 0xFFFFFFFF + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + PERBUF + Period Buffer Value + 6 + 18 + + + + + 6 + 0x4 + CCBUF%s + Compare and Capture Buffer + 0x70 + 32 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 24 + + + + + 6 + 0x4 + CCBUF%s_DITH4 + Compare and Capture Buffer + CCBUF%s + 0x70 + 32 + + + CCBUF + Channel Compare/Capture Buffer Value + 0 + 4 + + + DITHERBUF + Dithering Buffer Cycle Number + 4 + 20 + + + + + 6 + 0x4 + CCBUF%s_DITH5 + Compare and Capture Buffer + CCBUF%s + 0x70 + 32 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 5 + + + CCBUF + Channel Compare/Capture Buffer Value + 5 + 19 + + + + + 6 + 0x4 + CCBUF%s_DITH6 + Compare and Capture Buffer + CCBUF%s + 0x70 + 32 + + + DITHERBUF + Dithering Buffer Cycle Number + 0 + 6 + + + CCBUF + Channel Compare/Capture Buffer Value + 6 + 18 + + + + + + + TCC1 + Timer Counter Control 1 + 0x41018000 + + TCC1_INTREQ_0 + 92 + + + TCC1_INTREQ_1 + 93 + + + TCC1_INTREQ_2 + 94 + + + TCC1_INTREQ_3 + 95 + + + TCC1_INTREQ_4 + 96 + + + + TCC2 + Timer Counter Control 2 + 0x42000C00 + + TCC2_INTREQ_0 + 97 + + + TCC2_INTREQ_1 + 98 + + + TCC2_INTREQ_2 + 99 + + + TCC2_INTREQ_3 + 100 + + + + TCC3 + Timer Counter Control 3 + 0x42001000 + + TCC3_INTREQ_0 + 101 + + + TCC3_INTREQ_1 + 102 + + + TCC3_INTREQ_2 + 103 + + + + TCC4 + Timer Counter Control 4 + 0x43001000 + + TCC4_INTREQ_0 + 104 + + + TCC4_INTREQ_1 + 105 + + + TCC4_INTREQ_2 + 106 + + + + TRNG + 1.1.0 + True Random Generator + TRNG + TRNG_ + 0x42002800 + + 0 + 0x40 + registers + + + TRNG_INTREQ + 131 + + + + CTRLA + Control A + 0x00 + 8 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby + 6 + 1 + + + + + EVCTRL + Event Control + 0x04 + 8 + + + DATARDYEO + Data Ready Event Output + 0 + 1 + + + + + INTENCLR + Interrupt Enable Clear + 0x08 + 8 + + + DATARDY + Data Ready Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x09 + 8 + + + DATARDY + Data Ready Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x0A + 8 + + + DATARDY + Data Ready Interrupt Flag + 0 + 1 + + + + + DATA + Output Data + 0x20 + 32 + read-only + + + DATA + Output Data + 0 + 32 + read-only + + + + + + + USB + 1.2.0 + Universal Serial Bus + USB + USB_ + 0x41000000 + + 0 + 0x400 + registers + + + USB_INTREQ_0 + 80 + + + USB_INTREQ_1 + 81 + + + USB_INTREQ_2 + 82 + + + USB_INTREQ_3 + 83 + + + + DEVICE + USB is Device + UsbDevice + 0x0 + + CTRLA + Control A + 0x000 + 8 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0x0 + + + HOST + Host Mode + 0x1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x002 + 8 + read-only + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + read-only + + + ENABLE + Enable Synchronization Busy + 1 + 1 + read-only + + + + + QOSCTRL + USB Quality Of Service + 0x003 + 8 + 0x0F + + + CQOS + Configuration Quality of Service + 0 + 2 + + + DQOS + Data Quality of Service + 2 + 2 + + + + + CTRLB + DEVICE Control B + 0x008 + 16 + 0x0001 + + + DETACH + Detach + 0 + 1 + + + UPRSM + Upstream Resume + 1 + 1 + + + SPDCONF + Speed Configuration + 2 + 2 + + SPDCONFSelect + + FS + FS : Full Speed + 0x0 + + + LS + LS : Low Speed + 0x1 + + + HS + HS : High Speed capable + 0x2 + + + HSTM + HSTM: High Speed Test Mode (force high-speed mode for test mode) + 0x3 + + + + + NREPLY + No Reply + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + TSTPCKT + Test packet mode + 7 + 1 + + + OPMODE2 + Specific Operational Mode + 8 + 1 + + + GNAK + Global NAK + 9 + 1 + + + LPMHDSK + Link Power Management Handshake + 10 + 2 + + LPMHDSKSelect + + NO + No handshake. LPM is not supported + 0x0 + + + ACK + ACK + 0x1 + + + NYET + NYET + 0x2 + + + STALL + STALL + 0x3 + + + + + + + DADD + DEVICE Device Address + 0x00A + 8 + + + DADD + Device Address + 0 + 7 + + + ADDEN + Device Address Enable + 7 + 1 + + + + + STATUS + DEVICE Status + 0x00C + 8 + read-only + 0x40 + + + SPEED + Speed Status + 2 + 2 + read-only + + SPEEDSelect + + FS + Full-speed mode + 0x0 + + + LS + Low-speed mode + 0x1 + + + HS + High-speed mode + 0x2 + + + + + LINESTATE + USB Line State Status + 6 + 2 + read-only + + LINESTATESelect + + 0 + SE0/RESET + 0x0 + + + 1 + FS-J or LS-K State + 0x1 + + + 2 + FS-K or LS-J State + 0x2 + + + + + + + FSMSTATUS + Finite State Machine Status + 0x00D + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + read-only + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + DEVICE Device Frame Number + 0x010 + 16 + read-only + + + MFNUM + Micro Frame Number + 0 + 3 + read-only + + + FNUM + Frame Number + 3 + 11 + read-only + + + FNCERR + Frame Number CRC Error + 15 + 1 + read-only + + + + + INTENCLR + DEVICE Device Interrupt Enable Clear + 0x014 + 16 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTENSET + DEVICE Device Interrupt Enable Set + 0x018 + 16 + + + SUSPEND + Suspend Interrupt Enable + 0 + 1 + + + MSOF + Micro Start of Frame Interrupt Enable in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame Interrupt Enable + 2 + 1 + + + EORST + End of Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + EORSM + End Of Resume Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + LPMNYET + Link Power Management Not Yet Interrupt Enable + 8 + 1 + + + LPMSUSP + Link Power Management Suspend Interrupt Enable + 9 + 1 + + + + + INTFLAG + DEVICE Device Interrupt Flag + 0x01C + 16 + + + SUSPEND + Suspend + 0 + 1 + + + MSOF + Micro Start of Frame in High Speed Mode + 1 + 1 + + + SOF + Start Of Frame + 2 + 1 + + + EORST + End of Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + EORSM + End Of Resume + 5 + 1 + + + UPRSM + Upstream Resume + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + LPMNYET + Link Power Management Not Yet + 8 + 1 + + + LPMSUSP + Link Power Management Suspend + 9 + 1 + + + + + EPINTSMRY + DEVICE End Point Interrupt Summary + 0x020 + 16 + read-only + + + EPINT0 + End Point 0 Interrupt + 0 + 1 + read-only + + + EPINT1 + End Point 1 Interrupt + 1 + 1 + read-only + + + EPINT2 + End Point 2 Interrupt + 2 + 1 + read-only + + + EPINT3 + End Point 3 Interrupt + 3 + 1 + read-only + + + EPINT4 + End Point 4 Interrupt + 4 + 1 + read-only + + + EPINT5 + End Point 5 Interrupt + 5 + 1 + read-only + + + EPINT6 + End Point 6 Interrupt + 6 + 1 + read-only + + + EPINT7 + End Point 7 Interrupt + 7 + 1 + read-only + + + + + DESCADD + Descriptor Address + 0x024 + 32 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x028 + 16 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + EPCFG%s + DEVICE End Point Configuration + 0x100 + 8 + + + EPTYPE0 + End Point Type0 + 0 + 3 + + + EPTYPE1 + End Point Type1 + 4 + 3 + + + NYETDIS + NYET Token Disable + 7 + 1 + + + + + 8 + 0x20 + EPSTATUSCLR%s + DEVICE End Point Pipe Status Clear + 0x104 + 8 + write-only + + + DTGLOUT + Data Toggle OUT Clear + 0 + 1 + write-only + + + DTGLIN + Data Toggle IN Clear + 1 + 1 + write-only + + + CURBK + Current Bank Clear + 2 + 1 + write-only + + + STALLRQ0 + Stall 0 Request Clear + 4 + 1 + write-only + + + STALLRQ1 + Stall 1 Request Clear + 5 + 1 + write-only + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + write-only + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + write-only + + + + + 8 + 0x20 + EPSTATUSSET%s + DEVICE End Point Pipe Status Set + 0x105 + 8 + write-only + + + DTGLOUT + Data Toggle OUT Set + 0 + 1 + write-only + + + DTGLIN + Data Toggle IN Set + 1 + 1 + write-only + + + CURBK + Current Bank Set + 2 + 1 + write-only + + + STALLRQ0 + Stall 0 Request Set + 4 + 1 + write-only + + + STALLRQ1 + Stall 1 Request Set + 5 + 1 + write-only + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + write-only + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + write-only + + + + + 8 + 0x20 + EPSTATUS%s + DEVICE End Point Pipe Status + 0x106 + 8 + read-only + + + DTGLOUT + Data Toggle Out + 0 + 1 + read-only + + + DTGLIN + Data Toggle In + 1 + 1 + read-only + + + CURBK + Current Bank + 2 + 1 + read-only + + + STALLRQ0 + Stall 0 Request + 4 + 1 + read-only + + + STALLRQ1 + Stall 1 Request + 5 + 1 + read-only + + + BK0RDY + Bank 0 ready + 6 + 1 + read-only + + + BK1RDY + Bank 1 ready + 7 + 1 + read-only + + + + + 8 + 0x20 + EPINTFLAG%s + DEVICE End Point Interrupt Flag + 0x107 + 8 + + + TRCPT0 + Transfer Complete 0 + 0 + 1 + + + TRCPT1 + Transfer Complete 1 + 1 + 1 + + + TRFAIL0 + Error Flow 0 + 2 + 1 + + + TRFAIL1 + Error Flow 1 + 3 + 1 + + + RXSTP + Received Setup + 4 + 1 + + + STALL0 + Stall 0 In/out + 5 + 1 + + + STALL1 + Stall 1 In/out + 6 + 1 + + + + + 8 + 0x20 + EPINTENCLR%s + DEVICE End Point Interrupt Clear Flag + 0x108 + 8 + + + TRCPT0 + Transfer Complete 0 Interrupt Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Disable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Disable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Disable + 3 + 1 + + + RXSTP + Received Setup Interrupt Disable + 4 + 1 + + + STALL0 + Stall 0 In/Out Interrupt Disable + 5 + 1 + + + STALL1 + Stall 1 In/Out Interrupt Disable + 6 + 1 + + + + + 8 + 0x20 + EPINTENSET%s + DEVICE End Point Interrupt Set Flag + 0x109 + 8 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL0 + Error Flow 0 Interrupt Enable + 2 + 1 + + + TRFAIL1 + Error Flow 1 Interrupt Enable + 3 + 1 + + + RXSTP + Received Setup Interrupt Enable + 4 + 1 + + + STALL0 + Stall 0 In/out Interrupt enable + 5 + 1 + + + STALL1 + Stall 1 In/out Interrupt enable + 6 + 1 + + + + + + HOST + USB is Host + DEVICE + UsbHost + 0x0 + + CTRLA + Control A + 0x000 + 8 + + + SWRST + Software Reset + 0 + 1 + + + ENABLE + Enable + 1 + 1 + + + RUNSTDBY + Run in Standby Mode + 2 + 1 + + + MODE + Operating Mode + 7 + 1 + + MODESelect + + DEVICE + Device Mode + 0x0 + + + HOST + Host Mode + 0x1 + + + + + + + SYNCBUSY + Synchronization Busy + 0x002 + 8 + read-only + + + SWRST + Software Reset Synchronization Busy + 0 + 1 + read-only + + + ENABLE + Enable Synchronization Busy + 1 + 1 + read-only + + + + + QOSCTRL + USB Quality Of Service + 0x003 + 8 + 0x0F + + + CQOS + Configuration Quality of Service + 0 + 2 + + + DQOS + Data Quality of Service + 2 + 2 + + + + + CTRLB + HOST Control B + 0x008 + 16 + + + RESUME + Send USB Resume + 1 + 1 + + + SPDCONF + Speed Configuration for Host + 2 + 2 + + SPDCONFSelect + + NORMAL + Normal mode: the host starts in full-speed mode and performs a high-speed reset to switch to the high speed mode if the downstream peripheral is high-speed capable. + 0x0 + + + FS + Full-speed: the host remains in full-speed mode whatever is the peripheral speed capability. Relevant in UTMI mode only. + 0x3 + + + + + AUTORESUME + Auto Resume Enable + 4 + 1 + + + TSTJ + Test mode J + 5 + 1 + + + TSTK + Test mode K + 6 + 1 + + + SOFE + Start of Frame Generation Enable + 8 + 1 + + + BUSRESET + Send USB Reset + 9 + 1 + + + VBUSOK + VBUS is OK + 10 + 1 + + + L1RESUME + Send L1 Resume + 11 + 1 + + + + + HSOFC + HOST Host Start Of Frame Control + 0x00A + 8 + + + FLENC + Frame Length Control + 0 + 4 + + + FLENCE + Frame Length Control Enable + 7 + 1 + + + + + STATUS + HOST Status + 0x00C + 8 + + + SPEED + Speed Status + 2 + 2 + + + LINESTATE + USB Line State Status + 6 + 2 + read-only + + + + + FSMSTATUS + Finite State Machine Status + 0x00D + 8 + read-only + 0x01 + + + FSMSTATE + Fine State Machine Status + 0 + 7 + read-only + + FSMSTATESelect + + OFF + OFF (L3). It corresponds to the powered-off, disconnected, and disabled state + 0x1 + + + ON + ON (L0). It corresponds to the Idle and Active states + 0x2 + + + SUSPEND + SUSPEND (L2) + 0x4 + + + SLEEP + SLEEP (L1) + 0x8 + + + DNRESUME + DNRESUME. Down Stream Resume. + 0x10 + + + UPRESUME + UPRESUME. Up Stream Resume. + 0x20 + + + RESET + RESET. USB lines Reset. + 0x40 + + + + + + + FNUM + HOST Host Frame Number + 0x010 + 16 + + + MFNUM + Micro Frame Number + 0 + 3 + + + FNUM + Frame Number + 3 + 11 + + + + + FLENHIGH + HOST Host Frame Length + 0x012 + 8 + read-only + + + FLENHIGH + Frame Length + 0 + 8 + read-only + + + + + INTENCLR + HOST Host Interrupt Enable Clear + 0x014 + 16 + + + HSOF + Host Start Of Frame Interrupt Disable + 2 + 1 + + + RST + BUS Reset Interrupt Disable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Disable + 4 + 1 + + + DNRSM + DownStream to Device Interrupt Disable + 5 + 1 + + + UPRSM + Upstream Resume from Device Interrupt Disable + 6 + 1 + + + RAMACER + Ram Access Interrupt Disable + 7 + 1 + + + DCONN + Device Connection Interrupt Disable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Disable + 9 + 1 + + + + + INTENSET + HOST Host Interrupt Enable Set + 0x018 + 16 + + + HSOF + Host Start Of Frame Interrupt Enable + 2 + 1 + + + RST + Bus Reset Interrupt Enable + 3 + 1 + + + WAKEUP + Wake Up Interrupt Enable + 4 + 1 + + + DNRSM + DownStream to the Device Interrupt Enable + 5 + 1 + + + UPRSM + Upstream Resume fromthe device Interrupt Enable + 6 + 1 + + + RAMACER + Ram Access Interrupt Enable + 7 + 1 + + + DCONN + Link Power Management Interrupt Enable + 8 + 1 + + + DDISC + Device Disconnection Interrupt Enable + 9 + 1 + + + + + INTFLAG + HOST Host Interrupt Flag + 0x01C + 16 + + + HSOF + Host Start Of Frame + 2 + 1 + + + RST + Bus Reset + 3 + 1 + + + WAKEUP + Wake Up + 4 + 1 + + + DNRSM + Downstream + 5 + 1 + + + UPRSM + Upstream Resume from the Device + 6 + 1 + + + RAMACER + Ram Access + 7 + 1 + + + DCONN + Device Connection + 8 + 1 + + + DDISC + Device Disconnection + 9 + 1 + + + + + PINTSMRY + HOST Pipe Interrupt Summary + 0x020 + 16 + read-only + + + EPINT0 + Pipe 0 Interrupt + 0 + 1 + read-only + + + EPINT1 + Pipe 1 Interrupt + 1 + 1 + read-only + + + EPINT2 + Pipe 2 Interrupt + 2 + 1 + read-only + + + EPINT3 + Pipe 3 Interrupt + 3 + 1 + read-only + + + EPINT4 + Pipe 4 Interrupt + 4 + 1 + read-only + + + EPINT5 + Pipe 5 Interrupt + 5 + 1 + read-only + + + EPINT6 + Pipe 6 Interrupt + 6 + 1 + read-only + + + EPINT7 + Pipe 7 Interrupt + 7 + 1 + read-only + + + + + DESCADD + Descriptor Address + 0x024 + 32 + + + DESCADD + Descriptor Address Value + 0 + 32 + + + + + PADCAL + USB PAD Calibration + 0x028 + 16 + + + TRANSP + USB Pad Transp calibration + 0 + 5 + + + TRANSN + USB Pad Transn calibration + 6 + 5 + + + TRIM + USB Pad Trim calibration + 12 + 3 + + + + + 8 + 0x20 + PCFG%s + HOST End Point Configuration + 0x100 + 8 + + + PTOKEN + Pipe Token + 0 + 2 + + + BK + Pipe Bank + 2 + 1 + + + PTYPE + Pipe Type + 3 + 3 + + + + + 8 + 0x20 + BINTERVAL%s + HOST Bus Access Period of Pipe + 0x103 + 8 + + + BITINTERVAL + Bit Interval + 0 + 8 + + + + + 8 + 0x20 + PSTATUSCLR%s + HOST End Point Pipe Status Clear + 0x104 + 8 + write-only + + + DTGL + Data Toggle clear + 0 + 1 + read-only + + + CURBK + Curren Bank clear + 2 + 1 + write-only + + + PFREEZE + Pipe Freeze Clear + 4 + 1 + write-only + + + BK0RDY + Bank 0 Ready Clear + 6 + 1 + write-only + + + BK1RDY + Bank 1 Ready Clear + 7 + 1 + write-only + + + + + 8 + 0x20 + PSTATUSSET%s + HOST End Point Pipe Status Set + 0x105 + 8 + write-only + + + DTGL + Data Toggle Set + 0 + 1 + write-only + + + CURBK + Current Bank Set + 2 + 1 + write-only + + + PFREEZE + Pipe Freeze Set + 4 + 1 + write-only + + + BK0RDY + Bank 0 Ready Set + 6 + 1 + write-only + + + BK1RDY + Bank 1 Ready Set + 7 + 1 + write-only + + + + + 8 + 0x20 + PSTATUS%s + HOST End Point Pipe Status + 0x106 + 8 + read-only + + + DTGL + Data Toggle + 0 + 1 + read-only + + + CURBK + Current Bank + 2 + 1 + read-only + + + PFREEZE + Pipe Freeze + 4 + 1 + read-only + + + BK0RDY + Bank 0 ready + 6 + 1 + read-only + + + BK1RDY + Bank 1 ready + 7 + 1 + read-only + + + + + 8 + 0x20 + PINTFLAG%s + HOST Pipe Interrupt Flag + 0x107 + 8 + + + TRCPT0 + Transfer Complete 0 Interrupt Flag + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Flag + 1 + 1 + + + TRFAIL + Error Flow Interrupt Flag + 2 + 1 + + + PERR + Pipe Error Interrupt Flag + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Flag + 4 + 1 + + + STALL + Stall Interrupt Flag + 5 + 1 + + + + + 8 + 0x20 + PINTENCLR%s + HOST Pipe Interrupt Flag Clear + 0x108 + 8 + + + TRCPT0 + Transfer Complete 0 Disable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Disable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Disable + 2 + 1 + + + PERR + Pipe Error Interrupt Disable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Disable + 4 + 1 + + + STALL + Stall Inetrrupt Disable + 5 + 1 + + + + + 8 + 0x20 + PINTENSET%s + HOST Pipe Interrupt Flag Set + 0x109 + 8 + + + TRCPT0 + Transfer Complete 0 Interrupt Enable + 0 + 1 + + + TRCPT1 + Transfer Complete 1 Interrupt Enable + 1 + 1 + + + TRFAIL + Error Flow Interrupt Enable + 2 + 1 + + + PERR + Pipe Error Interrupt Enable + 3 + 1 + + + TXSTP + Transmit Setup Interrupt Enable + 4 + 1 + + + STALL + Stall Interrupt Enable + 5 + 1 + + + + + + + + WDT + 1.1.0 + Watchdog Timer + WDT + WDT_ + 0x40002000 + + 0 + 0x10 + registers + + + WDT_INTREQ + 10 + + + + CTRLA + Control + 0x0 + 8 + + + ENABLE + Enable + 1 + 1 + + + WEN + Watchdog Timer Window Mode Enable + 2 + 1 + + + ALWAYSON + Always-On + 7 + 1 + + + + + CONFIG + Configuration + 0x1 + 8 + 0xBB + + + PER + Time-Out Period + 0 + 4 + + PERSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xa + + + CYC16384 + 16384 clock cycles + 0xb + + + + + WINDOW + Window Mode Time-Out Period + 4 + 4 + + WINDOWSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xa + + + CYC16384 + 16384 clock cycles + 0xb + + + + + + + EWCTRL + Early Warning Interrupt Control + 0x2 + 8 + 0x0B + + + EWOFFSET + Early Warning Interrupt Time Offset + 0 + 4 + + EWOFFSETSelect + + CYC8 + 8 clock cycles + 0x0 + + + CYC16 + 16 clock cycles + 0x1 + + + CYC32 + 32 clock cycles + 0x2 + + + CYC64 + 64 clock cycles + 0x3 + + + CYC128 + 128 clock cycles + 0x4 + + + CYC256 + 256 clock cycles + 0x5 + + + CYC512 + 512 clock cycles + 0x6 + + + CYC1024 + 1024 clock cycles + 0x7 + + + CYC2048 + 2048 clock cycles + 0x8 + + + CYC4096 + 4096 clock cycles + 0x9 + + + CYC8192 + 8192 clock cycles + 0xa + + + CYC16384 + 16384 clock cycles + 0xb + + + + + + + INTENCLR + Interrupt Enable Clear + 0x4 + 8 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTENSET + Interrupt Enable Set + 0x5 + 8 + + + EW + Early Warning Interrupt Enable + 0 + 1 + + + + + INTFLAG + Interrupt Flag Status and Clear + 0x6 + 8 + + + EW + Early Warning + 0 + 1 + + + + + SYNCBUSY + Synchronization Busy + 0x8 + 32 + read-only + + + ENABLE + Enable Synchronization Busy + 1 + 1 + read-only + + + WEN + Window Enable Synchronization Busy + 2 + 1 + read-only + + + ALWAYSON + Always-On Synchronization Busy + 3 + 1 + read-only + + + CLEAR + Clear Synchronization Busy + 4 + 1 + read-only + + + + + CLEAR + Clear + 0xC + 8 + write-only + + + CLEAR + Watchdog Clear + 0 + 8 + write-only + + CLEARSelect + + KEY + Clear Key + 0xa5 + + + + + + + + + diff --git a/platform.json b/platform.json index 4fa22a4..4165075 100644 --- a/platform.json +++ b/platform.json @@ -40,7 +40,7 @@ "framework-arduinosam": { "type": "framework", "optional": true, - "version": "~2.10618.1" + "version": "~3.10618.0" }, "framework-mbed": { "type": "framework", diff --git a/platform.py b/platform.py index cc2506b..b66b69f 100644 --- a/platform.py +++ b/platform.py @@ -19,10 +19,9 @@ class AtmelsamPlatform(PlatformBase): def configure_default_packages(self, variables, targets): if variables.get("board"): + board = self.board_config(variables.get("board")) upload_protocol = variables.get("upload_protocol", - self.board_config( - variables.get("board")).get( - "upload.protocol", "")) + board.get("upload.protocol", "")) upload_tool = "tool-openocd" if upload_protocol == "sam-ba": upload_tool = "tool-bossac" @@ -39,6 +38,8 @@ def configure_default_packages(self, variables, targets): if "mbed" in variables.get("pioframework", []): self.packages["toolchain-gccarmnoneeabi"][ 'version'] = ">=1.60301.0" + if board.get("build.core", "") == "adafruit": + self.packages["tool-bossac"]['version'] = "~1.10900.0" return PlatformBase.configure_default_packages(self, variables, targets) @@ -80,9 +81,9 @@ def _add_default_debug_tools(self, board): "-c", "set CHIPNAME %s; set ENDIAN little" % openocd_chipname, "-f", - "target/%s.cfg" % - ("at91sam3ax_8x" - if "at91sam3" in openocd_chipname else "at91samdXX") + "target/%s.cfg" % ("at91sam3ax_8x" + if "at91sam3" in openocd_chipname else + "at91samdXX") ] debug['tools'][link] = { "server": { From 0380b80fe4e363379a1dbabac02d90e7d1a4981a Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Tue, 10 Jul 2018 22:12:47 +0300 Subject: [PATCH 2/3] Disable Cross Reference Table --- builder/main.py | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/builder/main.py b/builder/main.py index daad650..fadb428 100644 --- a/builder/main.py +++ b/builder/main.py @@ -96,7 +96,7 @@ def BeforeUpload(target, source, env): # pylint: disable=W0613,W0621 "-Os", "-mthumb", "-mcpu=%s" % board.get("build.cpu"), - "-Wl,--cref", + # "-Wl,--cref", # don't enable it, it prints Cross Reference Table "-Wl,--gc-sections", "-Wl,--check-sections", "-Wl,--unresolved-symbols=report-all", From b8255e1e2c7fb782d0b0b2a23115f8ab7c102a91 Mon Sep 17 00:00:00 2001 From: Ivan Kravets Date: Mon, 16 Jul 2018 17:19:42 +0300 Subject: [PATCH 3/3] Bump version to 3.2.0 --- platform.json | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/platform.json b/platform.json index 4165075..abcdac1 100644 --- a/platform.json +++ b/platform.json @@ -12,7 +12,7 @@ "type": "git", "url": "https://github.com/platformio/platform-atmelsam.git" }, - "version": "3.1.2", + "version": "3.2.0", "packageRepositories": [ "https://dl.bintray.com/platformio/dl-packages/manifest.json", "http://dl.platformio.org/packages/manifest.json",