From f2b7fc3deba218d1519efe170a946ae188d658d1 Mon Sep 17 00:00:00 2001
From: Fangfei Yang <yangff1@gmail.com>
Date: Sat, 24 Jul 2021 04:34:09 -0500
Subject: [PATCH] padding to 32

---
 script/reglib.py | 8 ++++++++
 1 file changed, 8 insertions(+)

diff --git a/script/reglib.py b/script/reglib.py
index 05a4fe7..7db82d2 100755
--- a/script/reglib.py
+++ b/script/reglib.py
@@ -97,6 +97,8 @@ def genHeader(self):
                     padId = padId + 1
                 s.extend(ident(i.genHeader(), 2, '\t'))
                 currentBit = i.msb + 1
+            if currentBit != 32:
+                s.append(f'\t\tuint32_t pad{padId} : {32 - currentBit};')
 
             s.extend([
                 "\t};",
@@ -290,6 +292,12 @@ def FieldBit(name, bit, len=1):
         context.r.addField(name, (~(((2**len)-1)<<bit) & 0xFFFFFFFF))
     else:
         print("You are not in any register")
+
+def FieldRename(lsb, name):
+    if context.r:
+        for f in context.r.fields:
+            if f.lsb == lsb:
+                f.name = name
         
 def HasField(addr):
     if context.r: