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Miscompilation of trivial loop after NodePushOut and NodePullIn #586
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@phate Just a heads up, this bug is possibly a bit gnarly. I was curious and had a look at the RVSDG, and it might look like it is not the I'm not 100% certain, as I might have mixed up some boolean values in my head, but it appears as if a trivial delta in the RVSDG was turned into a select with the parameters in the wrong order or something. |
I can reproduce it. |
1. Cleans up the basic block conversion in the LLVM backend 2. Assigns name "bb[0...]" to the basic block in the output This PR is required for #586 in order to better follow the output. It is also part of the effort in #529. Example output: ``` ; Function Attrs: noinline nounwind optnone uwtable define i64 @fac(i64 noundef %0) #0 { bb0: %1 = alloca i64, align 8 %2 = alloca i64, align 8 store i64 %0, ptr %2, align 8 store i64 1, ptr %1, align 8 br label %bb1 bb1: ; preds = %bb4, %bb0 %3 = load i64, ptr %1, align 8 %4 = load i64, ptr %2, align 8 %5 = icmp ugt i64 %4, 1 br i1 %5, label %bb3, label %bb2 bb2: ; preds = %bb1 br label %bb4 bb3: ; preds = %bb1 %6 = mul i64 %3, %4 store i64 %6, ptr %1, align 8 %7 = load i64, ptr %2, align 8 %8 = add i64 %7, -1 store i64 %8, ptr %2, align 8 br label %bb4 bb4: ; preds = %bb3, %bb2 %9 = phi i1 [ false, %bb2 ], [ true, %bb3 ] br i1 %9, label %bb1, label %bb5 bb5: ; preds = %bb4 %10 = load i64, ptr %1, align 8 ret i64 %10 } ```
The node pullin optimization only seems to be the trigger, but not the culprit. When I comment out the |
1. Moves all the gamma tests of the RVSDG to CFG pass into a single file 2. Cleans them up a bit 3. Fix indentation of test files in Makefile This is part of the fix for #586.
The ascii output for the control flow graph is not easily readable. This is the first PR on improving it. It does the following: 1. Moves the functions for converting a CFG to ascii to the cfg class 2. Adds a unit test for the conversion of three address codes In order to add a unit test for the CFG conversion, I first need to make the output more deterministic. This will happen in a follow up PR. This PR is part of issue #586
The PR does the following: 1. Ensure that CFG arguments are labeled after RVSDG to CFG conversion 2. Give readable labels to CFG nodes 3. Add missing newline after CFG printing This PR is part of issue #586
Given the following code
there is a miscompilation causing an infinite loop when compiled like so:
The issue persists if breaking the for-loop into a while-loop.
The issue only appears when invoking
NodePushOut
andNodePullIn
in two separatejlm-opt
commands.Removing any one of these passes causes the issue to disappear.
Compiling
main-mem2reg-jlmopt.ll
works, so the issue seams to appear inNodePullIn
.The
mem2reg
is also needed for the issue to appear. For reference, this is the content ofmain-mem2reg.ll
:Here is the
main
function frommain-mem2reg-jlmopt.ll
:And here is the
main
function frommain-mem2reg-jlmopt-twice.ll
(this is the one that never terminates):The text was updated successfully, but these errors were encountered: