From 26ce1ca6a675f96d725b550e408ca3da1d0bf9af Mon Sep 17 00:00:00 2001 From: =?UTF-8?q?Micha=C5=82=20=C5=BBygowski?= Date: Mon, 4 Oct 2021 15:00:37 +0200 Subject: [PATCH] src/northbridge/amd/pi/00730F01/northbridge.c: implement CC6 errata MIME-Version: 1.0 Content-Type: text/plain; charset=UTF-8 Content-Transfer-Encoding: 8bit Signed-off-by: Michał Żygowski --- src/northbridge/amd/pi/00730F01/northbridge.c | 14 ++++++++++++++ 1 file changed, 14 insertions(+) diff --git a/src/northbridge/amd/pi/00730F01/northbridge.c b/src/northbridge/amd/pi/00730F01/northbridge.c index b8ef6722bba..a783796c17e 100644 --- a/src/northbridge/amd/pi/00730F01/northbridge.c +++ b/src/northbridge/amd/pi/00730F01/northbridge.c @@ -759,6 +759,7 @@ static void fam16_finalize(void *chip_info) { struct device *dev; u32 value; + msr_t msr; dev = pcidev_on_root(0, 0); /* clear IoapicSbFeatureEn */ pci_write_config32(dev, 0xF8, 0); pci_write_config32(dev, 0xFC, 5); /* TODO: move it to dsdt.asl */ @@ -799,6 +800,19 @@ static void fam16_finalize(void *chip_info) value &= ~(1 << 11); pci_write_config32(dev, 0x60, value); } + + msr.lo = 5; + msr.hi = 0; + wrmsr(OSVW_ID_Length, msr); + + /* Errata: DRAM Scrubbing May Overwrite CC6 CoreSaveStateData, check if CC6 enabled */ + if (pci_read_config32(__f2_dev[0], 0x118) & (1 << 18)) { + dev = pcidev_on_root(0x18, 3); + /* Disable sequential DRAM scrubbing */ + pci_write_config8(dev, 0x58, pci_read_config8(dev, 0x58) & 0xF0); + /* Disable re-direct DRAM scrubbing */ + pci_write_config8(dev, 0x5C, pci_read_config8(dev, 0x5C) & 0xFE); + } } struct chip_operations northbridge_amd_pi_00730F01_ops = {