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Add I/O interface #1

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pbing opened this issue Apr 18, 2021 · 0 comments

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pbing commented Apr 18, 2021 •

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Original J1 (Verilog) I/O interface has

io_addr[15:0]
io_din[15:0]
io_dout[15:0]
io_rd
io_we

For the J1_BSV a ClientServer interface between CPU and I/O can be considered. Since the J1 is a single-cycle processor, this may not be feasible.

pbing added the enhancement label

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