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Bender.yml
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package:
name: ariane
authors:
- "Florian Zaruba <[email protected]>"
- "Michael Schaffner <[email protected]>"
- "Andreas Kuster <[email protected]>"
# WT_DCACHE
export_include_dirs:
- common/submodules/common_cells/include/
sources:
- defines:
WT_DCACHE: 1
files:
# Packages
- core/include/riscv_pkg.sv
- corev_apu/riscv-dbg/src/dm_pkg.sv
- core/include/ariane_pkg.sv
- core/include/std_cache_pkg.sv
- core/include/wt_cache_pkg.sv
- corev_apu/axi/src/axi_pkg.sv
- corev_apu/register_interface/src/reg_intf.sv
- corev_apu/register_interface/src/reg_intf_pkg.sv
- core/include/axi_intf.sv
- corev_apu/tb/ariane_soc_pkg.sv
- corev_apu/tb/ariane_axi_soc_pkg.sv
- core/include/ariane_axi_pkg.sv
- core/fpu/src/fpnew_pkg.sv
- core/fpu/src/fpu_div_sqrt_mvp/hdl/defs_div_sqrt_mvp.sv
# Stand-alone source files
- core/ariane.sv
- core/serdiv.sv
- core/ariane_regfile_ff.sv
- core/amo_buffer.sv
- core/id_stage.sv
- core/branch_unit.sv
- core/instr_realign.sv
- core/load_store_unit.sv
- core/controller.sv
- core/issue_stage.sv
- core/re_name.sv
- core/csr_buffer.sv
- core/mmu_sv32/cva6_tlb_sv32.sv
- core/mmu_sv39/tlb.sv
- core/decoder.sv
- core/scoreboard.sv
- core/perf_counters.sv
- core/store_unit.sv
- core/axi_adapter.sv
- core/fpu_wrap.sv
- core/csr_regfile.sv
- core/commit_stage.sv
- core/alu.sv
- core/multiplier.sv
- core/store_buffer.sv
- core/compressed_decoder.sv
- core/axi_shim.sv
- core/ex_stage.sv
- core/mmu_sv39/mmu.sv
- core/mmu_sv39/ptw.sv
- core/mult.sv
- core/mmu_sv32/cva6_mmu_sv32.sv
- core/mmu_sv32/cva6_ptw_sv32.sv
- core/load_unit.sv
- core/issue_read_operands.sv
- core/pmp/src/pmp_entry.sv
- core/pmp/src/pmp.sv
- core/fpu/src/fpnew_fma.sv
- core/fpu/src/fpnew_opgroup_fmt_slice.sv
- core/fpu/src/fpnew_divsqrt_multi.sv
- core/fpu/src/fpnew_fma_multi.sv
- core/fpu/src/fpnew_opgroup_multifmt_slice.sv
- core/fpu/src/fpnew_classifier.sv
- core/fpu/src/fpnew_noncomp.sv
- core/fpu/src/fpnew_cast_multi.sv
- core/fpu/src/fpnew_opgroup_block.sv
- core/fpu/src/fpnew_rounding.sv
- core/fpu/src/fpnew_top.sv
- core/fpu/src/fpu_div_sqrt_mvp/hdl/iteration_div_sqrt_mvp.sv
- core/fpu/src/fpu_div_sqrt_mvp/hdl/nrbd_nrsc_mvp.sv
- core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_top_mvp.sv
- core/fpu/src/fpu_div_sqrt_mvp/hdl/preprocess_mvp.sv
- core/fpu/src/fpu_div_sqrt_mvp/hdl/control_mvp.sv
- core/fpu/src/fpu_div_sqrt_mvp/hdl/norm_div_sqrt_mvp.sv
- core/fpu/src/fpu_div_sqrt_mvp/hdl/div_sqrt_mvp_wrapper.sv
- core/frontend/frontend.sv
- core/frontend/instr_scan.sv
- core/frontend/instr_queue.sv
- core/frontend/bht.sv
- core/frontend/btb.sv
- core/frontend/ras.sv
- core/cache_subsystem/tag_cmp.sv
- core/cache_subsystem/cache_ctrl.sv
- core/cache_subsystem/amo_alu.sv
- core/cache_subsystem/wt_axi_adapter.sv
- core/cache_subsystem/wt_dcache_ctrl.sv
- core/cache_subsystem/wt_cache_subsystem.sv
- core/cache_subsystem/wt_dcache_missunit.sv
- core/cache_subsystem/cva6_icache.sv
- core/cache_subsystem/wt_dcache_wbuffer.sv
- core/cache_subsystem/wt_l15_adapter.sv
- core/cache_subsystem/wt_dcache_mem.sv
- core/cache_subsystem/cva6_icache_axi_wrapper.sv
- core/cache_subsystem/std_cache_subsystem.sv
- core/cache_subsystem/wt_dcache.sv
- corev_apu/clint/axi_lite_interface.sv
- corev_apu/clint/clint.sv
- corev_apu/fpga/src/axi2apb/src/axi2apb_wrap.sv
- corev_apu/fpga/src/axi2apb/src/axi2apb.sv
- corev_apu/fpga/src/axi2apb/src/axi2apb_64_32.sv
- corev_apu/fpga/src/axi_slice/src/axi_w_buffer.sv
- corev_apu/fpga/src/axi_slice/src/axi_b_buffer.sv
- corev_apu/fpga/src/axi_slice/src/axi_slice_wrap.sv
- corev_apu/fpga/src/axi_slice/src/axi_slice.sv
- corev_apu/fpga/src/axi_slice/src/axi_single_slice.sv
- corev_apu/fpga/src/axi_slice/src/axi_ar_buffer.sv
- corev_apu/fpga/src/axi_slice/src/axi_r_buffer.sv
- corev_apu/fpga/src/axi_slice/src/axi_aw_buffer.sv
- corev_apu/fpga/src/apb_timer/apb_timer.sv
- corev_apu/fpga/src/apb_timer/timer.sv
- corev_apu/axi_node/src/axi_regs_top.sv
- corev_apu/axi_node/src/axi_BR_allocator.sv
- corev_apu/axi_node/src/axi_BW_allocator.sv
- corev_apu/axi_node/src/axi_address_decoder_BR.sv
- corev_apu/axi_node/src/axi_DW_allocator.sv
- corev_apu/axi_node/src/axi_address_decoder_BW.sv
- corev_apu/axi_node/src/axi_address_decoder_DW.sv
- corev_apu/axi_node/src/axi_node_arbiter.sv
- corev_apu/axi_node/src/axi_response_block.sv
- corev_apu/axi_node/src/axi_request_block.sv
- corev_apu/axi_node/src/axi_AR_allocator.sv
- corev_apu/axi_node/src/axi_AW_allocator.sv
- corev_apu/axi_node/src/axi_address_decoder_AR.sv
- corev_apu/axi_node/src/axi_address_decoder_AW.sv
- corev_apu/axi_node/src/apb_regs_top.sv
- corev_apu/axi_node/src/axi_node_intf_wrap.sv
- corev_apu/axi_node/src/axi_node.sv
- corev_apu/axi_node/src/axi_node_wrap_with_slices.sv
- corev_apu/axi_node/src/axi_multiplexer.sv
- corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos.sv
- corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics.sv
- corev_apu/src/axi_riscv_atomics/src/axi_res_tbl.sv
- corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc_wrap.sv
- corev_apu/src/axi_riscv_atomics/src/axi_riscv_amos_alu.sv
- corev_apu/src/axi_riscv_atomics/src/axi_riscv_lrsc.sv
- corev_apu/src/axi_riscv_atomics/src/axi_riscv_atomics_wrap.sv
- corev_apu/axi_mem_if/src/axi2mem.sv
- corev_apu/rv_plic/rtl/rv_plic_target.sv
- corev_apu/rv_plic/rtl/rv_plic_gateway.sv
- corev_apu/rv_plic/rtl/plic_regmap.sv
- corev_apu/rv_plic/rtl/plic_top.sv
- corev_apu/riscv-dbg/src/dmi_cdc.sv
- corev_apu/riscv-dbg/src/dmi_jtag.sv
- corev_apu/riscv-dbg/src/dmi_jtag_tap.sv
- corev_apu/riscv-dbg/src/dm_csrs.sv
- corev_apu/riscv-dbg/src/dm_mem.sv
- corev_apu/riscv-dbg/src/dm_sba.sv
- corev_apu/riscv-dbg/src/dm_top.sv
- corev_apu/riscv-dbg/debug_rom/debug_rom.sv
- corev_apu/register_interface/src/apb_to_reg.sv
- corev_apu/axi/src/axi_multicut.sv
- common/submodules/common_cells/src/deprecated/generic_fifo.sv
- common/submodules/common_cells/src/deprecated/pulp_sync.sv
- common/submodules/common_cells/src/deprecated/find_first_one.sv
- common/submodules/common_cells/src/rstgen_bypass.sv
- common/submodules/common_cells/src/rstgen.sv
- common/submodules/common_cells/src/stream_mux.sv
- common/submodules/common_cells/src/stream_demux.sv
- common/submodules/common_cells/src/stream_arbiter.sv
- common/submodules/common_cells/src/stream_arbiter_flushable.sv
- common/local/util/axi_master_connect.sv
- common/local/util/axi_slave_connect.sv
- common/local/util/axi_master_connect_rev.sv
- common/local/util/axi_slave_connect_rev.sv
- corev_apu/axi/src/axi_cut.sv
- corev_apu/axi/src/axi_join.sv
- corev_apu/axi/src/axi_delayer.sv
- corev_apu/axi/src/axi_to_axi_lite.sv
- corev_apu/fpga-support/rtl/SyncSpRamBeNx64.sv
- common/submodules/common_cells/src/sync.sv
- common/submodules/common_cells/src/popcount.sv
- common/submodules/common_cells/src/unread.sv
- common/submodules/common_cells/src/cdc_2phase.sv
- common/submodules/common_cells/src/spill_register.sv
- common/submodules/common_cells/src/edge_detect.sv
- common/submodules/common_cells/src/fifo_v3.sv
- common/submodules/common_cells/src/deprecated/fifo_v2.sv
- common/submodules/common_cells/src/deprecated/fifo_v1.sv
- common/submodules/common_cells/src/lzc.sv
- common/submodules/common_cells/src/rr_arb_tree.sv
- common/submodules/common_cells/src/deprecated/rrarbiter.sv
- common/submodules/common_cells/src/stream_delay.sv
- common/submodules/common_cells/src/lfsr.sv
- common/submodules/common_cells/src/lfsr_8bit.sv
- common/submodules/common_cells/src/lfsr_16bit.sv
- common/submodules/common_cells/src/counter.sv
- common/submodules/common_cells/src/shift_reg.sv
- common/submodules/common_cells/src/exp_backoff.sv
- corev_apu/src/tech_cells_generic/src/cluster_clock_inverter.sv
- corev_apu/src/tech_cells_generic/src/pulp_clock_mux2.sv
- target: not(cv32a6)
files:
- core/include/cv64a6_imafdc_sv39_config_pkg.sv
- target: cv32a6
files:
- core/include/cv32a6_imac_sv0_config_pkg.sv
- target: test
files:
- corev_apu/tb/ariane_soc_pkg.sv
- corev_apu/tb/ariane_axi_soc_pkg.sv
- corev_apu/tb/ariane_testharness.sv
- corev_apu/tb/ariane_peripherals.sv
- corev_apu/tb/common/uart.sv
- corev_apu/tb/common/SimDTM.sv
- corev_apu/tb/common/SimJTAG.sv
- corev_apu/bootrom/bootrom.sv
- corev_apu/tb/common/mock_uart.sv
- common/local/util/sram.sv
- target: not(synthesis)
files:
- common/local/util/instr_tracer.sv
- common/local/util/instr_tracer_if.sv
- common/local/util/instr_trace_item.svh
- common/local/util/ex_trace_item.svh
- target: all(fpga, xilinx)
files:
- corev_apu/fpga/src/ariane_peripherals_xilinx.sv
- corev_apu/fpga/src/ariane_xilinx.sv
- corev_apu/fpga/src/fan_ctrl.sv
- corev_apu/fpga/src/bootrom/bootrom.sv
- corev_apu/fpga/src/ariane-ethernet/ssio_ddr_in.sv
- corev_apu/fpga/src/ariane-ethernet/rgmii_soc.sv
- corev_apu/fpga/src/ariane-ethernet/axis_gmii_rx.sv
- corev_apu/fpga/src/ariane-ethernet/oddr.sv
- corev_apu/fpga/src/ariane-ethernet/axis_gmii_tx.sv
- corev_apu/fpga/src/ariane-ethernet/dualmem_widen8.sv
- corev_apu/fpga/src/ariane-ethernet/rgmii_phy_if.sv
- corev_apu/fpga/src/ariane-ethernet/dualmem_widen.sv
- corev_apu/fpga/src/ariane-ethernet/rgmii_lfsr.sv
- corev_apu/fpga/src/ariane-ethernet/rgmii_core.sv
- corev_apu/fpga/src/ariane-ethernet/eth_mac_1g.sv
- corev_apu/fpga/src/ariane-ethernet/eth_mac_1g_rgmii.sv
- corev_apu/fpga/src/ariane-ethernet/eth_mac_1g_rgmii_fifo.sv
- corev_apu/fpga/src/ariane-ethernet/iddr.sv
- corev_apu/fpga/src/ariane-ethernet/framing_top.sv
- corev_apu/fpga/src/apb_uart/src/apb_uart.vhd
- corev_apu/fpga/src/apb_uart/src/uart_transmitter.vhd
- corev_apu/fpga/src/apb_uart/src/uart_interrupt.vhd
- corev_apu/fpga/src/apb_uart/src/slib_mv_filter.vhd
- corev_apu/fpga/src/apb_uart/src/slib_input_filter.vhd
- corev_apu/fpga/src/apb_uart/src/slib_counter.vhd
- corev_apu/fpga/src/apb_uart/src/uart_receiver.vhd
- corev_apu/fpga/src/apb_uart/src/slib_input_sync.vhd
- corev_apu/fpga/src/apb_uart/src/slib_edge_detect.vhd
- corev_apu/fpga/src/apb_uart/src/slib_clock_div.vhd
- corev_apu/fpga/src/apb_uart/src/slib_fifo.vhd
- corev_apu/fpga/src/apb_uart/src/uart_baudgen.vhd