AST (Abstract Syntax Tree) from OpenVAF

[EktaBhaskar]

Is there a way to get the AST (Abstract Syntax Tree) out of Lexer->Preprocessor -> Parser modules? I'm new in rust, can't figure out how output of 1 module is stored and passed to another.

[pascalkuthe]

The interface that is exposed by the various frontend crates is the compilation database. The AST for a single Verilog-A file is exposed by BasedDB::parse (in the basedb crate). However, I doubt you will find the AST very useful as its just a very thin wrapper around the raw syntax tree generated by the parser.

OpenVAF builds multiple data structures (collectively called HIR) on top of the AST to extract semantic information (what declaration an identifier resolves to, what types something has etc). This happens in the hir_def and hir_ty crates. The HIR contains significantly more semantic information than the AST but it doesn't contain the information/code needed by circuit simulator. That information/code is generated in the backend (osdi, sim_back, mir, mir_opt, mir_autodiff, hir_lower) and use their own SSA based IR (called MIR).

If you provide me with more information about what you are trying to accomplish I can give you a more detailed answer.

[EktaBhaskar]

Thankyou @pascalkuthe . Really appreciate your help.

So given a bsimcmg.va file to the code, I'm trying to get a decision-tree kind of structure of the whole equation(it can be in .json format or some file that I can extrapolate using python). I was able to see code files in basedb and other crates and I ran openvaf with input file "bsimcmg.va" and was able to get "bsimcmg.osdi" file as well.

But I want to get intermediate files like after Ast, parser, Lexer, etc. How and where are the result files being stored in each crate? Is there any main file in "openvaf" module that I can debug and follow the path to see the flow?

In short, I want every intermediate step file before simulation starts.

[pascalkuthe]

In short, I want every intermediate step file before the simulation starts.

Hmm perhaps there is a misunderstanding. There are no files that OpenVAF produces as an intermediate step. OpenVAF keeps all data structures in memory. Serializing to disk is very inefficient. OpenVAf also uses a modern query-driven architecture which means there often aren't any "monolithic" data structures (like typical in pass-based compilers) that could be dumped to a file.

a decision-tree kind of structure of the whole equation

I am not quite sure what you mean by that. Decision trees as they are used in machine learning are not used in compilers. An AST is just a structured representation of the source code but that is usually not very useful for reasoning about the behavior of the model. OpenVAF mostly uses an SSA based IR for analyzing sourcecode (and expanding Verilog-A operators). The instructions in the IR are arranged in a Control Flow Graph. This is sort of similar to a decision tree but much more complex (and notably not a tree but a directed graph). There isn't also really a single "equation" since a model has many equations which are solved by the simulator at the same time.

OpenVAF has some debug machinery to print this internal IR but it's only intended for debugging and not for processing in a different programming language. There is no way to print the IR without changing the source code right now (since it's only intended for internal development). SSA-based IR is quite complex and will not be useful to you without all the additional infrastructure in OpenVAF.

If you just want to execute parts of the model (or specific equations) from Python you can use VerilogAE for that. You can find the documentation here. The docs are slightly outdated and will be updated and moved to the normal website soon. You can install VerilogAE (currently only on linux) with pip install verilogae (follow the instructions for version 0.9+). More detailed examples can be found here although please note that these still refer to the old VerilogAE Verison (0.8) instead of the new 1.0 version so every time you seen import diode, import hl2 simply use import veriogae and veriloge.load("<VA-FILE>") instead as shown in the 0.9+ introduction.

before simulation starts.

OpenVAF itself never performs any circuit simulators. The OSDI file just contains executable code as a shared library that conforms to the OSDI interface. This also offers access to the full model equations (as solved by the simulator). OSDI is documented here.

[EktaBhaskar]

Thankyou so much @pascalkuthe

Is there a way I can get the osdi library in python? Or any way to use this library in code instead of simulator tools like "ngspice"?

[pascalkuthe]

The osdi library is just a shared object file (same as .so Linux or .dll on windows). You can load those with cffi but I an not sure how well that would work. Alternatively you could write a python native extension in C which loads the OSDI file and exposes a more convenient interface to python.

The PDF document I linkes is aimed at simulators but all the documentation there should still be useful. Specifically you want to (simplified):

• allocate a model object
• allocate an instance object
• write model parameters into the model with access
• call setup_model and setup_instance
• call eval (you need to pass all internal voltages here)

Afterwards you can access the result of all Kirchoff equations (and the corresponding Jacobian).

If something like this is what you need (call a function from python and a get a value without running a circuit simulation) then VeriligAE is likely a better fit. I build VeriligAE specifically to make working with Verilog-A from python easy (for parameter extraftion). If what VerilogAE currently offers doesn't work for you I could look intk expanding it's capabilities.

[EktaBhaskar]

Thankyou @pascalkuthe . I'll try as mentioned above and reach out to you again in case I need more help.

Really appreciate your quick responses.