From f0363cf3df81766f27cf9ce78ef2a530dcf496d7 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 13 May 2024 14:42:34 +0800 Subject: [PATCH 1/2] Update correct testname Signed-off-by: dd-baoshan --- .../corev-dv/corev_rand_pulp_hwloop_exception/corev-dv.yaml | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-) diff --git a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_exception/corev-dv.yaml b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_exception/corev-dv.yaml index f6d5c6c52b..0c0f24c93c 100644 --- a/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_exception/corev-dv.yaml +++ b/cv32e40p/tests/programs/corev-dv/corev_rand_pulp_hwloop_exception/corev-dv.yaml @@ -3,7 +3,7 @@ # Test definition YAML for corev-dv test generator # corev-dv generator test -name: corev_rand_pulp_hwloop_test +name: corev_rand_pulp_hwloop_exception uvm_test: $(CV_CORE_LC)_instr_base_test description: > RISCV-DV generated random hwloop test From 328d8e98bc08302268b7862c457065e61cfd7d44 Mon Sep 17 00:00:00 2001 From: dd-baoshan Date: Mon, 13 May 2024 14:43:26 +0800 Subject: [PATCH 2/2] Update behavioral logic on collecting clk_cycle_window for fpu Signed-off-by: dd-baoshan --- cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv | 36 +++++++++++++++--------- 1 file changed, 23 insertions(+), 13 deletions(-) diff --git a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv index 0e88f94ed3..5a517e3788 100644 --- a/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv +++ b/cv32e40p/tb/uvmt/uvmt_cv32e40p_tb_ifs.sv @@ -541,6 +541,7 @@ interface uvmt_cv32e40p_cov_if `else parameter int FPU_LAT_1_CYC = 0; `endif + parameter int MAX_FP_XACT_CYCLE = 19; logic [4:0] clk_cycle_window; logic [5:0] curr_fpu_apu_op_if; @@ -598,25 +599,34 @@ interface uvmt_cv32e40p_cov_if // bhv_logic_1 // calculate each APU operation's current clock cycle number during execution for functional coverage use // input(s): apu_op, + bit detect_apu_rvalid = 1; always @(posedge clk_i or negedge rst_ni) begin - if(!rst_ni) begin - clk_cycle_window = 0; - curr_fpu_apu_op_if = 0; + if (!rst_ni) begin + clk_cycle_window = 0; + curr_fpu_apu_op_if = 0; + detect_apu_rvalid = 1; end else begin - if((clk_cycle_window == 0) && (apu_req == 1)) begin - clk_cycle_window = 1; - curr_fpu_apu_op_if = apu_op; + assert (clk_cycle_window <= MAX_FP_XACT_CYCLE); + if (apu_req && apu_gnt && apu_rvalid_i && detect_apu_rvalid) begin : IS_0_CYC_FPU + clk_cycle_window = 0; + detect_apu_rvalid = 0; + curr_fpu_apu_op_if = apu_op; end - else if((clk_cycle_window != 0) && (apu_req == 1)) begin - clk_cycle_window = 1; - curr_fpu_apu_op_if = apu_op; + else if (apu_req && apu_gnt && !apu_rvalid_i && detect_apu_rvalid) begin : NOT_0_CYC_FPU + clk_cycle_window = 1; + detect_apu_rvalid = 0; + curr_fpu_apu_op_if = apu_op; end - else if((clk_cycle_window != 0) && (apu_busy == 1)) begin - clk_cycle_window += 1; + else if (apu_busy && !apu_rvalid_i && !detect_apu_rvalid) begin : FPU_MULT_CYC + // fpu write delay should not increase the cyc cnt + clk_cycle_window += 1; end - else begin - clk_cycle_window = 0; + else if (apu_busy && apu_rvalid_i && !detect_apu_rvalid) begin : DONE_FPU_CYCLE + detect_apu_rvalid = 1; + end + else if (!apu_busy) begin + clk_cycle_window = 0; end end end