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cfg_corev.gpr[0], cfg_corev.gpr[0])); instr.push_back($sformatf("andi x%0d, x%0d, 0x3", cfg_corev.gpr[0], cfg_corev.gpr[0])); //Check MSTATUS.FS bit instr.push_back($sformatf("li x%0d, 0x%0x", cfg_corev.gpr[1], 3)); - instr.push_back($sformatf("bne x%0d, x%0d, 2f", cfg_corev.gpr[0], cfg_corev.gpr[1])); // MSTATUS.FS!=3 do not push + if (cfg_corev.enable_nested_interrupt) begin + // fixme: refer workaround_1 + instr.push_back($sformatf("# bne x%0d, x%0d, 2f # workaround for mstatus.FS during nested irq", cfg_corev.gpr[0], cfg_corev.gpr[1])); // MSTATUS.FS!=3 do not push + end + else begin + instr.push_back($sformatf("bne x%0d, x%0d, 2f", cfg_corev.gpr[0], cfg_corev.gpr[1])); // MSTATUS.FS!=3 do not push + end // Reserve space from kernel stack to save all 32 FPR + FCSR instr.push_back($sformatf("addi x%0d, x%0d, -%0d", sp, sp, 33 * (XLEN/8))); @@ -442,18 +448,31 @@ package cv32e40p_instr_test_pkg; // Pop MSTATUS.FS from kernel stack instr.push_back($sformatf("%0s x%0d, %0d(x%0d)", load_instr, cfg_corev.gpr[0], 0, sp)); + // Restore MSTATUS.FS - instr.push_back($sformatf("li x%0d, 0x%0x", cfg_corev.gpr[1], 3)); //Clear FS - instr.push_back($sformatf("slli x%0d, x%0d, 13", cfg_corev.gpr[1], cfg_corev.gpr[1])); - instr.push_back($sformatf("csrrc x0, 0x%0x, x%0d # %0s", status, cfg_corev.gpr[1], status.name())); - instr.push_back($sformatf("slli x%0d, x%0d, 13", cfg_corev.gpr[1], cfg_corev.gpr[0])); - instr.push_back($sformatf("csrrs x0, 0x%0x, x%0d # %0s", status, cfg_corev.gpr[1], status.name())); + if (cfg_corev.enable_nested_interrupt) begin + // fixme: refer workaround_1 + // do not clear FS + end + else begin + instr.push_back($sformatf("li x%0d, 0x%0x", cfg_corev.gpr[1], 3)); //Clear FS + instr.push_back($sformatf("slli x%0d, x%0d, 13", cfg_corev.gpr[1], cfg_corev.gpr[1])); + instr.push_back($sformatf("csrrc x0, 0x%0x, x%0d # %0s", status, cfg_corev.gpr[1], status.name())); + instr.push_back($sformatf("slli x%0d, x%0d, 13", cfg_corev.gpr[1], cfg_corev.gpr[0])); + instr.push_back($sformatf("csrrs x0, 0x%0x, x%0d # %0s", status, cfg_corev.gpr[1], status.name())); + end // Restore kernel stack pointer instr.push_back($sformatf("addi x%0d, x%0d, %0d", sp, sp, 1 * (XLEN/8))); instr.push_back($sformatf("li x%0d, 0x%0x", cfg_corev.gpr[1], 3)); - instr.push_back($sformatf("bne x%0d, x%0d, 2f", cfg_corev.gpr[0], cfg_corev.gpr[1])); // MSTATUS.FS!=3 do not pop FPR + if (cfg_corev.enable_nested_interrupt) begin + // fixme: refer workaround_1 + instr.push_back($sformatf("# bne x%0d, x%0d, 2f # workaround for mstatus.FS during nested irq", cfg_corev.gpr[0], cfg_corev.gpr[1])); // MSTATUS.FS!=3 do not pop FPR + end + else begin + instr.push_back($sformatf("bne x%0d, x%0d, 2f", cfg_corev.gpr[0], cfg_corev.gpr[1])); // MSTATUS.FS!=3 do not pop FPR + end randcase 1: load_instr = (FLEN == 32) ? "flw" : "fld"; @@ -478,6 +497,15 @@ package cv32e40p_instr_test_pkg; end + // fixme: the irq handling logic flow need to be rework to consider nested irq scenario for fpu csr such as FS. + // workaround_1 for MSTATUS.FS during nested irq by assuming FS always DIRTY prior irq handling. + if (cfg_corev.enable_nested_interrupt) begin + // always set FS to DIRTY prior mret + instr.push_back($sformatf("li x%0d, 0x3 # workaround for mstatus.FS during nested irq", cfg_corev.gpr[1])); + instr.push_back($sformatf("slli x%0d, x%0d, 13 # workaround for mstatus.FS during nested irq", cfg_corev.gpr[1], cfg_corev.gpr[1])); + instr.push_back($sformatf("csrrs x0, mstatus, x%0d # workaround for mstatus.FS during nested irq", cfg_corev.gpr[1])); + end + load_instr = (XLEN == 32) ? "lw" : "ld"; // Pop user mode GPRs from kernel stack for(int i = 1; i < 32; i++) begin diff --git a/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv b/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv index 52d201e79c..55d1cc6167 100644 --- a/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv +++ b/cv32e40p/env/uvme/cov/uvme_cv32e40p_zfinx_instr_covg.sv @@ -65,7 +65,7 @@ class uvme_cv32e40p_zfinx_instr_covg extends uvm_component; ignore_bins cur_fpu_wo_rs3 = !binsof(cp_cur_is_fpu_instr) intersect {`RV32ZFINX_INSTR_W_RS3}; `define IGNORE_BINS_NON_RS1_CV32E40P_INSTR \ - ignore_bins non_rs1_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL}; + ignore_bins non_rs1_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {`RV32_OPCODE_WITH_NO_RS1}; `define IGNORE_BINS_NON_RS2_CV32E40P_INSTR \ ignore_bins non_rs2_rv32_instr = binsof(cp_id_stage_non_rv32fc_inst) intersect {`RV32_OPCODE_WITH_NO_RS2}; diff --git a/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv b/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv index ccb29cce97..4f3c0736ee 100644 --- a/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv +++ b/cv32e40p/env/uvme/uvme_cv32e40p_macros.sv @@ -32,8 +32,11 @@ TB_OPCODE_OP, TB_OPCODE_OPIMM, TB_OPCODE_LOAD, TB_OPCODE_JALR, TB_OPCODE_JAL, TB_OPCODE_AUIPC, TB_OPCODE_LUI, \ OPCODE_CUSTOM_0, OPCODE_CUSTOM_1, OPCODE_CUSTOM_2, OPCODE_CUSTOM_3 +`define RV32_OPCODE_WITH_NO_RS1 \ + TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL,TB_OPCODE_FENCE + `define RV32_OPCODE_WITH_NO_RS2 \ - TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL,TB_OPCODE_JALR,TB_OPCODE_LOAD,TB_OPCODE_OPIMM,TB_OPCODE_FENCE,TB_OPCODE_SYSTEM + TB_OPCODE_LUI,TB_OPCODE_AUIPC,TB_OPCODE_JAL,TB_OPCODE_JALR,TB_OPCODE_LOAD,TB_OPCODE_OPIMM,TB_OPCODE_FENCE,TB_OPCODE_SYSTEM,OPCODE_CUSTOM_0 `define RV32F_INSTR_WITH_FS1 \ TB_INS_FMADD, TB_INS_FNMADD, TB_INS_FMSUB, TB_INS_FNMSUB, TB_INS_FADD, TB_INS_FSUB, TB_INS_FMUL, TB_INS_FDIV, TB_INS_FSQRT, \ diff --git a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml index b4b3551c12..5ecf11890b 100644 --- a/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml +++ b/cv32e40p/regress/cv32e40pv2_interrupt_debug_long.yaml @@ -21,6 +21,18 @@ builds: # List of tests tests: + corev_rand_interrupt_wfi: + build: uvmt_cv32e40p + description: corev_rand_interrupt_wfi + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi CFG_PLUSARGS="+UVM_TIMEOUT=30000000" + + corev_rand_interrupt_wfi_mem_stress: + build: uvmt_cv32e40p + description: corev_rand_interrupt_wfi_mem_stress + dir: cv32e40p/sim/uvmt + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=50000000" + corev_rand_debug: build: uvmt_cv32e40p description: corev_rand_debug @@ -69,23 +81,11 @@ tests: dir: cv32e40p/sim/uvmt cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_exception CFG_PLUSARGS="+UVM_TIMEOUT=30000000" -# corev_rand_interrupt_nested: -# build: uvmt_cv32e40p -# description: corev_rand_interrupt_nested -# dir: cv32e40p/sim/uvmt -# cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_nested CFG_PLUSARGS="+UVM_TIMEOUT=30000000" - - corev_rand_interrupt_wfi: + corev_rand_interrupt_nested: build: uvmt_cv32e40p - description: corev_rand_interrupt_wfi + description: corev_rand_interrupt_nested dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi CFG_PLUSARGS="+UVM_TIMEOUT=30000000" - - corev_rand_interrupt_wfi_mem_stress: - build: uvmt_cv32e40p - description: corev_rand_interrupt_wfi_mem_stress - dir: cv32e40p/sim/uvmt - cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_wfi_mem_stress CFG_PLUSARGS="+UVM_TIMEOUT=50000000" + cmd: make gen_corev-dv test COREV=YES TEST=corev_rand_interrupt_nested CFG_PLUSARGS="+UVM_TIMEOUT=30000000" # list of corev_rand_pulp_hwloop_debug - START diff --git a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do index 276edb5b1b..6ba7d3cb9c 100644 --- a/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do +++ b/cv32e40p/sim/tools/vsim/exclusion/cv32e40pv2_code_fpu_cfg_waiver.do @@ -30,7 +30,10 @@ coverage exclude -line 226 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t coverage exclude -line 227 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} coverage exclude -line 228 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} coverage exclude -line 229 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} -coverage exclude -line 292 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} +coverage exclude -line 287 -code c -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {Specific combination is unreachable. Proven with Formal.} +coverage exclude -line 287 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {Specific combination is unreachable. Proven with Formal.} +coverage exclude -line 288 -code s -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {Specific combination is unreachable. Proven with Formal.} +coverage exclude -feccondrow 292 4 -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {flush_i set to 1'b0} coverage exclude -line 415 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} coverage exclude -line 416 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} coverage exclude -line 424 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[1]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/genblk1/i_fpnew_divsqrt_multi_th} -comment {out_ready is stuck to 1. We never go to hold state.} @@ -377,3 +380,7 @@ coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_t coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_lzc/gen_lzc/g_levels[4]/g_not_last_level/g_level[13]} -comment {this part of leading zero counter is not used.} coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_lzc/gen_lzc/g_levels[4]/g_not_last_level/g_level[14]} -comment {this part of leading zero counter is not used.} coverage exclude -line 101 -code b -scope {/uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/fpu_gen/fp_wrapper_i/i_fpnew_bulk/gen_operation_groups[0]/i_opgroup_block/gen_merged_slice/i_multifmt_slice/gen_num_lanes[0]/active_lane/lane_instance/i_fpnew_fma_multi/i_lzc/gen_lzc/g_levels[4]/g_not_last_level/g_level[15]} -comment {this part of leading zero counter is not used.} +coverage exclude -feccondrow 211 4 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {one specific condition (row4) is unreachable. Proven with Formal. We never apu_en_1 and regfile_alu_we at the same time.} +coverage exclude -feccondrow 237 5 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {one specific condition (Row5) is unreachable. Proven with Formal.} +coverage exclude -feccondrow 241 5 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {one specific condition (Row5) is unreachable. Proven with Formal.} +coverage exclude -feccondrow 387 22 -scope /uvmt_cv32e40p_tb/dut_wrap/cv32e40p_tb_wrapper_i/cv32e40p_top_i/core_i/ex_stage_i -comment {unreachable in FPU config. It only could be hit with Z config for apu_read_dep_for_jalr.} diff --git a/cv32e40p/tests/programs/custom/debug_hwloop_test/trigger_code.S b/cv32e40p/tests/programs/custom/debug_hwloop_test/trigger_code.S index 299aad770f..e55bc5cb67 100644 --- a/cv32e40p/tests/programs/custom/debug_hwloop_test/trigger_code.S +++ b/cv32e40p/tests/programs/custom/debug_hwloop_test/trigger_code.S @@ -1,4 +1,4 @@ -#Copyright 202[x] Silicon Labs, Inc. +#Copyright (c) 2024 Dolphin Design # #This file, and derivatives thereof are licensed under the #Solderpad License, Version 2.0 (the "License"); diff --git a/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/fpu_func_cov_improve_test.S b/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/fpu_func_cov_improve_test.S index 2c9f86edc1..47d7b70875 100644 --- a/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/fpu_func_cov_improve_test.S +++ b/cv32e40p/tests/programs/custom/fpu_func_cov_improve_test/fpu_func_cov_improve_test.S @@ -1511,6 +1511,72 @@ _jrsw31:fsw f31, -8(x31) cv.lbu x31, (x1), 4 fcvt.s.wu f31, x31 + # 20 + auipc x0, 0x40000 + flw f0, 0(x0) + auipc x1, 0x40000 + flw f1, 0(x1) + auipc x2, 0x40000 + flw f2, 0(x2) + auipc x3, 0x40000 + flw f3, 0(x3) + auipc x4, 0x40000 + flw f4, 0(x4) + auipc x5, 0x40000 + flw f5, 0(x5) + auipc x6, 0x40000 + flw f6, 0(x6) + auipc x7, 0x40000 + flw f7, 0(x7) + auipc x8, 0x40000 + flw f8, 0(x8) + auipc x9, 0x40000 + flw f9, 0(x9) + auipc x10, 0x40000 + flw f10, 0(x10) + auipc x11, 0x40000 + flw f11, 0(x11) + auipc x12, 0x40000 + flw f12, 0(x12) + auipc x13, 0x40000 + flw f13, 0(x13) + auipc x14, 0x40000 + flw f14, 0(x14) + auipc x15, 0x40000 + flw f15, 0(x15) + auipc x16, 0x40000 + flw f16, 0(x16) + auipc x17, 0x40000 + flw f17, 0(x17) + auipc x18, 0x40000 + flw f18, 0(x18) + auipc x19, 0x40000 + flw f19, 0(x19) + auipc x20, 0x40000 + flw f20, 0(x20) + auipc x21, 0x40000 + flw f21, 0(x21) + auipc x22, 0x40000 + flw f22, 0(x22) + auipc x23, 0x40000 + flw f23, 0(x23) + auipc x24, 0x40000 + flw f24, 0(x24) + auipc x25, 0x40000 + flw f25, 0(x25) + auipc x26, 0x40000 + flw f26, 0(x26) + auipc x27, 0x40000 + flw f27, 0(x27) + auipc x28, 0x40000 + flw f28, 0(x28) + auipc x29, 0x40000 + flw f29, 0(x29) + auipc x30, 0x40000 + flw f30, 0(x30) + auipc x31, 0x40000 + flw f31, 0(x31) + # for uvme_cv32e40p_fp_instr_covg/cg_f_inst_reg/cr_non_rv32f_rd_rv32f_rs1 - end ######### FOR PULP_FPU CFG - END ######### diff --git a/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S index c6537d6e36..ee2efc40b1 100644 --- a/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S +++ b/cv32e40p/tests/programs/custom/zfinx_func_cov_improve_test/zfinx_func_cov_improve_test.S @@ -21,7 +21,7 @@ main: #endif ######### FOR PULP_FPU CFG - START ######### - # for uvme_cv32e40p_fp_instr_covg/cg_f_inst_reg/cr_non_rv32f_rd_rv32f_rs1 - start + # for uvme_cv32e40p_fp_instr_covg/cg_f_inst_reg/cr_non_rv32f_rd_rv32f_rs[1/2/3] - start .align 2 // 1 - jal -> fsub (rs1, rs2) @@ -3675,13 +3675,76 @@ _fsgnjx_jr31: fsgnjx.s x31, x31, x31 cv.lbu x0, (x1), 4 fcvt.wu.s x1, x0 + cv.lbu x0, (x1), 4 + fcvt.s.wu x1, x0 + cv.lbu x5, (x1), 4 + fcvt.s.wu x1, x5 + cv.lbu x0, (x1), 4 + flt.s x1, x0, x0 + cv.lbu x15, (x1), 4 + flt.s x1, x15, x15 + cv.lbu x7, (x1), 4 + fle.s x1, x7, x7 + cv.lbu x9, (x1), 4 + fdiv.s x1, x9, x9 + cv.lbu x22, (x1), 4 + fdiv.s x1, x22, x22 + cv.lbu x31, (x1), 4 + fdiv.s x1, x31, x31 + cv.lbu x17, (x1), 4 + fnmsub.s x1, x17, x17, x17 + cv.lbu x18, (x1), 4 + fnmsub.s x1, x18, x18, x18 + cv.lbu x24, (x1), 4 + fmadd.s x1, x24, x24, x24 + cv.lbu x29, (x1), 4 + fmadd.s x1, x29, x29, x29 + cv.lbu x27, (x1), 4 + feq.s x1, x27, x27 + cv.lbu x5, (x1), 4 + fnmadd.s x1, x5, x5, x5 + cv.lbu x13, (x1), 4 + fnmadd.s x1, x13, x13, x13 + cv.lbu x15, (x1), 4 + fnmadd.s x1, x15, x15, x15 + cv.lbu x25, (x1), 4 + fnmadd.s x1, x25, x25, x25 + cv.lbu x29, (x1), 4 + fnmadd.s x1, x29, x29, x29 + cv.lbu x7, (x1), 4 + fsgnjn.s x1, x0, x0 + cv.lbu x21, (x1), 4 + fdiv.s x1, x21, x21 + cv.lbu x23, (x1), 4 + feq.s x1, x23, x23 + cv.lbu x25, (x1), 4 + fnmsub.s x1, x25, x25, x25 + cv.lbu x14, (x1), 4 + fmadd.s x1, x14, x14, x14 + cv.lbu x21, (x1), 4 + fnmsub.s x1, x21, x21, x21 + cv.lbu x5, (x1), 4 + flt.s x1, x5, x5 + cv.lbu x7, (x1), 4 + fsgnjn.s x1, x7, x7 + cv.lbu x13, (x1), 4 + fmadd.s x1, x13, x13, x13 + cv.lbu x15, (x1), 4 + fmadd.s x1, x15, x15, x15 + // 46 - custom_1 - rd0 cv.lbu x0, (x1), x0 fnmsub.s x1, x0, x0, x0 cv.lbu x0, (x1), x0 fnmadd.s x1, x0, x0, x0 + cv.lbu x0, (x1), x0 + feq.s x1, x0, x0 + + // 47 - custom_2 - rd0 + cv.addun x19, x19, x0, 0 + fsgnjx.s x1, x19, x19 + - // 47 - // 48 - // 49 - // 50 - @@ -3692,14 +3755,173 @@ _fsgnjx_jr31: fsgnjx.s x31, x31, x31 // (rs1) refer lines 190-253 // (rs1) refer lines 256-351 - # for uvme_cv32e40p_fp_instr_covg/cg_f_inst_reg/cr_non_rv32f_rd_rv32f_rs1 - end + # for uvme_cv32e40p_fp_instr_covg/cg_f_inst_reg/cr_non_rv32f_rd_rv32f_rs[1/2/3] - end + + + # for uvme_cv32e40p_fp_instr_covg/cg_f_inst_reg/cr_rv32f_rd_non_rv32f_rs[1/2]_eq_nonzero_lat - start + + fdiv.s x0, x0, x0 + bne x0, x0, _branch_0 + fdiv.s x1, x1, x1 + bne x1, x1, _branch_0 + fdiv.s x2, x2, x2 + bne x2, x2, _branch_0 + fdiv.s x3, x3, x3 + bne x3, x3, _branch_0 + fdiv.s x4, x4, x4 + bne x4, x4, _branch_0 + fdiv.s x5, x5, x5 + bne x5, x5, _branch_0 + fdiv.s x6, x6, x6 + bne x6, x6, _branch_0 + fdiv.s x7, x7, x7 + bne x7, x7, _branch_0 + fdiv.s x8, x8, x8 + bne x8, x8, _branch_0 + fdiv.s x9, x9, x9 + bne x9, x9, _branch_0 + fdiv.s x10, x10, x10 + bne x10, x10, _branch_0 + fdiv.s x11, x11, x11 + bne x11, x11, _branch_0 + fdiv.s x12, x12, x12 + bne x12, x12, _branch_0 + fdiv.s x13, x13, x13 + bne x13, x13, _branch_0 + fdiv.s x14, x14, x14 + bne x14, x14, _branch_0 + fdiv.s x15, x15, x15 + bne x15, x15, _branch_0 + fdiv.s x16, x16, x16 + bne x16, x16, _branch_0 + fdiv.s x17, x17, x17 + bne x17, x17, _branch_0 + fdiv.s x18, x18, x18 + bne x18, x18, _branch_0 + fdiv.s x19, x19, x19 + bne x19, x19, _branch_0 + fdiv.s x20, x20, x20 + bne x20, x20, _branch_0 + fdiv.s x21, x21, x21 + bne x21, x21, _branch_0 + fdiv.s x22, x22, x22 + bne x22, x22, _branch_0 + fdiv.s x23, x23, x23 + bne x23, x23, _branch_0 + fdiv.s x24, x24, x24 + bne x24, x24, _branch_0 + fdiv.s x25, x25, x25 + bne x25, x25, _branch_0 + fdiv.s x26, x26, x26 + bne x26, x26, _branch_0 + fdiv.s x27, x27, x27 + bne x27, x27, _branch_0 + fdiv.s x28, x28, x28 + bne x28, x28, _branch_0 + fdiv.s x29, x29, x29 + bne x29, x29, _branch_0 + fdiv.s x30, x30, x30 + bne x30, x30, _branch_0 + fdiv.s x31, x31, x31 + bne x31, x31, _branch_0 + + fsqrt.s x0, x0 + bne x0, x0, _branch_0 + fsqrt.s x1, x1 + bne x1, x1, _branch_0 + fsqrt.s x2, x2 + bne x2, x2, _branch_0 + fsqrt.s x3, x3 + bne x3, x3, _branch_0 + fsqrt.s x4, x4 + bne x4, x4, _branch_0 + fsqrt.s x5, x5 + bne x5, x5, _branch_0 + fsqrt.s x6, x6 + bne x6, x6, _branch_0 + fsqrt.s x7, x7 + bne x7, x7, _branch_0 + fsqrt.s x8, x8 + bne x8, x8, _branch_0 + fsqrt.s x9, x9 + bne x9, x9, _branch_0 + fsqrt.s x10, x10 + bne x10, x10, _branch_0 + fsqrt.s x11, x11 + bne x11, x11, _branch_0 + fsqrt.s x12, x12 + bne x12, x12, _branch_0 + fsqrt.s x13, x13 + bne x13, x13, _branch_0 + fsqrt.s x14, x14 + bne x14, x14, _branch_0 + fsqrt.s x15, x15 + bne x15, x15, _branch_0 + fsqrt.s x16, x16 + bne x16, x16, _branch_0 + fsqrt.s x17, x17 + bne x17, x17, _branch_0 + fsqrt.s x18, x18 + bne x18, x18, _branch_0 + fsqrt.s x19, x19 + bne x19, x19, _branch_0 + fsqrt.s x20, x20 + bne x20, x20, _branch_0 + fsqrt.s x21, x21 + bne x21, x21, _branch_0 + fsqrt.s x22, x22 + bne x22, x22, _branch_0 + fsqrt.s x23, x23 + bne x23, x23, _branch_0 + fsqrt.s x24, x24 + bne x24, x24, _branch_0 + fsqrt.s x25, x25 + bne x25, x25, _branch_0 + fsqrt.s x26, x26 + bne x26, x26, _branch_0 + fsqrt.s x27, x27 + bne x27, x27, _branch_0 + fsqrt.s x28, x28 + bne x28, x28, _branch_0 + fsqrt.s x29, x29 + bne x29, x29, _branch_0 + fsqrt.s x30, x30 + bne x30, x30, _branch_0 + fsqrt.s x31, x31 + bne x31, x31, _branch_0 +_branch_0: + + fsqrt.s x0, x1 + sw x0, 0(x0) + +// below codes are not straight forward and for operand forward between fsqrt->jalr : start + li x2, 32871 // x2 == jalr x0, x1, 0 + and x1, x1, x0 + auipc x1, 0x0 + addi x1, x1, 18 // x1 == pc for symbol _fsqrt_jr_3 + sw x2, 0(x0) // store x2 to pc=0 + fsqrt.s x3, x0 + jalr x0, x3, 0 +_fsqrt_jr_3: + li x2, 32871 // x2 == jalr x0, x1, 0 + and x1, x1, x0 + auipc x1, 0x0 + addi x1, x1, 18 // x1 == pc for symbol _fsqrt_jr_3 + sw x2, 0(x0) // store x2 to pc=0 + fsqrt.s x16, x0 + jalr x0, x16, 0 +_fsqrt_jr_16: +// below codes are not straight forward and for operand forward between fsqrt->jalr : end + + # for uvme_cv32e40p_fp_instr_covg/cg_f_inst_reg/cr_rv32f_rd_non_rv32f_rs[1/2]_eq_nonzero_lat - end + ######### FOR PULP_FPU CFG - END ######### ######### Added for ex_stage hole coverage ######### la x1, test_end li x2, 1 fcvt.s.w x2, x2 - + fdiv.s x3, x1, x2 div x4, x5, x0 jalr x0, x3, 0