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As a use of flexus, I want a 2 level TLB hierarchy So that we can model modern CPU architectures.
Specification:
[Condition 1: Before a page walk. it should check the second level TLB (sTLB) for the given address
[Condition 2: After a page walk, it should insert the address into sTLB for future access
Tasks:
UPDATE -[22.10.2024]: implemented with dc96928 and fffaa72
The text was updated successfully, but these errors were encountered:
BugraEryilmaz
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As a use of flexus,
I want a 2 level TLB hierarchy
So that we can model modern CPU architectures.
Specification:
[Condition 1: Before a page walk. it should check the second level TLB (sTLB) for the given address
[Condition 2: After a page walk, it should insert the address into sTLB for future access
Tasks:
UPDATE
-[22.10.2024]: implemented with dc96928 and fffaa72
The text was updated successfully, but these errors were encountered: