2nd Level TLB

[BugraEryilmaz]

As a use of flexus,
I want a 2 level TLB hierarchy
So that we can model modern CPU architectures.

Specification:

1. [Condition 1: Before a page walk. it should check the second level TLB (sTLB) for the given address

   • [Detail 1] With a given delay, the cycle accurate simulator should check a second level TLB for address translation
   • [Detail 2] If the address is also not in the sTLB, then it should go for the page walk

2. [Condition 2: After a page walk, it should insert the address into sTLB for future access

Tasks:

• [Task 1: implement sTLB in flexus

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UPDATE
-[22.10.2024]: implemented with dc96928 and fffaa72