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    21 repositories

    • SigasiProjectCreator

      Public
      Python scripts that help generating custom Sigasi Project and Libary configuration files
      Python
      •
      BSD 3-Clause "New" or "Revised" License
      •11•16•4•0•Updated Feb 27, 2024Feb 27, 2024

    • Sigasi_CLI_in_CI_demo

      Public
      A demonstration of how the Sigasi CLI can be used in a CI/CD pipeline
      SystemVerilog
      •
      BSD 3-Clause "New" or "Revised" License
      •0•0•1•0•Updated Feb 14, 2024Feb 14, 2024

    • veresta-doc

      Public
      Generate Sigasi project documentation in CI
      SystemVerilog
      •0•0•0•0•Updated Dec 19, 2023Dec 19, 2023

    • sigasi_online_demo

      Public
      Demo project
      VHDL
      •
      BSD 3-Clause "New" or "Revised" License
      •0•2•0•0•Updated Aug 9, 2023Aug 9, 2023

    • sigasi_demos

      Public
      SystemVerilog
      •3•9•0•2•Updated May 26, 2023May 26, 2023

    • uvm-in-vunit-tutorial-simple-adder

      Public
      A demonstration of how to run UVM tests in VUnit
      SystemVerilog
      •87•0•0•0•Updated Jun 27, 2022Jun 27, 2022

    • sigasi_training

      Public
      Training material for Sigasi software
      VHDL
      •
      BSD 3-Clause "New" or "Revised" License
      •0•1•0•0•Updated Jan 5, 2022Jan 5, 2022

    • sigasi-tmlanguage

      Public
      provide VHDL and SV syntax highlighting
      BSD 3-Clause "New" or "Revised" License
      •0•0•0•0•Updated Dec 7, 2021Dec 7, 2021

    • sigasi_documentation_examples

      Public
      This repository contains examples of documentation that has been generated using Sigasi Studio.
      HTML
      •
      MIT License
      •0•1•0•0•Updated Jun 11, 2021Jun 11, 2021

    • opentitan

      Public
      OpenTitan: Open source silicon root of trust
      SystemVerilog
      •
      Apache License 2.0
      •804•0•0•0•Updated Dec 11, 2020Dec 11, 2020

    • vhdl2008-tester

      Public archive
      VHDL
      •0•0•0•0•Updated Nov 19, 2020Nov 19, 2020

    • sigasi-csv-build

      Public archive
      Python
      •
      BSD 4-Clause "Original" or "Old" License
      •0•0•0•0•Updated Nov 19, 2020Nov 19, 2020

    • markermanager_doc

      Public archive
      HTML
      •0•0•0•0•Updated Nov 19, 2019Nov 19, 2019

    • UVVM_All

      Public
      Open Source VHDL Verification Component Framework for making structured VHDL testbenches for verification of FPGA and ASIC.
      VHDL
      •
      MIT License
      •97•0•0•0•Updated Oct 18, 2017Oct 18, 2017

    • eclipse_custom_code_checker

      Public
      Python
      •0•0•0•0•Updated May 1, 2015May 1, 2015

    • mips_r2000

      Public
      VHDL
      •0•0•0•0•Updated Oct 19, 2014Oct 19, 2014

    • sigasi_premium_tutorial

      Public archive
      VHDL
      •0•0•0•0•Updated May 31, 2014May 31, 2014

    • sigasi_demo

      Public archive
      VHDL
      •0•0•0•0•Updated May 27, 2014May 27, 2014

    • XilinxTclStore

      Public
      Xilinx Tcl Store
      Tcl
      •190•0•0•0•Updated Apr 29, 2014Apr 29, 2014

    • com.sigasi.ultraedit.bindings

      Public
      UltraEdit key bindings scheme for Eclipse
      Eclipse Public License 1.0
      •1•0•0•0•Updated Oct 23, 2013Oct 23, 2013

    • EMF-Statistics-View

      Public
      Eclipse support for viewing the statistics of a EMF model associated with the active editor.
      Eclipse Public License 1.0
      •5•0•0•0•Updated Jul 4, 2011Jul 4, 2011