Has anyone produced state machine diagrams for open thread devices?

[mikew67]

Sure would be useful for documenting and understanding the Thread protocol if someone has produced a "finite state machine" (FSM) diagram for each of the Thread device types. Surprised that I haven't seen those anywhere. Is it because the protocol isn't "static", i.e., there are time-dependent events such as timeouts in it? I imagine these could be handled by adding timer states. Would the use of "Hierarchical State Machine" formalism be useful, e.g., to factor out common behavior between the different device types?

This need arose when thinking about tools for Thread networks. For example, a Thread message sniffer with an internal copy of the appropriate FSM would be much more useful than one without.

Comments? Suggestions? Sources?

[mikew67]

Note, since posting the above question, I have looked further for Matter-related FSM diagrams and:

• I have searched the thousand pages or so in the three official Matter 1.0 Specification PDF files and found two instances of state machine diagrams, both for a small, localized piece of the protocol.
• I suspect that composing an all-encompassing FSM diagram or collection would be a massive effort, but that just shows how useful such a tool would be.

[abtink]

In essense OT stack is a state machine but I expect it to be a rather complex FSM overall.

Just to give a sense, MLE layer uses mAttachState, mParentRequestCounter, mAttachCounter, mParentCandidate, mAnnounceDelay, mAnnounceChannel and mAttachTimer representing its overall state during an attach cycle, and for reattaches AttachMode and ReattachState are also used.

[mikew67]

abtink,

Thanks for the reply. That's about what I expected, including from the example you cite. Nevertheless, I expect that a visual diagram of the OT stack would be a valuable tool. If I was assigned the task of understanding the stack, my study would include drawing such a FSM from the spec.

Mike