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    • Athestia

      Public
      Clean slate application using NDN with Dilithium to enhance security in future internet technology
      0200Updated Nov 13, 2024Nov 13, 2024
    • A Kyber768-90's Hardware Accelerator.
      Python
      2300Updated Nov 12, 2024Nov 12, 2024
    • oxygen

      Public
      A RISC-V Simulator
      Python
      GNU General Public License v3.0
      3201Updated Nov 11, 2024Nov 11, 2024
    • vaquita

      Public
      Scala
      GNU General Public License v3.0
      61201Updated Nov 6, 2024Nov 6, 2024
    • Jupyter Notebook
      1000Updated Oct 27, 2024Oct 27, 2024
    • An open source Mini SoC Generator which will generate SoC based on parameters.
      Verilog
      1180Updated Oct 3, 2024Oct 3, 2024
    • jigsaw

      Public
      A platform containing useful peripherals implemented in Chisel that can be attached together to complete the puzzle (SoC).
      Scala
      7312Updated Oct 3, 2024Oct 3, 2024
    • caravan

      Public
      A caravan equipped with API for creating bus protocols in Chisel with ease.
      Scala
      Apache License 2.0
      111340Updated Oct 3, 2024Oct 3, 2024
    • 0000Updated Oct 2, 2024Oct 2, 2024
    • nucleusrv

      Public
      NucleusRV - A 32-bit 5 staged pipelined risc-v core.
      C
      GNU General Public License v3.0
      2460150Updated Oct 1, 2024Oct 1, 2024
    • RISC-V 32-bit CPU written in amaranth (python-lib)
      Verilog
      5811Updated Sep 23, 2024Sep 23, 2024
    • ArcheV

      Public
      RISC-V RV-32i RTL Benchmark for evaluating Large Language Models.
      Verilog
      3010Updated Sep 20, 2024Sep 20, 2024
    • Python
      1000Updated Sep 19, 2024Sep 19, 2024
    • a dedicated hardware accelerator accelerating Baby Kyber Encryption operations on hardware level written in CHISEL HDL
      C++
      0000Updated Sep 10, 2024Sep 10, 2024
    • C++
      0000Updated Aug 23, 2024Aug 23, 2024
    • An All in one RISC-V Suite.
      JavaScript
      4500Updated Aug 15, 2024Aug 15, 2024
    • NucleusRV - A 32-bit 5 staged pipelined risc-v core.
      C
      GNU General Public License v3.0
      24000Updated Jul 23, 2024Jul 23, 2024
    • OpenTCAM

      Public
      An open-source Ternary Content Addressable Memory (TCAM) compiler.
      Python
      Apache License 2.0
      112001Updated Jul 19, 2024Jul 19, 2024
    • zeusic-v

      Public
      RISC-V based Neuromorphic Processor for accelerating Spiking Neural Networks
      2200Updated Jul 4, 2024Jul 4, 2024
    • JavaScript
      Other
      6103Updated Mar 27, 2024Mar 27, 2024
    • xodus

      Public
      RV32-I 5 Stage Pipelined Core implemented in CHISEL HDL
      Scala
      GNU General Public License v3.0
      1200Updated Mar 23, 2024Mar 23, 2024
    • magma-si

      Public
      Matrix Accelerator Generator for GeMM Operations based on SIGMA Architecture in CHISEL HDL
      Scala
      GNU General Public License v3.0
      3942Updated Mar 21, 2024Mar 21, 2024
    • Project ideas list for Google Summer of Code.
      21100Updated Feb 1, 2024Feb 1, 2024
    • chisel

      Public
      Chisel: A Modern Hardware Design Language
      Scala
      Apache License 2.0
      597000Updated Feb 1, 2024Feb 1, 2024
    • Verilog
      Apache License 2.0
      0100Updated Jan 11, 2024Jan 11, 2024
    • Lib Analyzer is an application which is used to analyze the cells in the liberty files.
      Python
      1220Updated Dec 25, 2023Dec 25, 2023
    • cachefy

      Public
      CHISEL API for plug n play connection of Caches in CHISEL designs
      Scala
      Apache License 2.0
      1300Updated Dec 19, 2023Dec 19, 2023
    • Verilog
      Apache License 2.0
      0000Updated Dec 11, 2023Dec 11, 2023
    • tracer

      Public
      CHISEL based RVFI Tracer
      Scala
      0000Updated Nov 30, 2023Nov 30, 2023
    • NucleusRV - A 32-bit 5 staged pipelined risc-v core.
      C
      GNU General Public License v3.0
      24000Updated Nov 7, 2023Nov 7, 2023