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If the latency of your L3Xbar and the latency of L2Xbar are the same, you can use L2Xbar. If they are different, you can To create a separate L3Xbar |
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Hello! I'm trying to expand on the private_l1_private_l2 and private_l1_shared_l2 cache hierarchy classes already included in the source Python for gem5 by building a three level cache that uses a private_l1_private_l2_shared_l3 hierarchy. So far, I've done so creating an L3Cache class and a PrivateL1PrivateL2SharedL3Hierarchy class - pretty much following the same template as the pre-existing models. I'm wondering if the way I'm going about creating the bus between the L2 caches and the shared L3 cache is correct. In my code, I'm just using the same L2XBar() on line 132 that is used in both two-level cache classes that are already implemented. I already have one connecting each private l1 cache to each private l2 cache. Should I be using something else for the bus connecting the shared L3 cache (i.e., do I need to make an L3XBar()?)
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