Does Gem5 support heterogeneous multi-core modeling？

[flyeagle0]

I would like to know if Gem5 supports heterogeneous multi-core modeling. For example, I want to model two RISCV kernels, one as the main kernel and one as the slave kernel. The RISCV ISA of the two kernels may have differences, and the two kernels have interactive operations. Do Gem5 support this type of modeling, and how should I implement it specifically?

[BobbyRBruce]

The only part of that scenario I think would be difficult is having different cores having differences. I think right now all the cores would need to conform to the same ISA. You can look at src/arch/riscv/RiscvCPU and see that all our RISCV processors have the same ISA. To engineer something around this may be more trouble than it's worth.

To answer your question more broadly. You can put as many cores in your simulation as you want and the cores can have different processes set each. The difficulty is figuring out how you want these core models to communicate in your simulation, share memory etc. That's dependent on how you envision this system and, from there, taking the time to setup your simulation. There may be difficulties in this i haven't envisioned but that's my feeling on this.

I'm not aware of any out-of-the-box solution if that's what you're looking for. You may just need to sit down and build this yourself from the ground up. You can start small. Try getting a SE-mode simulation with two RISCV cores running, each running a different process.

[andysan]

Didn't Gabe's multi-ISA changes add support for this? IIRC, the long term plan was to support multi-ISA simulation. It has been a while since I looked at this though.

[BobbyRBruce]

I think I'm gradually walking my self back from my negative statement now I think it through more. I know we could have two different ISAs (e.g.,, X86 and RISCV) in the same situation if you wanted thanks to Gabe's multi-ISA work. I was more uncertain on how you could run two different flavors of RISCV in the same simulation because that's slightly diffrent.

The gap in my knowledge is knowing what is set globally in gem5 and what is set per-core in gem5 when it comes to ISAs. Though given we can already define which RISC-V extensions to use per-core, I guess there's enough configurability at the core level to make this work.

To talk more to @flyeagle0 : It'd be worth looking into how we enabled RISC-V vector extensions in the RISC-V ISA if you look in src/arch/riscv/isa.cc, you can see the ISA constructor has enableRvv (enable RISCV Vector extension) and variables for setting the vector length (vlen), etc. So, you'd have to do this for your own work. but when you setup your cores I think you could do something like:

isa1=RiscvISA(enable_special_instructions=True)
isa2=RiscvISA(enable_special_instructions=False)

core1=RiscvTimingSimpleCPU(isa=isa1)
core2=RiscvTimingSimpleCPU(isa=isa2)

[flyeagle0]

thank you！