Where and how to guarantee that the mshr has entry for the miss req when allocate a entry?

[gxflying]

Hi sir, I am learning about the gem5 cache now, when I check the flow for a missing request, I found that it may allocate a mshr entry which is make sense,
BUT the allocating is without checking whether there is free entry in the MSHR?
and in function handleTimingReqMiss , allocateMissBuffer is called without checking the result which may be NULL?
I think it is possible that the MSHR has no entries when MSHRQueue::allocate is called, and a NULL pointer is returned
especally, in the MSHRQueue::allocate there is a assert than freelist must NOT be empty, but HOW to guarantee this condition ？

gem5/src/mem/cache/base.cc

Line 398 in f29bfc0

allocateMissBuffer(pkt, forward_time);

gem5/src/mem/cache/base.hh

Line 1171 in f29bfc0

MSHR *mshr = mshrQueue.allocate(pkt->getBlockAddr(blkSize), blkSize,

MSHR * MSHRQueue::allocate(Addr blk_addr, unsigned blk_size, PacketPtr pkt,
                    Tick when_ready, Counter order, bool alloc_on_fill)
{
    assert(!freeList.empty());

[gxflying]

yeah I have get the point
every time BaseCache::allocateMissBuffer() is called， in the function will check the mshrQueue and set blocked flage if the queue is full.

        if (mshrQueue.isFull()) {
            setBlocked((BlockedCause)MSHRQueue_MSHRs);
        }

and every time the cache receive a request, the function BaseCache::CpuSidePort::recvTimingReq is called, and in the function where before BaseCache::recvTimingReq is called, tryTiming is called to check the blocked flag, if it set true, the BaseCache::recvTimingReq will not be called in which mshr entry may be allocated

gem5/src/mem/cache/base.cc

Line 2562 in f29bfc0

} else if (tryTiming(pkt)) {

    } else if (tryTiming(pkt)) {
        cache.recvTimingReq(pkt);
        return true;
    }