How to disable MMU and use the direct memory access for RISCV in gem5?

[Godblessmycode1]

I tried to set two memory ranges (Physical address)with different types of memory. I want to interact with different memory regions to simulate the load/write efficiency. However, the direct memory access (provided physical address in a specific memory range) will cause a page fault. And the malloc() or mmap() function under se mode will not meet the situation that memories will be split into different memory regions. Instead, under most situations, the physical address translated by MMU always falls in one region(I have tracked using --debug-flags MMU and MemoryAccess).

So is there any way, to use direct memory access under RISCV for gem5?

Platform: Ubuntu 22.04
Cross-compiler: riscv64-unknown-elf-gcc and riscv64-linux-gnu-gcc both
Gem5 Version:v24.0.0.1

[Godblessmycode1]

Here is my simulation Python file

from m5.objects import *

# Create the system
system = System()

# Define the clock and voltage domain
system.clk_domain = SrcClockDomain()
system.clk_domain.clock = '1GHz'
system.clk_domain.voltage_domain = VoltageDomain()
system.mem_bus = SystemXBar()
# Create the CPU
# Set up a simple CPU without an MMU
system.cpu = MinorCPU()
system.cpu.createInterruptController()
# Create memory controllers for HBM and DRAM
# Wrap HBM in a memory controller
system.hbm_ctrl = MemCtrl()
system.hbm_ctrl.dram = HBM_1000_4H_1x128()
system.hbm_ctrl.dram.range = AddrRange(start='0x10000000', size='128MB')  # HBM memory size

# Wrap DRAM in a memory controller, connected through PCIe
system.dram_ctrl = MemCtrl()
system.dram_ctrl.dram = DDR3_1600_8x8()
system.dram_ctrl.dram.range = AddrRange(start='0x20000000', size='256MB')  # DRAM memory size


# Connect CPU caches to memory bus
system.cpu.icache_port = system.mem_bus.cpu_side_ports
system.cpu.dcache_port = system.mem_bus.cpu_side_ports


# Define the hbm bus
system.hbm_bus= SystemXBar()
# Define the PCIe bus
# system.pcie_bus= SystemXBar()
system.pcie_bus = NoncoherentXBar()  # Initialize the PCIe bus
system.pcie_bus.forward_latency = 10 # Example latency values
system.pcie_bus.response_latency = 10
system.pcie_bus.frontend_latency = 100
system.pcie_bus.width = 128

# Using membus to connect PCIe bus
system.mem_bus.mem_side_ports = [system.pcie_bus.cpu_side_ports,system.hbm_bus.cpu_side_ports]

# Connect the memory controller of Dram to PCIe bus
system.dram_ctrl.port = system.pcie_bus.mem_side_ports
system.hbm_ctrl.port=system.hbm_bus.mem_side_ports
# System settings
system.mem_mode = 'timing'
system.mem_ranges = [system.hbm_ctrl.dram.range, system.dram_ctrl.dram.range]  # Specify the memory ranges for HBM and DRAM


# Set up the process workload
binary = '/path/to/binary or elf'
process = Process()
process = Process('0x10000000','0x10000000',size=("128MB"))
process = Process('0x20000000','0x20000000',size=("256MB"))
process.useArchPT = False
process.cmd = [binary]
system.cpu.workload = process
system.cpu.createThreads()

# Set up SEWorkload to use the binary
system.workload = SEWorkload.init_compatible(binary)

# Setup simulation
root = Root(full_system=False, system=system)

m5.instantiate()
m5.stats.dump()
print("Starting simulation")
exit_event = m5.simulate()
print("Exiting @ tick", m5.curTick(), "because", exit_event.getCause())

And my test .c file is as follows

#include <stdint.h>
#include <stdio.h>
#define HBM_START 0x10000000
#define DRAM_START 0x20000000

int main() {
   int* hbm_ptr=(int*)(HBM_START);
   int* dram_ptr=(int*)(DRAM_START);
   *hbm_ptr=1;
   *dram_ptr=1;
   return 0;
}

[Godblessmycode1]

And using process.map function will cause one runtime error:RuntimeError: Attempt to instantiate orphan node

[Will-Shaddix]

did you call process.map() after m5.instantiate?

[TopGun34]

hello, have you resolve this issue? I recently meet the same issue as you.The system i simulated directly use physical address in instruction, but gem5 default add mmu->translateTiming for each memory related instruction, i want to disable VA->PA translation, if you have any progress could you share with me ?

any reply is appreciated!