Creating LVSRAM with one Master port and multiple Slave ports

[YazhengTu]

I am trying to modify LVSRAM.cc and LVSRAM.hh to create master/slave communication ports for LVSARM in gem5. I have already added one master and one slave port, but now I am having trouble with how to extend the slave port into an array containing multiple slave ports.

below is the definition in .hh file:

CPUSidePort dmaCpuPort;
CPUSidePort vlsuCpuPort;
CPUSidePort tcCpuPort;
CPUSidePort vcCpuPort;
MemSidePort m0CpuPort;
CPUSidePortLink s0CpuPort;
MemSidePort s0CpuPorts[num_row];

and here is the constructor i am writing:

LVSRAM::LVSRAM(const LVSRAMParams &params) :
    ClockedObject(params),
    addrRange(params.addr_range),
    latency(params.latency),
    size(params.size),
    version(params.version),
    dmaCpuPort(name() + ".dma_port", 0, this, params.dma_acc_align),
    vlsuCpuPort(name() + ".vlsu_port", 0, this, params.vlsu_acc_align),
    tcCpuPort(name() + ".tc_port", 0, this, params.tc_acc_align),
    vcCpuPort(name() + ".vc_port", 0, this, params.vc_acc_align),
    //m0CpuPort(params.name + ".m0_port", this, params.bus_acc_align),
    m0CpuPort(name() + ".m0_port", this),
    s0CpuPorts(new MemSidePort[num_row]),
    s0CpuPort(name() + ".s0_port", 0, this, params.slave_acc_align),
    id(params.id)
{      
    Addr start = addrRange.start();
    Addr end = addrRange.end();

    warn_if(size != end - start, "LVSRAM size(%#x) is inconsistent with the addr_range[%#x,%#x].\n",
        size, start, end);

    ramCell = (uint8_t *) new uint64_t[params.size / 8]; // align with 8 bytes

    // initial ramCell for test
    for (int i = 0; i < params.size; i++) {
        ramCell[i] = i & 0xff;
    }

    for (int i = 0; i < num_row; i++) {
        std::string port_name = name() + ".s0_port_" + std::to_string(i);
        s0CpuPorts[i] = MemSidePort(port_name, this);
    }


}

I have an error saying no default constructor exists for class "gem5::LVSRAM::MemSidePort" for s0CpuPorts(new MemSidePort[num_row]), and function "gem5::LVSRAM::MemSidePort::operator=(const gem5::LVSRAM::MemSidePort &)" (declared implicitly) cannot be referenced -- it is a deleted functionC in the last for loop where I want to create ports for each element in the array.

Anyone knows how I should correctly create the array?